1 /**********************************************************
2 * Copyright 2008-2009 VMware, Inc. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 **********************************************************/
26 #include "git_sha1.h" /* For MESA_GIT_SHA1 */
27 #include "util/format/u_format.h"
28 #include "util/u_memory.h"
29 #include "util/u_inlines.h"
30 #include "util/u_screen.h"
31 #include "util/u_string.h"
32 #include "util/u_math.h"
34 #include "os/os_process.h"
36 #include "svga_winsys.h"
37 #include "svga_public.h"
38 #include "svga_context.h"
39 #include "svga_format.h"
40 #include "svga_screen.h"
41 #include "svga_tgsi.h"
42 #include "svga_resource_texture.h"
43 #include "svga_resource.h"
44 #include "svga_debug.h"
46 #include "svga3d_shaderdefs.h"
47 #include "VGPU10ShaderTokens.h"
49 /* NOTE: this constant may get moved into a svga3d*.h header file */
50 #define SVGA3D_DX_MAX_RESOURCE_SIZE (128 * 1024 * 1024)
53 #define MESA_GIT_SHA1 "(unknown git revision)"
59 static const struct debug_named_value svga_debug_flags
[] = {
60 { "dma", DEBUG_DMA
, NULL
},
61 { "tgsi", DEBUG_TGSI
, NULL
},
62 { "pipe", DEBUG_PIPE
, NULL
},
63 { "state", DEBUG_STATE
, NULL
},
64 { "screen", DEBUG_SCREEN
, NULL
},
65 { "tex", DEBUG_TEX
, NULL
},
66 { "swtnl", DEBUG_SWTNL
, NULL
},
67 { "const", DEBUG_CONSTS
, NULL
},
68 { "viewport", DEBUG_VIEWPORT
, NULL
},
69 { "views", DEBUG_VIEWS
, NULL
},
70 { "perf", DEBUG_PERF
, NULL
},
71 { "flush", DEBUG_FLUSH
, NULL
},
72 { "sync", DEBUG_SYNC
, NULL
},
73 { "cache", DEBUG_CACHE
, NULL
},
74 { "streamout", DEBUG_STREAMOUT
, NULL
},
75 { "query", DEBUG_QUERY
, NULL
},
76 { "samplers", DEBUG_SAMPLERS
, NULL
},
82 svga_get_vendor( struct pipe_screen
*pscreen
)
84 return "VMware, Inc.";
89 svga_get_name( struct pipe_screen
*pscreen
)
91 const char *build
= "", *llvm
= "", *mutex
= "";
92 static char name
[100];
94 /* Only return internal details in the DEBUG version:
96 build
= "build: DEBUG;";
97 mutex
= "mutex: " PIPE_ATOMIC
";";
99 build
= "build: RELEASE;";
101 #ifdef LLVM_AVAILABLE
105 snprintf(name
, sizeof(name
), "SVGA3D; %s %s %s", build
, mutex
, llvm
);
110 /** Helper for querying float-valued device cap */
112 get_float_cap(struct svga_winsys_screen
*sws
, SVGA3dDevCapIndex cap
,
115 SVGA3dDevCapResult result
;
116 if (sws
->get_cap(sws
, cap
, &result
))
123 /** Helper for querying uint-valued device cap */
125 get_uint_cap(struct svga_winsys_screen
*sws
, SVGA3dDevCapIndex cap
,
128 SVGA3dDevCapResult result
;
129 if (sws
->get_cap(sws
, cap
, &result
))
136 /** Helper for querying boolean-valued device cap */
138 get_bool_cap(struct svga_winsys_screen
*sws
, SVGA3dDevCapIndex cap
,
141 SVGA3dDevCapResult result
;
142 if (sws
->get_cap(sws
, cap
, &result
))
150 svga_get_paramf(struct pipe_screen
*screen
, enum pipe_capf param
)
152 struct svga_screen
*svgascreen
= svga_screen(screen
);
153 struct svga_winsys_screen
*sws
= svgascreen
->sws
;
156 case PIPE_CAPF_MAX_LINE_WIDTH
:
157 return svgascreen
->maxLineWidth
;
158 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
159 return svgascreen
->maxLineWidthAA
;
161 case PIPE_CAPF_MAX_POINT_WIDTH
:
163 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
164 return svgascreen
->maxPointSize
;
166 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
167 return (float) get_uint_cap(sws
, SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY
, 4);
169 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
172 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE
:
174 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE
:
176 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY
:
181 debug_printf("Unexpected PIPE_CAPF_ query %u\n", param
);
187 svga_get_param(struct pipe_screen
*screen
, enum pipe_cap param
)
189 struct svga_screen
*svgascreen
= svga_screen(screen
);
190 struct svga_winsys_screen
*sws
= svgascreen
->sws
;
191 SVGA3dDevCapResult result
;
194 case PIPE_CAP_NPOT_TEXTURES
:
195 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
196 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS
:
198 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
200 * "In virtually every OpenGL implementation and hardware,
201 * GL_MAX_DUAL_SOURCE_DRAW_BUFFERS is 1"
202 * http://www.opengl.org/wiki/Blending
204 return sws
->have_vgpu10
? 1 : 0;
205 case PIPE_CAP_ANISOTROPIC_FILTER
:
207 case PIPE_CAP_POINT_SPRITE
:
209 case PIPE_CAP_MAX_RENDER_TARGETS
:
210 return svgascreen
->max_color_buffers
;
211 case PIPE_CAP_OCCLUSION_QUERY
:
213 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
214 return sws
->have_vgpu10
;
215 case PIPE_CAP_TEXTURE_SWIZZLE
:
217 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
220 case PIPE_CAP_MAX_TEXTURE_2D_SIZE
:
222 unsigned size
= 1 << (SVGA_MAX_TEXTURE_LEVELS
- 1);
223 if (sws
->get_cap(sws
, SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH
, &result
))
224 size
= MIN2(result
.u
, size
);
227 if (sws
->get_cap(sws
, SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT
, &result
))
228 size
= MIN2(result
.u
, size
);
234 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
235 if (!sws
->get_cap(sws
, SVGA3D_DEVCAP_MAX_VOLUME_EXTENT
, &result
))
236 return 8; /* max 128x128x128 */
237 return MIN2(util_logbase2(result
.u
) + 1, SVGA_MAX_TEXTURE_LEVELS
);
239 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
241 * No mechanism to query the host, and at least limited to 2048x2048 on
244 return MIN2(util_last_bit(screen
->get_param(screen
, PIPE_CAP_MAX_TEXTURE_2D_SIZE
)),
247 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
248 return sws
->have_sm5
? SVGA3D_SM5_MAX_SURFACE_ARRAYSIZE
:
249 (sws
->have_vgpu10
? SVGA3D_SM4_MAX_SURFACE_ARRAYSIZE
: 0);
251 case PIPE_CAP_BLEND_EQUATION_SEPARATE
: /* req. for GL 1.5 */
254 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
256 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
257 return sws
->have_vgpu10
;
258 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
259 return !sws
->have_vgpu10
;
261 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
262 return 1; /* The color outputs of vertex shaders are not clamped */
263 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
264 return sws
->have_vgpu10
;
266 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
267 return 1; /* expected for GL_ARB_framebuffer_object */
269 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
272 } else if (sws
->have_vgpu10
) {
278 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY
:
279 return sws
->have_sm5
? 410 : (sws
->have_vgpu10
? 330 : 120);
281 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
284 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD
:
285 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES
:
286 case PIPE_CAP_VERTEX_SHADER_SATURATE
:
289 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
290 case PIPE_CAP_INDEP_BLEND_ENABLE
:
291 case PIPE_CAP_CONDITIONAL_RENDER
:
292 case PIPE_CAP_QUERY_TIMESTAMP
:
293 case PIPE_CAP_TGSI_INSTANCEID
:
294 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
295 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
296 case PIPE_CAP_FAKE_SW_MSAA
:
297 return sws
->have_vgpu10
;
299 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
300 return sws
->have_vgpu10
? SVGA3D_DX_MAX_SOTARGETS
: 0;
301 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
302 return sws
->have_vgpu10
? 4 : 0;
303 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
304 return sws
->have_sm5
? SVGA3D_MAX_STREAMOUT_DECLS
:
305 (sws
->have_vgpu10
? SVGA3D_MAX_DX10_STREAMOUT_DECLS
: 0);
306 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
307 return sws
->have_sm5
;
308 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS
:
309 return sws
->have_sm5
;
310 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
311 return svgascreen
->ms_samples
? 1 : 0;
313 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
314 /* convert bytes to texels for the case of the largest texel
317 return SVGA3D_DX_MAX_RESOURCE_SIZE
/ (4 * sizeof(float));
319 case PIPE_CAP_MIN_TEXEL_OFFSET
:
320 return sws
->have_vgpu10
? VGPU10_MIN_TEXEL_FETCH_OFFSET
: 0;
321 case PIPE_CAP_MAX_TEXEL_OFFSET
:
322 return sws
->have_vgpu10
? VGPU10_MAX_TEXEL_FETCH_OFFSET
: 0;
324 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
325 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
328 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
329 return sws
->have_vgpu10
? 256 : 0;
330 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
331 return sws
->have_vgpu10
? 1024 : 0;
333 case PIPE_CAP_PRIMITIVE_RESTART
:
334 case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX
:
335 return 1; /* may be a sw fallback, depending on restart index */
337 case PIPE_CAP_GENERATE_MIPMAP
:
338 return sws
->have_generate_mipmap_cmd
;
340 case PIPE_CAP_NATIVE_FENCE_FD
:
341 return sws
->have_fence_fd
;
343 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
346 case PIPE_CAP_CUBE_MAP_ARRAY
:
347 case PIPE_CAP_INDEP_BLEND_FUNC
:
348 case PIPE_CAP_SAMPLE_SHADING
:
349 case PIPE_CAP_FORCE_PERSAMPLE_INTERP
:
350 case PIPE_CAP_TEXTURE_QUERY_LOD
:
351 return sws
->have_sm4_1
;
353 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
354 /* SM4_1 supports only single-channel textures where as SM5 supports
355 * all four channel textures */
356 return sws
->have_sm5
? 4 :
357 (sws
->have_sm4_1
? 1 : 0);
358 case PIPE_CAP_DRAW_INDIRECT
:
359 return sws
->have_sm5
;
360 case PIPE_CAP_MAX_VERTEX_STREAMS
:
361 return sws
->have_sm5
? 4 : 0;
362 case PIPE_CAP_COMPUTE
:
364 case PIPE_CAP_MAX_VARYINGS
:
365 return sws
->have_vgpu10
? VGPU10_MAX_FS_INPUTS
: 10;
366 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
367 return sws
->have_coherent
;
369 case PIPE_CAP_PCI_GROUP
:
370 case PIPE_CAP_PCI_BUS
:
371 case PIPE_CAP_PCI_DEVICE
:
372 case PIPE_CAP_PCI_FUNCTION
:
374 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
376 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
377 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
378 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
379 return 1; /* need 4-byte alignment for all offsets and strides */
380 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
382 case PIPE_CAP_MAX_VIEWPORTS
:
383 assert((!sws
->have_vgpu10
&& svgascreen
->max_viewports
== 1) ||
385 svgascreen
->max_viewports
== SVGA3D_DX_MAX_VIEWPORTS
));
386 return svgascreen
->max_viewports
;
387 case PIPE_CAP_ENDIANNESS
:
388 return PIPE_ENDIAN_LITTLE
;
390 case PIPE_CAP_VENDOR_ID
:
391 return 0x15ad; /* VMware Inc. */
392 case PIPE_CAP_DEVICE_ID
:
393 return 0x0405; /* assume SVGA II */
394 case PIPE_CAP_ACCELERATED
:
396 case PIPE_CAP_VIDEO_MEMORY
:
397 /* XXX: Query the host ? */
399 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
:
400 return sws
->have_vgpu10
;
401 case PIPE_CAP_CLEAR_TEXTURE
:
402 return sws
->have_vgpu10
;
403 case PIPE_CAP_DOUBLES
:
404 return sws
->have_sm5
;
406 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY
:
407 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION
:
409 case PIPE_CAP_TGSI_DIV
:
411 case PIPE_CAP_MAX_GS_INVOCATIONS
:
413 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE
:
415 /* Verify this once protocol is finalized. Setting it to minimum value. */
416 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
:
417 return sws
->have_sm5
? 30 : 0;
419 return u_pipe_screen_get_param_defaults(screen
, param
);
425 vgpu9_get_shader_param(struct pipe_screen
*screen
,
426 enum pipe_shader_type shader
,
427 enum pipe_shader_cap param
)
429 struct svga_screen
*svgascreen
= svga_screen(screen
);
430 struct svga_winsys_screen
*sws
= svgascreen
->sws
;
433 assert(!sws
->have_vgpu10
);
437 case PIPE_SHADER_FRAGMENT
:
440 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
441 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
442 return get_uint_cap(sws
,
443 SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS
,
445 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
446 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
448 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
449 return SVGA3D_MAX_NESTING_LEVEL
;
450 case PIPE_SHADER_CAP_MAX_INPUTS
:
452 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
453 return svgascreen
->max_color_buffers
;
454 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
455 return 224 * sizeof(float[4]);
456 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
458 case PIPE_SHADER_CAP_MAX_TEMPS
:
459 val
= get_uint_cap(sws
, SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS
, 32);
460 return MIN2(val
, SVGA3D_TEMPREG_MAX
);
461 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
463 * Although PS 3.0 has some addressing abilities it can only represent
464 * loops that can be statically determined and unrolled. Given we can
465 * only handle a subset of the cases that the gallium frontend already
466 * does it is better to defer loop unrolling to the gallium frontend.
469 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
471 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
473 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
474 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
475 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
477 case PIPE_SHADER_CAP_SUBROUTINES
:
479 case PIPE_SHADER_CAP_INT64_ATOMICS
:
480 case PIPE_SHADER_CAP_INTEGERS
:
482 case PIPE_SHADER_CAP_FP16
:
483 case PIPE_SHADER_CAP_FP16_DERIVATIVES
:
484 case PIPE_SHADER_CAP_INT16
:
485 case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS
:
487 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
488 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
490 case PIPE_SHADER_CAP_PREFERRED_IR
:
491 return PIPE_SHADER_IR_TGSI
;
492 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
494 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
495 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
496 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
:
497 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
498 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
499 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
500 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
501 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
502 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
503 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS
:
504 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS
:
506 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
509 /* If we get here, we failed to handle a cap above */
510 debug_printf("Unexpected fragment shader query %u\n", param
);
512 case PIPE_SHADER_VERTEX
:
515 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
516 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
517 return get_uint_cap(sws
, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS
,
519 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
520 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
521 /* XXX: until we have vertex texture support */
523 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
524 return SVGA3D_MAX_NESTING_LEVEL
;
525 case PIPE_SHADER_CAP_MAX_INPUTS
:
527 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
529 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
530 return 256 * sizeof(float[4]);
531 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
533 case PIPE_SHADER_CAP_MAX_TEMPS
:
534 val
= get_uint_cap(sws
, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS
, 32);
535 return MIN2(val
, SVGA3D_TEMPREG_MAX
);
536 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
538 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
540 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
541 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
543 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
545 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
547 case PIPE_SHADER_CAP_SUBROUTINES
:
549 case PIPE_SHADER_CAP_INT64_ATOMICS
:
550 case PIPE_SHADER_CAP_INTEGERS
:
552 case PIPE_SHADER_CAP_FP16
:
553 case PIPE_SHADER_CAP_FP16_DERIVATIVES
:
554 case PIPE_SHADER_CAP_INT16
:
555 case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS
:
557 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
558 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
560 case PIPE_SHADER_CAP_PREFERRED_IR
:
561 return PIPE_SHADER_IR_TGSI
;
562 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
564 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
565 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
566 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
:
567 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
568 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
569 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
570 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
571 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
572 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
573 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS
:
574 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS
:
576 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
579 /* If we get here, we failed to handle a cap above */
580 debug_printf("Unexpected vertex shader query %u\n", param
);
582 case PIPE_SHADER_GEOMETRY
:
583 case PIPE_SHADER_COMPUTE
:
584 case PIPE_SHADER_TESS_CTRL
:
585 case PIPE_SHADER_TESS_EVAL
:
586 /* no support for geometry, tess or compute shaders at this time */
589 debug_printf("Unexpected shader type (%u) query\n", shader
);
597 vgpu10_get_shader_param(struct pipe_screen
*screen
,
598 enum pipe_shader_type shader
,
599 enum pipe_shader_cap param
)
601 struct svga_screen
*svgascreen
= svga_screen(screen
);
602 struct svga_winsys_screen
*sws
= svgascreen
->sws
;
604 assert(sws
->have_vgpu10
);
605 (void) sws
; /* silence unused var warnings in non-debug builds */
607 if ((!sws
->have_sm5
) &&
608 (shader
== PIPE_SHADER_TESS_CTRL
|| shader
== PIPE_SHADER_TESS_EVAL
))
611 if (shader
== PIPE_SHADER_COMPUTE
)
614 /* NOTE: we do not query the device for any caps/limits at this time */
616 /* Generally the same limits for vertex, geometry and fragment shaders */
618 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
619 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
620 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
621 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
623 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
625 case PIPE_SHADER_CAP_MAX_INPUTS
:
626 if (shader
== PIPE_SHADER_FRAGMENT
)
627 return VGPU10_MAX_FS_INPUTS
;
628 else if (shader
== PIPE_SHADER_GEOMETRY
)
629 return VGPU10_MAX_GS_INPUTS
;
630 else if (shader
== PIPE_SHADER_TESS_CTRL
)
631 return VGPU11_MAX_HS_INPUT_CONTROL_POINTS
;
632 else if (shader
== PIPE_SHADER_TESS_EVAL
)
633 return VGPU11_MAX_DS_INPUT_CONTROL_POINTS
;
635 return VGPU10_MAX_VS_INPUTS
;
636 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
637 if (shader
== PIPE_SHADER_FRAGMENT
)
638 return VGPU10_MAX_FS_OUTPUTS
;
639 else if (shader
== PIPE_SHADER_GEOMETRY
)
640 return VGPU10_MAX_GS_OUTPUTS
;
641 else if (shader
== PIPE_SHADER_TESS_CTRL
)
642 return VGPU11_MAX_HS_OUTPUTS
;
643 else if (shader
== PIPE_SHADER_TESS_EVAL
)
644 return VGPU11_MAX_DS_OUTPUTS
;
646 return VGPU10_MAX_VS_OUTPUTS
;
647 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
648 return VGPU10_MAX_CONSTANT_BUFFER_ELEMENT_COUNT
* sizeof(float[4]);
649 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
650 return svgascreen
->max_const_buffers
;
651 case PIPE_SHADER_CAP_MAX_TEMPS
:
652 return VGPU10_MAX_TEMPS
;
653 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
654 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
655 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
656 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
657 return TRUE
; /* XXX verify */
658 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
659 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
660 case PIPE_SHADER_CAP_SUBROUTINES
:
661 case PIPE_SHADER_CAP_INTEGERS
:
663 case PIPE_SHADER_CAP_FP16
:
664 case PIPE_SHADER_CAP_FP16_DERIVATIVES
:
665 case PIPE_SHADER_CAP_INT16
:
666 case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS
:
668 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
669 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
670 return SVGA3D_DX_MAX_SAMPLERS
;
671 case PIPE_SHADER_CAP_PREFERRED_IR
:
672 return PIPE_SHADER_IR_TGSI
;
673 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
675 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
676 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
677 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
:
678 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
679 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
680 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
681 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
682 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
683 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
684 case PIPE_SHADER_CAP_INT64_ATOMICS
:
685 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS
:
686 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS
:
688 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
691 debug_printf("Unexpected vgpu10 shader query %u\n", param
);
699 svga_get_shader_param(struct pipe_screen
*screen
, enum pipe_shader_type shader
,
700 enum pipe_shader_cap param
)
702 struct svga_screen
*svgascreen
= svga_screen(screen
);
703 struct svga_winsys_screen
*sws
= svgascreen
->sws
;
704 if (sws
->have_vgpu10
) {
705 return vgpu10_get_shader_param(screen
, shader
, param
);
708 return vgpu9_get_shader_param(screen
, shader
, param
);
714 svga_fence_reference(struct pipe_screen
*screen
,
715 struct pipe_fence_handle
**ptr
,
716 struct pipe_fence_handle
*fence
)
718 struct svga_winsys_screen
*sws
= svga_screen(screen
)->sws
;
719 sws
->fence_reference(sws
, ptr
, fence
);
724 svga_fence_finish(struct pipe_screen
*screen
,
725 struct pipe_context
*ctx
,
726 struct pipe_fence_handle
*fence
,
729 struct svga_winsys_screen
*sws
= svga_screen(screen
)->sws
;
732 SVGA_STATS_TIME_PUSH(sws
, SVGA_STATS_TIME_FENCEFINISH
);
735 retVal
= sws
->fence_signalled(sws
, fence
, 0) == 0;
738 SVGA_DBG(DEBUG_DMA
|DEBUG_PERF
, "%s fence_ptr %p\n",
739 __FUNCTION__
, fence
);
741 retVal
= sws
->fence_finish(sws
, fence
, timeout
, 0) == 0;
744 SVGA_STATS_TIME_POP(sws
);
751 svga_fence_get_fd(struct pipe_screen
*screen
,
752 struct pipe_fence_handle
*fence
)
754 struct svga_winsys_screen
*sws
= svga_screen(screen
)->sws
;
756 return sws
->fence_get_fd(sws
, fence
, TRUE
);
761 svga_get_driver_query_info(struct pipe_screen
*screen
,
763 struct pipe_driver_query_info
*info
)
765 #define QUERY(NAME, ENUM, UNITS) \
766 {NAME, ENUM, {0}, UNITS, PIPE_DRIVER_QUERY_RESULT_TYPE_AVERAGE, 0, 0x0}
768 static const struct pipe_driver_query_info queries
[] = {
769 /* per-frame counters */
770 QUERY("num-draw-calls", SVGA_QUERY_NUM_DRAW_CALLS
,
771 PIPE_DRIVER_QUERY_TYPE_UINT64
),
772 QUERY("num-fallbacks", SVGA_QUERY_NUM_FALLBACKS
,
773 PIPE_DRIVER_QUERY_TYPE_UINT64
),
774 QUERY("num-flushes", SVGA_QUERY_NUM_FLUSHES
,
775 PIPE_DRIVER_QUERY_TYPE_UINT64
),
776 QUERY("num-validations", SVGA_QUERY_NUM_VALIDATIONS
,
777 PIPE_DRIVER_QUERY_TYPE_UINT64
),
778 QUERY("map-buffer-time", SVGA_QUERY_MAP_BUFFER_TIME
,
779 PIPE_DRIVER_QUERY_TYPE_MICROSECONDS
),
780 QUERY("num-buffers-mapped", SVGA_QUERY_NUM_BUFFERS_MAPPED
,
781 PIPE_DRIVER_QUERY_TYPE_UINT64
),
782 QUERY("num-textures-mapped", SVGA_QUERY_NUM_TEXTURES_MAPPED
,
783 PIPE_DRIVER_QUERY_TYPE_UINT64
),
784 QUERY("num-bytes-uploaded", SVGA_QUERY_NUM_BYTES_UPLOADED
,
785 PIPE_DRIVER_QUERY_TYPE_BYTES
),
786 QUERY("num-command-buffers", SVGA_QUERY_NUM_COMMAND_BUFFERS
,
787 PIPE_DRIVER_QUERY_TYPE_UINT64
),
788 QUERY("command-buffer-size", SVGA_QUERY_COMMAND_BUFFER_SIZE
,
789 PIPE_DRIVER_QUERY_TYPE_BYTES
),
790 QUERY("flush-time", SVGA_QUERY_FLUSH_TIME
,
791 PIPE_DRIVER_QUERY_TYPE_MICROSECONDS
),
792 QUERY("surface-write-flushes", SVGA_QUERY_SURFACE_WRITE_FLUSHES
,
793 PIPE_DRIVER_QUERY_TYPE_UINT64
),
794 QUERY("num-readbacks", SVGA_QUERY_NUM_READBACKS
,
795 PIPE_DRIVER_QUERY_TYPE_UINT64
),
796 QUERY("num-resource-updates", SVGA_QUERY_NUM_RESOURCE_UPDATES
,
797 PIPE_DRIVER_QUERY_TYPE_UINT64
),
798 QUERY("num-buffer-uploads", SVGA_QUERY_NUM_BUFFER_UPLOADS
,
799 PIPE_DRIVER_QUERY_TYPE_UINT64
),
800 QUERY("num-const-buf-updates", SVGA_QUERY_NUM_CONST_BUF_UPDATES
,
801 PIPE_DRIVER_QUERY_TYPE_UINT64
),
802 QUERY("num-const-updates", SVGA_QUERY_NUM_CONST_UPDATES
,
803 PIPE_DRIVER_QUERY_TYPE_UINT64
),
804 QUERY("num-shader-relocations", SVGA_QUERY_NUM_SHADER_RELOCATIONS
,
805 PIPE_DRIVER_QUERY_TYPE_UINT64
),
806 QUERY("num-surface-relocations", SVGA_QUERY_NUM_SURFACE_RELOCATIONS
,
807 PIPE_DRIVER_QUERY_TYPE_UINT64
),
809 /* running total counters */
810 QUERY("memory-used", SVGA_QUERY_MEMORY_USED
,
811 PIPE_DRIVER_QUERY_TYPE_BYTES
),
812 QUERY("num-shaders", SVGA_QUERY_NUM_SHADERS
,
813 PIPE_DRIVER_QUERY_TYPE_UINT64
),
814 QUERY("num-resources", SVGA_QUERY_NUM_RESOURCES
,
815 PIPE_DRIVER_QUERY_TYPE_UINT64
),
816 QUERY("num-state-objects", SVGA_QUERY_NUM_STATE_OBJECTS
,
817 PIPE_DRIVER_QUERY_TYPE_UINT64
),
818 QUERY("num-surface-views", SVGA_QUERY_NUM_SURFACE_VIEWS
,
819 PIPE_DRIVER_QUERY_TYPE_UINT64
),
820 QUERY("num-generate-mipmap", SVGA_QUERY_NUM_GENERATE_MIPMAP
,
821 PIPE_DRIVER_QUERY_TYPE_UINT64
),
822 QUERY("num-failed-allocations", SVGA_QUERY_NUM_FAILED_ALLOCATIONS
,
823 PIPE_DRIVER_QUERY_TYPE_UINT64
),
824 QUERY("num-commands-per-draw", SVGA_QUERY_NUM_COMMANDS_PER_DRAW
,
825 PIPE_DRIVER_QUERY_TYPE_FLOAT
),
826 QUERY("shader-mem-used", SVGA_QUERY_SHADER_MEM_USED
,
827 PIPE_DRIVER_QUERY_TYPE_UINT64
),
832 return ARRAY_SIZE(queries
);
834 if (index
>= ARRAY_SIZE(queries
))
837 *info
= queries
[index
];
843 init_logging(struct pipe_screen
*screen
)
845 struct svga_screen
*svgascreen
= svga_screen(screen
);
846 static const char *log_prefix
= "Mesa: ";
849 /* Log Version to Host */
850 snprintf(host_log
, sizeof(host_log
) - strlen(log_prefix
),
851 "%s%s\n", log_prefix
, svga_get_name(screen
));
852 svgascreen
->sws
->host_log(svgascreen
->sws
, host_log
);
854 snprintf(host_log
, sizeof(host_log
) - strlen(log_prefix
),
855 "%s" PACKAGE_VERSION MESA_GIT_SHA1
, log_prefix
);
856 svgascreen
->sws
->host_log(svgascreen
->sws
, host_log
);
858 /* If the SVGA_EXTRA_LOGGING env var is set, log the process's command
859 * line (program name and arguments).
861 if (debug_get_bool_option("SVGA_EXTRA_LOGGING", FALSE
)) {
863 if (os_get_command_line(cmdline
, sizeof(cmdline
))) {
864 snprintf(host_log
, sizeof(host_log
) - strlen(log_prefix
),
865 "%s%s\n", log_prefix
, cmdline
);
866 svgascreen
->sws
->host_log(svgascreen
->sws
, host_log
);
873 * no-op logging function to use when SVGA_NO_LOGGING is set.
876 nop_host_log(struct svga_winsys_screen
*sws
, const char *message
)
883 svga_destroy_screen( struct pipe_screen
*screen
)
885 struct svga_screen
*svgascreen
= svga_screen(screen
);
887 svga_screen_cache_cleanup(svgascreen
);
889 mtx_destroy(&svgascreen
->swc_mutex
);
890 mtx_destroy(&svgascreen
->tex_mutex
);
892 svgascreen
->sws
->destroy(svgascreen
->sws
);
899 * Create a new svga_screen object
902 svga_screen_create(struct svga_winsys_screen
*sws
)
904 struct svga_screen
*svgascreen
;
905 struct pipe_screen
*screen
;
908 SVGA_DEBUG
= debug_get_flags_option("SVGA_DEBUG", svga_debug_flags
, 0 );
911 svgascreen
= CALLOC_STRUCT(svga_screen
);
915 svgascreen
->debug
.force_level_surface_view
=
916 debug_get_bool_option("SVGA_FORCE_LEVEL_SURFACE_VIEW", FALSE
);
917 svgascreen
->debug
.force_surface_view
=
918 debug_get_bool_option("SVGA_FORCE_SURFACE_VIEW", FALSE
);
919 svgascreen
->debug
.force_sampler_view
=
920 debug_get_bool_option("SVGA_FORCE_SAMPLER_VIEW", FALSE
);
921 svgascreen
->debug
.no_surface_view
=
922 debug_get_bool_option("SVGA_NO_SURFACE_VIEW", FALSE
);
923 svgascreen
->debug
.no_sampler_view
=
924 debug_get_bool_option("SVGA_NO_SAMPLER_VIEW", FALSE
);
925 svgascreen
->debug
.no_cache_index_buffers
=
926 debug_get_bool_option("SVGA_NO_CACHE_INDEX_BUFFERS", FALSE
);
928 screen
= &svgascreen
->screen
;
930 screen
->destroy
= svga_destroy_screen
;
931 screen
->get_name
= svga_get_name
;
932 screen
->get_vendor
= svga_get_vendor
;
933 screen
->get_device_vendor
= svga_get_vendor
; // TODO actual device vendor
934 screen
->get_param
= svga_get_param
;
935 screen
->get_shader_param
= svga_get_shader_param
;
936 screen
->get_paramf
= svga_get_paramf
;
937 screen
->get_timestamp
= NULL
;
938 screen
->is_format_supported
= svga_is_format_supported
;
939 screen
->context_create
= svga_context_create
;
940 screen
->fence_reference
= svga_fence_reference
;
941 screen
->fence_finish
= svga_fence_finish
;
942 screen
->fence_get_fd
= svga_fence_get_fd
;
944 screen
->get_driver_query_info
= svga_get_driver_query_info
;
945 svgascreen
->sws
= sws
;
947 svga_init_screen_resource_functions(svgascreen
);
949 if (sws
->get_hw_version
) {
950 svgascreen
->hw_version
= sws
->get_hw_version(sws
);
952 svgascreen
->hw_version
= SVGA3D_HWVERSION_WS65_B1
;
955 if (svgascreen
->hw_version
< SVGA3D_HWVERSION_WS8_B1
) {
956 /* too old for 3D acceleration */
957 debug_printf("Hardware version 0x%x is too old for accerated 3D\n",
958 svgascreen
->hw_version
);
962 debug_printf("%s enabled\n",
963 sws
->have_sm5
? "SM5" :
964 sws
->have_sm4_1
? "SM4_1" :
965 sws
->have_vgpu10
? "VGPU10" : "VGPU9");
967 debug_printf("Mesa: %s %s (%s)\n", svga_get_name(screen
),
968 PACKAGE_VERSION
, MESA_GIT_SHA1
);
971 * The D16, D24X8, and D24S8 formats always do an implicit shadow compare
972 * when sampled from, where as the DF16, DF24, and D24S8_INT do not. So
973 * we prefer the later when available.
975 * This mimics hardware vendors extensions for D3D depth sampling. See also
976 * http://aras-p.info/texts/D3D9GPUHacks.html
980 boolean has_df16
, has_df24
, has_d24s8_int
;
981 SVGA3dSurfaceFormatCaps caps
;
982 SVGA3dSurfaceFormatCaps mask
;
987 svgascreen
->depth
.z16
= SVGA3D_Z_D16
;
988 svgascreen
->depth
.x8z24
= SVGA3D_Z_D24X8
;
989 svgascreen
->depth
.s8z24
= SVGA3D_Z_D24S8
;
991 svga_get_format_cap(svgascreen
, SVGA3D_Z_DF16
, &caps
);
992 has_df16
= (caps
.value
& mask
.value
) == mask
.value
;
994 svga_get_format_cap(svgascreen
, SVGA3D_Z_DF24
, &caps
);
995 has_df24
= (caps
.value
& mask
.value
) == mask
.value
;
997 svga_get_format_cap(svgascreen
, SVGA3D_Z_D24S8_INT
, &caps
);
998 has_d24s8_int
= (caps
.value
& mask
.value
) == mask
.value
;
1000 /* XXX: We might want some other logic here.
1001 * Like if we only have d24s8_int we should
1002 * emulate the other formats with that.
1005 svgascreen
->depth
.z16
= SVGA3D_Z_DF16
;
1008 svgascreen
->depth
.x8z24
= SVGA3D_Z_DF24
;
1010 if (has_d24s8_int
) {
1011 svgascreen
->depth
.s8z24
= SVGA3D_Z_D24S8_INT
;
1015 /* Query device caps
1017 if (sws
->have_vgpu10
) {
1018 svgascreen
->haveProvokingVertex
1019 = get_bool_cap(sws
, SVGA3D_DEVCAP_DX_PROVOKING_VERTEX
, FALSE
);
1020 svgascreen
->haveLineSmooth
= TRUE
;
1021 svgascreen
->maxPointSize
= 80.0F
;
1022 svgascreen
->max_color_buffers
= SVGA3D_DX_MAX_RENDER_TARGETS
;
1024 /* Multisample samples per pixel */
1025 if (sws
->have_sm4_1
&& debug_get_bool_option("SVGA_MSAA", TRUE
)) {
1026 if (get_bool_cap(sws
, SVGA3D_DEVCAP_MULTISAMPLE_2X
, FALSE
))
1027 svgascreen
->ms_samples
|= 1 << 1;
1028 if (get_bool_cap(sws
, SVGA3D_DEVCAP_MULTISAMPLE_4X
, FALSE
))
1029 svgascreen
->ms_samples
|= 1 << 3;
1032 if (sws
->have_sm5
&& debug_get_bool_option("SVGA_MSAA", TRUE
)) {
1033 if (get_bool_cap(sws
, SVGA3D_DEVCAP_MULTISAMPLE_8X
, FALSE
))
1034 svgascreen
->ms_samples
|= 1 << 7;
1037 /* Maximum number of constant buffers */
1038 svgascreen
->max_const_buffers
=
1039 get_uint_cap(sws
, SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS
, 1);
1040 svgascreen
->max_const_buffers
= MIN2(svgascreen
->max_const_buffers
,
1041 SVGA_MAX_CONST_BUFS
);
1043 svgascreen
->haveBlendLogicops
=
1044 get_bool_cap(sws
, SVGA3D_DEVCAP_LOGIC_BLENDOPS
, FALSE
);
1046 screen
->is_format_supported
= svga_is_dx_format_supported
;
1048 svgascreen
->max_viewports
= SVGA3D_DX_MAX_VIEWPORTS
;
1052 unsigned vs_ver
= get_uint_cap(sws
, SVGA3D_DEVCAP_VERTEX_SHADER_VERSION
,
1053 SVGA3DVSVERSION_NONE
);
1054 unsigned fs_ver
= get_uint_cap(sws
, SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION
,
1055 SVGA3DPSVERSION_NONE
);
1057 /* we require Shader model 3.0 or later */
1058 if (fs_ver
< SVGA3DPSVERSION_30
|| vs_ver
< SVGA3DVSVERSION_30
) {
1062 svgascreen
->haveProvokingVertex
= FALSE
;
1064 svgascreen
->haveLineSmooth
=
1065 get_bool_cap(sws
, SVGA3D_DEVCAP_LINE_AA
, FALSE
);
1067 svgascreen
->maxPointSize
=
1068 get_float_cap(sws
, SVGA3D_DEVCAP_MAX_POINT_SIZE
, 1.0f
);
1069 /* Keep this to a reasonable size to avoid failures in conform/pntaa.c */
1070 svgascreen
->maxPointSize
= MIN2(svgascreen
->maxPointSize
, 80.0f
);
1072 /* The SVGA3D device always supports 4 targets at this time, regardless
1073 * of what querying SVGA3D_DEVCAP_MAX_RENDER_TARGETS might return.
1075 svgascreen
->max_color_buffers
= 4;
1077 /* Only support one constant buffer
1079 svgascreen
->max_const_buffers
= 1;
1081 /* No multisampling */
1082 svgascreen
->ms_samples
= 0;
1084 /* Only one viewport */
1085 svgascreen
->max_viewports
= 1;
1088 /* common VGPU9 / VGPU10 caps */
1089 svgascreen
->haveLineStipple
=
1090 get_bool_cap(sws
, SVGA3D_DEVCAP_LINE_STIPPLE
, FALSE
);
1092 svgascreen
->maxLineWidth
=
1093 MAX2(1.0, get_float_cap(sws
, SVGA3D_DEVCAP_MAX_LINE_WIDTH
, 1.0f
));
1095 svgascreen
->maxLineWidthAA
=
1096 MAX2(1.0, get_float_cap(sws
, SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH
, 1.0f
));
1099 debug_printf("svga: haveProvokingVertex %u\n",
1100 svgascreen
->haveProvokingVertex
);
1101 debug_printf("svga: haveLineStip %u "
1102 "haveLineSmooth %u maxLineWidth %.2f maxLineWidthAA %.2f\n",
1103 svgascreen
->haveLineStipple
, svgascreen
->haveLineSmooth
,
1104 svgascreen
->maxLineWidth
, svgascreen
->maxLineWidthAA
);
1105 debug_printf("svga: maxPointSize %g\n", svgascreen
->maxPointSize
);
1106 debug_printf("svga: msaa samples mask: 0x%x\n", svgascreen
->ms_samples
);
1109 (void) mtx_init(&svgascreen
->tex_mutex
, mtx_plain
);
1110 (void) mtx_init(&svgascreen
->swc_mutex
, mtx_recursive
);
1112 svga_screen_cache_init(svgascreen
);
1114 if (debug_get_bool_option("SVGA_NO_LOGGING", FALSE
) == TRUE
) {
1115 svgascreen
->sws
->host_log
= nop_host_log
;
1117 init_logging(screen
);
1128 struct svga_winsys_screen
*
1129 svga_winsys_screen(struct pipe_screen
*screen
)
1131 return svga_screen(screen
)->sws
;
1136 struct svga_screen
*
1137 svga_screen(struct pipe_screen
*screen
)
1140 assert(screen
->destroy
== svga_destroy_screen
);
1141 return (struct svga_screen
*)screen
;