src/gallium/drivers/svga/svga_screen.c

   1 /**********************************************************
   2  * Copyright 2008-2009 VMware, Inc.  All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person
   5  * obtaining a copy of this software and associated documentation
   6  * files (the "Software"), to deal in the Software without
   7  * restriction, including without limitation the rights to use, copy,
   8  * modify, merge, publish, distribute, sublicense, and/or sell copies
   9  * of the Software, and to permit persons to whom the Software is
  10  * furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be
  13  * included in all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  16  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  17  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  18  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  19  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  20  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  21  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  *
  24  **********************************************************/
  25
  26 #include "git_sha1.h" /* For MESA_GIT_SHA1 */
  27 #include "util/u_format.h"
  28 #include "util/u_memory.h"
  29 #include "util/u_inlines.h"
  30 #include "util/u_string.h"
  31 #include "util/u_math.h"
  32
  33 #include "os/os_process.h"
  34
  35 #include "svga_winsys.h"
  36 #include "svga_public.h"
  37 #include "svga_context.h"
  38 #include "svga_format.h"
  39 #include "svga_msg.h"
  40 #include "svga_screen.h"
  41 #include "svga_tgsi.h"
  42 #include "svga_resource_texture.h"
  43 #include "svga_resource.h"
  44 #include "svga_debug.h"
  45
  46 #include "svga3d_shaderdefs.h"
  47 #include "VGPU10ShaderTokens.h"
  48
  49 /* NOTE: this constant may get moved into a svga3d*.h header file */
  50 #define SVGA3D_DX_MAX_RESOURCE_SIZE (128 * 1024 * 1024)
  51
  52 #ifdef DEBUG
  53 int SVGA_DEBUG = 0;
  54
  55 static const struct debug_named_value svga_debug_flags[] = {
  56    { "dma",         DEBUG_DMA, NULL },
  57    { "tgsi",        DEBUG_TGSI, NULL },
  58    { "pipe",        DEBUG_PIPE, NULL },
  59    { "state",       DEBUG_STATE, NULL },
  60    { "screen",      DEBUG_SCREEN, NULL },
  61    { "tex",         DEBUG_TEX, NULL },
  62    { "swtnl",       DEBUG_SWTNL, NULL },
  63    { "const",       DEBUG_CONSTS, NULL },
  64    { "viewport",    DEBUG_VIEWPORT, NULL },
  65    { "views",       DEBUG_VIEWS, NULL },
  66    { "perf",        DEBUG_PERF, NULL },
  67    { "flush",       DEBUG_FLUSH, NULL },
  68    { "sync",        DEBUG_SYNC, NULL },
  69    { "cache",       DEBUG_CACHE, NULL },
  70    { "streamout",   DEBUG_STREAMOUT, NULL },
  71    { "query",       DEBUG_QUERY, NULL },
  72    { "samplers",    DEBUG_SAMPLERS, NULL },
  73    DEBUG_NAMED_VALUE_END
  74 };
  75 #endif
  76
  77 static const char *
  78 svga_get_vendor( struct pipe_screen *pscreen )
  79 {
  80    return "VMware, Inc.";
  81 }
  82
  83
  84 static const char *
  85 svga_get_name( struct pipe_screen *pscreen )
  86 {
  87    const char *build = "", *llvm = "", *mutex = "";
  88    static char name[100];
  89 #ifdef DEBUG
  90    /* Only return internal details in the DEBUG version:
  91     */
  92    build = "build: DEBUG;";
  93    mutex = "mutex: " PIPE_ATOMIC ";";
  94 #elif defined(VMX86_STATS)
  95    build = "build: OPT;";
  96 #else
  97    build = "build: RELEASE;";
  98 #endif
  99 #ifdef HAVE_LLVM
 100    llvm = "LLVM;";
 101 #endif
 102
 103    util_snprintf(name, sizeof(name), "SVGA3D; %s %s %s", build, mutex, llvm);
 104    return name;
 105 }
 106
 107
 108 /** Helper for querying float-valued device cap */
 109 static float
 110 get_float_cap(struct svga_winsys_screen *sws, SVGA3dDevCapIndex cap,
 111               float defaultVal)
 112 {
 113    SVGA3dDevCapResult result;
 114    if (sws->get_cap(sws, cap, &result))
 115       return result.f;
 116    else
 117       return defaultVal;
 118 }
 119
 120
 121 /** Helper for querying uint-valued device cap */
 122 static unsigned
 123 get_uint_cap(struct svga_winsys_screen *sws, SVGA3dDevCapIndex cap,
 124              unsigned defaultVal)
 125 {
 126    SVGA3dDevCapResult result;
 127    if (sws->get_cap(sws, cap, &result))
 128       return result.u;
 129    else
 130       return defaultVal;
 131 }
 132
 133
 134 /** Helper for querying boolean-valued device cap */
 135 static boolean
 136 get_bool_cap(struct svga_winsys_screen *sws, SVGA3dDevCapIndex cap,
 137              boolean defaultVal)
 138 {
 139    SVGA3dDevCapResult result;
 140    if (sws->get_cap(sws, cap, &result))
 141       return result.b;
 142    else
 143       return defaultVal;
 144 }
 145
 146
 147 static float
 148 svga_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
 149 {
 150    struct svga_screen *svgascreen = svga_screen(screen);
 151    struct svga_winsys_screen *sws = svgascreen->sws;
 152
 153    switch (param) {
 154    case PIPE_CAPF_MAX_LINE_WIDTH:
 155       return svgascreen->maxLineWidth;
 156    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 157       return svgascreen->maxLineWidthAA;
 158
 159    case PIPE_CAPF_MAX_POINT_WIDTH:
 160       /* fall-through */
 161    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 162       return svgascreen->maxPointSize;
 163
 164    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 165       return (float) get_uint_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY, 4);
 166
 167    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 168       return 15.0;
 169
 170    case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 171       /* fall-through */
 172    case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 173       /* fall-through */
 174    case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 175       return 0.0f;
 176
 177    }
 178
 179    debug_printf("Unexpected PIPE_CAPF_ query %u\n", param);
 180    return 0;
 181 }
 182
 183
 184 static int
 185 svga_get_param(struct pipe_screen *screen, enum pipe_cap param)
 186 {
 187    struct svga_screen *svgascreen = svga_screen(screen);
 188    struct svga_winsys_screen *sws = svgascreen->sws;
 189    SVGA3dDevCapResult result;
 190
 191    switch (param) {
 192    case PIPE_CAP_NPOT_TEXTURES:
 193    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 194    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 195       return 1;
 196    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 197       /*
 198        * "In virtually every OpenGL implementation and hardware,
 199        * GL_MAX_DUAL_SOURCE_DRAW_BUFFERS is 1"
 200        * http://www.opengl.org/wiki/Blending
 201        */
 202       return sws->have_vgpu10 ? 1 : 0;
 203    case PIPE_CAP_ANISOTROPIC_FILTER:
 204       return 1;
 205    case PIPE_CAP_POINT_SPRITE:
 206       return 1;
 207    case PIPE_CAP_TGSI_TEXCOORD:
 208       return 0;
 209    case PIPE_CAP_MAX_RENDER_TARGETS:
 210       return svgascreen->max_color_buffers;
 211    case PIPE_CAP_OCCLUSION_QUERY:
 212       return 1;
 213    case PIPE_CAP_QUERY_TIME_ELAPSED:
 214       return 0;
 215    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 216       return sws->have_vgpu10;
 217    case PIPE_CAP_TEXTURE_SWIZZLE:
 218       return 1;
 219    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 220       return 0;
 221    case PIPE_CAP_USER_VERTEX_BUFFERS:
 222       return 0;
 223    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 224       return 256;
 225
 226    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 227       {
 228          unsigned levels = SVGA_MAX_TEXTURE_LEVELS;
 229          if (sws->get_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH, &result))
 230             levels = MIN2(util_logbase2(result.u) + 1, levels);
 231          else
 232             levels = 12 /* 2048x2048 */;
 233          if (sws->get_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT, &result))
 234             levels = MIN2(util_logbase2(result.u) + 1, levels);
 235          else
 236             levels = 12 /* 2048x2048 */;
 237          return levels;
 238       }
 239
 240    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 241       if (!sws->get_cap(sws, SVGA3D_DEVCAP_MAX_VOLUME_EXTENT, &result))
 242          return 8;  /* max 128x128x128 */
 243       return MIN2(util_logbase2(result.u) + 1, SVGA_MAX_TEXTURE_LEVELS);
 244
 245    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 246       /*
 247        * No mechanism to query the host, and at least limited to 2048x2048 on
 248        * certain hardware.
 249        */
 250       return MIN2(screen->get_param(screen, PIPE_CAP_MAX_TEXTURE_2D_LEVELS),
 251                   12 /* 2048x2048 */);
 252
 253    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 254       return sws->have_vgpu10 ? SVGA3D_MAX_SURFACE_ARRAYSIZE : 0;
 255
 256    case PIPE_CAP_BLEND_EQUATION_SEPARATE: /* req. for GL 1.5 */
 257       return 1;
 258
 259    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 260       return 1;
 261    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 262       return sws->have_vgpu10;
 263    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 264       return 0;
 265    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 266       return !sws->have_vgpu10;
 267
 268    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 269       return 1; /* The color outputs of vertex shaders are not clamped */
 270    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 271       return 0; /* The driver can't clamp vertex colors */
 272    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 273       return 0; /* The driver can't clamp fragment colors */
 274
 275    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 276       return 1; /* expected for GL_ARB_framebuffer_object */
 277
 278    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 279       return sws->have_vgpu10 ? 330 : 120;
 280
 281    case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 282       return sws->have_vgpu10 ? 140 : 120;
 283
 284    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 285       return 0;
 286
 287    case PIPE_CAP_SM3:
 288       return 1;
 289
 290    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 291    case PIPE_CAP_INDEP_BLEND_ENABLE:
 292    case PIPE_CAP_CONDITIONAL_RENDER:
 293    case PIPE_CAP_QUERY_TIMESTAMP:
 294    case PIPE_CAP_TGSI_INSTANCEID:
 295    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 296    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 297    case PIPE_CAP_FAKE_SW_MSAA:
 298       return sws->have_vgpu10;
 299
 300    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 301       return sws->have_vgpu10 ? SVGA3D_DX_MAX_SOTARGETS : 0;
 302    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 303       return sws->have_vgpu10 ? 4 : 0;
 304    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 305       return sws->have_vgpu10 ? SVGA3D_MAX_STREAMOUT_DECLS : 0;
 306    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 307    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 308       return 0;
 309    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 310       return svgascreen->ms_samples ? 1 : 0;
 311
 312    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 313       /* convert bytes to texels for the case of the largest texel
 314        * size: float[4].
 315        */
 316       return SVGA3D_DX_MAX_RESOURCE_SIZE / (4 * sizeof(float));
 317
 318    case PIPE_CAP_MIN_TEXEL_OFFSET:
 319       return sws->have_vgpu10 ? VGPU10_MIN_TEXEL_FETCH_OFFSET : 0;
 320    case PIPE_CAP_MAX_TEXEL_OFFSET:
 321       return sws->have_vgpu10 ? VGPU10_MAX_TEXEL_FETCH_OFFSET : 0;
 322
 323    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 324    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 325       return 0;
 326
 327    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 328       return sws->have_vgpu10 ? 256 : 0;
 329    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 330       return sws->have_vgpu10 ? 1024 : 0;
 331
 332    case PIPE_CAP_PRIMITIVE_RESTART:
 333       return 1; /* may be a sw fallback, depending on restart index */
 334
 335    case PIPE_CAP_GENERATE_MIPMAP:
 336       return sws->have_generate_mipmap_cmd;
 337
 338    case PIPE_CAP_NATIVE_FENCE_FD:
 339       return sws->have_fence_fd;
 340
 341    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 342       return 1;
 343
 344    /* Unsupported features */
 345    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 346    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 347    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 348    case PIPE_CAP_INDEP_BLEND_FUNC:
 349    case PIPE_CAP_TEXTURE_BARRIER:
 350    case PIPE_CAP_MAX_VERTEX_STREAMS:
 351    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 352    case PIPE_CAP_COMPUTE:
 353    case PIPE_CAP_START_INSTANCE:
 354    case PIPE_CAP_CUBE_MAP_ARRAY:
 355    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 356    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 357    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 358    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 359    case PIPE_CAP_TEXTURE_GATHER_SM5:
 360    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 361    case PIPE_CAP_TEXTURE_QUERY_LOD:
 362    case PIPE_CAP_SAMPLE_SHADING:
 363    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 364    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 365    case PIPE_CAP_DRAW_INDIRECT:
 366    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 367    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 368    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 369    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 370    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 371    case PIPE_CAP_CLIP_HALFZ:
 372    case PIPE_CAP_VERTEXID_NOBASE:
 373    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 374    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 375    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 376    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 377    case PIPE_CAP_INVALIDATE_BUFFER:
 378    case PIPE_CAP_STRING_MARKER:
 379    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 380    case PIPE_CAP_QUERY_MEMORY_INFO:
 381    case PIPE_CAP_PCI_GROUP:
 382    case PIPE_CAP_PCI_BUS:
 383    case PIPE_CAP_PCI_DEVICE:
 384    case PIPE_CAP_PCI_FUNCTION:
 385    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 386    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
 387    case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
 388    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
 389    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
 390    case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
 391    case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
 392       return 0;
 393    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 394       return 64;
 395    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 396    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 397    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 398       return 1;  /* need 4-byte alignment for all offsets and strides */
 399    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 400       return 2048;
 401    case PIPE_CAP_MAX_VIEWPORTS:
 402       return 1;
 403    case PIPE_CAP_ENDIANNESS:
 404       return PIPE_ENDIAN_LITTLE;
 405
 406    case PIPE_CAP_VENDOR_ID:
 407       return 0x15ad; /* VMware Inc. */
 408    case PIPE_CAP_DEVICE_ID:
 409       return 0x0405; /* assume SVGA II */
 410    case PIPE_CAP_ACCELERATED:
 411       return 0; /* XXX: */
 412    case PIPE_CAP_VIDEO_MEMORY:
 413       /* XXX: Query the host ? */
 414       return 1;
 415    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 416       return sws->have_vgpu10;
 417    case PIPE_CAP_CLEAR_TEXTURE:
 418       return sws->have_vgpu10;
 419    case PIPE_CAP_UMA:
 420    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 421    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 422    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 423    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 424    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 425    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 426    case PIPE_CAP_TGSI_TXQS:
 427    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 428    case PIPE_CAP_SHAREABLE_SHADERS:
 429    case PIPE_CAP_DRAW_PARAMETERS:
 430    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 431    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 432    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 433    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 434    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 435    case PIPE_CAP_CULL_DISTANCE:
 436    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 437    case PIPE_CAP_TGSI_VOTE:
 438    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 439    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 440    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 441    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 442    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 443    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 444    case PIPE_CAP_TGSI_FS_FBFETCH:
 445    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 446    case PIPE_CAP_DOUBLES:
 447    case PIPE_CAP_INT64:
 448    case PIPE_CAP_INT64_DIVMOD:
 449    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 450    case PIPE_CAP_TGSI_CLOCK:
 451    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 452    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 453    case PIPE_CAP_TGSI_BALLOT:
 454    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 455    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 456    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 457    case PIPE_CAP_POST_DEPTH_COVERAGE:
 458    case PIPE_CAP_BINDLESS_TEXTURE:
 459    case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 460    case PIPE_CAP_QUERY_SO_OVERFLOW:
 461    case PIPE_CAP_MEMOBJ:
 462    case PIPE_CAP_LOAD_CONSTBUF:
 463    case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 464    case PIPE_CAP_TILE_RASTER_ORDER:
 465    case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 466    case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
 467    case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 468    case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 469    case PIPE_CAP_FENCE_SIGNAL:
 470    case PIPE_CAP_CONSTBUF0_FLAGS:
 471    case PIPE_CAP_PACKED_UNIFORMS:
 472    case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
 473       return 0;
 474    case PIPE_CAP_MAX_GS_INVOCATIONS:
 475       return 32;
 476    case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
 477       return 1 << 27;
 478    }
 479
 480    debug_printf("Unexpected PIPE_CAP_ query %u\n", param);
 481    return 0;
 482 }
 483
 484
 485 static int
 486 vgpu9_get_shader_param(struct pipe_screen *screen,
 487                        enum pipe_shader_type shader,
 488                        enum pipe_shader_cap param)
 489 {
 490    struct svga_screen *svgascreen = svga_screen(screen);
 491    struct svga_winsys_screen *sws = svgascreen->sws;
 492    unsigned val;
 493
 494    assert(!sws->have_vgpu10);
 495
 496    switch (shader)
 497    {
 498    case PIPE_SHADER_FRAGMENT:
 499       switch (param)
 500       {
 501       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 502       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 503          return get_uint_cap(sws,
 504                              SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS,
 505                              512);
 506       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 507       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 508          return 512;
 509       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 510          return SVGA3D_MAX_NESTING_LEVEL;
 511       case PIPE_SHADER_CAP_MAX_INPUTS:
 512          return 10;
 513       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 514          return svgascreen->max_color_buffers;
 515       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 516          return 224 * sizeof(float[4]);
 517       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 518          return 1;
 519       case PIPE_SHADER_CAP_MAX_TEMPS:
 520          val = get_uint_cap(sws, SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS, 32);
 521          return MIN2(val, SVGA3D_TEMPREG_MAX);
 522       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 523          /*
 524           * Although PS 3.0 has some addressing abilities it can only represent
 525           * loops that can be statically determined and unrolled. Given we can
 526           * only handle a subset of the cases that the state tracker already
 527           * does it is better to defer loop unrolling to the state tracker.
 528           */
 529          return 0;
 530       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 531          return 0;
 532       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 533          return 0;
 534       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 535       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 536       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 537          return 0;
 538       case PIPE_SHADER_CAP_SUBROUTINES:
 539          return 0;
 540       case PIPE_SHADER_CAP_INT64_ATOMICS:
 541       case PIPE_SHADER_CAP_INTEGERS:
 542          return 0;
 543       case PIPE_SHADER_CAP_FP16:
 544          return 0;
 545       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 546       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 547          return 16;
 548       case PIPE_SHADER_CAP_PREFERRED_IR:
 549          return PIPE_SHADER_IR_TGSI;
 550       case PIPE_SHADER_CAP_SUPPORTED_IRS:
 551          return 0;
 552       case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 553       case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 554       case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 555       case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 556       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 557       case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 558       case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 559       case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 560       case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 561       case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 562       case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 563          return 0;
 564       case PIPE_SHADER_CAP_SCALAR_ISA:
 565          return 1;
 566       case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 567          return 32;
 568       }
 569       /* If we get here, we failed to handle a cap above */
 570       debug_printf("Unexpected fragment shader query %u\n", param);
 571       return 0;
 572    case PIPE_SHADER_VERTEX:
 573       switch (param)
 574       {
 575       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 576       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 577          return get_uint_cap(sws, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS,
 578                              512);
 579       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 580       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 581          /* XXX: until we have vertex texture support */
 582          return 0;
 583       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 584          return SVGA3D_MAX_NESTING_LEVEL;
 585       case PIPE_SHADER_CAP_MAX_INPUTS:
 586          return 16;
 587       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 588          return 10;
 589       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 590          return 256 * sizeof(float[4]);
 591       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 592          return 1;
 593       case PIPE_SHADER_CAP_MAX_TEMPS:
 594          val = get_uint_cap(sws, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS, 32);
 595          return MIN2(val, SVGA3D_TEMPREG_MAX);
 596       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 597          return 0;
 598       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 599          return 0;
 600       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 601       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 602          return 1;
 603       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 604          return 0;
 605       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 606          return 1;
 607       case PIPE_SHADER_CAP_SUBROUTINES:
 608          return 0;
 609       case PIPE_SHADER_CAP_INT64_ATOMICS:
 610       case PIPE_SHADER_CAP_INTEGERS:
 611          return 0;
 612       case PIPE_SHADER_CAP_FP16:
 613          return 0;
 614       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 615       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 616          return 0;
 617       case PIPE_SHADER_CAP_PREFERRED_IR:
 618          return PIPE_SHADER_IR_TGSI;
 619       case PIPE_SHADER_CAP_SUPPORTED_IRS:
 620          return 0;
 621       case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 622       case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 623       case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 624       case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 625       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 626       case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 627       case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 628       case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 629       case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 630       case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 631       case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 632          return 0;
 633       case PIPE_SHADER_CAP_SCALAR_ISA:
 634          return 1;
 635       case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 636          return 32;
 637       }
 638       /* If we get here, we failed to handle a cap above */
 639       debug_printf("Unexpected vertex shader query %u\n", param);
 640       return 0;
 641    case PIPE_SHADER_GEOMETRY:
 642    case PIPE_SHADER_COMPUTE:
 643    case PIPE_SHADER_TESS_CTRL:
 644    case PIPE_SHADER_TESS_EVAL:
 645       /* no support for geometry, tess or compute shaders at this time */
 646       return 0;
 647    default:
 648       debug_printf("Unexpected shader type (%u) query\n", shader);
 649       return 0;
 650    }
 651    return 0;
 652 }
 653
 654
 655 static int
 656 vgpu10_get_shader_param(struct pipe_screen *screen,
 657                         enum pipe_shader_type shader,
 658                         enum pipe_shader_cap param)
 659 {
 660    struct svga_screen *svgascreen = svga_screen(screen);
 661    struct svga_winsys_screen *sws = svgascreen->sws;
 662
 663    assert(sws->have_vgpu10);
 664    (void) sws;  /* silence unused var warnings in non-debug builds */
 665
 666    /* Only VS, GS, FS supported */
 667    if (shader != PIPE_SHADER_VERTEX &&
 668        shader != PIPE_SHADER_GEOMETRY &&
 669        shader != PIPE_SHADER_FRAGMENT) {
 670       return 0;
 671    }
 672
 673    /* NOTE: we do not query the device for any caps/limits at this time */
 674
 675    /* Generally the same limits for vertex, geometry and fragment shaders */
 676    switch (param) {
 677    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 678    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 679    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 680    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 681       return 64 * 1024;
 682    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 683       return 64;
 684    case PIPE_SHADER_CAP_MAX_INPUTS:
 685       if (shader == PIPE_SHADER_FRAGMENT)
 686          return VGPU10_MAX_FS_INPUTS;
 687       else if (shader == PIPE_SHADER_GEOMETRY)
 688          return VGPU10_MAX_GS_INPUTS;
 689       else
 690          return VGPU10_MAX_VS_INPUTS;
 691    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 692       if (shader == PIPE_SHADER_FRAGMENT)
 693          return VGPU10_MAX_FS_OUTPUTS;
 694       else if (shader == PIPE_SHADER_GEOMETRY)
 695          return VGPU10_MAX_GS_OUTPUTS;
 696       else
 697          return VGPU10_MAX_VS_OUTPUTS;
 698    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 699       return VGPU10_MAX_CONSTANT_BUFFER_ELEMENT_COUNT * sizeof(float[4]);
 700    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 701       return svgascreen->max_const_buffers;
 702    case PIPE_SHADER_CAP_MAX_TEMPS:
 703       return VGPU10_MAX_TEMPS;
 704    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 705    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 706    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 707    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 708       return TRUE; /* XXX verify */
 709    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 710    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 711    case PIPE_SHADER_CAP_SUBROUTINES:
 712    case PIPE_SHADER_CAP_INTEGERS:
 713       return TRUE;
 714    case PIPE_SHADER_CAP_FP16:
 715       return FALSE;
 716    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 717    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 718       return SVGA3D_DX_MAX_SAMPLERS;
 719    case PIPE_SHADER_CAP_PREFERRED_IR:
 720       return PIPE_SHADER_IR_TGSI;
 721    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 722       return 0;
 723    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 724    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 725    case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 726    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 727    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 728    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 729    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 730    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 731    case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 732    case PIPE_SHADER_CAP_INT64_ATOMICS:
 733    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 734    case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 735       return 0;
 736    case PIPE_SHADER_CAP_SCALAR_ISA:
 737       return 1;
 738    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 739       return 32;
 740    default:
 741       debug_printf("Unexpected vgpu10 shader query %u\n", param);
 742       return 0;
 743    }
 744    return 0;
 745 }
 746
 747
 748 static int
 749 svga_get_shader_param(struct pipe_screen *screen, enum pipe_shader_type shader,
 750                       enum pipe_shader_cap param)
 751 {
 752    struct svga_screen *svgascreen = svga_screen(screen);
 753    struct svga_winsys_screen *sws = svgascreen->sws;
 754    if (sws->have_vgpu10) {
 755       return vgpu10_get_shader_param(screen, shader, param);
 756    }
 757    else {
 758       return vgpu9_get_shader_param(screen, shader, param);
 759    }
 760 }
 761
 762
 763 static void
 764 svga_fence_reference(struct pipe_screen *screen,
 765                      struct pipe_fence_handle **ptr,
 766                      struct pipe_fence_handle *fence)
 767 {
 768    struct svga_winsys_screen *sws = svga_screen(screen)->sws;
 769    sws->fence_reference(sws, ptr, fence);
 770 }
 771
 772
 773 static boolean
 774 svga_fence_finish(struct pipe_screen *screen,
 775                   struct pipe_context *ctx,
 776                   struct pipe_fence_handle *fence,
 777                   uint64_t timeout)
 778 {
 779    struct svga_winsys_screen *sws = svga_screen(screen)->sws;
 780    boolean retVal;
 781
 782    SVGA_STATS_TIME_PUSH(sws, SVGA_STATS_TIME_FENCEFINISH);
 783
 784    if (!timeout) {
 785       retVal = sws->fence_signalled(sws, fence, 0) == 0;
 786    }
 787    else {
 788       SVGA_DBG(DEBUG_DMA|DEBUG_PERF, "%s fence_ptr %p\n",
 789                __FUNCTION__, fence);
 790
 791       retVal = sws->fence_finish(sws, fence, timeout, 0) == 0;
 792    }
 793
 794    SVGA_STATS_TIME_POP(sws);
 795
 796    return retVal;
 797 }
 798
 799
 800 static int
 801 svga_fence_get_fd(struct pipe_screen *screen,
 802                   struct pipe_fence_handle *fence)
 803 {
 804    struct svga_winsys_screen *sws = svga_screen(screen)->sws;
 805
 806    return sws->fence_get_fd(sws, fence, TRUE);
 807 }
 808
 809
 810 static int
 811 svga_get_driver_query_info(struct pipe_screen *screen,
 812                            unsigned index,
 813                            struct pipe_driver_query_info *info)
 814 {
 815 #define QUERY(NAME, ENUM, UNITS) \
 816    {NAME, ENUM, {0}, UNITS, PIPE_DRIVER_QUERY_RESULT_TYPE_AVERAGE, 0, 0x0}
 817
 818    static const struct pipe_driver_query_info queries[] = {
 819       /* per-frame counters */
 820       QUERY("num-draw-calls", SVGA_QUERY_NUM_DRAW_CALLS,
 821             PIPE_DRIVER_QUERY_TYPE_UINT64),
 822       QUERY("num-fallbacks", SVGA_QUERY_NUM_FALLBACKS,
 823             PIPE_DRIVER_QUERY_TYPE_UINT64),
 824       QUERY("num-flushes", SVGA_QUERY_NUM_FLUSHES,
 825             PIPE_DRIVER_QUERY_TYPE_UINT64),
 826       QUERY("num-validations", SVGA_QUERY_NUM_VALIDATIONS,
 827             PIPE_DRIVER_QUERY_TYPE_UINT64),
 828       QUERY("map-buffer-time", SVGA_QUERY_MAP_BUFFER_TIME,
 829             PIPE_DRIVER_QUERY_TYPE_MICROSECONDS),
 830       QUERY("num-buffers-mapped", SVGA_QUERY_NUM_BUFFERS_MAPPED,
 831             PIPE_DRIVER_QUERY_TYPE_UINT64),
 832       QUERY("num-textures-mapped", SVGA_QUERY_NUM_TEXTURES_MAPPED,
 833             PIPE_DRIVER_QUERY_TYPE_UINT64),
 834       QUERY("num-bytes-uploaded", SVGA_QUERY_NUM_BYTES_UPLOADED,
 835             PIPE_DRIVER_QUERY_TYPE_BYTES),
 836       QUERY("command-buffer-size", SVGA_QUERY_COMMAND_BUFFER_SIZE,
 837             PIPE_DRIVER_QUERY_TYPE_BYTES),
 838       QUERY("flush-time", SVGA_QUERY_FLUSH_TIME,
 839             PIPE_DRIVER_QUERY_TYPE_MICROSECONDS),
 840       QUERY("surface-write-flushes", SVGA_QUERY_SURFACE_WRITE_FLUSHES,
 841             PIPE_DRIVER_QUERY_TYPE_UINT64),
 842       QUERY("num-readbacks", SVGA_QUERY_NUM_READBACKS,
 843             PIPE_DRIVER_QUERY_TYPE_UINT64),
 844       QUERY("num-resource-updates", SVGA_QUERY_NUM_RESOURCE_UPDATES,
 845             PIPE_DRIVER_QUERY_TYPE_UINT64),
 846       QUERY("num-buffer-uploads", SVGA_QUERY_NUM_BUFFER_UPLOADS,
 847             PIPE_DRIVER_QUERY_TYPE_UINT64),
 848       QUERY("num-const-buf-updates", SVGA_QUERY_NUM_CONST_BUF_UPDATES,
 849             PIPE_DRIVER_QUERY_TYPE_UINT64),
 850       QUERY("num-const-updates", SVGA_QUERY_NUM_CONST_UPDATES,
 851             PIPE_DRIVER_QUERY_TYPE_UINT64),
 852
 853       /* running total counters */
 854       QUERY("memory-used", SVGA_QUERY_MEMORY_USED,
 855             PIPE_DRIVER_QUERY_TYPE_BYTES),
 856       QUERY("num-shaders", SVGA_QUERY_NUM_SHADERS,
 857             PIPE_DRIVER_QUERY_TYPE_UINT64),
 858       QUERY("num-resources", SVGA_QUERY_NUM_RESOURCES,
 859             PIPE_DRIVER_QUERY_TYPE_UINT64),
 860       QUERY("num-state-objects", SVGA_QUERY_NUM_STATE_OBJECTS,
 861             PIPE_DRIVER_QUERY_TYPE_UINT64),
 862       QUERY("num-surface-views", SVGA_QUERY_NUM_SURFACE_VIEWS,
 863             PIPE_DRIVER_QUERY_TYPE_UINT64),
 864       QUERY("num-generate-mipmap", SVGA_QUERY_NUM_GENERATE_MIPMAP,
 865             PIPE_DRIVER_QUERY_TYPE_UINT64),
 866       QUERY("num-failed-allocations", SVGA_QUERY_NUM_FAILED_ALLOCATIONS,
 867             PIPE_DRIVER_QUERY_TYPE_UINT64),
 868       QUERY("num-commands-per-draw", SVGA_QUERY_NUM_COMMANDS_PER_DRAW,
 869             PIPE_DRIVER_QUERY_TYPE_FLOAT),
 870    };
 871 #undef QUERY
 872
 873    if (!info)
 874       return ARRAY_SIZE(queries);
 875
 876    if (index >= ARRAY_SIZE(queries))
 877       return 0;
 878
 879    *info = queries[index];
 880    return 1;
 881 }
 882
 883
 884 static void
 885 init_logging(struct pipe_screen *screen)
 886 {
 887    static const char *log_prefix = "Mesa: ";
 888    char host_log[1000];
 889
 890    /* Log Version to Host */
 891    util_snprintf(host_log, sizeof(host_log) - strlen(log_prefix),
 892                  "%s%s", log_prefix, svga_get_name(screen));
 893    svga_host_log(host_log);
 894
 895    util_snprintf(host_log, sizeof(host_log) - strlen(log_prefix),
 896                  "%s" PACKAGE_VERSION MESA_GIT_SHA1, log_prefix);
 897    svga_host_log(host_log);
 898
 899    /* If the SVGA_EXTRA_LOGGING env var is set, log the process's command
 900     * line (program name and arguments).
 901     */
 902    if (debug_get_bool_option("SVGA_EXTRA_LOGGING", FALSE)) {
 903       char cmdline[1000];
 904       if (os_get_command_line(cmdline, sizeof(cmdline))) {
 905          util_snprintf(host_log, sizeof(host_log) - strlen(log_prefix),
 906                        "%s%s", log_prefix, cmdline);
 907          svga_host_log(host_log);
 908       }
 909    }
 910 }
 911
 912
 913 static void
 914 svga_destroy_screen( struct pipe_screen *screen )
 915 {
 916    struct svga_screen *svgascreen = svga_screen(screen);
 917
 918    svga_screen_cache_cleanup(svgascreen);
 919
 920    mtx_destroy(&svgascreen->swc_mutex);
 921    mtx_destroy(&svgascreen->tex_mutex);
 922
 923    svgascreen->sws->destroy(svgascreen->sws);
 924
 925    FREE(svgascreen);
 926 }
 927
 928
 929 /**
 930  * Create a new svga_screen object
 931  */
 932 struct pipe_screen *
 933 svga_screen_create(struct svga_winsys_screen *sws)
 934 {
 935    struct svga_screen *svgascreen;
 936    struct pipe_screen *screen;
 937
 938 #ifdef DEBUG
 939    SVGA_DEBUG = debug_get_flags_option("SVGA_DEBUG", svga_debug_flags, 0 );
 940 #endif
 941
 942    svgascreen = CALLOC_STRUCT(svga_screen);
 943    if (!svgascreen)
 944       goto error1;
 945
 946    svgascreen->debug.force_level_surface_view =
 947       debug_get_bool_option("SVGA_FORCE_LEVEL_SURFACE_VIEW", FALSE);
 948    svgascreen->debug.force_surface_view =
 949       debug_get_bool_option("SVGA_FORCE_SURFACE_VIEW", FALSE);
 950    svgascreen->debug.force_sampler_view =
 951       debug_get_bool_option("SVGA_FORCE_SAMPLER_VIEW", FALSE);
 952    svgascreen->debug.no_surface_view =
 953       debug_get_bool_option("SVGA_NO_SURFACE_VIEW", FALSE);
 954    svgascreen->debug.no_sampler_view =
 955       debug_get_bool_option("SVGA_NO_SAMPLER_VIEW", FALSE);
 956    svgascreen->debug.no_cache_index_buffers =
 957       debug_get_bool_option("SVGA_NO_CACHE_INDEX_BUFFERS", FALSE);
 958
 959    screen = &svgascreen->screen;
 960
 961    screen->destroy = svga_destroy_screen;
 962    screen->get_name = svga_get_name;
 963    screen->get_vendor = svga_get_vendor;
 964    screen->get_device_vendor = svga_get_vendor; // TODO actual device vendor
 965    screen->get_param = svga_get_param;
 966    screen->get_shader_param = svga_get_shader_param;
 967    screen->get_paramf = svga_get_paramf;
 968    screen->get_timestamp = NULL;
 969    screen->is_format_supported = svga_is_format_supported;
 970    screen->context_create = svga_context_create;
 971    screen->fence_reference = svga_fence_reference;
 972    screen->fence_finish = svga_fence_finish;
 973    screen->fence_get_fd = svga_fence_get_fd;
 974
 975    screen->get_driver_query_info = svga_get_driver_query_info;
 976    svgascreen->sws = sws;
 977
 978    svga_init_screen_resource_functions(svgascreen);
 979
 980    if (sws->get_hw_version) {
 981       svgascreen->hw_version = sws->get_hw_version(sws);
 982    } else {
 983       svgascreen->hw_version = SVGA3D_HWVERSION_WS65_B1;
 984    }
 985
 986    if (svgascreen->hw_version < SVGA3D_HWVERSION_WS8_B1) {
 987       /* too old for 3D acceleration */
 988       debug_printf("Hardware version 0x%x is too old for accerated 3D\n",
 989                    svgascreen->hw_version);
 990       goto error2;
 991    }
 992
 993    /*
 994     * The D16, D24X8, and D24S8 formats always do an implicit shadow compare
 995     * when sampled from, where as the DF16, DF24, and D24S8_INT do not.  So
 996     * we prefer the later when available.
 997     *
 998     * This mimics hardware vendors extensions for D3D depth sampling. See also
 999     * http://aras-p.info/texts/D3D9GPUHacks.html
1000     */
1001
1002    {
1003       boolean has_df16, has_df24, has_d24s8_int;
1004       SVGA3dSurfaceFormatCaps caps;
1005       SVGA3dSurfaceFormatCaps mask;
1006       mask.value = 0;
1007       mask.zStencil = 1;
1008       mask.texture = 1;
1009
1010       svgascreen->depth.z16 = SVGA3D_Z_D16;
1011       svgascreen->depth.x8z24 = SVGA3D_Z_D24X8;
1012       svgascreen->depth.s8z24 = SVGA3D_Z_D24S8;
1013
1014       svga_get_format_cap(svgascreen, SVGA3D_Z_DF16, &caps);
1015       has_df16 = (caps.value & mask.value) == mask.value;
1016
1017       svga_get_format_cap(svgascreen, SVGA3D_Z_DF24, &caps);
1018       has_df24 = (caps.value & mask.value) == mask.value;
1019
1020       svga_get_format_cap(svgascreen, SVGA3D_Z_D24S8_INT, &caps);
1021       has_d24s8_int = (caps.value & mask.value) == mask.value;
1022
1023       /* XXX: We might want some other logic here.
1024        * Like if we only have d24s8_int we should
1025        * emulate the other formats with that.
1026        */
1027       if (has_df16) {
1028          svgascreen->depth.z16 = SVGA3D_Z_DF16;
1029       }
1030       if (has_df24) {
1031          svgascreen->depth.x8z24 = SVGA3D_Z_DF24;
1032       }
1033       if (has_d24s8_int) {
1034          svgascreen->depth.s8z24 = SVGA3D_Z_D24S8_INT;
1035       }
1036    }
1037
1038    /* Query device caps
1039     */
1040    if (sws->have_vgpu10) {
1041       svgascreen->haveProvokingVertex
1042          = get_bool_cap(sws, SVGA3D_DEVCAP_DX_PROVOKING_VERTEX, FALSE);
1043       svgascreen->haveLineSmooth = TRUE;
1044       svgascreen->maxPointSize = 80.0F;
1045       svgascreen->max_color_buffers = SVGA3D_DX_MAX_RENDER_TARGETS;
1046
1047       /* Multisample samples per pixel */
1048       if (debug_get_bool_option("SVGA_MSAA", TRUE)) {
1049          svgascreen->ms_samples =
1050             get_uint_cap(sws, SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES, 0);
1051       }
1052
1053       /* We only support 4x, 8x, 16x MSAA */
1054       svgascreen->ms_samples &= ((1 << (4-1)) |
1055                                  (1 << (8-1)) |
1056                                  (1 << (16-1)));
1057
1058       /* Maximum number of constant buffers */
1059       svgascreen->max_const_buffers =
1060          get_uint_cap(sws, SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS, 1);
1061       assert(svgascreen->max_const_buffers <= SVGA_MAX_CONST_BUFS);
1062    }
1063    else {
1064       /* VGPU9 */
1065       unsigned vs_ver = get_uint_cap(sws, SVGA3D_DEVCAP_VERTEX_SHADER_VERSION,
1066                                      SVGA3DVSVERSION_NONE);
1067       unsigned fs_ver = get_uint_cap(sws, SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION,
1068                                      SVGA3DPSVERSION_NONE);
1069
1070       /* we require Shader model 3.0 or later */
1071       if (fs_ver < SVGA3DPSVERSION_30 || vs_ver < SVGA3DVSVERSION_30) {
1072          goto error2;
1073       }
1074
1075       svgascreen->haveProvokingVertex = FALSE;
1076
1077       svgascreen->haveLineSmooth =
1078          get_bool_cap(sws, SVGA3D_DEVCAP_LINE_AA, FALSE);
1079
1080       svgascreen->maxPointSize =
1081          get_float_cap(sws, SVGA3D_DEVCAP_MAX_POINT_SIZE, 1.0f);
1082       /* Keep this to a reasonable size to avoid failures in conform/pntaa.c */
1083       svgascreen->maxPointSize = MIN2(svgascreen->maxPointSize, 80.0f);
1084
1085       /* The SVGA3D device always supports 4 targets at this time, regardless
1086        * of what querying SVGA3D_DEVCAP_MAX_RENDER_TARGETS might return.
1087        */
1088       svgascreen->max_color_buffers = 4;
1089
1090       /* Only support one constant buffer
1091        */
1092       svgascreen->max_const_buffers = 1;
1093
1094       /* No multisampling */
1095       svgascreen->ms_samples = 0;
1096    }
1097
1098    /* common VGPU9 / VGPU10 caps */
1099    svgascreen->haveLineStipple =
1100       get_bool_cap(sws, SVGA3D_DEVCAP_LINE_STIPPLE, FALSE);
1101
1102    svgascreen->maxLineWidth =
1103       MAX2(1.0, get_float_cap(sws, SVGA3D_DEVCAP_MAX_LINE_WIDTH, 1.0f));
1104
1105    svgascreen->maxLineWidthAA =
1106       MAX2(1.0, get_float_cap(sws, SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH, 1.0f));
1107
1108    if (0) {
1109       debug_printf("svga: haveProvokingVertex %u\n",
1110                    svgascreen->haveProvokingVertex);
1111       debug_printf("svga: haveLineStip %u  "
1112                    "haveLineSmooth %u  maxLineWidth %.2f  maxLineWidthAA %.2f\n",
1113                    svgascreen->haveLineStipple, svgascreen->haveLineSmooth,
1114                    svgascreen->maxLineWidth, svgascreen->maxLineWidthAA);
1115       debug_printf("svga: maxPointSize %g\n", svgascreen->maxPointSize);
1116       debug_printf("svga: msaa samples mask: 0x%x\n", svgascreen->ms_samples);
1117    }
1118
1119    (void) mtx_init(&svgascreen->tex_mutex, mtx_plain);
1120    (void) mtx_init(&svgascreen->swc_mutex, mtx_recursive);
1121
1122    svga_screen_cache_init(svgascreen);
1123
1124    init_logging(screen);
1125
1126    return screen;
1127 error2:
1128    FREE(svgascreen);
1129 error1:
1130    return NULL;
1131 }
1132
1133
1134 struct svga_winsys_screen *
1135 svga_winsys_screen(struct pipe_screen *screen)
1136 {
1137    return svga_screen(screen)->sws;
1138 }
1139
1140
1141 #ifdef DEBUG
1142 struct svga_screen *
1143 svga_screen(struct pipe_screen *screen)
1144 {
1145    assert(screen);
1146    assert(screen->destroy == svga_destroy_screen);
1147    return (struct svga_screen *)screen;
1148 }
1149 #endif