1 /**********************************************************
2 * Copyright 2008-2009 VMware, Inc. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 **********************************************************/
26 #include "git_sha1.h" /* For MESA_GIT_SHA1 */
27 #include "util/u_format.h"
28 #include "util/u_memory.h"
29 #include "util/u_inlines.h"
30 #include "util/u_screen.h"
31 #include "util/u_string.h"
32 #include "util/u_math.h"
34 #include "os/os_process.h"
36 #include "svga_winsys.h"
37 #include "svga_public.h"
38 #include "svga_context.h"
39 #include "svga_format.h"
41 #include "svga_screen.h"
42 #include "svga_tgsi.h"
43 #include "svga_resource_texture.h"
44 #include "svga_resource.h"
45 #include "svga_debug.h"
47 #include "svga3d_shaderdefs.h"
48 #include "VGPU10ShaderTokens.h"
50 /* NOTE: this constant may get moved into a svga3d*.h header file */
51 #define SVGA3D_DX_MAX_RESOURCE_SIZE (128 * 1024 * 1024)
56 static const struct debug_named_value svga_debug_flags
[] = {
57 { "dma", DEBUG_DMA
, NULL
},
58 { "tgsi", DEBUG_TGSI
, NULL
},
59 { "pipe", DEBUG_PIPE
, NULL
},
60 { "state", DEBUG_STATE
, NULL
},
61 { "screen", DEBUG_SCREEN
, NULL
},
62 { "tex", DEBUG_TEX
, NULL
},
63 { "swtnl", DEBUG_SWTNL
, NULL
},
64 { "const", DEBUG_CONSTS
, NULL
},
65 { "viewport", DEBUG_VIEWPORT
, NULL
},
66 { "views", DEBUG_VIEWS
, NULL
},
67 { "perf", DEBUG_PERF
, NULL
},
68 { "flush", DEBUG_FLUSH
, NULL
},
69 { "sync", DEBUG_SYNC
, NULL
},
70 { "cache", DEBUG_CACHE
, NULL
},
71 { "streamout", DEBUG_STREAMOUT
, NULL
},
72 { "query", DEBUG_QUERY
, NULL
},
73 { "samplers", DEBUG_SAMPLERS
, NULL
},
79 svga_get_vendor( struct pipe_screen
*pscreen
)
81 return "VMware, Inc.";
86 svga_get_name( struct pipe_screen
*pscreen
)
88 const char *build
= "", *llvm
= "", *mutex
= "";
89 static char name
[100];
91 /* Only return internal details in the DEBUG version:
93 build
= "build: DEBUG;";
94 mutex
= "mutex: " PIPE_ATOMIC
";";
96 build
= "build: RELEASE;";
102 util_snprintf(name
, sizeof(name
), "SVGA3D; %s %s %s", build
, mutex
, llvm
);
107 /** Helper for querying float-valued device cap */
109 get_float_cap(struct svga_winsys_screen
*sws
, SVGA3dDevCapIndex cap
,
112 SVGA3dDevCapResult result
;
113 if (sws
->get_cap(sws
, cap
, &result
))
120 /** Helper for querying uint-valued device cap */
122 get_uint_cap(struct svga_winsys_screen
*sws
, SVGA3dDevCapIndex cap
,
125 SVGA3dDevCapResult result
;
126 if (sws
->get_cap(sws
, cap
, &result
))
133 /** Helper for querying boolean-valued device cap */
135 get_bool_cap(struct svga_winsys_screen
*sws
, SVGA3dDevCapIndex cap
,
138 SVGA3dDevCapResult result
;
139 if (sws
->get_cap(sws
, cap
, &result
))
147 svga_get_paramf(struct pipe_screen
*screen
, enum pipe_capf param
)
149 struct svga_screen
*svgascreen
= svga_screen(screen
);
150 struct svga_winsys_screen
*sws
= svgascreen
->sws
;
153 case PIPE_CAPF_MAX_LINE_WIDTH
:
154 return svgascreen
->maxLineWidth
;
155 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
156 return svgascreen
->maxLineWidthAA
;
158 case PIPE_CAPF_MAX_POINT_WIDTH
:
160 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
161 return svgascreen
->maxPointSize
;
163 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
164 return (float) get_uint_cap(sws
, SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY
, 4);
166 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
169 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE
:
171 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE
:
173 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY
:
178 debug_printf("Unexpected PIPE_CAPF_ query %u\n", param
);
184 svga_get_param(struct pipe_screen
*screen
, enum pipe_cap param
)
186 struct svga_screen
*svgascreen
= svga_screen(screen
);
187 struct svga_winsys_screen
*sws
= svgascreen
->sws
;
188 SVGA3dDevCapResult result
;
191 case PIPE_CAP_NPOT_TEXTURES
:
192 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
193 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS
:
195 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
197 * "In virtually every OpenGL implementation and hardware,
198 * GL_MAX_DUAL_SOURCE_DRAW_BUFFERS is 1"
199 * http://www.opengl.org/wiki/Blending
201 return sws
->have_vgpu10
? 1 : 0;
202 case PIPE_CAP_ANISOTROPIC_FILTER
:
204 case PIPE_CAP_POINT_SPRITE
:
206 case PIPE_CAP_TGSI_TEXCOORD
:
208 case PIPE_CAP_MAX_RENDER_TARGETS
:
209 return svgascreen
->max_color_buffers
;
210 case PIPE_CAP_OCCLUSION_QUERY
:
212 case PIPE_CAP_QUERY_TIME_ELAPSED
:
214 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
215 return sws
->have_vgpu10
;
216 case PIPE_CAP_TEXTURE_SWIZZLE
:
218 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
220 case PIPE_CAP_USER_VERTEX_BUFFERS
:
222 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
225 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
227 unsigned levels
= SVGA_MAX_TEXTURE_LEVELS
;
228 if (sws
->get_cap(sws
, SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH
, &result
))
229 levels
= MIN2(util_logbase2(result
.u
) + 1, levels
);
231 levels
= 12 /* 2048x2048 */;
232 if (sws
->get_cap(sws
, SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT
, &result
))
233 levels
= MIN2(util_logbase2(result
.u
) + 1, levels
);
235 levels
= 12 /* 2048x2048 */;
239 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
240 if (!sws
->get_cap(sws
, SVGA3D_DEVCAP_MAX_VOLUME_EXTENT
, &result
))
241 return 8; /* max 128x128x128 */
242 return MIN2(util_logbase2(result
.u
) + 1, SVGA_MAX_TEXTURE_LEVELS
);
244 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
246 * No mechanism to query the host, and at least limited to 2048x2048 on
249 return MIN2(screen
->get_param(screen
, PIPE_CAP_MAX_TEXTURE_2D_LEVELS
),
252 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
253 return sws
->have_vgpu10
? SVGA3D_MAX_SURFACE_ARRAYSIZE
: 0;
255 case PIPE_CAP_BLEND_EQUATION_SEPARATE
: /* req. for GL 1.5 */
258 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
260 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
261 return sws
->have_vgpu10
;
262 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
264 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
265 return !sws
->have_vgpu10
;
267 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
268 return 1; /* The color outputs of vertex shaders are not clamped */
269 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
270 return 0; /* The driver can't clamp vertex colors */
271 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
272 return 0; /* The driver can't clamp fragment colors */
274 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
275 return 1; /* expected for GL_ARB_framebuffer_object */
277 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
278 return sws
->have_vgpu10
? 330 : 120;
280 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY
:
281 return sws
->have_vgpu10
? 330 : 120;
283 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
284 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE
:
290 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
291 case PIPE_CAP_INDEP_BLEND_ENABLE
:
292 case PIPE_CAP_CONDITIONAL_RENDER
:
293 case PIPE_CAP_QUERY_TIMESTAMP
:
294 case PIPE_CAP_TGSI_INSTANCEID
:
295 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
296 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
297 case PIPE_CAP_FAKE_SW_MSAA
:
298 return sws
->have_vgpu10
;
300 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
301 return sws
->have_vgpu10
? SVGA3D_DX_MAX_SOTARGETS
: 0;
302 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
303 return sws
->have_vgpu10
? 4 : 0;
304 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
305 return sws
->have_vgpu10
? SVGA3D_MAX_STREAMOUT_DECLS
: 0;
306 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
307 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS
:
309 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
310 return svgascreen
->ms_samples
? 1 : 0;
312 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
313 /* convert bytes to texels for the case of the largest texel
316 return SVGA3D_DX_MAX_RESOURCE_SIZE
/ (4 * sizeof(float));
318 case PIPE_CAP_MIN_TEXEL_OFFSET
:
319 return sws
->have_vgpu10
? VGPU10_MIN_TEXEL_FETCH_OFFSET
: 0;
320 case PIPE_CAP_MAX_TEXEL_OFFSET
:
321 return sws
->have_vgpu10
? VGPU10_MAX_TEXEL_FETCH_OFFSET
: 0;
323 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
324 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
327 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
328 return sws
->have_vgpu10
? 256 : 0;
329 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
330 return sws
->have_vgpu10
? 1024 : 0;
332 case PIPE_CAP_PRIMITIVE_RESTART
:
333 return 1; /* may be a sw fallback, depending on restart index */
335 case PIPE_CAP_GENERATE_MIPMAP
:
336 return sws
->have_generate_mipmap_cmd
;
338 case PIPE_CAP_NATIVE_FENCE_FD
:
339 return sws
->have_fence_fd
;
341 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
344 case PIPE_CAP_CUBE_MAP_ARRAY
:
345 case PIPE_CAP_INDEP_BLEND_FUNC
:
346 case PIPE_CAP_SAMPLE_SHADING
:
347 case PIPE_CAP_FORCE_PERSAMPLE_INTERP
:
348 case PIPE_CAP_TEXTURE_QUERY_LOD
:
349 return sws
->have_sm4_1
;
351 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
352 return sws
->have_sm4_1
? 1 : 0; /* only single-channel textures */
353 case PIPE_CAP_MAX_VARYINGS
:
354 return sws
->have_vgpu10
? VGPU10_MAX_FS_INPUTS
: 10;
356 /* Unsupported features */
357 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
358 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE
:
359 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
360 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
361 case PIPE_CAP_TEXTURE_BARRIER
:
362 case PIPE_CAP_MAX_VERTEX_STREAMS
:
363 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
364 case PIPE_CAP_COMPUTE
:
365 case PIPE_CAP_START_INSTANCE
:
366 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
367 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
368 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
369 case PIPE_CAP_TEXTURE_GATHER_SM5
:
370 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
371 case PIPE_CAP_TEXTURE_GATHER_OFFSETS
:
372 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
373 case PIPE_CAP_DRAW_INDIRECT
:
374 case PIPE_CAP_MULTI_DRAW_INDIRECT
:
375 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS
:
376 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
377 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
378 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
379 case PIPE_CAP_CLIP_HALFZ
:
380 case PIPE_CAP_VERTEXID_NOBASE
:
381 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
382 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE
:
383 case PIPE_CAP_TGSI_PACK_HALF_FLOAT
:
384 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
:
385 case PIPE_CAP_INVALIDATE_BUFFER
:
386 case PIPE_CAP_STRING_MARKER
:
387 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS
:
388 case PIPE_CAP_QUERY_MEMORY_INFO
:
389 case PIPE_CAP_PCI_GROUP
:
390 case PIPE_CAP_PCI_BUS
:
391 case PIPE_CAP_PCI_DEVICE
:
392 case PIPE_CAP_PCI_FUNCTION
:
393 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR
:
394 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES
:
395 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES
:
396 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES
:
397 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES
:
398 case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE
:
399 case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS
:
400 case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET
:
402 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
404 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
405 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
406 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
407 return 1; /* need 4-byte alignment for all offsets and strides */
408 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
410 case PIPE_CAP_MAX_VIEWPORTS
:
412 case PIPE_CAP_ENDIANNESS
:
413 return PIPE_ENDIAN_LITTLE
;
415 case PIPE_CAP_VENDOR_ID
:
416 return 0x15ad; /* VMware Inc. */
417 case PIPE_CAP_DEVICE_ID
:
418 return 0x0405; /* assume SVGA II */
419 case PIPE_CAP_ACCELERATED
:
421 case PIPE_CAP_VIDEO_MEMORY
:
422 /* XXX: Query the host ? */
424 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
:
425 return sws
->have_vgpu10
;
426 case PIPE_CAP_CLEAR_TEXTURE
:
427 return sws
->have_vgpu10
;
429 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY
:
430 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY
:
431 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
:
432 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
433 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
434 case PIPE_CAP_DEPTH_BOUNDS_TEST
:
435 case PIPE_CAP_TGSI_TXQS
:
436 case PIPE_CAP_SHAREABLE_SHADERS
:
437 case PIPE_CAP_DRAW_PARAMETERS
:
438 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL
:
439 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL
:
440 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY
:
441 case PIPE_CAP_QUERY_BUFFER_OBJECT
:
442 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT
:
443 case PIPE_CAP_CULL_DISTANCE
:
444 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES
:
445 case PIPE_CAP_TGSI_VOTE
:
446 case PIPE_CAP_MAX_WINDOW_RECTANGLES
:
447 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED
:
448 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS
:
449 case PIPE_CAP_TGSI_ARRAY_COMPONENTS
:
450 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS
:
451 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY
:
452 case PIPE_CAP_TGSI_FS_FBFETCH
:
453 case PIPE_CAP_TGSI_MUL_ZERO_WINS
:
454 case PIPE_CAP_DOUBLES
:
456 case PIPE_CAP_INT64_DIVMOD
:
457 case PIPE_CAP_TGSI_TEX_TXF_LZ
:
458 case PIPE_CAP_TGSI_CLOCK
:
459 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE
:
460 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE
:
461 case PIPE_CAP_TGSI_BALLOT
:
462 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT
:
463 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX
:
464 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION
:
465 case PIPE_CAP_POST_DEPTH_COVERAGE
:
466 case PIPE_CAP_BINDLESS_TEXTURE
:
467 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF
:
468 case PIPE_CAP_QUERY_SO_OVERFLOW
:
469 case PIPE_CAP_MEMOBJ
:
470 case PIPE_CAP_LOAD_CONSTBUF
:
471 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS
:
472 case PIPE_CAP_TILE_RASTER_ORDER
:
473 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES
:
474 case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS
:
475 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET
:
476 case PIPE_CAP_CONTEXT_PRIORITY_MASK
:
477 case PIPE_CAP_FENCE_SIGNAL
:
478 case PIPE_CAP_CONSTBUF0_FLAGS
:
479 case PIPE_CAP_PACKED_UNIFORMS
:
480 case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS
:
482 case PIPE_CAP_MAX_FRAMES_IN_FLIGHT
:
484 case PIPE_CAP_MAX_GS_INVOCATIONS
:
486 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE
:
489 return u_pipe_screen_get_param_defaults(screen
, param
);
495 vgpu9_get_shader_param(struct pipe_screen
*screen
,
496 enum pipe_shader_type shader
,
497 enum pipe_shader_cap param
)
499 struct svga_screen
*svgascreen
= svga_screen(screen
);
500 struct svga_winsys_screen
*sws
= svgascreen
->sws
;
503 assert(!sws
->have_vgpu10
);
507 case PIPE_SHADER_FRAGMENT
:
510 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
511 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
512 return get_uint_cap(sws
,
513 SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS
,
515 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
516 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
518 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
519 return SVGA3D_MAX_NESTING_LEVEL
;
520 case PIPE_SHADER_CAP_MAX_INPUTS
:
522 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
523 return svgascreen
->max_color_buffers
;
524 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
525 return 224 * sizeof(float[4]);
526 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
528 case PIPE_SHADER_CAP_MAX_TEMPS
:
529 val
= get_uint_cap(sws
, SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS
, 32);
530 return MIN2(val
, SVGA3D_TEMPREG_MAX
);
531 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
533 * Although PS 3.0 has some addressing abilities it can only represent
534 * loops that can be statically determined and unrolled. Given we can
535 * only handle a subset of the cases that the state tracker already
536 * does it is better to defer loop unrolling to the state tracker.
539 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
541 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
543 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
544 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
545 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
547 case PIPE_SHADER_CAP_SUBROUTINES
:
549 case PIPE_SHADER_CAP_INT64_ATOMICS
:
550 case PIPE_SHADER_CAP_INTEGERS
:
552 case PIPE_SHADER_CAP_FP16
:
554 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
555 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
557 case PIPE_SHADER_CAP_PREFERRED_IR
:
558 return PIPE_SHADER_IR_TGSI
;
559 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
561 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
562 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
563 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
:
564 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
565 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
566 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
567 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
568 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
569 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
570 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS
:
571 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS
:
573 case PIPE_SHADER_CAP_SCALAR_ISA
:
575 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
578 /* If we get here, we failed to handle a cap above */
579 debug_printf("Unexpected fragment shader query %u\n", param
);
581 case PIPE_SHADER_VERTEX
:
584 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
585 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
586 return get_uint_cap(sws
, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS
,
588 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
589 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
590 /* XXX: until we have vertex texture support */
592 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
593 return SVGA3D_MAX_NESTING_LEVEL
;
594 case PIPE_SHADER_CAP_MAX_INPUTS
:
596 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
598 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
599 return 256 * sizeof(float[4]);
600 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
602 case PIPE_SHADER_CAP_MAX_TEMPS
:
603 val
= get_uint_cap(sws
, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS
, 32);
604 return MIN2(val
, SVGA3D_TEMPREG_MAX
);
605 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
607 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
609 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
610 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
612 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
614 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
616 case PIPE_SHADER_CAP_SUBROUTINES
:
618 case PIPE_SHADER_CAP_INT64_ATOMICS
:
619 case PIPE_SHADER_CAP_INTEGERS
:
621 case PIPE_SHADER_CAP_FP16
:
623 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
624 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
626 case PIPE_SHADER_CAP_PREFERRED_IR
:
627 return PIPE_SHADER_IR_TGSI
;
628 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
630 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
631 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
632 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
:
633 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
634 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
635 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
636 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
637 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
638 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
639 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS
:
640 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS
:
642 case PIPE_SHADER_CAP_SCALAR_ISA
:
644 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
647 /* If we get here, we failed to handle a cap above */
648 debug_printf("Unexpected vertex shader query %u\n", param
);
650 case PIPE_SHADER_GEOMETRY
:
651 case PIPE_SHADER_COMPUTE
:
652 case PIPE_SHADER_TESS_CTRL
:
653 case PIPE_SHADER_TESS_EVAL
:
654 /* no support for geometry, tess or compute shaders at this time */
657 debug_printf("Unexpected shader type (%u) query\n", shader
);
665 vgpu10_get_shader_param(struct pipe_screen
*screen
,
666 enum pipe_shader_type shader
,
667 enum pipe_shader_cap param
)
669 struct svga_screen
*svgascreen
= svga_screen(screen
);
670 struct svga_winsys_screen
*sws
= svgascreen
->sws
;
672 assert(sws
->have_vgpu10
);
673 (void) sws
; /* silence unused var warnings in non-debug builds */
675 /* Only VS, GS, FS supported */
676 if (shader
!= PIPE_SHADER_VERTEX
&&
677 shader
!= PIPE_SHADER_GEOMETRY
&&
678 shader
!= PIPE_SHADER_FRAGMENT
) {
682 /* NOTE: we do not query the device for any caps/limits at this time */
684 /* Generally the same limits for vertex, geometry and fragment shaders */
686 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
687 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
688 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
689 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
691 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
693 case PIPE_SHADER_CAP_MAX_INPUTS
:
694 if (shader
== PIPE_SHADER_FRAGMENT
)
695 return VGPU10_MAX_FS_INPUTS
;
696 else if (shader
== PIPE_SHADER_GEOMETRY
)
697 return VGPU10_MAX_GS_INPUTS
;
699 return VGPU10_MAX_VS_INPUTS
;
700 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
701 if (shader
== PIPE_SHADER_FRAGMENT
)
702 return VGPU10_MAX_FS_OUTPUTS
;
703 else if (shader
== PIPE_SHADER_GEOMETRY
)
704 return VGPU10_MAX_GS_OUTPUTS
;
706 return VGPU10_MAX_VS_OUTPUTS
;
707 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
708 return VGPU10_MAX_CONSTANT_BUFFER_ELEMENT_COUNT
* sizeof(float[4]);
709 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
710 return svgascreen
->max_const_buffers
;
711 case PIPE_SHADER_CAP_MAX_TEMPS
:
712 return VGPU10_MAX_TEMPS
;
713 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
714 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
715 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
716 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
717 return TRUE
; /* XXX verify */
718 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
719 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
720 case PIPE_SHADER_CAP_SUBROUTINES
:
721 case PIPE_SHADER_CAP_INTEGERS
:
723 case PIPE_SHADER_CAP_FP16
:
725 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
726 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
727 return SVGA3D_DX_MAX_SAMPLERS
;
728 case PIPE_SHADER_CAP_PREFERRED_IR
:
729 return PIPE_SHADER_IR_TGSI
;
730 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
732 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
733 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
734 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
:
735 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
736 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
737 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
738 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
739 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
740 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
741 case PIPE_SHADER_CAP_INT64_ATOMICS
:
742 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS
:
743 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS
:
745 case PIPE_SHADER_CAP_SCALAR_ISA
:
747 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
750 debug_printf("Unexpected vgpu10 shader query %u\n", param
);
758 svga_get_shader_param(struct pipe_screen
*screen
, enum pipe_shader_type shader
,
759 enum pipe_shader_cap param
)
761 struct svga_screen
*svgascreen
= svga_screen(screen
);
762 struct svga_winsys_screen
*sws
= svgascreen
->sws
;
763 if (sws
->have_vgpu10
) {
764 return vgpu10_get_shader_param(screen
, shader
, param
);
767 return vgpu9_get_shader_param(screen
, shader
, param
);
773 svga_fence_reference(struct pipe_screen
*screen
,
774 struct pipe_fence_handle
**ptr
,
775 struct pipe_fence_handle
*fence
)
777 struct svga_winsys_screen
*sws
= svga_screen(screen
)->sws
;
778 sws
->fence_reference(sws
, ptr
, fence
);
783 svga_fence_finish(struct pipe_screen
*screen
,
784 struct pipe_context
*ctx
,
785 struct pipe_fence_handle
*fence
,
788 struct svga_winsys_screen
*sws
= svga_screen(screen
)->sws
;
791 SVGA_STATS_TIME_PUSH(sws
, SVGA_STATS_TIME_FENCEFINISH
);
794 retVal
= sws
->fence_signalled(sws
, fence
, 0) == 0;
797 SVGA_DBG(DEBUG_DMA
|DEBUG_PERF
, "%s fence_ptr %p\n",
798 __FUNCTION__
, fence
);
800 retVal
= sws
->fence_finish(sws
, fence
, timeout
, 0) == 0;
803 SVGA_STATS_TIME_POP(sws
);
810 svga_fence_get_fd(struct pipe_screen
*screen
,
811 struct pipe_fence_handle
*fence
)
813 struct svga_winsys_screen
*sws
= svga_screen(screen
)->sws
;
815 return sws
->fence_get_fd(sws
, fence
, TRUE
);
820 svga_get_driver_query_info(struct pipe_screen
*screen
,
822 struct pipe_driver_query_info
*info
)
824 #define QUERY(NAME, ENUM, UNITS) \
825 {NAME, ENUM, {0}, UNITS, PIPE_DRIVER_QUERY_RESULT_TYPE_AVERAGE, 0, 0x0}
827 static const struct pipe_driver_query_info queries
[] = {
828 /* per-frame counters */
829 QUERY("num-draw-calls", SVGA_QUERY_NUM_DRAW_CALLS
,
830 PIPE_DRIVER_QUERY_TYPE_UINT64
),
831 QUERY("num-fallbacks", SVGA_QUERY_NUM_FALLBACKS
,
832 PIPE_DRIVER_QUERY_TYPE_UINT64
),
833 QUERY("num-flushes", SVGA_QUERY_NUM_FLUSHES
,
834 PIPE_DRIVER_QUERY_TYPE_UINT64
),
835 QUERY("num-validations", SVGA_QUERY_NUM_VALIDATIONS
,
836 PIPE_DRIVER_QUERY_TYPE_UINT64
),
837 QUERY("map-buffer-time", SVGA_QUERY_MAP_BUFFER_TIME
,
838 PIPE_DRIVER_QUERY_TYPE_MICROSECONDS
),
839 QUERY("num-buffers-mapped", SVGA_QUERY_NUM_BUFFERS_MAPPED
,
840 PIPE_DRIVER_QUERY_TYPE_UINT64
),
841 QUERY("num-textures-mapped", SVGA_QUERY_NUM_TEXTURES_MAPPED
,
842 PIPE_DRIVER_QUERY_TYPE_UINT64
),
843 QUERY("num-bytes-uploaded", SVGA_QUERY_NUM_BYTES_UPLOADED
,
844 PIPE_DRIVER_QUERY_TYPE_BYTES
),
845 QUERY("command-buffer-size", SVGA_QUERY_COMMAND_BUFFER_SIZE
,
846 PIPE_DRIVER_QUERY_TYPE_BYTES
),
847 QUERY("flush-time", SVGA_QUERY_FLUSH_TIME
,
848 PIPE_DRIVER_QUERY_TYPE_MICROSECONDS
),
849 QUERY("surface-write-flushes", SVGA_QUERY_SURFACE_WRITE_FLUSHES
,
850 PIPE_DRIVER_QUERY_TYPE_UINT64
),
851 QUERY("num-readbacks", SVGA_QUERY_NUM_READBACKS
,
852 PIPE_DRIVER_QUERY_TYPE_UINT64
),
853 QUERY("num-resource-updates", SVGA_QUERY_NUM_RESOURCE_UPDATES
,
854 PIPE_DRIVER_QUERY_TYPE_UINT64
),
855 QUERY("num-buffer-uploads", SVGA_QUERY_NUM_BUFFER_UPLOADS
,
856 PIPE_DRIVER_QUERY_TYPE_UINT64
),
857 QUERY("num-const-buf-updates", SVGA_QUERY_NUM_CONST_BUF_UPDATES
,
858 PIPE_DRIVER_QUERY_TYPE_UINT64
),
859 QUERY("num-const-updates", SVGA_QUERY_NUM_CONST_UPDATES
,
860 PIPE_DRIVER_QUERY_TYPE_UINT64
),
862 /* running total counters */
863 QUERY("memory-used", SVGA_QUERY_MEMORY_USED
,
864 PIPE_DRIVER_QUERY_TYPE_BYTES
),
865 QUERY("num-shaders", SVGA_QUERY_NUM_SHADERS
,
866 PIPE_DRIVER_QUERY_TYPE_UINT64
),
867 QUERY("num-resources", SVGA_QUERY_NUM_RESOURCES
,
868 PIPE_DRIVER_QUERY_TYPE_UINT64
),
869 QUERY("num-state-objects", SVGA_QUERY_NUM_STATE_OBJECTS
,
870 PIPE_DRIVER_QUERY_TYPE_UINT64
),
871 QUERY("num-surface-views", SVGA_QUERY_NUM_SURFACE_VIEWS
,
872 PIPE_DRIVER_QUERY_TYPE_UINT64
),
873 QUERY("num-generate-mipmap", SVGA_QUERY_NUM_GENERATE_MIPMAP
,
874 PIPE_DRIVER_QUERY_TYPE_UINT64
),
875 QUERY("num-failed-allocations", SVGA_QUERY_NUM_FAILED_ALLOCATIONS
,
876 PIPE_DRIVER_QUERY_TYPE_UINT64
),
877 QUERY("num-commands-per-draw", SVGA_QUERY_NUM_COMMANDS_PER_DRAW
,
878 PIPE_DRIVER_QUERY_TYPE_FLOAT
),
883 return ARRAY_SIZE(queries
);
885 if (index
>= ARRAY_SIZE(queries
))
888 *info
= queries
[index
];
894 init_logging(struct pipe_screen
*screen
)
896 static const char *log_prefix
= "Mesa: ";
899 /* Log Version to Host */
900 util_snprintf(host_log
, sizeof(host_log
) - strlen(log_prefix
),
901 "%s%s", log_prefix
, svga_get_name(screen
));
902 svga_host_log(host_log
);
904 util_snprintf(host_log
, sizeof(host_log
) - strlen(log_prefix
),
905 "%s" PACKAGE_VERSION MESA_GIT_SHA1
, log_prefix
);
906 svga_host_log(host_log
);
908 /* If the SVGA_EXTRA_LOGGING env var is set, log the process's command
909 * line (program name and arguments).
911 if (debug_get_bool_option("SVGA_EXTRA_LOGGING", FALSE
)) {
913 if (os_get_command_line(cmdline
, sizeof(cmdline
))) {
914 util_snprintf(host_log
, sizeof(host_log
) - strlen(log_prefix
),
915 "%s%s", log_prefix
, cmdline
);
916 svga_host_log(host_log
);
923 svga_destroy_screen( struct pipe_screen
*screen
)
925 struct svga_screen
*svgascreen
= svga_screen(screen
);
927 svga_screen_cache_cleanup(svgascreen
);
929 mtx_destroy(&svgascreen
->swc_mutex
);
930 mtx_destroy(&svgascreen
->tex_mutex
);
932 svgascreen
->sws
->destroy(svgascreen
->sws
);
939 * Create a new svga_screen object
942 svga_screen_create(struct svga_winsys_screen
*sws
)
944 struct svga_screen
*svgascreen
;
945 struct pipe_screen
*screen
;
948 SVGA_DEBUG
= debug_get_flags_option("SVGA_DEBUG", svga_debug_flags
, 0 );
951 svgascreen
= CALLOC_STRUCT(svga_screen
);
955 svgascreen
->debug
.force_level_surface_view
=
956 debug_get_bool_option("SVGA_FORCE_LEVEL_SURFACE_VIEW", FALSE
);
957 svgascreen
->debug
.force_surface_view
=
958 debug_get_bool_option("SVGA_FORCE_SURFACE_VIEW", FALSE
);
959 svgascreen
->debug
.force_sampler_view
=
960 debug_get_bool_option("SVGA_FORCE_SAMPLER_VIEW", FALSE
);
961 svgascreen
->debug
.no_surface_view
=
962 debug_get_bool_option("SVGA_NO_SURFACE_VIEW", FALSE
);
963 svgascreen
->debug
.no_sampler_view
=
964 debug_get_bool_option("SVGA_NO_SAMPLER_VIEW", FALSE
);
965 svgascreen
->debug
.no_cache_index_buffers
=
966 debug_get_bool_option("SVGA_NO_CACHE_INDEX_BUFFERS", FALSE
);
968 screen
= &svgascreen
->screen
;
970 screen
->destroy
= svga_destroy_screen
;
971 screen
->get_name
= svga_get_name
;
972 screen
->get_vendor
= svga_get_vendor
;
973 screen
->get_device_vendor
= svga_get_vendor
; // TODO actual device vendor
974 screen
->get_param
= svga_get_param
;
975 screen
->get_shader_param
= svga_get_shader_param
;
976 screen
->get_paramf
= svga_get_paramf
;
977 screen
->get_timestamp
= NULL
;
978 screen
->is_format_supported
= svga_is_format_supported
;
979 screen
->context_create
= svga_context_create
;
980 screen
->fence_reference
= svga_fence_reference
;
981 screen
->fence_finish
= svga_fence_finish
;
982 screen
->fence_get_fd
= svga_fence_get_fd
;
984 screen
->get_driver_query_info
= svga_get_driver_query_info
;
985 svgascreen
->sws
= sws
;
987 svga_init_screen_resource_functions(svgascreen
);
989 if (sws
->get_hw_version
) {
990 svgascreen
->hw_version
= sws
->get_hw_version(sws
);
992 svgascreen
->hw_version
= SVGA3D_HWVERSION_WS65_B1
;
995 if (svgascreen
->hw_version
< SVGA3D_HWVERSION_WS8_B1
) {
996 /* too old for 3D acceleration */
997 debug_printf("Hardware version 0x%x is too old for accerated 3D\n",
998 svgascreen
->hw_version
);
1002 debug_printf("%s enabled = %u\n",
1003 sws
->have_sm4_1
? "SM4_1" : "VGPU10",
1004 sws
->have_sm4_1
? 1 : sws
->have_vgpu10
);
1006 debug_printf("Mesa: %s %s (%s)\n", svga_get_name(screen
),
1007 PACKAGE_VERSION
, MESA_GIT_SHA1
);
1010 * The D16, D24X8, and D24S8 formats always do an implicit shadow compare
1011 * when sampled from, where as the DF16, DF24, and D24S8_INT do not. So
1012 * we prefer the later when available.
1014 * This mimics hardware vendors extensions for D3D depth sampling. See also
1015 * http://aras-p.info/texts/D3D9GPUHacks.html
1019 boolean has_df16
, has_df24
, has_d24s8_int
;
1020 SVGA3dSurfaceFormatCaps caps
;
1021 SVGA3dSurfaceFormatCaps mask
;
1026 svgascreen
->depth
.z16
= SVGA3D_Z_D16
;
1027 svgascreen
->depth
.x8z24
= SVGA3D_Z_D24X8
;
1028 svgascreen
->depth
.s8z24
= SVGA3D_Z_D24S8
;
1030 svga_get_format_cap(svgascreen
, SVGA3D_Z_DF16
, &caps
);
1031 has_df16
= (caps
.value
& mask
.value
) == mask
.value
;
1033 svga_get_format_cap(svgascreen
, SVGA3D_Z_DF24
, &caps
);
1034 has_df24
= (caps
.value
& mask
.value
) == mask
.value
;
1036 svga_get_format_cap(svgascreen
, SVGA3D_Z_D24S8_INT
, &caps
);
1037 has_d24s8_int
= (caps
.value
& mask
.value
) == mask
.value
;
1039 /* XXX: We might want some other logic here.
1040 * Like if we only have d24s8_int we should
1041 * emulate the other formats with that.
1044 svgascreen
->depth
.z16
= SVGA3D_Z_DF16
;
1047 svgascreen
->depth
.x8z24
= SVGA3D_Z_DF24
;
1049 if (has_d24s8_int
) {
1050 svgascreen
->depth
.s8z24
= SVGA3D_Z_D24S8_INT
;
1054 /* Query device caps
1056 if (sws
->have_vgpu10
) {
1057 svgascreen
->haveProvokingVertex
1058 = get_bool_cap(sws
, SVGA3D_DEVCAP_DX_PROVOKING_VERTEX
, FALSE
);
1059 svgascreen
->haveLineSmooth
= TRUE
;
1060 svgascreen
->maxPointSize
= 80.0F
;
1061 svgascreen
->max_color_buffers
= SVGA3D_DX_MAX_RENDER_TARGETS
;
1063 /* Multisample samples per pixel */
1064 if (sws
->have_sm4_1
&& debug_get_bool_option("SVGA_MSAA", TRUE
)) {
1065 if (get_bool_cap(sws
, SVGA3D_DEVCAP_MULTISAMPLE_2X
, FALSE
))
1066 svgascreen
->ms_samples
|= 1 << 1;
1067 if (get_bool_cap(sws
, SVGA3D_DEVCAP_MULTISAMPLE_4X
, FALSE
))
1068 svgascreen
->ms_samples
|= 1 << 3;
1071 /* Maximum number of constant buffers */
1072 svgascreen
->max_const_buffers
=
1073 get_uint_cap(sws
, SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS
, 1);
1074 assert(svgascreen
->max_const_buffers
<= SVGA_MAX_CONST_BUFS
);
1076 screen
->is_format_supported
= svga_is_dx_format_supported
;
1080 unsigned vs_ver
= get_uint_cap(sws
, SVGA3D_DEVCAP_VERTEX_SHADER_VERSION
,
1081 SVGA3DVSVERSION_NONE
);
1082 unsigned fs_ver
= get_uint_cap(sws
, SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION
,
1083 SVGA3DPSVERSION_NONE
);
1085 /* we require Shader model 3.0 or later */
1086 if (fs_ver
< SVGA3DPSVERSION_30
|| vs_ver
< SVGA3DVSVERSION_30
) {
1090 svgascreen
->haveProvokingVertex
= FALSE
;
1092 svgascreen
->haveLineSmooth
=
1093 get_bool_cap(sws
, SVGA3D_DEVCAP_LINE_AA
, FALSE
);
1095 svgascreen
->maxPointSize
=
1096 get_float_cap(sws
, SVGA3D_DEVCAP_MAX_POINT_SIZE
, 1.0f
);
1097 /* Keep this to a reasonable size to avoid failures in conform/pntaa.c */
1098 svgascreen
->maxPointSize
= MIN2(svgascreen
->maxPointSize
, 80.0f
);
1100 /* The SVGA3D device always supports 4 targets at this time, regardless
1101 * of what querying SVGA3D_DEVCAP_MAX_RENDER_TARGETS might return.
1103 svgascreen
->max_color_buffers
= 4;
1105 /* Only support one constant buffer
1107 svgascreen
->max_const_buffers
= 1;
1109 /* No multisampling */
1110 svgascreen
->ms_samples
= 0;
1113 /* common VGPU9 / VGPU10 caps */
1114 svgascreen
->haveLineStipple
=
1115 get_bool_cap(sws
, SVGA3D_DEVCAP_LINE_STIPPLE
, FALSE
);
1117 svgascreen
->maxLineWidth
=
1118 MAX2(1.0, get_float_cap(sws
, SVGA3D_DEVCAP_MAX_LINE_WIDTH
, 1.0f
));
1120 svgascreen
->maxLineWidthAA
=
1121 MAX2(1.0, get_float_cap(sws
, SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH
, 1.0f
));
1124 debug_printf("svga: haveProvokingVertex %u\n",
1125 svgascreen
->haveProvokingVertex
);
1126 debug_printf("svga: haveLineStip %u "
1127 "haveLineSmooth %u maxLineWidth %.2f maxLineWidthAA %.2f\n",
1128 svgascreen
->haveLineStipple
, svgascreen
->haveLineSmooth
,
1129 svgascreen
->maxLineWidth
, svgascreen
->maxLineWidthAA
);
1130 debug_printf("svga: maxPointSize %g\n", svgascreen
->maxPointSize
);
1131 debug_printf("svga: msaa samples mask: 0x%x\n", svgascreen
->ms_samples
);
1134 (void) mtx_init(&svgascreen
->tex_mutex
, mtx_plain
);
1135 (void) mtx_init(&svgascreen
->swc_mutex
, mtx_recursive
);
1137 svga_screen_cache_init(svgascreen
);
1139 init_logging(screen
);
1149 struct svga_winsys_screen
*
1150 svga_winsys_screen(struct pipe_screen
*screen
)
1152 return svga_screen(screen
)->sws
;
1157 struct svga_screen
*
1158 svga_screen(struct pipe_screen
*screen
)
1161 assert(screen
->destroy
== svga_destroy_screen
);
1162 return (struct svga_screen
*)screen
;