src/gallium/drivers/svga/svga_screen.c

   1 /**********************************************************
   2  * Copyright 2008-2009 VMware, Inc.  All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person
   5  * obtaining a copy of this software and associated documentation
   6  * files (the "Software"), to deal in the Software without
   7  * restriction, including without limitation the rights to use, copy,
   8  * modify, merge, publish, distribute, sublicense, and/or sell copies
   9  * of the Software, and to permit persons to whom the Software is
  10  * furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be
  13  * included in all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  16  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  17  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  18  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  19  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  20  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  21  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  *
  24  **********************************************************/
  25
  26 #include "util/u_format.h"
  27 #include "util/u_memory.h"
  28 #include "util/u_inlines.h"
  29 #include "util/u_string.h"
  30 #include "util/u_math.h"
  31
  32 #include "svga_winsys.h"
  33 #include "svga_public.h"
  34 #include "svga_context.h"
  35 #include "svga_format.h"
  36 #include "svga_screen.h"
  37 #include "svga_tgsi.h"
  38 #include "svga_resource_texture.h"
  39 #include "svga_resource.h"
  40 #include "svga_debug.h"
  41
  42 #include "svga3d_shaderdefs.h"
  43 #include "VGPU10ShaderTokens.h"
  44
  45 /* NOTE: this constant may get moved into a svga3d*.h header file */
  46 #define SVGA3D_DX_MAX_RESOURCE_SIZE (128 * 1024 * 1024)
  47
  48 #ifdef DEBUG
  49 int SVGA_DEBUG = 0;
  50
  51 static const struct debug_named_value svga_debug_flags[] = {
  52    { "dma",         DEBUG_DMA, NULL },
  53    { "tgsi",        DEBUG_TGSI, NULL },
  54    { "pipe",        DEBUG_PIPE, NULL },
  55    { "state",       DEBUG_STATE, NULL },
  56    { "screen",      DEBUG_SCREEN, NULL },
  57    { "tex",         DEBUG_TEX, NULL },
  58    { "swtnl",       DEBUG_SWTNL, NULL },
  59    { "const",       DEBUG_CONSTS, NULL },
  60    { "viewport",    DEBUG_VIEWPORT, NULL },
  61    { "views",       DEBUG_VIEWS, NULL },
  62    { "perf",        DEBUG_PERF, NULL },
  63    { "flush",       DEBUG_FLUSH, NULL },
  64    { "sync",        DEBUG_SYNC, NULL },
  65    { "cache",       DEBUG_CACHE, NULL },
  66    { "streamout",   DEBUG_STREAMOUT, NULL },
  67    { "query",       DEBUG_QUERY, NULL },
  68    DEBUG_NAMED_VALUE_END
  69 };
  70 #endif
  71
  72 static const char *
  73 svga_get_vendor( struct pipe_screen *pscreen )
  74 {
  75    return "VMware, Inc.";
  76 }
  77
  78
  79 static const char *
  80 svga_get_name( struct pipe_screen *pscreen )
  81 {
  82    const char *build = "", *llvm = "", *mutex = "";
  83    static char name[100];
  84 #ifdef DEBUG
  85    /* Only return internal details in the DEBUG version:
  86     */
  87    build = "build: DEBUG;";
  88    mutex = "mutex: " PIPE_ATOMIC ";";
  89 #elif defined(VMX86_STATS)
  90    build = "build: OPT;";
  91 #else
  92    build = "build: RELEASE;";
  93 #endif
  94 #ifdef HAVE_LLVM
  95    llvm = "LLVM;";
  96 #endif
  97
  98    util_snprintf(name, sizeof(name), "SVGA3D; %s %s %s", build, mutex, llvm);
  99    return name;
 100 }
 101
 102
 103 /** Helper for querying float-valued device cap */
 104 static float
 105 get_float_cap(struct svga_winsys_screen *sws, unsigned cap, float defaultVal)
 106 {
 107    SVGA3dDevCapResult result;
 108    if (sws->get_cap(sws, cap, &result))
 109       return result.f;
 110    else
 111       return defaultVal;
 112 }
 113
 114
 115 /** Helper for querying uint-valued device cap */
 116 static unsigned
 117 get_uint_cap(struct svga_winsys_screen *sws, unsigned cap, unsigned defaultVal)
 118 {
 119    SVGA3dDevCapResult result;
 120    if (sws->get_cap(sws, cap, &result))
 121       return result.u;
 122    else
 123       return defaultVal;
 124 }
 125
 126
 127 /** Helper for querying boolean-valued device cap */
 128 static boolean
 129 get_bool_cap(struct svga_winsys_screen *sws, unsigned cap, boolean defaultVal)
 130 {
 131    SVGA3dDevCapResult result;
 132    if (sws->get_cap(sws, cap, &result))
 133       return result.b;
 134    else
 135       return defaultVal;
 136 }
 137
 138
 139 static float
 140 svga_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
 141 {
 142    struct svga_screen *svgascreen = svga_screen(screen);
 143    struct svga_winsys_screen *sws = svgascreen->sws;
 144
 145    switch (param) {
 146    case PIPE_CAPF_MAX_LINE_WIDTH:
 147       return svgascreen->maxLineWidth;
 148    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 149       return svgascreen->maxLineWidthAA;
 150
 151    case PIPE_CAPF_MAX_POINT_WIDTH:
 152       /* fall-through */
 153    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 154       return svgascreen->maxPointSize;
 155
 156    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 157       return (float) get_uint_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY, 4);
 158
 159    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 160       return 15.0;
 161
 162    case PIPE_CAPF_GUARD_BAND_LEFT:
 163    case PIPE_CAPF_GUARD_BAND_TOP:
 164    case PIPE_CAPF_GUARD_BAND_RIGHT:
 165    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 166       return 0.0;
 167    }
 168
 169    debug_printf("Unexpected PIPE_CAPF_ query %u\n", param);
 170    return 0;
 171 }
 172
 173
 174 static int
 175 svga_get_param(struct pipe_screen *screen, enum pipe_cap param)
 176 {
 177    struct svga_screen *svgascreen = svga_screen(screen);
 178    struct svga_winsys_screen *sws = svgascreen->sws;
 179    SVGA3dDevCapResult result;
 180
 181    switch (param) {
 182    case PIPE_CAP_NPOT_TEXTURES:
 183    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 184    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 185    case PIPE_CAP_USER_INDEX_BUFFERS:
 186       return 1;
 187    case PIPE_CAP_TWO_SIDED_STENCIL:
 188       return 1;
 189    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 190       /*
 191        * "In virtually every OpenGL implementation and hardware,
 192        * GL_MAX_DUAL_SOURCE_DRAW_BUFFERS is 1"
 193        * http://www.opengl.org/wiki/Blending
 194        */
 195       return sws->have_vgpu10 ? 1 : 0;
 196    case PIPE_CAP_ANISOTROPIC_FILTER:
 197       return 1;
 198    case PIPE_CAP_POINT_SPRITE:
 199       return 1;
 200    case PIPE_CAP_TGSI_TEXCOORD:
 201       return 0;
 202    case PIPE_CAP_MAX_RENDER_TARGETS:
 203       return svgascreen->max_color_buffers;
 204    case PIPE_CAP_OCCLUSION_QUERY:
 205       return 1;
 206    case PIPE_CAP_QUERY_TIME_ELAPSED:
 207       return 0;
 208    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 209       return sws->have_vgpu10;
 210    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 211       return 1;
 212    case PIPE_CAP_TEXTURE_SWIZZLE:
 213       return 1;
 214    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 215       return 0;
 216    case PIPE_CAP_USER_VERTEX_BUFFERS:
 217       return 0;
 218    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 219       return 1;
 220    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 221       return 256;
 222
 223    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 224       {
 225          unsigned levels = SVGA_MAX_TEXTURE_LEVELS;
 226          if (sws->get_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH, &result))
 227             levels = MIN2(util_logbase2(result.u) + 1, levels);
 228          else
 229             levels = 12 /* 2048x2048 */;
 230          if (sws->get_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT, &result))
 231             levels = MIN2(util_logbase2(result.u) + 1, levels);
 232          else
 233             levels = 12 /* 2048x2048 */;
 234          return levels;
 235       }
 236
 237    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 238       if (!sws->get_cap(sws, SVGA3D_DEVCAP_MAX_VOLUME_EXTENT, &result))
 239          return 8;  /* max 128x128x128 */
 240       return MIN2(util_logbase2(result.u) + 1, SVGA_MAX_TEXTURE_LEVELS);
 241
 242    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 243       /*
 244        * No mechanism to query the host, and at least limited to 2048x2048 on
 245        * certain hardware.
 246        */
 247       return MIN2(screen->get_param(screen, PIPE_CAP_MAX_TEXTURE_2D_LEVELS),
 248                   12 /* 2048x2048 */);
 249
 250    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 251       return sws->have_vgpu10 ? SVGA3D_MAX_SURFACE_ARRAYSIZE : 0;
 252
 253    case PIPE_CAP_BLEND_EQUATION_SEPARATE: /* req. for GL 1.5 */
 254       return 1;
 255
 256    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 257       return 1;
 258    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 259       return sws->have_vgpu10;
 260    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 261       return 0;
 262    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 263       return !sws->have_vgpu10;
 264
 265    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 266       return 1; /* The color outputs of vertex shaders are not clamped */
 267    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 268       return 0; /* The driver can't clamp vertex colors */
 269    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 270       return 0; /* The driver can't clamp fragment colors */
 271
 272    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 273       return 1; /* expected for GL_ARB_framebuffer_object */
 274
 275    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 276       return sws->have_vgpu10 ? 330 : 120;
 277
 278    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 279       return 0;
 280
 281    case PIPE_CAP_SM3:
 282       return 1;
 283
 284    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 285    case PIPE_CAP_INDEP_BLEND_ENABLE:
 286    case PIPE_CAP_CONDITIONAL_RENDER:
 287    case PIPE_CAP_QUERY_TIMESTAMP:
 288    case PIPE_CAP_TGSI_INSTANCEID:
 289    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 290    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 291    case PIPE_CAP_FAKE_SW_MSAA:
 292       return sws->have_vgpu10;
 293
 294    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 295       return sws->have_vgpu10 ? SVGA3D_DX_MAX_SOTARGETS : 0;
 296    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 297       return sws->have_vgpu10 ? 4 : 0;
 298    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 299       return sws->have_vgpu10 ? SVGA3D_MAX_STREAMOUT_DECLS : 0;
 300    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 301    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 302       return 0;
 303    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 304       return svgascreen->ms_samples ? 1 : 0;
 305
 306    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 307       return SVGA3D_DX_MAX_RESOURCE_SIZE;
 308
 309    case PIPE_CAP_MIN_TEXEL_OFFSET:
 310       return sws->have_vgpu10 ? VGPU10_MIN_TEXEL_FETCH_OFFSET : 0;
 311    case PIPE_CAP_MAX_TEXEL_OFFSET:
 312       return sws->have_vgpu10 ? VGPU10_MAX_TEXEL_FETCH_OFFSET : 0;
 313
 314    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 315    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 316       return 0;
 317
 318    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 319       return sws->have_vgpu10 ? 256 : 0;
 320    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 321       return sws->have_vgpu10 ? 1024 : 0;
 322
 323    case PIPE_CAP_PRIMITIVE_RESTART:
 324       return 1; /* may be a sw fallback, depending on restart index */
 325
 326    case PIPE_CAP_GENERATE_MIPMAP:
 327       return sws->have_generate_mipmap_cmd;
 328
 329    /* Unsupported features */
 330    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 331    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 332    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 333    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 334    case PIPE_CAP_INDEP_BLEND_FUNC:
 335    case PIPE_CAP_TEXTURE_BARRIER:
 336    case PIPE_CAP_MAX_VERTEX_STREAMS:
 337    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 338    case PIPE_CAP_COMPUTE:
 339    case PIPE_CAP_START_INSTANCE:
 340    case PIPE_CAP_CUBE_MAP_ARRAY:
 341    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 342    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 343    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 344    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 345    case PIPE_CAP_TEXTURE_GATHER_SM5:
 346    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 347    case PIPE_CAP_TEXTURE_QUERY_LOD:
 348    case PIPE_CAP_SAMPLE_SHADING:
 349    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 350    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 351    case PIPE_CAP_DRAW_INDIRECT:
 352    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 353    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 354    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 355    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 356    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 357    case PIPE_CAP_CLIP_HALFZ:
 358    case PIPE_CAP_VERTEXID_NOBASE:
 359    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 360    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 361    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 362    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 363    case PIPE_CAP_INVALIDATE_BUFFER:
 364    case PIPE_CAP_STRING_MARKER:
 365    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 366    case PIPE_CAP_QUERY_MEMORY_INFO:
 367    case PIPE_CAP_PCI_GROUP:
 368    case PIPE_CAP_PCI_BUS:
 369    case PIPE_CAP_PCI_DEVICE:
 370    case PIPE_CAP_PCI_FUNCTION:
 371    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 372    case PIPE_CAP_NATIVE_FENCE_FD:
 373       return 0;
 374    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 375       return 64;
 376    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 377    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 378    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 379       return 1;  /* need 4-byte alignment for all offsets and strides */
 380    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 381       return 2048;
 382    case PIPE_CAP_MAX_VIEWPORTS:
 383       return 1;
 384    case PIPE_CAP_ENDIANNESS:
 385       return PIPE_ENDIAN_LITTLE;
 386
 387    case PIPE_CAP_VENDOR_ID:
 388       return 0x15ad; /* VMware Inc. */
 389    case PIPE_CAP_DEVICE_ID:
 390       return 0x0405; /* assume SVGA II */
 391    case PIPE_CAP_ACCELERATED:
 392       return 0; /* XXX: */
 393    case PIPE_CAP_VIDEO_MEMORY:
 394       /* XXX: Query the host ? */
 395       return 1;
 396    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 397       return sws->have_vgpu10;
 398    case PIPE_CAP_CLEAR_TEXTURE:
 399       return sws->have_vgpu10;
 400    case PIPE_CAP_UMA:
 401    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 402    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 403    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 404    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 405    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 406    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 407    case PIPE_CAP_TGSI_TXQS:
 408    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 409    case PIPE_CAP_SHAREABLE_SHADERS:
 410    case PIPE_CAP_DRAW_PARAMETERS:
 411    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 412    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 413    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 414    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 415    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 416    case PIPE_CAP_CULL_DISTANCE:
 417    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 418    case PIPE_CAP_TGSI_VOTE:
 419    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 420    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 421    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 422    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 423    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 424    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 425    case PIPE_CAP_TGSI_FS_FBFETCH:
 426    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 427    case PIPE_CAP_DOUBLES:
 428    case PIPE_CAP_INT64:
 429    case PIPE_CAP_INT64_DIVMOD:
 430       return 0;
 431    }
 432
 433    debug_printf("Unexpected PIPE_CAP_ query %u\n", param);
 434    return 0;
 435 }
 436
 437
 438 static int
 439 vgpu9_get_shader_param(struct pipe_screen *screen, unsigned shader,
 440                        enum pipe_shader_cap param)
 441 {
 442    struct svga_screen *svgascreen = svga_screen(screen);
 443    struct svga_winsys_screen *sws = svgascreen->sws;
 444    unsigned val;
 445
 446    assert(!sws->have_vgpu10);
 447
 448    switch (shader)
 449    {
 450    case PIPE_SHADER_FRAGMENT:
 451       switch (param)
 452       {
 453       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 454       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 455          return get_uint_cap(sws,
 456                              SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS,
 457                              512);
 458       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 459       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 460          return 512;
 461       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 462          return SVGA3D_MAX_NESTING_LEVEL;
 463       case PIPE_SHADER_CAP_MAX_INPUTS:
 464          return 10;
 465       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 466          return svgascreen->max_color_buffers;
 467       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 468          return 224 * sizeof(float[4]);
 469       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 470          return 1;
 471       case PIPE_SHADER_CAP_MAX_TEMPS:
 472          val = get_uint_cap(sws, SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS, 32);
 473          return MIN2(val, SVGA3D_TEMPREG_MAX);
 474       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 475          /*
 476           * Although PS 3.0 has some addressing abilities it can only represent
 477           * loops that can be statically determined and unrolled. Given we can
 478           * only handle a subset of the cases that the state tracker already
 479           * does it is better to defer loop unrolling to the state tracker.
 480           */
 481          return 0;
 482       case PIPE_SHADER_CAP_MAX_PREDS:
 483          return 1;
 484       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 485          return 0;
 486       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 487          return 0;
 488       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 489       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 490       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 491          return 0;
 492       case PIPE_SHADER_CAP_SUBROUTINES:
 493          return 0;
 494       case PIPE_SHADER_CAP_INTEGERS:
 495          return 0;
 496       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 497       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 498          return 16;
 499       case PIPE_SHADER_CAP_PREFERRED_IR:
 500          return PIPE_SHADER_IR_TGSI;
 501       case PIPE_SHADER_CAP_SUPPORTED_IRS:
 502          return 0;
 503       case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 504       case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 505       case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 506       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 507       case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 508       case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 509       case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 510          return 0;
 511       case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 512          return 32;
 513       }
 514       /* If we get here, we failed to handle a cap above */
 515       debug_printf("Unexpected fragment shader query %u\n", param);
 516       return 0;
 517    case PIPE_SHADER_VERTEX:
 518       switch (param)
 519       {
 520       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 521       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 522          return get_uint_cap(sws, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS,
 523                              512);
 524       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 525       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 526          /* XXX: until we have vertex texture support */
 527          return 0;
 528       case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 529          return SVGA3D_MAX_NESTING_LEVEL;
 530       case PIPE_SHADER_CAP_MAX_INPUTS:
 531          return 16;
 532       case PIPE_SHADER_CAP_MAX_OUTPUTS:
 533          return 10;
 534       case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 535          return 256 * sizeof(float[4]);
 536       case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 537          return 1;
 538       case PIPE_SHADER_CAP_MAX_TEMPS:
 539          val = get_uint_cap(sws, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS, 32);
 540          return MIN2(val, SVGA3D_TEMPREG_MAX);
 541       case PIPE_SHADER_CAP_MAX_PREDS:
 542          return 1;
 543       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 544          return 0;
 545       case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 546          return 0;
 547       case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 548       case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 549          return 1;
 550       case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 551          return 0;
 552       case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 553          return 1;
 554       case PIPE_SHADER_CAP_SUBROUTINES:
 555          return 0;
 556       case PIPE_SHADER_CAP_INTEGERS:
 557          return 0;
 558       case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 559       case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 560          return 0;
 561       case PIPE_SHADER_CAP_PREFERRED_IR:
 562          return PIPE_SHADER_IR_TGSI;
 563       case PIPE_SHADER_CAP_SUPPORTED_IRS:
 564          return 0;
 565       case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 566       case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 567       case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 568       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 569       case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 570       case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 571       case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 572          return 0;
 573       case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 574          return 32;
 575       }
 576       /* If we get here, we failed to handle a cap above */
 577       debug_printf("Unexpected vertex shader query %u\n", param);
 578       return 0;
 579    case PIPE_SHADER_GEOMETRY:
 580    case PIPE_SHADER_COMPUTE:
 581    case PIPE_SHADER_TESS_CTRL:
 582    case PIPE_SHADER_TESS_EVAL:
 583       /* no support for geometry, tess or compute shaders at this time */
 584       return 0;
 585    default:
 586       debug_printf("Unexpected shader type (%u) query\n", shader);
 587       return 0;
 588    }
 589    return 0;
 590 }
 591
 592
 593 static int
 594 vgpu10_get_shader_param(struct pipe_screen *screen, unsigned shader,
 595                         enum pipe_shader_cap param)
 596 {
 597    struct svga_screen *svgascreen = svga_screen(screen);
 598    struct svga_winsys_screen *sws = svgascreen->sws;
 599
 600    assert(sws->have_vgpu10);
 601    (void) sws;  /* silence unused var warnings in non-debug builds */
 602
 603    /* Only VS, GS, FS supported */
 604    if (shader != PIPE_SHADER_VERTEX &&
 605        shader != PIPE_SHADER_GEOMETRY &&
 606        shader != PIPE_SHADER_FRAGMENT) {
 607       return 0;
 608    }
 609
 610    /* NOTE: we do not query the device for any caps/limits at this time */
 611
 612    /* Generally the same limits for vertex, geometry and fragment shaders */
 613    switch (param) {
 614    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 615    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 616    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 617    case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 618       return 64 * 1024;
 619    case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 620       return 64;
 621    case PIPE_SHADER_CAP_MAX_INPUTS:
 622       if (shader == PIPE_SHADER_FRAGMENT)
 623          return VGPU10_MAX_FS_INPUTS;
 624       else if (shader == PIPE_SHADER_GEOMETRY)
 625          return VGPU10_MAX_GS_INPUTS;
 626       else
 627          return VGPU10_MAX_VS_INPUTS;
 628    case PIPE_SHADER_CAP_MAX_OUTPUTS:
 629       if (shader == PIPE_SHADER_FRAGMENT)
 630          return VGPU10_MAX_FS_OUTPUTS;
 631       else if (shader == PIPE_SHADER_GEOMETRY)
 632          return VGPU10_MAX_GS_OUTPUTS;
 633       else
 634          return VGPU10_MAX_VS_OUTPUTS;
 635    case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 636       return VGPU10_MAX_CONSTANT_BUFFER_ELEMENT_COUNT * sizeof(float[4]);
 637    case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 638       return svgascreen->max_const_buffers;
 639    case PIPE_SHADER_CAP_MAX_TEMPS:
 640       return VGPU10_MAX_TEMPS;
 641    case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 642    case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 643    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 644    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 645       return TRUE; /* XXX verify */
 646    case PIPE_SHADER_CAP_MAX_PREDS:
 647       return 0;
 648    case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 649    case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 650    case PIPE_SHADER_CAP_SUBROUTINES:
 651    case PIPE_SHADER_CAP_INTEGERS:
 652       return TRUE;
 653    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 654    case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 655       return SVGA3D_DX_MAX_SAMPLERS;
 656    case PIPE_SHADER_CAP_PREFERRED_IR:
 657       return PIPE_SHADER_IR_TGSI;
 658    case PIPE_SHADER_CAP_SUPPORTED_IRS:
 659          return 0;
 660    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 661    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 662    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 663    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 664    case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 665    case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 666    case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 667       return 0;
 668    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 669       return 32;
 670    default:
 671       debug_printf("Unexpected vgpu10 shader query %u\n", param);
 672       return 0;
 673    }
 674    return 0;
 675 }
 676
 677
 678 static int
 679 svga_get_shader_param(struct pipe_screen *screen, unsigned shader,
 680                       enum pipe_shader_cap param)
 681 {
 682    struct svga_screen *svgascreen = svga_screen(screen);
 683    struct svga_winsys_screen *sws = svgascreen->sws;
 684    if (sws->have_vgpu10) {
 685       return vgpu10_get_shader_param(screen, shader, param);
 686    }
 687    else {
 688       return vgpu9_get_shader_param(screen, shader, param);
 689    }
 690 }
 691
 692
 693 /**
 694  * Implement pipe_screen::is_format_supported().
 695  * \param bindings  bitmask of PIPE_BIND_x flags
 696  */
 697 static boolean
 698 svga_is_format_supported( struct pipe_screen *screen,
 699                           enum pipe_format format,
 700                           enum pipe_texture_target target,
 701                           unsigned sample_count,
 702                           unsigned bindings)
 703 {
 704    struct svga_screen *ss = svga_screen(screen);
 705    SVGA3dSurfaceFormat svga_format;
 706    SVGA3dSurfaceFormatCaps caps;
 707    SVGA3dSurfaceFormatCaps mask;
 708
 709    assert(bindings);
 710
 711    if (sample_count > 1) {
 712       /* In ms_samples, if bit N is set it means that we support
 713        * multisample with N+1 samples per pixel.
 714        */
 715       if ((ss->ms_samples & (1 << (sample_count - 1))) == 0) {
 716          return FALSE;
 717       }
 718    }
 719
 720    svga_format = svga_translate_format(ss, format, bindings);
 721    if (svga_format == SVGA3D_FORMAT_INVALID) {
 722       return FALSE;
 723    }
 724
 725    /* we don't support sRGB rendering into display targets */
 726    if (util_format_is_srgb(format) && (bindings & PIPE_BIND_DISPLAY_TARGET)) {
 727       return FALSE;
 728    }
 729
 730    /*
 731     * For VGPU10 vertex formats, skip querying host capabilities
 732     */
 733
 734    if (ss->sws->have_vgpu10 && (bindings & PIPE_BIND_VERTEX_BUFFER)) {
 735       SVGA3dSurfaceFormat svga_format;
 736       unsigned flags;
 737       svga_translate_vertex_format_vgpu10(format, &svga_format, &flags);
 738       return svga_format != SVGA3D_FORMAT_INVALID;
 739    }
 740
 741    /*
 742     * Override host capabilities, so that we end up with the same
 743     * visuals for all virtual hardware implementations.
 744     */
 745
 746    if (bindings & PIPE_BIND_DISPLAY_TARGET) {
 747       switch (svga_format) {
 748       case SVGA3D_A8R8G8B8:
 749       case SVGA3D_X8R8G8B8:
 750       case SVGA3D_R5G6B5:
 751          break;
 752
 753       /* VGPU10 formats */
 754       case SVGA3D_B8G8R8A8_UNORM:
 755       case SVGA3D_B8G8R8X8_UNORM:
 756       case SVGA3D_B5G6R5_UNORM:
 757          break;
 758
 759       /* Often unsupported/problematic. This means we end up with the same
 760        * visuals for all virtual hardware implementations.
 761        */
 762       case SVGA3D_A4R4G4B4:
 763       case SVGA3D_A1R5G5B5:
 764          return FALSE;
 765
 766       default:
 767          return FALSE;
 768       }
 769    }
 770
 771    /*
 772     * Query the host capabilities.
 773     */
 774
 775    svga_get_format_cap(ss, svga_format, &caps);
 776
 777    if (bindings & PIPE_BIND_RENDER_TARGET) {
 778       /* Check that the color surface is blendable, unless it's an
 779        * integer format.
 780        */
 781       if (!svga_format_is_integer(svga_format) &&
 782           (caps.value & SVGA3DFORMAT_OP_NOALPHABLEND)) {
 783          return FALSE;
 784       }
 785    }
 786
 787    mask.value = 0;
 788    if (bindings & PIPE_BIND_RENDER_TARGET) {
 789       mask.value |= SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET;
 790    }
 791    if (bindings & PIPE_BIND_DEPTH_STENCIL) {
 792       mask.value |= SVGA3DFORMAT_OP_ZSTENCIL;
 793    }
 794    if (bindings & PIPE_BIND_SAMPLER_VIEW) {
 795       mask.value |= SVGA3DFORMAT_OP_TEXTURE;
 796    }
 797
 798    if (target == PIPE_TEXTURE_CUBE) {
 799       mask.value |= SVGA3DFORMAT_OP_CUBETEXTURE;
 800    }
 801    else if (target == PIPE_TEXTURE_3D) {
 802       mask.value |= SVGA3DFORMAT_OP_VOLUMETEXTURE;
 803    }
 804
 805    return (caps.value & mask.value) == mask.value;
 806 }
 807
 808
 809 static void
 810 svga_fence_reference(struct pipe_screen *screen,
 811                      struct pipe_fence_handle **ptr,
 812                      struct pipe_fence_handle *fence)
 813 {
 814    struct svga_winsys_screen *sws = svga_screen(screen)->sws;
 815    sws->fence_reference(sws, ptr, fence);
 816 }
 817
 818
 819 static boolean
 820 svga_fence_finish(struct pipe_screen *screen,
 821                   struct pipe_context *ctx,
 822                   struct pipe_fence_handle *fence,
 823                   uint64_t timeout)
 824 {
 825    struct svga_winsys_screen *sws = svga_screen(screen)->sws;
 826    boolean retVal;
 827
 828    SVGA_STATS_TIME_PUSH(sws, SVGA_STATS_TIME_FENCEFINISH);
 829
 830    if (!timeout) {
 831       retVal = sws->fence_signalled(sws, fence, 0) == 0;
 832    }
 833    else {
 834       SVGA_DBG(DEBUG_DMA|DEBUG_PERF, "%s fence_ptr %p\n",
 835                __FUNCTION__, fence);
 836
 837       retVal = sws->fence_finish(sws, fence, 0) == 0;
 838    }
 839
 840    SVGA_STATS_TIME_POP(sws);
 841
 842    return retVal;
 843 }
 844
 845
 846 static int
 847 svga_get_driver_query_info(struct pipe_screen *screen,
 848                            unsigned index,
 849                            struct pipe_driver_query_info *info)
 850 {
 851 #define QUERY(NAME, ENUM, UNITS) \
 852    {NAME, ENUM, {0}, UNITS, PIPE_DRIVER_QUERY_RESULT_TYPE_AVERAGE, 0, 0x0}
 853
 854    static const struct pipe_driver_query_info queries[] = {
 855       /* per-frame counters */
 856       QUERY("num-draw-calls", SVGA_QUERY_NUM_DRAW_CALLS,
 857             PIPE_DRIVER_QUERY_TYPE_UINT64),
 858       QUERY("num-fallbacks", SVGA_QUERY_NUM_FALLBACKS,
 859             PIPE_DRIVER_QUERY_TYPE_UINT64),
 860       QUERY("num-flushes", SVGA_QUERY_NUM_FLUSHES,
 861             PIPE_DRIVER_QUERY_TYPE_UINT64),
 862       QUERY("num-validations", SVGA_QUERY_NUM_VALIDATIONS,
 863             PIPE_DRIVER_QUERY_TYPE_UINT64),
 864       QUERY("map-buffer-time", SVGA_QUERY_MAP_BUFFER_TIME,
 865             PIPE_DRIVER_QUERY_TYPE_MICROSECONDS),
 866       QUERY("num-buffers-mapped", SVGA_QUERY_NUM_BUFFERS_MAPPED,
 867             PIPE_DRIVER_QUERY_TYPE_UINT64),
 868       QUERY("num-textures-mapped", SVGA_QUERY_NUM_TEXTURES_MAPPED,
 869             PIPE_DRIVER_QUERY_TYPE_UINT64),
 870       QUERY("num-bytes-uploaded", SVGA_QUERY_NUM_BYTES_UPLOADED,
 871             PIPE_DRIVER_QUERY_TYPE_BYTES),
 872       QUERY("command-buffer-size", SVGA_QUERY_COMMAND_BUFFER_SIZE,
 873             PIPE_DRIVER_QUERY_TYPE_BYTES),
 874       QUERY("flush-time", SVGA_QUERY_FLUSH_TIME,
 875             PIPE_DRIVER_QUERY_TYPE_MICROSECONDS),
 876       QUERY("surface-write-flushes", SVGA_QUERY_SURFACE_WRITE_FLUSHES,
 877             PIPE_DRIVER_QUERY_TYPE_UINT64),
 878       QUERY("num-readbacks", SVGA_QUERY_NUM_READBACKS,
 879             PIPE_DRIVER_QUERY_TYPE_UINT64),
 880       QUERY("num-resource-updates", SVGA_QUERY_NUM_RESOURCE_UPDATES,
 881             PIPE_DRIVER_QUERY_TYPE_UINT64),
 882       QUERY("num-buffer-uploads", SVGA_QUERY_NUM_BUFFER_UPLOADS,
 883             PIPE_DRIVER_QUERY_TYPE_UINT64),
 884       QUERY("num-const-buf-updates", SVGA_QUERY_NUM_CONST_BUF_UPDATES,
 885             PIPE_DRIVER_QUERY_TYPE_UINT64),
 886       QUERY("num-const-updates", SVGA_QUERY_NUM_CONST_UPDATES,
 887             PIPE_DRIVER_QUERY_TYPE_UINT64),
 888
 889       /* running total counters */
 890       QUERY("memory-used", SVGA_QUERY_MEMORY_USED,
 891             PIPE_DRIVER_QUERY_TYPE_BYTES),
 892       QUERY("num-shaders", SVGA_QUERY_NUM_SHADERS,
 893             PIPE_DRIVER_QUERY_TYPE_UINT64),
 894       QUERY("num-resources", SVGA_QUERY_NUM_RESOURCES,
 895             PIPE_DRIVER_QUERY_TYPE_UINT64),
 896       QUERY("num-state-objects", SVGA_QUERY_NUM_STATE_OBJECTS,
 897             PIPE_DRIVER_QUERY_TYPE_UINT64),
 898       QUERY("num-surface-views", SVGA_QUERY_NUM_SURFACE_VIEWS,
 899             PIPE_DRIVER_QUERY_TYPE_UINT64),
 900       QUERY("num-generate-mipmap", SVGA_QUERY_NUM_GENERATE_MIPMAP,
 901             PIPE_DRIVER_QUERY_TYPE_UINT64),
 902    };
 903 #undef QUERY
 904
 905    if (!info)
 906       return ARRAY_SIZE(queries);
 907
 908    if (index >= ARRAY_SIZE(queries))
 909       return 0;
 910
 911    *info = queries[index];
 912    return 1;
 913 }
 914
 915
 916 static void
 917 svga_destroy_screen( struct pipe_screen *screen )
 918 {
 919    struct svga_screen *svgascreen = svga_screen(screen);
 920
 921    svga_screen_cache_cleanup(svgascreen);
 922
 923    pipe_mutex_destroy(svgascreen->swc_mutex);
 924    pipe_mutex_destroy(svgascreen->tex_mutex);
 925
 926    svgascreen->sws->destroy(svgascreen->sws);
 927
 928    FREE(svgascreen);
 929 }
 930
 931
 932 /**
 933  * Create a new svga_screen object
 934  */
 935 struct pipe_screen *
 936 svga_screen_create(struct svga_winsys_screen *sws)
 937 {
 938    struct svga_screen *svgascreen;
 939    struct pipe_screen *screen;
 940
 941 #ifdef DEBUG
 942    SVGA_DEBUG = debug_get_flags_option("SVGA_DEBUG", svga_debug_flags, 0 );
 943 #endif
 944
 945    svgascreen = CALLOC_STRUCT(svga_screen);
 946    if (!svgascreen)
 947       goto error1;
 948
 949    svgascreen->debug.force_level_surface_view =
 950       debug_get_bool_option("SVGA_FORCE_LEVEL_SURFACE_VIEW", FALSE);
 951    svgascreen->debug.force_surface_view =
 952       debug_get_bool_option("SVGA_FORCE_SURFACE_VIEW", FALSE);
 953    svgascreen->debug.force_sampler_view =
 954       debug_get_bool_option("SVGA_FORCE_SAMPLER_VIEW", FALSE);
 955    svgascreen->debug.no_surface_view =
 956       debug_get_bool_option("SVGA_NO_SURFACE_VIEW", FALSE);
 957    svgascreen->debug.no_sampler_view =
 958       debug_get_bool_option("SVGA_NO_SAMPLER_VIEW", FALSE);
 959    svgascreen->debug.no_cache_index_buffers =
 960       debug_get_bool_option("SVGA_NO_CACHE_INDEX_BUFFERS", FALSE);
 961
 962    screen = &svgascreen->screen;
 963
 964    screen->destroy = svga_destroy_screen;
 965    screen->get_name = svga_get_name;
 966    screen->get_vendor = svga_get_vendor;
 967    screen->get_device_vendor = svga_get_vendor; // TODO actual device vendor
 968    screen->get_param = svga_get_param;
 969    screen->get_shader_param = svga_get_shader_param;
 970    screen->get_paramf = svga_get_paramf;
 971    screen->get_timestamp = NULL;
 972    screen->is_format_supported = svga_is_format_supported;
 973    screen->context_create = svga_context_create;
 974    screen->fence_reference = svga_fence_reference;
 975    screen->fence_finish = svga_fence_finish;
 976    screen->get_driver_query_info = svga_get_driver_query_info;
 977    svgascreen->sws = sws;
 978
 979    svga_init_screen_resource_functions(svgascreen);
 980
 981    if (sws->get_hw_version) {
 982       svgascreen->hw_version = sws->get_hw_version(sws);
 983    } else {
 984       svgascreen->hw_version = SVGA3D_HWVERSION_WS65_B1;
 985    }
 986
 987    /*
 988     * The D16, D24X8, and D24S8 formats always do an implicit shadow compare
 989     * when sampled from, where as the DF16, DF24, and D24S8_INT do not.  So
 990     * we prefer the later when available.
 991     *
 992     * This mimics hardware vendors extensions for D3D depth sampling. See also
 993     * http://aras-p.info/texts/D3D9GPUHacks.html
 994     */
 995
 996    {
 997       boolean has_df16, has_df24, has_d24s8_int;
 998       SVGA3dSurfaceFormatCaps caps;
 999       SVGA3dSurfaceFormatCaps mask;
1000       mask.value = 0;
1001       mask.zStencil = 1;
1002       mask.texture = 1;
1003
1004       svgascreen->depth.z16 = SVGA3D_Z_D16;
1005       svgascreen->depth.x8z24 = SVGA3D_Z_D24X8;
1006       svgascreen->depth.s8z24 = SVGA3D_Z_D24S8;
1007
1008       svga_get_format_cap(svgascreen, SVGA3D_Z_DF16, &caps);
1009       has_df16 = (caps.value & mask.value) == mask.value;
1010
1011       svga_get_format_cap(svgascreen, SVGA3D_Z_DF24, &caps);
1012       has_df24 = (caps.value & mask.value) == mask.value;
1013
1014       svga_get_format_cap(svgascreen, SVGA3D_Z_D24S8_INT, &caps);
1015       has_d24s8_int = (caps.value & mask.value) == mask.value;
1016
1017       /* XXX: We might want some other logic here.
1018        * Like if we only have d24s8_int we should
1019        * emulate the other formats with that.
1020        */
1021       if (has_df16) {
1022          svgascreen->depth.z16 = SVGA3D_Z_DF16;
1023       }
1024       if (has_df24) {
1025          svgascreen->depth.x8z24 = SVGA3D_Z_DF24;
1026       }
1027       if (has_d24s8_int) {
1028          svgascreen->depth.s8z24 = SVGA3D_Z_D24S8_INT;
1029       }
1030    }
1031
1032    /* Query device caps
1033     */
1034    if (sws->have_vgpu10) {
1035       svgascreen->haveProvokingVertex
1036          = get_bool_cap(sws, SVGA3D_DEVCAP_DX_PROVOKING_VERTEX, FALSE);
1037       svgascreen->haveLineSmooth = TRUE;
1038       svgascreen->maxPointSize = 80.0F;
1039       svgascreen->max_color_buffers = SVGA3D_DX_MAX_RENDER_TARGETS;
1040
1041       /* Multisample samples per pixel */
1042       if (debug_get_bool_option("SVGA_MSAA", TRUE)) {
1043          svgascreen->ms_samples =
1044             get_uint_cap(sws, SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES, 0);
1045       }
1046
1047       /* Maximum number of constant buffers */
1048       svgascreen->max_const_buffers =
1049          get_uint_cap(sws, SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS, 1);
1050       assert(svgascreen->max_const_buffers <= SVGA_MAX_CONST_BUFS);
1051    }
1052    else {
1053       /* VGPU9 */
1054       unsigned vs_ver = get_uint_cap(sws, SVGA3D_DEVCAP_VERTEX_SHADER_VERSION,
1055                                      SVGA3DVSVERSION_NONE);
1056       unsigned fs_ver = get_uint_cap(sws, SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION,
1057                                      SVGA3DPSVERSION_NONE);
1058
1059       /* we require Shader model 3.0 or later */
1060       if (fs_ver < SVGA3DPSVERSION_30 || vs_ver < SVGA3DVSVERSION_30) {
1061          goto error2;
1062       }
1063
1064       svgascreen->haveProvokingVertex = FALSE;
1065
1066       svgascreen->haveLineSmooth =
1067          get_bool_cap(sws, SVGA3D_DEVCAP_LINE_AA, FALSE);
1068
1069       svgascreen->maxPointSize =
1070          get_float_cap(sws, SVGA3D_DEVCAP_MAX_POINT_SIZE, 1.0f);
1071       /* Keep this to a reasonable size to avoid failures in conform/pntaa.c */
1072       svgascreen->maxPointSize = MIN2(svgascreen->maxPointSize, 80.0f);
1073
1074       /* The SVGA3D device always supports 4 targets at this time, regardless
1075        * of what querying SVGA3D_DEVCAP_MAX_RENDER_TARGETS might return.
1076        */
1077       svgascreen->max_color_buffers = 4;
1078
1079       /* Only support one constant buffer
1080        */
1081       svgascreen->max_const_buffers = 1;
1082
1083       /* No multisampling */
1084       svgascreen->ms_samples = 0;
1085    }
1086
1087    /* common VGPU9 / VGPU10 caps */
1088    svgascreen->haveLineStipple =
1089       get_bool_cap(sws, SVGA3D_DEVCAP_LINE_STIPPLE, FALSE);
1090
1091    svgascreen->maxLineWidth =
1092       get_float_cap(sws, SVGA3D_DEVCAP_MAX_LINE_WIDTH, 1.0f);
1093
1094    svgascreen->maxLineWidthAA =
1095       get_float_cap(sws, SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH, 1.0f);
1096
1097    if (0) {
1098       debug_printf("svga: haveProvokingVertex %u\n",
1099                    svgascreen->haveProvokingVertex);
1100       debug_printf("svga: haveLineStip %u  "
1101                    "haveLineSmooth %u  maxLineWidth %f\n",
1102                    svgascreen->haveLineStipple, svgascreen->haveLineSmooth,
1103                    svgascreen->maxLineWidth);
1104       debug_printf("svga: maxPointSize %g\n", svgascreen->maxPointSize);
1105       debug_printf("svga: msaa samples mask: 0x%x\n", svgascreen->ms_samples);
1106    }
1107
1108    pipe_mutex_init(svgascreen->tex_mutex);
1109    pipe_mutex_init(svgascreen->swc_mutex);
1110
1111    svga_screen_cache_init(svgascreen);
1112
1113    return screen;
1114 error2:
1115    FREE(svgascreen);
1116 error1:
1117    return NULL;
1118 }
1119
1120 struct svga_winsys_screen *
1121 svga_winsys_screen(struct pipe_screen *screen)
1122 {
1123    return svga_screen(screen)->sws;
1124 }
1125
1126 #ifdef DEBUG
1127 struct svga_screen *
1128 svga_screen(struct pipe_screen *screen)
1129 {
1130    assert(screen);
1131    assert(screen->destroy == svga_destroy_screen);
1132    return (struct svga_screen *)screen;
1133 }
1134 #endif