1 /**********************************************************
2 * Copyright 2008-2009 VMware, Inc. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 **********************************************************/
28 #include "pipe/p_state.h"
29 #include "pipe/p_defines.h"
30 #include "pipe/p_inlines.h"
31 #include "pipe/p_thread.h"
32 #include "util/u_math.h"
33 #include "util/u_memory.h"
35 #include "svga_context.h"
36 #include "svga_screen.h"
37 #include "svga_screen_buffer.h"
38 #include "svga_winsys.h"
39 #include "svga_debug.h"
43 * Vertex and index buffers have to be treated slightly differently from
44 * regular guest memory regions because the SVGA device sees them as
45 * surfaces, and the state tracker can create/destroy without the pipe
46 * driver, therefore we must do the uploads from the vws.
49 svga_buffer_needs_hw_storage(unsigned usage
)
51 return usage
& (PIPE_BUFFER_USAGE_VERTEX
| PIPE_BUFFER_USAGE_INDEX
);
55 static INLINE
enum pipe_error
56 svga_buffer_create_host_surface(struct svga_screen
*ss
,
57 struct svga_buffer
*sbuf
)
62 sbuf
->key
.format
= SVGA3D_BUFFER
;
63 if(sbuf
->base
.usage
& PIPE_BUFFER_USAGE_VERTEX
)
64 sbuf
->key
.flags
|= SVGA3D_SURFACE_HINT_VERTEXBUFFER
;
65 if(sbuf
->base
.usage
& PIPE_BUFFER_USAGE_INDEX
)
66 sbuf
->key
.flags
|= SVGA3D_SURFACE_HINT_INDEXBUFFER
;
68 sbuf
->key
.size
.width
= sbuf
->base
.size
;
69 sbuf
->key
.size
.height
= 1;
70 sbuf
->key
.size
.depth
= 1;
72 sbuf
->key
.numFaces
= 1;
73 sbuf
->key
.numMipLevels
= 1;
74 sbuf
->key
.cachable
= 1;
76 SVGA_DBG(DEBUG_DMA
, "surface_create for buffer sz %d\n", sbuf
->base
.size
);
78 sbuf
->handle
= svga_screen_surface_create(ss
, &sbuf
->key
);
80 return PIPE_ERROR_OUT_OF_MEMORY
;
82 /* Always set the discard flag on the first time the buffer is written
83 * as svga_screen_surface_create might have passed a recycled host
86 sbuf
->hw
.flags
.discard
= TRUE
;
88 SVGA_DBG(DEBUG_DMA
, " --> got sid %p sz %d (buffer)\n", sbuf
->handle
, sbuf
->base
.size
);
96 svga_buffer_destroy_host_surface(struct svga_screen
*ss
,
97 struct svga_buffer
*sbuf
)
100 SVGA_DBG(DEBUG_DMA
, " ungrab sid %p sz %d\n", sbuf
->handle
, sbuf
->base
.size
);
101 svga_screen_surface_destroy(ss
, &sbuf
->key
, &sbuf
->handle
);
107 svga_buffer_destroy_hw_storage(struct svga_screen
*ss
, struct svga_buffer
*sbuf
)
109 struct svga_winsys_screen
*sws
= ss
->sws
;
111 assert(!sbuf
->map
.count
);
112 assert(sbuf
->hw
.buf
);
114 sws
->buffer_destroy(sws
, sbuf
->hw
.buf
);
116 assert(sbuf
->head
.prev
&& sbuf
->head
.next
);
117 LIST_DEL(&sbuf
->head
);
119 sbuf
->head
.next
= sbuf
->head
.prev
= NULL
;
124 static INLINE
enum pipe_error
125 svga_buffer_backup(struct svga_screen
*ss
, struct svga_buffer
*sbuf
)
127 if (sbuf
->hw
.buf
&& sbuf
->hw
.num_ranges
) {
131 sbuf
->swbuf
= align_malloc(sbuf
->base
.size
, sbuf
->base
.alignment
);
133 return PIPE_ERROR_OUT_OF_MEMORY
;
135 src
= ss
->sws
->buffer_map(ss
->sws
, sbuf
->hw
.buf
,
136 PIPE_BUFFER_USAGE_CPU_READ
);
140 memcpy(sbuf
->swbuf
, src
, sbuf
->base
.size
);
141 ss
->sws
->buffer_unmap(ss
->sws
, sbuf
->hw
.buf
);
148 * Try to make GMR space available by freeing the hardware storage of
152 svga_buffer_free_cached_hw_storage(struct svga_screen
*ss
)
154 struct list_head
*curr
;
155 struct svga_buffer
*sbuf
;
156 enum pipe_error ret
= PIPE_OK
;
158 curr
= ss
->cached_buffers
.prev
;
160 /* free the least recently used buffer's hw storage which is not mapped */
162 if(curr
== &ss
->cached_buffers
)
165 sbuf
= LIST_ENTRY(struct svga_buffer
, curr
, head
);
168 if (sbuf
->map
.count
== 0)
169 ret
= svga_buffer_backup(ss
, sbuf
);
171 } while(sbuf
->map
.count
!= 0 || ret
!= PIPE_OK
);
173 svga_buffer_destroy_hw_storage(ss
, sbuf
);
178 struct svga_winsys_buffer
*
179 svga_winsys_buffer_create( struct svga_screen
*ss
,
184 struct svga_winsys_screen
*sws
= ss
->sws
;
185 struct svga_winsys_buffer
*buf
;
188 buf
= sws
->buffer_create(sws
, alignment
, usage
, size
);
191 SVGA_DBG(DEBUG_DMA
|DEBUG_PERF
, "flushing screen to find %d bytes GMR\n",
194 /* Try flushing all pending DMAs */
195 svga_screen_flush(ss
, NULL
);
196 buf
= sws
->buffer_create(sws
, alignment
, usage
, size
);
198 SVGA_DBG(DEBUG_DMA
|DEBUG_PERF
, "evicting buffers to find %d bytes GMR\n",
201 /* Try evicing all buffer storage */
202 while(!buf
&& svga_buffer_free_cached_hw_storage(ss
))
203 buf
= sws
->buffer_create(sws
, alignment
, usage
, size
);
211 * Allocate DMA'ble storage for the buffer.
213 * Called before mapping a buffer.
215 static INLINE
enum pipe_error
216 svga_buffer_create_hw_storage(struct svga_screen
*ss
,
217 struct svga_buffer
*sbuf
)
220 unsigned alignment
= sbuf
->base
.alignment
;
222 unsigned size
= sbuf
->base
.size
;
224 sbuf
->hw
.buf
= svga_winsys_buffer_create(ss
, alignment
, usage
, size
);
226 return PIPE_ERROR_OUT_OF_MEMORY
;
228 assert(!sbuf
->needs_flush
);
229 assert(!sbuf
->head
.prev
&& !sbuf
->head
.next
);
230 LIST_ADD(&sbuf
->head
, &ss
->cached_buffers
);
238 * Variant of SVGA3D_BufferDMA which leaves the copy box temporarily in blank.
240 static enum pipe_error
241 svga_buffer_upload_command(struct svga_context
*svga
,
242 struct svga_buffer
*sbuf
)
244 struct svga_winsys_context
*swc
= svga
->swc
;
245 struct svga_winsys_buffer
*guest
= sbuf
->hw
.buf
;
246 struct svga_winsys_surface
*host
= sbuf
->handle
;
247 SVGA3dTransferType transfer
= SVGA3D_WRITE_HOST_VRAM
;
248 SVGA3dSurfaceDMAFlags flags
= sbuf
->hw
.flags
;
249 SVGA3dCmdSurfaceDMA
*cmd
;
250 uint32 numBoxes
= sbuf
->hw
.num_ranges
;
251 SVGA3dCopyBox
*boxes
;
252 SVGA3dCmdSurfaceDMASuffix
*pSuffix
;
253 unsigned region_flags
;
254 unsigned surface_flags
;
255 struct pipe_buffer
*dummy
;
257 if(transfer
== SVGA3D_WRITE_HOST_VRAM
) {
258 region_flags
= PIPE_BUFFER_USAGE_GPU_READ
;
259 surface_flags
= PIPE_BUFFER_USAGE_GPU_WRITE
;
261 else if(transfer
== SVGA3D_READ_HOST_VRAM
) {
262 region_flags
= PIPE_BUFFER_USAGE_GPU_WRITE
;
263 surface_flags
= PIPE_BUFFER_USAGE_GPU_READ
;
267 return PIPE_ERROR_BAD_INPUT
;
272 cmd
= SVGA3D_FIFOReserve(swc
,
273 SVGA_3D_CMD_SURFACE_DMA
,
274 sizeof *cmd
+ numBoxes
* sizeof *boxes
+ sizeof *pSuffix
,
277 return PIPE_ERROR_OUT_OF_MEMORY
;
279 swc
->region_relocation(swc
, &cmd
->guest
.ptr
, guest
, 0, region_flags
);
280 cmd
->guest
.pitch
= 0;
282 swc
->surface_relocation(swc
, &cmd
->host
.sid
, host
, surface_flags
);
284 cmd
->host
.mipmap
= 0;
286 cmd
->transfer
= transfer
;
288 sbuf
->hw
.boxes
= (SVGA3dCopyBox
*)&cmd
[1];
289 sbuf
->hw
.svga
= svga
;
291 /* Increment reference count */
293 pipe_buffer_reference(&dummy
, &sbuf
->base
);
295 pSuffix
= (SVGA3dCmdSurfaceDMASuffix
*)((uint8_t*)cmd
+ sizeof *cmd
+ numBoxes
* sizeof *boxes
);
296 pSuffix
->suffixSize
= sizeof *pSuffix
;
297 pSuffix
->maximumOffset
= sbuf
->base
.size
;
298 pSuffix
->flags
= flags
;
307 * Patch up the upload DMA command reserved by svga_buffer_upload_command
308 * with the final ranges.
311 svga_buffer_upload_flush(struct svga_context
*svga
,
312 struct svga_buffer
*sbuf
)
314 struct svga_screen
*ss
= svga_screen(svga
->pipe
.screen
);
315 SVGA3dCopyBox
*boxes
;
318 assert(sbuf
->handle
);
319 assert(sbuf
->hw
.buf
);
320 assert(sbuf
->hw
.num_ranges
);
321 assert(sbuf
->hw
.svga
== svga
);
322 assert(sbuf
->hw
.boxes
);
325 * Patch the DMA command with the final copy box.
328 SVGA_DBG(DEBUG_DMA
, "dma to sid %p\n", sbuf
->handle
);
330 boxes
= sbuf
->hw
.boxes
;
331 for(i
= 0; i
< sbuf
->hw
.num_ranges
; ++i
) {
332 SVGA_DBG(DEBUG_DMA
, " bytes %u - %u\n",
333 sbuf
->hw
.ranges
[i
].start
, sbuf
->hw
.ranges
[i
].end
);
335 boxes
[i
].x
= sbuf
->hw
.ranges
[i
].start
;
338 boxes
[i
].w
= sbuf
->hw
.ranges
[i
].end
- sbuf
->hw
.ranges
[i
].start
;
341 boxes
[i
].srcx
= sbuf
->hw
.ranges
[i
].start
;
346 sbuf
->hw
.num_ranges
= 0;
347 memset(&sbuf
->hw
.flags
, 0, sizeof sbuf
->hw
.flags
);
349 assert(sbuf
->head
.prev
&& sbuf
->head
.next
);
350 LIST_DEL(&sbuf
->head
);
351 sbuf
->needs_flush
= FALSE
;
352 /* XXX: do we care about cached_buffers any more ?*/
353 LIST_ADD(&sbuf
->head
, &ss
->cached_buffers
);
355 sbuf
->hw
.svga
= NULL
;
356 sbuf
->hw
.boxes
= NULL
;
358 sbuf
->host_written
= TRUE
;
360 /* Decrement reference count */
361 pipe_buffer_reference((struct pipe_buffer
**)&sbuf
, NULL
);
366 * Queue a DMA upload of a range of this buffer to the host.
368 * This function only notes the range down. It doesn't actually emit a DMA
369 * upload command. That only happens when a context tries to refer to this
370 * buffer, and the DMA upload command is added to that context's command buffer.
372 * We try to lump as many contiguous DMA transfers together as possible.
375 svga_buffer_upload_queue(struct svga_buffer
*sbuf
,
381 assert(sbuf
->hw
.buf
);
385 * Try to grow one of the ranges.
387 * Note that it is not this function task to care about overlapping ranges,
388 * as the GMR was already given so it is too late to do anything. Situations
389 * where overlapping ranges may pose a problem should be detected via
390 * pipe_context::is_buffer_referenced and the context that refers to the
391 * buffer should be flushed.
394 for(i
= 0; i
< sbuf
->hw
.num_ranges
; ++i
) {
395 if(start
<= sbuf
->hw
.ranges
[i
].end
&& sbuf
->hw
.ranges
[i
].start
<= end
) {
396 sbuf
->hw
.ranges
[i
].start
= MIN2(sbuf
->hw
.ranges
[i
].start
, start
);
397 sbuf
->hw
.ranges
[i
].end
= MAX2(sbuf
->hw
.ranges
[i
].end
, end
);
403 * We cannot add a new range to an existing DMA command, so patch-up the
404 * pending DMA upload and start clean.
407 if(sbuf
->needs_flush
)
408 svga_buffer_upload_flush(sbuf
->hw
.svga
, sbuf
);
410 assert(!sbuf
->needs_flush
);
411 assert(!sbuf
->hw
.svga
);
412 assert(!sbuf
->hw
.boxes
);
418 sbuf
->hw
.ranges
[sbuf
->hw
.num_ranges
].start
= start
;
419 sbuf
->hw
.ranges
[sbuf
->hw
.num_ranges
].end
= end
;
420 ++sbuf
->hw
.num_ranges
;
425 svga_buffer_map_range( struct pipe_screen
*screen
,
426 struct pipe_buffer
*buf
,
427 unsigned offset
, unsigned length
,
430 struct svga_screen
*ss
= svga_screen(screen
);
431 struct svga_winsys_screen
*sws
= ss
->sws
;
432 struct svga_buffer
*sbuf
= svga_buffer( buf
);
436 /* User/malloc buffer */
441 if(svga_buffer_create_hw_storage(ss
, sbuf
) != PIPE_OK
)
444 /* Populate the hardware storage if the host surface pre-existed */
445 if(sbuf
->host_written
) {
446 SVGA3dSurfaceDMAFlags flags
;
448 struct pipe_fence_handle
*fence
= NULL
;
450 assert(sbuf
->handle
);
452 SVGA_DBG(DEBUG_DMA
|DEBUG_PERF
, "dma from sid %p (buffer), bytes %u - %u\n",
453 sbuf
->handle
, 0, sbuf
->base
.size
);
455 memset(&flags
, 0, sizeof flags
);
457 ret
= SVGA3D_BufferDMA(ss
->swc
,
460 SVGA3D_READ_HOST_VRAM
,
465 ss
->swc
->flush(ss
->swc
, NULL
);
467 ret
= SVGA3D_BufferDMA(ss
->swc
,
470 SVGA3D_READ_HOST_VRAM
,
474 assert(ret
== PIPE_OK
);
477 ss
->swc
->flush(ss
->swc
, &fence
);
478 sws
->fence_finish(sws
, fence
, 0);
479 sws
->fence_reference(sws
, &fence
, NULL
);
483 if(!(usage
& PIPE_BUFFER_USAGE_DISCARD
) && !sbuf
->needs_flush
) {
484 /* We already had the hardware storage but we would have to issue
485 * a download if we hadn't, so move the buffer to the begginning
488 assert(sbuf
->head
.prev
&& sbuf
->head
.next
);
489 LIST_DEL(&sbuf
->head
);
490 LIST_ADD(&sbuf
->head
, &ss
->cached_buffers
);
494 map
= sws
->buffer_map(sws
, sbuf
->hw
.buf
, usage
);
498 pipe_mutex_lock(ss
->swc_mutex
);
502 if (usage
& PIPE_BUFFER_USAGE_CPU_WRITE
) {
503 assert(sbuf
->map
.count
<= 1);
504 sbuf
->map
.writing
= TRUE
;
505 if (usage
& PIPE_BUFFER_USAGE_FLUSH_EXPLICIT
)
506 sbuf
->map
.flush_explicit
= TRUE
;
509 pipe_mutex_unlock(ss
->swc_mutex
);
516 svga_buffer_flush_mapped_range( struct pipe_screen
*screen
,
517 struct pipe_buffer
*buf
,
518 unsigned offset
, unsigned length
)
520 struct svga_buffer
*sbuf
= svga_buffer( buf
);
521 struct svga_screen
*ss
= svga_screen(screen
);
523 pipe_mutex_lock(ss
->swc_mutex
);
524 assert(sbuf
->map
.writing
);
525 if(sbuf
->map
.writing
) {
526 assert(sbuf
->map
.flush_explicit
);
528 svga_buffer_upload_queue(sbuf
, offset
, offset
+ length
);
530 pipe_mutex_unlock(ss
->swc_mutex
);
534 svga_buffer_unmap( struct pipe_screen
*screen
,
535 struct pipe_buffer
*buf
)
537 struct svga_screen
*ss
= svga_screen(screen
);
538 struct svga_winsys_screen
*sws
= ss
->sws
;
539 struct svga_buffer
*sbuf
= svga_buffer( buf
);
541 pipe_mutex_lock(ss
->swc_mutex
);
543 assert(sbuf
->map
.count
);
548 sws
->buffer_unmap(sws
, sbuf
->hw
.buf
);
550 if(sbuf
->map
.writing
) {
551 if(!sbuf
->map
.flush_explicit
) {
552 /* No mapped range was flushed -- flush the whole buffer */
553 SVGA_DBG(DEBUG_DMA
, "flushing the whole buffer\n");
556 svga_buffer_upload_queue(sbuf
, 0, sbuf
->base
.size
);
559 sbuf
->map
.writing
= FALSE
;
560 sbuf
->map
.flush_explicit
= FALSE
;
563 pipe_mutex_unlock(ss
->swc_mutex
);
567 svga_buffer_destroy( struct pipe_buffer
*buf
)
569 struct svga_screen
*ss
= svga_screen(buf
->screen
);
570 struct svga_buffer
*sbuf
= svga_buffer( buf
);
572 assert(!p_atomic_read(&buf
->reference
.count
));
574 assert(!sbuf
->needs_flush
);
577 SVGA_DBG(DEBUG_DMA
, "release sid %p sz %d\n", sbuf
->handle
, sbuf
->base
.size
);
578 svga_screen_surface_destroy(ss
, &sbuf
->key
, &sbuf
->handle
);
582 svga_buffer_destroy_hw_storage(ss
, sbuf
);
584 if(sbuf
->swbuf
&& !sbuf
->user
)
585 align_free(sbuf
->swbuf
);
590 static struct pipe_buffer
*
591 svga_buffer_create(struct pipe_screen
*screen
,
596 struct svga_screen
*ss
= svga_screen(screen
);
597 struct svga_buffer
*sbuf
;
602 sbuf
= CALLOC_STRUCT(svga_buffer
);
606 sbuf
->magic
= SVGA_BUFFER_MAGIC
;
608 pipe_reference_init(&sbuf
->base
.reference
, 1);
609 sbuf
->base
.screen
= screen
;
610 sbuf
->base
.alignment
= alignment
;
611 sbuf
->base
.usage
= usage
;
612 sbuf
->base
.size
= size
;
614 if(svga_buffer_needs_hw_storage(usage
)) {
615 if(svga_buffer_create_host_surface(ss
, sbuf
) != PIPE_OK
)
619 if(alignment
< sizeof(void*))
620 alignment
= sizeof(void*);
622 usage
|= PIPE_BUFFER_USAGE_CPU_READ_WRITE
;
624 sbuf
->swbuf
= align_malloc(size
, alignment
);
637 static struct pipe_buffer
*
638 svga_user_buffer_create(struct pipe_screen
*screen
,
642 struct svga_buffer
*sbuf
;
644 sbuf
= CALLOC_STRUCT(svga_buffer
);
648 sbuf
->magic
= SVGA_BUFFER_MAGIC
;
653 pipe_reference_init(&sbuf
->base
.reference
, 1);
654 sbuf
->base
.screen
= screen
;
655 sbuf
->base
.alignment
= 1;
656 sbuf
->base
.usage
= 0;
657 sbuf
->base
.size
= bytes
;
667 svga_screen_init_buffer_functions(struct pipe_screen
*screen
)
669 screen
->buffer_create
= svga_buffer_create
;
670 screen
->user_buffer_create
= svga_user_buffer_create
;
671 screen
->buffer_map_range
= svga_buffer_map_range
;
672 screen
->buffer_flush_mapped_range
= svga_buffer_flush_mapped_range
;
673 screen
->buffer_unmap
= svga_buffer_unmap
;
674 screen
->buffer_destroy
= svga_buffer_destroy
;
679 * Copy the contents of the user buffer / malloc buffer to a hardware buffer.
681 static INLINE
enum pipe_error
682 svga_buffer_update_hw(struct svga_screen
*ss
, struct svga_buffer
*sbuf
)
692 ret
= svga_buffer_create_hw_storage(ss
, sbuf
);
693 assert(ret
== PIPE_OK
);
697 pipe_mutex_lock(ss
->swc_mutex
);
698 map
= ss
->sws
->buffer_map(ss
->sws
, sbuf
->hw
.buf
, PIPE_BUFFER_USAGE_CPU_WRITE
);
701 pipe_mutex_unlock(ss
->swc_mutex
);
702 return PIPE_ERROR_OUT_OF_MEMORY
;
705 memcpy(map
, sbuf
->swbuf
, sbuf
->base
.size
);
706 ss
->sws
->buffer_unmap(ss
->sws
, sbuf
->hw
.buf
);
708 /* This user/malloc buffer is now indistinguishable from a gpu buffer */
709 assert(!sbuf
->map
.count
);
710 if(!sbuf
->map
.count
) {
714 align_free(sbuf
->swbuf
);
718 svga_buffer_upload_queue(sbuf
, 0, sbuf
->base
.size
);
721 pipe_mutex_unlock(ss
->swc_mutex
);
726 struct svga_winsys_surface
*
727 svga_buffer_handle(struct svga_context
*svga
,
728 struct pipe_buffer
*buf
)
730 struct pipe_screen
*screen
= svga
->pipe
.screen
;
731 struct svga_screen
*ss
= svga_screen(screen
);
732 struct svga_buffer
*sbuf
;
738 sbuf
= svga_buffer(buf
);
740 assert(!sbuf
->map
.count
);
743 ret
= svga_buffer_create_host_surface(ss
, sbuf
);
747 ret
= svga_buffer_update_hw(ss
, sbuf
);
752 if(!sbuf
->needs_flush
&& sbuf
->hw
.num_ranges
) {
753 /* Queue the buffer for flushing */
754 ret
= svga_buffer_upload_command(svga
, sbuf
);
756 /* XXX: Should probably have a richer return value */
759 assert(sbuf
->hw
.svga
== svga
);
761 sbuf
->needs_flush
= TRUE
;
762 assert(sbuf
->head
.prev
&& sbuf
->head
.next
);
763 LIST_DEL(&sbuf
->head
);
764 LIST_ADDTAIL(&sbuf
->head
, &svga
->dirty_buffers
);
771 svga_screen_buffer_wrap_surface(struct pipe_screen
*screen
,
772 enum SVGA3dSurfaceFormat format
,
773 struct svga_winsys_surface
*srf
)
775 struct pipe_buffer
*buf
;
776 struct svga_buffer
*sbuf
;
777 struct svga_winsys_screen
*sws
= svga_winsys_screen(screen
);
779 buf
= svga_buffer_create(screen
, 0, SVGA_BUFFER_USAGE_WRAPPED
, 0);
783 sbuf
= svga_buffer(buf
);
786 * We are not the creator of this surface and therefore we must not
787 * cache it for reuse. Set the cacheable flag to zero in the key to
790 sbuf
->key
.format
= format
;
791 sbuf
->key
.cachable
= 0;
792 sws
->surface_reference(sws
, &sbuf
->handle
, srf
);
798 struct svga_winsys_surface
*
799 svga_screen_buffer_get_winsys_surface(struct pipe_buffer
*buffer
)
801 struct svga_winsys_screen
*sws
= svga_winsys_screen(buffer
->screen
);
802 struct svga_winsys_surface
*vsurf
= NULL
;
804 assert(svga_buffer(buffer
)->key
.cachable
== 0);
805 svga_buffer(buffer
)->key
.cachable
= 0;
806 sws
->surface_reference(sws
, &vsurf
, svga_buffer(buffer
)->handle
);
811 svga_context_flush_buffers(struct svga_context
*svga
)
813 struct list_head
*curr
, *next
;
814 struct svga_buffer
*sbuf
;
816 curr
= svga
->dirty_buffers
.next
;
818 while(curr
!= &svga
->dirty_buffers
) {
819 sbuf
= LIST_ENTRY(struct svga_buffer
, curr
, head
);
821 assert(p_atomic_read(&sbuf
->base
.reference
.count
) != 0);
822 assert(sbuf
->needs_flush
);
824 svga_buffer_upload_flush(svga
, sbuf
);