1 /**********************************************************
2 * Copyright 2008-2009 VMware, Inc. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 **********************************************************/
26 #include "util/u_inlines.h"
27 #include "util/u_memory.h"
28 #include "pipe/p_defines.h"
29 #include "util/u_math.h"
31 #include "svga_context.h"
32 #include "svga_screen.h"
33 #include "svga_state.h"
39 SVGA3dRenderState rs
[SVGA3D_RS_MAX
];
43 #define EMIT_RS(svga, value, token, fail) \
45 assert(SVGA3D_RS_##token < Elements(svga->state.hw_draw.rs)); \
46 if (svga->state.hw_draw.rs[SVGA3D_RS_##token] != value) { \
47 svga_queue_rs( &queue, SVGA3D_RS_##token, value ); \
48 svga->state.hw_draw.rs[SVGA3D_RS_##token] = value; \
52 #define EMIT_RS_FLOAT(svga, fvalue, token, fail) \
54 unsigned value = fui(fvalue); \
55 assert(SVGA3D_RS_##token < Elements(svga->state.hw_draw.rs)); \
56 if (svga->state.hw_draw.rs[SVGA3D_RS_##token] != value) { \
57 svga_queue_rs( &queue, SVGA3D_RS_##token, value ); \
58 svga->state.hw_draw.rs[SVGA3D_RS_##token] = value; \
64 svga_queue_rs( struct rs_queue
*q
,
68 q
->rs
[q
->rs_count
].state
= rss
;
69 q
->rs
[q
->rs_count
].uintValue
= value
;
74 /* Compare old and new render states and emit differences between them
75 * to hardware. Simplest implementation would be to emit the whole of
78 static enum pipe_error
79 emit_rss(struct svga_context
*svga
, unsigned dirty
)
81 struct svga_screen
*screen
= svga_screen(svga
->pipe
.screen
);
82 struct rs_queue queue
;
87 if (dirty
& SVGA_NEW_BLEND
) {
88 const struct svga_blend_state
*curr
= svga
->curr
.blend
;
90 EMIT_RS( svga
, curr
->rt
[0].writemask
, COLORWRITEENABLE
, fail
);
91 EMIT_RS( svga
, curr
->rt
[0].blend_enable
, BLENDENABLE
, fail
);
93 if (curr
->rt
[0].blend_enable
) {
94 EMIT_RS( svga
, curr
->rt
[0].srcblend
, SRCBLEND
, fail
);
95 EMIT_RS( svga
, curr
->rt
[0].dstblend
, DSTBLEND
, fail
);
96 EMIT_RS( svga
, curr
->rt
[0].blendeq
, BLENDEQUATION
, fail
);
98 EMIT_RS( svga
, curr
->rt
[0].separate_alpha_blend_enable
,
99 SEPARATEALPHABLENDENABLE
, fail
);
101 if (curr
->rt
[0].separate_alpha_blend_enable
) {
102 EMIT_RS( svga
, curr
->rt
[0].srcblend_alpha
, SRCBLENDALPHA
, fail
);
103 EMIT_RS( svga
, curr
->rt
[0].dstblend_alpha
, DSTBLENDALPHA
, fail
);
104 EMIT_RS( svga
, curr
->rt
[0].blendeq_alpha
, BLENDEQUATIONALPHA
, fail
);
109 if (dirty
& SVGA_NEW_BLEND_COLOR
) {
111 uint32 r
= float_to_ubyte(svga
->curr
.blend_color
.color
[0]);
112 uint32 g
= float_to_ubyte(svga
->curr
.blend_color
.color
[1]);
113 uint32 b
= float_to_ubyte(svga
->curr
.blend_color
.color
[2]);
114 uint32 a
= float_to_ubyte(svga
->curr
.blend_color
.color
[3]);
116 color
= (a
<< 24) | (r
<< 16) | (g
<< 8) | b
;
118 EMIT_RS( svga
, color
, BLENDCOLOR
, fail
);
121 if (dirty
& (SVGA_NEW_DEPTH_STENCIL
| SVGA_NEW_RAST
)) {
122 const struct svga_depth_stencil_state
*curr
= svga
->curr
.depth
;
123 const struct svga_rasterizer_state
*rast
= svga
->curr
.rast
;
125 if (!curr
->stencil
[0].enabled
)
129 EMIT_RS( svga
, FALSE
, STENCILENABLE
, fail
);
130 EMIT_RS( svga
, FALSE
, STENCILENABLE2SIDED
, fail
);
132 else if (curr
->stencil
[0].enabled
&& !curr
->stencil
[1].enabled
)
136 EMIT_RS( svga
, TRUE
, STENCILENABLE
, fail
);
137 EMIT_RS( svga
, FALSE
, STENCILENABLE2SIDED
, fail
);
139 EMIT_RS( svga
, curr
->stencil
[0].func
, STENCILFUNC
, fail
);
140 EMIT_RS( svga
, curr
->stencil
[0].fail
, STENCILFAIL
, fail
);
141 EMIT_RS( svga
, curr
->stencil
[0].zfail
, STENCILZFAIL
, fail
);
142 EMIT_RS( svga
, curr
->stencil
[0].pass
, STENCILPASS
, fail
);
144 EMIT_RS( svga
, curr
->stencil_mask
, STENCILMASK
, fail
);
145 EMIT_RS( svga
, curr
->stencil_writemask
, STENCILWRITEMASK
, fail
);
151 /* Hardware frontwinding is always CW, so if ours is also CW,
152 * then our definition of front face agrees with hardware.
153 * Otherwise need to flip.
155 if (rast
->templ
.front_ccw
) {
166 EMIT_RS( svga
, TRUE
, STENCILENABLE
, fail
);
167 EMIT_RS( svga
, TRUE
, STENCILENABLE2SIDED
, fail
);
169 EMIT_RS( svga
, curr
->stencil
[cw
].func
, STENCILFUNC
, fail
);
170 EMIT_RS( svga
, curr
->stencil
[cw
].fail
, STENCILFAIL
, fail
);
171 EMIT_RS( svga
, curr
->stencil
[cw
].zfail
, STENCILZFAIL
, fail
);
172 EMIT_RS( svga
, curr
->stencil
[cw
].pass
, STENCILPASS
, fail
);
174 EMIT_RS( svga
, curr
->stencil
[ccw
].func
, CCWSTENCILFUNC
, fail
);
175 EMIT_RS( svga
, curr
->stencil
[ccw
].fail
, CCWSTENCILFAIL
, fail
);
176 EMIT_RS( svga
, curr
->stencil
[ccw
].zfail
, CCWSTENCILZFAIL
, fail
);
177 EMIT_RS( svga
, curr
->stencil
[ccw
].pass
, CCWSTENCILPASS
, fail
);
179 EMIT_RS( svga
, curr
->stencil_mask
, STENCILMASK
, fail
);
180 EMIT_RS( svga
, curr
->stencil_writemask
, STENCILWRITEMASK
, fail
);
183 EMIT_RS( svga
, curr
->zenable
, ZENABLE
, fail
);
185 EMIT_RS( svga
, curr
->zfunc
, ZFUNC
, fail
);
186 EMIT_RS( svga
, curr
->zwriteenable
, ZWRITEENABLE
, fail
);
189 EMIT_RS( svga
, curr
->alphatestenable
, ALPHATESTENABLE
, fail
);
190 if (curr
->alphatestenable
) {
191 EMIT_RS( svga
, curr
->alphafunc
, ALPHAFUNC
, fail
);
192 EMIT_RS_FLOAT( svga
, curr
->alpharef
, ALPHAREF
, fail
);
196 if (dirty
& SVGA_NEW_STENCIL_REF
) {
197 EMIT_RS( svga
, svga
->curr
.stencil_ref
.ref_value
[0], STENCILREF
, fail
);
200 if (dirty
& (SVGA_NEW_RAST
| SVGA_NEW_NEED_PIPELINE
))
202 const struct svga_rasterizer_state
*curr
= svga
->curr
.rast
;
203 unsigned cullmode
= curr
->cullmode
;
205 /* Shademode: still need to rearrange index list to move
206 * flat-shading PV first vertex.
208 EMIT_RS( svga
, curr
->shademode
, SHADEMODE
, fail
);
210 /* Don't do culling while the software pipeline is active. It
211 * does it for us, and additionally introduces potentially
212 * back-facing triangles.
214 if (svga
->state
.sw
.need_pipeline
)
215 cullmode
= SVGA3D_FACE_NONE
;
217 point_size_min
= util_get_min_point_size(&curr
->templ
);
219 EMIT_RS( svga
, cullmode
, CULLMODE
, fail
);
220 EMIT_RS( svga
, curr
->scissortestenable
, SCISSORTESTENABLE
, fail
);
221 EMIT_RS( svga
, curr
->multisampleantialias
, MULTISAMPLEANTIALIAS
, fail
);
222 EMIT_RS( svga
, curr
->lastpixel
, LASTPIXEL
, fail
);
223 EMIT_RS( svga
, curr
->linepattern
, LINEPATTERN
, fail
);
224 EMIT_RS_FLOAT( svga
, curr
->pointsize
, POINTSIZE
, fail
);
225 EMIT_RS_FLOAT( svga
, point_size_min
, POINTSIZEMIN
, fail
);
226 EMIT_RS_FLOAT( svga
, screen
->maxPointSize
, POINTSIZEMAX
, fail
);
227 EMIT_RS( svga
, curr
->pointsprite
, POINTSPRITEENABLE
, fail
);
230 if (dirty
& (SVGA_NEW_RAST
| SVGA_NEW_FRAME_BUFFER
| SVGA_NEW_NEED_PIPELINE
))
232 const struct svga_rasterizer_state
*curr
= svga
->curr
.rast
;
236 /* Need to modify depth bias according to bound depthbuffer
237 * format. Don't do hardware depthbias while the software
238 * pipeline is active.
240 if (!svga
->state
.sw
.need_pipeline
&&
241 svga
->curr
.framebuffer
.zsbuf
)
243 slope
= curr
->slopescaledepthbias
;
244 bias
= svga
->curr
.depthscale
* curr
->depthbias
;
247 EMIT_RS_FLOAT( svga
, slope
, SLOPESCALEDEPTHBIAS
, fail
);
248 EMIT_RS_FLOAT( svga
, bias
, DEPTHBIAS
, fail
);
251 if (dirty
& SVGA_NEW_RAST
) {
252 /* bitmask of the enabled clip planes */
253 unsigned enabled
= svga
->curr
.rast
->templ
.clip_plane_enable
;
254 EMIT_RS( svga
, enabled
, CLIPPLANEENABLE
, fail
);
257 if (queue
.rs_count
) {
258 SVGA3dRenderState
*rs
;
260 if (SVGA3D_BeginSetRenderState( svga
->swc
,
262 queue
.rs_count
) != PIPE_OK
)
267 queue
.rs_count
* sizeof queue
.rs
[0]);
269 SVGA_FIFOCommitAll( svga
->swc
);
275 /* XXX: need to poison cached hardware state on failure to ensure
276 * dirty state gets re-emitted. Fix this by re-instating partial
277 * FIFOCommit command and only updating cached hw state once the
278 * initial allocation has succeeded.
280 memset(svga
->state
.hw_draw
.rs
, 0xcd, sizeof(svga
->state
.hw_draw
.rs
));
282 return PIPE_ERROR_OUT_OF_MEMORY
;
286 struct svga_tracked_state svga_hw_rss
=
291 SVGA_NEW_BLEND_COLOR
|
292 SVGA_NEW_DEPTH_STENCIL
|
293 SVGA_NEW_STENCIL_REF
|
295 SVGA_NEW_FRAME_BUFFER
|
296 SVGA_NEW_NEED_PIPELINE
),