src/gallium/drivers/svga/svga_state_rss.c

   1 /**********************************************************
   2  * Copyright 2008-2009 VMware, Inc.  All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person
   5  * obtaining a copy of this software and associated documentation
   6  * files (the "Software"), to deal in the Software without
   7  * restriction, including without limitation the rights to use, copy,
   8  * modify, merge, publish, distribute, sublicense, and/or sell copies
   9  * of the Software, and to permit persons to whom the Software is
  10  * furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be
  13  * included in all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  16  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  17  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  18  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  19  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  20  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  21  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  *
  24  **********************************************************/
  25
  26 #include "util/u_inlines.h"
  27 #include "util/u_memory.h"
  28 #include "pipe/p_defines.h"
  29 #include "util/u_math.h"
  30
  31 #include "svga_context.h"
  32 #include "svga_state.h"
  33 #include "svga_cmd.h"
  34
  35
  36 struct rs_queue {
  37    unsigned rs_count;
  38    SVGA3dRenderState rs[SVGA3D_RS_MAX];
  39 };
  40
  41
  42 #define EMIT_RS(svga, value, token, fail)                       \
  43 do {                                                            \
  44    assert(SVGA3D_RS_##token < Elements(svga->state.hw_draw.rs)); \
  45    if (svga->state.hw_draw.rs[SVGA3D_RS_##token] != value) {    \
  46       svga_queue_rs( &queue, SVGA3D_RS_##token, value );        \
  47       svga->state.hw_draw.rs[SVGA3D_RS_##token] = value;        \
  48    }                                                            \
  49 } while (0)
  50
  51 #define EMIT_RS_FLOAT(svga, fvalue, token, fail)                \
  52 do {                                                            \
  53    unsigned value = fui(fvalue);                                \
  54    assert(SVGA3D_RS_##token < Elements(svga->state.hw_draw.rs)); \
  55    if (svga->state.hw_draw.rs[SVGA3D_RS_##token] != value) {    \
  56       svga_queue_rs( &queue, SVGA3D_RS_##token, value );        \
  57       svga->state.hw_draw.rs[SVGA3D_RS_##token] = value;        \
  58    }                                                            \
  59 } while (0)
  60
  61
  62 static INLINE void
  63 svga_queue_rs( struct rs_queue *q,
  64                unsigned rss,
  65                unsigned value )
  66 {
  67    q->rs[q->rs_count].state = rss;
  68    q->rs[q->rs_count].uintValue = value;
  69    q->rs_count++;
  70 }
  71
  72
  73 /* Compare old and new render states and emit differences between them
  74  * to hardware.  Simplest implementation would be to emit the whole of
  75  * the "to" state.
  76  */
  77 static int emit_rss( struct svga_context *svga,
  78                      unsigned dirty )
  79 {
  80    struct rs_queue queue;
  81
  82    queue.rs_count = 0;
  83
  84    if (dirty & SVGA_NEW_BLEND) {
  85       const struct svga_blend_state *curr = svga->curr.blend;
  86
  87       EMIT_RS( svga, curr->rt[0].writemask, COLORWRITEENABLE, fail );
  88       EMIT_RS( svga, curr->rt[0].blend_enable, BLENDENABLE, fail );
  89
  90       if (curr->rt[0].blend_enable) {
  91          EMIT_RS( svga, curr->rt[0].srcblend, SRCBLEND, fail );
  92          EMIT_RS( svga, curr->rt[0].dstblend, DSTBLEND, fail );
  93          EMIT_RS( svga, curr->rt[0].blendeq, BLENDEQUATION, fail );
  94
  95          EMIT_RS( svga, curr->rt[0].separate_alpha_blend_enable,
  96                   SEPARATEALPHABLENDENABLE, fail );
  97
  98          if (curr->rt[0].separate_alpha_blend_enable) {
  99             EMIT_RS( svga, curr->rt[0].srcblend_alpha, SRCBLENDALPHA, fail );
 100             EMIT_RS( svga, curr->rt[0].dstblend_alpha, DSTBLENDALPHA, fail );
 101             EMIT_RS( svga, curr->rt[0].blendeq_alpha, BLENDEQUATIONALPHA, fail );
 102          }
 103       }
 104    }
 105
 106    if (dirty & SVGA_NEW_BLEND_COLOR) {
 107       uint32 color;
 108       uint32 r = float_to_ubyte(svga->curr.blend_color.color[0]);
 109       uint32 g = float_to_ubyte(svga->curr.blend_color.color[1]);
 110       uint32 b = float_to_ubyte(svga->curr.blend_color.color[2]);
 111       uint32 a = float_to_ubyte(svga->curr.blend_color.color[3]);
 112
 113       color = (a << 24) | (r << 16) | (g << 8) | b;
 114
 115       EMIT_RS( svga, color, BLENDCOLOR, fail );
 116    }
 117
 118    if (dirty & (SVGA_NEW_DEPTH_STENCIL | SVGA_NEW_RAST)) {
 119       const struct svga_depth_stencil_state *curr = svga->curr.depth;
 120       const struct svga_rasterizer_state *rast = svga->curr.rast;
 121
 122       if (!curr->stencil[0].enabled)
 123       {
 124          /* Stencil disabled
 125           */
 126          EMIT_RS( svga, FALSE, STENCILENABLE, fail );
 127          EMIT_RS( svga, FALSE, STENCILENABLE2SIDED, fail );
 128       }
 129       else if (curr->stencil[0].enabled && !curr->stencil[1].enabled)
 130       {
 131          /* Regular stencil
 132           */
 133          EMIT_RS( svga, TRUE, STENCILENABLE, fail );
 134          EMIT_RS( svga, FALSE, STENCILENABLE2SIDED, fail );
 135
 136          EMIT_RS( svga, curr->stencil[0].func,  STENCILFUNC, fail );
 137          EMIT_RS( svga, curr->stencil[0].fail,  STENCILFAIL, fail );
 138          EMIT_RS( svga, curr->stencil[0].zfail, STENCILZFAIL, fail );
 139          EMIT_RS( svga, curr->stencil[0].pass,  STENCILPASS, fail );
 140
 141          EMIT_RS( svga, curr->stencil_mask, STENCILMASK, fail );
 142          EMIT_RS( svga, curr->stencil_writemask, STENCILWRITEMASK, fail );
 143       }
 144       else
 145       {
 146          int cw, ccw;
 147
 148          /* Hardware frontwinding is always CW, so if ours is also CW,
 149           * then our definition of front face agrees with hardware.
 150           * Otherwise need to flip.
 151           */
 152          if (rast->templ.front_ccw) {
 153             ccw = 0;
 154             cw = 1;
 155          }
 156          else {
 157             ccw = 1;
 158             cw = 0;
 159          }
 160
 161          /* Twoside stencil
 162           */
 163          EMIT_RS( svga, TRUE, STENCILENABLE, fail );
 164          EMIT_RS( svga, TRUE, STENCILENABLE2SIDED, fail );
 165
 166          EMIT_RS( svga, curr->stencil[cw].func,  STENCILFUNC, fail );
 167          EMIT_RS( svga, curr->stencil[cw].fail,  STENCILFAIL, fail );
 168          EMIT_RS( svga, curr->stencil[cw].zfail, STENCILZFAIL, fail );
 169          EMIT_RS( svga, curr->stencil[cw].pass,  STENCILPASS, fail );
 170
 171          EMIT_RS( svga, curr->stencil[ccw].func,  CCWSTENCILFUNC, fail );
 172          EMIT_RS( svga, curr->stencil[ccw].fail,  CCWSTENCILFAIL, fail );
 173          EMIT_RS( svga, curr->stencil[ccw].zfail, CCWSTENCILZFAIL, fail );
 174          EMIT_RS( svga, curr->stencil[ccw].pass,  CCWSTENCILPASS, fail );
 175
 176          EMIT_RS( svga, curr->stencil_mask, STENCILMASK, fail );
 177          EMIT_RS( svga, curr->stencil_writemask, STENCILWRITEMASK, fail );
 178       }
 179
 180       EMIT_RS( svga, curr->zenable, ZENABLE, fail );
 181       if (curr->zenable) {
 182          EMIT_RS( svga, curr->zfunc, ZFUNC, fail );
 183          EMIT_RS( svga, curr->zwriteenable, ZWRITEENABLE, fail );
 184       }
 185
 186       EMIT_RS( svga, curr->alphatestenable, ALPHATESTENABLE, fail );
 187       if (curr->alphatestenable) {
 188          EMIT_RS( svga, curr->alphafunc, ALPHAFUNC, fail );
 189          EMIT_RS_FLOAT( svga, curr->alpharef, ALPHAREF, fail );
 190       }
 191    }
 192
 193    if (dirty & SVGA_NEW_STENCIL_REF) {
 194       EMIT_RS( svga, svga->curr.stencil_ref.ref_value[0], STENCILREF, fail );
 195    }
 196
 197    if (dirty & (SVGA_NEW_RAST | SVGA_NEW_NEED_PIPELINE))
 198    {
 199       const struct svga_rasterizer_state *curr = svga->curr.rast;
 200       unsigned cullmode = curr->cullmode;
 201
 202       /* Shademode: still need to rearrange index list to move
 203        * flat-shading PV first vertex.
 204        */
 205       EMIT_RS( svga, curr->shademode, SHADEMODE, fail );
 206
 207       /* Don't do culling while the software pipeline is active.  It
 208        * does it for us, and additionally introduces potentially
 209        * back-facing triangles.
 210        */
 211       if (svga->state.sw.need_pipeline)
 212          cullmode = SVGA3D_FACE_NONE;
 213
 214       EMIT_RS( svga, cullmode, CULLMODE, fail );
 215       EMIT_RS( svga, curr->scissortestenable, SCISSORTESTENABLE, fail );
 216       EMIT_RS( svga, curr->multisampleantialias, MULTISAMPLEANTIALIAS, fail );
 217       EMIT_RS( svga, curr->lastpixel, LASTPIXEL, fail );
 218       EMIT_RS( svga, curr->linepattern, LINEPATTERN, fail );
 219       EMIT_RS_FLOAT( svga, curr->pointsize, POINTSIZE, fail );
 220       /* XXX still need to set this? */
 221       EMIT_RS_FLOAT( svga, 0.0, POINTSIZEMIN, fail );
 222       EMIT_RS_FLOAT( svga, SVGA_MAX_POINTSIZE, POINTSIZEMAX, fail );
 223       EMIT_RS( svga, curr->pointsprite, POINTSPRITEENABLE, fail);
 224    }
 225
 226    if (dirty & (SVGA_NEW_RAST | SVGA_NEW_FRAME_BUFFER | SVGA_NEW_NEED_PIPELINE))
 227    {
 228       const struct svga_rasterizer_state *curr = svga->curr.rast;
 229       float slope = 0.0;
 230       float bias  = 0.0;
 231
 232       /* Need to modify depth bias according to bound depthbuffer
 233        * format.  Don't do hardware depthbias while the software
 234        * pipeline is active.
 235        */
 236       if (!svga->state.sw.need_pipeline &&
 237           svga->curr.framebuffer.zsbuf)
 238       {
 239          slope = curr->slopescaledepthbias;
 240          bias  = svga->curr.depthscale * curr->depthbias;
 241       }
 242
 243       EMIT_RS_FLOAT( svga, slope, SLOPESCALEDEPTHBIAS, fail );
 244       EMIT_RS_FLOAT( svga, bias, DEPTHBIAS, fail );
 245    }
 246
 247    if (dirty & SVGA_NEW_CLIP) {
 248       /* the number of clip planes is how many planes to enable */
 249       unsigned enabled = svga->curr.rast->templ.clip_plane_enable;
 250       EMIT_RS( svga, enabled, CLIPPLANEENABLE, fail );
 251    }
 252
 253    if (queue.rs_count) {
 254       SVGA3dRenderState *rs;
 255
 256       if (SVGA3D_BeginSetRenderState( svga->swc,
 257                                       &rs,
 258                                       queue.rs_count ) != PIPE_OK)
 259          goto fail;
 260
 261       memcpy( rs,
 262               queue.rs,
 263               queue.rs_count * sizeof queue.rs[0]);
 264
 265       SVGA_FIFOCommitAll( svga->swc );
 266    }
 267
 268    return 0;
 269
 270 fail:
 271    /* XXX: need to poison cached hardware state on failure to ensure
 272     * dirty state gets re-emitted.  Fix this by re-instating partial
 273     * FIFOCommit command and only updating cached hw state once the
 274     * initial allocation has succeeded.
 275     */
 276    memset(svga->state.hw_draw.rs, 0xcd, sizeof(svga->state.hw_draw.rs));
 277
 278    return PIPE_ERROR_OUT_OF_MEMORY;
 279 }
 280
 281
 282 struct svga_tracked_state svga_hw_rss =
 283 {
 284    "hw rss state",
 285
 286    (SVGA_NEW_BLEND |
 287     SVGA_NEW_BLEND_COLOR |
 288     SVGA_NEW_CLIP |
 289     SVGA_NEW_DEPTH_STENCIL |
 290     SVGA_NEW_STENCIL_REF |
 291     SVGA_NEW_RAST |
 292     SVGA_NEW_FRAME_BUFFER |
 293     SVGA_NEW_NEED_PIPELINE),
 294
 295    emit_rss
 296 };