1 /**********************************************************
2 * Copyright 2008-2009 VMware, Inc. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 **********************************************************/
26 #include "pipe/p_inlines.h"
27 #include "pipe/p_defines.h"
28 #include "util/u_math.h"
30 #include "svga_context.h"
31 #include "svga_state.h"
34 #include "svga_hw_reg.h"
40 SVGA3dRenderState rs
[SVGA3D_RS_MAX
];
44 #define EMIT_RS(svga, value, token, fail) \
46 if (svga->state.hw_draw.rs[SVGA3D_RS_##token] != value) { \
47 svga_queue_rs( &queue, SVGA3D_RS_##token, value ); \
48 svga->state.hw_draw.rs[SVGA3D_RS_##token] = value; \
52 #define EMIT_RS_FLOAT(svga, fvalue, token, fail) \
54 unsigned value = fui(fvalue); \
55 if (svga->state.hw_draw.rs[SVGA3D_RS_##token] != value) { \
56 svga_queue_rs( &queue, SVGA3D_RS_##token, value ); \
57 svga->state.hw_draw.rs[SVGA3D_RS_##token] = value; \
63 svga_queue_rs( struct rs_queue
*q
,
67 q
->rs
[q
->rs_count
].state
= rss
;
68 q
->rs
[q
->rs_count
].uintValue
= value
;
73 /* Compare old and new render states and emit differences between them
74 * to hardware. Simplest implementation would be to emit the whole of
77 static int emit_rss( struct svga_context
*svga
,
80 struct rs_queue queue
;
84 if (dirty
& SVGA_NEW_BLEND
) {
85 const struct svga_blend_state
*curr
= svga
->curr
.blend
;
87 EMIT_RS( svga
, curr
->rt
[0].writemask
, COLORWRITEENABLE
, fail
);
88 EMIT_RS( svga
, curr
->rt
[0].blend_enable
, BLENDENABLE
, fail
);
90 if (curr
->rt
[0].blend_enable
) {
91 EMIT_RS( svga
, curr
->rt
[0].srcblend
, SRCBLEND
, fail
);
92 EMIT_RS( svga
, curr
->rt
[0].dstblend
, DSTBLEND
, fail
);
93 EMIT_RS( svga
, curr
->rt
[0].blendeq
, BLENDEQUATION
, fail
);
95 EMIT_RS( svga
, curr
->rt
[0].separate_alpha_blend_enable
,
96 SEPARATEALPHABLENDENABLE
, fail
);
98 if (curr
->rt
[0].separate_alpha_blend_enable
) {
99 EMIT_RS( svga
, curr
->rt
[0].srcblend_alpha
, SRCBLENDALPHA
, fail
);
100 EMIT_RS( svga
, curr
->rt
[0].dstblend_alpha
, DSTBLENDALPHA
, fail
);
101 EMIT_RS( svga
, curr
->rt
[0].blendeq_alpha
, BLENDEQUATIONALPHA
, fail
);
107 if (dirty
& (SVGA_NEW_DEPTH_STENCIL
| SVGA_NEW_RAST
)) {
108 const struct svga_depth_stencil_state
*curr
= svga
->curr
.depth
;
109 const struct svga_rasterizer_state
*rast
= svga
->curr
.rast
;
111 if (!curr
->stencil
[0].enabled
)
115 EMIT_RS( svga
, FALSE
, STENCILENABLE
, fail
);
116 EMIT_RS( svga
, FALSE
, STENCILENABLE2SIDED
, fail
);
118 else if (curr
->stencil
[0].enabled
&& !curr
->stencil
[1].enabled
)
122 EMIT_RS( svga
, TRUE
, STENCILENABLE
, fail
);
123 EMIT_RS( svga
, FALSE
, STENCILENABLE2SIDED
, fail
);
125 EMIT_RS( svga
, curr
->stencil
[0].func
, STENCILFUNC
, fail
);
126 EMIT_RS( svga
, curr
->stencil
[0].fail
, STENCILFAIL
, fail
);
127 EMIT_RS( svga
, curr
->stencil
[0].zfail
, STENCILZFAIL
, fail
);
128 EMIT_RS( svga
, curr
->stencil
[0].pass
, STENCILPASS
, fail
);
130 EMIT_RS( svga
, curr
->stencil_ref
, STENCILREF
, fail
);
131 EMIT_RS( svga
, curr
->stencil_mask
, STENCILMASK
, fail
);
132 EMIT_RS( svga
, curr
->stencil_writemask
, STENCILWRITEMASK
, fail
);
138 /* Hardware frontwinding is always CW, so if ours is also CW,
139 * then our definition of front face agrees with hardware.
140 * Otherwise need to flip.
142 if (rast
->templ
.front_winding
== PIPE_WINDING_CW
) {
153 EMIT_RS( svga
, TRUE
, STENCILENABLE
, fail
);
154 EMIT_RS( svga
, TRUE
, STENCILENABLE2SIDED
, fail
);
156 EMIT_RS( svga
, curr
->stencil
[cw
].func
, STENCILFUNC
, fail
);
157 EMIT_RS( svga
, curr
->stencil
[cw
].fail
, STENCILFAIL
, fail
);
158 EMIT_RS( svga
, curr
->stencil
[cw
].zfail
, STENCILZFAIL
, fail
);
159 EMIT_RS( svga
, curr
->stencil
[cw
].pass
, STENCILPASS
, fail
);
161 EMIT_RS( svga
, curr
->stencil
[ccw
].func
, CCWSTENCILFUNC
, fail
);
162 EMIT_RS( svga
, curr
->stencil
[ccw
].fail
, CCWSTENCILFAIL
, fail
);
163 EMIT_RS( svga
, curr
->stencil
[ccw
].zfail
, CCWSTENCILZFAIL
, fail
);
164 EMIT_RS( svga
, curr
->stencil
[ccw
].pass
, CCWSTENCILPASS
, fail
);
166 EMIT_RS( svga
, curr
->stencil_ref
, STENCILREF
, fail
);
167 EMIT_RS( svga
, curr
->stencil_mask
, STENCILMASK
, fail
);
168 EMIT_RS( svga
, curr
->stencil_writemask
, STENCILWRITEMASK
, fail
);
171 EMIT_RS( svga
, curr
->zenable
, ZENABLE
, fail
);
173 EMIT_RS( svga
, curr
->zfunc
, ZFUNC
, fail
);
174 EMIT_RS( svga
, curr
->zwriteenable
, ZWRITEENABLE
, fail
);
177 EMIT_RS( svga
, curr
->alphatestenable
, ALPHATESTENABLE
, fail
);
178 if (curr
->alphatestenable
) {
179 EMIT_RS( svga
, curr
->alphafunc
, ALPHAFUNC
, fail
);
180 EMIT_RS_FLOAT( svga
, curr
->alpharef
, ALPHAREF
, fail
);
185 if (dirty
& SVGA_NEW_RAST
)
187 const struct svga_rasterizer_state
*curr
= svga
->curr
.rast
;
189 /* Shademode: still need to rearrange index list to move
190 * flat-shading PV first vertex.
192 EMIT_RS( svga
, curr
->shademode
, SHADEMODE
, fail
);
193 EMIT_RS( svga
, curr
->cullmode
, CULLMODE
, fail
);
194 EMIT_RS( svga
, curr
->scissortestenable
, SCISSORTESTENABLE
, fail
);
195 EMIT_RS( svga
, curr
->multisampleantialias
, MULTISAMPLEANTIALIAS
, fail
);
196 EMIT_RS( svga
, curr
->lastpixel
, LASTPIXEL
, fail
);
197 EMIT_RS( svga
, curr
->linepattern
, LINEPATTERN
, fail
);
198 EMIT_RS_FLOAT( svga
, curr
->pointsize
, POINTSIZE
, fail
);
199 EMIT_RS_FLOAT( svga
, curr
->pointsize_min
, POINTSIZEMIN
, fail
);
200 EMIT_RS_FLOAT( svga
, curr
->pointsize_max
, POINTSIZEMAX
, fail
);
203 if (dirty
& (SVGA_NEW_RAST
| SVGA_NEW_FRAME_BUFFER
| SVGA_NEW_NEED_PIPELINE
))
205 const struct svga_rasterizer_state
*curr
= svga
->curr
.rast
;
209 /* Need to modify depth bias according to bound depthbuffer
210 * format. Don't do hardware depthbias while the software
211 * pipeline is active.
213 if (!svga
->state
.sw
.need_pipeline
&&
214 svga
->curr
.framebuffer
.zsbuf
)
216 slope
= curr
->slopescaledepthbias
;
217 bias
= svga
->curr
.depthscale
* curr
->depthbias
;
220 EMIT_RS_FLOAT( svga
, slope
, SLOPESCALEDEPTHBIAS
, fail
);
221 EMIT_RS_FLOAT( svga
, bias
, DEPTHBIAS
, fail
);
225 if (queue
.rs_count
) {
226 SVGA3dRenderState
*rs
;
228 if (SVGA3D_BeginSetRenderState( svga
->swc
,
230 queue
.rs_count
) != PIPE_OK
)
235 queue
.rs_count
* sizeof queue
.rs
[0]);
237 SVGA_FIFOCommitAll( svga
->swc
);
246 /* XXX: need to poison cached hardware state on failure to ensure
247 * dirty state gets re-emitted. Fix this by re-instating partial
248 * FIFOCommit command and only updating cached hw state once the
249 * initial allocation has succeeded.
251 memset(svga
->state
.hw_draw
.rs
, 0xcd, sizeof(svga
->state
.hw_draw
.rs
));
253 return PIPE_ERROR_OUT_OF_MEMORY
;
257 struct svga_tracked_state svga_hw_rss
=
262 SVGA_NEW_DEPTH_STENCIL
|
264 SVGA_NEW_FRAME_BUFFER
|
265 SVGA_NEW_NEED_PIPELINE
),