src/gallium/drivers/svga/svga_state_rss.c

   1 /**********************************************************
   2  * Copyright 2008-2009 VMware, Inc.  All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person
   5  * obtaining a copy of this software and associated documentation
   6  * files (the "Software"), to deal in the Software without
   7  * restriction, including without limitation the rights to use, copy,
   8  * modify, merge, publish, distribute, sublicense, and/or sell copies
   9  * of the Software, and to permit persons to whom the Software is
  10  * furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be
  13  * included in all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  16  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  17  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  18  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  19  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  20  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  21  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  *
  24  **********************************************************/
  25
  26 #include "util/u_inlines.h"
  27 #include "pipe/p_defines.h"
  28 #include "util/u_math.h"
  29 #if 0
  30 #include "util/u_pack_color.h"
  31 #endif
  32
  33 #include "svga_context.h"
  34 #include "svga_state.h"
  35 #include "svga_cmd.h"
  36
  37
  38 struct rs_queue {
  39    unsigned rs_count;
  40    SVGA3dRenderState rs[SVGA3D_RS_MAX];
  41 };
  42
  43
  44 #define EMIT_RS(svga, value, token, fail)                       \
  45 do {                                                            \
  46    if (svga->state.hw_draw.rs[SVGA3D_RS_##token] != value) {    \
  47       svga_queue_rs( &queue, SVGA3D_RS_##token, value );        \
  48       svga->state.hw_draw.rs[SVGA3D_RS_##token] = value;        \
  49    }                                                            \
  50 } while (0)
  51
  52 #define EMIT_RS_FLOAT(svga, fvalue, token, fail)                \
  53 do {                                                            \
  54    unsigned value = fui(fvalue);                                \
  55    if (svga->state.hw_draw.rs[SVGA3D_RS_##token] != value) {    \
  56       svga_queue_rs( &queue, SVGA3D_RS_##token, value );        \
  57       svga->state.hw_draw.rs[SVGA3D_RS_##token] = value;        \
  58    }                                                            \
  59 } while (0)
  60
  61
  62 static INLINE void
  63 svga_queue_rs( struct rs_queue *q,
  64                unsigned rss,
  65                unsigned value )
  66 {
  67    q->rs[q->rs_count].state = rss;
  68    q->rs[q->rs_count].uintValue = value;
  69    q->rs_count++;
  70 }
  71
  72
  73 /* Compare old and new render states and emit differences between them
  74  * to hardware.  Simplest implementation would be to emit the whole of
  75  * the "to" state.
  76  */
  77 static int emit_rss( struct svga_context *svga,
  78                      unsigned dirty )
  79 {
  80    struct rs_queue queue;
  81
  82    queue.rs_count = 0;
  83
  84    if (dirty & SVGA_NEW_BLEND) {
  85       const struct svga_blend_state *curr = svga->curr.blend;
  86
  87       EMIT_RS( svga, curr->rt[0].writemask, COLORWRITEENABLE, fail );
  88       EMIT_RS( svga, curr->rt[0].blend_enable, BLENDENABLE, fail );
  89
  90       if (curr->rt[0].blend_enable) {
  91          EMIT_RS( svga, curr->rt[0].srcblend, SRCBLEND, fail );
  92          EMIT_RS( svga, curr->rt[0].dstblend, DSTBLEND, fail );
  93          EMIT_RS( svga, curr->rt[0].blendeq, BLENDEQUATION, fail );
  94
  95          EMIT_RS( svga, curr->rt[0].separate_alpha_blend_enable,
  96                   SEPARATEALPHABLENDENABLE, fail );
  97
  98          if (curr->rt[0].separate_alpha_blend_enable) {
  99             EMIT_RS( svga, curr->rt[0].srcblend_alpha, SRCBLENDALPHA, fail );
 100             EMIT_RS( svga, curr->rt[0].dstblend_alpha, DSTBLENDALPHA, fail );
 101             EMIT_RS( svga, curr->rt[0].blendeq_alpha, BLENDEQUATIONALPHA, fail );
 102          }
 103       }
 104    }
 105
 106 #if 0
 107    /* FIXME: shouldn't we emit blend color here */
 108    if (dirty & SVGA_NEW_BLEND_COLOR) {
 109       union util_color uc;
 110       ubyte r = float_to_ubyte(svga->curr.blend_color.color[0]);
 111       ubyte g = float_to_ubyte(svga->curr.blend_color.color[1]);
 112       ubyte b = float_to_ubyte(svga->curr.blend_color.color[2]);
 113       ubyte a = float_to_ubyte(svga->curr.blend_color.color[3]);
 114
 115       util_pack_color_ub( r, g, b, a,
 116                           PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
 117
 118       EMIT_RS( svga, uc.ui, BLENDCOLOR, fail );
 119    }
 120 #endif
 121
 122
 123
 124    if (dirty & (SVGA_NEW_DEPTH_STENCIL | SVGA_NEW_RAST)) {
 125       const struct svga_depth_stencil_state *curr = svga->curr.depth;
 126       const struct svga_rasterizer_state *rast = svga->curr.rast;
 127
 128       if (!curr->stencil[0].enabled)
 129       {
 130          /* Stencil disabled
 131           */
 132          EMIT_RS( svga, FALSE, STENCILENABLE, fail );
 133          EMIT_RS( svga, FALSE, STENCILENABLE2SIDED, fail );
 134       }
 135       else if (curr->stencil[0].enabled && !curr->stencil[1].enabled)
 136       {
 137          /* Regular stencil
 138           */
 139          EMIT_RS( svga, TRUE, STENCILENABLE, fail );
 140          EMIT_RS( svga, FALSE, STENCILENABLE2SIDED, fail );
 141
 142          EMIT_RS( svga, curr->stencil[0].func,  STENCILFUNC, fail );
 143          EMIT_RS( svga, curr->stencil[0].fail,  STENCILFAIL, fail );
 144          EMIT_RS( svga, curr->stencil[0].zfail, STENCILZFAIL, fail );
 145          EMIT_RS( svga, curr->stencil[0].pass,  STENCILPASS, fail );
 146
 147          EMIT_RS( svga, curr->stencil_mask, STENCILMASK, fail );
 148          EMIT_RS( svga, curr->stencil_writemask, STENCILWRITEMASK, fail );
 149       }
 150       else
 151       {
 152          int cw, ccw;
 153
 154          /* Hardware frontwinding is always CW, so if ours is also CW,
 155           * then our definition of front face agrees with hardware.
 156           * Otherwise need to flip.
 157           */
 158          if (rast->templ.front_winding == PIPE_WINDING_CW) {
 159             cw = 0;
 160             ccw = 1;
 161          }
 162          else {
 163             cw = 1;
 164             ccw = 0;
 165          }
 166
 167          /* Twoside stencil
 168           */
 169          EMIT_RS( svga, TRUE, STENCILENABLE, fail );
 170          EMIT_RS( svga, TRUE, STENCILENABLE2SIDED, fail );
 171
 172          EMIT_RS( svga, curr->stencil[cw].func,  STENCILFUNC, fail );
 173          EMIT_RS( svga, curr->stencil[cw].fail,  STENCILFAIL, fail );
 174          EMIT_RS( svga, curr->stencil[cw].zfail, STENCILZFAIL, fail );
 175          EMIT_RS( svga, curr->stencil[cw].pass,  STENCILPASS, fail );
 176
 177          EMIT_RS( svga, curr->stencil[ccw].func,  CCWSTENCILFUNC, fail );
 178          EMIT_RS( svga, curr->stencil[ccw].fail,  CCWSTENCILFAIL, fail );
 179          EMIT_RS( svga, curr->stencil[ccw].zfail, CCWSTENCILZFAIL, fail );
 180          EMIT_RS( svga, curr->stencil[ccw].pass,  CCWSTENCILPASS, fail );
 181
 182          EMIT_RS( svga, curr->stencil_mask, STENCILMASK, fail );
 183          EMIT_RS( svga, curr->stencil_writemask, STENCILWRITEMASK, fail );
 184       }
 185
 186       EMIT_RS( svga, curr->zenable, ZENABLE, fail );
 187       if (curr->zenable) {
 188          EMIT_RS( svga, curr->zfunc, ZFUNC, fail );
 189          EMIT_RS( svga, curr->zwriteenable, ZWRITEENABLE, fail );
 190       }
 191
 192       EMIT_RS( svga, curr->alphatestenable, ALPHATESTENABLE, fail );
 193       if (curr->alphatestenable) {
 194          EMIT_RS( svga, curr->alphafunc, ALPHAFUNC, fail );
 195          EMIT_RS_FLOAT( svga, curr->alpharef, ALPHAREF, fail );
 196       }
 197    }
 198
 199    if (dirty & SVGA_NEW_STENCIL_REF) {
 200       EMIT_RS( svga, svga->curr.stencil_ref.ref_value[0], STENCILREF, fail );
 201    }
 202
 203    if (dirty & SVGA_NEW_RAST)
 204    {
 205       const struct svga_rasterizer_state *curr = svga->curr.rast;
 206
 207       /* Shademode: still need to rearrange index list to move
 208        * flat-shading PV first vertex.
 209        */
 210       EMIT_RS( svga, curr->shademode, SHADEMODE, fail );
 211       EMIT_RS( svga, curr->cullmode, CULLMODE, fail );
 212       EMIT_RS( svga, curr->scissortestenable, SCISSORTESTENABLE, fail );
 213       EMIT_RS( svga, curr->multisampleantialias, MULTISAMPLEANTIALIAS, fail );
 214       EMIT_RS( svga, curr->lastpixel, LASTPIXEL, fail );
 215       EMIT_RS( svga, curr->linepattern, LINEPATTERN, fail );
 216       EMIT_RS_FLOAT( svga, curr->pointsize, POINTSIZE, fail );
 217       /* XXX still need to set this? */
 218       EMIT_RS_FLOAT( svga, 0.0, POINTSIZEMIN, fail );
 219       EMIT_RS_FLOAT( svga, SVGA_MAX_POINTSIZE, POINTSIZEMAX, fail );
 220    }
 221
 222    if (dirty & (SVGA_NEW_RAST | SVGA_NEW_FRAME_BUFFER | SVGA_NEW_NEED_PIPELINE))
 223    {
 224       const struct svga_rasterizer_state *curr = svga->curr.rast;
 225       float slope = 0.0;
 226       float bias  = 0.0;
 227
 228       /* Need to modify depth bias according to bound depthbuffer
 229        * format.  Don't do hardware depthbias while the software
 230        * pipeline is active.
 231        */
 232       if (!svga->state.sw.need_pipeline &&
 233           svga->curr.framebuffer.zsbuf)
 234       {
 235          slope = curr->slopescaledepthbias;
 236          bias  = svga->curr.depthscale * curr->depthbias;
 237       }
 238
 239       EMIT_RS_FLOAT( svga, slope, SLOPESCALEDEPTHBIAS, fail );
 240       EMIT_RS_FLOAT( svga, bias, DEPTHBIAS, fail );
 241    }
 242
 243
 244    if (queue.rs_count) {
 245       SVGA3dRenderState *rs;
 246
 247       if (SVGA3D_BeginSetRenderState( svga->swc,
 248                                       &rs,
 249                                       queue.rs_count ) != PIPE_OK)
 250          goto fail;
 251
 252       memcpy( rs,
 253               queue.rs,
 254               queue.rs_count * sizeof queue.rs[0]);
 255
 256       SVGA_FIFOCommitAll( svga->swc );
 257    }
 258
 259    /* Also blend color:
 260     */
 261
 262    return 0;
 263
 264 fail:
 265    /* XXX: need to poison cached hardware state on failure to ensure
 266     * dirty state gets re-emitted.  Fix this by re-instating partial
 267     * FIFOCommit command and only updating cached hw state once the
 268     * initial allocation has succeeded.
 269     */
 270    memset(svga->state.hw_draw.rs, 0xcd, sizeof(svga->state.hw_draw.rs));
 271
 272    return PIPE_ERROR_OUT_OF_MEMORY;
 273 }
 274
 275
 276 struct svga_tracked_state svga_hw_rss =
 277 {
 278    "hw rss state",
 279
 280    (SVGA_NEW_BLEND |
 281 #if 0
 282     SVGA_NEW_BLEND_COLOR |
 283 #endif
 284     SVGA_NEW_DEPTH_STENCIL |
 285     SVGA_NEW_STENCIL_REF |
 286     SVGA_NEW_RAST |
 287     SVGA_NEW_FRAME_BUFFER |
 288     SVGA_NEW_NEED_PIPELINE),
 289
 290    emit_rss
 291 };