1 /**********************************************************
2 * Copyright 2008-2009 VMware, Inc. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 **********************************************************/
26 #include "util/u_inlines.h"
27 #include "util/u_memory.h"
28 #include "pipe/p_defines.h"
29 #include "util/u_math.h"
31 #include "svga_resource_texture.h"
32 #include "svga_sampler_view.h"
33 #include "svga_winsys.h"
34 #include "svga_context.h"
35 #include "svga_shader.h"
36 #include "svga_state.h"
41 * Called when tearing down a context to free resources and samplers.
44 svga_cleanup_tss_binding(struct svga_context
*svga
)
46 const enum pipe_shader_type shader
= PIPE_SHADER_FRAGMENT
;
49 for (i
= 0; i
< ARRAY_SIZE(svga
->state
.hw_draw
.views
); i
++) {
50 struct svga_hw_view_state
*view
= &svga
->state
.hw_draw
.views
[i
];
52 svga_sampler_view_reference(&view
->v
, NULL
);
53 pipe_sampler_view_reference(&svga
->curr
.sampler_views
[shader
][i
],
55 pipe_resource_reference(&view
->texture
, NULL
);
65 struct svga_hw_view_state
*view
;
66 } bind
[PIPE_MAX_SAMPLERS
];
73 * Update the texture binding for one texture unit.
76 emit_tex_binding_unit(struct svga_context
*svga
,
78 const struct svga_sampler_state
*s
,
79 const struct pipe_sampler_view
*sv
,
80 struct svga_hw_view_state
*view
,
82 struct bind_queue
*queue
)
84 struct pipe_resource
*texture
= NULL
;
85 unsigned last_level
, min_lod
, max_lod
;
89 if (s
->mipfilter
== SVGA3D_TEX_FILTER_NONE
) {
90 /* just use the base level image */
91 min_lod
= max_lod
= sv
->u
.tex
.first_level
;
94 last_level
= MIN2(sv
->u
.tex
.last_level
, sv
->texture
->last_level
);
95 min_lod
= s
->view_min_lod
+ sv
->u
.tex
.first_level
;
96 min_lod
= MIN2(min_lod
, last_level
);
97 max_lod
= MIN2(s
->view_max_lod
+ sv
->u
.tex
.first_level
, last_level
);
99 texture
= sv
->texture
;
106 if (view
->texture
!= texture
||
107 view
->min_lod
!= min_lod
||
108 view
->max_lod
!= max_lod
) {
110 svga_sampler_view_reference(&view
->v
, NULL
);
111 pipe_resource_reference(&view
->texture
, texture
);
114 view
->min_lod
= min_lod
;
115 view
->max_lod
= max_lod
;
118 view
->v
= svga_get_tex_sampler_view(&svga
->pipe
,
126 * We need to reemit non-null texture bindings, even when they are not
127 * dirty, to ensure that the resources are paged in.
129 if (view
->dirty
|| (reemit
&& view
->v
)) {
130 queue
->bind
[queue
->bind_count
].unit
= unit
;
131 queue
->bind
[queue
->bind_count
].view
= view
;
135 if (!view
->dirty
&& view
->v
) {
136 svga_validate_sampler_view(svga
, view
->v
);
141 static enum pipe_error
142 update_tss_binding(struct svga_context
*svga
, uint64_t dirty
)
144 const enum pipe_shader_type shader
= PIPE_SHADER_FRAGMENT
;
145 boolean reemit
= svga
->rebind
.flags
.texture_samplers
;
147 unsigned count
= MAX2(svga
->curr
.num_sampler_views
[shader
],
148 svga
->state
.hw_draw
.num_views
);
150 struct bind_queue queue
;
152 assert(!svga_have_vgpu10(svga
));
154 queue
.bind_count
= 0;
156 for (i
= 0; i
< count
; i
++) {
157 emit_tex_binding_unit(svga
, i
,
158 svga
->curr
.sampler
[shader
][i
],
159 svga
->curr
.sampler_views
[shader
][i
],
160 &svga
->state
.hw_draw
.views
[i
],
165 svga
->state
.hw_draw
.num_views
= svga
->curr
.num_sampler_views
[shader
];
167 /* Polygon stipple */
168 if (svga
->curr
.rast
->templ
.poly_stipple_enable
) {
169 const unsigned unit
=
170 svga_fs_variant(svga
->state
.hw_draw
.fs
)->pstipple_sampler_unit
;
171 emit_tex_binding_unit(svga
, unit
,
172 svga
->polygon_stipple
.sampler
,
173 &svga
->polygon_stipple
.sampler_view
->base
,
174 &svga
->state
.hw_draw
.views
[unit
],
179 svga
->state
.hw_draw
.num_backed_views
= 0;
181 if (queue
.bind_count
) {
182 SVGA3dTextureState
*ts
;
184 if (SVGA3D_BeginSetTextureState(svga
->swc
, &ts
,
185 queue
.bind_count
) != PIPE_OK
)
188 for (i
= 0; i
< queue
.bind_count
; i
++) {
189 struct svga_winsys_surface
*handle
;
190 struct svga_hw_view_state
*view
= queue
.bind
[i
].view
;
192 ts
[i
].stage
= queue
.bind
[i
].unit
;
193 ts
[i
].name
= SVGA3D_TS_BIND_TEXTURE
;
196 handle
= view
->v
->handle
;
198 /* Keep track of number of views with a backing copy
201 if (handle
!= svga_texture(view
->texture
)->handle
)
202 svga
->state
.hw_draw
.num_backed_views
++;
207 svga
->swc
->surface_relocation(svga
->swc
,
213 queue
.bind
[i
].view
->dirty
= FALSE
;
216 SVGA_FIFOCommitAll(svga
->swc
);
219 svga
->rebind
.flags
.texture_samplers
= FALSE
;
224 return PIPE_ERROR_OUT_OF_MEMORY
;
231 * Similar to update_tss_binding, but without any state checking/update.
233 * Called at the beginning of every new command buffer to ensure that
234 * non-dirty textures are properly paged-in.
237 svga_reemit_tss_bindings(struct svga_context
*svga
)
241 struct bind_queue queue
;
243 assert(!svga_have_vgpu10(svga
));
244 assert(svga
->rebind
.flags
.texture_samplers
);
246 queue
.bind_count
= 0;
248 for (i
= 0; i
< svga
->state
.hw_draw
.num_views
; i
++) {
249 struct svga_hw_view_state
*view
= &svga
->state
.hw_draw
.views
[i
];
252 queue
.bind
[queue
.bind_count
].unit
= i
;
253 queue
.bind
[queue
.bind_count
].view
= view
;
258 /* Polygon stipple */
259 if (svga
->curr
.rast
&& svga
->curr
.rast
->templ
.poly_stipple_enable
) {
260 const unsigned unit
=
261 svga_fs_variant(svga
->state
.hw_draw
.fs
)->pstipple_sampler_unit
;
262 struct svga_hw_view_state
*view
= &svga
->state
.hw_draw
.views
[unit
];
265 queue
.bind
[queue
.bind_count
].unit
= unit
;
266 queue
.bind
[queue
.bind_count
].view
= view
;
271 if (queue
.bind_count
) {
272 SVGA3dTextureState
*ts
;
274 ret
= SVGA3D_BeginSetTextureState(svga
->swc
, &ts
, queue
.bind_count
);
275 if (ret
!= PIPE_OK
) {
279 for (i
= 0; i
< queue
.bind_count
; i
++) {
280 struct svga_winsys_surface
*handle
;
282 ts
[i
].stage
= queue
.bind
[i
].unit
;
283 ts
[i
].name
= SVGA3D_TS_BIND_TEXTURE
;
285 assert(queue
.bind
[i
].view
->v
);
286 handle
= queue
.bind
[i
].view
->v
->handle
;
287 svga
->swc
->surface_relocation(svga
->swc
,
294 SVGA_FIFOCommitAll(svga
->swc
);
297 svga
->rebind
.flags
.texture_samplers
= FALSE
;
303 struct svga_tracked_state svga_hw_tss_binding
= {
304 "texture binding emit",
305 SVGA_NEW_FRAME_BUFFER
|
306 SVGA_NEW_TEXTURE_BINDING
|
316 SVGA3dTextureState ts
[PIPE_MAX_SAMPLERS
*SVGA3D_TS_MAX
];
321 svga_queue_tss(struct ts_queue
*q
, unsigned unit
, unsigned tss
, unsigned value
)
323 assert(q
->ts_count
< ARRAY_SIZE(q
->ts
));
324 q
->ts
[q
->ts_count
].stage
= unit
;
325 q
->ts
[q
->ts_count
].name
= tss
;
326 q
->ts
[q
->ts_count
].value
= value
;
331 #define EMIT_TS(svga, unit, val, token) \
333 assert(unit < ARRAY_SIZE(svga->state.hw_draw.ts)); \
334 STATIC_ASSERT(SVGA3D_TS_##token < ARRAY_SIZE(svga->state.hw_draw.ts[unit])); \
335 if (svga->state.hw_draw.ts[unit][SVGA3D_TS_##token] != val) { \
336 svga_queue_tss(queue, unit, SVGA3D_TS_##token, val); \
337 svga->state.hw_draw.ts[unit][SVGA3D_TS_##token] = val; \
341 #define EMIT_TS_FLOAT(svga, unit, fvalue, token) \
343 unsigned val = fui(fvalue); \
344 assert(unit < ARRAY_SIZE(svga->state.hw_draw.ts)); \
345 STATIC_ASSERT(SVGA3D_TS_##token < ARRAY_SIZE(svga->state.hw_draw.ts[unit])); \
346 if (svga->state.hw_draw.ts[unit][SVGA3D_TS_##token] != val) { \
347 svga_queue_tss(queue, unit, SVGA3D_TS_##token, val); \
348 svga->state.hw_draw.ts[unit][SVGA3D_TS_##token] = val; \
354 * Emit texture sampler state (tss) for one texture unit.
357 emit_tss_unit(struct svga_context
*svga
, unsigned unit
,
358 const struct svga_sampler_state
*state
,
359 struct ts_queue
*queue
)
361 EMIT_TS(svga
, unit
, state
->mipfilter
, MIPFILTER
);
362 EMIT_TS(svga
, unit
, state
->min_lod
, TEXTURE_MIPMAP_LEVEL
);
363 EMIT_TS(svga
, unit
, state
->magfilter
, MAGFILTER
);
364 EMIT_TS(svga
, unit
, state
->minfilter
, MINFILTER
);
365 EMIT_TS(svga
, unit
, state
->aniso_level
, TEXTURE_ANISOTROPIC_LEVEL
);
366 EMIT_TS_FLOAT(svga
, unit
, state
->lod_bias
, TEXTURE_LOD_BIAS
);
367 EMIT_TS(svga
, unit
, state
->addressu
, ADDRESSU
);
368 EMIT_TS(svga
, unit
, state
->addressw
, ADDRESSW
);
369 EMIT_TS(svga
, unit
, state
->bordercolor
, BORDERCOLOR
);
370 // TEXCOORDINDEX -- hopefully not needed
372 if (svga
->curr
.tex_flags
.flag_1d
& (1 << unit
))
373 EMIT_TS(svga
, unit
, SVGA3D_TEX_ADDRESS_WRAP
, ADDRESSV
);
375 EMIT_TS(svga
, unit
, state
->addressv
, ADDRESSV
);
377 if (svga
->curr
.tex_flags
.flag_srgb
& (1 << unit
))
378 EMIT_TS_FLOAT(svga
, unit
, 2.2f
, GAMMA
);
380 EMIT_TS_FLOAT(svga
, unit
, 1.0f
, GAMMA
);
383 static enum pipe_error
384 update_tss(struct svga_context
*svga
, uint64_t dirty
)
386 const enum pipe_shader_type shader
= PIPE_SHADER_FRAGMENT
;
388 struct ts_queue queue
;
390 assert(!svga_have_vgpu10(svga
));
393 for (i
= 0; i
< svga
->curr
.num_samplers
[shader
]; i
++) {
394 if (svga
->curr
.sampler
[shader
][i
]) {
395 const struct svga_sampler_state
*curr
= svga
->curr
.sampler
[shader
][i
];
396 emit_tss_unit(svga
, i
, curr
, &queue
);
400 /* polygon stipple sampler */
401 if (svga
->curr
.rast
->templ
.poly_stipple_enable
) {
403 svga_fs_variant(svga
->state
.hw_draw
.fs
)->pstipple_sampler_unit
,
404 svga
->polygon_stipple
.sampler
,
408 if (queue
.ts_count
) {
409 SVGA3dTextureState
*ts
;
411 if (SVGA3D_BeginSetTextureState(svga
->swc
, &ts
, queue
.ts_count
) != PIPE_OK
)
414 memcpy(ts
, queue
.ts
, queue
.ts_count
* sizeof queue
.ts
[0]);
416 SVGA_FIFOCommitAll(svga
->swc
);
422 /* XXX: need to poison cached hardware state on failure to ensure
423 * dirty state gets re-emitted. Fix this by re-instating partial
424 * FIFOCommit command and only updating cached hw state once the
425 * initial allocation has succeeded.
427 memset(svga
->state
.hw_draw
.ts
, 0xcd, sizeof(svga
->state
.hw_draw
.ts
));
429 return PIPE_ERROR_OUT_OF_MEMORY
;
433 struct svga_tracked_state svga_hw_tss
= {
434 "texture state emit",
437 SVGA_NEW_TEXTURE_FLAGS
),