src/gallium/drivers/svga/svga_tgsi_emit.h

   1 /**********************************************************
   2  * Copyright 2008-2009 VMware, Inc.  All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person
   5  * obtaining a copy of this software and associated documentation
   6  * files (the "Software"), to deal in the Software without
   7  * restriction, including without limitation the rights to use, copy,
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   9  * of the Software, and to permit persons to whom the Software is
  10  * furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be
  13  * included in all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  16  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  17  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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  22  * SOFTWARE.
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  24  **********************************************************/
  25
  26 #ifndef SVGA_TGSI_EMIT_H
  27 #define SVGA_TGSI_EMIT_H
  28
  29 #include "tgsi/tgsi_scan.h"
  30 #include "svga_hw_reg.h"
  31 #include "svga_shader.h"
  32 #include "svga_tgsi.h"
  33 #include "svga3d_shaderdefs.h"
  34
  35 struct src_register
  36 {
  37    SVGA3dShaderSrcToken base;
  38    SVGA3dShaderSrcToken indirect;
  39 };
  40
  41
  42 struct svga_arl_consts
  43 {
  44    int number;
  45    int idx;
  46    int swizzle;
  47    int arl_num;
  48 };
  49
  50
  51 /**
  52  * This is the context/state used during TGSI->SVGA shader translation.
  53  */
  54 struct svga_shader_emitter
  55 {
  56    unsigned size;
  57    char *buf;
  58    char *ptr;
  59
  60    struct svga_compile_key key;
  61    struct tgsi_shader_info info;
  62    int unit;
  63
  64    int imm_start;
  65
  66    int nr_hw_float_const;
  67    int nr_hw_int_const;
  68    int nr_hw_temp;
  69
  70    int insn_offset;
  71
  72    int internal_temp_count;
  73    int internal_imm_count;
  74
  75    int internal_color_idx[2]; /* diffuse, specular */
  76    int internal_color_count;
  77
  78    boolean emitted_vface;
  79    boolean emit_frontface;
  80    int internal_frontface_idx;
  81
  82    int ps30_input_count;
  83    int vs30_output_count;
  84
  85    int dynamic_branching_level;
  86
  87    unsigned num_output_writes;
  88    boolean constant_color_output;
  89
  90    boolean in_main_func;
  91
  92    boolean created_common_immediate;
  93    int common_immediate_idx[2];
  94
  95    boolean created_loop_const;
  96    int loop_const_idx;
  97
  98    unsigned inverted_texcoords;  /**< bitmask of which texcoords are flipped */
  99    struct src_register ps_true_texcoord[PIPE_MAX_ATTRIBS];
 100    struct src_register ps_inverted_texcoord[PIPE_MAX_ATTRIBS];
 101    unsigned ps_inverted_texcoord_input[PIPE_MAX_ATTRIBS];
 102
 103    unsigned label[32];
 104    unsigned nr_labels;
 105
 106    /** input/output register mappings, indexed by register number */
 107    struct src_register input_map[PIPE_MAX_ATTRIBS];
 108    SVGA3dShaderDestToken output_map[PIPE_MAX_ATTRIBS];
 109
 110    boolean ps_reads_pos;
 111    boolean emitted_depth_fog;
 112    struct src_register ps_true_pos;
 113    struct src_register ps_depth_pos;
 114    SVGA3dShaderDestToken ps_temp_pos;
 115
 116    /* shared input for depth and fog */
 117    struct src_register ps_depth_fog;
 118
 119    struct src_register imm_0055;
 120    SVGA3dShaderDestToken temp_pos;
 121    SVGA3dShaderDestToken true_pos;
 122    SVGA3dShaderDestToken depth_pos;
 123
 124    /* shared output for depth and fog */
 125    SVGA3dShaderDestToken vs_depth_fog;
 126
 127    /* PS output colors (indexed by color semantic index) */
 128    SVGA3dShaderDestToken temp_color_output[PIPE_MAX_COLOR_BUFS];
 129    SVGA3dShaderDestToken true_color_output[PIPE_MAX_COLOR_BUFS];
 130
 131    SVGA3dShaderDestToken temp_psiz;
 132    SVGA3dShaderDestToken true_psiz;
 133
 134    struct svga_arl_consts arl_consts[12];
 135    int num_arl_consts;
 136    int current_arl;
 137
 138    unsigned pstipple_sampler_unit;
 139 };
 140
 141
 142 boolean
 143 svga_shader_emit_dword(struct svga_shader_emitter *emit, unsigned dword);
 144
 145 boolean
 146 svga_shader_emit_dwords(struct svga_shader_emitter *emit,
 147                         const unsigned *dwords, unsigned nr);
 148
 149 boolean
 150 svga_shader_emit_opcode(struct svga_shader_emitter *emit,
 151                         unsigned opcode);
 152
 153 boolean
 154 svga_shader_emit_instructions(struct svga_shader_emitter *emit,
 155                               const struct tgsi_token *tokens);
 156
 157 boolean
 158 svga_translate_decl_sm30(struct svga_shader_emitter *emit,
 159                          const struct tgsi_full_declaration *decl);
 160
 161
 162 #define TRANSLATE_SWIZZLE(x,y,z,w)  ((x) | ((y) << 2) | ((z) << 4) | ((w) << 6))
 163 #define SWIZZLE_XYZW  \
 164  TRANSLATE_SWIZZLE(TGSI_SWIZZLE_X,TGSI_SWIZZLE_Y,TGSI_SWIZZLE_Z,TGSI_SWIZZLE_W)
 165 #define SWIZZLE_XXXX  \
 166  TRANSLATE_SWIZZLE(TGSI_SWIZZLE_X,TGSI_SWIZZLE_X,TGSI_SWIZZLE_X,TGSI_SWIZZLE_X)
 167 #define SWIZZLE_YYYY  \
 168  TRANSLATE_SWIZZLE(TGSI_SWIZZLE_Y,TGSI_SWIZZLE_Y,TGSI_SWIZZLE_Y,TGSI_SWIZZLE_Y)
 169 #define SWIZZLE_ZZZZ  \
 170  TRANSLATE_SWIZZLE(TGSI_SWIZZLE_Z,TGSI_SWIZZLE_Z,TGSI_SWIZZLE_Z,TGSI_SWIZZLE_Z)
 171 #define SWIZZLE_WWWW  \
 172  TRANSLATE_SWIZZLE(TGSI_SWIZZLE_W,TGSI_SWIZZLE_W,TGSI_SWIZZLE_W,TGSI_SWIZZLE_W)
 173
 174
 175 /** Emit the given SVGA3dShaderInstToken opcode */
 176 static inline boolean
 177 emit_instruction(struct svga_shader_emitter *emit,
 178                  SVGA3dShaderInstToken opcode)
 179 {
 180    return svga_shader_emit_opcode(emit, opcode.value);
 181 }
 182
 183
 184 /** Generate a SVGA3dShaderInstToken for the given SVGA3D shader opcode */
 185 static inline SVGA3dShaderInstToken
 186 inst_token(unsigned opcode)
 187 {
 188    SVGA3dShaderInstToken inst;
 189
 190    inst.value = 0;
 191    inst.op = opcode;
 192
 193    return inst;
 194 }
 195
 196
 197 /**
 198  * Generate a SVGA3dShaderInstToken for the given SVGA3D shader opcode
 199  * with the predication flag set.
 200  */
 201 static inline SVGA3dShaderInstToken
 202 inst_token_predicated(unsigned opcode)
 203 {
 204    SVGA3dShaderInstToken inst;
 205
 206    inst.value = 0;
 207    inst.op = opcode;
 208    inst.predicated = 1;
 209
 210    return inst;
 211 }
 212
 213
 214 /**
 215  * Generate a SVGA3dShaderInstToken for a SETP instruction (set predicate)
 216  * using the given comparison operator (one of SVGA3DOPCOMP_xx).
 217  */
 218 static inline SVGA3dShaderInstToken
 219 inst_token_setp(unsigned operator)
 220 {
 221    SVGA3dShaderInstToken inst;
 222
 223    inst.value = 0;
 224    inst.op = SVGA3DOP_SETP;
 225    inst.control = operator;
 226
 227    return inst;
 228 }
 229
 230
 231 /**
 232  * Create an instance of a SVGA3dShaderDestToken.
 233  * Note that this function is used to create tokens for output registers,
 234  * temp registers AND constants (see emit_def_const()).
 235  */
 236 static inline SVGA3dShaderDestToken
 237 dst_register(unsigned file, int number)
 238 {
 239    SVGA3dShaderDestToken dest;
 240
 241    /* check values against bitfield sizes */
 242    assert(number < (1 << 11));
 243    assert(file <= SVGA3DREG_PREDICATE);
 244
 245    dest.value = 0;
 246    dest.num = number;
 247    dest.type_upper = file >> 3;
 248    dest.relAddr = 0;
 249    dest.reserved1 = 0;
 250    dest.mask = 0xf;
 251    dest.dstMod = 0;
 252    dest.shfScale = 0;
 253    dest.type_lower = file & 0x7;
 254    dest.reserved0 = 1;          /* is_reg */
 255
 256    return dest;
 257 }
 258
 259
 260 /**
 261  * Apply a writemask to the given SVGA3dShaderDestToken, returning a
 262  * new SVGA3dShaderDestToken.
 263  */
 264 static inline SVGA3dShaderDestToken
 265 writemask(SVGA3dShaderDestToken dest, unsigned mask)
 266 {
 267    assert(dest.mask & mask);
 268    dest.mask &= mask;
 269    return dest;
 270 }
 271
 272
 273 /** Create a SVGA3dShaderSrcToken given a register file and number */
 274 static inline SVGA3dShaderSrcToken
 275 src_token(unsigned file, int number)
 276 {
 277    SVGA3dShaderSrcToken src;
 278
 279    /* check values against bitfield sizes */
 280    assert(number < (1 << 11));
 281    assert(file <= SVGA3DREG_PREDICATE);
 282
 283    src.value = 0;
 284    src.num = number;
 285    src.type_upper = file >> 3;
 286    src.relAddr = 0;
 287    src.reserved1 = 0;
 288    src.swizzle = SWIZZLE_XYZW;
 289    src.srcMod = 0;
 290    src.type_lower = file & 0x7;
 291    src.reserved0 = 1;           /* is_reg */
 292
 293    return src;
 294 }
 295
 296
 297 /** Create a src_register given a register file and register number */
 298 static inline struct src_register
 299 src_register(unsigned file, int number)
 300 {
 301    struct src_register src;
 302
 303    src.base = src_token(file, number);
 304    src.indirect.value = 0;
 305
 306    return src;
 307 }
 308
 309 /** Translate src_register into SVGA3dShaderDestToken */
 310 static inline SVGA3dShaderDestToken
 311 dst(struct src_register src)
 312 {
 313    return dst_register(SVGA3dShaderGetRegType(src.base.value), src.base.num);
 314 }
 315
 316
 317 /** Translate SVGA3dShaderDestToken to a src_register */
 318 static inline struct src_register
 319 src(SVGA3dShaderDestToken dst)
 320 {
 321    return src_register(SVGA3dShaderGetRegType(dst.value), dst.num);
 322 }
 323
 324 #endif