src/gallium/drivers/svga/svga_tgsi_emit.h

   1 /**********************************************************
   2  * Copyright 2008-2009 VMware, Inc.  All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person
   5  * obtaining a copy of this software and associated documentation
   6  * files (the "Software"), to deal in the Software without
   7  * restriction, including without limitation the rights to use, copy,
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   9  * of the Software, and to permit persons to whom the Software is
  10  * furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be
  13  * included in all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  16  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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  22  * SOFTWARE.
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  24  **********************************************************/
  25
  26 #ifndef SVGA_TGSI_EMIT_H
  27 #define SVGA_TGSI_EMIT_H
  28
  29 #include "tgsi/tgsi_scan.h"
  30 #include "svga_hw_reg.h"
  31 #include "svga_tgsi.h"
  32 #include "svga3d_shaderdefs.h"
  33
  34 struct src_register
  35 {
  36    SVGA3dShaderSrcToken base;
  37    SVGA3dShaderSrcToken indirect;
  38 };
  39
  40
  41 struct svga_arl_consts
  42 {
  43    int number;
  44    int idx;
  45    int swizzle;
  46    int arl_num;
  47 };
  48
  49
  50 /**
  51  * This is the context/state used during TGSI->SVGA shader translation.
  52  */
  53 struct svga_shader_emitter
  54 {
  55    unsigned size;
  56    char *buf;
  57    char *ptr;
  58
  59    struct svga_compile_key key;
  60    struct tgsi_shader_info info;
  61    int unit;
  62
  63    int imm_start;
  64
  65    int nr_hw_float_const;
  66    int nr_hw_int_const;
  67    int nr_hw_temp;
  68
  69    int insn_offset;
  70
  71    int internal_temp_count;
  72    int internal_imm_count;
  73
  74    int internal_color_idx[2]; /* diffuse, specular */
  75    int internal_color_count;
  76
  77    boolean emitted_vface;
  78    boolean emit_frontface;
  79    int internal_frontface_idx;
  80
  81    int ps30_input_count;
  82    int vs30_output_count;
  83
  84    int dynamic_branching_level;
  85
  86    boolean in_main_func;
  87
  88    boolean created_common_immediate;
  89    int common_immediate_idx;
  90
  91    boolean created_loop_const;
  92    int loop_const_idx;
  93
  94    unsigned inverted_texcoords;  /**< bitmask of which texcoords are flipped */
  95    struct src_register ps_true_texcoord[PIPE_MAX_ATTRIBS];
  96    struct src_register ps_inverted_texcoord[PIPE_MAX_ATTRIBS];
  97    unsigned ps_inverted_texcoord_input[PIPE_MAX_ATTRIBS];
  98
  99    unsigned label[32];
 100    unsigned nr_labels;
 101
 102    /** input/output register mappings, indexed by register number */
 103    struct src_register input_map[PIPE_MAX_ATTRIBS];
 104    SVGA3dShaderDestToken output_map[PIPE_MAX_ATTRIBS];
 105
 106    boolean ps_reads_pos;
 107    boolean emitted_depth_fog;
 108    struct src_register ps_true_pos;
 109    struct src_register ps_depth_pos;
 110    SVGA3dShaderDestToken ps_temp_pos;
 111
 112    /* shared input for depth and fog */
 113    struct src_register ps_depth_fog;
 114
 115    struct src_register imm_0055;
 116    SVGA3dShaderDestToken temp_pos;
 117    SVGA3dShaderDestToken true_pos;
 118    SVGA3dShaderDestToken depth_pos;
 119
 120    /* shared output for depth and fog */
 121    SVGA3dShaderDestToken vs_depth_fog;
 122
 123    /* PS output colors (indexed by color semantic index) */
 124    SVGA3dShaderDestToken temp_color_output[PIPE_MAX_COLOR_BUFS];
 125    SVGA3dShaderDestToken true_color_output[PIPE_MAX_COLOR_BUFS];
 126
 127    SVGA3dShaderDestToken temp_psiz;
 128    SVGA3dShaderDestToken true_psiz;
 129
 130    struct svga_arl_consts arl_consts[12];
 131    int num_arl_consts;
 132    int current_arl;
 133 };
 134
 135
 136 boolean
 137 svga_shader_emit_dword(struct svga_shader_emitter *emit, unsigned dword);
 138
 139 boolean
 140 svga_shader_emit_dwords(struct svga_shader_emitter *emit,
 141                         const unsigned *dwords, unsigned nr);
 142
 143 boolean
 144 svga_shader_emit_opcode(struct svga_shader_emitter *emit,
 145                         unsigned opcode);
 146
 147 boolean
 148 svga_shader_emit_instructions(struct svga_shader_emitter *emit,
 149                               const struct tgsi_token *tokens);
 150
 151 boolean
 152 svga_translate_decl_sm30(struct svga_shader_emitter *emit,
 153                          const struct tgsi_full_declaration *decl);
 154
 155
 156 #define TRANSLATE_SWIZZLE(x,y,z,w)  ((x) | ((y) << 2) | ((z) << 4) | ((w) << 6))
 157 #define SWIZZLE_XYZW  \
 158  TRANSLATE_SWIZZLE(TGSI_SWIZZLE_X,TGSI_SWIZZLE_Y,TGSI_SWIZZLE_Z,TGSI_SWIZZLE_W)
 159 #define SWIZZLE_XXXX  \
 160  TRANSLATE_SWIZZLE(TGSI_SWIZZLE_X,TGSI_SWIZZLE_X,TGSI_SWIZZLE_X,TGSI_SWIZZLE_X)
 161 #define SWIZZLE_YYYY  \
 162  TRANSLATE_SWIZZLE(TGSI_SWIZZLE_Y,TGSI_SWIZZLE_Y,TGSI_SWIZZLE_Y,TGSI_SWIZZLE_Y)
 163 #define SWIZZLE_ZZZZ  \
 164  TRANSLATE_SWIZZLE(TGSI_SWIZZLE_Z,TGSI_SWIZZLE_Z,TGSI_SWIZZLE_Z,TGSI_SWIZZLE_Z)
 165 #define SWIZZLE_WWWW  \
 166  TRANSLATE_SWIZZLE(TGSI_SWIZZLE_W,TGSI_SWIZZLE_W,TGSI_SWIZZLE_W,TGSI_SWIZZLE_W)
 167
 168
 169 /** Emit the given SVGA3dShaderInstToken opcode */
 170 static INLINE boolean
 171 emit_instruction(struct svga_shader_emitter *emit,
 172                  SVGA3dShaderInstToken opcode)
 173 {
 174    return svga_shader_emit_opcode(emit, opcode.value);
 175 }
 176
 177
 178 /** Generate a SVGA3dShaderInstToken for the given SVGA3D shader opcode */
 179 static INLINE SVGA3dShaderInstToken
 180 inst_token(unsigned opcode)
 181 {
 182    SVGA3dShaderInstToken inst;
 183
 184    inst.value = 0;
 185    inst.op = opcode;
 186
 187    return inst;
 188 }
 189
 190
 191 /**
 192  * Generate a SVGA3dShaderInstToken for the given SVGA3D shader opcode
 193  * with the predication flag set.
 194  */
 195 static INLINE SVGA3dShaderInstToken
 196 inst_token_predicated(unsigned opcode)
 197 {
 198    SVGA3dShaderInstToken inst;
 199
 200    inst.value = 0;
 201    inst.op = opcode;
 202    inst.predicated = 1;
 203
 204    return inst;
 205 }
 206
 207
 208 /**
 209  * Generate a SVGA3dShaderInstToken for a SETP instruction (set predicate)
 210  * using the given comparison operator (one of SVGA3DOPCOMP_xx).
 211  */
 212 static INLINE SVGA3dShaderInstToken
 213 inst_token_setp(unsigned operator)
 214 {
 215    SVGA3dShaderInstToken inst;
 216
 217    inst.value = 0;
 218    inst.op = SVGA3DOP_SETP;
 219    inst.control = operator;
 220
 221    return inst;
 222 }
 223
 224
 225 /**
 226  * Create an instance of a SVGA3dShaderDestToken.
 227  * Note that this function is used to create tokens for output registers,
 228  * temp registers AND constants (see emit_def_const()).
 229  */
 230 static INLINE SVGA3dShaderDestToken
 231 dst_register(unsigned file, int number)
 232 {
 233    SVGA3dShaderDestToken dest;
 234
 235    /* check values against bitfield sizes */
 236    assert(number < (1 << 11));
 237    assert(file <= SVGA3DREG_PREDICATE);
 238
 239    dest.value = 0;
 240    dest.num = number;
 241    dest.type_upper = file >> 3;
 242    dest.relAddr = 0;
 243    dest.reserved1 = 0;
 244    dest.mask = 0xf;
 245    dest.dstMod = 0;
 246    dest.shfScale = 0;
 247    dest.type_lower = file & 0x7;
 248    dest.reserved0 = 1;          /* is_reg */
 249
 250    return dest;
 251 }
 252
 253
 254 /**
 255  * Apply a writemask to the given SVGA3dShaderDestToken, returning a
 256  * new SVGA3dShaderDestToken.
 257  */
 258 static INLINE SVGA3dShaderDestToken
 259 writemask(SVGA3dShaderDestToken dest, unsigned mask)
 260 {
 261    assert(dest.mask & mask);
 262    dest.mask &= mask;
 263    return dest;
 264 }
 265
 266
 267 /** Create a SVGA3dShaderSrcToken given a register file and number */
 268 static INLINE SVGA3dShaderSrcToken
 269 src_token(unsigned file, int number)
 270 {
 271    SVGA3dShaderSrcToken src;
 272
 273    /* check values against bitfield sizes */
 274    assert(number < (1 << 11));
 275    assert(file <= SVGA3DREG_PREDICATE);
 276
 277    src.value = 0;
 278    src.num = number;
 279    src.type_upper = file >> 3;
 280    src.relAddr = 0;
 281    src.reserved1 = 0;
 282    src.swizzle = SWIZZLE_XYZW;
 283    src.srcMod = 0;
 284    src.type_lower = file & 0x7;
 285    src.reserved0 = 1;           /* is_reg */
 286
 287    return src;
 288 }
 289
 290
 291 /** Create a src_register given a register file and register number */
 292 static INLINE struct src_register
 293 src_register(unsigned file, int number)
 294 {
 295    struct src_register src;
 296
 297    src.base = src_token(file, number);
 298    src.indirect.value = 0;
 299
 300    return src;
 301 }
 302
 303 /** Translate src_register into SVGA3dShaderDestToken */
 304 static INLINE SVGA3dShaderDestToken
 305 dst(struct src_register src)
 306 {
 307    return dst_register(SVGA3dShaderGetRegType(src.base.value), src.base.num);
 308 }
 309
 310
 311 /** Translate SVGA3dShaderDestToken to a src_register */
 312 static INLINE struct src_register
 313 src(SVGA3dShaderDestToken dst)
 314 {
 315    return src_register(SVGA3dShaderGetRegType(dst.value), dst.num);
 316 }
 317
 318 #endif