src/gallium/drivers/svga/svga_tgsi_emit.h

   1 /**********************************************************
   2  * Copyright 2008-2009 VMware, Inc.  All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person
   5  * obtaining a copy of this software and associated documentation
   6  * files (the "Software"), to deal in the Software without
   7  * restriction, including without limitation the rights to use, copy,
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   9  * of the Software, and to permit persons to whom the Software is
  10  * furnished to do so, subject to the following conditions:
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  12  * The above copyright notice and this permission notice shall be
  13  * included in all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  16  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  17  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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  22  * SOFTWARE.
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  24  **********************************************************/
  25
  26 #ifndef SVGA_TGSI_EMIT_H
  27 #define SVGA_TGSI_EMIT_H
  28
  29 #include "tgsi/tgsi_scan.h"
  30 #include "svga_hw_reg.h"
  31 #include "svga_shader.h"
  32 #include "svga_tgsi.h"
  33 #include "svga3d_shaderdefs.h"
  34
  35 struct src_register
  36 {
  37    SVGA3dShaderSrcToken base;
  38    SVGA3dShaderSrcToken indirect;
  39 };
  40
  41
  42 struct svga_arl_consts
  43 {
  44    int number;
  45    int idx;
  46    int swizzle;
  47    int arl_num;
  48 };
  49
  50
  51 /**
  52  * This is the context/state used during TGSI->SVGA shader translation.
  53  */
  54 struct svga_shader_emitter
  55 {
  56    unsigned size;
  57    char *buf;
  58    char *ptr;
  59
  60    struct svga_compile_key key;
  61    struct tgsi_shader_info info;
  62    int unit;
  63
  64    int imm_start;
  65
  66    int nr_hw_float_const;
  67    int nr_hw_int_const;
  68    int nr_hw_temp;
  69
  70    int insn_offset;
  71
  72    int internal_temp_count;
  73    int internal_imm_count;
  74
  75    int internal_color_idx[2]; /* diffuse, specular */
  76    int internal_color_count;
  77
  78    boolean emitted_vface;
  79    boolean emit_frontface;
  80    int internal_frontface_idx;
  81
  82    int ps30_input_count;
  83    int vs30_output_count;
  84
  85    int dynamic_branching_level;
  86
  87    boolean in_main_func;
  88
  89    boolean created_common_immediate;
  90    int common_immediate_idx[2];
  91
  92    boolean created_loop_const;
  93    int loop_const_idx;
  94
  95    unsigned inverted_texcoords;  /**< bitmask of which texcoords are flipped */
  96    struct src_register ps_true_texcoord[PIPE_MAX_ATTRIBS];
  97    struct src_register ps_inverted_texcoord[PIPE_MAX_ATTRIBS];
  98    unsigned ps_inverted_texcoord_input[PIPE_MAX_ATTRIBS];
  99
 100    unsigned label[32];
 101    unsigned nr_labels;
 102
 103    /** input/output register mappings, indexed by register number */
 104    struct src_register input_map[PIPE_MAX_ATTRIBS];
 105    SVGA3dShaderDestToken output_map[PIPE_MAX_ATTRIBS];
 106
 107    boolean ps_reads_pos;
 108    boolean emitted_depth_fog;
 109    struct src_register ps_true_pos;
 110    struct src_register ps_depth_pos;
 111    SVGA3dShaderDestToken ps_temp_pos;
 112
 113    /* shared input for depth and fog */
 114    struct src_register ps_depth_fog;
 115
 116    struct src_register imm_0055;
 117    SVGA3dShaderDestToken temp_pos;
 118    SVGA3dShaderDestToken true_pos;
 119    SVGA3dShaderDestToken depth_pos;
 120
 121    /* shared output for depth and fog */
 122    SVGA3dShaderDestToken vs_depth_fog;
 123
 124    /* PS output colors (indexed by color semantic index) */
 125    SVGA3dShaderDestToken temp_color_output[PIPE_MAX_COLOR_BUFS];
 126    SVGA3dShaderDestToken true_color_output[PIPE_MAX_COLOR_BUFS];
 127
 128    SVGA3dShaderDestToken temp_psiz;
 129    SVGA3dShaderDestToken true_psiz;
 130
 131    struct svga_arl_consts arl_consts[12];
 132    int num_arl_consts;
 133    int current_arl;
 134
 135    unsigned pstipple_sampler_unit;
 136 };
 137
 138
 139 boolean
 140 svga_shader_emit_dword(struct svga_shader_emitter *emit, unsigned dword);
 141
 142 boolean
 143 svga_shader_emit_dwords(struct svga_shader_emitter *emit,
 144                         const unsigned *dwords, unsigned nr);
 145
 146 boolean
 147 svga_shader_emit_opcode(struct svga_shader_emitter *emit,
 148                         unsigned opcode);
 149
 150 boolean
 151 svga_shader_emit_instructions(struct svga_shader_emitter *emit,
 152                               const struct tgsi_token *tokens);
 153
 154 boolean
 155 svga_translate_decl_sm30(struct svga_shader_emitter *emit,
 156                          const struct tgsi_full_declaration *decl);
 157
 158
 159 #define TRANSLATE_SWIZZLE(x,y,z,w)  ((x) | ((y) << 2) | ((z) << 4) | ((w) << 6))
 160 #define SWIZZLE_XYZW  \
 161  TRANSLATE_SWIZZLE(TGSI_SWIZZLE_X,TGSI_SWIZZLE_Y,TGSI_SWIZZLE_Z,TGSI_SWIZZLE_W)
 162 #define SWIZZLE_XXXX  \
 163  TRANSLATE_SWIZZLE(TGSI_SWIZZLE_X,TGSI_SWIZZLE_X,TGSI_SWIZZLE_X,TGSI_SWIZZLE_X)
 164 #define SWIZZLE_YYYY  \
 165  TRANSLATE_SWIZZLE(TGSI_SWIZZLE_Y,TGSI_SWIZZLE_Y,TGSI_SWIZZLE_Y,TGSI_SWIZZLE_Y)
 166 #define SWIZZLE_ZZZZ  \
 167  TRANSLATE_SWIZZLE(TGSI_SWIZZLE_Z,TGSI_SWIZZLE_Z,TGSI_SWIZZLE_Z,TGSI_SWIZZLE_Z)
 168 #define SWIZZLE_WWWW  \
 169  TRANSLATE_SWIZZLE(TGSI_SWIZZLE_W,TGSI_SWIZZLE_W,TGSI_SWIZZLE_W,TGSI_SWIZZLE_W)
 170
 171
 172 /** Emit the given SVGA3dShaderInstToken opcode */
 173 static inline boolean
 174 emit_instruction(struct svga_shader_emitter *emit,
 175                  SVGA3dShaderInstToken opcode)
 176 {
 177    return svga_shader_emit_opcode(emit, opcode.value);
 178 }
 179
 180
 181 /** Generate a SVGA3dShaderInstToken for the given SVGA3D shader opcode */
 182 static inline SVGA3dShaderInstToken
 183 inst_token(unsigned opcode)
 184 {
 185    SVGA3dShaderInstToken inst;
 186
 187    inst.value = 0;
 188    inst.op = opcode;
 189
 190    return inst;
 191 }
 192
 193
 194 /**
 195  * Generate a SVGA3dShaderInstToken for the given SVGA3D shader opcode
 196  * with the predication flag set.
 197  */
 198 static inline SVGA3dShaderInstToken
 199 inst_token_predicated(unsigned opcode)
 200 {
 201    SVGA3dShaderInstToken inst;
 202
 203    inst.value = 0;
 204    inst.op = opcode;
 205    inst.predicated = 1;
 206
 207    return inst;
 208 }
 209
 210
 211 /**
 212  * Generate a SVGA3dShaderInstToken for a SETP instruction (set predicate)
 213  * using the given comparison operator (one of SVGA3DOPCOMP_xx).
 214  */
 215 static inline SVGA3dShaderInstToken
 216 inst_token_setp(unsigned operator)
 217 {
 218    SVGA3dShaderInstToken inst;
 219
 220    inst.value = 0;
 221    inst.op = SVGA3DOP_SETP;
 222    inst.control = operator;
 223
 224    return inst;
 225 }
 226
 227
 228 /**
 229  * Create an instance of a SVGA3dShaderDestToken.
 230  * Note that this function is used to create tokens for output registers,
 231  * temp registers AND constants (see emit_def_const()).
 232  */
 233 static inline SVGA3dShaderDestToken
 234 dst_register(unsigned file, int number)
 235 {
 236    SVGA3dShaderDestToken dest;
 237
 238    /* check values against bitfield sizes */
 239    assert(number < (1 << 11));
 240    assert(file <= SVGA3DREG_PREDICATE);
 241
 242    dest.value = 0;
 243    dest.num = number;
 244    dest.type_upper = file >> 3;
 245    dest.relAddr = 0;
 246    dest.reserved1 = 0;
 247    dest.mask = 0xf;
 248    dest.dstMod = 0;
 249    dest.shfScale = 0;
 250    dest.type_lower = file & 0x7;
 251    dest.reserved0 = 1;          /* is_reg */
 252
 253    return dest;
 254 }
 255
 256
 257 /**
 258  * Apply a writemask to the given SVGA3dShaderDestToken, returning a
 259  * new SVGA3dShaderDestToken.
 260  */
 261 static inline SVGA3dShaderDestToken
 262 writemask(SVGA3dShaderDestToken dest, unsigned mask)
 263 {
 264    assert(dest.mask & mask);
 265    dest.mask &= mask;
 266    return dest;
 267 }
 268
 269
 270 /** Create a SVGA3dShaderSrcToken given a register file and number */
 271 static inline SVGA3dShaderSrcToken
 272 src_token(unsigned file, int number)
 273 {
 274    SVGA3dShaderSrcToken src;
 275
 276    /* check values against bitfield sizes */
 277    assert(number < (1 << 11));
 278    assert(file <= SVGA3DREG_PREDICATE);
 279
 280    src.value = 0;
 281    src.num = number;
 282    src.type_upper = file >> 3;
 283    src.relAddr = 0;
 284    src.reserved1 = 0;
 285    src.swizzle = SWIZZLE_XYZW;
 286    src.srcMod = 0;
 287    src.type_lower = file & 0x7;
 288    src.reserved0 = 1;           /* is_reg */
 289
 290    return src;
 291 }
 292
 293
 294 /** Create a src_register given a register file and register number */
 295 static inline struct src_register
 296 src_register(unsigned file, int number)
 297 {
 298    struct src_register src;
 299
 300    src.base = src_token(file, number);
 301    src.indirect.value = 0;
 302
 303    return src;
 304 }
 305
 306 /** Translate src_register into SVGA3dShaderDestToken */
 307 static inline SVGA3dShaderDestToken
 308 dst(struct src_register src)
 309 {
 310    return dst_register(SVGA3dShaderGetRegType(src.base.value), src.base.num);
 311 }
 312
 313
 314 /** Translate SVGA3dShaderDestToken to a src_register */
 315 static inline struct src_register
 316 src(SVGA3dShaderDestToken dst)
 317 {
 318    return src_register(SVGA3dShaderGetRegType(dst.value), dst.num);
 319 }
 320
 321 #endif