1 /**********************************************************
2 * Copyright 2008-2009 VMware, Inc. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 **********************************************************/
27 #include "pipe/p_shader_tokens.h"
28 #include "tgsi/tgsi_dump.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/u_memory.h"
31 #include "util/u_math.h"
32 #include "util/u_pstipple.h"
34 #include "svga_tgsi_emit.h"
35 #include "svga_context.h"
38 static boolean
emit_vs_postamble( struct svga_shader_emitter
*emit
);
39 static boolean
emit_ps_postamble( struct svga_shader_emitter
*emit
);
42 static SVGA3dShaderOpCodeType
43 translate_opcode(enum tgsi_opcode opcode
)
46 case TGSI_OPCODE_ADD
: return SVGA3DOP_ADD
;
47 case TGSI_OPCODE_DP3
: return SVGA3DOP_DP3
;
48 case TGSI_OPCODE_DP4
: return SVGA3DOP_DP4
;
49 case TGSI_OPCODE_FRC
: return SVGA3DOP_FRC
;
50 case TGSI_OPCODE_MAD
: return SVGA3DOP_MAD
;
51 case TGSI_OPCODE_MAX
: return SVGA3DOP_MAX
;
52 case TGSI_OPCODE_MIN
: return SVGA3DOP_MIN
;
53 case TGSI_OPCODE_MOV
: return SVGA3DOP_MOV
;
54 case TGSI_OPCODE_MUL
: return SVGA3DOP_MUL
;
55 case TGSI_OPCODE_NOP
: return SVGA3DOP_NOP
;
57 assert(!"svga: unexpected opcode in translate_opcode()");
58 return SVGA3DOP_LAST_INST
;
63 static SVGA3dShaderRegType
64 translate_file(enum tgsi_file_type file
)
67 case TGSI_FILE_TEMPORARY
: return SVGA3DREG_TEMP
;
68 case TGSI_FILE_INPUT
: return SVGA3DREG_INPUT
;
69 case TGSI_FILE_OUTPUT
: return SVGA3DREG_OUTPUT
; /* VS3.0+ only */
70 case TGSI_FILE_IMMEDIATE
: return SVGA3DREG_CONST
;
71 case TGSI_FILE_CONSTANT
: return SVGA3DREG_CONST
;
72 case TGSI_FILE_SAMPLER
: return SVGA3DREG_SAMPLER
;
73 case TGSI_FILE_ADDRESS
: return SVGA3DREG_ADDR
;
75 assert(!"svga: unexpected register file in translate_file()");
76 return SVGA3DREG_TEMP
;
82 * Translate a TGSI destination register to an SVGA3DShaderDestToken.
83 * \param insn the TGSI instruction
84 * \param idx which TGSI dest register to translate (usually (always?) zero)
86 static SVGA3dShaderDestToken
87 translate_dst_register( struct svga_shader_emitter
*emit
,
88 const struct tgsi_full_instruction
*insn
,
91 const struct tgsi_full_dst_register
*reg
= &insn
->Dst
[idx
];
92 SVGA3dShaderDestToken dest
;
94 switch (reg
->Register
.File
) {
95 case TGSI_FILE_OUTPUT
:
96 /* Output registers encode semantic information in their name.
97 * Need to lookup a table built at decl time:
99 dest
= emit
->output_map
[reg
->Register
.Index
];
100 emit
->num_output_writes
++;
105 unsigned index
= reg
->Register
.Index
;
106 assert(index
< SVGA3D_TEMPREG_MAX
);
107 index
= MIN2(index
, SVGA3D_TEMPREG_MAX
- 1);
108 dest
= dst_register(translate_file(reg
->Register
.File
), index
);
113 if (reg
->Register
.Indirect
) {
114 debug_warning("Indirect indexing of dest registers is not supported!\n");
117 dest
.mask
= reg
->Register
.WriteMask
;
120 if (insn
->Instruction
.Saturate
)
121 dest
.dstMod
= SVGA3DDSTMOD_SATURATE
;
128 * Apply a swizzle to a src_register, returning a new src_register
129 * Ex: swizzle(SRC.ZZYY, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_X, SWIZZLE_Y)
130 * would return SRC.YYZZ
132 static struct src_register
133 swizzle(struct src_register src
,
134 unsigned x
, unsigned y
, unsigned z
, unsigned w
)
140 x
= (src
.base
.swizzle
>> (x
* 2)) & 0x3;
141 y
= (src
.base
.swizzle
>> (y
* 2)) & 0x3;
142 z
= (src
.base
.swizzle
>> (z
* 2)) & 0x3;
143 w
= (src
.base
.swizzle
>> (w
* 2)) & 0x3;
145 src
.base
.swizzle
= TRANSLATE_SWIZZLE(x
, y
, z
, w
);
152 * Apply a "scalar" swizzle to a src_register returning a new
153 * src_register where all the swizzle terms are the same.
154 * Ex: scalar(SRC.WZYX, SWIZZLE_Y) would return SRC.ZZZZ
156 static struct src_register
157 scalar(struct src_register src
, unsigned comp
)
160 return swizzle( src
, comp
, comp
, comp
, comp
);
165 svga_arl_needs_adjustment( const struct svga_shader_emitter
*emit
)
169 for (i
= 0; i
< emit
->num_arl_consts
; ++i
) {
170 if (emit
->arl_consts
[i
].arl_num
== emit
->current_arl
)
178 svga_arl_adjustment( const struct svga_shader_emitter
*emit
)
182 for (i
= 0; i
< emit
->num_arl_consts
; ++i
) {
183 if (emit
->arl_consts
[i
].arl_num
== emit
->current_arl
)
184 return emit
->arl_consts
[i
].number
;
191 * Translate a TGSI src register to a src_register.
193 static struct src_register
194 translate_src_register( const struct svga_shader_emitter
*emit
,
195 const struct tgsi_full_src_register
*reg
)
197 struct src_register src
;
199 switch (reg
->Register
.File
) {
200 case TGSI_FILE_INPUT
:
201 /* Input registers are referred to by their semantic name rather
202 * than by index. Use the mapping build up from the decls:
204 src
= emit
->input_map
[reg
->Register
.Index
];
207 case TGSI_FILE_IMMEDIATE
:
208 /* Immediates are appended after TGSI constants in the D3D
211 src
= src_register( translate_file( reg
->Register
.File
),
212 reg
->Register
.Index
+ emit
->imm_start
);
216 src
= src_register( translate_file( reg
->Register
.File
),
217 reg
->Register
.Index
);
221 /* Indirect addressing.
223 if (reg
->Register
.Indirect
) {
224 if (emit
->unit
== PIPE_SHADER_FRAGMENT
) {
225 /* Pixel shaders have only loop registers for relative
226 * addressing into inputs. Ignore the redundant address
227 * register, the contents of aL should be in sync with it.
229 if (reg
->Register
.File
== TGSI_FILE_INPUT
) {
230 src
.base
.relAddr
= 1;
231 src
.indirect
= src_token(SVGA3DREG_LOOP
, 0);
235 /* Constant buffers only.
237 if (reg
->Register
.File
== TGSI_FILE_CONSTANT
) {
238 /* we shift the offset towards the minimum */
239 if (svga_arl_needs_adjustment( emit
)) {
240 src
.base
.num
-= svga_arl_adjustment( emit
);
242 src
.base
.relAddr
= 1;
244 /* Not really sure what should go in the second token:
246 src
.indirect
= src_token( SVGA3DREG_ADDR
,
247 reg
->Indirect
.Index
);
249 src
.indirect
.swizzle
= SWIZZLE_XXXX
;
255 reg
->Register
.SwizzleX
,
256 reg
->Register
.SwizzleY
,
257 reg
->Register
.SwizzleZ
,
258 reg
->Register
.SwizzleW
);
260 /* src.mod isn't a bitfield, unfortunately:
261 * See tgsi_util_get_full_src_register_sign_mode for implementation details.
263 if (reg
->Register
.Absolute
) {
264 if (reg
->Register
.Negate
)
265 src
.base
.srcMod
= SVGA3DSRCMOD_ABSNEG
;
267 src
.base
.srcMod
= SVGA3DSRCMOD_ABS
;
270 if (reg
->Register
.Negate
)
271 src
.base
.srcMod
= SVGA3DSRCMOD_NEG
;
273 src
.base
.srcMod
= SVGA3DSRCMOD_NONE
;
281 * Get a temporary register.
282 * Note: if we exceed the temporary register limit we just use
283 * register SVGA3D_TEMPREG_MAX - 1.
285 static SVGA3dShaderDestToken
286 get_temp( struct svga_shader_emitter
*emit
)
288 int i
= emit
->nr_hw_temp
+ emit
->internal_temp_count
++;
289 if (i
>= SVGA3D_TEMPREG_MAX
) {
290 debug_warn_once("svga: Too many temporary registers used in shader\n");
291 i
= SVGA3D_TEMPREG_MAX
- 1;
293 return dst_register( SVGA3DREG_TEMP
, i
);
298 * Release a single temp. Currently only effective if it was the last
299 * allocated temp, otherwise release will be delayed until the next
300 * call to reset_temp_regs().
303 release_temp( struct svga_shader_emitter
*emit
,
304 SVGA3dShaderDestToken temp
)
306 if (temp
.num
== emit
->internal_temp_count
- 1)
307 emit
->internal_temp_count
--;
315 reset_temp_regs(struct svga_shader_emitter
*emit
)
317 emit
->internal_temp_count
= 0;
321 /** Emit bytecode for a src_register */
323 emit_src(struct svga_shader_emitter
*emit
, const struct src_register src
)
325 if (src
.base
.relAddr
) {
326 assert(src
.base
.reserved0
);
327 assert(src
.indirect
.reserved0
);
328 return (svga_shader_emit_dword( emit
, src
.base
.value
) &&
329 svga_shader_emit_dword( emit
, src
.indirect
.value
));
332 assert(src
.base
.reserved0
);
333 return svga_shader_emit_dword( emit
, src
.base
.value
);
338 /** Emit bytecode for a dst_register */
340 emit_dst(struct svga_shader_emitter
*emit
, SVGA3dShaderDestToken dest
)
342 assert(dest
.reserved0
);
344 return svga_shader_emit_dword( emit
, dest
.value
);
348 /** Emit bytecode for a 1-operand instruction */
350 emit_op1(struct svga_shader_emitter
*emit
,
351 SVGA3dShaderInstToken inst
,
352 SVGA3dShaderDestToken dest
,
353 struct src_register src0
)
355 return (emit_instruction(emit
, inst
) &&
356 emit_dst(emit
, dest
) &&
357 emit_src(emit
, src0
));
361 /** Emit bytecode for a 2-operand instruction */
363 emit_op2(struct svga_shader_emitter
*emit
,
364 SVGA3dShaderInstToken inst
,
365 SVGA3dShaderDestToken dest
,
366 struct src_register src0
,
367 struct src_register src1
)
369 return (emit_instruction(emit
, inst
) &&
370 emit_dst(emit
, dest
) &&
371 emit_src(emit
, src0
) &&
372 emit_src(emit
, src1
));
376 /** Emit bytecode for a 3-operand instruction */
378 emit_op3(struct svga_shader_emitter
*emit
,
379 SVGA3dShaderInstToken inst
,
380 SVGA3dShaderDestToken dest
,
381 struct src_register src0
,
382 struct src_register src1
,
383 struct src_register src2
)
385 return (emit_instruction(emit
, inst
) &&
386 emit_dst(emit
, dest
) &&
387 emit_src(emit
, src0
) &&
388 emit_src(emit
, src1
) &&
389 emit_src(emit
, src2
));
393 /** Emit bytecode for a 4-operand instruction */
395 emit_op4(struct svga_shader_emitter
*emit
,
396 SVGA3dShaderInstToken inst
,
397 SVGA3dShaderDestToken dest
,
398 struct src_register src0
,
399 struct src_register src1
,
400 struct src_register src2
,
401 struct src_register src3
)
403 return (emit_instruction(emit
, inst
) &&
404 emit_dst(emit
, dest
) &&
405 emit_src(emit
, src0
) &&
406 emit_src(emit
, src1
) &&
407 emit_src(emit
, src2
) &&
408 emit_src(emit
, src3
));
413 * Apply the absolute value modifier to the given src_register, returning
414 * a new src_register.
416 static struct src_register
417 absolute(struct src_register src
)
419 src
.base
.srcMod
= SVGA3DSRCMOD_ABS
;
425 * Apply the negation modifier to the given src_register, returning
426 * a new src_register.
428 static struct src_register
429 negate(struct src_register src
)
431 switch (src
.base
.srcMod
) {
432 case SVGA3DSRCMOD_ABS
:
433 src
.base
.srcMod
= SVGA3DSRCMOD_ABSNEG
;
435 case SVGA3DSRCMOD_ABSNEG
:
436 src
.base
.srcMod
= SVGA3DSRCMOD_ABS
;
438 case SVGA3DSRCMOD_NEG
:
439 src
.base
.srcMod
= SVGA3DSRCMOD_NONE
;
441 case SVGA3DSRCMOD_NONE
:
442 src
.base
.srcMod
= SVGA3DSRCMOD_NEG
;
450 /* Replace the src with the temporary specified in the dst, but copying
451 * only the necessary channels, and preserving the original swizzle (which is
452 * important given that several opcodes have constraints in the allowed
456 emit_repl(struct svga_shader_emitter
*emit
,
457 SVGA3dShaderDestToken dst
,
458 struct src_register
*src0
)
460 unsigned src0_swizzle
;
463 assert(SVGA3dShaderGetRegType(dst
.value
) == SVGA3DREG_TEMP
);
465 src0_swizzle
= src0
->base
.swizzle
;
468 for (chan
= 0; chan
< 4; ++chan
) {
469 unsigned swizzle
= (src0_swizzle
>> (chan
*2)) & 0x3;
470 dst
.mask
|= 1 << swizzle
;
474 src0
->base
.swizzle
= SVGA3DSWIZZLE_NONE
;
476 if (!emit_op1( emit
, inst_token( SVGA3DOP_MOV
), dst
, *src0
))
480 src0
->base
.swizzle
= src0_swizzle
;
487 * Submit/emit an instruction with zero operands.
490 submit_op0(struct svga_shader_emitter
*emit
,
491 SVGA3dShaderInstToken inst
,
492 SVGA3dShaderDestToken dest
)
494 return (emit_instruction( emit
, inst
) &&
495 emit_dst( emit
, dest
));
500 * Submit/emit an instruction with one operand.
503 submit_op1(struct svga_shader_emitter
*emit
,
504 SVGA3dShaderInstToken inst
,
505 SVGA3dShaderDestToken dest
,
506 struct src_register src0
)
508 return emit_op1( emit
, inst
, dest
, src0
);
513 * Submit/emit an instruction with two operands.
515 * SVGA shaders may not refer to >1 constant register in a single
516 * instruction. This function checks for that usage and inserts a
517 * move to temporary if detected.
519 * The same applies to input registers -- at most a single input
520 * register may be read by any instruction.
523 submit_op2(struct svga_shader_emitter
*emit
,
524 SVGA3dShaderInstToken inst
,
525 SVGA3dShaderDestToken dest
,
526 struct src_register src0
,
527 struct src_register src1
)
529 SVGA3dShaderDestToken temp
;
530 SVGA3dShaderRegType type0
, type1
;
531 boolean need_temp
= FALSE
;
534 type0
= SVGA3dShaderGetRegType( src0
.base
.value
);
535 type1
= SVGA3dShaderGetRegType( src1
.base
.value
);
537 if (type0
== SVGA3DREG_CONST
&&
538 type1
== SVGA3DREG_CONST
&&
539 src0
.base
.num
!= src1
.base
.num
)
542 if (type0
== SVGA3DREG_INPUT
&&
543 type1
== SVGA3DREG_INPUT
&&
544 src0
.base
.num
!= src1
.base
.num
)
548 temp
= get_temp( emit
);
550 if (!emit_repl( emit
, temp
, &src0
))
554 if (!emit_op2( emit
, inst
, dest
, src0
, src1
))
558 release_temp( emit
, temp
);
565 * Submit/emit an instruction with three operands.
567 * SVGA shaders may not refer to >1 constant register in a single
568 * instruction. This function checks for that usage and inserts a
569 * move to temporary if detected.
572 submit_op3(struct svga_shader_emitter
*emit
,
573 SVGA3dShaderInstToken inst
,
574 SVGA3dShaderDestToken dest
,
575 struct src_register src0
,
576 struct src_register src1
,
577 struct src_register src2
)
579 SVGA3dShaderDestToken temp0
;
580 SVGA3dShaderDestToken temp1
;
581 boolean need_temp0
= FALSE
;
582 boolean need_temp1
= FALSE
;
583 SVGA3dShaderRegType type0
, type1
, type2
;
587 type0
= SVGA3dShaderGetRegType( src0
.base
.value
);
588 type1
= SVGA3dShaderGetRegType( src1
.base
.value
);
589 type2
= SVGA3dShaderGetRegType( src2
.base
.value
);
591 if (inst
.op
!= SVGA3DOP_SINCOS
) {
592 if (type0
== SVGA3DREG_CONST
&&
593 ((type1
== SVGA3DREG_CONST
&& src0
.base
.num
!= src1
.base
.num
) ||
594 (type2
== SVGA3DREG_CONST
&& src0
.base
.num
!= src2
.base
.num
)))
597 if (type1
== SVGA3DREG_CONST
&&
598 (type2
== SVGA3DREG_CONST
&& src1
.base
.num
!= src2
.base
.num
))
602 if (type0
== SVGA3DREG_INPUT
&&
603 ((type1
== SVGA3DREG_INPUT
&& src0
.base
.num
!= src1
.base
.num
) ||
604 (type2
== SVGA3DREG_INPUT
&& src0
.base
.num
!= src2
.base
.num
)))
607 if (type1
== SVGA3DREG_INPUT
&&
608 (type2
== SVGA3DREG_INPUT
&& src1
.base
.num
!= src2
.base
.num
))
612 temp0
= get_temp( emit
);
614 if (!emit_repl( emit
, temp0
, &src0
))
619 temp1
= get_temp( emit
);
621 if (!emit_repl( emit
, temp1
, &src1
))
625 if (!emit_op3( emit
, inst
, dest
, src0
, src1
, src2
))
629 release_temp( emit
, temp1
);
631 release_temp( emit
, temp0
);
637 * Submit/emit an instruction with four operands.
639 * SVGA shaders may not refer to >1 constant register in a single
640 * instruction. This function checks for that usage and inserts a
641 * move to temporary if detected.
644 submit_op4(struct svga_shader_emitter
*emit
,
645 SVGA3dShaderInstToken inst
,
646 SVGA3dShaderDestToken dest
,
647 struct src_register src0
,
648 struct src_register src1
,
649 struct src_register src2
,
650 struct src_register src3
)
652 SVGA3dShaderDestToken temp0
;
653 SVGA3dShaderDestToken temp3
;
654 boolean need_temp0
= FALSE
;
655 boolean need_temp3
= FALSE
;
656 SVGA3dShaderRegType type0
, type1
, type2
, type3
;
660 type0
= SVGA3dShaderGetRegType( src0
.base
.value
);
661 type1
= SVGA3dShaderGetRegType( src1
.base
.value
);
662 type2
= SVGA3dShaderGetRegType( src2
.base
.value
);
663 type3
= SVGA3dShaderGetRegType( src2
.base
.value
);
665 /* Make life a little easier - this is only used by the TXD
666 * instruction which is guaranteed not to have a constant/input reg
667 * in one slot at least:
669 assert(type1
== SVGA3DREG_SAMPLER
);
672 if (type0
== SVGA3DREG_CONST
&&
673 ((type3
== SVGA3DREG_CONST
&& src0
.base
.num
!= src3
.base
.num
) ||
674 (type2
== SVGA3DREG_CONST
&& src0
.base
.num
!= src2
.base
.num
)))
677 if (type3
== SVGA3DREG_CONST
&&
678 (type2
== SVGA3DREG_CONST
&& src3
.base
.num
!= src2
.base
.num
))
681 if (type0
== SVGA3DREG_INPUT
&&
682 ((type3
== SVGA3DREG_INPUT
&& src0
.base
.num
!= src3
.base
.num
) ||
683 (type2
== SVGA3DREG_INPUT
&& src0
.base
.num
!= src2
.base
.num
)))
686 if (type3
== SVGA3DREG_INPUT
&&
687 (type2
== SVGA3DREG_INPUT
&& src3
.base
.num
!= src2
.base
.num
))
691 temp0
= get_temp( emit
);
693 if (!emit_repl( emit
, temp0
, &src0
))
698 temp3
= get_temp( emit
);
700 if (!emit_repl( emit
, temp3
, &src3
))
704 if (!emit_op4( emit
, inst
, dest
, src0
, src1
, src2
, src3
))
708 release_temp( emit
, temp3
);
710 release_temp( emit
, temp0
);
716 * Do the src and dest registers refer to the same register?
719 alias_src_dst(struct src_register src
,
720 SVGA3dShaderDestToken dst
)
722 if (src
.base
.num
!= dst
.num
)
725 if (SVGA3dShaderGetRegType(dst
.value
) !=
726 SVGA3dShaderGetRegType(src
.base
.value
))
734 * Helper for emitting SVGA immediate values using the SVGA3DOP_DEF[I]
738 emit_def_const(struct svga_shader_emitter
*emit
,
739 SVGA3dShaderConstType type
,
740 unsigned idx
, float a
, float b
, float c
, float d
)
743 SVGA3dShaderInstToken opcode
;
746 case SVGA3D_CONST_TYPE_FLOAT
:
747 opcode
= inst_token( SVGA3DOP_DEF
);
748 def
.dst
= dst_register( SVGA3DREG_CONST
, idx
);
749 def
.constValues
[0] = a
;
750 def
.constValues
[1] = b
;
751 def
.constValues
[2] = c
;
752 def
.constValues
[3] = d
;
754 case SVGA3D_CONST_TYPE_INT
:
755 opcode
= inst_token( SVGA3DOP_DEFI
);
756 def
.dst
= dst_register( SVGA3DREG_CONSTINT
, idx
);
757 def
.constIValues
[0] = (int)a
;
758 def
.constIValues
[1] = (int)b
;
759 def
.constIValues
[2] = (int)c
;
760 def
.constIValues
[3] = (int)d
;
764 opcode
= inst_token( SVGA3DOP_NOP
);
768 if (!emit_instruction(emit
, opcode
) ||
769 !svga_shader_emit_dwords( emit
, def
.values
, ARRAY_SIZE(def
.values
)))
777 create_loop_const( struct svga_shader_emitter
*emit
)
779 unsigned idx
= emit
->nr_hw_int_const
++;
781 if (!emit_def_const( emit
, SVGA3D_CONST_TYPE_INT
, idx
,
782 255, /* iteration count */
783 0, /* initial value */
785 0 /* not used, must be 0 */))
788 emit
->loop_const_idx
= idx
;
789 emit
->created_loop_const
= TRUE
;
795 create_arl_consts( struct svga_shader_emitter
*emit
)
799 for (i
= 0; i
< emit
->num_arl_consts
; i
+= 4) {
801 unsigned idx
= emit
->nr_hw_float_const
++;
803 for (j
= 0; j
< 4 && (j
+ i
) < emit
->num_arl_consts
; ++j
) {
804 vals
[j
] = (float) emit
->arl_consts
[i
+ j
].number
;
805 emit
->arl_consts
[i
+ j
].idx
= idx
;
808 emit
->arl_consts
[i
+ 0].swizzle
= TGSI_SWIZZLE_X
;
811 emit
->arl_consts
[i
+ 0].swizzle
= TGSI_SWIZZLE_Y
;
814 emit
->arl_consts
[i
+ 0].swizzle
= TGSI_SWIZZLE_Z
;
817 emit
->arl_consts
[i
+ 0].swizzle
= TGSI_SWIZZLE_W
;
824 if (!emit_def_const( emit
, SVGA3D_CONST_TYPE_FLOAT
, idx
,
835 * Return the register which holds the pixel shaders front/back-
838 static struct src_register
839 get_vface( struct svga_shader_emitter
*emit
)
841 assert(emit
->emitted_vface
);
842 return src_register(SVGA3DREG_MISCTYPE
, SVGA3DMISCREG_FACE
);
847 * Create/emit a "common" constant with values {0, 0.5, -1, 1}.
848 * We can swizzle this to produce other useful constants such as
849 * {0, 0, 0, 0}, {1, 1, 1, 1}, etc.
852 create_common_immediate( struct svga_shader_emitter
*emit
)
854 unsigned idx
= emit
->nr_hw_float_const
++;
856 /* Emit the constant (0, 0.5, -1, 1) and use swizzling to generate
857 * other useful vectors.
859 if (!emit_def_const( emit
, SVGA3D_CONST_TYPE_FLOAT
,
860 idx
, 0.0f
, 0.5f
, -1.0f
, 1.0f
))
862 emit
->common_immediate_idx
[0] = idx
;
865 /* Emit constant {2, 0, 0, 0} (only the 2 is used for now) */
866 if (emit
->key
.vs
.adjust_attrib_range
) {
867 if (!emit_def_const( emit
, SVGA3D_CONST_TYPE_FLOAT
,
868 idx
, 2.0f
, 0.0f
, 0.0f
, 0.0f
))
870 emit
->common_immediate_idx
[1] = idx
;
873 emit
->common_immediate_idx
[1] = -1;
876 emit
->created_common_immediate
= TRUE
;
883 * Return swizzle/position for the given value in the "common" immediate.
885 static inline unsigned
886 common_immediate_swizzle(float value
)
889 return TGSI_SWIZZLE_X
;
890 else if (value
== 0.5f
)
891 return TGSI_SWIZZLE_Y
;
892 else if (value
== -1.0f
)
893 return TGSI_SWIZZLE_Z
;
894 else if (value
== 1.0f
)
895 return TGSI_SWIZZLE_W
;
897 assert(!"illegal value in common_immediate_swizzle");
898 return TGSI_SWIZZLE_X
;
904 * Returns an immediate reg where all the terms are either 0, 1, 2 or 0.5
906 static struct src_register
907 get_immediate(struct svga_shader_emitter
*emit
,
908 float x
, float y
, float z
, float w
)
910 unsigned sx
= common_immediate_swizzle(x
);
911 unsigned sy
= common_immediate_swizzle(y
);
912 unsigned sz
= common_immediate_swizzle(z
);
913 unsigned sw
= common_immediate_swizzle(w
);
914 assert(emit
->created_common_immediate
);
915 assert(emit
->common_immediate_idx
[0] >= 0);
916 return swizzle(src_register(SVGA3DREG_CONST
, emit
->common_immediate_idx
[0]),
922 * returns {0, 0, 0, 0} immediate
924 static struct src_register
925 get_zero_immediate( struct svga_shader_emitter
*emit
)
927 assert(emit
->created_common_immediate
);
928 assert(emit
->common_immediate_idx
[0] >= 0);
929 return swizzle(src_register( SVGA3DREG_CONST
,
930 emit
->common_immediate_idx
[0]),
936 * returns {1, 1, 1, 1} immediate
938 static struct src_register
939 get_one_immediate( struct svga_shader_emitter
*emit
)
941 assert(emit
->created_common_immediate
);
942 assert(emit
->common_immediate_idx
[0] >= 0);
943 return swizzle(src_register( SVGA3DREG_CONST
,
944 emit
->common_immediate_idx
[0]),
950 * returns {0.5, 0.5, 0.5, 0.5} immediate
952 static struct src_register
953 get_half_immediate( struct svga_shader_emitter
*emit
)
955 assert(emit
->created_common_immediate
);
956 assert(emit
->common_immediate_idx
[0] >= 0);
957 return swizzle(src_register(SVGA3DREG_CONST
, emit
->common_immediate_idx
[0]),
963 * returns {2, 2, 2, 2} immediate
965 static struct src_register
966 get_two_immediate( struct svga_shader_emitter
*emit
)
968 /* Note we use the second common immediate here */
969 assert(emit
->created_common_immediate
);
970 assert(emit
->common_immediate_idx
[1] >= 0);
971 return swizzle(src_register( SVGA3DREG_CONST
,
972 emit
->common_immediate_idx
[1]),
978 * returns the loop const
980 static struct src_register
981 get_loop_const( struct svga_shader_emitter
*emit
)
983 assert(emit
->created_loop_const
);
984 assert(emit
->loop_const_idx
>= 0);
985 return src_register( SVGA3DREG_CONSTINT
,
986 emit
->loop_const_idx
);
990 static struct src_register
991 get_fake_arl_const( struct svga_shader_emitter
*emit
)
993 struct src_register reg
;
994 int idx
= 0, swizzle
= 0, i
;
996 for (i
= 0; i
< emit
->num_arl_consts
; ++ i
) {
997 if (emit
->arl_consts
[i
].arl_num
== emit
->current_arl
) {
998 idx
= emit
->arl_consts
[i
].idx
;
999 swizzle
= emit
->arl_consts
[i
].swizzle
;
1003 reg
= src_register( SVGA3DREG_CONST
, idx
);
1004 return scalar(reg
, swizzle
);
1009 * Return a register which holds the width and height of the texture
1010 * currently bound to the given sampler.
1012 static struct src_register
1013 get_tex_dimensions( struct svga_shader_emitter
*emit
, int sampler_num
)
1016 struct src_register reg
;
1018 /* the width/height indexes start right after constants */
1019 idx
= emit
->key
.tex
[sampler_num
].width_height_idx
+
1020 emit
->info
.file_max
[TGSI_FILE_CONSTANT
] + 1;
1022 reg
= src_register( SVGA3DREG_CONST
, idx
);
1028 emit_fake_arl(struct svga_shader_emitter
*emit
,
1029 const struct tgsi_full_instruction
*insn
)
1031 const struct src_register src0
=
1032 translate_src_register(emit
, &insn
->Src
[0] );
1033 struct src_register src1
= get_fake_arl_const( emit
);
1034 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1035 SVGA3dShaderDestToken tmp
= get_temp( emit
);
1037 if (!submit_op1(emit
, inst_token( SVGA3DOP_MOV
), tmp
, src0
))
1040 if (!submit_op2( emit
, inst_token( SVGA3DOP_ADD
), tmp
, src( tmp
),
1044 /* replicate the original swizzle */
1046 src1
.base
.swizzle
= src0
.base
.swizzle
;
1048 return submit_op1( emit
, inst_token( SVGA3DOP_MOVA
),
1054 emit_if(struct svga_shader_emitter
*emit
,
1055 const struct tgsi_full_instruction
*insn
)
1057 struct src_register src0
=
1058 translate_src_register(emit
, &insn
->Src
[0]);
1059 struct src_register zero
= get_zero_immediate(emit
);
1060 SVGA3dShaderInstToken if_token
= inst_token( SVGA3DOP_IFC
);
1062 if_token
.control
= SVGA3DOPCOMPC_NE
;
1064 if (SVGA3dShaderGetRegType(src0
.base
.value
) == SVGA3DREG_CONST
) {
1066 * Max different constant registers readable per IFC instruction is 1.
1068 SVGA3dShaderDestToken tmp
= get_temp( emit
);
1070 if (!submit_op1(emit
, inst_token( SVGA3DOP_MOV
), tmp
, src0
))
1073 src0
= scalar(src( tmp
), TGSI_SWIZZLE_X
);
1076 emit
->dynamic_branching_level
++;
1078 return (emit_instruction( emit
, if_token
) &&
1079 emit_src( emit
, src0
) &&
1080 emit_src( emit
, zero
) );
1085 emit_else(struct svga_shader_emitter
*emit
,
1086 const struct tgsi_full_instruction
*insn
)
1088 return emit_instruction(emit
, inst_token(SVGA3DOP_ELSE
));
1093 emit_endif(struct svga_shader_emitter
*emit
,
1094 const struct tgsi_full_instruction
*insn
)
1096 emit
->dynamic_branching_level
--;
1098 return emit_instruction(emit
, inst_token(SVGA3DOP_ENDIF
));
1103 * Translate the following TGSI FLR instruction.
1105 * To the following SVGA3D instruction sequence.
1110 emit_floor(struct svga_shader_emitter
*emit
,
1111 const struct tgsi_full_instruction
*insn
)
1113 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1114 const struct src_register src0
=
1115 translate_src_register(emit
, &insn
->Src
[0] );
1116 SVGA3dShaderDestToken temp
= get_temp( emit
);
1119 if (!submit_op1( emit
, inst_token( SVGA3DOP_FRC
), temp
, src0
))
1122 /* SUB DST, SRC, TMP */
1123 if (!submit_op2( emit
, inst_token( SVGA3DOP_ADD
), dst
, src0
,
1124 negate( src( temp
) ) ))
1132 * Translate the following TGSI CEIL instruction.
1134 * To the following SVGA3D instruction sequence.
1139 emit_ceil(struct svga_shader_emitter
*emit
,
1140 const struct tgsi_full_instruction
*insn
)
1142 SVGA3dShaderDestToken dst
= translate_dst_register(emit
, insn
, 0);
1143 const struct src_register src0
=
1144 translate_src_register(emit
, &insn
->Src
[0]);
1145 SVGA3dShaderDestToken temp
= get_temp(emit
);
1148 if (!submit_op1(emit
, inst_token(SVGA3DOP_FRC
), temp
, negate(src0
)))
1151 /* ADD DST, SRC, TMP */
1152 if (!submit_op2(emit
, inst_token(SVGA3DOP_ADD
), dst
, src0
, src(temp
)))
1160 * Translate the following TGSI DIV instruction.
1161 * DIV DST.xy, SRC0, SRC1
1162 * To the following SVGA3D instruction sequence.
1163 * RCP TMP.x, SRC1.xxxx
1164 * RCP TMP.y, SRC1.yyyy
1165 * MUL DST.xy, SRC0, TMP
1168 emit_div(struct svga_shader_emitter
*emit
,
1169 const struct tgsi_full_instruction
*insn
)
1171 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1172 const struct src_register src0
=
1173 translate_src_register(emit
, &insn
->Src
[0] );
1174 const struct src_register src1
=
1175 translate_src_register(emit
, &insn
->Src
[1] );
1176 SVGA3dShaderDestToken temp
= get_temp( emit
);
1179 /* For each enabled element, perform a RCP instruction. Note that
1180 * RCP is scalar in SVGA3D:
1182 for (i
= 0; i
< 4; i
++) {
1183 unsigned channel
= 1 << i
;
1184 if (dst
.mask
& channel
) {
1185 /* RCP TMP.?, SRC1.???? */
1186 if (!submit_op1( emit
, inst_token( SVGA3DOP_RCP
),
1187 writemask(temp
, channel
),
1194 * MUL DST, SRC0, TMP
1196 if (!submit_op2( emit
, inst_token( SVGA3DOP_MUL
), dst
, src0
,
1205 * Translate the following TGSI DP2 instruction.
1206 * DP2 DST, SRC1, SRC2
1207 * To the following SVGA3D instruction sequence.
1208 * MUL TMP, SRC1, SRC2
1209 * ADD DST, TMP.xxxx, TMP.yyyy
1212 emit_dp2(struct svga_shader_emitter
*emit
,
1213 const struct tgsi_full_instruction
*insn
)
1215 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1216 const struct src_register src0
=
1217 translate_src_register(emit
, &insn
->Src
[0]);
1218 const struct src_register src1
=
1219 translate_src_register(emit
, &insn
->Src
[1]);
1220 SVGA3dShaderDestToken temp
= get_temp( emit
);
1221 struct src_register temp_src0
, temp_src1
;
1223 /* MUL TMP, SRC1, SRC2 */
1224 if (!submit_op2( emit
, inst_token( SVGA3DOP_MUL
), temp
, src0
, src1
))
1227 temp_src0
= scalar(src( temp
), TGSI_SWIZZLE_X
);
1228 temp_src1
= scalar(src( temp
), TGSI_SWIZZLE_Y
);
1230 /* ADD DST, TMP.xxxx, TMP.yyyy */
1231 if (!submit_op2( emit
, inst_token( SVGA3DOP_ADD
), dst
,
1232 temp_src0
, temp_src1
))
1240 * Sine / Cosine helper function.
1243 do_emit_sincos(struct svga_shader_emitter
*emit
,
1244 SVGA3dShaderDestToken dst
,
1245 struct src_register src0
)
1247 src0
= scalar(src0
, TGSI_SWIZZLE_X
);
1248 return submit_op1(emit
, inst_token(SVGA3DOP_SINCOS
), dst
, src0
);
1253 * Translate TGSI SIN instruction into:
1258 emit_sin(struct svga_shader_emitter
*emit
,
1259 const struct tgsi_full_instruction
*insn
)
1261 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1262 struct src_register src0
=
1263 translate_src_register(emit
, &insn
->Src
[0] );
1264 SVGA3dShaderDestToken temp
= get_temp( emit
);
1267 if (!do_emit_sincos(emit
, writemask(temp
, TGSI_WRITEMASK_Y
), src0
))
1270 src0
= scalar(src( temp
), TGSI_SWIZZLE_Y
);
1272 /* MOV DST TMP.yyyy */
1273 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), dst
, src0
))
1281 * Translate TGSI COS instruction into:
1286 emit_cos(struct svga_shader_emitter
*emit
,
1287 const struct tgsi_full_instruction
*insn
)
1289 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1290 struct src_register src0
=
1291 translate_src_register(emit
, &insn
->Src
[0] );
1292 SVGA3dShaderDestToken temp
= get_temp( emit
);
1295 if (!do_emit_sincos( emit
, writemask(temp
, TGSI_WRITEMASK_X
), src0
))
1298 src0
= scalar(src( temp
), TGSI_SWIZZLE_X
);
1300 /* MOV DST TMP.xxxx */
1301 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), dst
, src0
))
1309 * Translate/emit TGSI SSG (Set Sign: -1, 0, +1) instruction.
1312 emit_ssg(struct svga_shader_emitter
*emit
,
1313 const struct tgsi_full_instruction
*insn
)
1315 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1316 struct src_register src0
=
1317 translate_src_register(emit
, &insn
->Src
[0] );
1318 SVGA3dShaderDestToken temp0
= get_temp( emit
);
1319 SVGA3dShaderDestToken temp1
= get_temp( emit
);
1320 struct src_register zero
, one
;
1322 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
1323 /* SGN DST, SRC0, TMP0, TMP1 */
1324 return submit_op3( emit
, inst_token( SVGA3DOP_SGN
), dst
, src0
,
1325 src( temp0
), src( temp1
) );
1328 one
= get_one_immediate(emit
);
1329 zero
= get_zero_immediate(emit
);
1331 /* CMP TMP0, SRC0, one, zero */
1332 if (!submit_op3( emit
, inst_token( SVGA3DOP_CMP
),
1333 writemask( temp0
, dst
.mask
), src0
, one
, zero
))
1336 /* CMP TMP1, negate(SRC0), negate(one), zero */
1337 if (!submit_op3( emit
, inst_token( SVGA3DOP_CMP
),
1338 writemask( temp1
, dst
.mask
), negate( src0
), negate( one
),
1342 /* ADD DST, TMP0, TMP1 */
1343 return submit_op2( emit
, inst_token( SVGA3DOP_ADD
), dst
, src( temp0
),
1349 * Translate/emit KILL_IF instruction (kill if any of X,Y,Z,W are negative).
1352 emit_kill_if(struct svga_shader_emitter
*emit
,
1353 const struct tgsi_full_instruction
*insn
)
1355 const struct tgsi_full_src_register
*reg
= &insn
->Src
[0];
1356 struct src_register src0
, srcIn
;
1357 const boolean special
= (reg
->Register
.Absolute
||
1358 reg
->Register
.Negate
||
1359 reg
->Register
.Indirect
||
1360 reg
->Register
.SwizzleX
!= 0 ||
1361 reg
->Register
.SwizzleY
!= 1 ||
1362 reg
->Register
.SwizzleZ
!= 2 ||
1363 reg
->Register
.File
!= TGSI_FILE_TEMPORARY
);
1364 SVGA3dShaderDestToken temp
;
1366 src0
= srcIn
= translate_src_register( emit
, reg
);
1369 /* need a temp reg */
1370 temp
= get_temp( emit
);
1374 /* move the source into a temp register */
1375 submit_op1(emit
, inst_token(SVGA3DOP_MOV
), temp
, src0
);
1380 /* Do the texkill by checking if any of the XYZW components are < 0.
1381 * Note that ps_2_0 and later take XYZW in consideration, while ps_1_x
1382 * only used XYZ. The MSDN documentation about this is incorrect.
1384 if (!submit_op0( emit
, inst_token( SVGA3DOP_TEXKILL
), dst(src0
) ))
1392 * Translate/emit unconditional kill instruction (usually found inside
1393 * an IF/ELSE/ENDIF block).
1396 emit_kill(struct svga_shader_emitter
*emit
,
1397 const struct tgsi_full_instruction
*insn
)
1399 SVGA3dShaderDestToken temp
;
1400 struct src_register one
= get_one_immediate(emit
);
1401 SVGA3dShaderInstToken inst
= inst_token( SVGA3DOP_TEXKILL
);
1403 /* texkill doesn't allow negation on the operand so lets move
1404 * negation of {1} to a temp register */
1405 temp
= get_temp( emit
);
1406 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), temp
,
1410 return submit_op0( emit
, inst
, temp
);
1415 * Test if r1 and r2 are the same register.
1418 same_register(struct src_register r1
, struct src_register r2
)
1420 return (r1
.base
.num
== r2
.base
.num
&&
1421 r1
.base
.type_upper
== r2
.base
.type_upper
&&
1422 r1
.base
.type_lower
== r2
.base
.type_lower
);
1428 * Implement conditionals by initializing destination reg to 'fail',
1429 * then set predicate reg with UFOP_SETP, then move 'pass' to dest
1430 * based on predicate reg.
1432 * SETP src0, cmp, src1 -- do this first to avoid aliasing problems.
1437 emit_conditional(struct svga_shader_emitter
*emit
,
1438 enum pipe_compare_func compare_func
,
1439 SVGA3dShaderDestToken dst
,
1440 struct src_register src0
,
1441 struct src_register src1
,
1442 struct src_register pass
,
1443 struct src_register fail
)
1445 SVGA3dShaderDestToken pred_reg
= dst_register( SVGA3DREG_PREDICATE
, 0 );
1446 SVGA3dShaderInstToken setp_token
;
1448 switch (compare_func
) {
1449 case PIPE_FUNC_NEVER
:
1450 return submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
1453 case PIPE_FUNC_LESS
:
1454 setp_token
= inst_token_setp(SVGA3DOPCOMP_LT
);
1456 case PIPE_FUNC_EQUAL
:
1457 setp_token
= inst_token_setp(SVGA3DOPCOMP_EQ
);
1459 case PIPE_FUNC_LEQUAL
:
1460 setp_token
= inst_token_setp(SVGA3DOPCOMP_LE
);
1462 case PIPE_FUNC_GREATER
:
1463 setp_token
= inst_token_setp(SVGA3DOPCOMP_GT
);
1465 case PIPE_FUNC_NOTEQUAL
:
1466 setp_token
= inst_token_setp(SVGA3DOPCOMPC_NE
);
1468 case PIPE_FUNC_GEQUAL
:
1469 setp_token
= inst_token_setp(SVGA3DOPCOMP_GE
);
1471 case PIPE_FUNC_ALWAYS
:
1472 return submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
1477 if (same_register(src(dst
), pass
)) {
1478 /* We'll get bad results if the dst and pass registers are the same
1479 * so use a temp register containing pass.
1481 SVGA3dShaderDestToken temp
= get_temp(emit
);
1482 if (!submit_op1(emit
, inst_token(SVGA3DOP_MOV
), temp
, pass
))
1487 /* SETP src0, COMPOP, src1 */
1488 if (!submit_op2( emit
, setp_token
, pred_reg
,
1493 if (!submit_op1(emit
, inst_token(SVGA3DOP_MOV
), dst
, fail
))
1496 /* MOV dst, pass (predicated)
1498 * Note that the predicate reg (and possible modifiers) is passed
1499 * as the first source argument.
1501 if (!submit_op2(emit
,
1502 inst_token_predicated(SVGA3DOP_MOV
), dst
,
1503 src(pred_reg
), pass
))
1511 * Helper for emiting 'selection' commands. Basically:
1518 emit_select(struct svga_shader_emitter
*emit
,
1519 enum pipe_compare_func compare_func
,
1520 SVGA3dShaderDestToken dst
,
1521 struct src_register src0
,
1522 struct src_register src1
)
1524 /* There are some SVGA instructions which implement some selects
1525 * directly, but they are only available in the vertex shader.
1527 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
1528 switch (compare_func
) {
1529 case PIPE_FUNC_GEQUAL
:
1530 return submit_op2( emit
, inst_token( SVGA3DOP_SGE
), dst
, src0
, src1
);
1531 case PIPE_FUNC_LEQUAL
:
1532 return submit_op2( emit
, inst_token( SVGA3DOP_SGE
), dst
, src1
, src0
);
1533 case PIPE_FUNC_GREATER
:
1534 return submit_op2( emit
, inst_token( SVGA3DOP_SLT
), dst
, src1
, src0
);
1535 case PIPE_FUNC_LESS
:
1536 return submit_op2( emit
, inst_token( SVGA3DOP_SLT
), dst
, src0
, src1
);
1542 /* Otherwise, need to use the setp approach:
1545 struct src_register one
, zero
;
1546 /* zero immediate is 0,0,0,1 */
1547 zero
= get_zero_immediate(emit
);
1548 one
= get_one_immediate(emit
);
1550 return emit_conditional(emit
, compare_func
, dst
, src0
, src1
, one
, zero
);
1556 * Translate/emit a TGSI SEQ, SNE, SLT, SGE, etc. instruction.
1559 emit_select_op(struct svga_shader_emitter
*emit
,
1561 const struct tgsi_full_instruction
*insn
)
1563 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1564 struct src_register src0
= translate_src_register(
1565 emit
, &insn
->Src
[0] );
1566 struct src_register src1
= translate_src_register(
1567 emit
, &insn
->Src
[1] );
1569 return emit_select( emit
, compare
, dst
, src0
, src1
);
1574 * Translate TGSI CMP instruction. Component-wise:
1575 * dst = (src0 < 0.0) ? src1 : src2
1578 emit_cmp(struct svga_shader_emitter
*emit
,
1579 const struct tgsi_full_instruction
*insn
)
1581 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1582 const struct src_register src0
=
1583 translate_src_register(emit
, &insn
->Src
[0] );
1584 const struct src_register src1
=
1585 translate_src_register(emit
, &insn
->Src
[1] );
1586 const struct src_register src2
=
1587 translate_src_register(emit
, &insn
->Src
[2] );
1589 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
1590 struct src_register zero
= get_zero_immediate(emit
);
1591 /* We used to simulate CMP with SLT+LRP. But that didn't work when
1592 * src1 or src2 was Inf/NaN. In particular, GLSL sqrt(0) failed
1593 * because it involves a CMP to handle the 0 case.
1594 * Use a conditional expression instead.
1596 return emit_conditional(emit
, PIPE_FUNC_LESS
, dst
,
1597 src0
, zero
, src1
, src2
);
1600 assert(emit
->unit
== PIPE_SHADER_FRAGMENT
);
1602 /* CMP DST, SRC0, SRC2, SRC1 */
1603 return submit_op3( emit
, inst_token( SVGA3DOP_CMP
), dst
,
1610 * Translate/emit 2-operand (coord, sampler) texture instructions.
1613 emit_tex2(struct svga_shader_emitter
*emit
,
1614 const struct tgsi_full_instruction
*insn
,
1615 SVGA3dShaderDestToken dst
)
1617 SVGA3dShaderInstToken inst
;
1618 struct src_register texcoord
;
1619 struct src_register sampler
;
1620 SVGA3dShaderDestToken tmp
;
1624 switch (insn
->Instruction
.Opcode
) {
1625 case TGSI_OPCODE_TEX
:
1626 inst
.op
= SVGA3DOP_TEX
;
1628 case TGSI_OPCODE_TXP
:
1629 inst
.op
= SVGA3DOP_TEX
;
1630 inst
.control
= SVGA3DOPCONT_PROJECT
;
1632 case TGSI_OPCODE_TXB
:
1633 inst
.op
= SVGA3DOP_TEX
;
1634 inst
.control
= SVGA3DOPCONT_BIAS
;
1636 case TGSI_OPCODE_TXL
:
1637 inst
.op
= SVGA3DOP_TEXLDL
;
1644 texcoord
= translate_src_register( emit
, &insn
->Src
[0] );
1645 sampler
= translate_src_register( emit
, &insn
->Src
[1] );
1647 if (emit
->key
.tex
[sampler
.base
.num
].unnormalized
||
1648 emit
->dynamic_branching_level
> 0)
1649 tmp
= get_temp( emit
);
1651 /* Can't do mipmapping inside dynamic branch constructs. Force LOD
1652 * zero in that case.
1654 if (emit
->dynamic_branching_level
> 0 &&
1655 inst
.op
== SVGA3DOP_TEX
&&
1656 SVGA3dShaderGetRegType(texcoord
.base
.value
) == SVGA3DREG_TEMP
) {
1657 struct src_register zero
= get_zero_immediate(emit
);
1659 /* MOV tmp, texcoord */
1660 if (!submit_op1( emit
,
1661 inst_token( SVGA3DOP_MOV
),
1666 /* MOV tmp.w, zero */
1667 if (!submit_op1( emit
,
1668 inst_token( SVGA3DOP_MOV
),
1669 writemask( tmp
, TGSI_WRITEMASK_W
),
1673 texcoord
= src( tmp
);
1674 inst
.op
= SVGA3DOP_TEXLDL
;
1677 /* Explicit normalization of texcoords:
1679 if (emit
->key
.tex
[sampler
.base
.num
].unnormalized
) {
1680 struct src_register wh
= get_tex_dimensions( emit
, sampler
.base
.num
);
1682 /* MUL tmp, SRC0, WH */
1683 if (!submit_op2( emit
, inst_token( SVGA3DOP_MUL
),
1684 tmp
, texcoord
, wh
))
1687 texcoord
= src( tmp
);
1690 return submit_op2( emit
, inst
, dst
, texcoord
, sampler
);
1695 * Translate/emit 4-operand (coord, ddx, ddy, sampler) texture instructions.
1698 emit_tex4(struct svga_shader_emitter
*emit
,
1699 const struct tgsi_full_instruction
*insn
,
1700 SVGA3dShaderDestToken dst
)
1702 SVGA3dShaderInstToken inst
;
1703 struct src_register texcoord
;
1704 struct src_register ddx
;
1705 struct src_register ddy
;
1706 struct src_register sampler
;
1708 texcoord
= translate_src_register( emit
, &insn
->Src
[0] );
1709 ddx
= translate_src_register( emit
, &insn
->Src
[1] );
1710 ddy
= translate_src_register( emit
, &insn
->Src
[2] );
1711 sampler
= translate_src_register( emit
, &insn
->Src
[3] );
1715 switch (insn
->Instruction
.Opcode
) {
1716 case TGSI_OPCODE_TXD
:
1717 inst
.op
= SVGA3DOP_TEXLDD
; /* 4 args! */
1724 return submit_op4( emit
, inst
, dst
, texcoord
, sampler
, ddx
, ddy
);
1729 * Emit texture swizzle code. We do this here since SVGA samplers don't
1730 * directly support swizzles.
1733 emit_tex_swizzle(struct svga_shader_emitter
*emit
,
1734 SVGA3dShaderDestToken dst
,
1735 struct src_register src
,
1741 const unsigned swizzleIn
[4] = {swizzle_x
, swizzle_y
, swizzle_z
, swizzle_w
};
1742 unsigned srcSwizzle
[4];
1743 unsigned srcWritemask
= 0x0, zeroWritemask
= 0x0, oneWritemask
= 0x0;
1746 /* build writemasks and srcSwizzle terms */
1747 for (i
= 0; i
< 4; i
++) {
1748 if (swizzleIn
[i
] == PIPE_SWIZZLE_0
) {
1749 srcSwizzle
[i
] = TGSI_SWIZZLE_X
+ i
;
1750 zeroWritemask
|= (1 << i
);
1752 else if (swizzleIn
[i
] == PIPE_SWIZZLE_1
) {
1753 srcSwizzle
[i
] = TGSI_SWIZZLE_X
+ i
;
1754 oneWritemask
|= (1 << i
);
1757 srcSwizzle
[i
] = swizzleIn
[i
];
1758 srcWritemask
|= (1 << i
);
1762 /* write x/y/z/w comps */
1763 if (dst
.mask
& srcWritemask
) {
1764 if (!submit_op1(emit
,
1765 inst_token(SVGA3DOP_MOV
),
1766 writemask(dst
, srcWritemask
),
1776 if (dst
.mask
& zeroWritemask
) {
1777 if (!submit_op1(emit
,
1778 inst_token(SVGA3DOP_MOV
),
1779 writemask(dst
, zeroWritemask
),
1780 get_zero_immediate(emit
)))
1785 if (dst
.mask
& oneWritemask
) {
1786 if (!submit_op1(emit
,
1787 inst_token(SVGA3DOP_MOV
),
1788 writemask(dst
, oneWritemask
),
1789 get_one_immediate(emit
)))
1798 * Translate/emit a TGSI texture sample instruction.
1801 emit_tex(struct svga_shader_emitter
*emit
,
1802 const struct tgsi_full_instruction
*insn
)
1804 SVGA3dShaderDestToken dst
=
1805 translate_dst_register( emit
, insn
, 0 );
1806 struct src_register src0
=
1807 translate_src_register( emit
, &insn
->Src
[0] );
1808 struct src_register src1
=
1809 translate_src_register( emit
, &insn
->Src
[1] );
1811 SVGA3dShaderDestToken tex_result
;
1812 const unsigned unit
= src1
.base
.num
;
1814 /* check for shadow samplers */
1815 boolean compare
= (emit
->key
.tex
[unit
].compare_mode
==
1816 PIPE_TEX_COMPARE_R_TO_TEXTURE
);
1818 /* texture swizzle */
1819 boolean swizzle
= (emit
->key
.tex
[unit
].swizzle_r
!= PIPE_SWIZZLE_X
||
1820 emit
->key
.tex
[unit
].swizzle_g
!= PIPE_SWIZZLE_Y
||
1821 emit
->key
.tex
[unit
].swizzle_b
!= PIPE_SWIZZLE_Z
||
1822 emit
->key
.tex
[unit
].swizzle_a
!= PIPE_SWIZZLE_W
);
1824 boolean saturate
= insn
->Instruction
.Saturate
;
1826 /* If doing compare processing or tex swizzle or saturation, we need to put
1827 * the fetched color into a temporary so it can be used as a source later on.
1829 if (compare
|| swizzle
|| saturate
) {
1830 tex_result
= get_temp( emit
);
1836 switch(insn
->Instruction
.Opcode
) {
1837 case TGSI_OPCODE_TEX
:
1838 case TGSI_OPCODE_TXB
:
1839 case TGSI_OPCODE_TXP
:
1840 case TGSI_OPCODE_TXL
:
1841 if (!emit_tex2( emit
, insn
, tex_result
))
1844 case TGSI_OPCODE_TXD
:
1845 if (!emit_tex4( emit
, insn
, tex_result
))
1853 SVGA3dShaderDestToken dst2
;
1855 if (swizzle
|| saturate
)
1860 if (dst
.mask
& TGSI_WRITEMASK_XYZ
) {
1861 SVGA3dShaderDestToken src0_zdivw
= get_temp( emit
);
1862 /* When sampling a depth texture, the result of the comparison is in
1865 struct src_register tex_src_x
= scalar(src(tex_result
), TGSI_SWIZZLE_Y
);
1866 struct src_register r_coord
;
1868 if (insn
->Instruction
.Opcode
== TGSI_OPCODE_TXP
) {
1869 /* Divide texcoord R by Q */
1870 if (!submit_op1( emit
, inst_token( SVGA3DOP_RCP
),
1871 writemask(src0_zdivw
, TGSI_WRITEMASK_X
),
1872 scalar(src0
, TGSI_SWIZZLE_W
) ))
1875 if (!submit_op2( emit
, inst_token( SVGA3DOP_MUL
),
1876 writemask(src0_zdivw
, TGSI_WRITEMASK_X
),
1877 scalar(src0
, TGSI_SWIZZLE_Z
),
1878 scalar(src(src0_zdivw
), TGSI_SWIZZLE_X
) ))
1881 r_coord
= scalar(src(src0_zdivw
), TGSI_SWIZZLE_X
);
1884 r_coord
= scalar(src0
, TGSI_SWIZZLE_Z
);
1887 /* Compare texture sample value against R component of texcoord */
1888 if (!emit_select(emit
,
1889 emit
->key
.tex
[unit
].compare_func
,
1890 writemask( dst2
, TGSI_WRITEMASK_XYZ
),
1896 if (dst
.mask
& TGSI_WRITEMASK_W
) {
1897 struct src_register one
= get_one_immediate(emit
);
1899 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
1900 writemask( dst2
, TGSI_WRITEMASK_W
),
1906 if (saturate
&& !swizzle
) {
1907 /* MOV_SAT real_dst, dst */
1908 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), dst
, src(tex_result
) ))
1912 /* swizzle from tex_result to dst (handles saturation too, if any) */
1913 emit_tex_swizzle(emit
,
1914 dst
, src(tex_result
),
1915 emit
->key
.tex
[unit
].swizzle_r
,
1916 emit
->key
.tex
[unit
].swizzle_g
,
1917 emit
->key
.tex
[unit
].swizzle_b
,
1918 emit
->key
.tex
[unit
].swizzle_a
);
1926 emit_bgnloop(struct svga_shader_emitter
*emit
,
1927 const struct tgsi_full_instruction
*insn
)
1929 SVGA3dShaderInstToken inst
= inst_token( SVGA3DOP_LOOP
);
1930 struct src_register loop_reg
= src_register( SVGA3DREG_LOOP
, 0 );
1931 struct src_register const_int
= get_loop_const( emit
);
1933 emit
->dynamic_branching_level
++;
1935 return (emit_instruction( emit
, inst
) &&
1936 emit_src( emit
, loop_reg
) &&
1937 emit_src( emit
, const_int
) );
1942 emit_endloop(struct svga_shader_emitter
*emit
,
1943 const struct tgsi_full_instruction
*insn
)
1945 SVGA3dShaderInstToken inst
= inst_token( SVGA3DOP_ENDLOOP
);
1947 emit
->dynamic_branching_level
--;
1949 return emit_instruction( emit
, inst
);
1954 * Translate/emit TGSI BREAK (out of loop) instruction.
1957 emit_brk(struct svga_shader_emitter
*emit
,
1958 const struct tgsi_full_instruction
*insn
)
1960 SVGA3dShaderInstToken inst
= inst_token( SVGA3DOP_BREAK
);
1961 return emit_instruction( emit
, inst
);
1966 * Emit simple instruction which operates on one scalar value (not
1967 * a vector). Ex: LG2, RCP, RSQ.
1970 emit_scalar_op1(struct svga_shader_emitter
*emit
,
1971 SVGA3dShaderOpCodeType opcode
,
1972 const struct tgsi_full_instruction
*insn
)
1974 SVGA3dShaderInstToken inst
;
1975 SVGA3dShaderDestToken dst
;
1976 struct src_register src
;
1978 inst
= inst_token( opcode
);
1979 dst
= translate_dst_register( emit
, insn
, 0 );
1980 src
= translate_src_register( emit
, &insn
->Src
[0] );
1981 src
= scalar( src
, TGSI_SWIZZLE_X
);
1983 return submit_op1( emit
, inst
, dst
, src
);
1988 * Translate/emit a simple instruction (one which has no special-case
1989 * code) such as ADD, MUL, MIN, MAX.
1992 emit_simple_instruction(struct svga_shader_emitter
*emit
,
1993 SVGA3dShaderOpCodeType opcode
,
1994 const struct tgsi_full_instruction
*insn
)
1996 const struct tgsi_full_src_register
*src
= insn
->Src
;
1997 SVGA3dShaderInstToken inst
;
1998 SVGA3dShaderDestToken dst
;
2000 inst
= inst_token( opcode
);
2001 dst
= translate_dst_register( emit
, insn
, 0 );
2003 switch (insn
->Instruction
.NumSrcRegs
) {
2005 return submit_op0( emit
, inst
, dst
);
2007 return submit_op1( emit
, inst
, dst
,
2008 translate_src_register( emit
, &src
[0] ));
2010 return submit_op2( emit
, inst
, dst
,
2011 translate_src_register( emit
, &src
[0] ),
2012 translate_src_register( emit
, &src
[1] ) );
2014 return submit_op3( emit
, inst
, dst
,
2015 translate_src_register( emit
, &src
[0] ),
2016 translate_src_register( emit
, &src
[1] ),
2017 translate_src_register( emit
, &src
[2] ) );
2026 * TGSI_OPCODE_MOVE is only special-cased here to detect the
2027 * svga_fragment_shader::constant_color_output case.
2030 emit_mov(struct svga_shader_emitter
*emit
,
2031 const struct tgsi_full_instruction
*insn
)
2033 const struct tgsi_full_src_register
*src
= &insn
->Src
[0];
2034 const struct tgsi_full_dst_register
*dst
= &insn
->Dst
[0];
2036 if (emit
->unit
== PIPE_SHADER_FRAGMENT
&&
2037 dst
->Register
.File
== TGSI_FILE_OUTPUT
&&
2038 dst
->Register
.Index
== 0 &&
2039 src
->Register
.File
== TGSI_FILE_CONSTANT
&&
2040 !src
->Register
.Indirect
) {
2041 emit
->constant_color_output
= TRUE
;
2044 return emit_simple_instruction(emit
, SVGA3DOP_MOV
, insn
);
2049 * Translate/emit TGSI DDX, DDY instructions.
2052 emit_deriv(struct svga_shader_emitter
*emit
,
2053 const struct tgsi_full_instruction
*insn
)
2055 if (emit
->dynamic_branching_level
> 0 &&
2056 insn
->Src
[0].Register
.File
== TGSI_FILE_TEMPORARY
)
2058 SVGA3dShaderDestToken dst
=
2059 translate_dst_register( emit
, insn
, 0 );
2061 /* Deriv opcodes not valid inside dynamic branching, workaround
2062 * by zeroing out the destination.
2064 if (!submit_op1(emit
,
2065 inst_token( SVGA3DOP_MOV
),
2067 get_zero_immediate(emit
)))
2073 SVGA3dShaderOpCodeType opcode
;
2074 const struct tgsi_full_src_register
*reg
= &insn
->Src
[0];
2075 SVGA3dShaderInstToken inst
;
2076 SVGA3dShaderDestToken dst
;
2077 struct src_register src0
;
2079 switch (insn
->Instruction
.Opcode
) {
2080 case TGSI_OPCODE_DDX
:
2081 opcode
= SVGA3DOP_DSX
;
2083 case TGSI_OPCODE_DDY
:
2084 opcode
= SVGA3DOP_DSY
;
2090 inst
= inst_token( opcode
);
2091 dst
= translate_dst_register( emit
, insn
, 0 );
2092 src0
= translate_src_register( emit
, reg
);
2094 /* We cannot use negate or abs on source to dsx/dsy instruction.
2096 if (reg
->Register
.Absolute
||
2097 reg
->Register
.Negate
) {
2098 SVGA3dShaderDestToken temp
= get_temp( emit
);
2100 if (!emit_repl( emit
, temp
, &src0
))
2104 return submit_op1( emit
, inst
, dst
, src0
);
2110 * Translate/emit ARL (Address Register Load) instruction. Used to
2111 * move a value into the special 'address' register. Used to implement
2112 * indirect/variable indexing into arrays.
2115 emit_arl(struct svga_shader_emitter
*emit
,
2116 const struct tgsi_full_instruction
*insn
)
2118 ++emit
->current_arl
;
2119 if (emit
->unit
== PIPE_SHADER_FRAGMENT
) {
2120 /* MOVA not present in pixel shader instruction set.
2121 * Ignore this instruction altogether since it is
2122 * only used for loop counters -- and for that
2123 * we reference aL directly.
2127 if (svga_arl_needs_adjustment( emit
)) {
2128 return emit_fake_arl( emit
, insn
);
2130 /* no need to adjust, just emit straight arl */
2131 return emit_simple_instruction(emit
, SVGA3DOP_MOVA
, insn
);
2137 emit_pow(struct svga_shader_emitter
*emit
,
2138 const struct tgsi_full_instruction
*insn
)
2140 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
2141 struct src_register src0
= translate_src_register(
2142 emit
, &insn
->Src
[0] );
2143 struct src_register src1
= translate_src_register(
2144 emit
, &insn
->Src
[1] );
2145 boolean need_tmp
= FALSE
;
2147 /* POW can only output to a temporary */
2148 if (insn
->Dst
[0].Register
.File
!= TGSI_FILE_TEMPORARY
)
2151 /* POW src1 must not be the same register as dst */
2152 if (alias_src_dst( src1
, dst
))
2155 /* it's a scalar op */
2156 src0
= scalar( src0
, TGSI_SWIZZLE_X
);
2157 src1
= scalar( src1
, TGSI_SWIZZLE_X
);
2160 SVGA3dShaderDestToken tmp
=
2161 writemask(get_temp( emit
), TGSI_WRITEMASK_X
);
2163 if (!submit_op2(emit
, inst_token( SVGA3DOP_POW
), tmp
, src0
, src1
))
2166 return submit_op1(emit
, inst_token( SVGA3DOP_MOV
),
2167 dst
, scalar(src(tmp
), 0) );
2170 return submit_op2(emit
, inst_token( SVGA3DOP_POW
), dst
, src0
, src1
);
2176 * Emit a LRP (linear interpolation) instruction.
2179 submit_lrp(struct svga_shader_emitter
*emit
,
2180 SVGA3dShaderDestToken dst
,
2181 struct src_register src0
,
2182 struct src_register src1
,
2183 struct src_register src2
)
2185 SVGA3dShaderDestToken tmp
;
2186 boolean need_dst_tmp
= FALSE
;
2188 /* The dst reg must be a temporary, and not be the same as src0 or src2 */
2189 if (SVGA3dShaderGetRegType(dst
.value
) != SVGA3DREG_TEMP
||
2190 alias_src_dst(src0
, dst
) ||
2191 alias_src_dst(src2
, dst
))
2192 need_dst_tmp
= TRUE
;
2195 tmp
= get_temp( emit
);
2196 tmp
.mask
= dst
.mask
;
2202 if (!submit_op3(emit
, inst_token( SVGA3DOP_LRP
), tmp
, src0
, src1
, src2
))
2206 if (!submit_op1(emit
, inst_token( SVGA3DOP_MOV
), dst
, src( tmp
)))
2215 * Translate/emit LRP (Linear Interpolation) instruction.
2218 emit_lrp(struct svga_shader_emitter
*emit
,
2219 const struct tgsi_full_instruction
*insn
)
2221 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
2222 const struct src_register src0
= translate_src_register(
2223 emit
, &insn
->Src
[0] );
2224 const struct src_register src1
= translate_src_register(
2225 emit
, &insn
->Src
[1] );
2226 const struct src_register src2
= translate_src_register(
2227 emit
, &insn
->Src
[2] );
2229 return submit_lrp(emit
, dst
, src0
, src1
, src2
);
2233 * Translate/emit DST (Distance function) instruction.
2236 emit_dst_insn(struct svga_shader_emitter
*emit
,
2237 const struct tgsi_full_instruction
*insn
)
2239 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
2240 /* SVGA/DX9 has a DST instruction, but only for vertex shaders:
2242 return emit_simple_instruction(emit
, SVGA3DOP_DST
, insn
);
2245 /* result[0] = 1 * 1;
2246 * result[1] = a[1] * b[1];
2247 * result[2] = a[2] * 1;
2248 * result[3] = 1 * b[3];
2250 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
2251 SVGA3dShaderDestToken tmp
;
2252 const struct src_register src0
= translate_src_register(
2253 emit
, &insn
->Src
[0] );
2254 const struct src_register src1
= translate_src_register(
2255 emit
, &insn
->Src
[1] );
2256 boolean need_tmp
= FALSE
;
2258 if (SVGA3dShaderGetRegType(dst
.value
) != SVGA3DREG_TEMP
||
2259 alias_src_dst(src0
, dst
) ||
2260 alias_src_dst(src1
, dst
))
2264 tmp
= get_temp( emit
);
2272 if (tmp
.mask
& TGSI_WRITEMASK_XW
) {
2273 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
2274 writemask(tmp
, TGSI_WRITEMASK_XW
),
2275 get_one_immediate(emit
)))
2281 if (tmp
.mask
& TGSI_WRITEMASK_YZ
) {
2282 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
2283 writemask(tmp
, TGSI_WRITEMASK_YZ
),
2288 /* tmp.yw = tmp * src1
2290 if (tmp
.mask
& TGSI_WRITEMASK_YW
) {
2291 if (!submit_op2( emit
, inst_token( SVGA3DOP_MUL
),
2292 writemask(tmp
, TGSI_WRITEMASK_YW
),
2301 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
2313 emit_exp(struct svga_shader_emitter
*emit
,
2314 const struct tgsi_full_instruction
*insn
)
2316 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
2317 struct src_register src0
=
2318 translate_src_register( emit
, &insn
->Src
[0] );
2319 SVGA3dShaderDestToken fraction
;
2321 if (dst
.mask
& TGSI_WRITEMASK_Y
)
2323 else if (dst
.mask
& TGSI_WRITEMASK_X
)
2324 fraction
= get_temp( emit
);
2328 /* If y is being written, fill it with src0 - floor(src0).
2330 if (dst
.mask
& TGSI_WRITEMASK_XY
) {
2331 if (!submit_op1( emit
, inst_token( SVGA3DOP_FRC
),
2332 writemask( fraction
, TGSI_WRITEMASK_Y
),
2337 /* If x is being written, fill it with 2 ^ floor(src0).
2339 if (dst
.mask
& TGSI_WRITEMASK_X
) {
2340 if (!submit_op2( emit
, inst_token( SVGA3DOP_ADD
),
2341 writemask( dst
, TGSI_WRITEMASK_X
),
2343 scalar( negate( src( fraction
) ), TGSI_SWIZZLE_Y
) ) )
2346 if (!submit_op1( emit
, inst_token( SVGA3DOP_EXP
),
2347 writemask( dst
, TGSI_WRITEMASK_X
),
2348 scalar( src( dst
), TGSI_SWIZZLE_X
) ) )
2351 if (!(dst
.mask
& TGSI_WRITEMASK_Y
))
2352 release_temp( emit
, fraction
);
2355 /* If z is being written, fill it with 2 ^ src0 (partial precision).
2357 if (dst
.mask
& TGSI_WRITEMASK_Z
) {
2358 if (!submit_op1( emit
, inst_token( SVGA3DOP_EXPP
),
2359 writemask( dst
, TGSI_WRITEMASK_Z
),
2364 /* If w is being written, fill it with one.
2366 if (dst
.mask
& TGSI_WRITEMASK_W
) {
2367 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
2368 writemask(dst
, TGSI_WRITEMASK_W
),
2369 get_one_immediate(emit
)))
2378 * Translate/emit LIT (Lighting helper) instruction.
2381 emit_lit(struct svga_shader_emitter
*emit
,
2382 const struct tgsi_full_instruction
*insn
)
2384 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
2385 /* SVGA/DX9 has a LIT instruction, but only for vertex shaders:
2387 return emit_simple_instruction(emit
, SVGA3DOP_LIT
, insn
);
2390 /* D3D vs. GL semantics can be fairly easily accomodated by
2391 * variations on this sequence.
2395 * tmp.z = pow(src.y,src.w)
2396 * p0 = src0.xxxx > 0
2397 * result = zero.wxxw
2398 * (p0) result.yz = tmp
2402 * tmp.z = pow(src.y,src.w)
2403 * p0 = src0.xxyy > 0
2404 * result = zero.wxxw
2405 * (p0) result.yz = tmp
2407 * Will implement the GL version for now.
2409 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
2410 SVGA3dShaderDestToken tmp
= get_temp( emit
);
2411 const struct src_register src0
= translate_src_register(
2412 emit
, &insn
->Src
[0] );
2414 /* tmp = pow(src.y, src.w)
2416 if (dst
.mask
& TGSI_WRITEMASK_Z
) {
2417 if (!submit_op2(emit
, inst_token( SVGA3DOP_POW
),
2426 if (dst
.mask
& TGSI_WRITEMASK_Y
) {
2427 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
2428 writemask(tmp
, TGSI_WRITEMASK_Y
),
2433 /* Can't quite do this with emit conditional due to the extra
2434 * writemask on the predicated mov:
2437 SVGA3dShaderDestToken pred_reg
= dst_register( SVGA3DREG_PREDICATE
, 0 );
2438 struct src_register predsrc
;
2440 /* D3D vs GL semantics:
2443 predsrc
= swizzle(src0
, 0, 0, 1, 1); /* D3D */
2445 predsrc
= swizzle(src0
, 0, 0, 0, 0); /* GL */
2447 /* SETP src0.xxyy, GT, {0}.x */
2448 if (!submit_op2( emit
,
2449 inst_token_setp(SVGA3DOPCOMP_GT
),
2452 get_zero_immediate(emit
)))
2456 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), dst
,
2457 get_immediate(emit
, 1.0f
, 0.0f
, 0.0f
, 1.0f
)))
2460 /* MOV dst.yz, tmp (predicated)
2462 * Note that the predicate reg (and possible modifiers) is passed
2463 * as the first source argument.
2465 if (dst
.mask
& TGSI_WRITEMASK_YZ
) {
2466 if (!submit_op2( emit
,
2467 inst_token_predicated(SVGA3DOP_MOV
),
2468 writemask(dst
, TGSI_WRITEMASK_YZ
),
2469 src( pred_reg
), src( tmp
) ))
2480 emit_ex2(struct svga_shader_emitter
*emit
,
2481 const struct tgsi_full_instruction
*insn
)
2483 SVGA3dShaderInstToken inst
;
2484 SVGA3dShaderDestToken dst
;
2485 struct src_register src0
;
2487 inst
= inst_token( SVGA3DOP_EXP
);
2488 dst
= translate_dst_register( emit
, insn
, 0 );
2489 src0
= translate_src_register( emit
, &insn
->Src
[0] );
2490 src0
= scalar( src0
, TGSI_SWIZZLE_X
);
2492 if (dst
.mask
!= TGSI_WRITEMASK_XYZW
) {
2493 SVGA3dShaderDestToken tmp
= get_temp( emit
);
2495 if (!submit_op1( emit
, inst
, tmp
, src0
))
2498 return submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
2500 scalar( src( tmp
), TGSI_SWIZZLE_X
) );
2503 return submit_op1( emit
, inst
, dst
, src0
);
2508 emit_log(struct svga_shader_emitter
*emit
,
2509 const struct tgsi_full_instruction
*insn
)
2511 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
2512 struct src_register src0
=
2513 translate_src_register( emit
, &insn
->Src
[0] );
2514 SVGA3dShaderDestToken abs_tmp
;
2515 struct src_register abs_src0
;
2516 SVGA3dShaderDestToken log2_abs
;
2520 if (dst
.mask
& TGSI_WRITEMASK_Z
)
2522 else if (dst
.mask
& TGSI_WRITEMASK_XY
)
2523 log2_abs
= get_temp( emit
);
2527 /* If z is being written, fill it with log2( abs( src0 ) ).
2529 if (dst
.mask
& TGSI_WRITEMASK_XYZ
) {
2530 if (!src0
.base
.srcMod
|| src0
.base
.srcMod
== SVGA3DSRCMOD_ABS
)
2533 abs_tmp
= get_temp( emit
);
2535 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
2540 abs_src0
= src( abs_tmp
);
2543 abs_src0
= absolute( scalar( abs_src0
, TGSI_SWIZZLE_X
) );
2545 if (!submit_op1( emit
, inst_token( SVGA3DOP_LOG
),
2546 writemask( log2_abs
, TGSI_WRITEMASK_Z
),
2551 if (dst
.mask
& TGSI_WRITEMASK_XY
) {
2552 SVGA3dShaderDestToken floor_log2
;
2554 if (dst
.mask
& TGSI_WRITEMASK_X
)
2557 floor_log2
= get_temp( emit
);
2559 /* If x is being written, fill it with floor( log2( abs( src0 ) ) ).
2561 if (!submit_op1( emit
, inst_token( SVGA3DOP_FRC
),
2562 writemask( floor_log2
, TGSI_WRITEMASK_X
),
2563 scalar( src( log2_abs
), TGSI_SWIZZLE_Z
) ) )
2566 if (!submit_op2( emit
, inst_token( SVGA3DOP_ADD
),
2567 writemask( floor_log2
, TGSI_WRITEMASK_X
),
2568 scalar( src( log2_abs
), TGSI_SWIZZLE_Z
),
2569 negate( src( floor_log2
) ) ) )
2572 /* If y is being written, fill it with
2573 * abs ( src0 ) / ( 2 ^ floor( log2( abs( src0 ) ) ) ).
2575 if (dst
.mask
& TGSI_WRITEMASK_Y
) {
2576 if (!submit_op1( emit
, inst_token( SVGA3DOP_EXP
),
2577 writemask( dst
, TGSI_WRITEMASK_Y
),
2578 negate( scalar( src( floor_log2
),
2579 TGSI_SWIZZLE_X
) ) ) )
2582 if (!submit_op2( emit
, inst_token( SVGA3DOP_MUL
),
2583 writemask( dst
, TGSI_WRITEMASK_Y
),
2589 if (!(dst
.mask
& TGSI_WRITEMASK_X
))
2590 release_temp( emit
, floor_log2
);
2592 if (!(dst
.mask
& TGSI_WRITEMASK_Z
))
2593 release_temp( emit
, log2_abs
);
2596 if (dst
.mask
& TGSI_WRITEMASK_XYZ
&& src0
.base
.srcMod
&&
2597 src0
.base
.srcMod
!= SVGA3DSRCMOD_ABS
)
2598 release_temp( emit
, abs_tmp
);
2600 /* If w is being written, fill it with one.
2602 if (dst
.mask
& TGSI_WRITEMASK_W
) {
2603 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
2604 writemask(dst
, TGSI_WRITEMASK_W
),
2605 get_one_immediate(emit
)))
2614 * Translate TGSI TRUNC or ROUND instruction.
2615 * We need to truncate toward zero. Ex: trunc(-1.9) = -1
2616 * Different approaches are needed for VS versus PS.
2619 emit_trunc_round(struct svga_shader_emitter
*emit
,
2620 const struct tgsi_full_instruction
*insn
,
2623 SVGA3dShaderDestToken dst
= translate_dst_register(emit
, insn
, 0);
2624 const struct src_register src0
=
2625 translate_src_register(emit
, &insn
->Src
[0] );
2626 SVGA3dShaderDestToken t1
= get_temp(emit
);
2629 SVGA3dShaderDestToken t0
= get_temp(emit
);
2630 struct src_register half
= get_half_immediate(emit
);
2632 /* t0 = abs(src0) + 0.5 */
2633 if (!submit_op2(emit
, inst_token(SVGA3DOP_ADD
), t0
,
2634 absolute(src0
), half
))
2637 /* t1 = fract(t0) */
2638 if (!submit_op1(emit
, inst_token(SVGA3DOP_FRC
), t1
, src(t0
)))
2642 if (!submit_op2(emit
, inst_token(SVGA3DOP_ADD
), t1
, src(t0
),
2649 /* t1 = fract(abs(src0)) */
2650 if (!submit_op1(emit
, inst_token(SVGA3DOP_FRC
), t1
, absolute(src0
)))
2653 /* t1 = abs(src0) - t1 */
2654 if (!submit_op2(emit
, inst_token(SVGA3DOP_ADD
), t1
, absolute(src0
),
2660 * Now we need to multiply t1 by the sign of the original value.
2662 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
2663 /* For VS: use SGN instruction */
2664 /* Need two extra/dummy registers: */
2665 SVGA3dShaderDestToken t2
= get_temp(emit
), t3
= get_temp(emit
),
2666 t4
= get_temp(emit
);
2668 /* t2 = sign(src0) */
2669 if (!submit_op3(emit
, inst_token(SVGA3DOP_SGN
), t2
, src0
,
2674 if (!submit_op2(emit
, inst_token(SVGA3DOP_MUL
), dst
, src(t1
), src(t2
)))
2678 /* For FS: Use CMP instruction */
2679 return submit_op3(emit
, inst_token( SVGA3DOP_CMP
), dst
,
2680 src0
, src(t1
), negate(src(t1
)));
2688 * Translate/emit "begin subroutine" instruction/marker/label.
2691 emit_bgnsub(struct svga_shader_emitter
*emit
,
2693 const struct tgsi_full_instruction
*insn
)
2697 /* Note that we've finished the main function and are now emitting
2698 * subroutines. This affects how we terminate the generated
2701 emit
->in_main_func
= FALSE
;
2703 for (i
= 0; i
< emit
->nr_labels
; i
++) {
2704 if (emit
->label
[i
] == position
) {
2705 return (emit_instruction( emit
, inst_token( SVGA3DOP_RET
) ) &&
2706 emit_instruction( emit
, inst_token( SVGA3DOP_LABEL
) ) &&
2707 emit_src( emit
, src_register( SVGA3DREG_LABEL
, i
)));
2717 * Translate/emit subroutine call instruction.
2720 emit_call(struct svga_shader_emitter
*emit
,
2721 const struct tgsi_full_instruction
*insn
)
2723 unsigned position
= insn
->Label
.Label
;
2726 for (i
= 0; i
< emit
->nr_labels
; i
++) {
2727 if (emit
->label
[i
] == position
)
2731 if (emit
->nr_labels
== ARRAY_SIZE(emit
->label
))
2734 if (i
== emit
->nr_labels
) {
2735 emit
->label
[i
] = position
;
2739 return (emit_instruction( emit
, inst_token( SVGA3DOP_CALL
) ) &&
2740 emit_src( emit
, src_register( SVGA3DREG_LABEL
, i
)));
2745 * Called at the end of the shader. Actually, emit special "fix-up"
2746 * code for the vertex/fragment shader.
2749 emit_end(struct svga_shader_emitter
*emit
)
2751 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
2752 return emit_vs_postamble( emit
);
2755 return emit_ps_postamble( emit
);
2761 * Translate any TGSI instruction to SVGA.
2764 svga_emit_instruction(struct svga_shader_emitter
*emit
,
2766 const struct tgsi_full_instruction
*insn
)
2768 switch (insn
->Instruction
.Opcode
) {
2770 case TGSI_OPCODE_ARL
:
2771 return emit_arl( emit
, insn
);
2773 case TGSI_OPCODE_TEX
:
2774 case TGSI_OPCODE_TXB
:
2775 case TGSI_OPCODE_TXP
:
2776 case TGSI_OPCODE_TXL
:
2777 case TGSI_OPCODE_TXD
:
2778 return emit_tex( emit
, insn
);
2780 case TGSI_OPCODE_DDX
:
2781 case TGSI_OPCODE_DDY
:
2782 return emit_deriv( emit
, insn
);
2784 case TGSI_OPCODE_BGNSUB
:
2785 return emit_bgnsub( emit
, position
, insn
);
2787 case TGSI_OPCODE_ENDSUB
:
2790 case TGSI_OPCODE_CAL
:
2791 return emit_call( emit
, insn
);
2793 case TGSI_OPCODE_FLR
:
2794 return emit_floor( emit
, insn
);
2796 case TGSI_OPCODE_TRUNC
:
2797 return emit_trunc_round( emit
, insn
, FALSE
);
2799 case TGSI_OPCODE_ROUND
:
2800 return emit_trunc_round( emit
, insn
, TRUE
);
2802 case TGSI_OPCODE_CEIL
:
2803 return emit_ceil( emit
, insn
);
2805 case TGSI_OPCODE_CMP
:
2806 return emit_cmp( emit
, insn
);
2808 case TGSI_OPCODE_DIV
:
2809 return emit_div( emit
, insn
);
2811 case TGSI_OPCODE_DP2
:
2812 return emit_dp2( emit
, insn
);
2814 case TGSI_OPCODE_COS
:
2815 return emit_cos( emit
, insn
);
2817 case TGSI_OPCODE_SIN
:
2818 return emit_sin( emit
, insn
);
2820 case TGSI_OPCODE_END
:
2821 /* TGSI always finishes the main func with an END */
2822 return emit_end( emit
);
2824 case TGSI_OPCODE_KILL_IF
:
2825 return emit_kill_if( emit
, insn
);
2827 /* Selection opcodes. The underlying language is fairly
2828 * non-orthogonal about these.
2830 case TGSI_OPCODE_SEQ
:
2831 return emit_select_op( emit
, PIPE_FUNC_EQUAL
, insn
);
2833 case TGSI_OPCODE_SNE
:
2834 return emit_select_op( emit
, PIPE_FUNC_NOTEQUAL
, insn
);
2836 case TGSI_OPCODE_SGT
:
2837 return emit_select_op( emit
, PIPE_FUNC_GREATER
, insn
);
2839 case TGSI_OPCODE_SGE
:
2840 return emit_select_op( emit
, PIPE_FUNC_GEQUAL
, insn
);
2842 case TGSI_OPCODE_SLT
:
2843 return emit_select_op( emit
, PIPE_FUNC_LESS
, insn
);
2845 case TGSI_OPCODE_SLE
:
2846 return emit_select_op( emit
, PIPE_FUNC_LEQUAL
, insn
);
2848 case TGSI_OPCODE_POW
:
2849 return emit_pow( emit
, insn
);
2851 case TGSI_OPCODE_EX2
:
2852 return emit_ex2( emit
, insn
);
2854 case TGSI_OPCODE_EXP
:
2855 return emit_exp( emit
, insn
);
2857 case TGSI_OPCODE_LOG
:
2858 return emit_log( emit
, insn
);
2860 case TGSI_OPCODE_LG2
:
2861 return emit_scalar_op1( emit
, SVGA3DOP_LOG
, insn
);
2863 case TGSI_OPCODE_RSQ
:
2864 return emit_scalar_op1( emit
, SVGA3DOP_RSQ
, insn
);
2866 case TGSI_OPCODE_RCP
:
2867 return emit_scalar_op1( emit
, SVGA3DOP_RCP
, insn
);
2869 case TGSI_OPCODE_CONT
:
2870 /* not expected (we return PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED = 0) */
2873 case TGSI_OPCODE_RET
:
2874 /* This is a noop -- we tell mesa that we can't support RET
2875 * within a function (early return), so this will always be
2876 * followed by an ENDSUB.
2880 /* These aren't actually used by any of the frontends we care
2883 case TGSI_OPCODE_AND
:
2884 case TGSI_OPCODE_OR
:
2885 case TGSI_OPCODE_I2F
:
2886 case TGSI_OPCODE_NOT
:
2887 case TGSI_OPCODE_SHL
:
2888 case TGSI_OPCODE_ISHR
:
2889 case TGSI_OPCODE_XOR
:
2892 case TGSI_OPCODE_IF
:
2893 return emit_if( emit
, insn
);
2894 case TGSI_OPCODE_ELSE
:
2895 return emit_else( emit
, insn
);
2896 case TGSI_OPCODE_ENDIF
:
2897 return emit_endif( emit
, insn
);
2899 case TGSI_OPCODE_BGNLOOP
:
2900 return emit_bgnloop( emit
, insn
);
2901 case TGSI_OPCODE_ENDLOOP
:
2902 return emit_endloop( emit
, insn
);
2903 case TGSI_OPCODE_BRK
:
2904 return emit_brk( emit
, insn
);
2906 case TGSI_OPCODE_KILL
:
2907 return emit_kill( emit
, insn
);
2909 case TGSI_OPCODE_DST
:
2910 return emit_dst_insn( emit
, insn
);
2912 case TGSI_OPCODE_LIT
:
2913 return emit_lit( emit
, insn
);
2915 case TGSI_OPCODE_LRP
:
2916 return emit_lrp( emit
, insn
);
2918 case TGSI_OPCODE_SSG
:
2919 return emit_ssg( emit
, insn
);
2921 case TGSI_OPCODE_MOV
:
2922 return emit_mov( emit
, insn
);
2926 SVGA3dShaderOpCodeType opcode
=
2927 translate_opcode(insn
->Instruction
.Opcode
);
2929 if (opcode
== SVGA3DOP_LAST_INST
)
2932 if (!emit_simple_instruction( emit
, opcode
, insn
))
2942 * Translate/emit a TGSI IMMEDIATE declaration.
2943 * An immediate vector is a constant that's hard-coded into the shader.
2946 svga_emit_immediate(struct svga_shader_emitter
*emit
,
2947 const struct tgsi_full_immediate
*imm
)
2949 static const float id
[4] = {0,0,0,1};
2953 assert(1 <= imm
->Immediate
.NrTokens
&& imm
->Immediate
.NrTokens
<= 5);
2954 for (i
= 0; i
< 4 && i
< imm
->Immediate
.NrTokens
- 1; i
++) {
2955 float f
= imm
->u
[i
].Float
;
2956 value
[i
] = util_is_inf_or_nan(f
) ? 0.0f
: f
;
2959 /* If the immediate has less than four values, fill in the remaining
2960 * positions from id={0,0,0,1}.
2962 for ( ; i
< 4; i
++ )
2965 return emit_def_const( emit
, SVGA3D_CONST_TYPE_FLOAT
,
2966 emit
->imm_start
+ emit
->internal_imm_count
++,
2967 value
[0], value
[1], value
[2], value
[3]);
2972 make_immediate(struct svga_shader_emitter
*emit
,
2973 float a
, float b
, float c
, float d
,
2974 struct src_register
*out
)
2976 unsigned idx
= emit
->nr_hw_float_const
++;
2978 if (!emit_def_const( emit
, SVGA3D_CONST_TYPE_FLOAT
,
2982 *out
= src_register( SVGA3DREG_CONST
, idx
);
2989 * Emit special VS instructions at top of shader.
2992 emit_vs_preamble(struct svga_shader_emitter
*emit
)
2994 if (!emit
->key
.vs
.need_prescale
) {
2995 if (!make_immediate( emit
, 0, 0, .5, .5,
3005 * Emit special PS instructions at top of shader.
3008 emit_ps_preamble(struct svga_shader_emitter
*emit
)
3010 if (emit
->ps_reads_pos
&& emit
->info
.reads_z
) {
3012 * Assemble the position from various bits of inputs. Depth and W are
3013 * passed in a texcoord this is due to D3D's vPos not hold Z or W.
3014 * Also fixup the perspective interpolation.
3016 * temp_pos.xy = vPos.xy
3017 * temp_pos.w = rcp(texcoord1.w);
3018 * temp_pos.z = texcoord1.z * temp_pos.w;
3020 if (!submit_op1( emit
,
3021 inst_token(SVGA3DOP_MOV
),
3022 writemask( emit
->ps_temp_pos
, TGSI_WRITEMASK_XY
),
3023 emit
->ps_true_pos
))
3026 if (!submit_op1( emit
,
3027 inst_token(SVGA3DOP_RCP
),
3028 writemask( emit
->ps_temp_pos
, TGSI_WRITEMASK_W
),
3029 scalar( emit
->ps_depth_pos
, TGSI_SWIZZLE_W
) ))
3032 if (!submit_op2( emit
,
3033 inst_token(SVGA3DOP_MUL
),
3034 writemask( emit
->ps_temp_pos
, TGSI_WRITEMASK_Z
),
3035 scalar( emit
->ps_depth_pos
, TGSI_SWIZZLE_Z
),
3036 scalar( src(emit
->ps_temp_pos
), TGSI_SWIZZLE_W
) ))
3045 * Emit special PS instructions at end of shader.
3048 emit_ps_postamble(struct svga_shader_emitter
*emit
)
3052 /* PS oDepth is incredibly fragile and it's very hard to catch the
3053 * types of usage that break it during shader emit. Easier just to
3054 * redirect the main program to a temporary and then only touch
3055 * oDepth with a hand-crafted MOV below.
3057 if (SVGA3dShaderGetRegType(emit
->true_pos
.value
) != 0) {
3058 if (!submit_op1( emit
,
3059 inst_token(SVGA3DOP_MOV
),
3061 scalar(src(emit
->temp_pos
), TGSI_SWIZZLE_Z
) ))
3065 for (i
= 0; i
< PIPE_MAX_COLOR_BUFS
; i
++) {
3066 if (SVGA3dShaderGetRegType(emit
->true_color_output
[i
].value
) != 0) {
3067 /* Potentially override output colors with white for XOR
3068 * logicop workaround.
3070 if (emit
->unit
== PIPE_SHADER_FRAGMENT
&&
3071 emit
->key
.fs
.white_fragments
) {
3072 struct src_register one
= get_one_immediate(emit
);
3074 if (!submit_op1( emit
,
3075 inst_token(SVGA3DOP_MOV
),
3076 emit
->true_color_output
[i
],
3080 else if (emit
->unit
== PIPE_SHADER_FRAGMENT
&&
3081 i
< emit
->key
.fs
.write_color0_to_n_cbufs
) {
3082 /* Write temp color output [0] to true output [i] */
3083 if (!submit_op1(emit
, inst_token(SVGA3DOP_MOV
),
3084 emit
->true_color_output
[i
],
3085 src(emit
->temp_color_output
[0]))) {
3090 if (!submit_op1( emit
,
3091 inst_token(SVGA3DOP_MOV
),
3092 emit
->true_color_output
[i
],
3093 src(emit
->temp_color_output
[i
]) ))
3104 * Emit special VS instructions at end of shader.
3107 emit_vs_postamble(struct svga_shader_emitter
*emit
)
3109 /* PSIZ output is incredibly fragile and it's very hard to catch
3110 * the types of usage that break it during shader emit. Easier
3111 * just to redirect the main program to a temporary and then only
3112 * touch PSIZ with a hand-crafted MOV below.
3114 if (SVGA3dShaderGetRegType(emit
->true_psiz
.value
) != 0) {
3115 if (!submit_op1( emit
,
3116 inst_token(SVGA3DOP_MOV
),
3118 scalar(src(emit
->temp_psiz
), TGSI_SWIZZLE_X
) ))
3122 /* Need to perform various manipulations on vertex position to cope
3123 * with the different GL and D3D clip spaces.
3125 if (emit
->key
.vs
.need_prescale
) {
3126 SVGA3dShaderDestToken temp_pos
= emit
->temp_pos
;
3127 SVGA3dShaderDestToken depth
= emit
->depth_pos
;
3128 SVGA3dShaderDestToken pos
= emit
->true_pos
;
3129 unsigned offset
= emit
->info
.file_max
[TGSI_FILE_CONSTANT
] + 1;
3130 struct src_register prescale_scale
= src_register( SVGA3DREG_CONST
,
3132 struct src_register prescale_trans
= src_register( SVGA3DREG_CONST
,
3135 if (!submit_op1( emit
,
3136 inst_token(SVGA3DOP_MOV
),
3137 writemask(depth
, TGSI_WRITEMASK_W
),
3138 scalar(src(temp_pos
), TGSI_SWIZZLE_W
) ))
3141 /* MUL temp_pos.xyz, temp_pos, prescale.scale
3142 * MAD result.position, temp_pos.wwww, prescale.trans, temp_pos
3143 * --> Note that prescale.trans.w == 0
3145 if (!submit_op2( emit
,
3146 inst_token(SVGA3DOP_MUL
),
3147 writemask(temp_pos
, TGSI_WRITEMASK_XYZ
),
3152 if (!submit_op3( emit
,
3153 inst_token(SVGA3DOP_MAD
),
3155 swizzle(src(temp_pos
), 3, 3, 3, 3),
3160 /* Also write to depth value */
3161 if (!submit_op3( emit
,
3162 inst_token(SVGA3DOP_MAD
),
3163 writemask(depth
, TGSI_WRITEMASK_Z
),
3164 swizzle(src(temp_pos
), 3, 3, 3, 3),
3170 SVGA3dShaderDestToken temp_pos
= emit
->temp_pos
;
3171 SVGA3dShaderDestToken depth
= emit
->depth_pos
;
3172 SVGA3dShaderDestToken pos
= emit
->true_pos
;
3173 struct src_register imm_0055
= emit
->imm_0055
;
3175 /* Adjust GL clipping coordinate space to hardware (D3D-style):
3177 * DP4 temp_pos.z, {0,0,.5,.5}, temp_pos
3178 * MOV result.position, temp_pos
3180 if (!submit_op2( emit
,
3181 inst_token(SVGA3DOP_DP4
),
3182 writemask(temp_pos
, TGSI_WRITEMASK_Z
),
3187 if (!submit_op1( emit
,
3188 inst_token(SVGA3DOP_MOV
),
3193 /* Move the manipulated depth into the extra texcoord reg */
3194 if (!submit_op1( emit
,
3195 inst_token(SVGA3DOP_MOV
),
3196 writemask(depth
, TGSI_WRITEMASK_ZW
),
3206 * For the pixel shader: emit the code which chooses the front
3207 * or back face color depending on triangle orientation.
3208 * This happens at the top of the fragment shader.
3211 * 1: COLOR = FrontColor;
3213 * 3: COLOR = BackColor;
3217 emit_light_twoside(struct svga_shader_emitter
*emit
)
3219 struct src_register vface
, zero
;
3220 struct src_register front
[2];
3221 struct src_register back
[2];
3222 SVGA3dShaderDestToken color
[2];
3223 int count
= emit
->internal_color_count
;
3225 SVGA3dShaderInstToken if_token
;
3230 vface
= get_vface( emit
);
3231 zero
= get_zero_immediate(emit
);
3233 /* Can't use get_temp() to allocate the color reg as such
3234 * temporaries will be reclaimed after each instruction by the call
3235 * to reset_temp_regs().
3237 for (i
= 0; i
< count
; i
++) {
3238 color
[i
] = dst_register( SVGA3DREG_TEMP
, emit
->nr_hw_temp
++ );
3239 front
[i
] = emit
->input_map
[emit
->internal_color_idx
[i
]];
3241 /* Back is always the next input:
3244 back
[i
].base
.num
= front
[i
].base
.num
+ 1;
3246 /* Reassign the input_map to the actual front-face color:
3248 emit
->input_map
[emit
->internal_color_idx
[i
]] = src(color
[i
]);
3251 if_token
= inst_token( SVGA3DOP_IFC
);
3253 if (emit
->key
.fs
.front_ccw
)
3254 if_token
.control
= SVGA3DOPCOMP_LT
;
3256 if_token
.control
= SVGA3DOPCOMP_GT
;
3258 if (!(emit_instruction( emit
, if_token
) &&
3259 emit_src( emit
, vface
) &&
3260 emit_src( emit
, zero
) ))
3263 for (i
= 0; i
< count
; i
++) {
3264 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), color
[i
], front
[i
] ))
3268 if (!(emit_instruction( emit
, inst_token( SVGA3DOP_ELSE
))))
3271 for (i
= 0; i
< count
; i
++) {
3272 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), color
[i
], back
[i
] ))
3276 if (!emit_instruction( emit
, inst_token( SVGA3DOP_ENDIF
) ))
3284 * Emit special setup code for the front/back face register in the FS.
3285 * 0: SETP_GT TEMP, VFACE, 0
3286 * where TEMP is a fake frontface register
3289 emit_frontface(struct svga_shader_emitter
*emit
)
3291 struct src_register vface
;
3292 SVGA3dShaderDestToken temp
;
3293 struct src_register pass
, fail
;
3295 vface
= get_vface( emit
);
3297 /* Can't use get_temp() to allocate the fake frontface reg as such
3298 * temporaries will be reclaimed after each instruction by the call
3299 * to reset_temp_regs().
3301 temp
= dst_register( SVGA3DREG_TEMP
,
3302 emit
->nr_hw_temp
++ );
3304 if (emit
->key
.fs
.front_ccw
) {
3305 pass
= get_zero_immediate(emit
);
3306 fail
= get_one_immediate(emit
);
3308 pass
= get_one_immediate(emit
);
3309 fail
= get_zero_immediate(emit
);
3312 if (!emit_conditional(emit
, PIPE_FUNC_GREATER
,
3313 temp
, vface
, get_zero_immediate(emit
),
3317 /* Reassign the input_map to the actual front-face color:
3319 emit
->input_map
[emit
->internal_frontface_idx
] = src(temp
);
3326 * Emit code to invert the T component of the incoming texture coordinate.
3327 * This is used for drawing point sprites when
3328 * pipe_rasterizer_state::sprite_coord_mode == PIPE_SPRITE_COORD_LOWER_LEFT.
3331 emit_inverted_texcoords(struct svga_shader_emitter
*emit
)
3333 unsigned inverted_texcoords
= emit
->inverted_texcoords
;
3335 while (inverted_texcoords
) {
3336 const unsigned unit
= ffs(inverted_texcoords
) - 1;
3338 assert(emit
->inverted_texcoords
& (1 << unit
));
3340 assert(unit
< ARRAY_SIZE(emit
->ps_true_texcoord
));
3342 assert(unit
< ARRAY_SIZE(emit
->ps_inverted_texcoord_input
));
3344 assert(emit
->ps_inverted_texcoord_input
[unit
]
3345 < ARRAY_SIZE(emit
->input_map
));
3347 /* inverted = coord * (1, -1, 1, 1) + (0, 1, 0, 0) */
3348 if (!submit_op3(emit
,
3349 inst_token(SVGA3DOP_MAD
),
3350 dst(emit
->ps_inverted_texcoord
[unit
]),
3351 emit
->ps_true_texcoord
[unit
],
3352 get_immediate(emit
, 1.0f
, -1.0f
, 1.0f
, 1.0f
),
3353 get_immediate(emit
, 0.0f
, 1.0f
, 0.0f
, 0.0f
)))
3356 /* Reassign the input_map entry to the new texcoord register */
3357 emit
->input_map
[emit
->ps_inverted_texcoord_input
[unit
]] =
3358 emit
->ps_inverted_texcoord
[unit
];
3360 inverted_texcoords
&= ~(1 << unit
);
3368 * Emit code to adjust vertex shader inputs/attributes:
3369 * - Change range from [0,1] to [-1,1] (for normalized byte/short attribs).
3370 * - Set attrib W component = 1.
3373 emit_adjusted_vertex_attribs(struct svga_shader_emitter
*emit
)
3375 unsigned adjust_mask
= (emit
->key
.vs
.adjust_attrib_range
|
3376 emit
->key
.vs
.adjust_attrib_w_1
);
3378 while (adjust_mask
) {
3379 /* Adjust vertex attrib range and/or set W component = 1 */
3380 const unsigned index
= u_bit_scan(&adjust_mask
);
3381 struct src_register tmp
;
3383 /* allocate a temp reg */
3384 tmp
= src_register(SVGA3DREG_TEMP
, emit
->nr_hw_temp
);
3387 if (emit
->key
.vs
.adjust_attrib_range
& (1 << index
)) {
3388 /* The vertex input/attribute is supposed to be a signed value in
3389 * the range [-1,1] but we actually fetched/converted it to the
3390 * range [0,1]. This most likely happens when the app specifies a
3391 * signed byte attribute but we interpreted it as unsigned bytes.
3392 * See also svga_translate_vertex_format().
3394 * Here, we emit some extra instructions to adjust
3395 * the attribute values from [0,1] to [-1,1].
3397 * The adjustment we implement is:
3398 * new_attrib = attrib * 2.0;
3399 * if (attrib >= 0.5)
3400 * new_attrib = new_attrib - 2.0;
3401 * This isn't exactly right (it's off by a bit or so) but close enough.
3403 SVGA3dShaderDestToken pred_reg
= dst_register(SVGA3DREG_PREDICATE
, 0);
3405 /* tmp = attrib * 2.0 */
3406 if (!submit_op2(emit
,
3407 inst_token(SVGA3DOP_MUL
),
3409 emit
->input_map
[index
],
3410 get_two_immediate(emit
)))
3413 /* pred = (attrib >= 0.5) */
3414 if (!submit_op2(emit
,
3415 inst_token_setp(SVGA3DOPCOMP_GE
),
3417 emit
->input_map
[index
], /* vert attrib */
3418 get_half_immediate(emit
))) /* 0.5 */
3421 /* sub(pred) tmp, tmp, 2.0 */
3422 if (!submit_op3(emit
,
3423 inst_token_predicated(SVGA3DOP_SUB
),
3427 get_two_immediate(emit
)))
3431 /* just copy the vertex input attrib to the temp register */
3432 if (!submit_op1(emit
,
3433 inst_token(SVGA3DOP_MOV
),
3435 emit
->input_map
[index
]))
3439 if (emit
->key
.vs
.adjust_attrib_w_1
& (1 << index
)) {
3440 /* move 1 into W position of tmp */
3441 if (!submit_op1(emit
,
3442 inst_token(SVGA3DOP_MOV
),
3443 writemask(dst(tmp
), TGSI_WRITEMASK_W
),
3444 get_one_immediate(emit
)))
3448 /* Reassign the input_map entry to the new tmp register */
3449 emit
->input_map
[index
] = tmp
;
3457 * Determine if we need to create the "common" immediate value which is
3458 * used for generating useful vector constants such as {0,0,0,0} and
3460 * We could just do this all the time except that we want to conserve
3461 * registers whenever possible.
3464 needs_to_create_common_immediate(const struct svga_shader_emitter
*emit
)
3468 if (emit
->unit
== PIPE_SHADER_FRAGMENT
) {
3469 if (emit
->key
.fs
.light_twoside
)
3472 if (emit
->key
.fs
.white_fragments
)
3475 if (emit
->emit_frontface
)
3478 if (emit
->info
.opcode_count
[TGSI_OPCODE_DST
] >= 1 ||
3479 emit
->info
.opcode_count
[TGSI_OPCODE_SSG
] >= 1 ||
3480 emit
->info
.opcode_count
[TGSI_OPCODE_LIT
] >= 1)
3483 if (emit
->inverted_texcoords
)
3486 /* look for any PIPE_SWIZZLE_0/ONE terms */
3487 for (i
= 0; i
< emit
->key
.num_textures
; i
++) {
3488 if (emit
->key
.tex
[i
].swizzle_r
> PIPE_SWIZZLE_W
||
3489 emit
->key
.tex
[i
].swizzle_g
> PIPE_SWIZZLE_W
||
3490 emit
->key
.tex
[i
].swizzle_b
> PIPE_SWIZZLE_W
||
3491 emit
->key
.tex
[i
].swizzle_a
> PIPE_SWIZZLE_W
)
3495 for (i
= 0; i
< emit
->key
.num_textures
; i
++) {
3496 if (emit
->key
.tex
[i
].compare_mode
3497 == PIPE_TEX_COMPARE_R_TO_TEXTURE
)
3501 else if (emit
->unit
== PIPE_SHADER_VERTEX
) {
3502 if (emit
->info
.opcode_count
[TGSI_OPCODE_CMP
] >= 1)
3504 if (emit
->key
.vs
.adjust_attrib_range
||
3505 emit
->key
.vs
.adjust_attrib_w_1
)
3509 if (emit
->info
.opcode_count
[TGSI_OPCODE_IF
] >= 1 ||
3510 emit
->info
.opcode_count
[TGSI_OPCODE_BGNLOOP
] >= 1 ||
3511 emit
->info
.opcode_count
[TGSI_OPCODE_DDX
] >= 1 ||
3512 emit
->info
.opcode_count
[TGSI_OPCODE_DDY
] >= 1 ||
3513 emit
->info
.opcode_count
[TGSI_OPCODE_ROUND
] >= 1 ||
3514 emit
->info
.opcode_count
[TGSI_OPCODE_SGE
] >= 1 ||
3515 emit
->info
.opcode_count
[TGSI_OPCODE_SGT
] >= 1 ||
3516 emit
->info
.opcode_count
[TGSI_OPCODE_SLE
] >= 1 ||
3517 emit
->info
.opcode_count
[TGSI_OPCODE_SLT
] >= 1 ||
3518 emit
->info
.opcode_count
[TGSI_OPCODE_SNE
] >= 1 ||
3519 emit
->info
.opcode_count
[TGSI_OPCODE_SEQ
] >= 1 ||
3520 emit
->info
.opcode_count
[TGSI_OPCODE_EXP
] >= 1 ||
3521 emit
->info
.opcode_count
[TGSI_OPCODE_LOG
] >= 1 ||
3522 emit
->info
.opcode_count
[TGSI_OPCODE_KILL
] >= 1)
3530 * Do we need to create a looping constant?
3533 needs_to_create_loop_const(const struct svga_shader_emitter
*emit
)
3535 return (emit
->info
.opcode_count
[TGSI_OPCODE_BGNLOOP
] >= 1);
3540 needs_to_create_arl_consts(const struct svga_shader_emitter
*emit
)
3542 return (emit
->num_arl_consts
> 0);
3547 pre_parse_add_indirect( struct svga_shader_emitter
*emit
,
3548 int num
, int current_arl
)
3553 for (i
= 0; i
< emit
->num_arl_consts
; ++i
) {
3554 if (emit
->arl_consts
[i
].arl_num
== current_arl
)
3558 if (emit
->num_arl_consts
== i
) {
3559 ++emit
->num_arl_consts
;
3561 emit
->arl_consts
[i
].number
= (emit
->arl_consts
[i
].number
> num
) ?
3563 emit
->arl_consts
[i
].number
;
3564 emit
->arl_consts
[i
].arl_num
= current_arl
;
3570 pre_parse_instruction( struct svga_shader_emitter
*emit
,
3571 const struct tgsi_full_instruction
*insn
,
3574 if (insn
->Src
[0].Register
.Indirect
&&
3575 insn
->Src
[0].Indirect
.File
== TGSI_FILE_ADDRESS
) {
3576 const struct tgsi_full_src_register
*reg
= &insn
->Src
[0];
3577 if (reg
->Register
.Index
< 0) {
3578 pre_parse_add_indirect(emit
, reg
->Register
.Index
, current_arl
);
3582 if (insn
->Src
[1].Register
.Indirect
&&
3583 insn
->Src
[1].Indirect
.File
== TGSI_FILE_ADDRESS
) {
3584 const struct tgsi_full_src_register
*reg
= &insn
->Src
[1];
3585 if (reg
->Register
.Index
< 0) {
3586 pre_parse_add_indirect(emit
, reg
->Register
.Index
, current_arl
);
3590 if (insn
->Src
[2].Register
.Indirect
&&
3591 insn
->Src
[2].Indirect
.File
== TGSI_FILE_ADDRESS
) {
3592 const struct tgsi_full_src_register
*reg
= &insn
->Src
[2];
3593 if (reg
->Register
.Index
< 0) {
3594 pre_parse_add_indirect(emit
, reg
->Register
.Index
, current_arl
);
3603 pre_parse_tokens( struct svga_shader_emitter
*emit
,
3604 const struct tgsi_token
*tokens
)
3606 struct tgsi_parse_context parse
;
3607 int current_arl
= 0;
3609 tgsi_parse_init( &parse
, tokens
);
3611 while (!tgsi_parse_end_of_tokens( &parse
)) {
3612 tgsi_parse_token( &parse
);
3613 switch (parse
.FullToken
.Token
.Type
) {
3614 case TGSI_TOKEN_TYPE_IMMEDIATE
:
3615 case TGSI_TOKEN_TYPE_DECLARATION
:
3617 case TGSI_TOKEN_TYPE_INSTRUCTION
:
3618 if (parse
.FullToken
.FullInstruction
.Instruction
.Opcode
==
3622 if (!pre_parse_instruction( emit
, &parse
.FullToken
.FullInstruction
,
3636 svga_shader_emit_helpers(struct svga_shader_emitter
*emit
)
3638 if (needs_to_create_common_immediate( emit
)) {
3639 create_common_immediate( emit
);
3641 if (needs_to_create_loop_const( emit
)) {
3642 create_loop_const( emit
);
3644 if (needs_to_create_arl_consts( emit
)) {
3645 create_arl_consts( emit
);
3648 if (emit
->unit
== PIPE_SHADER_FRAGMENT
) {
3649 if (!svga_shader_emit_samplers_decl( emit
))
3652 if (!emit_ps_preamble( emit
))
3655 if (emit
->key
.fs
.light_twoside
) {
3656 if (!emit_light_twoside( emit
))
3659 if (emit
->emit_frontface
) {
3660 if (!emit_frontface( emit
))
3663 if (emit
->inverted_texcoords
) {
3664 if (!emit_inverted_texcoords( emit
))
3669 assert(emit
->unit
== PIPE_SHADER_VERTEX
);
3670 if (emit
->key
.vs
.adjust_attrib_range
) {
3671 if (!emit_adjusted_vertex_attribs(emit
) ||
3672 emit
->key
.vs
.adjust_attrib_w_1
) {
3683 * This is the main entrypoint into the TGSI instruction translater.
3684 * Translate TGSI shader tokens into an SVGA shader.
3687 svga_shader_emit_instructions(struct svga_shader_emitter
*emit
,
3688 const struct tgsi_token
*tokens
)
3690 struct tgsi_parse_context parse
;
3691 const struct tgsi_token
*new_tokens
= NULL
;
3693 boolean helpers_emitted
= FALSE
;
3694 unsigned line_nr
= 0;
3696 if (emit
->unit
== PIPE_SHADER_FRAGMENT
&& emit
->key
.fs
.pstipple
) {
3699 new_tokens
= util_pstipple_create_fragment_shader(tokens
, &unit
, 0,
3703 /* Setup texture state for stipple */
3704 emit
->sampler_target
[unit
] = TGSI_TEXTURE_2D
;
3705 emit
->key
.tex
[unit
].swizzle_r
= TGSI_SWIZZLE_X
;
3706 emit
->key
.tex
[unit
].swizzle_g
= TGSI_SWIZZLE_Y
;
3707 emit
->key
.tex
[unit
].swizzle_b
= TGSI_SWIZZLE_Z
;
3708 emit
->key
.tex
[unit
].swizzle_a
= TGSI_SWIZZLE_W
;
3710 emit
->pstipple_sampler_unit
= unit
;
3712 tokens
= new_tokens
;
3716 tgsi_parse_init( &parse
, tokens
);
3717 emit
->internal_imm_count
= 0;
3719 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
3720 ret
= emit_vs_preamble( emit
);
3725 pre_parse_tokens(emit
, tokens
);
3727 while (!tgsi_parse_end_of_tokens( &parse
)) {
3728 tgsi_parse_token( &parse
);
3730 switch (parse
.FullToken
.Token
.Type
) {
3731 case TGSI_TOKEN_TYPE_IMMEDIATE
:
3732 ret
= svga_emit_immediate( emit
, &parse
.FullToken
.FullImmediate
);
3737 case TGSI_TOKEN_TYPE_DECLARATION
:
3738 ret
= svga_translate_decl_sm30( emit
, &parse
.FullToken
.FullDeclaration
);
3743 case TGSI_TOKEN_TYPE_INSTRUCTION
:
3744 if (!helpers_emitted
) {
3745 if (!svga_shader_emit_helpers( emit
))
3747 helpers_emitted
= TRUE
;
3749 ret
= svga_emit_instruction( emit
,
3751 &parse
.FullToken
.FullInstruction
);
3759 reset_temp_regs( emit
);
3762 /* Need to terminate the current subroutine. Note that the
3763 * hardware doesn't tolerate shaders without sub-routines
3764 * terminating with RET+END.
3766 if (!emit
->in_main_func
) {
3767 ret
= emit_instruction( emit
, inst_token( SVGA3DOP_RET
) );
3772 assert(emit
->dynamic_branching_level
== 0);
3774 /* Need to terminate the whole shader:
3776 ret
= emit_instruction( emit
, inst_token( SVGA3DOP_END
) );
3781 tgsi_parse_free( &parse
);
3783 tgsi_free_tokens(new_tokens
);