1 /**********************************************************
2 * Copyright 2008-2009 VMware, Inc. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 **********************************************************/
27 #include "pipe/p_shader_tokens.h"
28 #include "tgsi/tgsi_dump.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/u_memory.h"
31 #include "util/u_math.h"
33 #include "svga_tgsi_emit.h"
34 #include "svga_context.h"
37 static boolean
emit_vs_postamble( struct svga_shader_emitter
*emit
);
38 static boolean
emit_ps_postamble( struct svga_shader_emitter
*emit
);
42 translate_opcode(uint opcode
)
45 case TGSI_OPCODE_ABS
: return SVGA3DOP_ABS
;
46 case TGSI_OPCODE_ADD
: return SVGA3DOP_ADD
;
47 case TGSI_OPCODE_DP2A
: return SVGA3DOP_DP2ADD
;
48 case TGSI_OPCODE_DP3
: return SVGA3DOP_DP3
;
49 case TGSI_OPCODE_DP4
: return SVGA3DOP_DP4
;
50 case TGSI_OPCODE_FRC
: return SVGA3DOP_FRC
;
51 case TGSI_OPCODE_MAD
: return SVGA3DOP_MAD
;
52 case TGSI_OPCODE_MAX
: return SVGA3DOP_MAX
;
53 case TGSI_OPCODE_MIN
: return SVGA3DOP_MIN
;
54 case TGSI_OPCODE_MOV
: return SVGA3DOP_MOV
;
55 case TGSI_OPCODE_MUL
: return SVGA3DOP_MUL
;
56 case TGSI_OPCODE_NOP
: return SVGA3DOP_NOP
;
57 case TGSI_OPCODE_NRM4
: return SVGA3DOP_NRM
;
59 assert(!"svga: unexpected opcode in translate_opcode()");
60 return SVGA3DOP_LAST_INST
;
66 translate_file(unsigned file
)
69 case TGSI_FILE_TEMPORARY
: return SVGA3DREG_TEMP
;
70 case TGSI_FILE_INPUT
: return SVGA3DREG_INPUT
;
71 case TGSI_FILE_OUTPUT
: return SVGA3DREG_OUTPUT
; /* VS3.0+ only */
72 case TGSI_FILE_IMMEDIATE
: return SVGA3DREG_CONST
;
73 case TGSI_FILE_CONSTANT
: return SVGA3DREG_CONST
;
74 case TGSI_FILE_SAMPLER
: return SVGA3DREG_SAMPLER
;
75 case TGSI_FILE_ADDRESS
: return SVGA3DREG_ADDR
;
77 assert(!"svga: unexpected register file in translate_file()");
78 return SVGA3DREG_TEMP
;
84 * Translate a TGSI destination register to an SVGA3DShaderDestToken.
85 * \param insn the TGSI instruction
86 * \param idx which TGSI dest register to translate (usually (always?) zero)
88 static SVGA3dShaderDestToken
89 translate_dst_register( struct svga_shader_emitter
*emit
,
90 const struct tgsi_full_instruction
*insn
,
93 const struct tgsi_full_dst_register
*reg
= &insn
->Dst
[idx
];
94 SVGA3dShaderDestToken dest
;
96 switch (reg
->Register
.File
) {
97 case TGSI_FILE_OUTPUT
:
98 /* Output registers encode semantic information in their name.
99 * Need to lookup a table built at decl time:
101 dest
= emit
->output_map
[reg
->Register
.Index
];
106 unsigned index
= reg
->Register
.Index
;
107 assert(index
< SVGA3D_TEMPREG_MAX
);
108 index
= MIN2(index
, SVGA3D_TEMPREG_MAX
- 1);
109 dest
= dst_register(translate_file(reg
->Register
.File
), index
);
114 if (reg
->Register
.Indirect
) {
115 debug_warning("Indirect indexing of dest registers is not supported!\n");
118 dest
.mask
= reg
->Register
.WriteMask
;
121 if (insn
->Instruction
.Saturate
)
122 dest
.dstMod
= SVGA3DDSTMOD_SATURATE
;
129 * Apply a swizzle to a src_register, returning a new src_register
130 * Ex: swizzle(SRC.ZZYY, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_X, SWIZZLE_Y)
131 * would return SRC.YYZZ
133 static struct src_register
134 swizzle(struct src_register src
,
135 unsigned x
, unsigned y
, unsigned z
, unsigned w
)
141 x
= (src
.base
.swizzle
>> (x
* 2)) & 0x3;
142 y
= (src
.base
.swizzle
>> (y
* 2)) & 0x3;
143 z
= (src
.base
.swizzle
>> (z
* 2)) & 0x3;
144 w
= (src
.base
.swizzle
>> (w
* 2)) & 0x3;
146 src
.base
.swizzle
= TRANSLATE_SWIZZLE(x
, y
, z
, w
);
153 * Apply a "scalar" swizzle to a src_register returning a new
154 * src_register where all the swizzle terms are the same.
155 * Ex: scalar(SRC.WZYX, SWIZZLE_Y) would return SRC.ZZZZ
157 static struct src_register
158 scalar(struct src_register src
, unsigned comp
)
161 return swizzle( src
, comp
, comp
, comp
, comp
);
166 svga_arl_needs_adjustment( const struct svga_shader_emitter
*emit
)
170 for (i
= 0; i
< emit
->num_arl_consts
; ++i
) {
171 if (emit
->arl_consts
[i
].arl_num
== emit
->current_arl
)
179 svga_arl_adjustment( const struct svga_shader_emitter
*emit
)
183 for (i
= 0; i
< emit
->num_arl_consts
; ++i
) {
184 if (emit
->arl_consts
[i
].arl_num
== emit
->current_arl
)
185 return emit
->arl_consts
[i
].number
;
192 * Translate a TGSI src register to a src_register.
194 static struct src_register
195 translate_src_register( const struct svga_shader_emitter
*emit
,
196 const struct tgsi_full_src_register
*reg
)
198 struct src_register src
;
200 switch (reg
->Register
.File
) {
201 case TGSI_FILE_INPUT
:
202 /* Input registers are referred to by their semantic name rather
203 * than by index. Use the mapping build up from the decls:
205 src
= emit
->input_map
[reg
->Register
.Index
];
208 case TGSI_FILE_IMMEDIATE
:
209 /* Immediates are appended after TGSI constants in the D3D
212 src
= src_register( translate_file( reg
->Register
.File
),
213 reg
->Register
.Index
+ emit
->imm_start
);
217 src
= src_register( translate_file( reg
->Register
.File
),
218 reg
->Register
.Index
);
222 /* Indirect addressing.
224 if (reg
->Register
.Indirect
) {
225 if (emit
->unit
== PIPE_SHADER_FRAGMENT
) {
226 /* Pixel shaders have only loop registers for relative
227 * addressing into inputs. Ignore the redundant address
228 * register, the contents of aL should be in sync with it.
230 if (reg
->Register
.File
== TGSI_FILE_INPUT
) {
231 src
.base
.relAddr
= 1;
232 src
.indirect
= src_token(SVGA3DREG_LOOP
, 0);
236 /* Constant buffers only.
238 if (reg
->Register
.File
== TGSI_FILE_CONSTANT
) {
239 /* we shift the offset towards the minimum */
240 if (svga_arl_needs_adjustment( emit
)) {
241 src
.base
.num
-= svga_arl_adjustment( emit
);
243 src
.base
.relAddr
= 1;
245 /* Not really sure what should go in the second token:
247 src
.indirect
= src_token( SVGA3DREG_ADDR
,
248 reg
->Indirect
.Index
);
250 src
.indirect
.swizzle
= SWIZZLE_XXXX
;
256 reg
->Register
.SwizzleX
,
257 reg
->Register
.SwizzleY
,
258 reg
->Register
.SwizzleZ
,
259 reg
->Register
.SwizzleW
);
261 /* src.mod isn't a bitfield, unfortunately:
262 * See tgsi_util_get_full_src_register_sign_mode for implementation details.
264 if (reg
->Register
.Absolute
) {
265 if (reg
->Register
.Negate
)
266 src
.base
.srcMod
= SVGA3DSRCMOD_ABSNEG
;
268 src
.base
.srcMod
= SVGA3DSRCMOD_ABS
;
271 if (reg
->Register
.Negate
)
272 src
.base
.srcMod
= SVGA3DSRCMOD_NEG
;
274 src
.base
.srcMod
= SVGA3DSRCMOD_NONE
;
282 * Get a temporary register.
283 * Note: if we exceed the temporary register limit we just use
284 * register SVGA3D_TEMPREG_MAX - 1.
286 static SVGA3dShaderDestToken
287 get_temp( struct svga_shader_emitter
*emit
)
289 int i
= emit
->nr_hw_temp
+ emit
->internal_temp_count
++;
290 if (i
>= SVGA3D_TEMPREG_MAX
) {
291 debug_warn_once("svga: Too many temporary registers used in shader\n");
292 i
= SVGA3D_TEMPREG_MAX
- 1;
294 return dst_register( SVGA3DREG_TEMP
, i
);
299 * Release a single temp. Currently only effective if it was the last
300 * allocated temp, otherwise release will be delayed until the next
301 * call to reset_temp_regs().
304 release_temp( struct svga_shader_emitter
*emit
,
305 SVGA3dShaderDestToken temp
)
307 if (temp
.num
== emit
->internal_temp_count
- 1)
308 emit
->internal_temp_count
--;
316 reset_temp_regs(struct svga_shader_emitter
*emit
)
318 emit
->internal_temp_count
= 0;
322 /** Emit bytecode for a src_register */
324 emit_src(struct svga_shader_emitter
*emit
, const struct src_register src
)
326 if (src
.base
.relAddr
) {
327 assert(src
.base
.reserved0
);
328 assert(src
.indirect
.reserved0
);
329 return (svga_shader_emit_dword( emit
, src
.base
.value
) &&
330 svga_shader_emit_dword( emit
, src
.indirect
.value
));
333 assert(src
.base
.reserved0
);
334 return svga_shader_emit_dword( emit
, src
.base
.value
);
339 /** Emit bytecode for a dst_register */
341 emit_dst(struct svga_shader_emitter
*emit
, SVGA3dShaderDestToken dest
)
343 assert(dest
.reserved0
);
345 return svga_shader_emit_dword( emit
, dest
.value
);
349 /** Emit bytecode for a 1-operand instruction */
351 emit_op1(struct svga_shader_emitter
*emit
,
352 SVGA3dShaderInstToken inst
,
353 SVGA3dShaderDestToken dest
,
354 struct src_register src0
)
356 return (emit_instruction(emit
, inst
) &&
357 emit_dst(emit
, dest
) &&
358 emit_src(emit
, src0
));
362 /** Emit bytecode for a 2-operand instruction */
364 emit_op2(struct svga_shader_emitter
*emit
,
365 SVGA3dShaderInstToken inst
,
366 SVGA3dShaderDestToken dest
,
367 struct src_register src0
,
368 struct src_register src1
)
370 return (emit_instruction(emit
, inst
) &&
371 emit_dst(emit
, dest
) &&
372 emit_src(emit
, src0
) &&
373 emit_src(emit
, src1
));
377 /** Emit bytecode for a 3-operand instruction */
379 emit_op3(struct svga_shader_emitter
*emit
,
380 SVGA3dShaderInstToken inst
,
381 SVGA3dShaderDestToken dest
,
382 struct src_register src0
,
383 struct src_register src1
,
384 struct src_register src2
)
386 return (emit_instruction(emit
, inst
) &&
387 emit_dst(emit
, dest
) &&
388 emit_src(emit
, src0
) &&
389 emit_src(emit
, src1
) &&
390 emit_src(emit
, src2
));
394 /** Emit bytecode for a 4-operand instruction */
396 emit_op4(struct svga_shader_emitter
*emit
,
397 SVGA3dShaderInstToken inst
,
398 SVGA3dShaderDestToken dest
,
399 struct src_register src0
,
400 struct src_register src1
,
401 struct src_register src2
,
402 struct src_register src3
)
404 return (emit_instruction(emit
, inst
) &&
405 emit_dst(emit
, dest
) &&
406 emit_src(emit
, src0
) &&
407 emit_src(emit
, src1
) &&
408 emit_src(emit
, src2
) &&
409 emit_src(emit
, src3
));
414 * Apply the absolute value modifier to the given src_register, returning
415 * a new src_register.
417 static struct src_register
418 absolute(struct src_register src
)
420 src
.base
.srcMod
= SVGA3DSRCMOD_ABS
;
426 * Apply the negation modifier to the given src_register, returning
427 * a new src_register.
429 static struct src_register
430 negate(struct src_register src
)
432 switch (src
.base
.srcMod
) {
433 case SVGA3DSRCMOD_ABS
:
434 src
.base
.srcMod
= SVGA3DSRCMOD_ABSNEG
;
436 case SVGA3DSRCMOD_ABSNEG
:
437 src
.base
.srcMod
= SVGA3DSRCMOD_ABS
;
439 case SVGA3DSRCMOD_NEG
:
440 src
.base
.srcMod
= SVGA3DSRCMOD_NONE
;
442 case SVGA3DSRCMOD_NONE
:
443 src
.base
.srcMod
= SVGA3DSRCMOD_NEG
;
451 /* Replace the src with the temporary specified in the dst, but copying
452 * only the necessary channels, and preserving the original swizzle (which is
453 * important given that several opcodes have constraints in the allowed
457 emit_repl(struct svga_shader_emitter
*emit
,
458 SVGA3dShaderDestToken dst
,
459 struct src_register
*src0
)
461 unsigned src0_swizzle
;
464 assert(SVGA3dShaderGetRegType(dst
.value
) == SVGA3DREG_TEMP
);
466 src0_swizzle
= src0
->base
.swizzle
;
469 for (chan
= 0; chan
< 4; ++chan
) {
470 unsigned swizzle
= (src0_swizzle
>> (chan
*2)) & 0x3;
471 dst
.mask
|= 1 << swizzle
;
475 src0
->base
.swizzle
= SVGA3DSWIZZLE_NONE
;
477 if (!emit_op1( emit
, inst_token( SVGA3DOP_MOV
), dst
, *src0
))
481 src0
->base
.swizzle
= src0_swizzle
;
488 * Submit/emit an instruction with zero operands.
491 submit_op0(struct svga_shader_emitter
*emit
,
492 SVGA3dShaderInstToken inst
,
493 SVGA3dShaderDestToken dest
)
495 return (emit_instruction( emit
, inst
) &&
496 emit_dst( emit
, dest
));
501 * Submit/emit an instruction with one operand.
504 submit_op1(struct svga_shader_emitter
*emit
,
505 SVGA3dShaderInstToken inst
,
506 SVGA3dShaderDestToken dest
,
507 struct src_register src0
)
509 return emit_op1( emit
, inst
, dest
, src0
);
514 * Submit/emit an instruction with two operands.
516 * SVGA shaders may not refer to >1 constant register in a single
517 * instruction. This function checks for that usage and inserts a
518 * move to temporary if detected.
520 * The same applies to input registers -- at most a single input
521 * register may be read by any instruction.
524 submit_op2(struct svga_shader_emitter
*emit
,
525 SVGA3dShaderInstToken inst
,
526 SVGA3dShaderDestToken dest
,
527 struct src_register src0
,
528 struct src_register src1
)
530 SVGA3dShaderDestToken temp
;
531 SVGA3dShaderRegType type0
, type1
;
532 boolean need_temp
= FALSE
;
535 type0
= SVGA3dShaderGetRegType( src0
.base
.value
);
536 type1
= SVGA3dShaderGetRegType( src1
.base
.value
);
538 if (type0
== SVGA3DREG_CONST
&&
539 type1
== SVGA3DREG_CONST
&&
540 src0
.base
.num
!= src1
.base
.num
)
543 if (type0
== SVGA3DREG_INPUT
&&
544 type1
== SVGA3DREG_INPUT
&&
545 src0
.base
.num
!= src1
.base
.num
)
549 temp
= get_temp( emit
);
551 if (!emit_repl( emit
, temp
, &src0
))
555 if (!emit_op2( emit
, inst
, dest
, src0
, src1
))
559 release_temp( emit
, temp
);
566 * Submit/emit an instruction with three operands.
568 * SVGA shaders may not refer to >1 constant register in a single
569 * instruction. This function checks for that usage and inserts a
570 * move to temporary if detected.
573 submit_op3(struct svga_shader_emitter
*emit
,
574 SVGA3dShaderInstToken inst
,
575 SVGA3dShaderDestToken dest
,
576 struct src_register src0
,
577 struct src_register src1
,
578 struct src_register src2
)
580 SVGA3dShaderDestToken temp0
;
581 SVGA3dShaderDestToken temp1
;
582 boolean need_temp0
= FALSE
;
583 boolean need_temp1
= FALSE
;
584 SVGA3dShaderRegType type0
, type1
, type2
;
588 type0
= SVGA3dShaderGetRegType( src0
.base
.value
);
589 type1
= SVGA3dShaderGetRegType( src1
.base
.value
);
590 type2
= SVGA3dShaderGetRegType( src2
.base
.value
);
592 if (inst
.op
!= SVGA3DOP_SINCOS
) {
593 if (type0
== SVGA3DREG_CONST
&&
594 ((type1
== SVGA3DREG_CONST
&& src0
.base
.num
!= src1
.base
.num
) ||
595 (type2
== SVGA3DREG_CONST
&& src0
.base
.num
!= src2
.base
.num
)))
598 if (type1
== SVGA3DREG_CONST
&&
599 (type2
== SVGA3DREG_CONST
&& src1
.base
.num
!= src2
.base
.num
))
603 if (type0
== SVGA3DREG_INPUT
&&
604 ((type1
== SVGA3DREG_INPUT
&& src0
.base
.num
!= src1
.base
.num
) ||
605 (type2
== SVGA3DREG_INPUT
&& src0
.base
.num
!= src2
.base
.num
)))
608 if (type1
== SVGA3DREG_INPUT
&&
609 (type2
== SVGA3DREG_INPUT
&& src1
.base
.num
!= src2
.base
.num
))
613 temp0
= get_temp( emit
);
615 if (!emit_repl( emit
, temp0
, &src0
))
620 temp1
= get_temp( emit
);
622 if (!emit_repl( emit
, temp1
, &src1
))
626 if (!emit_op3( emit
, inst
, dest
, src0
, src1
, src2
))
630 release_temp( emit
, temp1
);
632 release_temp( emit
, temp0
);
638 * Submit/emit an instruction with four operands.
640 * SVGA shaders may not refer to >1 constant register in a single
641 * instruction. This function checks for that usage and inserts a
642 * move to temporary if detected.
645 submit_op4(struct svga_shader_emitter
*emit
,
646 SVGA3dShaderInstToken inst
,
647 SVGA3dShaderDestToken dest
,
648 struct src_register src0
,
649 struct src_register src1
,
650 struct src_register src2
,
651 struct src_register src3
)
653 SVGA3dShaderDestToken temp0
;
654 SVGA3dShaderDestToken temp3
;
655 boolean need_temp0
= FALSE
;
656 boolean need_temp3
= FALSE
;
657 SVGA3dShaderRegType type0
, type1
, type2
, type3
;
661 type0
= SVGA3dShaderGetRegType( src0
.base
.value
);
662 type1
= SVGA3dShaderGetRegType( src1
.base
.value
);
663 type2
= SVGA3dShaderGetRegType( src2
.base
.value
);
664 type3
= SVGA3dShaderGetRegType( src2
.base
.value
);
666 /* Make life a little easier - this is only used by the TXD
667 * instruction which is guaranteed not to have a constant/input reg
668 * in one slot at least:
670 assert(type1
== SVGA3DREG_SAMPLER
);
672 if (type0
== SVGA3DREG_CONST
&&
673 ((type3
== SVGA3DREG_CONST
&& src0
.base
.num
!= src3
.base
.num
) ||
674 (type2
== SVGA3DREG_CONST
&& src0
.base
.num
!= src2
.base
.num
)))
677 if (type3
== SVGA3DREG_CONST
&&
678 (type2
== SVGA3DREG_CONST
&& src3
.base
.num
!= src2
.base
.num
))
681 if (type0
== SVGA3DREG_INPUT
&&
682 ((type3
== SVGA3DREG_INPUT
&& src0
.base
.num
!= src3
.base
.num
) ||
683 (type2
== SVGA3DREG_INPUT
&& src0
.base
.num
!= src2
.base
.num
)))
686 if (type3
== SVGA3DREG_INPUT
&&
687 (type2
== SVGA3DREG_INPUT
&& src3
.base
.num
!= src2
.base
.num
))
691 temp0
= get_temp( emit
);
693 if (!emit_repl( emit
, temp0
, &src0
))
698 temp3
= get_temp( emit
);
700 if (!emit_repl( emit
, temp3
, &src3
))
704 if (!emit_op4( emit
, inst
, dest
, src0
, src1
, src2
, src3
))
708 release_temp( emit
, temp3
);
710 release_temp( emit
, temp0
);
716 * Do the src and dest registers refer to the same register?
719 alias_src_dst(struct src_register src
,
720 SVGA3dShaderDestToken dst
)
722 if (src
.base
.num
!= dst
.num
)
725 if (SVGA3dShaderGetRegType(dst
.value
) !=
726 SVGA3dShaderGetRegType(src
.base
.value
))
734 * Helper for emitting SVGA immediate values using the SVGA3DOP_DEF[I]
738 emit_def_const(struct svga_shader_emitter
*emit
,
739 SVGA3dShaderConstType type
,
740 unsigned idx
, float a
, float b
, float c
, float d
)
743 SVGA3dShaderInstToken opcode
;
746 case SVGA3D_CONST_TYPE_FLOAT
:
747 opcode
= inst_token( SVGA3DOP_DEF
);
748 def
.dst
= dst_register( SVGA3DREG_CONST
, idx
);
749 def
.constValues
[0] = a
;
750 def
.constValues
[1] = b
;
751 def
.constValues
[2] = c
;
752 def
.constValues
[3] = d
;
754 case SVGA3D_CONST_TYPE_INT
:
755 opcode
= inst_token( SVGA3DOP_DEFI
);
756 def
.dst
= dst_register( SVGA3DREG_CONSTINT
, idx
);
757 def
.constIValues
[0] = (int)a
;
758 def
.constIValues
[1] = (int)b
;
759 def
.constIValues
[2] = (int)c
;
760 def
.constIValues
[3] = (int)d
;
764 opcode
= inst_token( SVGA3DOP_NOP
);
768 if (!emit_instruction(emit
, opcode
) ||
769 !svga_shader_emit_dwords( emit
, def
.values
, Elements(def
.values
)))
777 create_loop_const( struct svga_shader_emitter
*emit
)
779 unsigned idx
= emit
->nr_hw_int_const
++;
781 if (!emit_def_const( emit
, SVGA3D_CONST_TYPE_INT
, idx
,
782 255, /* iteration count */
783 0, /* initial value */
785 0 /* not used, must be 0 */))
788 emit
->loop_const_idx
= idx
;
789 emit
->created_loop_const
= TRUE
;
795 create_arl_consts( struct svga_shader_emitter
*emit
)
799 for (i
= 0; i
< emit
->num_arl_consts
; i
+= 4) {
801 unsigned idx
= emit
->nr_hw_float_const
++;
803 for (j
= 0; j
< 4 && (j
+ i
) < emit
->num_arl_consts
; ++j
) {
804 vals
[j
] = (float) emit
->arl_consts
[i
+ j
].number
;
805 emit
->arl_consts
[i
+ j
].idx
= idx
;
808 emit
->arl_consts
[i
+ 0].swizzle
= TGSI_SWIZZLE_X
;
811 emit
->arl_consts
[i
+ 0].swizzle
= TGSI_SWIZZLE_Y
;
814 emit
->arl_consts
[i
+ 0].swizzle
= TGSI_SWIZZLE_Z
;
817 emit
->arl_consts
[i
+ 0].swizzle
= TGSI_SWIZZLE_W
;
824 if (!emit_def_const( emit
, SVGA3D_CONST_TYPE_FLOAT
, idx
,
835 * Return the register which holds the pixel shaders front/back-
838 static struct src_register
839 get_vface( struct svga_shader_emitter
*emit
)
841 assert(emit
->emitted_vface
);
842 return src_register(SVGA3DREG_MISCTYPE
, SVGA3DMISCREG_FACE
);
847 * Create/emit a "common" constant with values {0, 0.5, -1, 1}.
848 * We can swizzle this to produce other useful constants such as
849 * {0, 0, 0, 0}, {1, 1, 1, 1}, etc.
852 create_common_immediate( struct svga_shader_emitter
*emit
)
854 unsigned idx
= emit
->nr_hw_float_const
++;
856 /* Emit the constant (0, 0.5, -1, 1) and use swizzling to generate
857 * other useful vectors.
859 if (!emit_def_const( emit
, SVGA3D_CONST_TYPE_FLOAT
,
860 idx
, 0.0f
, 0.5f
, -1.0f
, 1.0f
))
863 emit
->common_immediate_idx
= idx
;
864 emit
->created_common_immediate
= TRUE
;
871 * Return swizzle/position for the given value in the "common" immediate.
873 static inline unsigned
874 common_immediate_swizzle(float value
)
877 return TGSI_SWIZZLE_X
;
878 else if (value
== 0.5f
)
879 return TGSI_SWIZZLE_Y
;
880 else if (value
== -1.0f
)
881 return TGSI_SWIZZLE_Z
;
882 else if (value
== 1.0f
)
883 return TGSI_SWIZZLE_W
;
885 assert(!"illegal value in common_immediate_swizzle");
886 return TGSI_SWIZZLE_X
;
892 * Returns an immediate reg where all the terms are either 0, 1, -1 or 0.5
894 static struct src_register
895 get_immediate(struct svga_shader_emitter
*emit
,
896 float x
, float y
, float z
, float w
)
898 unsigned sx
= common_immediate_swizzle(x
);
899 unsigned sy
= common_immediate_swizzle(y
);
900 unsigned sz
= common_immediate_swizzle(z
);
901 unsigned sw
= common_immediate_swizzle(w
);
902 assert(emit
->created_common_immediate
);
903 assert(emit
->common_immediate_idx
>= 0);
904 return swizzle(src_register(SVGA3DREG_CONST
, emit
->common_immediate_idx
),
910 * returns {0, 0, 0, 0} immediate
912 static struct src_register
913 get_zero_immediate( struct svga_shader_emitter
*emit
)
915 assert(emit
->created_common_immediate
);
916 assert(emit
->common_immediate_idx
>= 0);
917 return swizzle(src_register( SVGA3DREG_CONST
,
918 emit
->common_immediate_idx
),
924 * returns {1, 1, 1, 1} immediate
926 static struct src_register
927 get_one_immediate( struct svga_shader_emitter
*emit
)
929 assert(emit
->created_common_immediate
);
930 assert(emit
->common_immediate_idx
>= 0);
931 return swizzle(src_register( SVGA3DREG_CONST
,
932 emit
->common_immediate_idx
),
938 * returns {0.5, 0.5, 0.5, 0.5} immediate
940 static struct src_register
941 get_half_immediate( struct svga_shader_emitter
*emit
)
943 assert(emit
->created_common_immediate
);
944 assert(emit
->common_immediate_idx
>= 0);
945 return swizzle(src_register(SVGA3DREG_CONST
, emit
->common_immediate_idx
),
951 * returns the loop const
953 static struct src_register
954 get_loop_const( struct svga_shader_emitter
*emit
)
956 assert(emit
->created_loop_const
);
957 assert(emit
->loop_const_idx
>= 0);
958 return src_register( SVGA3DREG_CONSTINT
,
959 emit
->loop_const_idx
);
963 static struct src_register
964 get_fake_arl_const( struct svga_shader_emitter
*emit
)
966 struct src_register reg
;
967 int idx
= 0, swizzle
= 0, i
;
969 for (i
= 0; i
< emit
->num_arl_consts
; ++ i
) {
970 if (emit
->arl_consts
[i
].arl_num
== emit
->current_arl
) {
971 idx
= emit
->arl_consts
[i
].idx
;
972 swizzle
= emit
->arl_consts
[i
].swizzle
;
976 reg
= src_register( SVGA3DREG_CONST
, idx
);
977 return scalar(reg
, swizzle
);
982 * Return a register which holds the width and height of the texture
983 * currently bound to the given sampler.
985 static struct src_register
986 get_tex_dimensions( struct svga_shader_emitter
*emit
, int sampler_num
)
989 struct src_register reg
;
991 /* the width/height indexes start right after constants */
992 idx
= emit
->key
.fkey
.tex
[sampler_num
].width_height_idx
+
993 emit
->info
.file_max
[TGSI_FILE_CONSTANT
] + 1;
995 reg
= src_register( SVGA3DREG_CONST
, idx
);
1001 emit_fake_arl(struct svga_shader_emitter
*emit
,
1002 const struct tgsi_full_instruction
*insn
)
1004 const struct src_register src0
=
1005 translate_src_register(emit
, &insn
->Src
[0] );
1006 struct src_register src1
= get_fake_arl_const( emit
);
1007 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1008 SVGA3dShaderDestToken tmp
= get_temp( emit
);
1010 if (!submit_op1(emit
, inst_token( SVGA3DOP_MOV
), tmp
, src0
))
1013 if (!submit_op2( emit
, inst_token( SVGA3DOP_ADD
), tmp
, src( tmp
),
1017 /* replicate the original swizzle */
1019 src1
.base
.swizzle
= src0
.base
.swizzle
;
1021 return submit_op1( emit
, inst_token( SVGA3DOP_MOVA
),
1027 emit_if(struct svga_shader_emitter
*emit
,
1028 const struct tgsi_full_instruction
*insn
)
1030 struct src_register src0
=
1031 translate_src_register(emit
, &insn
->Src
[0]);
1032 struct src_register zero
= get_zero_immediate(emit
);
1033 SVGA3dShaderInstToken if_token
= inst_token( SVGA3DOP_IFC
);
1035 if_token
.control
= SVGA3DOPCOMPC_NE
;
1037 if (SVGA3dShaderGetRegType(src0
.base
.value
) == SVGA3DREG_CONST
) {
1039 * Max different constant registers readable per IFC instruction is 1.
1041 SVGA3dShaderDestToken tmp
= get_temp( emit
);
1043 if (!submit_op1(emit
, inst_token( SVGA3DOP_MOV
), tmp
, src0
))
1046 src0
= scalar(src( tmp
), TGSI_SWIZZLE_X
);
1049 emit
->dynamic_branching_level
++;
1051 return (emit_instruction( emit
, if_token
) &&
1052 emit_src( emit
, src0
) &&
1053 emit_src( emit
, zero
) );
1058 emit_else(struct svga_shader_emitter
*emit
,
1059 const struct tgsi_full_instruction
*insn
)
1061 return emit_instruction(emit
, inst_token(SVGA3DOP_ELSE
));
1066 emit_endif(struct svga_shader_emitter
*emit
,
1067 const struct tgsi_full_instruction
*insn
)
1069 emit
->dynamic_branching_level
--;
1071 return emit_instruction(emit
, inst_token(SVGA3DOP_ENDIF
));
1076 * Translate the following TGSI FLR instruction.
1078 * To the following SVGA3D instruction sequence.
1083 emit_floor(struct svga_shader_emitter
*emit
,
1084 const struct tgsi_full_instruction
*insn
)
1086 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1087 const struct src_register src0
=
1088 translate_src_register(emit
, &insn
->Src
[0] );
1089 SVGA3dShaderDestToken temp
= get_temp( emit
);
1092 if (!submit_op1( emit
, inst_token( SVGA3DOP_FRC
), temp
, src0
))
1095 /* SUB DST, SRC, TMP */
1096 if (!submit_op2( emit
, inst_token( SVGA3DOP_ADD
), dst
, src0
,
1097 negate( src( temp
) ) ))
1105 * Translate the following TGSI CEIL instruction.
1107 * To the following SVGA3D instruction sequence.
1112 emit_ceil(struct svga_shader_emitter
*emit
,
1113 const struct tgsi_full_instruction
*insn
)
1115 SVGA3dShaderDestToken dst
= translate_dst_register(emit
, insn
, 0);
1116 const struct src_register src0
=
1117 translate_src_register(emit
, &insn
->Src
[0]);
1118 SVGA3dShaderDestToken temp
= get_temp(emit
);
1121 if (!submit_op1(emit
, inst_token(SVGA3DOP_FRC
), temp
, negate(src0
)))
1124 /* ADD DST, SRC, TMP */
1125 if (!submit_op2(emit
, inst_token(SVGA3DOP_ADD
), dst
, src0
, src(temp
)))
1133 * Translate the following TGSI DIV instruction.
1134 * DIV DST.xy, SRC0, SRC1
1135 * To the following SVGA3D instruction sequence.
1136 * RCP TMP.x, SRC1.xxxx
1137 * RCP TMP.y, SRC1.yyyy
1138 * MUL DST.xy, SRC0, TMP
1141 emit_div(struct svga_shader_emitter
*emit
,
1142 const struct tgsi_full_instruction
*insn
)
1144 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1145 const struct src_register src0
=
1146 translate_src_register(emit
, &insn
->Src
[0] );
1147 const struct src_register src1
=
1148 translate_src_register(emit
, &insn
->Src
[1] );
1149 SVGA3dShaderDestToken temp
= get_temp( emit
);
1152 /* For each enabled element, perform a RCP instruction. Note that
1153 * RCP is scalar in SVGA3D:
1155 for (i
= 0; i
< 4; i
++) {
1156 unsigned channel
= 1 << i
;
1157 if (dst
.mask
& channel
) {
1158 /* RCP TMP.?, SRC1.???? */
1159 if (!submit_op1( emit
, inst_token( SVGA3DOP_RCP
),
1160 writemask(temp
, channel
),
1167 * MUL DST, SRC0, TMP
1169 if (!submit_op2( emit
, inst_token( SVGA3DOP_MUL
), dst
, src0
,
1178 * Translate the following TGSI DP2 instruction.
1179 * DP2 DST, SRC1, SRC2
1180 * To the following SVGA3D instruction sequence.
1181 * MUL TMP, SRC1, SRC2
1182 * ADD DST, TMP.xxxx, TMP.yyyy
1185 emit_dp2(struct svga_shader_emitter
*emit
,
1186 const struct tgsi_full_instruction
*insn
)
1188 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1189 const struct src_register src0
=
1190 translate_src_register(emit
, &insn
->Src
[0]);
1191 const struct src_register src1
=
1192 translate_src_register(emit
, &insn
->Src
[1]);
1193 SVGA3dShaderDestToken temp
= get_temp( emit
);
1194 struct src_register temp_src0
, temp_src1
;
1196 /* MUL TMP, SRC1, SRC2 */
1197 if (!submit_op2( emit
, inst_token( SVGA3DOP_MUL
), temp
, src0
, src1
))
1200 temp_src0
= scalar(src( temp
), TGSI_SWIZZLE_X
);
1201 temp_src1
= scalar(src( temp
), TGSI_SWIZZLE_Y
);
1203 /* ADD DST, TMP.xxxx, TMP.yyyy */
1204 if (!submit_op2( emit
, inst_token( SVGA3DOP_ADD
), dst
,
1205 temp_src0
, temp_src1
))
1213 * Translate the following TGSI DPH instruction.
1214 * DPH DST, SRC1, SRC2
1215 * To the following SVGA3D instruction sequence.
1216 * DP3 TMP, SRC1, SRC2
1217 * ADD DST, TMP, SRC2.wwww
1220 emit_dph(struct svga_shader_emitter
*emit
,
1221 const struct tgsi_full_instruction
*insn
)
1223 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1224 const struct src_register src0
= translate_src_register(
1225 emit
, &insn
->Src
[0] );
1226 struct src_register src1
=
1227 translate_src_register(emit
, &insn
->Src
[1]);
1228 SVGA3dShaderDestToken temp
= get_temp( emit
);
1230 /* DP3 TMP, SRC1, SRC2 */
1231 if (!submit_op2( emit
, inst_token( SVGA3DOP_DP3
), temp
, src0
, src1
))
1234 src1
= scalar(src1
, TGSI_SWIZZLE_W
);
1236 /* ADD DST, TMP, SRC2.wwww */
1237 if (!submit_op2( emit
, inst_token( SVGA3DOP_ADD
), dst
,
1238 src( temp
), src1
))
1246 * Translate the following TGSI DST instruction.
1248 * To the following SVGA3D instruction sequence.
1254 emit_nrm(struct svga_shader_emitter
*emit
,
1255 const struct tgsi_full_instruction
*insn
)
1257 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1258 const struct src_register src0
=
1259 translate_src_register(emit
, &insn
->Src
[0]);
1260 SVGA3dShaderDestToken temp
= get_temp( emit
);
1262 /* DP3 TMP, SRC, SRC */
1263 if (!submit_op2( emit
, inst_token( SVGA3DOP_DP3
), temp
, src0
, src0
))
1267 if (!submit_op1( emit
, inst_token( SVGA3DOP_RSQ
), temp
, src( temp
)))
1270 /* MUL DST, SRC, TMP */
1271 if (!submit_op2( emit
, inst_token( SVGA3DOP_MUL
), dst
,
1280 * Sine / Cosine helper function.
1283 do_emit_sincos(struct svga_shader_emitter
*emit
,
1284 SVGA3dShaderDestToken dst
,
1285 struct src_register src0
)
1287 src0
= scalar(src0
, TGSI_SWIZZLE_X
);
1288 return submit_op1(emit
, inst_token(SVGA3DOP_SINCOS
), dst
, src0
);
1293 * Translate/emit a TGSI SIN, COS or CSC instruction.
1296 emit_sincos(struct svga_shader_emitter
*emit
,
1297 const struct tgsi_full_instruction
*insn
)
1299 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1300 struct src_register src0
= translate_src_register(emit
, &insn
->Src
[0]);
1301 SVGA3dShaderDestToken temp
= get_temp( emit
);
1304 if (!do_emit_sincos(emit
, writemask(temp
, TGSI_WRITEMASK_XY
), src0
))
1308 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), dst
, src( temp
) ))
1316 * Translate TGSI SIN instruction into:
1321 emit_sin(struct svga_shader_emitter
*emit
,
1322 const struct tgsi_full_instruction
*insn
)
1324 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1325 struct src_register src0
=
1326 translate_src_register(emit
, &insn
->Src
[0] );
1327 SVGA3dShaderDestToken temp
= get_temp( emit
);
1330 if (!do_emit_sincos(emit
, writemask(temp
, TGSI_WRITEMASK_Y
), src0
))
1333 src0
= scalar(src( temp
), TGSI_SWIZZLE_Y
);
1335 /* MOV DST TMP.yyyy */
1336 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), dst
, src0
))
1344 * Translate TGSI COS instruction into:
1349 emit_cos(struct svga_shader_emitter
*emit
,
1350 const struct tgsi_full_instruction
*insn
)
1352 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1353 struct src_register src0
=
1354 translate_src_register(emit
, &insn
->Src
[0] );
1355 SVGA3dShaderDestToken temp
= get_temp( emit
);
1358 if (!do_emit_sincos( emit
, writemask(temp
, TGSI_WRITEMASK_X
), src0
))
1361 src0
= scalar(src( temp
), TGSI_SWIZZLE_X
);
1363 /* MOV DST TMP.xxxx */
1364 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), dst
, src0
))
1372 * Translate/emit TGSI SSG (Set Sign: -1, 0, +1) instruction.
1375 emit_ssg(struct svga_shader_emitter
*emit
,
1376 const struct tgsi_full_instruction
*insn
)
1378 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1379 struct src_register src0
=
1380 translate_src_register(emit
, &insn
->Src
[0] );
1381 SVGA3dShaderDestToken temp0
= get_temp( emit
);
1382 SVGA3dShaderDestToken temp1
= get_temp( emit
);
1383 struct src_register zero
, one
;
1385 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
1386 /* SGN DST, SRC0, TMP0, TMP1 */
1387 return submit_op3( emit
, inst_token( SVGA3DOP_SGN
), dst
, src0
,
1388 src( temp0
), src( temp1
) );
1391 one
= get_one_immediate(emit
);
1392 zero
= get_zero_immediate(emit
);
1394 /* CMP TMP0, SRC0, one, zero */
1395 if (!submit_op3( emit
, inst_token( SVGA3DOP_CMP
),
1396 writemask( temp0
, dst
.mask
), src0
, one
, zero
))
1399 /* CMP TMP1, negate(SRC0), negate(one), zero */
1400 if (!submit_op3( emit
, inst_token( SVGA3DOP_CMP
),
1401 writemask( temp1
, dst
.mask
), negate( src0
), negate( one
),
1405 /* ADD DST, TMP0, TMP1 */
1406 return submit_op2( emit
, inst_token( SVGA3DOP_ADD
), dst
, src( temp0
),
1412 * Translate/emit TGSI SUB instruction as:
1413 * ADD DST, SRC0, negate(SRC1)
1416 emit_sub(struct svga_shader_emitter
*emit
,
1417 const struct tgsi_full_instruction
*insn
)
1419 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1420 struct src_register src0
= translate_src_register(
1421 emit
, &insn
->Src
[0] );
1422 struct src_register src1
= translate_src_register(
1423 emit
, &insn
->Src
[1] );
1425 src1
= negate(src1
);
1427 if (!submit_op2( emit
, inst_token( SVGA3DOP_ADD
), dst
,
1436 * Translate/emit KILL_IF instruction (kill if any of X,Y,Z,W are negative).
1439 emit_kill_if(struct svga_shader_emitter
*emit
,
1440 const struct tgsi_full_instruction
*insn
)
1442 const struct tgsi_full_src_register
*reg
= &insn
->Src
[0];
1443 struct src_register src0
, srcIn
;
1444 const boolean special
= (reg
->Register
.Absolute
||
1445 reg
->Register
.Negate
||
1446 reg
->Register
.Indirect
||
1447 reg
->Register
.SwizzleX
!= 0 ||
1448 reg
->Register
.SwizzleY
!= 1 ||
1449 reg
->Register
.SwizzleZ
!= 2 ||
1450 reg
->Register
.File
!= TGSI_FILE_TEMPORARY
);
1451 SVGA3dShaderDestToken temp
;
1453 src0
= srcIn
= translate_src_register( emit
, reg
);
1456 /* need a temp reg */
1457 temp
= get_temp( emit
);
1461 /* move the source into a temp register */
1462 submit_op1(emit
, inst_token(SVGA3DOP_MOV
), temp
, src0
);
1467 /* Do the texkill by checking if any of the XYZW components are < 0.
1468 * Note that ps_2_0 and later take XYZW in consideration, while ps_1_x
1469 * only used XYZ. The MSDN documentation about this is incorrect.
1471 if (!submit_op0( emit
, inst_token( SVGA3DOP_TEXKILL
), dst(src0
) ))
1479 * Translate/emit unconditional kill instruction (usually found inside
1480 * an IF/ELSE/ENDIF block).
1483 emit_kill(struct svga_shader_emitter
*emit
,
1484 const struct tgsi_full_instruction
*insn
)
1486 SVGA3dShaderDestToken temp
;
1487 struct src_register one
= get_one_immediate(emit
);
1488 SVGA3dShaderInstToken inst
= inst_token( SVGA3DOP_TEXKILL
);
1490 /* texkill doesn't allow negation on the operand so lets move
1491 * negation of {1} to a temp register */
1492 temp
= get_temp( emit
);
1493 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), temp
,
1497 return submit_op0( emit
, inst
, temp
);
1502 * Test if r1 and r2 are the same register.
1505 same_register(struct src_register r1
, struct src_register r2
)
1507 return (r1
.base
.num
== r2
.base
.num
&&
1508 r1
.base
.type_upper
== r2
.base
.type_upper
&&
1509 r1
.base
.type_lower
== r2
.base
.type_lower
);
1515 * Implement conditionals by initializing destination reg to 'fail',
1516 * then set predicate reg with UFOP_SETP, then move 'pass' to dest
1517 * based on predicate reg.
1519 * SETP src0, cmp, src1 -- do this first to avoid aliasing problems.
1524 emit_conditional(struct svga_shader_emitter
*emit
,
1525 unsigned compare_func
,
1526 SVGA3dShaderDestToken dst
,
1527 struct src_register src0
,
1528 struct src_register src1
,
1529 struct src_register pass
,
1530 struct src_register fail
)
1532 SVGA3dShaderDestToken pred_reg
= dst_register( SVGA3DREG_PREDICATE
, 0 );
1533 SVGA3dShaderInstToken setp_token
, mov_token
;
1534 setp_token
= inst_token( SVGA3DOP_SETP
);
1536 switch (compare_func
) {
1537 case PIPE_FUNC_NEVER
:
1538 return submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
1541 case PIPE_FUNC_LESS
:
1542 setp_token
.control
= SVGA3DOPCOMP_LT
;
1544 case PIPE_FUNC_EQUAL
:
1545 setp_token
.control
= SVGA3DOPCOMP_EQ
;
1547 case PIPE_FUNC_LEQUAL
:
1548 setp_token
.control
= SVGA3DOPCOMP_LE
;
1550 case PIPE_FUNC_GREATER
:
1551 setp_token
.control
= SVGA3DOPCOMP_GT
;
1553 case PIPE_FUNC_NOTEQUAL
:
1554 setp_token
.control
= SVGA3DOPCOMPC_NE
;
1556 case PIPE_FUNC_GEQUAL
:
1557 setp_token
.control
= SVGA3DOPCOMP_GE
;
1559 case PIPE_FUNC_ALWAYS
:
1560 return submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
1565 if (same_register(src(dst
), pass
)) {
1566 /* We'll get bad results if the dst and pass registers are the same
1567 * so use a temp register containing pass.
1569 SVGA3dShaderDestToken temp
= get_temp(emit
);
1570 if (!submit_op1(emit
, inst_token(SVGA3DOP_MOV
), temp
, pass
))
1575 /* SETP src0, COMPOP, src1 */
1576 if (!submit_op2( emit
, setp_token
, pred_reg
,
1580 mov_token
= inst_token( SVGA3DOP_MOV
);
1583 if (!submit_op1( emit
, mov_token
, dst
,
1587 /* MOV dst, pass (predicated)
1589 * Note that the predicate reg (and possible modifiers) is passed
1590 * as the first source argument.
1592 mov_token
.predicated
= 1;
1593 if (!submit_op2( emit
, mov_token
, dst
,
1594 src( pred_reg
), pass
))
1602 * Helper for emiting 'selection' commands. Basically:
1609 emit_select(struct svga_shader_emitter
*emit
,
1610 unsigned compare_func
,
1611 SVGA3dShaderDestToken dst
,
1612 struct src_register src0
,
1613 struct src_register src1
)
1615 /* There are some SVGA instructions which implement some selects
1616 * directly, but they are only available in the vertex shader.
1618 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
1619 switch (compare_func
) {
1620 case PIPE_FUNC_GEQUAL
:
1621 return submit_op2( emit
, inst_token( SVGA3DOP_SGE
), dst
, src0
, src1
);
1622 case PIPE_FUNC_LEQUAL
:
1623 return submit_op2( emit
, inst_token( SVGA3DOP_SGE
), dst
, src1
, src0
);
1624 case PIPE_FUNC_GREATER
:
1625 return submit_op2( emit
, inst_token( SVGA3DOP_SLT
), dst
, src1
, src0
);
1626 case PIPE_FUNC_LESS
:
1627 return submit_op2( emit
, inst_token( SVGA3DOP_SLT
), dst
, src0
, src1
);
1633 /* Otherwise, need to use the setp approach:
1636 struct src_register one
, zero
;
1637 /* zero immediate is 0,0,0,1 */
1638 zero
= get_zero_immediate(emit
);
1639 one
= get_one_immediate(emit
);
1641 return emit_conditional(emit
, compare_func
, dst
, src0
, src1
, one
, zero
);
1647 * Translate/emit a TGSI SEQ, SNE, SLT, SGE, etc. instruction.
1650 emit_select_op(struct svga_shader_emitter
*emit
,
1652 const struct tgsi_full_instruction
*insn
)
1654 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1655 struct src_register src0
= translate_src_register(
1656 emit
, &insn
->Src
[0] );
1657 struct src_register src1
= translate_src_register(
1658 emit
, &insn
->Src
[1] );
1660 return emit_select( emit
, compare
, dst
, src0
, src1
);
1665 * Translate TGSI CMP instruction. Component-wise:
1666 * dst = (src0 < 0.0) ? src1 : src2
1669 emit_cmp(struct svga_shader_emitter
*emit
,
1670 const struct tgsi_full_instruction
*insn
)
1672 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1673 const struct src_register src0
=
1674 translate_src_register(emit
, &insn
->Src
[0] );
1675 const struct src_register src1
=
1676 translate_src_register(emit
, &insn
->Src
[1] );
1677 const struct src_register src2
=
1678 translate_src_register(emit
, &insn
->Src
[2] );
1680 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
1681 struct src_register zero
= get_zero_immediate(emit
);
1682 /* We used to simulate CMP with SLT+LRP. But that didn't work when
1683 * src1 or src2 was Inf/NaN. In particular, GLSL sqrt(0) failed
1684 * because it involves a CMP to handle the 0 case.
1685 * Use a conditional expression instead.
1687 return emit_conditional(emit
, PIPE_FUNC_LESS
, dst
,
1688 src0
, zero
, src1
, src2
);
1691 assert(emit
->unit
== PIPE_SHADER_FRAGMENT
);
1693 /* CMP DST, SRC0, SRC2, SRC1 */
1694 return submit_op3( emit
, inst_token( SVGA3DOP_CMP
), dst
,
1701 * Translate/emit 2-operand (coord, sampler) texture instructions.
1704 emit_tex2(struct svga_shader_emitter
*emit
,
1705 const struct tgsi_full_instruction
*insn
,
1706 SVGA3dShaderDestToken dst
)
1708 SVGA3dShaderInstToken inst
;
1709 struct src_register texcoord
;
1710 struct src_register sampler
;
1711 SVGA3dShaderDestToken tmp
;
1715 switch (insn
->Instruction
.Opcode
) {
1716 case TGSI_OPCODE_TEX
:
1717 inst
.op
= SVGA3DOP_TEX
;
1719 case TGSI_OPCODE_TXP
:
1720 inst
.op
= SVGA3DOP_TEX
;
1721 inst
.control
= SVGA3DOPCONT_PROJECT
;
1723 case TGSI_OPCODE_TXB
:
1724 inst
.op
= SVGA3DOP_TEX
;
1725 inst
.control
= SVGA3DOPCONT_BIAS
;
1727 case TGSI_OPCODE_TXL
:
1728 inst
.op
= SVGA3DOP_TEXLDL
;
1735 texcoord
= translate_src_register( emit
, &insn
->Src
[0] );
1736 sampler
= translate_src_register( emit
, &insn
->Src
[1] );
1738 if (emit
->key
.fkey
.tex
[sampler
.base
.num
].unnormalized
||
1739 emit
->dynamic_branching_level
> 0)
1740 tmp
= get_temp( emit
);
1742 /* Can't do mipmapping inside dynamic branch constructs. Force LOD
1743 * zero in that case.
1745 if (emit
->dynamic_branching_level
> 0 &&
1746 inst
.op
== SVGA3DOP_TEX
&&
1747 SVGA3dShaderGetRegType(texcoord
.base
.value
) == SVGA3DREG_TEMP
) {
1748 struct src_register zero
= get_zero_immediate(emit
);
1750 /* MOV tmp, texcoord */
1751 if (!submit_op1( emit
,
1752 inst_token( SVGA3DOP_MOV
),
1757 /* MOV tmp.w, zero */
1758 if (!submit_op1( emit
,
1759 inst_token( SVGA3DOP_MOV
),
1760 writemask( tmp
, TGSI_WRITEMASK_W
),
1764 texcoord
= src( tmp
);
1765 inst
.op
= SVGA3DOP_TEXLDL
;
1768 /* Explicit normalization of texcoords:
1770 if (emit
->key
.fkey
.tex
[sampler
.base
.num
].unnormalized
) {
1771 struct src_register wh
= get_tex_dimensions( emit
, sampler
.base
.num
);
1773 /* MUL tmp, SRC0, WH */
1774 if (!submit_op2( emit
, inst_token( SVGA3DOP_MUL
),
1775 tmp
, texcoord
, wh
))
1778 texcoord
= src( tmp
);
1781 return submit_op2( emit
, inst
, dst
, texcoord
, sampler
);
1786 * Translate/emit 4-operand (coord, ddx, ddy, sampler) texture instructions.
1789 emit_tex4(struct svga_shader_emitter
*emit
,
1790 const struct tgsi_full_instruction
*insn
,
1791 SVGA3dShaderDestToken dst
)
1793 SVGA3dShaderInstToken inst
;
1794 struct src_register texcoord
;
1795 struct src_register ddx
;
1796 struct src_register ddy
;
1797 struct src_register sampler
;
1799 texcoord
= translate_src_register( emit
, &insn
->Src
[0] );
1800 ddx
= translate_src_register( emit
, &insn
->Src
[1] );
1801 ddy
= translate_src_register( emit
, &insn
->Src
[2] );
1802 sampler
= translate_src_register( emit
, &insn
->Src
[3] );
1806 switch (insn
->Instruction
.Opcode
) {
1807 case TGSI_OPCODE_TXD
:
1808 inst
.op
= SVGA3DOP_TEXLDD
; /* 4 args! */
1815 return submit_op4( emit
, inst
, dst
, texcoord
, sampler
, ddx
, ddy
);
1820 * Emit texture swizzle code. We do this here since SVGA samplers don't
1821 * directly support swizzles.
1824 emit_tex_swizzle(struct svga_shader_emitter
*emit
,
1825 SVGA3dShaderDestToken dst
,
1826 struct src_register src
,
1832 const unsigned swizzleIn
[4] = {swizzle_x
, swizzle_y
, swizzle_z
, swizzle_w
};
1833 unsigned srcSwizzle
[4];
1834 unsigned srcWritemask
= 0x0, zeroWritemask
= 0x0, oneWritemask
= 0x0;
1837 /* build writemasks and srcSwizzle terms */
1838 for (i
= 0; i
< 4; i
++) {
1839 if (swizzleIn
[i
] == PIPE_SWIZZLE_ZERO
) {
1840 srcSwizzle
[i
] = TGSI_SWIZZLE_X
+ i
;
1841 zeroWritemask
|= (1 << i
);
1843 else if (swizzleIn
[i
] == PIPE_SWIZZLE_ONE
) {
1844 srcSwizzle
[i
] = TGSI_SWIZZLE_X
+ i
;
1845 oneWritemask
|= (1 << i
);
1848 srcSwizzle
[i
] = swizzleIn
[i
];
1849 srcWritemask
|= (1 << i
);
1853 /* write x/y/z/w comps */
1854 if (dst
.mask
& srcWritemask
) {
1855 if (!submit_op1(emit
,
1856 inst_token(SVGA3DOP_MOV
),
1857 writemask(dst
, srcWritemask
),
1867 if (dst
.mask
& zeroWritemask
) {
1868 if (!submit_op1(emit
,
1869 inst_token(SVGA3DOP_MOV
),
1870 writemask(dst
, zeroWritemask
),
1871 get_zero_immediate(emit
)))
1876 if (dst
.mask
& oneWritemask
) {
1877 if (!submit_op1(emit
,
1878 inst_token(SVGA3DOP_MOV
),
1879 writemask(dst
, oneWritemask
),
1880 get_one_immediate(emit
)))
1889 * Translate/emit a TGSI texture sample instruction.
1892 emit_tex(struct svga_shader_emitter
*emit
,
1893 const struct tgsi_full_instruction
*insn
)
1895 SVGA3dShaderDestToken dst
=
1896 translate_dst_register( emit
, insn
, 0 );
1897 struct src_register src0
=
1898 translate_src_register( emit
, &insn
->Src
[0] );
1899 struct src_register src1
=
1900 translate_src_register( emit
, &insn
->Src
[1] );
1902 SVGA3dShaderDestToken tex_result
;
1903 const unsigned unit
= src1
.base
.num
;
1905 /* check for shadow samplers */
1906 boolean compare
= (emit
->key
.fkey
.tex
[unit
].compare_mode
==
1907 PIPE_TEX_COMPARE_R_TO_TEXTURE
);
1909 /* texture swizzle */
1910 boolean swizzle
= (emit
->key
.fkey
.tex
[unit
].swizzle_r
!= PIPE_SWIZZLE_RED
||
1911 emit
->key
.fkey
.tex
[unit
].swizzle_g
!= PIPE_SWIZZLE_GREEN
||
1912 emit
->key
.fkey
.tex
[unit
].swizzle_b
!= PIPE_SWIZZLE_BLUE
||
1913 emit
->key
.fkey
.tex
[unit
].swizzle_a
!= PIPE_SWIZZLE_ALPHA
);
1915 boolean saturate
= insn
->Instruction
.Saturate
!= TGSI_SAT_NONE
;
1917 /* If doing compare processing or tex swizzle or saturation, we need to put
1918 * the fetched color into a temporary so it can be used as a source later on.
1920 if (compare
|| swizzle
|| saturate
) {
1921 tex_result
= get_temp( emit
);
1927 switch(insn
->Instruction
.Opcode
) {
1928 case TGSI_OPCODE_TEX
:
1929 case TGSI_OPCODE_TXB
:
1930 case TGSI_OPCODE_TXP
:
1931 case TGSI_OPCODE_TXL
:
1932 if (!emit_tex2( emit
, insn
, tex_result
))
1935 case TGSI_OPCODE_TXD
:
1936 if (!emit_tex4( emit
, insn
, tex_result
))
1944 SVGA3dShaderDestToken dst2
;
1946 if (swizzle
|| saturate
)
1951 if (dst
.mask
& TGSI_WRITEMASK_XYZ
) {
1952 SVGA3dShaderDestToken src0_zdivw
= get_temp( emit
);
1953 /* When sampling a depth texture, the result of the comparison is in
1956 struct src_register tex_src_x
= scalar(src(tex_result
), TGSI_SWIZZLE_Y
);
1957 struct src_register r_coord
;
1959 if (insn
->Instruction
.Opcode
== TGSI_OPCODE_TXP
) {
1960 /* Divide texcoord R by Q */
1961 if (!submit_op1( emit
, inst_token( SVGA3DOP_RCP
),
1962 writemask(src0_zdivw
, TGSI_WRITEMASK_X
),
1963 scalar(src0
, TGSI_SWIZZLE_W
) ))
1966 if (!submit_op2( emit
, inst_token( SVGA3DOP_MUL
),
1967 writemask(src0_zdivw
, TGSI_WRITEMASK_X
),
1968 scalar(src0
, TGSI_SWIZZLE_Z
),
1969 scalar(src(src0_zdivw
), TGSI_SWIZZLE_X
) ))
1972 r_coord
= scalar(src(src0_zdivw
), TGSI_SWIZZLE_X
);
1975 r_coord
= scalar(src0
, TGSI_SWIZZLE_Z
);
1978 /* Compare texture sample value against R component of texcoord */
1979 if (!emit_select(emit
,
1980 emit
->key
.fkey
.tex
[unit
].compare_func
,
1981 writemask( dst2
, TGSI_WRITEMASK_XYZ
),
1987 if (dst
.mask
& TGSI_WRITEMASK_W
) {
1988 struct src_register one
= get_one_immediate(emit
);
1990 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
1991 writemask( dst2
, TGSI_WRITEMASK_W
),
1997 if (saturate
&& !swizzle
) {
1998 /* MOV_SAT real_dst, dst */
1999 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), dst
, src(tex_result
) ))
2003 /* swizzle from tex_result to dst (handles saturation too, if any) */
2004 emit_tex_swizzle(emit
,
2005 dst
, src(tex_result
),
2006 emit
->key
.fkey
.tex
[unit
].swizzle_r
,
2007 emit
->key
.fkey
.tex
[unit
].swizzle_g
,
2008 emit
->key
.fkey
.tex
[unit
].swizzle_b
,
2009 emit
->key
.fkey
.tex
[unit
].swizzle_a
);
2017 emit_bgnloop(struct svga_shader_emitter
*emit
,
2018 const struct tgsi_full_instruction
*insn
)
2020 SVGA3dShaderInstToken inst
= inst_token( SVGA3DOP_LOOP
);
2021 struct src_register loop_reg
= src_register( SVGA3DREG_LOOP
, 0 );
2022 struct src_register const_int
= get_loop_const( emit
);
2024 emit
->dynamic_branching_level
++;
2026 return (emit_instruction( emit
, inst
) &&
2027 emit_src( emit
, loop_reg
) &&
2028 emit_src( emit
, const_int
) );
2033 emit_endloop(struct svga_shader_emitter
*emit
,
2034 const struct tgsi_full_instruction
*insn
)
2036 SVGA3dShaderInstToken inst
= inst_token( SVGA3DOP_ENDLOOP
);
2038 emit
->dynamic_branching_level
--;
2040 return emit_instruction( emit
, inst
);
2045 * Translate/emit TGSI BREAK (out of loop) instruction.
2048 emit_brk(struct svga_shader_emitter
*emit
,
2049 const struct tgsi_full_instruction
*insn
)
2051 SVGA3dShaderInstToken inst
= inst_token( SVGA3DOP_BREAK
);
2052 return emit_instruction( emit
, inst
);
2057 * Emit simple instruction which operates on one scalar value (not
2058 * a vector). Ex: LG2, RCP, RSQ.
2061 emit_scalar_op1(struct svga_shader_emitter
*emit
,
2063 const struct tgsi_full_instruction
*insn
)
2065 SVGA3dShaderInstToken inst
;
2066 SVGA3dShaderDestToken dst
;
2067 struct src_register src
;
2069 inst
= inst_token( opcode
);
2070 dst
= translate_dst_register( emit
, insn
, 0 );
2071 src
= translate_src_register( emit
, &insn
->Src
[0] );
2072 src
= scalar( src
, TGSI_SWIZZLE_X
);
2074 return submit_op1( emit
, inst
, dst
, src
);
2079 * Translate/emit a simple instruction (one which has no special-case
2080 * code) such as ADD, MUL, MIN, MAX.
2083 emit_simple_instruction(struct svga_shader_emitter
*emit
,
2085 const struct tgsi_full_instruction
*insn
)
2087 const struct tgsi_full_src_register
*src
= insn
->Src
;
2088 SVGA3dShaderInstToken inst
;
2089 SVGA3dShaderDestToken dst
;
2091 inst
= inst_token( opcode
);
2092 dst
= translate_dst_register( emit
, insn
, 0 );
2094 switch (insn
->Instruction
.NumSrcRegs
) {
2096 return submit_op0( emit
, inst
, dst
);
2098 return submit_op1( emit
, inst
, dst
,
2099 translate_src_register( emit
, &src
[0] ));
2101 return submit_op2( emit
, inst
, dst
,
2102 translate_src_register( emit
, &src
[0] ),
2103 translate_src_register( emit
, &src
[1] ) );
2105 return submit_op3( emit
, inst
, dst
,
2106 translate_src_register( emit
, &src
[0] ),
2107 translate_src_register( emit
, &src
[1] ),
2108 translate_src_register( emit
, &src
[2] ) );
2117 * Translate/emit TGSI DDX, DDY instructions.
2120 emit_deriv(struct svga_shader_emitter
*emit
,
2121 const struct tgsi_full_instruction
*insn
)
2123 if (emit
->dynamic_branching_level
> 0 &&
2124 insn
->Src
[0].Register
.File
== TGSI_FILE_TEMPORARY
)
2126 SVGA3dShaderDestToken dst
=
2127 translate_dst_register( emit
, insn
, 0 );
2129 /* Deriv opcodes not valid inside dynamic branching, workaround
2130 * by zeroing out the destination.
2132 if (!submit_op1(emit
,
2133 inst_token( SVGA3DOP_MOV
),
2135 get_zero_immediate(emit
)))
2142 const struct tgsi_full_src_register
*reg
= &insn
->Src
[0];
2143 SVGA3dShaderInstToken inst
;
2144 SVGA3dShaderDestToken dst
;
2145 struct src_register src0
;
2147 switch (insn
->Instruction
.Opcode
) {
2148 case TGSI_OPCODE_DDX
:
2149 opcode
= SVGA3DOP_DSX
;
2151 case TGSI_OPCODE_DDY
:
2152 opcode
= SVGA3DOP_DSY
;
2158 inst
= inst_token( opcode
);
2159 dst
= translate_dst_register( emit
, insn
, 0 );
2160 src0
= translate_src_register( emit
, reg
);
2162 /* We cannot use negate or abs on source to dsx/dsy instruction.
2164 if (reg
->Register
.Absolute
||
2165 reg
->Register
.Negate
) {
2166 SVGA3dShaderDestToken temp
= get_temp( emit
);
2168 if (!emit_repl( emit
, temp
, &src0
))
2172 return submit_op1( emit
, inst
, dst
, src0
);
2178 * Translate/emit ARL (Address Register Load) instruction. Used to
2179 * move a value into the special 'address' register. Used to implement
2180 * indirect/variable indexing into arrays.
2183 emit_arl(struct svga_shader_emitter
*emit
,
2184 const struct tgsi_full_instruction
*insn
)
2186 ++emit
->current_arl
;
2187 if (emit
->unit
== PIPE_SHADER_FRAGMENT
) {
2188 /* MOVA not present in pixel shader instruction set.
2189 * Ignore this instruction altogether since it is
2190 * only used for loop counters -- and for that
2191 * we reference aL directly.
2195 if (svga_arl_needs_adjustment( emit
)) {
2196 return emit_fake_arl( emit
, insn
);
2198 /* no need to adjust, just emit straight arl */
2199 return emit_simple_instruction(emit
, SVGA3DOP_MOVA
, insn
);
2205 emit_pow(struct svga_shader_emitter
*emit
,
2206 const struct tgsi_full_instruction
*insn
)
2208 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
2209 struct src_register src0
= translate_src_register(
2210 emit
, &insn
->Src
[0] );
2211 struct src_register src1
= translate_src_register(
2212 emit
, &insn
->Src
[1] );
2213 boolean need_tmp
= FALSE
;
2215 /* POW can only output to a temporary */
2216 if (insn
->Dst
[0].Register
.File
!= TGSI_FILE_TEMPORARY
)
2219 /* POW src1 must not be the same register as dst */
2220 if (alias_src_dst( src1
, dst
))
2223 /* it's a scalar op */
2224 src0
= scalar( src0
, TGSI_SWIZZLE_X
);
2225 src1
= scalar( src1
, TGSI_SWIZZLE_X
);
2228 SVGA3dShaderDestToken tmp
=
2229 writemask(get_temp( emit
), TGSI_WRITEMASK_X
);
2231 if (!submit_op2(emit
, inst_token( SVGA3DOP_POW
), tmp
, src0
, src1
))
2234 return submit_op1(emit
, inst_token( SVGA3DOP_MOV
),
2235 dst
, scalar(src(tmp
), 0) );
2238 return submit_op2(emit
, inst_token( SVGA3DOP_POW
), dst
, src0
, src1
);
2244 * Translate/emit TGSI XPD (vector cross product) instruction.
2247 emit_xpd(struct svga_shader_emitter
*emit
,
2248 const struct tgsi_full_instruction
*insn
)
2250 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
2251 const struct src_register src0
= translate_src_register(
2252 emit
, &insn
->Src
[0] );
2253 const struct src_register src1
= translate_src_register(
2254 emit
, &insn
->Src
[1] );
2255 boolean need_dst_tmp
= FALSE
;
2257 /* XPD can only output to a temporary */
2258 if (SVGA3dShaderGetRegType(dst
.value
) != SVGA3DREG_TEMP
)
2259 need_dst_tmp
= TRUE
;
2261 /* The dst reg must not be the same as src0 or src1*/
2262 if (alias_src_dst(src0
, dst
) ||
2263 alias_src_dst(src1
, dst
))
2264 need_dst_tmp
= TRUE
;
2267 SVGA3dShaderDestToken tmp
= get_temp( emit
);
2269 /* Obey DX9 restrictions on mask:
2271 tmp
.mask
= dst
.mask
& TGSI_WRITEMASK_XYZ
;
2273 if (!submit_op2(emit
, inst_token( SVGA3DOP_CRS
), tmp
, src0
, src1
))
2276 if (!submit_op1(emit
, inst_token( SVGA3DOP_MOV
), dst
, src( tmp
)))
2280 if (!submit_op2(emit
, inst_token( SVGA3DOP_CRS
), dst
, src0
, src1
))
2284 /* Need to emit 1.0 to dst.w?
2286 if (dst
.mask
& TGSI_WRITEMASK_W
) {
2287 struct src_register one
= get_one_immediate( emit
);
2289 if (!submit_op1(emit
,
2290 inst_token( SVGA3DOP_MOV
),
2291 writemask(dst
, TGSI_WRITEMASK_W
),
2301 * Emit a LRP (linear interpolation) instruction.
2304 submit_lrp(struct svga_shader_emitter
*emit
,
2305 SVGA3dShaderDestToken dst
,
2306 struct src_register src0
,
2307 struct src_register src1
,
2308 struct src_register src2
)
2310 SVGA3dShaderDestToken tmp
;
2311 boolean need_dst_tmp
= FALSE
;
2313 /* The dst reg must be a temporary, and not be the same as src0 or src2 */
2314 if (SVGA3dShaderGetRegType(dst
.value
) != SVGA3DREG_TEMP
||
2315 alias_src_dst(src0
, dst
) ||
2316 alias_src_dst(src2
, dst
))
2317 need_dst_tmp
= TRUE
;
2320 tmp
= get_temp( emit
);
2321 tmp
.mask
= dst
.mask
;
2327 if (!submit_op3(emit
, inst_token( SVGA3DOP_LRP
), tmp
, src0
, src1
, src2
))
2331 if (!submit_op1(emit
, inst_token( SVGA3DOP_MOV
), dst
, src( tmp
)))
2340 * Translate/emit LRP (Linear Interpolation) instruction.
2343 emit_lrp(struct svga_shader_emitter
*emit
,
2344 const struct tgsi_full_instruction
*insn
)
2346 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
2347 const struct src_register src0
= translate_src_register(
2348 emit
, &insn
->Src
[0] );
2349 const struct src_register src1
= translate_src_register(
2350 emit
, &insn
->Src
[1] );
2351 const struct src_register src2
= translate_src_register(
2352 emit
, &insn
->Src
[2] );
2354 return submit_lrp(emit
, dst
, src0
, src1
, src2
);
2358 * Translate/emit DST (Distance function) instruction.
2361 emit_dst_insn(struct svga_shader_emitter
*emit
,
2362 const struct tgsi_full_instruction
*insn
)
2364 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
2365 /* SVGA/DX9 has a DST instruction, but only for vertex shaders:
2367 return emit_simple_instruction(emit
, SVGA3DOP_DST
, insn
);
2370 /* result[0] = 1 * 1;
2371 * result[1] = a[1] * b[1];
2372 * result[2] = a[2] * 1;
2373 * result[3] = 1 * b[3];
2375 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
2376 SVGA3dShaderDestToken tmp
;
2377 const struct src_register src0
= translate_src_register(
2378 emit
, &insn
->Src
[0] );
2379 const struct src_register src1
= translate_src_register(
2380 emit
, &insn
->Src
[1] );
2381 boolean need_tmp
= FALSE
;
2383 if (SVGA3dShaderGetRegType(dst
.value
) != SVGA3DREG_TEMP
||
2384 alias_src_dst(src0
, dst
) ||
2385 alias_src_dst(src1
, dst
))
2389 tmp
= get_temp( emit
);
2397 if (tmp
.mask
& TGSI_WRITEMASK_XW
) {
2398 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
2399 writemask(tmp
, TGSI_WRITEMASK_XW
),
2400 get_one_immediate(emit
)))
2406 if (tmp
.mask
& TGSI_WRITEMASK_YZ
) {
2407 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
2408 writemask(tmp
, TGSI_WRITEMASK_YZ
),
2413 /* tmp.yw = tmp * src1
2415 if (tmp
.mask
& TGSI_WRITEMASK_YW
) {
2416 if (!submit_op2( emit
, inst_token( SVGA3DOP_MUL
),
2417 writemask(tmp
, TGSI_WRITEMASK_YW
),
2426 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
2438 emit_exp(struct svga_shader_emitter
*emit
,
2439 const struct tgsi_full_instruction
*insn
)
2441 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
2442 struct src_register src0
=
2443 translate_src_register( emit
, &insn
->Src
[0] );
2444 SVGA3dShaderDestToken fraction
;
2446 if (dst
.mask
& TGSI_WRITEMASK_Y
)
2448 else if (dst
.mask
& TGSI_WRITEMASK_X
)
2449 fraction
= get_temp( emit
);
2453 /* If y is being written, fill it with src0 - floor(src0).
2455 if (dst
.mask
& TGSI_WRITEMASK_XY
) {
2456 if (!submit_op1( emit
, inst_token( SVGA3DOP_FRC
),
2457 writemask( fraction
, TGSI_WRITEMASK_Y
),
2462 /* If x is being written, fill it with 2 ^ floor(src0).
2464 if (dst
.mask
& TGSI_WRITEMASK_X
) {
2465 if (!submit_op2( emit
, inst_token( SVGA3DOP_ADD
),
2466 writemask( dst
, TGSI_WRITEMASK_X
),
2468 scalar( negate( src( fraction
) ), TGSI_SWIZZLE_Y
) ) )
2471 if (!submit_op1( emit
, inst_token( SVGA3DOP_EXP
),
2472 writemask( dst
, TGSI_WRITEMASK_X
),
2473 scalar( src( dst
), TGSI_SWIZZLE_X
) ) )
2476 if (!(dst
.mask
& TGSI_WRITEMASK_Y
))
2477 release_temp( emit
, fraction
);
2480 /* If z is being written, fill it with 2 ^ src0 (partial precision).
2482 if (dst
.mask
& TGSI_WRITEMASK_Z
) {
2483 if (!submit_op1( emit
, inst_token( SVGA3DOP_EXPP
),
2484 writemask( dst
, TGSI_WRITEMASK_Z
),
2489 /* If w is being written, fill it with one.
2491 if (dst
.mask
& TGSI_WRITEMASK_W
) {
2492 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
2493 writemask(dst
, TGSI_WRITEMASK_W
),
2494 get_one_immediate(emit
)))
2503 * Translate/emit LIT (Lighting helper) instruction.
2506 emit_lit(struct svga_shader_emitter
*emit
,
2507 const struct tgsi_full_instruction
*insn
)
2509 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
2510 /* SVGA/DX9 has a LIT instruction, but only for vertex shaders:
2512 return emit_simple_instruction(emit
, SVGA3DOP_LIT
, insn
);
2515 /* D3D vs. GL semantics can be fairly easily accomodated by
2516 * variations on this sequence.
2520 * tmp.z = pow(src.y,src.w)
2521 * p0 = src0.xxxx > 0
2522 * result = zero.wxxw
2523 * (p0) result.yz = tmp
2527 * tmp.z = pow(src.y,src.w)
2528 * p0 = src0.xxyy > 0
2529 * result = zero.wxxw
2530 * (p0) result.yz = tmp
2532 * Will implement the GL version for now.
2534 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
2535 SVGA3dShaderDestToken tmp
= get_temp( emit
);
2536 const struct src_register src0
= translate_src_register(
2537 emit
, &insn
->Src
[0] );
2539 /* tmp = pow(src.y, src.w)
2541 if (dst
.mask
& TGSI_WRITEMASK_Z
) {
2542 if (!submit_op2(emit
, inst_token( SVGA3DOP_POW
),
2551 if (dst
.mask
& TGSI_WRITEMASK_Y
) {
2552 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
2553 writemask(tmp
, TGSI_WRITEMASK_Y
),
2558 /* Can't quite do this with emit conditional due to the extra
2559 * writemask on the predicated mov:
2562 SVGA3dShaderDestToken pred_reg
= dst_register( SVGA3DREG_PREDICATE
, 0 );
2563 SVGA3dShaderInstToken setp_token
, mov_token
;
2564 struct src_register predsrc
;
2566 setp_token
= inst_token( SVGA3DOP_SETP
);
2567 mov_token
= inst_token( SVGA3DOP_MOV
);
2569 setp_token
.control
= SVGA3DOPCOMP_GT
;
2571 /* D3D vs GL semantics:
2574 predsrc
= swizzle(src0
, 0, 0, 1, 1); /* D3D */
2576 predsrc
= swizzle(src0
, 0, 0, 0, 0); /* GL */
2578 /* SETP src0.xxyy, GT, {0}.x */
2579 if (!submit_op2( emit
, setp_token
, pred_reg
,
2581 get_zero_immediate(emit
)))
2585 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), dst
,
2586 get_immediate(emit
, 1.0f
, 0.0f
, 0.0f
, 1.0f
)))
2589 /* MOV dst.yz, tmp (predicated)
2591 * Note that the predicate reg (and possible modifiers) is passed
2592 * as the first source argument.
2594 if (dst
.mask
& TGSI_WRITEMASK_YZ
) {
2595 mov_token
.predicated
= 1;
2596 if (!submit_op2( emit
, mov_token
,
2597 writemask(dst
, TGSI_WRITEMASK_YZ
),
2598 src( pred_reg
), src( tmp
) ))
2609 emit_ex2(struct svga_shader_emitter
*emit
,
2610 const struct tgsi_full_instruction
*insn
)
2612 SVGA3dShaderInstToken inst
;
2613 SVGA3dShaderDestToken dst
;
2614 struct src_register src0
;
2616 inst
= inst_token( SVGA3DOP_EXP
);
2617 dst
= translate_dst_register( emit
, insn
, 0 );
2618 src0
= translate_src_register( emit
, &insn
->Src
[0] );
2619 src0
= scalar( src0
, TGSI_SWIZZLE_X
);
2621 if (dst
.mask
!= TGSI_WRITEMASK_XYZW
) {
2622 SVGA3dShaderDestToken tmp
= get_temp( emit
);
2624 if (!submit_op1( emit
, inst
, tmp
, src0
))
2627 return submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
2629 scalar( src( tmp
), TGSI_SWIZZLE_X
) );
2632 return submit_op1( emit
, inst
, dst
, src0
);
2637 emit_log(struct svga_shader_emitter
*emit
,
2638 const struct tgsi_full_instruction
*insn
)
2640 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
2641 struct src_register src0
=
2642 translate_src_register( emit
, &insn
->Src
[0] );
2643 SVGA3dShaderDestToken abs_tmp
;
2644 struct src_register abs_src0
;
2645 SVGA3dShaderDestToken log2_abs
;
2649 if (dst
.mask
& TGSI_WRITEMASK_Z
)
2651 else if (dst
.mask
& TGSI_WRITEMASK_XY
)
2652 log2_abs
= get_temp( emit
);
2656 /* If z is being written, fill it with log2( abs( src0 ) ).
2658 if (dst
.mask
& TGSI_WRITEMASK_XYZ
) {
2659 if (!src0
.base
.srcMod
|| src0
.base
.srcMod
== SVGA3DSRCMOD_ABS
)
2662 abs_tmp
= get_temp( emit
);
2664 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
2669 abs_src0
= src( abs_tmp
);
2672 abs_src0
= absolute( scalar( abs_src0
, TGSI_SWIZZLE_X
) );
2674 if (!submit_op1( emit
, inst_token( SVGA3DOP_LOG
),
2675 writemask( log2_abs
, TGSI_WRITEMASK_Z
),
2680 if (dst
.mask
& TGSI_WRITEMASK_XY
) {
2681 SVGA3dShaderDestToken floor_log2
;
2683 if (dst
.mask
& TGSI_WRITEMASK_X
)
2686 floor_log2
= get_temp( emit
);
2688 /* If x is being written, fill it with floor( log2( abs( src0 ) ) ).
2690 if (!submit_op1( emit
, inst_token( SVGA3DOP_FRC
),
2691 writemask( floor_log2
, TGSI_WRITEMASK_X
),
2692 scalar( src( log2_abs
), TGSI_SWIZZLE_Z
) ) )
2695 if (!submit_op2( emit
, inst_token( SVGA3DOP_ADD
),
2696 writemask( floor_log2
, TGSI_WRITEMASK_X
),
2697 scalar( src( log2_abs
), TGSI_SWIZZLE_Z
),
2698 negate( src( floor_log2
) ) ) )
2701 /* If y is being written, fill it with
2702 * abs ( src0 ) / ( 2 ^ floor( log2( abs( src0 ) ) ) ).
2704 if (dst
.mask
& TGSI_WRITEMASK_Y
) {
2705 if (!submit_op1( emit
, inst_token( SVGA3DOP_EXP
),
2706 writemask( dst
, TGSI_WRITEMASK_Y
),
2707 negate( scalar( src( floor_log2
),
2708 TGSI_SWIZZLE_X
) ) ) )
2711 if (!submit_op2( emit
, inst_token( SVGA3DOP_MUL
),
2712 writemask( dst
, TGSI_WRITEMASK_Y
),
2718 if (!(dst
.mask
& TGSI_WRITEMASK_X
))
2719 release_temp( emit
, floor_log2
);
2721 if (!(dst
.mask
& TGSI_WRITEMASK_Z
))
2722 release_temp( emit
, log2_abs
);
2725 if (dst
.mask
& TGSI_WRITEMASK_XYZ
&& src0
.base
.srcMod
&&
2726 src0
.base
.srcMod
!= SVGA3DSRCMOD_ABS
)
2727 release_temp( emit
, abs_tmp
);
2729 /* If w is being written, fill it with one.
2731 if (dst
.mask
& TGSI_WRITEMASK_W
) {
2732 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
2733 writemask(dst
, TGSI_WRITEMASK_W
),
2734 get_one_immediate(emit
)))
2743 * Translate TGSI TRUNC or ROUND instruction.
2744 * We need to truncate toward zero. Ex: trunc(-1.9) = -1
2745 * Different approaches are needed for VS versus PS.
2748 emit_trunc_round(struct svga_shader_emitter
*emit
,
2749 const struct tgsi_full_instruction
*insn
,
2752 SVGA3dShaderDestToken dst
= translate_dst_register(emit
, insn
, 0);
2753 const struct src_register src0
=
2754 translate_src_register(emit
, &insn
->Src
[0] );
2755 SVGA3dShaderDestToken t1
= get_temp(emit
);
2758 SVGA3dShaderDestToken t0
= get_temp(emit
);
2759 struct src_register half
= get_half_immediate(emit
);
2761 /* t0 = abs(src0) + 0.5 */
2762 if (!submit_op2(emit
, inst_token(SVGA3DOP_ADD
), t0
,
2763 absolute(src0
), half
))
2766 /* t1 = fract(t0) */
2767 if (!submit_op1(emit
, inst_token(SVGA3DOP_FRC
), t1
, src(t0
)))
2771 if (!submit_op2(emit
, inst_token(SVGA3DOP_ADD
), t1
, src(t0
),
2778 /* t1 = fract(abs(src0)) */
2779 if (!submit_op1(emit
, inst_token(SVGA3DOP_FRC
), t1
, absolute(src0
)))
2782 /* t1 = abs(src0) - t1 */
2783 if (!submit_op2(emit
, inst_token(SVGA3DOP_ADD
), t1
, absolute(src0
),
2789 * Now we need to multiply t1 by the sign of the original value.
2791 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
2792 /* For VS: use SGN instruction */
2793 /* Need two extra/dummy registers: */
2794 SVGA3dShaderDestToken t2
= get_temp(emit
), t3
= get_temp(emit
),
2795 t4
= get_temp(emit
);
2797 /* t2 = sign(src0) */
2798 if (!submit_op3(emit
, inst_token(SVGA3DOP_SGN
), t2
, src0
,
2803 if (!submit_op2(emit
, inst_token(SVGA3DOP_MUL
), dst
, src(t1
), src(t2
)))
2807 /* For FS: Use CMP instruction */
2808 return submit_op3(emit
, inst_token( SVGA3DOP_CMP
), dst
,
2809 src0
, src(t1
), negate(src(t1
)));
2817 * Translate/emit "begin subroutine" instruction/marker/label.
2820 emit_bgnsub(struct svga_shader_emitter
*emit
,
2822 const struct tgsi_full_instruction
*insn
)
2826 /* Note that we've finished the main function and are now emitting
2827 * subroutines. This affects how we terminate the generated
2830 emit
->in_main_func
= FALSE
;
2832 for (i
= 0; i
< emit
->nr_labels
; i
++) {
2833 if (emit
->label
[i
] == position
) {
2834 return (emit_instruction( emit
, inst_token( SVGA3DOP_RET
) ) &&
2835 emit_instruction( emit
, inst_token( SVGA3DOP_LABEL
) ) &&
2836 emit_src( emit
, src_register( SVGA3DREG_LABEL
, i
)));
2846 * Translate/emit subroutine call instruction.
2849 emit_call(struct svga_shader_emitter
*emit
,
2850 const struct tgsi_full_instruction
*insn
)
2852 unsigned position
= insn
->Label
.Label
;
2855 for (i
= 0; i
< emit
->nr_labels
; i
++) {
2856 if (emit
->label
[i
] == position
)
2860 if (emit
->nr_labels
== Elements(emit
->label
))
2863 if (i
== emit
->nr_labels
) {
2864 emit
->label
[i
] = position
;
2868 return (emit_instruction( emit
, inst_token( SVGA3DOP_CALL
) ) &&
2869 emit_src( emit
, src_register( SVGA3DREG_LABEL
, i
)));
2874 * Called at the end of the shader. Actually, emit special "fix-up"
2875 * code for the vertex/fragment shader.
2878 emit_end(struct svga_shader_emitter
*emit
)
2880 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
2881 return emit_vs_postamble( emit
);
2884 return emit_ps_postamble( emit
);
2890 * Translate any TGSI instruction to SVGA.
2893 svga_emit_instruction(struct svga_shader_emitter
*emit
,
2895 const struct tgsi_full_instruction
*insn
)
2897 switch (insn
->Instruction
.Opcode
) {
2899 case TGSI_OPCODE_ARL
:
2900 return emit_arl( emit
, insn
);
2902 case TGSI_OPCODE_TEX
:
2903 case TGSI_OPCODE_TXB
:
2904 case TGSI_OPCODE_TXP
:
2905 case TGSI_OPCODE_TXL
:
2906 case TGSI_OPCODE_TXD
:
2907 return emit_tex( emit
, insn
);
2909 case TGSI_OPCODE_DDX
:
2910 case TGSI_OPCODE_DDY
:
2911 return emit_deriv( emit
, insn
);
2913 case TGSI_OPCODE_BGNSUB
:
2914 return emit_bgnsub( emit
, position
, insn
);
2916 case TGSI_OPCODE_ENDSUB
:
2919 case TGSI_OPCODE_CAL
:
2920 return emit_call( emit
, insn
);
2922 case TGSI_OPCODE_FLR
:
2923 return emit_floor( emit
, insn
);
2925 case TGSI_OPCODE_TRUNC
:
2926 return emit_trunc_round( emit
, insn
, FALSE
);
2928 case TGSI_OPCODE_ROUND
:
2929 return emit_trunc_round( emit
, insn
, TRUE
);
2931 case TGSI_OPCODE_CEIL
:
2932 return emit_ceil( emit
, insn
);
2934 case TGSI_OPCODE_CMP
:
2935 return emit_cmp( emit
, insn
);
2937 case TGSI_OPCODE_DIV
:
2938 return emit_div( emit
, insn
);
2940 case TGSI_OPCODE_DP2
:
2941 return emit_dp2( emit
, insn
);
2943 case TGSI_OPCODE_DPH
:
2944 return emit_dph( emit
, insn
);
2946 case TGSI_OPCODE_NRM
:
2947 return emit_nrm( emit
, insn
);
2949 case TGSI_OPCODE_COS
:
2950 return emit_cos( emit
, insn
);
2952 case TGSI_OPCODE_SIN
:
2953 return emit_sin( emit
, insn
);
2955 case TGSI_OPCODE_SCS
:
2956 return emit_sincos( emit
, insn
);
2958 case TGSI_OPCODE_END
:
2959 /* TGSI always finishes the main func with an END */
2960 return emit_end( emit
);
2962 case TGSI_OPCODE_KILL_IF
:
2963 return emit_kill_if( emit
, insn
);
2965 /* Selection opcodes. The underlying language is fairly
2966 * non-orthogonal about these.
2968 case TGSI_OPCODE_SEQ
:
2969 return emit_select_op( emit
, PIPE_FUNC_EQUAL
, insn
);
2971 case TGSI_OPCODE_SNE
:
2972 return emit_select_op( emit
, PIPE_FUNC_NOTEQUAL
, insn
);
2974 case TGSI_OPCODE_SGT
:
2975 return emit_select_op( emit
, PIPE_FUNC_GREATER
, insn
);
2977 case TGSI_OPCODE_SGE
:
2978 return emit_select_op( emit
, PIPE_FUNC_GEQUAL
, insn
);
2980 case TGSI_OPCODE_SLT
:
2981 return emit_select_op( emit
, PIPE_FUNC_LESS
, insn
);
2983 case TGSI_OPCODE_SLE
:
2984 return emit_select_op( emit
, PIPE_FUNC_LEQUAL
, insn
);
2986 case TGSI_OPCODE_SUB
:
2987 return emit_sub( emit
, insn
);
2989 case TGSI_OPCODE_POW
:
2990 return emit_pow( emit
, insn
);
2992 case TGSI_OPCODE_EX2
:
2993 return emit_ex2( emit
, insn
);
2995 case TGSI_OPCODE_EXP
:
2996 return emit_exp( emit
, insn
);
2998 case TGSI_OPCODE_LOG
:
2999 return emit_log( emit
, insn
);
3001 case TGSI_OPCODE_LG2
:
3002 return emit_scalar_op1( emit
, SVGA3DOP_LOG
, insn
);
3004 case TGSI_OPCODE_RSQ
:
3005 return emit_scalar_op1( emit
, SVGA3DOP_RSQ
, insn
);
3007 case TGSI_OPCODE_RCP
:
3008 return emit_scalar_op1( emit
, SVGA3DOP_RCP
, insn
);
3010 case TGSI_OPCODE_CONT
:
3011 /* not expected (we return PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED = 0) */
3014 case TGSI_OPCODE_RET
:
3015 /* This is a noop -- we tell mesa that we can't support RET
3016 * within a function (early return), so this will always be
3017 * followed by an ENDSUB.
3021 /* These aren't actually used by any of the frontends we care
3024 case TGSI_OPCODE_CLAMP
:
3025 case TGSI_OPCODE_AND
:
3026 case TGSI_OPCODE_OR
:
3027 case TGSI_OPCODE_I2F
:
3028 case TGSI_OPCODE_NOT
:
3029 case TGSI_OPCODE_SHL
:
3030 case TGSI_OPCODE_ISHR
:
3031 case TGSI_OPCODE_XOR
:
3034 case TGSI_OPCODE_IF
:
3035 return emit_if( emit
, insn
);
3036 case TGSI_OPCODE_ELSE
:
3037 return emit_else( emit
, insn
);
3038 case TGSI_OPCODE_ENDIF
:
3039 return emit_endif( emit
, insn
);
3041 case TGSI_OPCODE_BGNLOOP
:
3042 return emit_bgnloop( emit
, insn
);
3043 case TGSI_OPCODE_ENDLOOP
:
3044 return emit_endloop( emit
, insn
);
3045 case TGSI_OPCODE_BRK
:
3046 return emit_brk( emit
, insn
);
3048 case TGSI_OPCODE_XPD
:
3049 return emit_xpd( emit
, insn
);
3051 case TGSI_OPCODE_KILL
:
3052 return emit_kill( emit
, insn
);
3054 case TGSI_OPCODE_DST
:
3055 return emit_dst_insn( emit
, insn
);
3057 case TGSI_OPCODE_LIT
:
3058 return emit_lit( emit
, insn
);
3060 case TGSI_OPCODE_LRP
:
3061 return emit_lrp( emit
, insn
);
3063 case TGSI_OPCODE_SSG
:
3064 return emit_ssg( emit
, insn
);
3068 unsigned opcode
= translate_opcode(insn
->Instruction
.Opcode
);
3070 if (opcode
== SVGA3DOP_LAST_INST
)
3073 if (!emit_simple_instruction( emit
, opcode
, insn
))
3083 * Translate/emit a TGSI IMMEDIATE declaration.
3084 * An immediate vector is a constant that's hard-coded into the shader.
3087 svga_emit_immediate(struct svga_shader_emitter
*emit
,
3088 const struct tgsi_full_immediate
*imm
)
3090 static const float id
[4] = {0,0,0,1};
3094 assert(1 <= imm
->Immediate
.NrTokens
&& imm
->Immediate
.NrTokens
<= 5);
3095 for (i
= 0; i
< imm
->Immediate
.NrTokens
- 1; i
++) {
3096 float f
= imm
->u
[i
].Float
;
3097 value
[i
] = util_is_inf_or_nan(f
) ? 0.0f
: f
;
3100 /* If the immediate has less than four values, fill in the remaining
3101 * positions from id={0,0,0,1}.
3103 for ( ; i
< 4; i
++ )
3106 return emit_def_const( emit
, SVGA3D_CONST_TYPE_FLOAT
,
3107 emit
->imm_start
+ emit
->internal_imm_count
++,
3108 value
[0], value
[1], value
[2], value
[3]);
3113 make_immediate(struct svga_shader_emitter
*emit
,
3114 float a
, float b
, float c
, float d
,
3115 struct src_register
*out
)
3117 unsigned idx
= emit
->nr_hw_float_const
++;
3119 if (!emit_def_const( emit
, SVGA3D_CONST_TYPE_FLOAT
,
3123 *out
= src_register( SVGA3DREG_CONST
, idx
);
3130 * Emit special VS instructions at top of shader.
3133 emit_vs_preamble(struct svga_shader_emitter
*emit
)
3135 if (!emit
->key
.vkey
.need_prescale
) {
3136 if (!make_immediate( emit
, 0, 0, .5, .5,
3146 * Emit special PS instructions at top of shader.
3149 emit_ps_preamble(struct svga_shader_emitter
*emit
)
3151 if (emit
->ps_reads_pos
&& emit
->info
.reads_z
) {
3153 * Assemble the position from various bits of inputs. Depth and W are
3154 * passed in a texcoord this is due to D3D's vPos not hold Z or W.
3155 * Also fixup the perspective interpolation.
3157 * temp_pos.xy = vPos.xy
3158 * temp_pos.w = rcp(texcoord1.w);
3159 * temp_pos.z = texcoord1.z * temp_pos.w;
3161 if (!submit_op1( emit
,
3162 inst_token(SVGA3DOP_MOV
),
3163 writemask( emit
->ps_temp_pos
, TGSI_WRITEMASK_XY
),
3164 emit
->ps_true_pos
))
3167 if (!submit_op1( emit
,
3168 inst_token(SVGA3DOP_RCP
),
3169 writemask( emit
->ps_temp_pos
, TGSI_WRITEMASK_W
),
3170 scalar( emit
->ps_depth_pos
, TGSI_SWIZZLE_W
) ))
3173 if (!submit_op2( emit
,
3174 inst_token(SVGA3DOP_MUL
),
3175 writemask( emit
->ps_temp_pos
, TGSI_WRITEMASK_Z
),
3176 scalar( emit
->ps_depth_pos
, TGSI_SWIZZLE_Z
),
3177 scalar( src(emit
->ps_temp_pos
), TGSI_SWIZZLE_W
) ))
3186 * Emit special PS instructions at end of shader.
3189 emit_ps_postamble(struct svga_shader_emitter
*emit
)
3193 /* PS oDepth is incredibly fragile and it's very hard to catch the
3194 * types of usage that break it during shader emit. Easier just to
3195 * redirect the main program to a temporary and then only touch
3196 * oDepth with a hand-crafted MOV below.
3198 if (SVGA3dShaderGetRegType(emit
->true_pos
.value
) != 0) {
3199 if (!submit_op1( emit
,
3200 inst_token(SVGA3DOP_MOV
),
3202 scalar(src(emit
->temp_pos
), TGSI_SWIZZLE_Z
) ))
3206 for (i
= 0; i
< PIPE_MAX_COLOR_BUFS
; i
++) {
3207 if (SVGA3dShaderGetRegType(emit
->true_color_output
[i
].value
) != 0) {
3208 /* Potentially override output colors with white for XOR
3209 * logicop workaround.
3211 if (emit
->unit
== PIPE_SHADER_FRAGMENT
&&
3212 emit
->key
.fkey
.white_fragments
) {
3213 struct src_register one
= get_one_immediate(emit
);
3215 if (!submit_op1( emit
,
3216 inst_token(SVGA3DOP_MOV
),
3217 emit
->true_color_output
[i
],
3221 else if (emit
->unit
== PIPE_SHADER_FRAGMENT
&&
3222 i
< emit
->key
.fkey
.write_color0_to_n_cbufs
) {
3223 /* Write temp color output [0] to true output [i] */
3224 if (!submit_op1(emit
, inst_token(SVGA3DOP_MOV
),
3225 emit
->true_color_output
[i
],
3226 src(emit
->temp_color_output
[0]))) {
3231 if (!submit_op1( emit
,
3232 inst_token(SVGA3DOP_MOV
),
3233 emit
->true_color_output
[i
],
3234 src(emit
->temp_color_output
[i
]) ))
3245 * Emit special VS instructions at end of shader.
3248 emit_vs_postamble(struct svga_shader_emitter
*emit
)
3250 /* PSIZ output is incredibly fragile and it's very hard to catch
3251 * the types of usage that break it during shader emit. Easier
3252 * just to redirect the main program to a temporary and then only
3253 * touch PSIZ with a hand-crafted MOV below.
3255 if (SVGA3dShaderGetRegType(emit
->true_psiz
.value
) != 0) {
3256 if (!submit_op1( emit
,
3257 inst_token(SVGA3DOP_MOV
),
3259 scalar(src(emit
->temp_psiz
), TGSI_SWIZZLE_X
) ))
3263 /* Need to perform various manipulations on vertex position to cope
3264 * with the different GL and D3D clip spaces.
3266 if (emit
->key
.vkey
.need_prescale
) {
3267 SVGA3dShaderDestToken temp_pos
= emit
->temp_pos
;
3268 SVGA3dShaderDestToken depth
= emit
->depth_pos
;
3269 SVGA3dShaderDestToken pos
= emit
->true_pos
;
3270 unsigned offset
= emit
->info
.file_max
[TGSI_FILE_CONSTANT
] + 1;
3271 struct src_register prescale_scale
= src_register( SVGA3DREG_CONST
,
3273 struct src_register prescale_trans
= src_register( SVGA3DREG_CONST
,
3276 if (!submit_op1( emit
,
3277 inst_token(SVGA3DOP_MOV
),
3278 writemask(depth
, TGSI_WRITEMASK_W
),
3279 scalar(src(temp_pos
), TGSI_SWIZZLE_W
) ))
3282 /* MUL temp_pos.xyz, temp_pos, prescale.scale
3283 * MAD result.position, temp_pos.wwww, prescale.trans, temp_pos
3284 * --> Note that prescale.trans.w == 0
3286 if (!submit_op2( emit
,
3287 inst_token(SVGA3DOP_MUL
),
3288 writemask(temp_pos
, TGSI_WRITEMASK_XYZ
),
3293 if (!submit_op3( emit
,
3294 inst_token(SVGA3DOP_MAD
),
3296 swizzle(src(temp_pos
), 3, 3, 3, 3),
3301 /* Also write to depth value */
3302 if (!submit_op3( emit
,
3303 inst_token(SVGA3DOP_MAD
),
3304 writemask(depth
, TGSI_WRITEMASK_Z
),
3305 swizzle(src(temp_pos
), 3, 3, 3, 3),
3311 SVGA3dShaderDestToken temp_pos
= emit
->temp_pos
;
3312 SVGA3dShaderDestToken depth
= emit
->depth_pos
;
3313 SVGA3dShaderDestToken pos
= emit
->true_pos
;
3314 struct src_register imm_0055
= emit
->imm_0055
;
3316 /* Adjust GL clipping coordinate space to hardware (D3D-style):
3318 * DP4 temp_pos.z, {0,0,.5,.5}, temp_pos
3319 * MOV result.position, temp_pos
3321 if (!submit_op2( emit
,
3322 inst_token(SVGA3DOP_DP4
),
3323 writemask(temp_pos
, TGSI_WRITEMASK_Z
),
3328 if (!submit_op1( emit
,
3329 inst_token(SVGA3DOP_MOV
),
3334 /* Move the manipulated depth into the extra texcoord reg */
3335 if (!submit_op1( emit
,
3336 inst_token(SVGA3DOP_MOV
),
3337 writemask(depth
, TGSI_WRITEMASK_ZW
),
3347 * For the pixel shader: emit the code which chooses the front
3348 * or back face color depending on triangle orientation.
3349 * This happens at the top of the fragment shader.
3352 * 1: COLOR = FrontColor;
3354 * 3: COLOR = BackColor;
3358 emit_light_twoside(struct svga_shader_emitter
*emit
)
3360 struct src_register vface
, zero
;
3361 struct src_register front
[2];
3362 struct src_register back
[2];
3363 SVGA3dShaderDestToken color
[2];
3364 int count
= emit
->internal_color_count
;
3366 SVGA3dShaderInstToken if_token
;
3371 vface
= get_vface( emit
);
3372 zero
= get_zero_immediate(emit
);
3374 /* Can't use get_temp() to allocate the color reg as such
3375 * temporaries will be reclaimed after each instruction by the call
3376 * to reset_temp_regs().
3378 for (i
= 0; i
< count
; i
++) {
3379 color
[i
] = dst_register( SVGA3DREG_TEMP
, emit
->nr_hw_temp
++ );
3380 front
[i
] = emit
->input_map
[emit
->internal_color_idx
[i
]];
3382 /* Back is always the next input:
3385 back
[i
].base
.num
= front
[i
].base
.num
+ 1;
3387 /* Reassign the input_map to the actual front-face color:
3389 emit
->input_map
[emit
->internal_color_idx
[i
]] = src(color
[i
]);
3392 if_token
= inst_token( SVGA3DOP_IFC
);
3394 if (emit
->key
.fkey
.front_ccw
)
3395 if_token
.control
= SVGA3DOPCOMP_LT
;
3397 if_token
.control
= SVGA3DOPCOMP_GT
;
3399 if (!(emit_instruction( emit
, if_token
) &&
3400 emit_src( emit
, vface
) &&
3401 emit_src( emit
, zero
) ))
3404 for (i
= 0; i
< count
; i
++) {
3405 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), color
[i
], front
[i
] ))
3409 if (!(emit_instruction( emit
, inst_token( SVGA3DOP_ELSE
))))
3412 for (i
= 0; i
< count
; i
++) {
3413 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), color
[i
], back
[i
] ))
3417 if (!emit_instruction( emit
, inst_token( SVGA3DOP_ENDIF
) ))
3425 * Emit special setup code for the front/back face register in the FS.
3426 * 0: SETP_GT TEMP, VFACE, 0
3427 * where TEMP is a fake frontface register
3430 emit_frontface(struct svga_shader_emitter
*emit
)
3432 struct src_register vface
;
3433 SVGA3dShaderDestToken temp
;
3434 struct src_register pass
, fail
;
3436 vface
= get_vface( emit
);
3438 /* Can't use get_temp() to allocate the fake frontface reg as such
3439 * temporaries will be reclaimed after each instruction by the call
3440 * to reset_temp_regs().
3442 temp
= dst_register( SVGA3DREG_TEMP
,
3443 emit
->nr_hw_temp
++ );
3445 if (emit
->key
.fkey
.front_ccw
) {
3446 pass
= get_zero_immediate(emit
);
3447 fail
= get_one_immediate(emit
);
3449 pass
= get_one_immediate(emit
);
3450 fail
= get_zero_immediate(emit
);
3453 if (!emit_conditional(emit
, PIPE_FUNC_GREATER
,
3454 temp
, vface
, get_zero_immediate(emit
),
3458 /* Reassign the input_map to the actual front-face color:
3460 emit
->input_map
[emit
->internal_frontface_idx
] = src(temp
);
3467 * Emit code to invert the T component of the incoming texture coordinate.
3468 * This is used for drawing point sprites when
3469 * pipe_rasterizer_state::sprite_coord_mode == PIPE_SPRITE_COORD_LOWER_LEFT.
3472 emit_inverted_texcoords(struct svga_shader_emitter
*emit
)
3474 unsigned inverted_texcoords
= emit
->inverted_texcoords
;
3476 while (inverted_texcoords
) {
3477 const unsigned unit
= ffs(inverted_texcoords
) - 1;
3479 assert(emit
->inverted_texcoords
& (1 << unit
));
3481 assert(unit
< Elements(emit
->ps_true_texcoord
));
3483 assert(unit
< Elements(emit
->ps_inverted_texcoord_input
));
3485 assert(emit
->ps_inverted_texcoord_input
[unit
]
3486 < Elements(emit
->input_map
));
3488 /* inverted = coord * (1, -1, 1, 1) + (0, 1, 0, 0) */
3489 if (!submit_op3(emit
,
3490 inst_token(SVGA3DOP_MAD
),
3491 dst(emit
->ps_inverted_texcoord
[unit
]),
3492 emit
->ps_true_texcoord
[unit
],
3493 get_immediate(emit
, 1.0f
, -1.0f
, 1.0f
, 1.0f
),
3494 get_immediate(emit
, 0.0f
, 1.0f
, 0.0f
, 0.0f
)))
3497 /* Reassign the input_map entry to the new texcoord register */
3498 emit
->input_map
[emit
->ps_inverted_texcoord_input
[unit
]] =
3499 emit
->ps_inverted_texcoord
[unit
];
3501 inverted_texcoords
&= ~(1 << unit
);
3509 * Determine if we need to create the "common" immediate value which is
3510 * used for generating useful vector constants such as {0,0,0,0} and
3512 * We could just do this all the time except that we want to conserve
3513 * registers whenever possible.
3516 needs_to_create_common_immediate(const struct svga_shader_emitter
*emit
)
3520 if (emit
->unit
== PIPE_SHADER_FRAGMENT
) {
3521 if (emit
->key
.fkey
.light_twoside
)
3524 if (emit
->key
.fkey
.white_fragments
)
3527 if (emit
->emit_frontface
)
3530 if (emit
->info
.opcode_count
[TGSI_OPCODE_DST
] >= 1 ||
3531 emit
->info
.opcode_count
[TGSI_OPCODE_SSG
] >= 1 ||
3532 emit
->info
.opcode_count
[TGSI_OPCODE_LIT
] >= 1)
3535 if (emit
->inverted_texcoords
)
3538 /* look for any PIPE_SWIZZLE_ZERO/ONE terms */
3539 for (i
= 0; i
< emit
->key
.fkey
.num_textures
; i
++) {
3540 if (emit
->key
.fkey
.tex
[i
].swizzle_r
> PIPE_SWIZZLE_ALPHA
||
3541 emit
->key
.fkey
.tex
[i
].swizzle_g
> PIPE_SWIZZLE_ALPHA
||
3542 emit
->key
.fkey
.tex
[i
].swizzle_b
> PIPE_SWIZZLE_ALPHA
||
3543 emit
->key
.fkey
.tex
[i
].swizzle_a
> PIPE_SWIZZLE_ALPHA
)
3547 for (i
= 0; i
< emit
->key
.fkey
.num_textures
; i
++) {
3548 if (emit
->key
.fkey
.tex
[i
].compare_mode
3549 == PIPE_TEX_COMPARE_R_TO_TEXTURE
)
3554 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
3555 if (emit
->info
.opcode_count
[TGSI_OPCODE_CMP
] >= 1)
3559 if (emit
->info
.opcode_count
[TGSI_OPCODE_IF
] >= 1 ||
3560 emit
->info
.opcode_count
[TGSI_OPCODE_BGNLOOP
] >= 1 ||
3561 emit
->info
.opcode_count
[TGSI_OPCODE_DDX
] >= 1 ||
3562 emit
->info
.opcode_count
[TGSI_OPCODE_DDY
] >= 1 ||
3563 emit
->info
.opcode_count
[TGSI_OPCODE_ROUND
] >= 1 ||
3564 emit
->info
.opcode_count
[TGSI_OPCODE_SGE
] >= 1 ||
3565 emit
->info
.opcode_count
[TGSI_OPCODE_SGT
] >= 1 ||
3566 emit
->info
.opcode_count
[TGSI_OPCODE_SLE
] >= 1 ||
3567 emit
->info
.opcode_count
[TGSI_OPCODE_SLT
] >= 1 ||
3568 emit
->info
.opcode_count
[TGSI_OPCODE_SNE
] >= 1 ||
3569 emit
->info
.opcode_count
[TGSI_OPCODE_SEQ
] >= 1 ||
3570 emit
->info
.opcode_count
[TGSI_OPCODE_EXP
] >= 1 ||
3571 emit
->info
.opcode_count
[TGSI_OPCODE_LOG
] >= 1 ||
3572 emit
->info
.opcode_count
[TGSI_OPCODE_XPD
] >= 1 ||
3573 emit
->info
.opcode_count
[TGSI_OPCODE_KILL
] >= 1)
3581 * Do we need to create a looping constant?
3584 needs_to_create_loop_const(const struct svga_shader_emitter
*emit
)
3586 return (emit
->info
.opcode_count
[TGSI_OPCODE_BGNLOOP
] >= 1);
3591 needs_to_create_arl_consts(const struct svga_shader_emitter
*emit
)
3593 return (emit
->num_arl_consts
> 0);
3598 pre_parse_add_indirect( struct svga_shader_emitter
*emit
,
3599 int num
, int current_arl
)
3604 for (i
= 0; i
< emit
->num_arl_consts
; ++i
) {
3605 if (emit
->arl_consts
[i
].arl_num
== current_arl
)
3609 if (emit
->num_arl_consts
== i
) {
3610 ++emit
->num_arl_consts
;
3612 emit
->arl_consts
[i
].number
= (emit
->arl_consts
[i
].number
> num
) ?
3614 emit
->arl_consts
[i
].number
;
3615 emit
->arl_consts
[i
].arl_num
= current_arl
;
3621 pre_parse_instruction( struct svga_shader_emitter
*emit
,
3622 const struct tgsi_full_instruction
*insn
,
3625 if (insn
->Src
[0].Register
.Indirect
&&
3626 insn
->Src
[0].Indirect
.File
== TGSI_FILE_ADDRESS
) {
3627 const struct tgsi_full_src_register
*reg
= &insn
->Src
[0];
3628 if (reg
->Register
.Index
< 0) {
3629 pre_parse_add_indirect(emit
, reg
->Register
.Index
, current_arl
);
3633 if (insn
->Src
[1].Register
.Indirect
&&
3634 insn
->Src
[1].Indirect
.File
== TGSI_FILE_ADDRESS
) {
3635 const struct tgsi_full_src_register
*reg
= &insn
->Src
[1];
3636 if (reg
->Register
.Index
< 0) {
3637 pre_parse_add_indirect(emit
, reg
->Register
.Index
, current_arl
);
3641 if (insn
->Src
[2].Register
.Indirect
&&
3642 insn
->Src
[2].Indirect
.File
== TGSI_FILE_ADDRESS
) {
3643 const struct tgsi_full_src_register
*reg
= &insn
->Src
[2];
3644 if (reg
->Register
.Index
< 0) {
3645 pre_parse_add_indirect(emit
, reg
->Register
.Index
, current_arl
);
3654 pre_parse_tokens( struct svga_shader_emitter
*emit
,
3655 const struct tgsi_token
*tokens
)
3657 struct tgsi_parse_context parse
;
3658 int current_arl
= 0;
3660 tgsi_parse_init( &parse
, tokens
);
3662 while (!tgsi_parse_end_of_tokens( &parse
)) {
3663 tgsi_parse_token( &parse
);
3664 switch (parse
.FullToken
.Token
.Type
) {
3665 case TGSI_TOKEN_TYPE_IMMEDIATE
:
3666 case TGSI_TOKEN_TYPE_DECLARATION
:
3668 case TGSI_TOKEN_TYPE_INSTRUCTION
:
3669 if (parse
.FullToken
.FullInstruction
.Instruction
.Opcode
==
3673 if (!pre_parse_instruction( emit
, &parse
.FullToken
.FullInstruction
,
3687 svga_shader_emit_helpers(struct svga_shader_emitter
*emit
)
3689 if (needs_to_create_common_immediate( emit
)) {
3690 create_common_immediate( emit
);
3692 if (needs_to_create_loop_const( emit
)) {
3693 create_loop_const( emit
);
3695 if (needs_to_create_arl_consts( emit
)) {
3696 create_arl_consts( emit
);
3699 if (emit
->unit
== PIPE_SHADER_FRAGMENT
) {
3700 if (!emit_ps_preamble( emit
))
3703 if (emit
->key
.fkey
.light_twoside
) {
3704 if (!emit_light_twoside( emit
))
3707 if (emit
->emit_frontface
) {
3708 if (!emit_frontface( emit
))
3711 if (emit
->inverted_texcoords
) {
3712 if (!emit_inverted_texcoords( emit
))
3722 * This is the main entrypoint into the TGSI instruction translater.
3723 * Translate TGSI shader tokens into an SVGA shader.
3726 svga_shader_emit_instructions(struct svga_shader_emitter
*emit
,
3727 const struct tgsi_token
*tokens
)
3729 struct tgsi_parse_context parse
;
3731 boolean helpers_emitted
= FALSE
;
3732 unsigned line_nr
= 0;
3734 tgsi_parse_init( &parse
, tokens
);
3735 emit
->internal_imm_count
= 0;
3737 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
3738 ret
= emit_vs_preamble( emit
);
3743 pre_parse_tokens(emit
, tokens
);
3745 while (!tgsi_parse_end_of_tokens( &parse
)) {
3746 tgsi_parse_token( &parse
);
3748 switch (parse
.FullToken
.Token
.Type
) {
3749 case TGSI_TOKEN_TYPE_IMMEDIATE
:
3750 ret
= svga_emit_immediate( emit
, &parse
.FullToken
.FullImmediate
);
3755 case TGSI_TOKEN_TYPE_DECLARATION
:
3756 ret
= svga_translate_decl_sm30( emit
, &parse
.FullToken
.FullDeclaration
);
3761 case TGSI_TOKEN_TYPE_INSTRUCTION
:
3762 if (!helpers_emitted
) {
3763 if (!svga_shader_emit_helpers( emit
))
3765 helpers_emitted
= TRUE
;
3767 ret
= svga_emit_instruction( emit
,
3769 &parse
.FullToken
.FullInstruction
);
3777 reset_temp_regs( emit
);
3780 /* Need to terminate the current subroutine. Note that the
3781 * hardware doesn't tolerate shaders without sub-routines
3782 * terminating with RET+END.
3784 if (!emit
->in_main_func
) {
3785 ret
= emit_instruction( emit
, inst_token( SVGA3DOP_RET
) );
3790 assert(emit
->dynamic_branching_level
== 0);
3792 /* Need to terminate the whole shader:
3794 ret
= emit_instruction( emit
, inst_token( SVGA3DOP_END
) );
3799 tgsi_parse_free( &parse
);