1 /**********************************************************
2 * Copyright 2008-2009 VMware, Inc. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 **********************************************************/
27 #include "pipe/p_shader_tokens.h"
28 #include "tgsi/tgsi_dump.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/u_memory.h"
31 #include "util/u_math.h"
32 #include "util/u_pstipple.h"
34 #include "svga_tgsi_emit.h"
35 #include "svga_context.h"
38 static boolean
emit_vs_postamble( struct svga_shader_emitter
*emit
);
39 static boolean
emit_ps_postamble( struct svga_shader_emitter
*emit
);
43 translate_opcode(uint opcode
)
46 case TGSI_OPCODE_ABS
: return SVGA3DOP_ABS
;
47 case TGSI_OPCODE_ADD
: return SVGA3DOP_ADD
;
48 case TGSI_OPCODE_DP2A
: return SVGA3DOP_DP2ADD
;
49 case TGSI_OPCODE_DP3
: return SVGA3DOP_DP3
;
50 case TGSI_OPCODE_DP4
: return SVGA3DOP_DP4
;
51 case TGSI_OPCODE_FRC
: return SVGA3DOP_FRC
;
52 case TGSI_OPCODE_MAD
: return SVGA3DOP_MAD
;
53 case TGSI_OPCODE_MAX
: return SVGA3DOP_MAX
;
54 case TGSI_OPCODE_MIN
: return SVGA3DOP_MIN
;
55 case TGSI_OPCODE_MOV
: return SVGA3DOP_MOV
;
56 case TGSI_OPCODE_MUL
: return SVGA3DOP_MUL
;
57 case TGSI_OPCODE_NOP
: return SVGA3DOP_NOP
;
59 assert(!"svga: unexpected opcode in translate_opcode()");
60 return SVGA3DOP_LAST_INST
;
66 translate_file(unsigned file
)
69 case TGSI_FILE_TEMPORARY
: return SVGA3DREG_TEMP
;
70 case TGSI_FILE_INPUT
: return SVGA3DREG_INPUT
;
71 case TGSI_FILE_OUTPUT
: return SVGA3DREG_OUTPUT
; /* VS3.0+ only */
72 case TGSI_FILE_IMMEDIATE
: return SVGA3DREG_CONST
;
73 case TGSI_FILE_CONSTANT
: return SVGA3DREG_CONST
;
74 case TGSI_FILE_SAMPLER
: return SVGA3DREG_SAMPLER
;
75 case TGSI_FILE_ADDRESS
: return SVGA3DREG_ADDR
;
77 assert(!"svga: unexpected register file in translate_file()");
78 return SVGA3DREG_TEMP
;
84 * Translate a TGSI destination register to an SVGA3DShaderDestToken.
85 * \param insn the TGSI instruction
86 * \param idx which TGSI dest register to translate (usually (always?) zero)
88 static SVGA3dShaderDestToken
89 translate_dst_register( struct svga_shader_emitter
*emit
,
90 const struct tgsi_full_instruction
*insn
,
93 const struct tgsi_full_dst_register
*reg
= &insn
->Dst
[idx
];
94 SVGA3dShaderDestToken dest
;
96 switch (reg
->Register
.File
) {
97 case TGSI_FILE_OUTPUT
:
98 /* Output registers encode semantic information in their name.
99 * Need to lookup a table built at decl time:
101 dest
= emit
->output_map
[reg
->Register
.Index
];
102 emit
->num_output_writes
++;
107 unsigned index
= reg
->Register
.Index
;
108 assert(index
< SVGA3D_TEMPREG_MAX
);
109 index
= MIN2(index
, SVGA3D_TEMPREG_MAX
- 1);
110 dest
= dst_register(translate_file(reg
->Register
.File
), index
);
115 if (reg
->Register
.Indirect
) {
116 debug_warning("Indirect indexing of dest registers is not supported!\n");
119 dest
.mask
= reg
->Register
.WriteMask
;
122 if (insn
->Instruction
.Saturate
)
123 dest
.dstMod
= SVGA3DDSTMOD_SATURATE
;
130 * Apply a swizzle to a src_register, returning a new src_register
131 * Ex: swizzle(SRC.ZZYY, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_X, SWIZZLE_Y)
132 * would return SRC.YYZZ
134 static struct src_register
135 swizzle(struct src_register src
,
136 unsigned x
, unsigned y
, unsigned z
, unsigned w
)
142 x
= (src
.base
.swizzle
>> (x
* 2)) & 0x3;
143 y
= (src
.base
.swizzle
>> (y
* 2)) & 0x3;
144 z
= (src
.base
.swizzle
>> (z
* 2)) & 0x3;
145 w
= (src
.base
.swizzle
>> (w
* 2)) & 0x3;
147 src
.base
.swizzle
= TRANSLATE_SWIZZLE(x
, y
, z
, w
);
154 * Apply a "scalar" swizzle to a src_register returning a new
155 * src_register where all the swizzle terms are the same.
156 * Ex: scalar(SRC.WZYX, SWIZZLE_Y) would return SRC.ZZZZ
158 static struct src_register
159 scalar(struct src_register src
, unsigned comp
)
162 return swizzle( src
, comp
, comp
, comp
, comp
);
167 svga_arl_needs_adjustment( const struct svga_shader_emitter
*emit
)
171 for (i
= 0; i
< emit
->num_arl_consts
; ++i
) {
172 if (emit
->arl_consts
[i
].arl_num
== emit
->current_arl
)
180 svga_arl_adjustment( const struct svga_shader_emitter
*emit
)
184 for (i
= 0; i
< emit
->num_arl_consts
; ++i
) {
185 if (emit
->arl_consts
[i
].arl_num
== emit
->current_arl
)
186 return emit
->arl_consts
[i
].number
;
193 * Translate a TGSI src register to a src_register.
195 static struct src_register
196 translate_src_register( const struct svga_shader_emitter
*emit
,
197 const struct tgsi_full_src_register
*reg
)
199 struct src_register src
;
201 switch (reg
->Register
.File
) {
202 case TGSI_FILE_INPUT
:
203 /* Input registers are referred to by their semantic name rather
204 * than by index. Use the mapping build up from the decls:
206 src
= emit
->input_map
[reg
->Register
.Index
];
209 case TGSI_FILE_IMMEDIATE
:
210 /* Immediates are appended after TGSI constants in the D3D
213 src
= src_register( translate_file( reg
->Register
.File
),
214 reg
->Register
.Index
+ emit
->imm_start
);
218 src
= src_register( translate_file( reg
->Register
.File
),
219 reg
->Register
.Index
);
223 /* Indirect addressing.
225 if (reg
->Register
.Indirect
) {
226 if (emit
->unit
== PIPE_SHADER_FRAGMENT
) {
227 /* Pixel shaders have only loop registers for relative
228 * addressing into inputs. Ignore the redundant address
229 * register, the contents of aL should be in sync with it.
231 if (reg
->Register
.File
== TGSI_FILE_INPUT
) {
232 src
.base
.relAddr
= 1;
233 src
.indirect
= src_token(SVGA3DREG_LOOP
, 0);
237 /* Constant buffers only.
239 if (reg
->Register
.File
== TGSI_FILE_CONSTANT
) {
240 /* we shift the offset towards the minimum */
241 if (svga_arl_needs_adjustment( emit
)) {
242 src
.base
.num
-= svga_arl_adjustment( emit
);
244 src
.base
.relAddr
= 1;
246 /* Not really sure what should go in the second token:
248 src
.indirect
= src_token( SVGA3DREG_ADDR
,
249 reg
->Indirect
.Index
);
251 src
.indirect
.swizzle
= SWIZZLE_XXXX
;
257 reg
->Register
.SwizzleX
,
258 reg
->Register
.SwizzleY
,
259 reg
->Register
.SwizzleZ
,
260 reg
->Register
.SwizzleW
);
262 /* src.mod isn't a bitfield, unfortunately:
263 * See tgsi_util_get_full_src_register_sign_mode for implementation details.
265 if (reg
->Register
.Absolute
) {
266 if (reg
->Register
.Negate
)
267 src
.base
.srcMod
= SVGA3DSRCMOD_ABSNEG
;
269 src
.base
.srcMod
= SVGA3DSRCMOD_ABS
;
272 if (reg
->Register
.Negate
)
273 src
.base
.srcMod
= SVGA3DSRCMOD_NEG
;
275 src
.base
.srcMod
= SVGA3DSRCMOD_NONE
;
283 * Get a temporary register.
284 * Note: if we exceed the temporary register limit we just use
285 * register SVGA3D_TEMPREG_MAX - 1.
287 static SVGA3dShaderDestToken
288 get_temp( struct svga_shader_emitter
*emit
)
290 int i
= emit
->nr_hw_temp
+ emit
->internal_temp_count
++;
291 if (i
>= SVGA3D_TEMPREG_MAX
) {
292 debug_warn_once("svga: Too many temporary registers used in shader\n");
293 i
= SVGA3D_TEMPREG_MAX
- 1;
295 return dst_register( SVGA3DREG_TEMP
, i
);
300 * Release a single temp. Currently only effective if it was the last
301 * allocated temp, otherwise release will be delayed until the next
302 * call to reset_temp_regs().
305 release_temp( struct svga_shader_emitter
*emit
,
306 SVGA3dShaderDestToken temp
)
308 if (temp
.num
== emit
->internal_temp_count
- 1)
309 emit
->internal_temp_count
--;
317 reset_temp_regs(struct svga_shader_emitter
*emit
)
319 emit
->internal_temp_count
= 0;
323 /** Emit bytecode for a src_register */
325 emit_src(struct svga_shader_emitter
*emit
, const struct src_register src
)
327 if (src
.base
.relAddr
) {
328 assert(src
.base
.reserved0
);
329 assert(src
.indirect
.reserved0
);
330 return (svga_shader_emit_dword( emit
, src
.base
.value
) &&
331 svga_shader_emit_dword( emit
, src
.indirect
.value
));
334 assert(src
.base
.reserved0
);
335 return svga_shader_emit_dword( emit
, src
.base
.value
);
340 /** Emit bytecode for a dst_register */
342 emit_dst(struct svga_shader_emitter
*emit
, SVGA3dShaderDestToken dest
)
344 assert(dest
.reserved0
);
346 return svga_shader_emit_dword( emit
, dest
.value
);
350 /** Emit bytecode for a 1-operand instruction */
352 emit_op1(struct svga_shader_emitter
*emit
,
353 SVGA3dShaderInstToken inst
,
354 SVGA3dShaderDestToken dest
,
355 struct src_register src0
)
357 return (emit_instruction(emit
, inst
) &&
358 emit_dst(emit
, dest
) &&
359 emit_src(emit
, src0
));
363 /** Emit bytecode for a 2-operand instruction */
365 emit_op2(struct svga_shader_emitter
*emit
,
366 SVGA3dShaderInstToken inst
,
367 SVGA3dShaderDestToken dest
,
368 struct src_register src0
,
369 struct src_register src1
)
371 return (emit_instruction(emit
, inst
) &&
372 emit_dst(emit
, dest
) &&
373 emit_src(emit
, src0
) &&
374 emit_src(emit
, src1
));
378 /** Emit bytecode for a 3-operand instruction */
380 emit_op3(struct svga_shader_emitter
*emit
,
381 SVGA3dShaderInstToken inst
,
382 SVGA3dShaderDestToken dest
,
383 struct src_register src0
,
384 struct src_register src1
,
385 struct src_register src2
)
387 return (emit_instruction(emit
, inst
) &&
388 emit_dst(emit
, dest
) &&
389 emit_src(emit
, src0
) &&
390 emit_src(emit
, src1
) &&
391 emit_src(emit
, src2
));
395 /** Emit bytecode for a 4-operand instruction */
397 emit_op4(struct svga_shader_emitter
*emit
,
398 SVGA3dShaderInstToken inst
,
399 SVGA3dShaderDestToken dest
,
400 struct src_register src0
,
401 struct src_register src1
,
402 struct src_register src2
,
403 struct src_register src3
)
405 return (emit_instruction(emit
, inst
) &&
406 emit_dst(emit
, dest
) &&
407 emit_src(emit
, src0
) &&
408 emit_src(emit
, src1
) &&
409 emit_src(emit
, src2
) &&
410 emit_src(emit
, src3
));
415 * Apply the absolute value modifier to the given src_register, returning
416 * a new src_register.
418 static struct src_register
419 absolute(struct src_register src
)
421 src
.base
.srcMod
= SVGA3DSRCMOD_ABS
;
427 * Apply the negation modifier to the given src_register, returning
428 * a new src_register.
430 static struct src_register
431 negate(struct src_register src
)
433 switch (src
.base
.srcMod
) {
434 case SVGA3DSRCMOD_ABS
:
435 src
.base
.srcMod
= SVGA3DSRCMOD_ABSNEG
;
437 case SVGA3DSRCMOD_ABSNEG
:
438 src
.base
.srcMod
= SVGA3DSRCMOD_ABS
;
440 case SVGA3DSRCMOD_NEG
:
441 src
.base
.srcMod
= SVGA3DSRCMOD_NONE
;
443 case SVGA3DSRCMOD_NONE
:
444 src
.base
.srcMod
= SVGA3DSRCMOD_NEG
;
452 /* Replace the src with the temporary specified in the dst, but copying
453 * only the necessary channels, and preserving the original swizzle (which is
454 * important given that several opcodes have constraints in the allowed
458 emit_repl(struct svga_shader_emitter
*emit
,
459 SVGA3dShaderDestToken dst
,
460 struct src_register
*src0
)
462 unsigned src0_swizzle
;
465 assert(SVGA3dShaderGetRegType(dst
.value
) == SVGA3DREG_TEMP
);
467 src0_swizzle
= src0
->base
.swizzle
;
470 for (chan
= 0; chan
< 4; ++chan
) {
471 unsigned swizzle
= (src0_swizzle
>> (chan
*2)) & 0x3;
472 dst
.mask
|= 1 << swizzle
;
476 src0
->base
.swizzle
= SVGA3DSWIZZLE_NONE
;
478 if (!emit_op1( emit
, inst_token( SVGA3DOP_MOV
), dst
, *src0
))
482 src0
->base
.swizzle
= src0_swizzle
;
489 * Submit/emit an instruction with zero operands.
492 submit_op0(struct svga_shader_emitter
*emit
,
493 SVGA3dShaderInstToken inst
,
494 SVGA3dShaderDestToken dest
)
496 return (emit_instruction( emit
, inst
) &&
497 emit_dst( emit
, dest
));
502 * Submit/emit an instruction with one operand.
505 submit_op1(struct svga_shader_emitter
*emit
,
506 SVGA3dShaderInstToken inst
,
507 SVGA3dShaderDestToken dest
,
508 struct src_register src0
)
510 return emit_op1( emit
, inst
, dest
, src0
);
515 * Submit/emit an instruction with two operands.
517 * SVGA shaders may not refer to >1 constant register in a single
518 * instruction. This function checks for that usage and inserts a
519 * move to temporary if detected.
521 * The same applies to input registers -- at most a single input
522 * register may be read by any instruction.
525 submit_op2(struct svga_shader_emitter
*emit
,
526 SVGA3dShaderInstToken inst
,
527 SVGA3dShaderDestToken dest
,
528 struct src_register src0
,
529 struct src_register src1
)
531 SVGA3dShaderDestToken temp
;
532 SVGA3dShaderRegType type0
, type1
;
533 boolean need_temp
= FALSE
;
536 type0
= SVGA3dShaderGetRegType( src0
.base
.value
);
537 type1
= SVGA3dShaderGetRegType( src1
.base
.value
);
539 if (type0
== SVGA3DREG_CONST
&&
540 type1
== SVGA3DREG_CONST
&&
541 src0
.base
.num
!= src1
.base
.num
)
544 if (type0
== SVGA3DREG_INPUT
&&
545 type1
== SVGA3DREG_INPUT
&&
546 src0
.base
.num
!= src1
.base
.num
)
550 temp
= get_temp( emit
);
552 if (!emit_repl( emit
, temp
, &src0
))
556 if (!emit_op2( emit
, inst
, dest
, src0
, src1
))
560 release_temp( emit
, temp
);
567 * Submit/emit an instruction with three operands.
569 * SVGA shaders may not refer to >1 constant register in a single
570 * instruction. This function checks for that usage and inserts a
571 * move to temporary if detected.
574 submit_op3(struct svga_shader_emitter
*emit
,
575 SVGA3dShaderInstToken inst
,
576 SVGA3dShaderDestToken dest
,
577 struct src_register src0
,
578 struct src_register src1
,
579 struct src_register src2
)
581 SVGA3dShaderDestToken temp0
;
582 SVGA3dShaderDestToken temp1
;
583 boolean need_temp0
= FALSE
;
584 boolean need_temp1
= FALSE
;
585 SVGA3dShaderRegType type0
, type1
, type2
;
589 type0
= SVGA3dShaderGetRegType( src0
.base
.value
);
590 type1
= SVGA3dShaderGetRegType( src1
.base
.value
);
591 type2
= SVGA3dShaderGetRegType( src2
.base
.value
);
593 if (inst
.op
!= SVGA3DOP_SINCOS
) {
594 if (type0
== SVGA3DREG_CONST
&&
595 ((type1
== SVGA3DREG_CONST
&& src0
.base
.num
!= src1
.base
.num
) ||
596 (type2
== SVGA3DREG_CONST
&& src0
.base
.num
!= src2
.base
.num
)))
599 if (type1
== SVGA3DREG_CONST
&&
600 (type2
== SVGA3DREG_CONST
&& src1
.base
.num
!= src2
.base
.num
))
604 if (type0
== SVGA3DREG_INPUT
&&
605 ((type1
== SVGA3DREG_INPUT
&& src0
.base
.num
!= src1
.base
.num
) ||
606 (type2
== SVGA3DREG_INPUT
&& src0
.base
.num
!= src2
.base
.num
)))
609 if (type1
== SVGA3DREG_INPUT
&&
610 (type2
== SVGA3DREG_INPUT
&& src1
.base
.num
!= src2
.base
.num
))
614 temp0
= get_temp( emit
);
616 if (!emit_repl( emit
, temp0
, &src0
))
621 temp1
= get_temp( emit
);
623 if (!emit_repl( emit
, temp1
, &src1
))
627 if (!emit_op3( emit
, inst
, dest
, src0
, src1
, src2
))
631 release_temp( emit
, temp1
);
633 release_temp( emit
, temp0
);
639 * Submit/emit an instruction with four operands.
641 * SVGA shaders may not refer to >1 constant register in a single
642 * instruction. This function checks for that usage and inserts a
643 * move to temporary if detected.
646 submit_op4(struct svga_shader_emitter
*emit
,
647 SVGA3dShaderInstToken inst
,
648 SVGA3dShaderDestToken dest
,
649 struct src_register src0
,
650 struct src_register src1
,
651 struct src_register src2
,
652 struct src_register src3
)
654 SVGA3dShaderDestToken temp0
;
655 SVGA3dShaderDestToken temp3
;
656 boolean need_temp0
= FALSE
;
657 boolean need_temp3
= FALSE
;
658 SVGA3dShaderRegType type0
, type1
, type2
, type3
;
662 type0
= SVGA3dShaderGetRegType( src0
.base
.value
);
663 type1
= SVGA3dShaderGetRegType( src1
.base
.value
);
664 type2
= SVGA3dShaderGetRegType( src2
.base
.value
);
665 type3
= SVGA3dShaderGetRegType( src2
.base
.value
);
667 /* Make life a little easier - this is only used by the TXD
668 * instruction which is guaranteed not to have a constant/input reg
669 * in one slot at least:
671 assert(type1
== SVGA3DREG_SAMPLER
);
673 if (type0
== SVGA3DREG_CONST
&&
674 ((type3
== SVGA3DREG_CONST
&& src0
.base
.num
!= src3
.base
.num
) ||
675 (type2
== SVGA3DREG_CONST
&& src0
.base
.num
!= src2
.base
.num
)))
678 if (type3
== SVGA3DREG_CONST
&&
679 (type2
== SVGA3DREG_CONST
&& src3
.base
.num
!= src2
.base
.num
))
682 if (type0
== SVGA3DREG_INPUT
&&
683 ((type3
== SVGA3DREG_INPUT
&& src0
.base
.num
!= src3
.base
.num
) ||
684 (type2
== SVGA3DREG_INPUT
&& src0
.base
.num
!= src2
.base
.num
)))
687 if (type3
== SVGA3DREG_INPUT
&&
688 (type2
== SVGA3DREG_INPUT
&& src3
.base
.num
!= src2
.base
.num
))
692 temp0
= get_temp( emit
);
694 if (!emit_repl( emit
, temp0
, &src0
))
699 temp3
= get_temp( emit
);
701 if (!emit_repl( emit
, temp3
, &src3
))
705 if (!emit_op4( emit
, inst
, dest
, src0
, src1
, src2
, src3
))
709 release_temp( emit
, temp3
);
711 release_temp( emit
, temp0
);
717 * Do the src and dest registers refer to the same register?
720 alias_src_dst(struct src_register src
,
721 SVGA3dShaderDestToken dst
)
723 if (src
.base
.num
!= dst
.num
)
726 if (SVGA3dShaderGetRegType(dst
.value
) !=
727 SVGA3dShaderGetRegType(src
.base
.value
))
735 * Helper for emitting SVGA immediate values using the SVGA3DOP_DEF[I]
739 emit_def_const(struct svga_shader_emitter
*emit
,
740 SVGA3dShaderConstType type
,
741 unsigned idx
, float a
, float b
, float c
, float d
)
744 SVGA3dShaderInstToken opcode
;
747 case SVGA3D_CONST_TYPE_FLOAT
:
748 opcode
= inst_token( SVGA3DOP_DEF
);
749 def
.dst
= dst_register( SVGA3DREG_CONST
, idx
);
750 def
.constValues
[0] = a
;
751 def
.constValues
[1] = b
;
752 def
.constValues
[2] = c
;
753 def
.constValues
[3] = d
;
755 case SVGA3D_CONST_TYPE_INT
:
756 opcode
= inst_token( SVGA3DOP_DEFI
);
757 def
.dst
= dst_register( SVGA3DREG_CONSTINT
, idx
);
758 def
.constIValues
[0] = (int)a
;
759 def
.constIValues
[1] = (int)b
;
760 def
.constIValues
[2] = (int)c
;
761 def
.constIValues
[3] = (int)d
;
765 opcode
= inst_token( SVGA3DOP_NOP
);
769 if (!emit_instruction(emit
, opcode
) ||
770 !svga_shader_emit_dwords( emit
, def
.values
, Elements(def
.values
)))
778 create_loop_const( struct svga_shader_emitter
*emit
)
780 unsigned idx
= emit
->nr_hw_int_const
++;
782 if (!emit_def_const( emit
, SVGA3D_CONST_TYPE_INT
, idx
,
783 255, /* iteration count */
784 0, /* initial value */
786 0 /* not used, must be 0 */))
789 emit
->loop_const_idx
= idx
;
790 emit
->created_loop_const
= TRUE
;
796 create_arl_consts( struct svga_shader_emitter
*emit
)
800 for (i
= 0; i
< emit
->num_arl_consts
; i
+= 4) {
802 unsigned idx
= emit
->nr_hw_float_const
++;
804 for (j
= 0; j
< 4 && (j
+ i
) < emit
->num_arl_consts
; ++j
) {
805 vals
[j
] = (float) emit
->arl_consts
[i
+ j
].number
;
806 emit
->arl_consts
[i
+ j
].idx
= idx
;
809 emit
->arl_consts
[i
+ 0].swizzle
= TGSI_SWIZZLE_X
;
812 emit
->arl_consts
[i
+ 0].swizzle
= TGSI_SWIZZLE_Y
;
815 emit
->arl_consts
[i
+ 0].swizzle
= TGSI_SWIZZLE_Z
;
818 emit
->arl_consts
[i
+ 0].swizzle
= TGSI_SWIZZLE_W
;
825 if (!emit_def_const( emit
, SVGA3D_CONST_TYPE_FLOAT
, idx
,
836 * Return the register which holds the pixel shaders front/back-
839 static struct src_register
840 get_vface( struct svga_shader_emitter
*emit
)
842 assert(emit
->emitted_vface
);
843 return src_register(SVGA3DREG_MISCTYPE
, SVGA3DMISCREG_FACE
);
848 * Create/emit a "common" constant with values {0, 0.5, -1, 1}.
849 * We can swizzle this to produce other useful constants such as
850 * {0, 0, 0, 0}, {1, 1, 1, 1}, etc.
853 create_common_immediate( struct svga_shader_emitter
*emit
)
855 unsigned idx
= emit
->nr_hw_float_const
++;
857 /* Emit the constant (0, 0.5, -1, 1) and use swizzling to generate
858 * other useful vectors.
860 if (!emit_def_const( emit
, SVGA3D_CONST_TYPE_FLOAT
,
861 idx
, 0.0f
, 0.5f
, -1.0f
, 1.0f
))
863 emit
->common_immediate_idx
[0] = idx
;
866 /* Emit constant {2, 0, 0, 0} (only the 2 is used for now) */
867 if (emit
->key
.vs
.adjust_attrib_range
) {
868 if (!emit_def_const( emit
, SVGA3D_CONST_TYPE_FLOAT
,
869 idx
, 2.0f
, 0.0f
, 0.0f
, 0.0f
))
871 emit
->common_immediate_idx
[1] = idx
;
874 emit
->common_immediate_idx
[1] = -1;
877 emit
->created_common_immediate
= TRUE
;
884 * Return swizzle/position for the given value in the "common" immediate.
886 static inline unsigned
887 common_immediate_swizzle(float value
)
890 return TGSI_SWIZZLE_X
;
891 else if (value
== 0.5f
)
892 return TGSI_SWIZZLE_Y
;
893 else if (value
== -1.0f
)
894 return TGSI_SWIZZLE_Z
;
895 else if (value
== 1.0f
)
896 return TGSI_SWIZZLE_W
;
898 assert(!"illegal value in common_immediate_swizzle");
899 return TGSI_SWIZZLE_X
;
905 * Returns an immediate reg where all the terms are either 0, 1, 2 or 0.5
907 static struct src_register
908 get_immediate(struct svga_shader_emitter
*emit
,
909 float x
, float y
, float z
, float w
)
911 unsigned sx
= common_immediate_swizzle(x
);
912 unsigned sy
= common_immediate_swizzle(y
);
913 unsigned sz
= common_immediate_swizzle(z
);
914 unsigned sw
= common_immediate_swizzle(w
);
915 assert(emit
->created_common_immediate
);
916 assert(emit
->common_immediate_idx
[0] >= 0);
917 return swizzle(src_register(SVGA3DREG_CONST
, emit
->common_immediate_idx
[0]),
923 * returns {0, 0, 0, 0} immediate
925 static struct src_register
926 get_zero_immediate( struct svga_shader_emitter
*emit
)
928 assert(emit
->created_common_immediate
);
929 assert(emit
->common_immediate_idx
[0] >= 0);
930 return swizzle(src_register( SVGA3DREG_CONST
,
931 emit
->common_immediate_idx
[0]),
937 * returns {1, 1, 1, 1} immediate
939 static struct src_register
940 get_one_immediate( struct svga_shader_emitter
*emit
)
942 assert(emit
->created_common_immediate
);
943 assert(emit
->common_immediate_idx
[0] >= 0);
944 return swizzle(src_register( SVGA3DREG_CONST
,
945 emit
->common_immediate_idx
[0]),
951 * returns {0.5, 0.5, 0.5, 0.5} immediate
953 static struct src_register
954 get_half_immediate( struct svga_shader_emitter
*emit
)
956 assert(emit
->created_common_immediate
);
957 assert(emit
->common_immediate_idx
[0] >= 0);
958 return swizzle(src_register(SVGA3DREG_CONST
, emit
->common_immediate_idx
[0]),
964 * returns {2, 2, 2, 2} immediate
966 static struct src_register
967 get_two_immediate( struct svga_shader_emitter
*emit
)
969 /* Note we use the second common immediate here */
970 assert(emit
->created_common_immediate
);
971 assert(emit
->common_immediate_idx
[1] >= 0);
972 return swizzle(src_register( SVGA3DREG_CONST
,
973 emit
->common_immediate_idx
[1]),
979 * returns the loop const
981 static struct src_register
982 get_loop_const( struct svga_shader_emitter
*emit
)
984 assert(emit
->created_loop_const
);
985 assert(emit
->loop_const_idx
>= 0);
986 return src_register( SVGA3DREG_CONSTINT
,
987 emit
->loop_const_idx
);
991 static struct src_register
992 get_fake_arl_const( struct svga_shader_emitter
*emit
)
994 struct src_register reg
;
995 int idx
= 0, swizzle
= 0, i
;
997 for (i
= 0; i
< emit
->num_arl_consts
; ++ i
) {
998 if (emit
->arl_consts
[i
].arl_num
== emit
->current_arl
) {
999 idx
= emit
->arl_consts
[i
].idx
;
1000 swizzle
= emit
->arl_consts
[i
].swizzle
;
1004 reg
= src_register( SVGA3DREG_CONST
, idx
);
1005 return scalar(reg
, swizzle
);
1010 * Return a register which holds the width and height of the texture
1011 * currently bound to the given sampler.
1013 static struct src_register
1014 get_tex_dimensions( struct svga_shader_emitter
*emit
, int sampler_num
)
1017 struct src_register reg
;
1019 /* the width/height indexes start right after constants */
1020 idx
= emit
->key
.tex
[sampler_num
].width_height_idx
+
1021 emit
->info
.file_max
[TGSI_FILE_CONSTANT
] + 1;
1023 reg
= src_register( SVGA3DREG_CONST
, idx
);
1029 emit_fake_arl(struct svga_shader_emitter
*emit
,
1030 const struct tgsi_full_instruction
*insn
)
1032 const struct src_register src0
=
1033 translate_src_register(emit
, &insn
->Src
[0] );
1034 struct src_register src1
= get_fake_arl_const( emit
);
1035 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1036 SVGA3dShaderDestToken tmp
= get_temp( emit
);
1038 if (!submit_op1(emit
, inst_token( SVGA3DOP_MOV
), tmp
, src0
))
1041 if (!submit_op2( emit
, inst_token( SVGA3DOP_ADD
), tmp
, src( tmp
),
1045 /* replicate the original swizzle */
1047 src1
.base
.swizzle
= src0
.base
.swizzle
;
1049 return submit_op1( emit
, inst_token( SVGA3DOP_MOVA
),
1055 emit_if(struct svga_shader_emitter
*emit
,
1056 const struct tgsi_full_instruction
*insn
)
1058 struct src_register src0
=
1059 translate_src_register(emit
, &insn
->Src
[0]);
1060 struct src_register zero
= get_zero_immediate(emit
);
1061 SVGA3dShaderInstToken if_token
= inst_token( SVGA3DOP_IFC
);
1063 if_token
.control
= SVGA3DOPCOMPC_NE
;
1065 if (SVGA3dShaderGetRegType(src0
.base
.value
) == SVGA3DREG_CONST
) {
1067 * Max different constant registers readable per IFC instruction is 1.
1069 SVGA3dShaderDestToken tmp
= get_temp( emit
);
1071 if (!submit_op1(emit
, inst_token( SVGA3DOP_MOV
), tmp
, src0
))
1074 src0
= scalar(src( tmp
), TGSI_SWIZZLE_X
);
1077 emit
->dynamic_branching_level
++;
1079 return (emit_instruction( emit
, if_token
) &&
1080 emit_src( emit
, src0
) &&
1081 emit_src( emit
, zero
) );
1086 emit_else(struct svga_shader_emitter
*emit
,
1087 const struct tgsi_full_instruction
*insn
)
1089 return emit_instruction(emit
, inst_token(SVGA3DOP_ELSE
));
1094 emit_endif(struct svga_shader_emitter
*emit
,
1095 const struct tgsi_full_instruction
*insn
)
1097 emit
->dynamic_branching_level
--;
1099 return emit_instruction(emit
, inst_token(SVGA3DOP_ENDIF
));
1104 * Translate the following TGSI FLR instruction.
1106 * To the following SVGA3D instruction sequence.
1111 emit_floor(struct svga_shader_emitter
*emit
,
1112 const struct tgsi_full_instruction
*insn
)
1114 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1115 const struct src_register src0
=
1116 translate_src_register(emit
, &insn
->Src
[0] );
1117 SVGA3dShaderDestToken temp
= get_temp( emit
);
1120 if (!submit_op1( emit
, inst_token( SVGA3DOP_FRC
), temp
, src0
))
1123 /* SUB DST, SRC, TMP */
1124 if (!submit_op2( emit
, inst_token( SVGA3DOP_ADD
), dst
, src0
,
1125 negate( src( temp
) ) ))
1133 * Translate the following TGSI CEIL instruction.
1135 * To the following SVGA3D instruction sequence.
1140 emit_ceil(struct svga_shader_emitter
*emit
,
1141 const struct tgsi_full_instruction
*insn
)
1143 SVGA3dShaderDestToken dst
= translate_dst_register(emit
, insn
, 0);
1144 const struct src_register src0
=
1145 translate_src_register(emit
, &insn
->Src
[0]);
1146 SVGA3dShaderDestToken temp
= get_temp(emit
);
1149 if (!submit_op1(emit
, inst_token(SVGA3DOP_FRC
), temp
, negate(src0
)))
1152 /* ADD DST, SRC, TMP */
1153 if (!submit_op2(emit
, inst_token(SVGA3DOP_ADD
), dst
, src0
, src(temp
)))
1161 * Translate the following TGSI DIV instruction.
1162 * DIV DST.xy, SRC0, SRC1
1163 * To the following SVGA3D instruction sequence.
1164 * RCP TMP.x, SRC1.xxxx
1165 * RCP TMP.y, SRC1.yyyy
1166 * MUL DST.xy, SRC0, TMP
1169 emit_div(struct svga_shader_emitter
*emit
,
1170 const struct tgsi_full_instruction
*insn
)
1172 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1173 const struct src_register src0
=
1174 translate_src_register(emit
, &insn
->Src
[0] );
1175 const struct src_register src1
=
1176 translate_src_register(emit
, &insn
->Src
[1] );
1177 SVGA3dShaderDestToken temp
= get_temp( emit
);
1180 /* For each enabled element, perform a RCP instruction. Note that
1181 * RCP is scalar in SVGA3D:
1183 for (i
= 0; i
< 4; i
++) {
1184 unsigned channel
= 1 << i
;
1185 if (dst
.mask
& channel
) {
1186 /* RCP TMP.?, SRC1.???? */
1187 if (!submit_op1( emit
, inst_token( SVGA3DOP_RCP
),
1188 writemask(temp
, channel
),
1195 * MUL DST, SRC0, TMP
1197 if (!submit_op2( emit
, inst_token( SVGA3DOP_MUL
), dst
, src0
,
1206 * Translate the following TGSI DP2 instruction.
1207 * DP2 DST, SRC1, SRC2
1208 * To the following SVGA3D instruction sequence.
1209 * MUL TMP, SRC1, SRC2
1210 * ADD DST, TMP.xxxx, TMP.yyyy
1213 emit_dp2(struct svga_shader_emitter
*emit
,
1214 const struct tgsi_full_instruction
*insn
)
1216 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1217 const struct src_register src0
=
1218 translate_src_register(emit
, &insn
->Src
[0]);
1219 const struct src_register src1
=
1220 translate_src_register(emit
, &insn
->Src
[1]);
1221 SVGA3dShaderDestToken temp
= get_temp( emit
);
1222 struct src_register temp_src0
, temp_src1
;
1224 /* MUL TMP, SRC1, SRC2 */
1225 if (!submit_op2( emit
, inst_token( SVGA3DOP_MUL
), temp
, src0
, src1
))
1228 temp_src0
= scalar(src( temp
), TGSI_SWIZZLE_X
);
1229 temp_src1
= scalar(src( temp
), TGSI_SWIZZLE_Y
);
1231 /* ADD DST, TMP.xxxx, TMP.yyyy */
1232 if (!submit_op2( emit
, inst_token( SVGA3DOP_ADD
), dst
,
1233 temp_src0
, temp_src1
))
1241 * Translate the following TGSI DPH instruction.
1242 * DPH DST, SRC1, SRC2
1243 * To the following SVGA3D instruction sequence.
1244 * DP3 TMP, SRC1, SRC2
1245 * ADD DST, TMP, SRC2.wwww
1248 emit_dph(struct svga_shader_emitter
*emit
,
1249 const struct tgsi_full_instruction
*insn
)
1251 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1252 const struct src_register src0
= translate_src_register(
1253 emit
, &insn
->Src
[0] );
1254 struct src_register src1
=
1255 translate_src_register(emit
, &insn
->Src
[1]);
1256 SVGA3dShaderDestToken temp
= get_temp( emit
);
1258 /* DP3 TMP, SRC1, SRC2 */
1259 if (!submit_op2( emit
, inst_token( SVGA3DOP_DP3
), temp
, src0
, src1
))
1262 src1
= scalar(src1
, TGSI_SWIZZLE_W
);
1264 /* ADD DST, TMP, SRC2.wwww */
1265 if (!submit_op2( emit
, inst_token( SVGA3DOP_ADD
), dst
,
1266 src( temp
), src1
))
1274 * Sine / Cosine helper function.
1277 do_emit_sincos(struct svga_shader_emitter
*emit
,
1278 SVGA3dShaderDestToken dst
,
1279 struct src_register src0
)
1281 src0
= scalar(src0
, TGSI_SWIZZLE_X
);
1282 return submit_op1(emit
, inst_token(SVGA3DOP_SINCOS
), dst
, src0
);
1287 * Translate/emit a TGSI SIN, COS or CSC instruction.
1290 emit_sincos(struct svga_shader_emitter
*emit
,
1291 const struct tgsi_full_instruction
*insn
)
1293 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1294 struct src_register src0
= translate_src_register(emit
, &insn
->Src
[0]);
1295 SVGA3dShaderDestToken temp
= get_temp( emit
);
1298 if (!do_emit_sincos(emit
, writemask(temp
, TGSI_WRITEMASK_XY
), src0
))
1302 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), dst
, src( temp
) ))
1310 * Translate TGSI SIN instruction into:
1315 emit_sin(struct svga_shader_emitter
*emit
,
1316 const struct tgsi_full_instruction
*insn
)
1318 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1319 struct src_register src0
=
1320 translate_src_register(emit
, &insn
->Src
[0] );
1321 SVGA3dShaderDestToken temp
= get_temp( emit
);
1324 if (!do_emit_sincos(emit
, writemask(temp
, TGSI_WRITEMASK_Y
), src0
))
1327 src0
= scalar(src( temp
), TGSI_SWIZZLE_Y
);
1329 /* MOV DST TMP.yyyy */
1330 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), dst
, src0
))
1338 * Translate TGSI COS instruction into:
1343 emit_cos(struct svga_shader_emitter
*emit
,
1344 const struct tgsi_full_instruction
*insn
)
1346 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1347 struct src_register src0
=
1348 translate_src_register(emit
, &insn
->Src
[0] );
1349 SVGA3dShaderDestToken temp
= get_temp( emit
);
1352 if (!do_emit_sincos( emit
, writemask(temp
, TGSI_WRITEMASK_X
), src0
))
1355 src0
= scalar(src( temp
), TGSI_SWIZZLE_X
);
1357 /* MOV DST TMP.xxxx */
1358 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), dst
, src0
))
1366 * Translate/emit TGSI SSG (Set Sign: -1, 0, +1) instruction.
1369 emit_ssg(struct svga_shader_emitter
*emit
,
1370 const struct tgsi_full_instruction
*insn
)
1372 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1373 struct src_register src0
=
1374 translate_src_register(emit
, &insn
->Src
[0] );
1375 SVGA3dShaderDestToken temp0
= get_temp( emit
);
1376 SVGA3dShaderDestToken temp1
= get_temp( emit
);
1377 struct src_register zero
, one
;
1379 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
1380 /* SGN DST, SRC0, TMP0, TMP1 */
1381 return submit_op3( emit
, inst_token( SVGA3DOP_SGN
), dst
, src0
,
1382 src( temp0
), src( temp1
) );
1385 one
= get_one_immediate(emit
);
1386 zero
= get_zero_immediate(emit
);
1388 /* CMP TMP0, SRC0, one, zero */
1389 if (!submit_op3( emit
, inst_token( SVGA3DOP_CMP
),
1390 writemask( temp0
, dst
.mask
), src0
, one
, zero
))
1393 /* CMP TMP1, negate(SRC0), negate(one), zero */
1394 if (!submit_op3( emit
, inst_token( SVGA3DOP_CMP
),
1395 writemask( temp1
, dst
.mask
), negate( src0
), negate( one
),
1399 /* ADD DST, TMP0, TMP1 */
1400 return submit_op2( emit
, inst_token( SVGA3DOP_ADD
), dst
, src( temp0
),
1406 * Translate/emit TGSI SUB instruction as:
1407 * ADD DST, SRC0, negate(SRC1)
1410 emit_sub(struct svga_shader_emitter
*emit
,
1411 const struct tgsi_full_instruction
*insn
)
1413 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1414 struct src_register src0
= translate_src_register(
1415 emit
, &insn
->Src
[0] );
1416 struct src_register src1
= translate_src_register(
1417 emit
, &insn
->Src
[1] );
1419 src1
= negate(src1
);
1421 if (!submit_op2( emit
, inst_token( SVGA3DOP_ADD
), dst
,
1430 * Translate/emit KILL_IF instruction (kill if any of X,Y,Z,W are negative).
1433 emit_kill_if(struct svga_shader_emitter
*emit
,
1434 const struct tgsi_full_instruction
*insn
)
1436 const struct tgsi_full_src_register
*reg
= &insn
->Src
[0];
1437 struct src_register src0
, srcIn
;
1438 const boolean special
= (reg
->Register
.Absolute
||
1439 reg
->Register
.Negate
||
1440 reg
->Register
.Indirect
||
1441 reg
->Register
.SwizzleX
!= 0 ||
1442 reg
->Register
.SwizzleY
!= 1 ||
1443 reg
->Register
.SwizzleZ
!= 2 ||
1444 reg
->Register
.File
!= TGSI_FILE_TEMPORARY
);
1445 SVGA3dShaderDestToken temp
;
1447 src0
= srcIn
= translate_src_register( emit
, reg
);
1450 /* need a temp reg */
1451 temp
= get_temp( emit
);
1455 /* move the source into a temp register */
1456 submit_op1(emit
, inst_token(SVGA3DOP_MOV
), temp
, src0
);
1461 /* Do the texkill by checking if any of the XYZW components are < 0.
1462 * Note that ps_2_0 and later take XYZW in consideration, while ps_1_x
1463 * only used XYZ. The MSDN documentation about this is incorrect.
1465 if (!submit_op0( emit
, inst_token( SVGA3DOP_TEXKILL
), dst(src0
) ))
1473 * Translate/emit unconditional kill instruction (usually found inside
1474 * an IF/ELSE/ENDIF block).
1477 emit_kill(struct svga_shader_emitter
*emit
,
1478 const struct tgsi_full_instruction
*insn
)
1480 SVGA3dShaderDestToken temp
;
1481 struct src_register one
= get_one_immediate(emit
);
1482 SVGA3dShaderInstToken inst
= inst_token( SVGA3DOP_TEXKILL
);
1484 /* texkill doesn't allow negation on the operand so lets move
1485 * negation of {1} to a temp register */
1486 temp
= get_temp( emit
);
1487 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), temp
,
1491 return submit_op0( emit
, inst
, temp
);
1496 * Test if r1 and r2 are the same register.
1499 same_register(struct src_register r1
, struct src_register r2
)
1501 return (r1
.base
.num
== r2
.base
.num
&&
1502 r1
.base
.type_upper
== r2
.base
.type_upper
&&
1503 r1
.base
.type_lower
== r2
.base
.type_lower
);
1509 * Implement conditionals by initializing destination reg to 'fail',
1510 * then set predicate reg with UFOP_SETP, then move 'pass' to dest
1511 * based on predicate reg.
1513 * SETP src0, cmp, src1 -- do this first to avoid aliasing problems.
1518 emit_conditional(struct svga_shader_emitter
*emit
,
1519 unsigned compare_func
,
1520 SVGA3dShaderDestToken dst
,
1521 struct src_register src0
,
1522 struct src_register src1
,
1523 struct src_register pass
,
1524 struct src_register fail
)
1526 SVGA3dShaderDestToken pred_reg
= dst_register( SVGA3DREG_PREDICATE
, 0 );
1527 SVGA3dShaderInstToken setp_token
;
1529 switch (compare_func
) {
1530 case PIPE_FUNC_NEVER
:
1531 return submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
1534 case PIPE_FUNC_LESS
:
1535 setp_token
= inst_token_setp(SVGA3DOPCOMP_LT
);
1537 case PIPE_FUNC_EQUAL
:
1538 setp_token
= inst_token_setp(SVGA3DOPCOMP_EQ
);
1540 case PIPE_FUNC_LEQUAL
:
1541 setp_token
= inst_token_setp(SVGA3DOPCOMP_LE
);
1543 case PIPE_FUNC_GREATER
:
1544 setp_token
= inst_token_setp(SVGA3DOPCOMP_GT
);
1546 case PIPE_FUNC_NOTEQUAL
:
1547 setp_token
= inst_token_setp(SVGA3DOPCOMPC_NE
);
1549 case PIPE_FUNC_GEQUAL
:
1550 setp_token
= inst_token_setp(SVGA3DOPCOMP_GE
);
1552 case PIPE_FUNC_ALWAYS
:
1553 return submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
1558 if (same_register(src(dst
), pass
)) {
1559 /* We'll get bad results if the dst and pass registers are the same
1560 * so use a temp register containing pass.
1562 SVGA3dShaderDestToken temp
= get_temp(emit
);
1563 if (!submit_op1(emit
, inst_token(SVGA3DOP_MOV
), temp
, pass
))
1568 /* SETP src0, COMPOP, src1 */
1569 if (!submit_op2( emit
, setp_token
, pred_reg
,
1574 if (!submit_op1(emit
, inst_token(SVGA3DOP_MOV
), dst
, fail
))
1577 /* MOV dst, pass (predicated)
1579 * Note that the predicate reg (and possible modifiers) is passed
1580 * as the first source argument.
1582 if (!submit_op2(emit
,
1583 inst_token_predicated(SVGA3DOP_MOV
), dst
,
1584 src(pred_reg
), pass
))
1592 * Helper for emiting 'selection' commands. Basically:
1599 emit_select(struct svga_shader_emitter
*emit
,
1600 unsigned compare_func
,
1601 SVGA3dShaderDestToken dst
,
1602 struct src_register src0
,
1603 struct src_register src1
)
1605 /* There are some SVGA instructions which implement some selects
1606 * directly, but they are only available in the vertex shader.
1608 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
1609 switch (compare_func
) {
1610 case PIPE_FUNC_GEQUAL
:
1611 return submit_op2( emit
, inst_token( SVGA3DOP_SGE
), dst
, src0
, src1
);
1612 case PIPE_FUNC_LEQUAL
:
1613 return submit_op2( emit
, inst_token( SVGA3DOP_SGE
), dst
, src1
, src0
);
1614 case PIPE_FUNC_GREATER
:
1615 return submit_op2( emit
, inst_token( SVGA3DOP_SLT
), dst
, src1
, src0
);
1616 case PIPE_FUNC_LESS
:
1617 return submit_op2( emit
, inst_token( SVGA3DOP_SLT
), dst
, src0
, src1
);
1623 /* Otherwise, need to use the setp approach:
1626 struct src_register one
, zero
;
1627 /* zero immediate is 0,0,0,1 */
1628 zero
= get_zero_immediate(emit
);
1629 one
= get_one_immediate(emit
);
1631 return emit_conditional(emit
, compare_func
, dst
, src0
, src1
, one
, zero
);
1637 * Translate/emit a TGSI SEQ, SNE, SLT, SGE, etc. instruction.
1640 emit_select_op(struct svga_shader_emitter
*emit
,
1642 const struct tgsi_full_instruction
*insn
)
1644 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1645 struct src_register src0
= translate_src_register(
1646 emit
, &insn
->Src
[0] );
1647 struct src_register src1
= translate_src_register(
1648 emit
, &insn
->Src
[1] );
1650 return emit_select( emit
, compare
, dst
, src0
, src1
);
1655 * Translate TGSI CMP instruction. Component-wise:
1656 * dst = (src0 < 0.0) ? src1 : src2
1659 emit_cmp(struct svga_shader_emitter
*emit
,
1660 const struct tgsi_full_instruction
*insn
)
1662 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1663 const struct src_register src0
=
1664 translate_src_register(emit
, &insn
->Src
[0] );
1665 const struct src_register src1
=
1666 translate_src_register(emit
, &insn
->Src
[1] );
1667 const struct src_register src2
=
1668 translate_src_register(emit
, &insn
->Src
[2] );
1670 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
1671 struct src_register zero
= get_zero_immediate(emit
);
1672 /* We used to simulate CMP with SLT+LRP. But that didn't work when
1673 * src1 or src2 was Inf/NaN. In particular, GLSL sqrt(0) failed
1674 * because it involves a CMP to handle the 0 case.
1675 * Use a conditional expression instead.
1677 return emit_conditional(emit
, PIPE_FUNC_LESS
, dst
,
1678 src0
, zero
, src1
, src2
);
1681 assert(emit
->unit
== PIPE_SHADER_FRAGMENT
);
1683 /* CMP DST, SRC0, SRC2, SRC1 */
1684 return submit_op3( emit
, inst_token( SVGA3DOP_CMP
), dst
,
1691 * Translate/emit 2-operand (coord, sampler) texture instructions.
1694 emit_tex2(struct svga_shader_emitter
*emit
,
1695 const struct tgsi_full_instruction
*insn
,
1696 SVGA3dShaderDestToken dst
)
1698 SVGA3dShaderInstToken inst
;
1699 struct src_register texcoord
;
1700 struct src_register sampler
;
1701 SVGA3dShaderDestToken tmp
;
1705 switch (insn
->Instruction
.Opcode
) {
1706 case TGSI_OPCODE_TEX
:
1707 inst
.op
= SVGA3DOP_TEX
;
1709 case TGSI_OPCODE_TXP
:
1710 inst
.op
= SVGA3DOP_TEX
;
1711 inst
.control
= SVGA3DOPCONT_PROJECT
;
1713 case TGSI_OPCODE_TXB
:
1714 inst
.op
= SVGA3DOP_TEX
;
1715 inst
.control
= SVGA3DOPCONT_BIAS
;
1717 case TGSI_OPCODE_TXL
:
1718 inst
.op
= SVGA3DOP_TEXLDL
;
1725 texcoord
= translate_src_register( emit
, &insn
->Src
[0] );
1726 sampler
= translate_src_register( emit
, &insn
->Src
[1] );
1728 if (emit
->key
.tex
[sampler
.base
.num
].unnormalized
||
1729 emit
->dynamic_branching_level
> 0)
1730 tmp
= get_temp( emit
);
1732 /* Can't do mipmapping inside dynamic branch constructs. Force LOD
1733 * zero in that case.
1735 if (emit
->dynamic_branching_level
> 0 &&
1736 inst
.op
== SVGA3DOP_TEX
&&
1737 SVGA3dShaderGetRegType(texcoord
.base
.value
) == SVGA3DREG_TEMP
) {
1738 struct src_register zero
= get_zero_immediate(emit
);
1740 /* MOV tmp, texcoord */
1741 if (!submit_op1( emit
,
1742 inst_token( SVGA3DOP_MOV
),
1747 /* MOV tmp.w, zero */
1748 if (!submit_op1( emit
,
1749 inst_token( SVGA3DOP_MOV
),
1750 writemask( tmp
, TGSI_WRITEMASK_W
),
1754 texcoord
= src( tmp
);
1755 inst
.op
= SVGA3DOP_TEXLDL
;
1758 /* Explicit normalization of texcoords:
1760 if (emit
->key
.tex
[sampler
.base
.num
].unnormalized
) {
1761 struct src_register wh
= get_tex_dimensions( emit
, sampler
.base
.num
);
1763 /* MUL tmp, SRC0, WH */
1764 if (!submit_op2( emit
, inst_token( SVGA3DOP_MUL
),
1765 tmp
, texcoord
, wh
))
1768 texcoord
= src( tmp
);
1771 return submit_op2( emit
, inst
, dst
, texcoord
, sampler
);
1776 * Translate/emit 4-operand (coord, ddx, ddy, sampler) texture instructions.
1779 emit_tex4(struct svga_shader_emitter
*emit
,
1780 const struct tgsi_full_instruction
*insn
,
1781 SVGA3dShaderDestToken dst
)
1783 SVGA3dShaderInstToken inst
;
1784 struct src_register texcoord
;
1785 struct src_register ddx
;
1786 struct src_register ddy
;
1787 struct src_register sampler
;
1789 texcoord
= translate_src_register( emit
, &insn
->Src
[0] );
1790 ddx
= translate_src_register( emit
, &insn
->Src
[1] );
1791 ddy
= translate_src_register( emit
, &insn
->Src
[2] );
1792 sampler
= translate_src_register( emit
, &insn
->Src
[3] );
1796 switch (insn
->Instruction
.Opcode
) {
1797 case TGSI_OPCODE_TXD
:
1798 inst
.op
= SVGA3DOP_TEXLDD
; /* 4 args! */
1805 return submit_op4( emit
, inst
, dst
, texcoord
, sampler
, ddx
, ddy
);
1810 * Emit texture swizzle code. We do this here since SVGA samplers don't
1811 * directly support swizzles.
1814 emit_tex_swizzle(struct svga_shader_emitter
*emit
,
1815 SVGA3dShaderDestToken dst
,
1816 struct src_register src
,
1822 const unsigned swizzleIn
[4] = {swizzle_x
, swizzle_y
, swizzle_z
, swizzle_w
};
1823 unsigned srcSwizzle
[4];
1824 unsigned srcWritemask
= 0x0, zeroWritemask
= 0x0, oneWritemask
= 0x0;
1827 /* build writemasks and srcSwizzle terms */
1828 for (i
= 0; i
< 4; i
++) {
1829 if (swizzleIn
[i
] == PIPE_SWIZZLE_ZERO
) {
1830 srcSwizzle
[i
] = TGSI_SWIZZLE_X
+ i
;
1831 zeroWritemask
|= (1 << i
);
1833 else if (swizzleIn
[i
] == PIPE_SWIZZLE_ONE
) {
1834 srcSwizzle
[i
] = TGSI_SWIZZLE_X
+ i
;
1835 oneWritemask
|= (1 << i
);
1838 srcSwizzle
[i
] = swizzleIn
[i
];
1839 srcWritemask
|= (1 << i
);
1843 /* write x/y/z/w comps */
1844 if (dst
.mask
& srcWritemask
) {
1845 if (!submit_op1(emit
,
1846 inst_token(SVGA3DOP_MOV
),
1847 writemask(dst
, srcWritemask
),
1857 if (dst
.mask
& zeroWritemask
) {
1858 if (!submit_op1(emit
,
1859 inst_token(SVGA3DOP_MOV
),
1860 writemask(dst
, zeroWritemask
),
1861 get_zero_immediate(emit
)))
1866 if (dst
.mask
& oneWritemask
) {
1867 if (!submit_op1(emit
,
1868 inst_token(SVGA3DOP_MOV
),
1869 writemask(dst
, oneWritemask
),
1870 get_one_immediate(emit
)))
1879 * Translate/emit a TGSI texture sample instruction.
1882 emit_tex(struct svga_shader_emitter
*emit
,
1883 const struct tgsi_full_instruction
*insn
)
1885 SVGA3dShaderDestToken dst
=
1886 translate_dst_register( emit
, insn
, 0 );
1887 struct src_register src0
=
1888 translate_src_register( emit
, &insn
->Src
[0] );
1889 struct src_register src1
=
1890 translate_src_register( emit
, &insn
->Src
[1] );
1892 SVGA3dShaderDestToken tex_result
;
1893 const unsigned unit
= src1
.base
.num
;
1895 /* check for shadow samplers */
1896 boolean compare
= (emit
->key
.tex
[unit
].compare_mode
==
1897 PIPE_TEX_COMPARE_R_TO_TEXTURE
);
1899 /* texture swizzle */
1900 boolean swizzle
= (emit
->key
.tex
[unit
].swizzle_r
!= PIPE_SWIZZLE_RED
||
1901 emit
->key
.tex
[unit
].swizzle_g
!= PIPE_SWIZZLE_GREEN
||
1902 emit
->key
.tex
[unit
].swizzle_b
!= PIPE_SWIZZLE_BLUE
||
1903 emit
->key
.tex
[unit
].swizzle_a
!= PIPE_SWIZZLE_ALPHA
);
1905 boolean saturate
= insn
->Instruction
.Saturate
;
1907 /* If doing compare processing or tex swizzle or saturation, we need to put
1908 * the fetched color into a temporary so it can be used as a source later on.
1910 if (compare
|| swizzle
|| saturate
) {
1911 tex_result
= get_temp( emit
);
1917 switch(insn
->Instruction
.Opcode
) {
1918 case TGSI_OPCODE_TEX
:
1919 case TGSI_OPCODE_TXB
:
1920 case TGSI_OPCODE_TXP
:
1921 case TGSI_OPCODE_TXL
:
1922 if (!emit_tex2( emit
, insn
, tex_result
))
1925 case TGSI_OPCODE_TXD
:
1926 if (!emit_tex4( emit
, insn
, tex_result
))
1934 SVGA3dShaderDestToken dst2
;
1936 if (swizzle
|| saturate
)
1941 if (dst
.mask
& TGSI_WRITEMASK_XYZ
) {
1942 SVGA3dShaderDestToken src0_zdivw
= get_temp( emit
);
1943 /* When sampling a depth texture, the result of the comparison is in
1946 struct src_register tex_src_x
= scalar(src(tex_result
), TGSI_SWIZZLE_Y
);
1947 struct src_register r_coord
;
1949 if (insn
->Instruction
.Opcode
== TGSI_OPCODE_TXP
) {
1950 /* Divide texcoord R by Q */
1951 if (!submit_op1( emit
, inst_token( SVGA3DOP_RCP
),
1952 writemask(src0_zdivw
, TGSI_WRITEMASK_X
),
1953 scalar(src0
, TGSI_SWIZZLE_W
) ))
1956 if (!submit_op2( emit
, inst_token( SVGA3DOP_MUL
),
1957 writemask(src0_zdivw
, TGSI_WRITEMASK_X
),
1958 scalar(src0
, TGSI_SWIZZLE_Z
),
1959 scalar(src(src0_zdivw
), TGSI_SWIZZLE_X
) ))
1962 r_coord
= scalar(src(src0_zdivw
), TGSI_SWIZZLE_X
);
1965 r_coord
= scalar(src0
, TGSI_SWIZZLE_Z
);
1968 /* Compare texture sample value against R component of texcoord */
1969 if (!emit_select(emit
,
1970 emit
->key
.tex
[unit
].compare_func
,
1971 writemask( dst2
, TGSI_WRITEMASK_XYZ
),
1977 if (dst
.mask
& TGSI_WRITEMASK_W
) {
1978 struct src_register one
= get_one_immediate(emit
);
1980 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
1981 writemask( dst2
, TGSI_WRITEMASK_W
),
1987 if (saturate
&& !swizzle
) {
1988 /* MOV_SAT real_dst, dst */
1989 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), dst
, src(tex_result
) ))
1993 /* swizzle from tex_result to dst (handles saturation too, if any) */
1994 emit_tex_swizzle(emit
,
1995 dst
, src(tex_result
),
1996 emit
->key
.tex
[unit
].swizzle_r
,
1997 emit
->key
.tex
[unit
].swizzle_g
,
1998 emit
->key
.tex
[unit
].swizzle_b
,
1999 emit
->key
.tex
[unit
].swizzle_a
);
2007 emit_bgnloop(struct svga_shader_emitter
*emit
,
2008 const struct tgsi_full_instruction
*insn
)
2010 SVGA3dShaderInstToken inst
= inst_token( SVGA3DOP_LOOP
);
2011 struct src_register loop_reg
= src_register( SVGA3DREG_LOOP
, 0 );
2012 struct src_register const_int
= get_loop_const( emit
);
2014 emit
->dynamic_branching_level
++;
2016 return (emit_instruction( emit
, inst
) &&
2017 emit_src( emit
, loop_reg
) &&
2018 emit_src( emit
, const_int
) );
2023 emit_endloop(struct svga_shader_emitter
*emit
,
2024 const struct tgsi_full_instruction
*insn
)
2026 SVGA3dShaderInstToken inst
= inst_token( SVGA3DOP_ENDLOOP
);
2028 emit
->dynamic_branching_level
--;
2030 return emit_instruction( emit
, inst
);
2035 * Translate/emit TGSI BREAK (out of loop) instruction.
2038 emit_brk(struct svga_shader_emitter
*emit
,
2039 const struct tgsi_full_instruction
*insn
)
2041 SVGA3dShaderInstToken inst
= inst_token( SVGA3DOP_BREAK
);
2042 return emit_instruction( emit
, inst
);
2047 * Emit simple instruction which operates on one scalar value (not
2048 * a vector). Ex: LG2, RCP, RSQ.
2051 emit_scalar_op1(struct svga_shader_emitter
*emit
,
2053 const struct tgsi_full_instruction
*insn
)
2055 SVGA3dShaderInstToken inst
;
2056 SVGA3dShaderDestToken dst
;
2057 struct src_register src
;
2059 inst
= inst_token( opcode
);
2060 dst
= translate_dst_register( emit
, insn
, 0 );
2061 src
= translate_src_register( emit
, &insn
->Src
[0] );
2062 src
= scalar( src
, TGSI_SWIZZLE_X
);
2064 return submit_op1( emit
, inst
, dst
, src
);
2069 * Translate/emit a simple instruction (one which has no special-case
2070 * code) such as ADD, MUL, MIN, MAX.
2073 emit_simple_instruction(struct svga_shader_emitter
*emit
,
2075 const struct tgsi_full_instruction
*insn
)
2077 const struct tgsi_full_src_register
*src
= insn
->Src
;
2078 SVGA3dShaderInstToken inst
;
2079 SVGA3dShaderDestToken dst
;
2081 inst
= inst_token( opcode
);
2082 dst
= translate_dst_register( emit
, insn
, 0 );
2084 switch (insn
->Instruction
.NumSrcRegs
) {
2086 return submit_op0( emit
, inst
, dst
);
2088 return submit_op1( emit
, inst
, dst
,
2089 translate_src_register( emit
, &src
[0] ));
2091 return submit_op2( emit
, inst
, dst
,
2092 translate_src_register( emit
, &src
[0] ),
2093 translate_src_register( emit
, &src
[1] ) );
2095 return submit_op3( emit
, inst
, dst
,
2096 translate_src_register( emit
, &src
[0] ),
2097 translate_src_register( emit
, &src
[1] ),
2098 translate_src_register( emit
, &src
[2] ) );
2107 * TGSI_OPCODE_MOVE is only special-cased here to detect the
2108 * svga_fragment_shader::constant_color_output case.
2111 emit_mov(struct svga_shader_emitter
*emit
,
2112 const struct tgsi_full_instruction
*insn
)
2114 const struct tgsi_full_src_register
*src
= &insn
->Src
[0];
2115 const struct tgsi_full_dst_register
*dst
= &insn
->Dst
[0];
2117 if (emit
->unit
== PIPE_SHADER_FRAGMENT
&&
2118 dst
->Register
.File
== TGSI_FILE_OUTPUT
&&
2119 dst
->Register
.Index
== 0 &&
2120 src
->Register
.File
== TGSI_FILE_CONSTANT
&&
2121 !src
->Register
.Indirect
) {
2122 emit
->constant_color_output
= TRUE
;
2125 return emit_simple_instruction(emit
, SVGA3DOP_MOV
, insn
);
2130 * Translate/emit TGSI DDX, DDY instructions.
2133 emit_deriv(struct svga_shader_emitter
*emit
,
2134 const struct tgsi_full_instruction
*insn
)
2136 if (emit
->dynamic_branching_level
> 0 &&
2137 insn
->Src
[0].Register
.File
== TGSI_FILE_TEMPORARY
)
2139 SVGA3dShaderDestToken dst
=
2140 translate_dst_register( emit
, insn
, 0 );
2142 /* Deriv opcodes not valid inside dynamic branching, workaround
2143 * by zeroing out the destination.
2145 if (!submit_op1(emit
,
2146 inst_token( SVGA3DOP_MOV
),
2148 get_zero_immediate(emit
)))
2155 const struct tgsi_full_src_register
*reg
= &insn
->Src
[0];
2156 SVGA3dShaderInstToken inst
;
2157 SVGA3dShaderDestToken dst
;
2158 struct src_register src0
;
2160 switch (insn
->Instruction
.Opcode
) {
2161 case TGSI_OPCODE_DDX
:
2162 opcode
= SVGA3DOP_DSX
;
2164 case TGSI_OPCODE_DDY
:
2165 opcode
= SVGA3DOP_DSY
;
2171 inst
= inst_token( opcode
);
2172 dst
= translate_dst_register( emit
, insn
, 0 );
2173 src0
= translate_src_register( emit
, reg
);
2175 /* We cannot use negate or abs on source to dsx/dsy instruction.
2177 if (reg
->Register
.Absolute
||
2178 reg
->Register
.Negate
) {
2179 SVGA3dShaderDestToken temp
= get_temp( emit
);
2181 if (!emit_repl( emit
, temp
, &src0
))
2185 return submit_op1( emit
, inst
, dst
, src0
);
2191 * Translate/emit ARL (Address Register Load) instruction. Used to
2192 * move a value into the special 'address' register. Used to implement
2193 * indirect/variable indexing into arrays.
2196 emit_arl(struct svga_shader_emitter
*emit
,
2197 const struct tgsi_full_instruction
*insn
)
2199 ++emit
->current_arl
;
2200 if (emit
->unit
== PIPE_SHADER_FRAGMENT
) {
2201 /* MOVA not present in pixel shader instruction set.
2202 * Ignore this instruction altogether since it is
2203 * only used for loop counters -- and for that
2204 * we reference aL directly.
2208 if (svga_arl_needs_adjustment( emit
)) {
2209 return emit_fake_arl( emit
, insn
);
2211 /* no need to adjust, just emit straight arl */
2212 return emit_simple_instruction(emit
, SVGA3DOP_MOVA
, insn
);
2218 emit_pow(struct svga_shader_emitter
*emit
,
2219 const struct tgsi_full_instruction
*insn
)
2221 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
2222 struct src_register src0
= translate_src_register(
2223 emit
, &insn
->Src
[0] );
2224 struct src_register src1
= translate_src_register(
2225 emit
, &insn
->Src
[1] );
2226 boolean need_tmp
= FALSE
;
2228 /* POW can only output to a temporary */
2229 if (insn
->Dst
[0].Register
.File
!= TGSI_FILE_TEMPORARY
)
2232 /* POW src1 must not be the same register as dst */
2233 if (alias_src_dst( src1
, dst
))
2236 /* it's a scalar op */
2237 src0
= scalar( src0
, TGSI_SWIZZLE_X
);
2238 src1
= scalar( src1
, TGSI_SWIZZLE_X
);
2241 SVGA3dShaderDestToken tmp
=
2242 writemask(get_temp( emit
), TGSI_WRITEMASK_X
);
2244 if (!submit_op2(emit
, inst_token( SVGA3DOP_POW
), tmp
, src0
, src1
))
2247 return submit_op1(emit
, inst_token( SVGA3DOP_MOV
),
2248 dst
, scalar(src(tmp
), 0) );
2251 return submit_op2(emit
, inst_token( SVGA3DOP_POW
), dst
, src0
, src1
);
2257 * Translate/emit TGSI XPD (vector cross product) instruction.
2260 emit_xpd(struct svga_shader_emitter
*emit
,
2261 const struct tgsi_full_instruction
*insn
)
2263 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
2264 const struct src_register src0
= translate_src_register(
2265 emit
, &insn
->Src
[0] );
2266 const struct src_register src1
= translate_src_register(
2267 emit
, &insn
->Src
[1] );
2268 boolean need_dst_tmp
= FALSE
;
2270 /* XPD can only output to a temporary */
2271 if (SVGA3dShaderGetRegType(dst
.value
) != SVGA3DREG_TEMP
)
2272 need_dst_tmp
= TRUE
;
2274 /* The dst reg must not be the same as src0 or src1*/
2275 if (alias_src_dst(src0
, dst
) ||
2276 alias_src_dst(src1
, dst
))
2277 need_dst_tmp
= TRUE
;
2280 SVGA3dShaderDestToken tmp
= get_temp( emit
);
2282 /* Obey DX9 restrictions on mask:
2284 tmp
.mask
= dst
.mask
& TGSI_WRITEMASK_XYZ
;
2286 if (!submit_op2(emit
, inst_token( SVGA3DOP_CRS
), tmp
, src0
, src1
))
2289 if (!submit_op1(emit
, inst_token( SVGA3DOP_MOV
), dst
, src( tmp
)))
2293 if (!submit_op2(emit
, inst_token( SVGA3DOP_CRS
), dst
, src0
, src1
))
2297 /* Need to emit 1.0 to dst.w?
2299 if (dst
.mask
& TGSI_WRITEMASK_W
) {
2300 struct src_register one
= get_one_immediate( emit
);
2302 if (!submit_op1(emit
,
2303 inst_token( SVGA3DOP_MOV
),
2304 writemask(dst
, TGSI_WRITEMASK_W
),
2314 * Emit a LRP (linear interpolation) instruction.
2317 submit_lrp(struct svga_shader_emitter
*emit
,
2318 SVGA3dShaderDestToken dst
,
2319 struct src_register src0
,
2320 struct src_register src1
,
2321 struct src_register src2
)
2323 SVGA3dShaderDestToken tmp
;
2324 boolean need_dst_tmp
= FALSE
;
2326 /* The dst reg must be a temporary, and not be the same as src0 or src2 */
2327 if (SVGA3dShaderGetRegType(dst
.value
) != SVGA3DREG_TEMP
||
2328 alias_src_dst(src0
, dst
) ||
2329 alias_src_dst(src2
, dst
))
2330 need_dst_tmp
= TRUE
;
2333 tmp
= get_temp( emit
);
2334 tmp
.mask
= dst
.mask
;
2340 if (!submit_op3(emit
, inst_token( SVGA3DOP_LRP
), tmp
, src0
, src1
, src2
))
2344 if (!submit_op1(emit
, inst_token( SVGA3DOP_MOV
), dst
, src( tmp
)))
2353 * Translate/emit LRP (Linear Interpolation) instruction.
2356 emit_lrp(struct svga_shader_emitter
*emit
,
2357 const struct tgsi_full_instruction
*insn
)
2359 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
2360 const struct src_register src0
= translate_src_register(
2361 emit
, &insn
->Src
[0] );
2362 const struct src_register src1
= translate_src_register(
2363 emit
, &insn
->Src
[1] );
2364 const struct src_register src2
= translate_src_register(
2365 emit
, &insn
->Src
[2] );
2367 return submit_lrp(emit
, dst
, src0
, src1
, src2
);
2371 * Translate/emit DST (Distance function) instruction.
2374 emit_dst_insn(struct svga_shader_emitter
*emit
,
2375 const struct tgsi_full_instruction
*insn
)
2377 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
2378 /* SVGA/DX9 has a DST instruction, but only for vertex shaders:
2380 return emit_simple_instruction(emit
, SVGA3DOP_DST
, insn
);
2383 /* result[0] = 1 * 1;
2384 * result[1] = a[1] * b[1];
2385 * result[2] = a[2] * 1;
2386 * result[3] = 1 * b[3];
2388 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
2389 SVGA3dShaderDestToken tmp
;
2390 const struct src_register src0
= translate_src_register(
2391 emit
, &insn
->Src
[0] );
2392 const struct src_register src1
= translate_src_register(
2393 emit
, &insn
->Src
[1] );
2394 boolean need_tmp
= FALSE
;
2396 if (SVGA3dShaderGetRegType(dst
.value
) != SVGA3DREG_TEMP
||
2397 alias_src_dst(src0
, dst
) ||
2398 alias_src_dst(src1
, dst
))
2402 tmp
= get_temp( emit
);
2410 if (tmp
.mask
& TGSI_WRITEMASK_XW
) {
2411 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
2412 writemask(tmp
, TGSI_WRITEMASK_XW
),
2413 get_one_immediate(emit
)))
2419 if (tmp
.mask
& TGSI_WRITEMASK_YZ
) {
2420 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
2421 writemask(tmp
, TGSI_WRITEMASK_YZ
),
2426 /* tmp.yw = tmp * src1
2428 if (tmp
.mask
& TGSI_WRITEMASK_YW
) {
2429 if (!submit_op2( emit
, inst_token( SVGA3DOP_MUL
),
2430 writemask(tmp
, TGSI_WRITEMASK_YW
),
2439 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
2451 emit_exp(struct svga_shader_emitter
*emit
,
2452 const struct tgsi_full_instruction
*insn
)
2454 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
2455 struct src_register src0
=
2456 translate_src_register( emit
, &insn
->Src
[0] );
2457 SVGA3dShaderDestToken fraction
;
2459 if (dst
.mask
& TGSI_WRITEMASK_Y
)
2461 else if (dst
.mask
& TGSI_WRITEMASK_X
)
2462 fraction
= get_temp( emit
);
2466 /* If y is being written, fill it with src0 - floor(src0).
2468 if (dst
.mask
& TGSI_WRITEMASK_XY
) {
2469 if (!submit_op1( emit
, inst_token( SVGA3DOP_FRC
),
2470 writemask( fraction
, TGSI_WRITEMASK_Y
),
2475 /* If x is being written, fill it with 2 ^ floor(src0).
2477 if (dst
.mask
& TGSI_WRITEMASK_X
) {
2478 if (!submit_op2( emit
, inst_token( SVGA3DOP_ADD
),
2479 writemask( dst
, TGSI_WRITEMASK_X
),
2481 scalar( negate( src( fraction
) ), TGSI_SWIZZLE_Y
) ) )
2484 if (!submit_op1( emit
, inst_token( SVGA3DOP_EXP
),
2485 writemask( dst
, TGSI_WRITEMASK_X
),
2486 scalar( src( dst
), TGSI_SWIZZLE_X
) ) )
2489 if (!(dst
.mask
& TGSI_WRITEMASK_Y
))
2490 release_temp( emit
, fraction
);
2493 /* If z is being written, fill it with 2 ^ src0 (partial precision).
2495 if (dst
.mask
& TGSI_WRITEMASK_Z
) {
2496 if (!submit_op1( emit
, inst_token( SVGA3DOP_EXPP
),
2497 writemask( dst
, TGSI_WRITEMASK_Z
),
2502 /* If w is being written, fill it with one.
2504 if (dst
.mask
& TGSI_WRITEMASK_W
) {
2505 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
2506 writemask(dst
, TGSI_WRITEMASK_W
),
2507 get_one_immediate(emit
)))
2516 * Translate/emit LIT (Lighting helper) instruction.
2519 emit_lit(struct svga_shader_emitter
*emit
,
2520 const struct tgsi_full_instruction
*insn
)
2522 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
2523 /* SVGA/DX9 has a LIT instruction, but only for vertex shaders:
2525 return emit_simple_instruction(emit
, SVGA3DOP_LIT
, insn
);
2528 /* D3D vs. GL semantics can be fairly easily accomodated by
2529 * variations on this sequence.
2533 * tmp.z = pow(src.y,src.w)
2534 * p0 = src0.xxxx > 0
2535 * result = zero.wxxw
2536 * (p0) result.yz = tmp
2540 * tmp.z = pow(src.y,src.w)
2541 * p0 = src0.xxyy > 0
2542 * result = zero.wxxw
2543 * (p0) result.yz = tmp
2545 * Will implement the GL version for now.
2547 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
2548 SVGA3dShaderDestToken tmp
= get_temp( emit
);
2549 const struct src_register src0
= translate_src_register(
2550 emit
, &insn
->Src
[0] );
2552 /* tmp = pow(src.y, src.w)
2554 if (dst
.mask
& TGSI_WRITEMASK_Z
) {
2555 if (!submit_op2(emit
, inst_token( SVGA3DOP_POW
),
2564 if (dst
.mask
& TGSI_WRITEMASK_Y
) {
2565 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
2566 writemask(tmp
, TGSI_WRITEMASK_Y
),
2571 /* Can't quite do this with emit conditional due to the extra
2572 * writemask on the predicated mov:
2575 SVGA3dShaderDestToken pred_reg
= dst_register( SVGA3DREG_PREDICATE
, 0 );
2576 struct src_register predsrc
;
2578 /* D3D vs GL semantics:
2581 predsrc
= swizzle(src0
, 0, 0, 1, 1); /* D3D */
2583 predsrc
= swizzle(src0
, 0, 0, 0, 0); /* GL */
2585 /* SETP src0.xxyy, GT, {0}.x */
2586 if (!submit_op2( emit
,
2587 inst_token_setp(SVGA3DOPCOMP_GT
),
2590 get_zero_immediate(emit
)))
2594 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), dst
,
2595 get_immediate(emit
, 1.0f
, 0.0f
, 0.0f
, 1.0f
)))
2598 /* MOV dst.yz, tmp (predicated)
2600 * Note that the predicate reg (and possible modifiers) is passed
2601 * as the first source argument.
2603 if (dst
.mask
& TGSI_WRITEMASK_YZ
) {
2604 if (!submit_op2( emit
,
2605 inst_token_predicated(SVGA3DOP_MOV
),
2606 writemask(dst
, TGSI_WRITEMASK_YZ
),
2607 src( pred_reg
), src( tmp
) ))
2618 emit_ex2(struct svga_shader_emitter
*emit
,
2619 const struct tgsi_full_instruction
*insn
)
2621 SVGA3dShaderInstToken inst
;
2622 SVGA3dShaderDestToken dst
;
2623 struct src_register src0
;
2625 inst
= inst_token( SVGA3DOP_EXP
);
2626 dst
= translate_dst_register( emit
, insn
, 0 );
2627 src0
= translate_src_register( emit
, &insn
->Src
[0] );
2628 src0
= scalar( src0
, TGSI_SWIZZLE_X
);
2630 if (dst
.mask
!= TGSI_WRITEMASK_XYZW
) {
2631 SVGA3dShaderDestToken tmp
= get_temp( emit
);
2633 if (!submit_op1( emit
, inst
, tmp
, src0
))
2636 return submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
2638 scalar( src( tmp
), TGSI_SWIZZLE_X
) );
2641 return submit_op1( emit
, inst
, dst
, src0
);
2646 emit_log(struct svga_shader_emitter
*emit
,
2647 const struct tgsi_full_instruction
*insn
)
2649 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
2650 struct src_register src0
=
2651 translate_src_register( emit
, &insn
->Src
[0] );
2652 SVGA3dShaderDestToken abs_tmp
;
2653 struct src_register abs_src0
;
2654 SVGA3dShaderDestToken log2_abs
;
2658 if (dst
.mask
& TGSI_WRITEMASK_Z
)
2660 else if (dst
.mask
& TGSI_WRITEMASK_XY
)
2661 log2_abs
= get_temp( emit
);
2665 /* If z is being written, fill it with log2( abs( src0 ) ).
2667 if (dst
.mask
& TGSI_WRITEMASK_XYZ
) {
2668 if (!src0
.base
.srcMod
|| src0
.base
.srcMod
== SVGA3DSRCMOD_ABS
)
2671 abs_tmp
= get_temp( emit
);
2673 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
2678 abs_src0
= src( abs_tmp
);
2681 abs_src0
= absolute( scalar( abs_src0
, TGSI_SWIZZLE_X
) );
2683 if (!submit_op1( emit
, inst_token( SVGA3DOP_LOG
),
2684 writemask( log2_abs
, TGSI_WRITEMASK_Z
),
2689 if (dst
.mask
& TGSI_WRITEMASK_XY
) {
2690 SVGA3dShaderDestToken floor_log2
;
2692 if (dst
.mask
& TGSI_WRITEMASK_X
)
2695 floor_log2
= get_temp( emit
);
2697 /* If x is being written, fill it with floor( log2( abs( src0 ) ) ).
2699 if (!submit_op1( emit
, inst_token( SVGA3DOP_FRC
),
2700 writemask( floor_log2
, TGSI_WRITEMASK_X
),
2701 scalar( src( log2_abs
), TGSI_SWIZZLE_Z
) ) )
2704 if (!submit_op2( emit
, inst_token( SVGA3DOP_ADD
),
2705 writemask( floor_log2
, TGSI_WRITEMASK_X
),
2706 scalar( src( log2_abs
), TGSI_SWIZZLE_Z
),
2707 negate( src( floor_log2
) ) ) )
2710 /* If y is being written, fill it with
2711 * abs ( src0 ) / ( 2 ^ floor( log2( abs( src0 ) ) ) ).
2713 if (dst
.mask
& TGSI_WRITEMASK_Y
) {
2714 if (!submit_op1( emit
, inst_token( SVGA3DOP_EXP
),
2715 writemask( dst
, TGSI_WRITEMASK_Y
),
2716 negate( scalar( src( floor_log2
),
2717 TGSI_SWIZZLE_X
) ) ) )
2720 if (!submit_op2( emit
, inst_token( SVGA3DOP_MUL
),
2721 writemask( dst
, TGSI_WRITEMASK_Y
),
2727 if (!(dst
.mask
& TGSI_WRITEMASK_X
))
2728 release_temp( emit
, floor_log2
);
2730 if (!(dst
.mask
& TGSI_WRITEMASK_Z
))
2731 release_temp( emit
, log2_abs
);
2734 if (dst
.mask
& TGSI_WRITEMASK_XYZ
&& src0
.base
.srcMod
&&
2735 src0
.base
.srcMod
!= SVGA3DSRCMOD_ABS
)
2736 release_temp( emit
, abs_tmp
);
2738 /* If w is being written, fill it with one.
2740 if (dst
.mask
& TGSI_WRITEMASK_W
) {
2741 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
2742 writemask(dst
, TGSI_WRITEMASK_W
),
2743 get_one_immediate(emit
)))
2752 * Translate TGSI TRUNC or ROUND instruction.
2753 * We need to truncate toward zero. Ex: trunc(-1.9) = -1
2754 * Different approaches are needed for VS versus PS.
2757 emit_trunc_round(struct svga_shader_emitter
*emit
,
2758 const struct tgsi_full_instruction
*insn
,
2761 SVGA3dShaderDestToken dst
= translate_dst_register(emit
, insn
, 0);
2762 const struct src_register src0
=
2763 translate_src_register(emit
, &insn
->Src
[0] );
2764 SVGA3dShaderDestToken t1
= get_temp(emit
);
2767 SVGA3dShaderDestToken t0
= get_temp(emit
);
2768 struct src_register half
= get_half_immediate(emit
);
2770 /* t0 = abs(src0) + 0.5 */
2771 if (!submit_op2(emit
, inst_token(SVGA3DOP_ADD
), t0
,
2772 absolute(src0
), half
))
2775 /* t1 = fract(t0) */
2776 if (!submit_op1(emit
, inst_token(SVGA3DOP_FRC
), t1
, src(t0
)))
2780 if (!submit_op2(emit
, inst_token(SVGA3DOP_ADD
), t1
, src(t0
),
2787 /* t1 = fract(abs(src0)) */
2788 if (!submit_op1(emit
, inst_token(SVGA3DOP_FRC
), t1
, absolute(src0
)))
2791 /* t1 = abs(src0) - t1 */
2792 if (!submit_op2(emit
, inst_token(SVGA3DOP_ADD
), t1
, absolute(src0
),
2798 * Now we need to multiply t1 by the sign of the original value.
2800 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
2801 /* For VS: use SGN instruction */
2802 /* Need two extra/dummy registers: */
2803 SVGA3dShaderDestToken t2
= get_temp(emit
), t3
= get_temp(emit
),
2804 t4
= get_temp(emit
);
2806 /* t2 = sign(src0) */
2807 if (!submit_op3(emit
, inst_token(SVGA3DOP_SGN
), t2
, src0
,
2812 if (!submit_op2(emit
, inst_token(SVGA3DOP_MUL
), dst
, src(t1
), src(t2
)))
2816 /* For FS: Use CMP instruction */
2817 return submit_op3(emit
, inst_token( SVGA3DOP_CMP
), dst
,
2818 src0
, src(t1
), negate(src(t1
)));
2826 * Translate/emit "begin subroutine" instruction/marker/label.
2829 emit_bgnsub(struct svga_shader_emitter
*emit
,
2831 const struct tgsi_full_instruction
*insn
)
2835 /* Note that we've finished the main function and are now emitting
2836 * subroutines. This affects how we terminate the generated
2839 emit
->in_main_func
= FALSE
;
2841 for (i
= 0; i
< emit
->nr_labels
; i
++) {
2842 if (emit
->label
[i
] == position
) {
2843 return (emit_instruction( emit
, inst_token( SVGA3DOP_RET
) ) &&
2844 emit_instruction( emit
, inst_token( SVGA3DOP_LABEL
) ) &&
2845 emit_src( emit
, src_register( SVGA3DREG_LABEL
, i
)));
2855 * Translate/emit subroutine call instruction.
2858 emit_call(struct svga_shader_emitter
*emit
,
2859 const struct tgsi_full_instruction
*insn
)
2861 unsigned position
= insn
->Label
.Label
;
2864 for (i
= 0; i
< emit
->nr_labels
; i
++) {
2865 if (emit
->label
[i
] == position
)
2869 if (emit
->nr_labels
== Elements(emit
->label
))
2872 if (i
== emit
->nr_labels
) {
2873 emit
->label
[i
] = position
;
2877 return (emit_instruction( emit
, inst_token( SVGA3DOP_CALL
) ) &&
2878 emit_src( emit
, src_register( SVGA3DREG_LABEL
, i
)));
2883 * Called at the end of the shader. Actually, emit special "fix-up"
2884 * code for the vertex/fragment shader.
2887 emit_end(struct svga_shader_emitter
*emit
)
2889 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
2890 return emit_vs_postamble( emit
);
2893 return emit_ps_postamble( emit
);
2899 * Translate any TGSI instruction to SVGA.
2902 svga_emit_instruction(struct svga_shader_emitter
*emit
,
2904 const struct tgsi_full_instruction
*insn
)
2906 switch (insn
->Instruction
.Opcode
) {
2908 case TGSI_OPCODE_ARL
:
2909 return emit_arl( emit
, insn
);
2911 case TGSI_OPCODE_TEX
:
2912 case TGSI_OPCODE_TXB
:
2913 case TGSI_OPCODE_TXP
:
2914 case TGSI_OPCODE_TXL
:
2915 case TGSI_OPCODE_TXD
:
2916 return emit_tex( emit
, insn
);
2918 case TGSI_OPCODE_DDX
:
2919 case TGSI_OPCODE_DDY
:
2920 return emit_deriv( emit
, insn
);
2922 case TGSI_OPCODE_BGNSUB
:
2923 return emit_bgnsub( emit
, position
, insn
);
2925 case TGSI_OPCODE_ENDSUB
:
2928 case TGSI_OPCODE_CAL
:
2929 return emit_call( emit
, insn
);
2931 case TGSI_OPCODE_FLR
:
2932 return emit_floor( emit
, insn
);
2934 case TGSI_OPCODE_TRUNC
:
2935 return emit_trunc_round( emit
, insn
, FALSE
);
2937 case TGSI_OPCODE_ROUND
:
2938 return emit_trunc_round( emit
, insn
, TRUE
);
2940 case TGSI_OPCODE_CEIL
:
2941 return emit_ceil( emit
, insn
);
2943 case TGSI_OPCODE_CMP
:
2944 return emit_cmp( emit
, insn
);
2946 case TGSI_OPCODE_DIV
:
2947 return emit_div( emit
, insn
);
2949 case TGSI_OPCODE_DP2
:
2950 return emit_dp2( emit
, insn
);
2952 case TGSI_OPCODE_DPH
:
2953 return emit_dph( emit
, insn
);
2955 case TGSI_OPCODE_COS
:
2956 return emit_cos( emit
, insn
);
2958 case TGSI_OPCODE_SIN
:
2959 return emit_sin( emit
, insn
);
2961 case TGSI_OPCODE_SCS
:
2962 return emit_sincos( emit
, insn
);
2964 case TGSI_OPCODE_END
:
2965 /* TGSI always finishes the main func with an END */
2966 return emit_end( emit
);
2968 case TGSI_OPCODE_KILL_IF
:
2969 return emit_kill_if( emit
, insn
);
2971 /* Selection opcodes. The underlying language is fairly
2972 * non-orthogonal about these.
2974 case TGSI_OPCODE_SEQ
:
2975 return emit_select_op( emit
, PIPE_FUNC_EQUAL
, insn
);
2977 case TGSI_OPCODE_SNE
:
2978 return emit_select_op( emit
, PIPE_FUNC_NOTEQUAL
, insn
);
2980 case TGSI_OPCODE_SGT
:
2981 return emit_select_op( emit
, PIPE_FUNC_GREATER
, insn
);
2983 case TGSI_OPCODE_SGE
:
2984 return emit_select_op( emit
, PIPE_FUNC_GEQUAL
, insn
);
2986 case TGSI_OPCODE_SLT
:
2987 return emit_select_op( emit
, PIPE_FUNC_LESS
, insn
);
2989 case TGSI_OPCODE_SLE
:
2990 return emit_select_op( emit
, PIPE_FUNC_LEQUAL
, insn
);
2992 case TGSI_OPCODE_SUB
:
2993 return emit_sub( emit
, insn
);
2995 case TGSI_OPCODE_POW
:
2996 return emit_pow( emit
, insn
);
2998 case TGSI_OPCODE_EX2
:
2999 return emit_ex2( emit
, insn
);
3001 case TGSI_OPCODE_EXP
:
3002 return emit_exp( emit
, insn
);
3004 case TGSI_OPCODE_LOG
:
3005 return emit_log( emit
, insn
);
3007 case TGSI_OPCODE_LG2
:
3008 return emit_scalar_op1( emit
, SVGA3DOP_LOG
, insn
);
3010 case TGSI_OPCODE_RSQ
:
3011 return emit_scalar_op1( emit
, SVGA3DOP_RSQ
, insn
);
3013 case TGSI_OPCODE_RCP
:
3014 return emit_scalar_op1( emit
, SVGA3DOP_RCP
, insn
);
3016 case TGSI_OPCODE_CONT
:
3017 /* not expected (we return PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED = 0) */
3020 case TGSI_OPCODE_RET
:
3021 /* This is a noop -- we tell mesa that we can't support RET
3022 * within a function (early return), so this will always be
3023 * followed by an ENDSUB.
3027 /* These aren't actually used by any of the frontends we care
3030 case TGSI_OPCODE_CLAMP
:
3031 case TGSI_OPCODE_AND
:
3032 case TGSI_OPCODE_OR
:
3033 case TGSI_OPCODE_I2F
:
3034 case TGSI_OPCODE_NOT
:
3035 case TGSI_OPCODE_SHL
:
3036 case TGSI_OPCODE_ISHR
:
3037 case TGSI_OPCODE_XOR
:
3040 case TGSI_OPCODE_IF
:
3041 return emit_if( emit
, insn
);
3042 case TGSI_OPCODE_ELSE
:
3043 return emit_else( emit
, insn
);
3044 case TGSI_OPCODE_ENDIF
:
3045 return emit_endif( emit
, insn
);
3047 case TGSI_OPCODE_BGNLOOP
:
3048 return emit_bgnloop( emit
, insn
);
3049 case TGSI_OPCODE_ENDLOOP
:
3050 return emit_endloop( emit
, insn
);
3051 case TGSI_OPCODE_BRK
:
3052 return emit_brk( emit
, insn
);
3054 case TGSI_OPCODE_XPD
:
3055 return emit_xpd( emit
, insn
);
3057 case TGSI_OPCODE_KILL
:
3058 return emit_kill( emit
, insn
);
3060 case TGSI_OPCODE_DST
:
3061 return emit_dst_insn( emit
, insn
);
3063 case TGSI_OPCODE_LIT
:
3064 return emit_lit( emit
, insn
);
3066 case TGSI_OPCODE_LRP
:
3067 return emit_lrp( emit
, insn
);
3069 case TGSI_OPCODE_SSG
:
3070 return emit_ssg( emit
, insn
);
3072 case TGSI_OPCODE_MOV
:
3073 return emit_mov( emit
, insn
);
3077 unsigned opcode
= translate_opcode(insn
->Instruction
.Opcode
);
3079 if (opcode
== SVGA3DOP_LAST_INST
)
3082 if (!emit_simple_instruction( emit
, opcode
, insn
))
3092 * Translate/emit a TGSI IMMEDIATE declaration.
3093 * An immediate vector is a constant that's hard-coded into the shader.
3096 svga_emit_immediate(struct svga_shader_emitter
*emit
,
3097 const struct tgsi_full_immediate
*imm
)
3099 static const float id
[4] = {0,0,0,1};
3103 assert(1 <= imm
->Immediate
.NrTokens
&& imm
->Immediate
.NrTokens
<= 5);
3104 for (i
= 0; i
< imm
->Immediate
.NrTokens
- 1; i
++) {
3105 float f
= imm
->u
[i
].Float
;
3106 value
[i
] = util_is_inf_or_nan(f
) ? 0.0f
: f
;
3109 /* If the immediate has less than four values, fill in the remaining
3110 * positions from id={0,0,0,1}.
3112 for ( ; i
< 4; i
++ )
3115 return emit_def_const( emit
, SVGA3D_CONST_TYPE_FLOAT
,
3116 emit
->imm_start
+ emit
->internal_imm_count
++,
3117 value
[0], value
[1], value
[2], value
[3]);
3122 make_immediate(struct svga_shader_emitter
*emit
,
3123 float a
, float b
, float c
, float d
,
3124 struct src_register
*out
)
3126 unsigned idx
= emit
->nr_hw_float_const
++;
3128 if (!emit_def_const( emit
, SVGA3D_CONST_TYPE_FLOAT
,
3132 *out
= src_register( SVGA3DREG_CONST
, idx
);
3139 * Emit special VS instructions at top of shader.
3142 emit_vs_preamble(struct svga_shader_emitter
*emit
)
3144 if (!emit
->key
.vs
.need_prescale
) {
3145 if (!make_immediate( emit
, 0, 0, .5, .5,
3155 * Emit special PS instructions at top of shader.
3158 emit_ps_preamble(struct svga_shader_emitter
*emit
)
3160 if (emit
->ps_reads_pos
&& emit
->info
.reads_z
) {
3162 * Assemble the position from various bits of inputs. Depth and W are
3163 * passed in a texcoord this is due to D3D's vPos not hold Z or W.
3164 * Also fixup the perspective interpolation.
3166 * temp_pos.xy = vPos.xy
3167 * temp_pos.w = rcp(texcoord1.w);
3168 * temp_pos.z = texcoord1.z * temp_pos.w;
3170 if (!submit_op1( emit
,
3171 inst_token(SVGA3DOP_MOV
),
3172 writemask( emit
->ps_temp_pos
, TGSI_WRITEMASK_XY
),
3173 emit
->ps_true_pos
))
3176 if (!submit_op1( emit
,
3177 inst_token(SVGA3DOP_RCP
),
3178 writemask( emit
->ps_temp_pos
, TGSI_WRITEMASK_W
),
3179 scalar( emit
->ps_depth_pos
, TGSI_SWIZZLE_W
) ))
3182 if (!submit_op2( emit
,
3183 inst_token(SVGA3DOP_MUL
),
3184 writemask( emit
->ps_temp_pos
, TGSI_WRITEMASK_Z
),
3185 scalar( emit
->ps_depth_pos
, TGSI_SWIZZLE_Z
),
3186 scalar( src(emit
->ps_temp_pos
), TGSI_SWIZZLE_W
) ))
3195 * Emit special PS instructions at end of shader.
3198 emit_ps_postamble(struct svga_shader_emitter
*emit
)
3202 /* PS oDepth is incredibly fragile and it's very hard to catch the
3203 * types of usage that break it during shader emit. Easier just to
3204 * redirect the main program to a temporary and then only touch
3205 * oDepth with a hand-crafted MOV below.
3207 if (SVGA3dShaderGetRegType(emit
->true_pos
.value
) != 0) {
3208 if (!submit_op1( emit
,
3209 inst_token(SVGA3DOP_MOV
),
3211 scalar(src(emit
->temp_pos
), TGSI_SWIZZLE_Z
) ))
3215 for (i
= 0; i
< PIPE_MAX_COLOR_BUFS
; i
++) {
3216 if (SVGA3dShaderGetRegType(emit
->true_color_output
[i
].value
) != 0) {
3217 /* Potentially override output colors with white for XOR
3218 * logicop workaround.
3220 if (emit
->unit
== PIPE_SHADER_FRAGMENT
&&
3221 emit
->key
.fs
.white_fragments
) {
3222 struct src_register one
= get_one_immediate(emit
);
3224 if (!submit_op1( emit
,
3225 inst_token(SVGA3DOP_MOV
),
3226 emit
->true_color_output
[i
],
3230 else if (emit
->unit
== PIPE_SHADER_FRAGMENT
&&
3231 i
< emit
->key
.fs
.write_color0_to_n_cbufs
) {
3232 /* Write temp color output [0] to true output [i] */
3233 if (!submit_op1(emit
, inst_token(SVGA3DOP_MOV
),
3234 emit
->true_color_output
[i
],
3235 src(emit
->temp_color_output
[0]))) {
3240 if (!submit_op1( emit
,
3241 inst_token(SVGA3DOP_MOV
),
3242 emit
->true_color_output
[i
],
3243 src(emit
->temp_color_output
[i
]) ))
3254 * Emit special VS instructions at end of shader.
3257 emit_vs_postamble(struct svga_shader_emitter
*emit
)
3259 /* PSIZ output is incredibly fragile and it's very hard to catch
3260 * the types of usage that break it during shader emit. Easier
3261 * just to redirect the main program to a temporary and then only
3262 * touch PSIZ with a hand-crafted MOV below.
3264 if (SVGA3dShaderGetRegType(emit
->true_psiz
.value
) != 0) {
3265 if (!submit_op1( emit
,
3266 inst_token(SVGA3DOP_MOV
),
3268 scalar(src(emit
->temp_psiz
), TGSI_SWIZZLE_X
) ))
3272 /* Need to perform various manipulations on vertex position to cope
3273 * with the different GL and D3D clip spaces.
3275 if (emit
->key
.vs
.need_prescale
) {
3276 SVGA3dShaderDestToken temp_pos
= emit
->temp_pos
;
3277 SVGA3dShaderDestToken depth
= emit
->depth_pos
;
3278 SVGA3dShaderDestToken pos
= emit
->true_pos
;
3279 unsigned offset
= emit
->info
.file_max
[TGSI_FILE_CONSTANT
] + 1;
3280 struct src_register prescale_scale
= src_register( SVGA3DREG_CONST
,
3282 struct src_register prescale_trans
= src_register( SVGA3DREG_CONST
,
3285 if (!submit_op1( emit
,
3286 inst_token(SVGA3DOP_MOV
),
3287 writemask(depth
, TGSI_WRITEMASK_W
),
3288 scalar(src(temp_pos
), TGSI_SWIZZLE_W
) ))
3291 /* MUL temp_pos.xyz, temp_pos, prescale.scale
3292 * MAD result.position, temp_pos.wwww, prescale.trans, temp_pos
3293 * --> Note that prescale.trans.w == 0
3295 if (!submit_op2( emit
,
3296 inst_token(SVGA3DOP_MUL
),
3297 writemask(temp_pos
, TGSI_WRITEMASK_XYZ
),
3302 if (!submit_op3( emit
,
3303 inst_token(SVGA3DOP_MAD
),
3305 swizzle(src(temp_pos
), 3, 3, 3, 3),
3310 /* Also write to depth value */
3311 if (!submit_op3( emit
,
3312 inst_token(SVGA3DOP_MAD
),
3313 writemask(depth
, TGSI_WRITEMASK_Z
),
3314 swizzle(src(temp_pos
), 3, 3, 3, 3),
3320 SVGA3dShaderDestToken temp_pos
= emit
->temp_pos
;
3321 SVGA3dShaderDestToken depth
= emit
->depth_pos
;
3322 SVGA3dShaderDestToken pos
= emit
->true_pos
;
3323 struct src_register imm_0055
= emit
->imm_0055
;
3325 /* Adjust GL clipping coordinate space to hardware (D3D-style):
3327 * DP4 temp_pos.z, {0,0,.5,.5}, temp_pos
3328 * MOV result.position, temp_pos
3330 if (!submit_op2( emit
,
3331 inst_token(SVGA3DOP_DP4
),
3332 writemask(temp_pos
, TGSI_WRITEMASK_Z
),
3337 if (!submit_op1( emit
,
3338 inst_token(SVGA3DOP_MOV
),
3343 /* Move the manipulated depth into the extra texcoord reg */
3344 if (!submit_op1( emit
,
3345 inst_token(SVGA3DOP_MOV
),
3346 writemask(depth
, TGSI_WRITEMASK_ZW
),
3356 * For the pixel shader: emit the code which chooses the front
3357 * or back face color depending on triangle orientation.
3358 * This happens at the top of the fragment shader.
3361 * 1: COLOR = FrontColor;
3363 * 3: COLOR = BackColor;
3367 emit_light_twoside(struct svga_shader_emitter
*emit
)
3369 struct src_register vface
, zero
;
3370 struct src_register front
[2];
3371 struct src_register back
[2];
3372 SVGA3dShaderDestToken color
[2];
3373 int count
= emit
->internal_color_count
;
3375 SVGA3dShaderInstToken if_token
;
3380 vface
= get_vface( emit
);
3381 zero
= get_zero_immediate(emit
);
3383 /* Can't use get_temp() to allocate the color reg as such
3384 * temporaries will be reclaimed after each instruction by the call
3385 * to reset_temp_regs().
3387 for (i
= 0; i
< count
; i
++) {
3388 color
[i
] = dst_register( SVGA3DREG_TEMP
, emit
->nr_hw_temp
++ );
3389 front
[i
] = emit
->input_map
[emit
->internal_color_idx
[i
]];
3391 /* Back is always the next input:
3394 back
[i
].base
.num
= front
[i
].base
.num
+ 1;
3396 /* Reassign the input_map to the actual front-face color:
3398 emit
->input_map
[emit
->internal_color_idx
[i
]] = src(color
[i
]);
3401 if_token
= inst_token( SVGA3DOP_IFC
);
3403 if (emit
->key
.fs
.front_ccw
)
3404 if_token
.control
= SVGA3DOPCOMP_LT
;
3406 if_token
.control
= SVGA3DOPCOMP_GT
;
3408 if (!(emit_instruction( emit
, if_token
) &&
3409 emit_src( emit
, vface
) &&
3410 emit_src( emit
, zero
) ))
3413 for (i
= 0; i
< count
; i
++) {
3414 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), color
[i
], front
[i
] ))
3418 if (!(emit_instruction( emit
, inst_token( SVGA3DOP_ELSE
))))
3421 for (i
= 0; i
< count
; i
++) {
3422 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), color
[i
], back
[i
] ))
3426 if (!emit_instruction( emit
, inst_token( SVGA3DOP_ENDIF
) ))
3434 * Emit special setup code for the front/back face register in the FS.
3435 * 0: SETP_GT TEMP, VFACE, 0
3436 * where TEMP is a fake frontface register
3439 emit_frontface(struct svga_shader_emitter
*emit
)
3441 struct src_register vface
;
3442 SVGA3dShaderDestToken temp
;
3443 struct src_register pass
, fail
;
3445 vface
= get_vface( emit
);
3447 /* Can't use get_temp() to allocate the fake frontface reg as such
3448 * temporaries will be reclaimed after each instruction by the call
3449 * to reset_temp_regs().
3451 temp
= dst_register( SVGA3DREG_TEMP
,
3452 emit
->nr_hw_temp
++ );
3454 if (emit
->key
.fs
.front_ccw
) {
3455 pass
= get_zero_immediate(emit
);
3456 fail
= get_one_immediate(emit
);
3458 pass
= get_one_immediate(emit
);
3459 fail
= get_zero_immediate(emit
);
3462 if (!emit_conditional(emit
, PIPE_FUNC_GREATER
,
3463 temp
, vface
, get_zero_immediate(emit
),
3467 /* Reassign the input_map to the actual front-face color:
3469 emit
->input_map
[emit
->internal_frontface_idx
] = src(temp
);
3476 * Emit code to invert the T component of the incoming texture coordinate.
3477 * This is used for drawing point sprites when
3478 * pipe_rasterizer_state::sprite_coord_mode == PIPE_SPRITE_COORD_LOWER_LEFT.
3481 emit_inverted_texcoords(struct svga_shader_emitter
*emit
)
3483 unsigned inverted_texcoords
= emit
->inverted_texcoords
;
3485 while (inverted_texcoords
) {
3486 const unsigned unit
= ffs(inverted_texcoords
) - 1;
3488 assert(emit
->inverted_texcoords
& (1 << unit
));
3490 assert(unit
< Elements(emit
->ps_true_texcoord
));
3492 assert(unit
< Elements(emit
->ps_inverted_texcoord_input
));
3494 assert(emit
->ps_inverted_texcoord_input
[unit
]
3495 < Elements(emit
->input_map
));
3497 /* inverted = coord * (1, -1, 1, 1) + (0, 1, 0, 0) */
3498 if (!submit_op3(emit
,
3499 inst_token(SVGA3DOP_MAD
),
3500 dst(emit
->ps_inverted_texcoord
[unit
]),
3501 emit
->ps_true_texcoord
[unit
],
3502 get_immediate(emit
, 1.0f
, -1.0f
, 1.0f
, 1.0f
),
3503 get_immediate(emit
, 0.0f
, 1.0f
, 0.0f
, 0.0f
)))
3506 /* Reassign the input_map entry to the new texcoord register */
3507 emit
->input_map
[emit
->ps_inverted_texcoord_input
[unit
]] =
3508 emit
->ps_inverted_texcoord
[unit
];
3510 inverted_texcoords
&= ~(1 << unit
);
3518 * Emit code to adjust vertex shader inputs/attributes:
3519 * - Change range from [0,1] to [-1,1] (for normalized byte/short attribs).
3520 * - Set attrib W component = 1.
3523 emit_adjusted_vertex_attribs(struct svga_shader_emitter
*emit
)
3525 unsigned adjust_mask
= (emit
->key
.vs
.adjust_attrib_range
|
3526 emit
->key
.vs
.adjust_attrib_w_1
);
3528 while (adjust_mask
) {
3529 /* Adjust vertex attrib range and/or set W component = 1 */
3530 const unsigned index
= u_bit_scan(&adjust_mask
);
3531 struct src_register tmp
;
3533 /* allocate a temp reg */
3534 tmp
= src_register(SVGA3DREG_TEMP
, emit
->nr_hw_temp
);
3537 if (emit
->key
.vs
.adjust_attrib_range
& (1 << index
)) {
3538 /* The vertex input/attribute is supposed to be a signed value in
3539 * the range [-1,1] but we actually fetched/converted it to the
3540 * range [0,1]. This most likely happens when the app specifies a
3541 * signed byte attribute but we interpreted it as unsigned bytes.
3542 * See also svga_translate_vertex_format().
3544 * Here, we emit some extra instructions to adjust
3545 * the attribute values from [0,1] to [-1,1].
3547 * The adjustment we implement is:
3548 * new_attrib = attrib * 2.0;
3549 * if (attrib >= 0.5)
3550 * new_attrib = new_attrib - 2.0;
3551 * This isn't exactly right (it's off by a bit or so) but close enough.
3553 SVGA3dShaderDestToken pred_reg
= dst_register(SVGA3DREG_PREDICATE
, 0);
3555 /* tmp = attrib * 2.0 */
3556 if (!submit_op2(emit
,
3557 inst_token(SVGA3DOP_MUL
),
3559 emit
->input_map
[index
],
3560 get_two_immediate(emit
)))
3563 /* pred = (attrib >= 0.5) */
3564 if (!submit_op2(emit
,
3565 inst_token_setp(SVGA3DOPCOMP_GE
),
3567 emit
->input_map
[index
], /* vert attrib */
3568 get_half_immediate(emit
))) /* 0.5 */
3571 /* sub(pred) tmp, tmp, 2.0 */
3572 if (!submit_op3(emit
,
3573 inst_token_predicated(SVGA3DOP_SUB
),
3577 get_two_immediate(emit
)))
3581 /* just copy the vertex input attrib to the temp register */
3582 if (!submit_op1(emit
,
3583 inst_token(SVGA3DOP_MOV
),
3585 emit
->input_map
[index
]))
3589 if (emit
->key
.vs
.adjust_attrib_w_1
& (1 << index
)) {
3590 /* move 1 into W position of tmp */
3591 if (!submit_op1(emit
,
3592 inst_token(SVGA3DOP_MOV
),
3593 writemask(dst(tmp
), TGSI_WRITEMASK_W
),
3594 get_one_immediate(emit
)))
3598 /* Reassign the input_map entry to the new tmp register */
3599 emit
->input_map
[index
] = tmp
;
3607 * Determine if we need to create the "common" immediate value which is
3608 * used for generating useful vector constants such as {0,0,0,0} and
3610 * We could just do this all the time except that we want to conserve
3611 * registers whenever possible.
3614 needs_to_create_common_immediate(const struct svga_shader_emitter
*emit
)
3618 if (emit
->unit
== PIPE_SHADER_FRAGMENT
) {
3619 if (emit
->key
.fs
.light_twoside
)
3622 if (emit
->key
.fs
.white_fragments
)
3625 if (emit
->emit_frontface
)
3628 if (emit
->info
.opcode_count
[TGSI_OPCODE_DST
] >= 1 ||
3629 emit
->info
.opcode_count
[TGSI_OPCODE_SSG
] >= 1 ||
3630 emit
->info
.opcode_count
[TGSI_OPCODE_LIT
] >= 1)
3633 if (emit
->inverted_texcoords
)
3636 /* look for any PIPE_SWIZZLE_ZERO/ONE terms */
3637 for (i
= 0; i
< emit
->key
.num_textures
; i
++) {
3638 if (emit
->key
.tex
[i
].swizzle_r
> PIPE_SWIZZLE_ALPHA
||
3639 emit
->key
.tex
[i
].swizzle_g
> PIPE_SWIZZLE_ALPHA
||
3640 emit
->key
.tex
[i
].swizzle_b
> PIPE_SWIZZLE_ALPHA
||
3641 emit
->key
.tex
[i
].swizzle_a
> PIPE_SWIZZLE_ALPHA
)
3645 for (i
= 0; i
< emit
->key
.num_textures
; i
++) {
3646 if (emit
->key
.tex
[i
].compare_mode
3647 == PIPE_TEX_COMPARE_R_TO_TEXTURE
)
3651 else if (emit
->unit
== PIPE_SHADER_VERTEX
) {
3652 if (emit
->info
.opcode_count
[TGSI_OPCODE_CMP
] >= 1)
3654 if (emit
->key
.vs
.adjust_attrib_range
||
3655 emit
->key
.vs
.adjust_attrib_w_1
)
3659 if (emit
->info
.opcode_count
[TGSI_OPCODE_IF
] >= 1 ||
3660 emit
->info
.opcode_count
[TGSI_OPCODE_BGNLOOP
] >= 1 ||
3661 emit
->info
.opcode_count
[TGSI_OPCODE_DDX
] >= 1 ||
3662 emit
->info
.opcode_count
[TGSI_OPCODE_DDY
] >= 1 ||
3663 emit
->info
.opcode_count
[TGSI_OPCODE_ROUND
] >= 1 ||
3664 emit
->info
.opcode_count
[TGSI_OPCODE_SGE
] >= 1 ||
3665 emit
->info
.opcode_count
[TGSI_OPCODE_SGT
] >= 1 ||
3666 emit
->info
.opcode_count
[TGSI_OPCODE_SLE
] >= 1 ||
3667 emit
->info
.opcode_count
[TGSI_OPCODE_SLT
] >= 1 ||
3668 emit
->info
.opcode_count
[TGSI_OPCODE_SNE
] >= 1 ||
3669 emit
->info
.opcode_count
[TGSI_OPCODE_SEQ
] >= 1 ||
3670 emit
->info
.opcode_count
[TGSI_OPCODE_EXP
] >= 1 ||
3671 emit
->info
.opcode_count
[TGSI_OPCODE_LOG
] >= 1 ||
3672 emit
->info
.opcode_count
[TGSI_OPCODE_XPD
] >= 1 ||
3673 emit
->info
.opcode_count
[TGSI_OPCODE_KILL
] >= 1)
3681 * Do we need to create a looping constant?
3684 needs_to_create_loop_const(const struct svga_shader_emitter
*emit
)
3686 return (emit
->info
.opcode_count
[TGSI_OPCODE_BGNLOOP
] >= 1);
3691 needs_to_create_arl_consts(const struct svga_shader_emitter
*emit
)
3693 return (emit
->num_arl_consts
> 0);
3698 pre_parse_add_indirect( struct svga_shader_emitter
*emit
,
3699 int num
, int current_arl
)
3704 for (i
= 0; i
< emit
->num_arl_consts
; ++i
) {
3705 if (emit
->arl_consts
[i
].arl_num
== current_arl
)
3709 if (emit
->num_arl_consts
== i
) {
3710 ++emit
->num_arl_consts
;
3712 emit
->arl_consts
[i
].number
= (emit
->arl_consts
[i
].number
> num
) ?
3714 emit
->arl_consts
[i
].number
;
3715 emit
->arl_consts
[i
].arl_num
= current_arl
;
3721 pre_parse_instruction( struct svga_shader_emitter
*emit
,
3722 const struct tgsi_full_instruction
*insn
,
3725 if (insn
->Src
[0].Register
.Indirect
&&
3726 insn
->Src
[0].Indirect
.File
== TGSI_FILE_ADDRESS
) {
3727 const struct tgsi_full_src_register
*reg
= &insn
->Src
[0];
3728 if (reg
->Register
.Index
< 0) {
3729 pre_parse_add_indirect(emit
, reg
->Register
.Index
, current_arl
);
3733 if (insn
->Src
[1].Register
.Indirect
&&
3734 insn
->Src
[1].Indirect
.File
== TGSI_FILE_ADDRESS
) {
3735 const struct tgsi_full_src_register
*reg
= &insn
->Src
[1];
3736 if (reg
->Register
.Index
< 0) {
3737 pre_parse_add_indirect(emit
, reg
->Register
.Index
, current_arl
);
3741 if (insn
->Src
[2].Register
.Indirect
&&
3742 insn
->Src
[2].Indirect
.File
== TGSI_FILE_ADDRESS
) {
3743 const struct tgsi_full_src_register
*reg
= &insn
->Src
[2];
3744 if (reg
->Register
.Index
< 0) {
3745 pre_parse_add_indirect(emit
, reg
->Register
.Index
, current_arl
);
3754 pre_parse_tokens( struct svga_shader_emitter
*emit
,
3755 const struct tgsi_token
*tokens
)
3757 struct tgsi_parse_context parse
;
3758 int current_arl
= 0;
3760 tgsi_parse_init( &parse
, tokens
);
3762 while (!tgsi_parse_end_of_tokens( &parse
)) {
3763 tgsi_parse_token( &parse
);
3764 switch (parse
.FullToken
.Token
.Type
) {
3765 case TGSI_TOKEN_TYPE_IMMEDIATE
:
3766 case TGSI_TOKEN_TYPE_DECLARATION
:
3768 case TGSI_TOKEN_TYPE_INSTRUCTION
:
3769 if (parse
.FullToken
.FullInstruction
.Instruction
.Opcode
==
3773 if (!pre_parse_instruction( emit
, &parse
.FullToken
.FullInstruction
,
3787 svga_shader_emit_helpers(struct svga_shader_emitter
*emit
)
3789 if (needs_to_create_common_immediate( emit
)) {
3790 create_common_immediate( emit
);
3792 if (needs_to_create_loop_const( emit
)) {
3793 create_loop_const( emit
);
3795 if (needs_to_create_arl_consts( emit
)) {
3796 create_arl_consts( emit
);
3799 if (emit
->unit
== PIPE_SHADER_FRAGMENT
) {
3800 if (!emit_ps_preamble( emit
))
3803 if (emit
->key
.fs
.light_twoside
) {
3804 if (!emit_light_twoside( emit
))
3807 if (emit
->emit_frontface
) {
3808 if (!emit_frontface( emit
))
3811 if (emit
->inverted_texcoords
) {
3812 if (!emit_inverted_texcoords( emit
))
3817 assert(emit
->unit
== PIPE_SHADER_VERTEX
);
3818 if (emit
->key
.vs
.adjust_attrib_range
) {
3819 if (!emit_adjusted_vertex_attribs(emit
) ||
3820 emit
->key
.vs
.adjust_attrib_w_1
) {
3831 * This is the main entrypoint into the TGSI instruction translater.
3832 * Translate TGSI shader tokens into an SVGA shader.
3835 svga_shader_emit_instructions(struct svga_shader_emitter
*emit
,
3836 const struct tgsi_token
*tokens
)
3838 struct tgsi_parse_context parse
;
3839 const struct tgsi_token
*new_tokens
= NULL
;
3841 boolean helpers_emitted
= FALSE
;
3842 unsigned line_nr
= 0;
3844 if (emit
->unit
== PIPE_SHADER_FRAGMENT
&& emit
->key
.fs
.pstipple
) {
3847 new_tokens
= util_pstipple_create_fragment_shader(tokens
, &unit
, 0);
3850 /* Setup texture state for stipple */
3851 emit
->key
.tex
[unit
].texture_target
= PIPE_TEXTURE_2D
;
3852 emit
->key
.tex
[unit
].swizzle_r
= TGSI_SWIZZLE_X
;
3853 emit
->key
.tex
[unit
].swizzle_g
= TGSI_SWIZZLE_Y
;
3854 emit
->key
.tex
[unit
].swizzle_b
= TGSI_SWIZZLE_Z
;
3855 emit
->key
.tex
[unit
].swizzle_a
= TGSI_SWIZZLE_W
;
3857 emit
->pstipple_sampler_unit
= unit
;
3859 tokens
= new_tokens
;
3863 tgsi_parse_init( &parse
, tokens
);
3864 emit
->internal_imm_count
= 0;
3866 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
3867 ret
= emit_vs_preamble( emit
);
3872 pre_parse_tokens(emit
, tokens
);
3874 while (!tgsi_parse_end_of_tokens( &parse
)) {
3875 tgsi_parse_token( &parse
);
3877 switch (parse
.FullToken
.Token
.Type
) {
3878 case TGSI_TOKEN_TYPE_IMMEDIATE
:
3879 ret
= svga_emit_immediate( emit
, &parse
.FullToken
.FullImmediate
);
3884 case TGSI_TOKEN_TYPE_DECLARATION
:
3885 ret
= svga_translate_decl_sm30( emit
, &parse
.FullToken
.FullDeclaration
);
3890 case TGSI_TOKEN_TYPE_INSTRUCTION
:
3891 if (!helpers_emitted
) {
3892 if (!svga_shader_emit_helpers( emit
))
3894 helpers_emitted
= TRUE
;
3896 ret
= svga_emit_instruction( emit
,
3898 &parse
.FullToken
.FullInstruction
);
3906 reset_temp_regs( emit
);
3909 /* Need to terminate the current subroutine. Note that the
3910 * hardware doesn't tolerate shaders without sub-routines
3911 * terminating with RET+END.
3913 if (!emit
->in_main_func
) {
3914 ret
= emit_instruction( emit
, inst_token( SVGA3DOP_RET
) );
3919 assert(emit
->dynamic_branching_level
== 0);
3921 /* Need to terminate the whole shader:
3923 ret
= emit_instruction( emit
, inst_token( SVGA3DOP_END
) );
3928 tgsi_parse_free( &parse
);
3930 tgsi_free_tokens(new_tokens
);