1 /**********************************************************
2 * Copyright 2008-2009 VMware, Inc. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 **********************************************************/
27 #include "pipe/p_shader_tokens.h"
28 #include "tgsi/tgsi_dump.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/u_memory.h"
31 #include "util/u_math.h"
33 #include "svga_tgsi_emit.h"
34 #include "svga_context.h"
37 static boolean
emit_vs_postamble( struct svga_shader_emitter
*emit
);
38 static boolean
emit_ps_postamble( struct svga_shader_emitter
*emit
);
42 translate_opcode(uint opcode
)
45 case TGSI_OPCODE_ABS
: return SVGA3DOP_ABS
;
46 case TGSI_OPCODE_ADD
: return SVGA3DOP_ADD
;
47 case TGSI_OPCODE_DP2A
: return SVGA3DOP_DP2ADD
;
48 case TGSI_OPCODE_DP3
: return SVGA3DOP_DP3
;
49 case TGSI_OPCODE_DP4
: return SVGA3DOP_DP4
;
50 case TGSI_OPCODE_FRC
: return SVGA3DOP_FRC
;
51 case TGSI_OPCODE_MAD
: return SVGA3DOP_MAD
;
52 case TGSI_OPCODE_MAX
: return SVGA3DOP_MAX
;
53 case TGSI_OPCODE_MIN
: return SVGA3DOP_MIN
;
54 case TGSI_OPCODE_MOV
: return SVGA3DOP_MOV
;
55 case TGSI_OPCODE_MUL
: return SVGA3DOP_MUL
;
56 case TGSI_OPCODE_NOP
: return SVGA3DOP_NOP
;
57 case TGSI_OPCODE_NRM4
: return SVGA3DOP_NRM
;
59 assert(!"svga: unexpected opcode in translate_opcode()");
60 return SVGA3DOP_LAST_INST
;
66 translate_file(unsigned file
)
69 case TGSI_FILE_TEMPORARY
: return SVGA3DREG_TEMP
;
70 case TGSI_FILE_INPUT
: return SVGA3DREG_INPUT
;
71 case TGSI_FILE_OUTPUT
: return SVGA3DREG_OUTPUT
; /* VS3.0+ only */
72 case TGSI_FILE_IMMEDIATE
: return SVGA3DREG_CONST
;
73 case TGSI_FILE_CONSTANT
: return SVGA3DREG_CONST
;
74 case TGSI_FILE_SAMPLER
: return SVGA3DREG_SAMPLER
;
75 case TGSI_FILE_ADDRESS
: return SVGA3DREG_ADDR
;
77 assert(!"svga: unexpected register file in translate_file()");
78 return SVGA3DREG_TEMP
;
84 * Translate a TGSI destination register to an SVGA3DShaderDestToken.
85 * \param insn the TGSI instruction
86 * \param idx which TGSI dest register to translate (usually (always?) zero)
88 static SVGA3dShaderDestToken
89 translate_dst_register( struct svga_shader_emitter
*emit
,
90 const struct tgsi_full_instruction
*insn
,
93 const struct tgsi_full_dst_register
*reg
= &insn
->Dst
[idx
];
94 SVGA3dShaderDestToken dest
;
96 switch (reg
->Register
.File
) {
97 case TGSI_FILE_OUTPUT
:
98 /* Output registers encode semantic information in their name.
99 * Need to lookup a table built at decl time:
101 dest
= emit
->output_map
[reg
->Register
.Index
];
106 unsigned index
= reg
->Register
.Index
;
107 assert(index
< SVGA3D_TEMPREG_MAX
);
108 index
= MIN2(index
, SVGA3D_TEMPREG_MAX
- 1);
109 dest
= dst_register(translate_file(reg
->Register
.File
), index
);
114 if (reg
->Register
.Indirect
) {
115 debug_warning("Indirect indexing of dest registers is not supported!\n");
118 dest
.mask
= reg
->Register
.WriteMask
;
121 if (insn
->Instruction
.Saturate
)
122 dest
.dstMod
= SVGA3DDSTMOD_SATURATE
;
129 * Apply a swizzle to a src_register, returning a new src_register
130 * Ex: swizzle(SRC.ZZYY, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_X, SWIZZLE_Y)
131 * would return SRC.YYZZ
133 static struct src_register
134 swizzle(struct src_register src
,
135 unsigned x
, unsigned y
, unsigned z
, unsigned w
)
141 x
= (src
.base
.swizzle
>> (x
* 2)) & 0x3;
142 y
= (src
.base
.swizzle
>> (y
* 2)) & 0x3;
143 z
= (src
.base
.swizzle
>> (z
* 2)) & 0x3;
144 w
= (src
.base
.swizzle
>> (w
* 2)) & 0x3;
146 src
.base
.swizzle
= TRANSLATE_SWIZZLE(x
, y
, z
, w
);
153 * Apply a "scalar" swizzle to a src_register returning a new
154 * src_register where all the swizzle terms are the same.
155 * Ex: scalar(SRC.WZYX, SWIZZLE_Y) would return SRC.ZZZZ
157 static struct src_register
158 scalar(struct src_register src
, unsigned comp
)
161 return swizzle( src
, comp
, comp
, comp
, comp
);
166 svga_arl_needs_adjustment( const struct svga_shader_emitter
*emit
)
170 for (i
= 0; i
< emit
->num_arl_consts
; ++i
) {
171 if (emit
->arl_consts
[i
].arl_num
== emit
->current_arl
)
179 svga_arl_adjustment( const struct svga_shader_emitter
*emit
)
183 for (i
= 0; i
< emit
->num_arl_consts
; ++i
) {
184 if (emit
->arl_consts
[i
].arl_num
== emit
->current_arl
)
185 return emit
->arl_consts
[i
].number
;
192 * Translate a TGSI src register to a src_register.
194 static struct src_register
195 translate_src_register( const struct svga_shader_emitter
*emit
,
196 const struct tgsi_full_src_register
*reg
)
198 struct src_register src
;
200 switch (reg
->Register
.File
) {
201 case TGSI_FILE_INPUT
:
202 /* Input registers are referred to by their semantic name rather
203 * than by index. Use the mapping build up from the decls:
205 src
= emit
->input_map
[reg
->Register
.Index
];
208 case TGSI_FILE_IMMEDIATE
:
209 /* Immediates are appended after TGSI constants in the D3D
212 src
= src_register( translate_file( reg
->Register
.File
),
213 reg
->Register
.Index
+ emit
->imm_start
);
217 src
= src_register( translate_file( reg
->Register
.File
),
218 reg
->Register
.Index
);
222 /* Indirect addressing.
224 if (reg
->Register
.Indirect
) {
225 if (emit
->unit
== PIPE_SHADER_FRAGMENT
) {
226 /* Pixel shaders have only loop registers for relative
227 * addressing into inputs. Ignore the redundant address
228 * register, the contents of aL should be in sync with it.
230 if (reg
->Register
.File
== TGSI_FILE_INPUT
) {
231 src
.base
.relAddr
= 1;
232 src
.indirect
= src_token(SVGA3DREG_LOOP
, 0);
236 /* Constant buffers only.
238 if (reg
->Register
.File
== TGSI_FILE_CONSTANT
) {
239 /* we shift the offset towards the minimum */
240 if (svga_arl_needs_adjustment( emit
)) {
241 src
.base
.num
-= svga_arl_adjustment( emit
);
243 src
.base
.relAddr
= 1;
245 /* Not really sure what should go in the second token:
247 src
.indirect
= src_token( SVGA3DREG_ADDR
,
248 reg
->Indirect
.Index
);
250 src
.indirect
.swizzle
= SWIZZLE_XXXX
;
256 reg
->Register
.SwizzleX
,
257 reg
->Register
.SwizzleY
,
258 reg
->Register
.SwizzleZ
,
259 reg
->Register
.SwizzleW
);
261 /* src.mod isn't a bitfield, unfortunately:
262 * See tgsi_util_get_full_src_register_sign_mode for implementation details.
264 if (reg
->Register
.Absolute
) {
265 if (reg
->Register
.Negate
)
266 src
.base
.srcMod
= SVGA3DSRCMOD_ABSNEG
;
268 src
.base
.srcMod
= SVGA3DSRCMOD_ABS
;
271 if (reg
->Register
.Negate
)
272 src
.base
.srcMod
= SVGA3DSRCMOD_NEG
;
274 src
.base
.srcMod
= SVGA3DSRCMOD_NONE
;
282 * Get a temporary register.
283 * Note: if we exceed the temporary register limit we just use
284 * register SVGA3D_TEMPREG_MAX - 1.
286 static SVGA3dShaderDestToken
287 get_temp( struct svga_shader_emitter
*emit
)
289 int i
= emit
->nr_hw_temp
+ emit
->internal_temp_count
++;
290 if (i
>= SVGA3D_TEMPREG_MAX
) {
291 debug_warn_once("svga: Too many temporary registers used in shader\n");
292 i
= SVGA3D_TEMPREG_MAX
- 1;
294 return dst_register( SVGA3DREG_TEMP
, i
);
299 * Release a single temp. Currently only effective if it was the last
300 * allocated temp, otherwise release will be delayed until the next
301 * call to reset_temp_regs().
304 release_temp( struct svga_shader_emitter
*emit
,
305 SVGA3dShaderDestToken temp
)
307 if (temp
.num
== emit
->internal_temp_count
- 1)
308 emit
->internal_temp_count
--;
316 reset_temp_regs(struct svga_shader_emitter
*emit
)
318 emit
->internal_temp_count
= 0;
322 /** Emit bytecode for a src_register */
324 emit_src(struct svga_shader_emitter
*emit
, const struct src_register src
)
326 if (src
.base
.relAddr
) {
327 assert(src
.base
.reserved0
);
328 assert(src
.indirect
.reserved0
);
329 return (svga_shader_emit_dword( emit
, src
.base
.value
) &&
330 svga_shader_emit_dword( emit
, src
.indirect
.value
));
333 assert(src
.base
.reserved0
);
334 return svga_shader_emit_dword( emit
, src
.base
.value
);
339 /** Emit bytecode for a dst_register */
341 emit_dst(struct svga_shader_emitter
*emit
, SVGA3dShaderDestToken dest
)
343 assert(dest
.reserved0
);
345 return svga_shader_emit_dword( emit
, dest
.value
);
349 /** Emit bytecode for a 1-operand instruction */
351 emit_op1(struct svga_shader_emitter
*emit
,
352 SVGA3dShaderInstToken inst
,
353 SVGA3dShaderDestToken dest
,
354 struct src_register src0
)
356 return (emit_instruction(emit
, inst
) &&
357 emit_dst(emit
, dest
) &&
358 emit_src(emit
, src0
));
362 /** Emit bytecode for a 2-operand instruction */
364 emit_op2(struct svga_shader_emitter
*emit
,
365 SVGA3dShaderInstToken inst
,
366 SVGA3dShaderDestToken dest
,
367 struct src_register src0
,
368 struct src_register src1
)
370 return (emit_instruction(emit
, inst
) &&
371 emit_dst(emit
, dest
) &&
372 emit_src(emit
, src0
) &&
373 emit_src(emit
, src1
));
377 /** Emit bytecode for a 3-operand instruction */
379 emit_op3(struct svga_shader_emitter
*emit
,
380 SVGA3dShaderInstToken inst
,
381 SVGA3dShaderDestToken dest
,
382 struct src_register src0
,
383 struct src_register src1
,
384 struct src_register src2
)
386 return (emit_instruction(emit
, inst
) &&
387 emit_dst(emit
, dest
) &&
388 emit_src(emit
, src0
) &&
389 emit_src(emit
, src1
) &&
390 emit_src(emit
, src2
));
394 /** Emit bytecode for a 4-operand instruction */
396 emit_op4(struct svga_shader_emitter
*emit
,
397 SVGA3dShaderInstToken inst
,
398 SVGA3dShaderDestToken dest
,
399 struct src_register src0
,
400 struct src_register src1
,
401 struct src_register src2
,
402 struct src_register src3
)
404 return (emit_instruction(emit
, inst
) &&
405 emit_dst(emit
, dest
) &&
406 emit_src(emit
, src0
) &&
407 emit_src(emit
, src1
) &&
408 emit_src(emit
, src2
) &&
409 emit_src(emit
, src3
));
414 * Apply the absolute value modifier to the given src_register, returning
415 * a new src_register.
417 static struct src_register
418 absolute(struct src_register src
)
420 src
.base
.srcMod
= SVGA3DSRCMOD_ABS
;
426 * Apply the negation modifier to the given src_register, returning
427 * a new src_register.
429 static struct src_register
430 negate(struct src_register src
)
432 switch (src
.base
.srcMod
) {
433 case SVGA3DSRCMOD_ABS
:
434 src
.base
.srcMod
= SVGA3DSRCMOD_ABSNEG
;
436 case SVGA3DSRCMOD_ABSNEG
:
437 src
.base
.srcMod
= SVGA3DSRCMOD_ABS
;
439 case SVGA3DSRCMOD_NEG
:
440 src
.base
.srcMod
= SVGA3DSRCMOD_NONE
;
442 case SVGA3DSRCMOD_NONE
:
443 src
.base
.srcMod
= SVGA3DSRCMOD_NEG
;
451 /* Replace the src with the temporary specified in the dst, but copying
452 * only the necessary channels, and preserving the original swizzle (which is
453 * important given that several opcodes have constraints in the allowed
457 emit_repl(struct svga_shader_emitter
*emit
,
458 SVGA3dShaderDestToken dst
,
459 struct src_register
*src0
)
461 unsigned src0_swizzle
;
464 assert(SVGA3dShaderGetRegType(dst
.value
) == SVGA3DREG_TEMP
);
466 src0_swizzle
= src0
->base
.swizzle
;
469 for (chan
= 0; chan
< 4; ++chan
) {
470 unsigned swizzle
= (src0_swizzle
>> (chan
*2)) & 0x3;
471 dst
.mask
|= 1 << swizzle
;
475 src0
->base
.swizzle
= SVGA3DSWIZZLE_NONE
;
477 if (!emit_op1( emit
, inst_token( SVGA3DOP_MOV
), dst
, *src0
))
481 src0
->base
.swizzle
= src0_swizzle
;
488 * Submit/emit an instruction with zero operands.
491 submit_op0(struct svga_shader_emitter
*emit
,
492 SVGA3dShaderInstToken inst
,
493 SVGA3dShaderDestToken dest
)
495 return (emit_instruction( emit
, inst
) &&
496 emit_dst( emit
, dest
));
501 * Submit/emit an instruction with one operand.
504 submit_op1(struct svga_shader_emitter
*emit
,
505 SVGA3dShaderInstToken inst
,
506 SVGA3dShaderDestToken dest
,
507 struct src_register src0
)
509 return emit_op1( emit
, inst
, dest
, src0
);
514 * Submit/emit an instruction with two operands.
516 * SVGA shaders may not refer to >1 constant register in a single
517 * instruction. This function checks for that usage and inserts a
518 * move to temporary if detected.
520 * The same applies to input registers -- at most a single input
521 * register may be read by any instruction.
524 submit_op2(struct svga_shader_emitter
*emit
,
525 SVGA3dShaderInstToken inst
,
526 SVGA3dShaderDestToken dest
,
527 struct src_register src0
,
528 struct src_register src1
)
530 SVGA3dShaderDestToken temp
;
531 SVGA3dShaderRegType type0
, type1
;
532 boolean need_temp
= FALSE
;
535 type0
= SVGA3dShaderGetRegType( src0
.base
.value
);
536 type1
= SVGA3dShaderGetRegType( src1
.base
.value
);
538 if (type0
== SVGA3DREG_CONST
&&
539 type1
== SVGA3DREG_CONST
&&
540 src0
.base
.num
!= src1
.base
.num
)
543 if (type0
== SVGA3DREG_INPUT
&&
544 type1
== SVGA3DREG_INPUT
&&
545 src0
.base
.num
!= src1
.base
.num
)
549 temp
= get_temp( emit
);
551 if (!emit_repl( emit
, temp
, &src0
))
555 if (!emit_op2( emit
, inst
, dest
, src0
, src1
))
559 release_temp( emit
, temp
);
566 * Submit/emit an instruction with three operands.
568 * SVGA shaders may not refer to >1 constant register in a single
569 * instruction. This function checks for that usage and inserts a
570 * move to temporary if detected.
573 submit_op3(struct svga_shader_emitter
*emit
,
574 SVGA3dShaderInstToken inst
,
575 SVGA3dShaderDestToken dest
,
576 struct src_register src0
,
577 struct src_register src1
,
578 struct src_register src2
)
580 SVGA3dShaderDestToken temp0
;
581 SVGA3dShaderDestToken temp1
;
582 boolean need_temp0
= FALSE
;
583 boolean need_temp1
= FALSE
;
584 SVGA3dShaderRegType type0
, type1
, type2
;
588 type0
= SVGA3dShaderGetRegType( src0
.base
.value
);
589 type1
= SVGA3dShaderGetRegType( src1
.base
.value
);
590 type2
= SVGA3dShaderGetRegType( src2
.base
.value
);
592 if (inst
.op
!= SVGA3DOP_SINCOS
) {
593 if (type0
== SVGA3DREG_CONST
&&
594 ((type1
== SVGA3DREG_CONST
&& src0
.base
.num
!= src1
.base
.num
) ||
595 (type2
== SVGA3DREG_CONST
&& src0
.base
.num
!= src2
.base
.num
)))
598 if (type1
== SVGA3DREG_CONST
&&
599 (type2
== SVGA3DREG_CONST
&& src1
.base
.num
!= src2
.base
.num
))
603 if (type0
== SVGA3DREG_INPUT
&&
604 ((type1
== SVGA3DREG_INPUT
&& src0
.base
.num
!= src1
.base
.num
) ||
605 (type2
== SVGA3DREG_INPUT
&& src0
.base
.num
!= src2
.base
.num
)))
608 if (type1
== SVGA3DREG_INPUT
&&
609 (type2
== SVGA3DREG_INPUT
&& src1
.base
.num
!= src2
.base
.num
))
613 temp0
= get_temp( emit
);
615 if (!emit_repl( emit
, temp0
, &src0
))
620 temp1
= get_temp( emit
);
622 if (!emit_repl( emit
, temp1
, &src1
))
626 if (!emit_op3( emit
, inst
, dest
, src0
, src1
, src2
))
630 release_temp( emit
, temp1
);
632 release_temp( emit
, temp0
);
638 * Submit/emit an instruction with four operands.
640 * SVGA shaders may not refer to >1 constant register in a single
641 * instruction. This function checks for that usage and inserts a
642 * move to temporary if detected.
645 submit_op4(struct svga_shader_emitter
*emit
,
646 SVGA3dShaderInstToken inst
,
647 SVGA3dShaderDestToken dest
,
648 struct src_register src0
,
649 struct src_register src1
,
650 struct src_register src2
,
651 struct src_register src3
)
653 SVGA3dShaderDestToken temp0
;
654 SVGA3dShaderDestToken temp3
;
655 boolean need_temp0
= FALSE
;
656 boolean need_temp3
= FALSE
;
657 SVGA3dShaderRegType type0
, type1
, type2
, type3
;
661 type0
= SVGA3dShaderGetRegType( src0
.base
.value
);
662 type1
= SVGA3dShaderGetRegType( src1
.base
.value
);
663 type2
= SVGA3dShaderGetRegType( src2
.base
.value
);
664 type3
= SVGA3dShaderGetRegType( src2
.base
.value
);
666 /* Make life a little easier - this is only used by the TXD
667 * instruction which is guaranteed not to have a constant/input reg
668 * in one slot at least:
670 assert(type1
== SVGA3DREG_SAMPLER
);
672 if (type0
== SVGA3DREG_CONST
&&
673 ((type3
== SVGA3DREG_CONST
&& src0
.base
.num
!= src3
.base
.num
) ||
674 (type2
== SVGA3DREG_CONST
&& src0
.base
.num
!= src2
.base
.num
)))
677 if (type3
== SVGA3DREG_CONST
&&
678 (type2
== SVGA3DREG_CONST
&& src3
.base
.num
!= src2
.base
.num
))
681 if (type0
== SVGA3DREG_INPUT
&&
682 ((type3
== SVGA3DREG_INPUT
&& src0
.base
.num
!= src3
.base
.num
) ||
683 (type2
== SVGA3DREG_INPUT
&& src0
.base
.num
!= src2
.base
.num
)))
686 if (type3
== SVGA3DREG_INPUT
&&
687 (type2
== SVGA3DREG_INPUT
&& src3
.base
.num
!= src2
.base
.num
))
691 temp0
= get_temp( emit
);
693 if (!emit_repl( emit
, temp0
, &src0
))
698 temp3
= get_temp( emit
);
700 if (!emit_repl( emit
, temp3
, &src3
))
704 if (!emit_op4( emit
, inst
, dest
, src0
, src1
, src2
, src3
))
708 release_temp( emit
, temp3
);
710 release_temp( emit
, temp0
);
716 * Do the src and dest registers refer to the same register?
719 alias_src_dst(struct src_register src
,
720 SVGA3dShaderDestToken dst
)
722 if (src
.base
.num
!= dst
.num
)
725 if (SVGA3dShaderGetRegType(dst
.value
) !=
726 SVGA3dShaderGetRegType(src
.base
.value
))
734 * Helper for emitting SVGA immediate values using the SVGA3DOP_DEF[I]
738 emit_def_const(struct svga_shader_emitter
*emit
,
739 SVGA3dShaderConstType type
,
740 unsigned idx
, float a
, float b
, float c
, float d
)
743 SVGA3dShaderInstToken opcode
;
746 case SVGA3D_CONST_TYPE_FLOAT
:
747 opcode
= inst_token( SVGA3DOP_DEF
);
748 def
.dst
= dst_register( SVGA3DREG_CONST
, idx
);
749 def
.constValues
[0] = a
;
750 def
.constValues
[1] = b
;
751 def
.constValues
[2] = c
;
752 def
.constValues
[3] = d
;
754 case SVGA3D_CONST_TYPE_INT
:
755 opcode
= inst_token( SVGA3DOP_DEFI
);
756 def
.dst
= dst_register( SVGA3DREG_CONSTINT
, idx
);
757 def
.constIValues
[0] = (int)a
;
758 def
.constIValues
[1] = (int)b
;
759 def
.constIValues
[2] = (int)c
;
760 def
.constIValues
[3] = (int)d
;
764 opcode
= inst_token( SVGA3DOP_NOP
);
768 if (!emit_instruction(emit
, opcode
) ||
769 !svga_shader_emit_dwords( emit
, def
.values
, Elements(def
.values
)))
777 create_loop_const( struct svga_shader_emitter
*emit
)
779 unsigned idx
= emit
->nr_hw_int_const
++;
781 if (!emit_def_const( emit
, SVGA3D_CONST_TYPE_INT
, idx
,
782 255, /* iteration count */
783 0, /* initial value */
785 0 /* not used, must be 0 */))
788 emit
->loop_const_idx
= idx
;
789 emit
->created_loop_const
= TRUE
;
795 create_arl_consts( struct svga_shader_emitter
*emit
)
799 for (i
= 0; i
< emit
->num_arl_consts
; i
+= 4) {
801 unsigned idx
= emit
->nr_hw_float_const
++;
803 for (j
= 0; j
< 4 && (j
+ i
) < emit
->num_arl_consts
; ++j
) {
804 vals
[j
] = (float) emit
->arl_consts
[i
+ j
].number
;
805 emit
->arl_consts
[i
+ j
].idx
= idx
;
808 emit
->arl_consts
[i
+ 0].swizzle
= TGSI_SWIZZLE_X
;
811 emit
->arl_consts
[i
+ 0].swizzle
= TGSI_SWIZZLE_Y
;
814 emit
->arl_consts
[i
+ 0].swizzle
= TGSI_SWIZZLE_Z
;
817 emit
->arl_consts
[i
+ 0].swizzle
= TGSI_SWIZZLE_W
;
824 if (!emit_def_const( emit
, SVGA3D_CONST_TYPE_FLOAT
, idx
,
835 * Return the register which holds the pixel shaders front/back-
838 static struct src_register
839 get_vface( struct svga_shader_emitter
*emit
)
841 assert(emit
->emitted_vface
);
842 return src_register(SVGA3DREG_MISCTYPE
, SVGA3DMISCREG_FACE
);
847 * Create/emit a "common" constant with values {0, 0.5, -1, 1}.
848 * We can swizzle this to produce other useful constants such as
849 * {0, 0, 0, 0}, {1, 1, 1, 1}, etc.
852 create_common_immediate( struct svga_shader_emitter
*emit
)
854 unsigned idx
= emit
->nr_hw_float_const
++;
856 /* Emit the constant (0, 0.5, -1, 1) and use swizzling to generate
857 * other useful vectors.
859 if (!emit_def_const( emit
, SVGA3D_CONST_TYPE_FLOAT
,
860 idx
, 0.0f
, 0.5f
, -1.0f
, 1.0f
))
862 emit
->common_immediate_idx
[0] = idx
;
865 /* Emit constant {2, 0, 0, 0} (only the 2 is used for now) */
866 if (emit
->key
.vkey
.adjust_attrib_range
) {
867 if (!emit_def_const( emit
, SVGA3D_CONST_TYPE_FLOAT
,
868 idx
, 2.0f
, 0.0f
, 0.0f
, 0.0f
))
870 emit
->common_immediate_idx
[1] = idx
;
873 emit
->common_immediate_idx
[1] = -1;
876 emit
->created_common_immediate
= TRUE
;
883 * Return swizzle/position for the given value in the "common" immediate.
885 static inline unsigned
886 common_immediate_swizzle(float value
)
889 return TGSI_SWIZZLE_X
;
890 else if (value
== 0.5f
)
891 return TGSI_SWIZZLE_Y
;
892 else if (value
== -1.0f
)
893 return TGSI_SWIZZLE_Z
;
894 else if (value
== 1.0f
)
895 return TGSI_SWIZZLE_W
;
897 assert(!"illegal value in common_immediate_swizzle");
898 return TGSI_SWIZZLE_X
;
904 * Returns an immediate reg where all the terms are either 0, 1, 2 or 0.5
906 static struct src_register
907 get_immediate(struct svga_shader_emitter
*emit
,
908 float x
, float y
, float z
, float w
)
910 unsigned sx
= common_immediate_swizzle(x
);
911 unsigned sy
= common_immediate_swizzle(y
);
912 unsigned sz
= common_immediate_swizzle(z
);
913 unsigned sw
= common_immediate_swizzle(w
);
914 assert(emit
->created_common_immediate
);
915 assert(emit
->common_immediate_idx
[0] >= 0);
916 return swizzle(src_register(SVGA3DREG_CONST
, emit
->common_immediate_idx
[0]),
922 * returns {0, 0, 0, 0} immediate
924 static struct src_register
925 get_zero_immediate( struct svga_shader_emitter
*emit
)
927 assert(emit
->created_common_immediate
);
928 assert(emit
->common_immediate_idx
[0] >= 0);
929 return swizzle(src_register( SVGA3DREG_CONST
,
930 emit
->common_immediate_idx
[0]),
936 * returns {1, 1, 1, 1} immediate
938 static struct src_register
939 get_one_immediate( struct svga_shader_emitter
*emit
)
941 assert(emit
->created_common_immediate
);
942 assert(emit
->common_immediate_idx
[0] >= 0);
943 return swizzle(src_register( SVGA3DREG_CONST
,
944 emit
->common_immediate_idx
[0]),
950 * returns {0.5, 0.5, 0.5, 0.5} immediate
952 static struct src_register
953 get_half_immediate( struct svga_shader_emitter
*emit
)
955 assert(emit
->created_common_immediate
);
956 assert(emit
->common_immediate_idx
[0] >= 0);
957 return swizzle(src_register(SVGA3DREG_CONST
, emit
->common_immediate_idx
[0]),
963 * returns {2, 2, 2, 2} immediate
965 static struct src_register
966 get_two_immediate( struct svga_shader_emitter
*emit
)
968 /* Note we use the second common immediate here */
969 assert(emit
->created_common_immediate
);
970 assert(emit
->common_immediate_idx
[1] >= 0);
971 return swizzle(src_register( SVGA3DREG_CONST
,
972 emit
->common_immediate_idx
[1]),
978 * returns the loop const
980 static struct src_register
981 get_loop_const( struct svga_shader_emitter
*emit
)
983 assert(emit
->created_loop_const
);
984 assert(emit
->loop_const_idx
>= 0);
985 return src_register( SVGA3DREG_CONSTINT
,
986 emit
->loop_const_idx
);
990 static struct src_register
991 get_fake_arl_const( struct svga_shader_emitter
*emit
)
993 struct src_register reg
;
994 int idx
= 0, swizzle
= 0, i
;
996 for (i
= 0; i
< emit
->num_arl_consts
; ++ i
) {
997 if (emit
->arl_consts
[i
].arl_num
== emit
->current_arl
) {
998 idx
= emit
->arl_consts
[i
].idx
;
999 swizzle
= emit
->arl_consts
[i
].swizzle
;
1003 reg
= src_register( SVGA3DREG_CONST
, idx
);
1004 return scalar(reg
, swizzle
);
1009 * Return a register which holds the width and height of the texture
1010 * currently bound to the given sampler.
1012 static struct src_register
1013 get_tex_dimensions( struct svga_shader_emitter
*emit
, int sampler_num
)
1016 struct src_register reg
;
1018 /* the width/height indexes start right after constants */
1019 idx
= emit
->key
.fkey
.tex
[sampler_num
].width_height_idx
+
1020 emit
->info
.file_max
[TGSI_FILE_CONSTANT
] + 1;
1022 reg
= src_register( SVGA3DREG_CONST
, idx
);
1028 emit_fake_arl(struct svga_shader_emitter
*emit
,
1029 const struct tgsi_full_instruction
*insn
)
1031 const struct src_register src0
=
1032 translate_src_register(emit
, &insn
->Src
[0] );
1033 struct src_register src1
= get_fake_arl_const( emit
);
1034 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1035 SVGA3dShaderDestToken tmp
= get_temp( emit
);
1037 if (!submit_op1(emit
, inst_token( SVGA3DOP_MOV
), tmp
, src0
))
1040 if (!submit_op2( emit
, inst_token( SVGA3DOP_ADD
), tmp
, src( tmp
),
1044 /* replicate the original swizzle */
1046 src1
.base
.swizzle
= src0
.base
.swizzle
;
1048 return submit_op1( emit
, inst_token( SVGA3DOP_MOVA
),
1054 emit_if(struct svga_shader_emitter
*emit
,
1055 const struct tgsi_full_instruction
*insn
)
1057 struct src_register src0
=
1058 translate_src_register(emit
, &insn
->Src
[0]);
1059 struct src_register zero
= get_zero_immediate(emit
);
1060 SVGA3dShaderInstToken if_token
= inst_token( SVGA3DOP_IFC
);
1062 if_token
.control
= SVGA3DOPCOMPC_NE
;
1064 if (SVGA3dShaderGetRegType(src0
.base
.value
) == SVGA3DREG_CONST
) {
1066 * Max different constant registers readable per IFC instruction is 1.
1068 SVGA3dShaderDestToken tmp
= get_temp( emit
);
1070 if (!submit_op1(emit
, inst_token( SVGA3DOP_MOV
), tmp
, src0
))
1073 src0
= scalar(src( tmp
), TGSI_SWIZZLE_X
);
1076 emit
->dynamic_branching_level
++;
1078 return (emit_instruction( emit
, if_token
) &&
1079 emit_src( emit
, src0
) &&
1080 emit_src( emit
, zero
) );
1085 emit_else(struct svga_shader_emitter
*emit
,
1086 const struct tgsi_full_instruction
*insn
)
1088 return emit_instruction(emit
, inst_token(SVGA3DOP_ELSE
));
1093 emit_endif(struct svga_shader_emitter
*emit
,
1094 const struct tgsi_full_instruction
*insn
)
1096 emit
->dynamic_branching_level
--;
1098 return emit_instruction(emit
, inst_token(SVGA3DOP_ENDIF
));
1103 * Translate the following TGSI FLR instruction.
1105 * To the following SVGA3D instruction sequence.
1110 emit_floor(struct svga_shader_emitter
*emit
,
1111 const struct tgsi_full_instruction
*insn
)
1113 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1114 const struct src_register src0
=
1115 translate_src_register(emit
, &insn
->Src
[0] );
1116 SVGA3dShaderDestToken temp
= get_temp( emit
);
1119 if (!submit_op1( emit
, inst_token( SVGA3DOP_FRC
), temp
, src0
))
1122 /* SUB DST, SRC, TMP */
1123 if (!submit_op2( emit
, inst_token( SVGA3DOP_ADD
), dst
, src0
,
1124 negate( src( temp
) ) ))
1132 * Translate the following TGSI CEIL instruction.
1134 * To the following SVGA3D instruction sequence.
1139 emit_ceil(struct svga_shader_emitter
*emit
,
1140 const struct tgsi_full_instruction
*insn
)
1142 SVGA3dShaderDestToken dst
= translate_dst_register(emit
, insn
, 0);
1143 const struct src_register src0
=
1144 translate_src_register(emit
, &insn
->Src
[0]);
1145 SVGA3dShaderDestToken temp
= get_temp(emit
);
1148 if (!submit_op1(emit
, inst_token(SVGA3DOP_FRC
), temp
, negate(src0
)))
1151 /* ADD DST, SRC, TMP */
1152 if (!submit_op2(emit
, inst_token(SVGA3DOP_ADD
), dst
, src0
, src(temp
)))
1160 * Translate the following TGSI DIV instruction.
1161 * DIV DST.xy, SRC0, SRC1
1162 * To the following SVGA3D instruction sequence.
1163 * RCP TMP.x, SRC1.xxxx
1164 * RCP TMP.y, SRC1.yyyy
1165 * MUL DST.xy, SRC0, TMP
1168 emit_div(struct svga_shader_emitter
*emit
,
1169 const struct tgsi_full_instruction
*insn
)
1171 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1172 const struct src_register src0
=
1173 translate_src_register(emit
, &insn
->Src
[0] );
1174 const struct src_register src1
=
1175 translate_src_register(emit
, &insn
->Src
[1] );
1176 SVGA3dShaderDestToken temp
= get_temp( emit
);
1179 /* For each enabled element, perform a RCP instruction. Note that
1180 * RCP is scalar in SVGA3D:
1182 for (i
= 0; i
< 4; i
++) {
1183 unsigned channel
= 1 << i
;
1184 if (dst
.mask
& channel
) {
1185 /* RCP TMP.?, SRC1.???? */
1186 if (!submit_op1( emit
, inst_token( SVGA3DOP_RCP
),
1187 writemask(temp
, channel
),
1194 * MUL DST, SRC0, TMP
1196 if (!submit_op2( emit
, inst_token( SVGA3DOP_MUL
), dst
, src0
,
1205 * Translate the following TGSI DP2 instruction.
1206 * DP2 DST, SRC1, SRC2
1207 * To the following SVGA3D instruction sequence.
1208 * MUL TMP, SRC1, SRC2
1209 * ADD DST, TMP.xxxx, TMP.yyyy
1212 emit_dp2(struct svga_shader_emitter
*emit
,
1213 const struct tgsi_full_instruction
*insn
)
1215 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1216 const struct src_register src0
=
1217 translate_src_register(emit
, &insn
->Src
[0]);
1218 const struct src_register src1
=
1219 translate_src_register(emit
, &insn
->Src
[1]);
1220 SVGA3dShaderDestToken temp
= get_temp( emit
);
1221 struct src_register temp_src0
, temp_src1
;
1223 /* MUL TMP, SRC1, SRC2 */
1224 if (!submit_op2( emit
, inst_token( SVGA3DOP_MUL
), temp
, src0
, src1
))
1227 temp_src0
= scalar(src( temp
), TGSI_SWIZZLE_X
);
1228 temp_src1
= scalar(src( temp
), TGSI_SWIZZLE_Y
);
1230 /* ADD DST, TMP.xxxx, TMP.yyyy */
1231 if (!submit_op2( emit
, inst_token( SVGA3DOP_ADD
), dst
,
1232 temp_src0
, temp_src1
))
1240 * Translate the following TGSI DPH instruction.
1241 * DPH DST, SRC1, SRC2
1242 * To the following SVGA3D instruction sequence.
1243 * DP3 TMP, SRC1, SRC2
1244 * ADD DST, TMP, SRC2.wwww
1247 emit_dph(struct svga_shader_emitter
*emit
,
1248 const struct tgsi_full_instruction
*insn
)
1250 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1251 const struct src_register src0
= translate_src_register(
1252 emit
, &insn
->Src
[0] );
1253 struct src_register src1
=
1254 translate_src_register(emit
, &insn
->Src
[1]);
1255 SVGA3dShaderDestToken temp
= get_temp( emit
);
1257 /* DP3 TMP, SRC1, SRC2 */
1258 if (!submit_op2( emit
, inst_token( SVGA3DOP_DP3
), temp
, src0
, src1
))
1261 src1
= scalar(src1
, TGSI_SWIZZLE_W
);
1263 /* ADD DST, TMP, SRC2.wwww */
1264 if (!submit_op2( emit
, inst_token( SVGA3DOP_ADD
), dst
,
1265 src( temp
), src1
))
1273 * Translate the following TGSI DST instruction.
1275 * To the following SVGA3D instruction sequence.
1281 emit_nrm(struct svga_shader_emitter
*emit
,
1282 const struct tgsi_full_instruction
*insn
)
1284 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1285 const struct src_register src0
=
1286 translate_src_register(emit
, &insn
->Src
[0]);
1287 SVGA3dShaderDestToken temp
= get_temp( emit
);
1289 /* DP3 TMP, SRC, SRC */
1290 if (!submit_op2( emit
, inst_token( SVGA3DOP_DP3
), temp
, src0
, src0
))
1294 if (!submit_op1( emit
, inst_token( SVGA3DOP_RSQ
), temp
, src( temp
)))
1297 /* MUL DST, SRC, TMP */
1298 if (!submit_op2( emit
, inst_token( SVGA3DOP_MUL
), dst
,
1307 * Sine / Cosine helper function.
1310 do_emit_sincos(struct svga_shader_emitter
*emit
,
1311 SVGA3dShaderDestToken dst
,
1312 struct src_register src0
)
1314 src0
= scalar(src0
, TGSI_SWIZZLE_X
);
1315 return submit_op1(emit
, inst_token(SVGA3DOP_SINCOS
), dst
, src0
);
1320 * Translate/emit a TGSI SIN, COS or CSC instruction.
1323 emit_sincos(struct svga_shader_emitter
*emit
,
1324 const struct tgsi_full_instruction
*insn
)
1326 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1327 struct src_register src0
= translate_src_register(emit
, &insn
->Src
[0]);
1328 SVGA3dShaderDestToken temp
= get_temp( emit
);
1331 if (!do_emit_sincos(emit
, writemask(temp
, TGSI_WRITEMASK_XY
), src0
))
1335 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), dst
, src( temp
) ))
1343 * Translate TGSI SIN instruction into:
1348 emit_sin(struct svga_shader_emitter
*emit
,
1349 const struct tgsi_full_instruction
*insn
)
1351 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1352 struct src_register src0
=
1353 translate_src_register(emit
, &insn
->Src
[0] );
1354 SVGA3dShaderDestToken temp
= get_temp( emit
);
1357 if (!do_emit_sincos(emit
, writemask(temp
, TGSI_WRITEMASK_Y
), src0
))
1360 src0
= scalar(src( temp
), TGSI_SWIZZLE_Y
);
1362 /* MOV DST TMP.yyyy */
1363 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), dst
, src0
))
1371 * Translate TGSI COS instruction into:
1376 emit_cos(struct svga_shader_emitter
*emit
,
1377 const struct tgsi_full_instruction
*insn
)
1379 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1380 struct src_register src0
=
1381 translate_src_register(emit
, &insn
->Src
[0] );
1382 SVGA3dShaderDestToken temp
= get_temp( emit
);
1385 if (!do_emit_sincos( emit
, writemask(temp
, TGSI_WRITEMASK_X
), src0
))
1388 src0
= scalar(src( temp
), TGSI_SWIZZLE_X
);
1390 /* MOV DST TMP.xxxx */
1391 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), dst
, src0
))
1399 * Translate/emit TGSI SSG (Set Sign: -1, 0, +1) instruction.
1402 emit_ssg(struct svga_shader_emitter
*emit
,
1403 const struct tgsi_full_instruction
*insn
)
1405 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1406 struct src_register src0
=
1407 translate_src_register(emit
, &insn
->Src
[0] );
1408 SVGA3dShaderDestToken temp0
= get_temp( emit
);
1409 SVGA3dShaderDestToken temp1
= get_temp( emit
);
1410 struct src_register zero
, one
;
1412 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
1413 /* SGN DST, SRC0, TMP0, TMP1 */
1414 return submit_op3( emit
, inst_token( SVGA3DOP_SGN
), dst
, src0
,
1415 src( temp0
), src( temp1
) );
1418 one
= get_one_immediate(emit
);
1419 zero
= get_zero_immediate(emit
);
1421 /* CMP TMP0, SRC0, one, zero */
1422 if (!submit_op3( emit
, inst_token( SVGA3DOP_CMP
),
1423 writemask( temp0
, dst
.mask
), src0
, one
, zero
))
1426 /* CMP TMP1, negate(SRC0), negate(one), zero */
1427 if (!submit_op3( emit
, inst_token( SVGA3DOP_CMP
),
1428 writemask( temp1
, dst
.mask
), negate( src0
), negate( one
),
1432 /* ADD DST, TMP0, TMP1 */
1433 return submit_op2( emit
, inst_token( SVGA3DOP_ADD
), dst
, src( temp0
),
1439 * Translate/emit TGSI SUB instruction as:
1440 * ADD DST, SRC0, negate(SRC1)
1443 emit_sub(struct svga_shader_emitter
*emit
,
1444 const struct tgsi_full_instruction
*insn
)
1446 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1447 struct src_register src0
= translate_src_register(
1448 emit
, &insn
->Src
[0] );
1449 struct src_register src1
= translate_src_register(
1450 emit
, &insn
->Src
[1] );
1452 src1
= negate(src1
);
1454 if (!submit_op2( emit
, inst_token( SVGA3DOP_ADD
), dst
,
1463 * Translate/emit KILL_IF instruction (kill if any of X,Y,Z,W are negative).
1466 emit_kill_if(struct svga_shader_emitter
*emit
,
1467 const struct tgsi_full_instruction
*insn
)
1469 const struct tgsi_full_src_register
*reg
= &insn
->Src
[0];
1470 struct src_register src0
, srcIn
;
1471 const boolean special
= (reg
->Register
.Absolute
||
1472 reg
->Register
.Negate
||
1473 reg
->Register
.Indirect
||
1474 reg
->Register
.SwizzleX
!= 0 ||
1475 reg
->Register
.SwizzleY
!= 1 ||
1476 reg
->Register
.SwizzleZ
!= 2 ||
1477 reg
->Register
.File
!= TGSI_FILE_TEMPORARY
);
1478 SVGA3dShaderDestToken temp
;
1480 src0
= srcIn
= translate_src_register( emit
, reg
);
1483 /* need a temp reg */
1484 temp
= get_temp( emit
);
1488 /* move the source into a temp register */
1489 submit_op1(emit
, inst_token(SVGA3DOP_MOV
), temp
, src0
);
1494 /* Do the texkill by checking if any of the XYZW components are < 0.
1495 * Note that ps_2_0 and later take XYZW in consideration, while ps_1_x
1496 * only used XYZ. The MSDN documentation about this is incorrect.
1498 if (!submit_op0( emit
, inst_token( SVGA3DOP_TEXKILL
), dst(src0
) ))
1506 * Translate/emit unconditional kill instruction (usually found inside
1507 * an IF/ELSE/ENDIF block).
1510 emit_kill(struct svga_shader_emitter
*emit
,
1511 const struct tgsi_full_instruction
*insn
)
1513 SVGA3dShaderDestToken temp
;
1514 struct src_register one
= get_one_immediate(emit
);
1515 SVGA3dShaderInstToken inst
= inst_token( SVGA3DOP_TEXKILL
);
1517 /* texkill doesn't allow negation on the operand so lets move
1518 * negation of {1} to a temp register */
1519 temp
= get_temp( emit
);
1520 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), temp
,
1524 return submit_op0( emit
, inst
, temp
);
1529 * Test if r1 and r2 are the same register.
1532 same_register(struct src_register r1
, struct src_register r2
)
1534 return (r1
.base
.num
== r2
.base
.num
&&
1535 r1
.base
.type_upper
== r2
.base
.type_upper
&&
1536 r1
.base
.type_lower
== r2
.base
.type_lower
);
1542 * Implement conditionals by initializing destination reg to 'fail',
1543 * then set predicate reg with UFOP_SETP, then move 'pass' to dest
1544 * based on predicate reg.
1546 * SETP src0, cmp, src1 -- do this first to avoid aliasing problems.
1551 emit_conditional(struct svga_shader_emitter
*emit
,
1552 unsigned compare_func
,
1553 SVGA3dShaderDestToken dst
,
1554 struct src_register src0
,
1555 struct src_register src1
,
1556 struct src_register pass
,
1557 struct src_register fail
)
1559 SVGA3dShaderDestToken pred_reg
= dst_register( SVGA3DREG_PREDICATE
, 0 );
1560 SVGA3dShaderInstToken setp_token
;
1562 switch (compare_func
) {
1563 case PIPE_FUNC_NEVER
:
1564 return submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
1567 case PIPE_FUNC_LESS
:
1568 setp_token
= inst_token_setp(SVGA3DOPCOMP_LT
);
1570 case PIPE_FUNC_EQUAL
:
1571 setp_token
= inst_token_setp(SVGA3DOPCOMP_EQ
);
1573 case PIPE_FUNC_LEQUAL
:
1574 setp_token
= inst_token_setp(SVGA3DOPCOMP_LE
);
1576 case PIPE_FUNC_GREATER
:
1577 setp_token
= inst_token_setp(SVGA3DOPCOMP_GT
);
1579 case PIPE_FUNC_NOTEQUAL
:
1580 setp_token
= inst_token_setp(SVGA3DOPCOMPC_NE
);
1582 case PIPE_FUNC_GEQUAL
:
1583 setp_token
= inst_token_setp(SVGA3DOPCOMP_GE
);
1585 case PIPE_FUNC_ALWAYS
:
1586 return submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
1591 if (same_register(src(dst
), pass
)) {
1592 /* We'll get bad results if the dst and pass registers are the same
1593 * so use a temp register containing pass.
1595 SVGA3dShaderDestToken temp
= get_temp(emit
);
1596 if (!submit_op1(emit
, inst_token(SVGA3DOP_MOV
), temp
, pass
))
1601 /* SETP src0, COMPOP, src1 */
1602 if (!submit_op2( emit
, setp_token
, pred_reg
,
1607 if (!submit_op1(emit
, inst_token(SVGA3DOP_MOV
), dst
, fail
))
1610 /* MOV dst, pass (predicated)
1612 * Note that the predicate reg (and possible modifiers) is passed
1613 * as the first source argument.
1615 if (!submit_op2(emit
,
1616 inst_token_predicated(SVGA3DOP_MOV
), dst
,
1617 src(pred_reg
), pass
))
1625 * Helper for emiting 'selection' commands. Basically:
1632 emit_select(struct svga_shader_emitter
*emit
,
1633 unsigned compare_func
,
1634 SVGA3dShaderDestToken dst
,
1635 struct src_register src0
,
1636 struct src_register src1
)
1638 /* There are some SVGA instructions which implement some selects
1639 * directly, but they are only available in the vertex shader.
1641 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
1642 switch (compare_func
) {
1643 case PIPE_FUNC_GEQUAL
:
1644 return submit_op2( emit
, inst_token( SVGA3DOP_SGE
), dst
, src0
, src1
);
1645 case PIPE_FUNC_LEQUAL
:
1646 return submit_op2( emit
, inst_token( SVGA3DOP_SGE
), dst
, src1
, src0
);
1647 case PIPE_FUNC_GREATER
:
1648 return submit_op2( emit
, inst_token( SVGA3DOP_SLT
), dst
, src1
, src0
);
1649 case PIPE_FUNC_LESS
:
1650 return submit_op2( emit
, inst_token( SVGA3DOP_SLT
), dst
, src0
, src1
);
1656 /* Otherwise, need to use the setp approach:
1659 struct src_register one
, zero
;
1660 /* zero immediate is 0,0,0,1 */
1661 zero
= get_zero_immediate(emit
);
1662 one
= get_one_immediate(emit
);
1664 return emit_conditional(emit
, compare_func
, dst
, src0
, src1
, one
, zero
);
1670 * Translate/emit a TGSI SEQ, SNE, SLT, SGE, etc. instruction.
1673 emit_select_op(struct svga_shader_emitter
*emit
,
1675 const struct tgsi_full_instruction
*insn
)
1677 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1678 struct src_register src0
= translate_src_register(
1679 emit
, &insn
->Src
[0] );
1680 struct src_register src1
= translate_src_register(
1681 emit
, &insn
->Src
[1] );
1683 return emit_select( emit
, compare
, dst
, src0
, src1
);
1688 * Translate TGSI CMP instruction. Component-wise:
1689 * dst = (src0 < 0.0) ? src1 : src2
1692 emit_cmp(struct svga_shader_emitter
*emit
,
1693 const struct tgsi_full_instruction
*insn
)
1695 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1696 const struct src_register src0
=
1697 translate_src_register(emit
, &insn
->Src
[0] );
1698 const struct src_register src1
=
1699 translate_src_register(emit
, &insn
->Src
[1] );
1700 const struct src_register src2
=
1701 translate_src_register(emit
, &insn
->Src
[2] );
1703 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
1704 struct src_register zero
= get_zero_immediate(emit
);
1705 /* We used to simulate CMP with SLT+LRP. But that didn't work when
1706 * src1 or src2 was Inf/NaN. In particular, GLSL sqrt(0) failed
1707 * because it involves a CMP to handle the 0 case.
1708 * Use a conditional expression instead.
1710 return emit_conditional(emit
, PIPE_FUNC_LESS
, dst
,
1711 src0
, zero
, src1
, src2
);
1714 assert(emit
->unit
== PIPE_SHADER_FRAGMENT
);
1716 /* CMP DST, SRC0, SRC2, SRC1 */
1717 return submit_op3( emit
, inst_token( SVGA3DOP_CMP
), dst
,
1724 * Translate/emit 2-operand (coord, sampler) texture instructions.
1727 emit_tex2(struct svga_shader_emitter
*emit
,
1728 const struct tgsi_full_instruction
*insn
,
1729 SVGA3dShaderDestToken dst
)
1731 SVGA3dShaderInstToken inst
;
1732 struct src_register texcoord
;
1733 struct src_register sampler
;
1734 SVGA3dShaderDestToken tmp
;
1738 switch (insn
->Instruction
.Opcode
) {
1739 case TGSI_OPCODE_TEX
:
1740 inst
.op
= SVGA3DOP_TEX
;
1742 case TGSI_OPCODE_TXP
:
1743 inst
.op
= SVGA3DOP_TEX
;
1744 inst
.control
= SVGA3DOPCONT_PROJECT
;
1746 case TGSI_OPCODE_TXB
:
1747 inst
.op
= SVGA3DOP_TEX
;
1748 inst
.control
= SVGA3DOPCONT_BIAS
;
1750 case TGSI_OPCODE_TXL
:
1751 inst
.op
= SVGA3DOP_TEXLDL
;
1758 texcoord
= translate_src_register( emit
, &insn
->Src
[0] );
1759 sampler
= translate_src_register( emit
, &insn
->Src
[1] );
1761 if (emit
->key
.fkey
.tex
[sampler
.base
.num
].unnormalized
||
1762 emit
->dynamic_branching_level
> 0)
1763 tmp
= get_temp( emit
);
1765 /* Can't do mipmapping inside dynamic branch constructs. Force LOD
1766 * zero in that case.
1768 if (emit
->dynamic_branching_level
> 0 &&
1769 inst
.op
== SVGA3DOP_TEX
&&
1770 SVGA3dShaderGetRegType(texcoord
.base
.value
) == SVGA3DREG_TEMP
) {
1771 struct src_register zero
= get_zero_immediate(emit
);
1773 /* MOV tmp, texcoord */
1774 if (!submit_op1( emit
,
1775 inst_token( SVGA3DOP_MOV
),
1780 /* MOV tmp.w, zero */
1781 if (!submit_op1( emit
,
1782 inst_token( SVGA3DOP_MOV
),
1783 writemask( tmp
, TGSI_WRITEMASK_W
),
1787 texcoord
= src( tmp
);
1788 inst
.op
= SVGA3DOP_TEXLDL
;
1791 /* Explicit normalization of texcoords:
1793 if (emit
->key
.fkey
.tex
[sampler
.base
.num
].unnormalized
) {
1794 struct src_register wh
= get_tex_dimensions( emit
, sampler
.base
.num
);
1796 /* MUL tmp, SRC0, WH */
1797 if (!submit_op2( emit
, inst_token( SVGA3DOP_MUL
),
1798 tmp
, texcoord
, wh
))
1801 texcoord
= src( tmp
);
1804 return submit_op2( emit
, inst
, dst
, texcoord
, sampler
);
1809 * Translate/emit 4-operand (coord, ddx, ddy, sampler) texture instructions.
1812 emit_tex4(struct svga_shader_emitter
*emit
,
1813 const struct tgsi_full_instruction
*insn
,
1814 SVGA3dShaderDestToken dst
)
1816 SVGA3dShaderInstToken inst
;
1817 struct src_register texcoord
;
1818 struct src_register ddx
;
1819 struct src_register ddy
;
1820 struct src_register sampler
;
1822 texcoord
= translate_src_register( emit
, &insn
->Src
[0] );
1823 ddx
= translate_src_register( emit
, &insn
->Src
[1] );
1824 ddy
= translate_src_register( emit
, &insn
->Src
[2] );
1825 sampler
= translate_src_register( emit
, &insn
->Src
[3] );
1829 switch (insn
->Instruction
.Opcode
) {
1830 case TGSI_OPCODE_TXD
:
1831 inst
.op
= SVGA3DOP_TEXLDD
; /* 4 args! */
1838 return submit_op4( emit
, inst
, dst
, texcoord
, sampler
, ddx
, ddy
);
1843 * Emit texture swizzle code. We do this here since SVGA samplers don't
1844 * directly support swizzles.
1847 emit_tex_swizzle(struct svga_shader_emitter
*emit
,
1848 SVGA3dShaderDestToken dst
,
1849 struct src_register src
,
1855 const unsigned swizzleIn
[4] = {swizzle_x
, swizzle_y
, swizzle_z
, swizzle_w
};
1856 unsigned srcSwizzle
[4];
1857 unsigned srcWritemask
= 0x0, zeroWritemask
= 0x0, oneWritemask
= 0x0;
1860 /* build writemasks and srcSwizzle terms */
1861 for (i
= 0; i
< 4; i
++) {
1862 if (swizzleIn
[i
] == PIPE_SWIZZLE_ZERO
) {
1863 srcSwizzle
[i
] = TGSI_SWIZZLE_X
+ i
;
1864 zeroWritemask
|= (1 << i
);
1866 else if (swizzleIn
[i
] == PIPE_SWIZZLE_ONE
) {
1867 srcSwizzle
[i
] = TGSI_SWIZZLE_X
+ i
;
1868 oneWritemask
|= (1 << i
);
1871 srcSwizzle
[i
] = swizzleIn
[i
];
1872 srcWritemask
|= (1 << i
);
1876 /* write x/y/z/w comps */
1877 if (dst
.mask
& srcWritemask
) {
1878 if (!submit_op1(emit
,
1879 inst_token(SVGA3DOP_MOV
),
1880 writemask(dst
, srcWritemask
),
1890 if (dst
.mask
& zeroWritemask
) {
1891 if (!submit_op1(emit
,
1892 inst_token(SVGA3DOP_MOV
),
1893 writemask(dst
, zeroWritemask
),
1894 get_zero_immediate(emit
)))
1899 if (dst
.mask
& oneWritemask
) {
1900 if (!submit_op1(emit
,
1901 inst_token(SVGA3DOP_MOV
),
1902 writemask(dst
, oneWritemask
),
1903 get_one_immediate(emit
)))
1912 * Translate/emit a TGSI texture sample instruction.
1915 emit_tex(struct svga_shader_emitter
*emit
,
1916 const struct tgsi_full_instruction
*insn
)
1918 SVGA3dShaderDestToken dst
=
1919 translate_dst_register( emit
, insn
, 0 );
1920 struct src_register src0
=
1921 translate_src_register( emit
, &insn
->Src
[0] );
1922 struct src_register src1
=
1923 translate_src_register( emit
, &insn
->Src
[1] );
1925 SVGA3dShaderDestToken tex_result
;
1926 const unsigned unit
= src1
.base
.num
;
1928 /* check for shadow samplers */
1929 boolean compare
= (emit
->key
.fkey
.tex
[unit
].compare_mode
==
1930 PIPE_TEX_COMPARE_R_TO_TEXTURE
);
1932 /* texture swizzle */
1933 boolean swizzle
= (emit
->key
.fkey
.tex
[unit
].swizzle_r
!= PIPE_SWIZZLE_RED
||
1934 emit
->key
.fkey
.tex
[unit
].swizzle_g
!= PIPE_SWIZZLE_GREEN
||
1935 emit
->key
.fkey
.tex
[unit
].swizzle_b
!= PIPE_SWIZZLE_BLUE
||
1936 emit
->key
.fkey
.tex
[unit
].swizzle_a
!= PIPE_SWIZZLE_ALPHA
);
1938 boolean saturate
= insn
->Instruction
.Saturate
!= TGSI_SAT_NONE
;
1940 /* If doing compare processing or tex swizzle or saturation, we need to put
1941 * the fetched color into a temporary so it can be used as a source later on.
1943 if (compare
|| swizzle
|| saturate
) {
1944 tex_result
= get_temp( emit
);
1950 switch(insn
->Instruction
.Opcode
) {
1951 case TGSI_OPCODE_TEX
:
1952 case TGSI_OPCODE_TXB
:
1953 case TGSI_OPCODE_TXP
:
1954 case TGSI_OPCODE_TXL
:
1955 if (!emit_tex2( emit
, insn
, tex_result
))
1958 case TGSI_OPCODE_TXD
:
1959 if (!emit_tex4( emit
, insn
, tex_result
))
1967 SVGA3dShaderDestToken dst2
;
1969 if (swizzle
|| saturate
)
1974 if (dst
.mask
& TGSI_WRITEMASK_XYZ
) {
1975 SVGA3dShaderDestToken src0_zdivw
= get_temp( emit
);
1976 /* When sampling a depth texture, the result of the comparison is in
1979 struct src_register tex_src_x
= scalar(src(tex_result
), TGSI_SWIZZLE_Y
);
1980 struct src_register r_coord
;
1982 if (insn
->Instruction
.Opcode
== TGSI_OPCODE_TXP
) {
1983 /* Divide texcoord R by Q */
1984 if (!submit_op1( emit
, inst_token( SVGA3DOP_RCP
),
1985 writemask(src0_zdivw
, TGSI_WRITEMASK_X
),
1986 scalar(src0
, TGSI_SWIZZLE_W
) ))
1989 if (!submit_op2( emit
, inst_token( SVGA3DOP_MUL
),
1990 writemask(src0_zdivw
, TGSI_WRITEMASK_X
),
1991 scalar(src0
, TGSI_SWIZZLE_Z
),
1992 scalar(src(src0_zdivw
), TGSI_SWIZZLE_X
) ))
1995 r_coord
= scalar(src(src0_zdivw
), TGSI_SWIZZLE_X
);
1998 r_coord
= scalar(src0
, TGSI_SWIZZLE_Z
);
2001 /* Compare texture sample value against R component of texcoord */
2002 if (!emit_select(emit
,
2003 emit
->key
.fkey
.tex
[unit
].compare_func
,
2004 writemask( dst2
, TGSI_WRITEMASK_XYZ
),
2010 if (dst
.mask
& TGSI_WRITEMASK_W
) {
2011 struct src_register one
= get_one_immediate(emit
);
2013 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
2014 writemask( dst2
, TGSI_WRITEMASK_W
),
2020 if (saturate
&& !swizzle
) {
2021 /* MOV_SAT real_dst, dst */
2022 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), dst
, src(tex_result
) ))
2026 /* swizzle from tex_result to dst (handles saturation too, if any) */
2027 emit_tex_swizzle(emit
,
2028 dst
, src(tex_result
),
2029 emit
->key
.fkey
.tex
[unit
].swizzle_r
,
2030 emit
->key
.fkey
.tex
[unit
].swizzle_g
,
2031 emit
->key
.fkey
.tex
[unit
].swizzle_b
,
2032 emit
->key
.fkey
.tex
[unit
].swizzle_a
);
2040 emit_bgnloop(struct svga_shader_emitter
*emit
,
2041 const struct tgsi_full_instruction
*insn
)
2043 SVGA3dShaderInstToken inst
= inst_token( SVGA3DOP_LOOP
);
2044 struct src_register loop_reg
= src_register( SVGA3DREG_LOOP
, 0 );
2045 struct src_register const_int
= get_loop_const( emit
);
2047 emit
->dynamic_branching_level
++;
2049 return (emit_instruction( emit
, inst
) &&
2050 emit_src( emit
, loop_reg
) &&
2051 emit_src( emit
, const_int
) );
2056 emit_endloop(struct svga_shader_emitter
*emit
,
2057 const struct tgsi_full_instruction
*insn
)
2059 SVGA3dShaderInstToken inst
= inst_token( SVGA3DOP_ENDLOOP
);
2061 emit
->dynamic_branching_level
--;
2063 return emit_instruction( emit
, inst
);
2068 * Translate/emit TGSI BREAK (out of loop) instruction.
2071 emit_brk(struct svga_shader_emitter
*emit
,
2072 const struct tgsi_full_instruction
*insn
)
2074 SVGA3dShaderInstToken inst
= inst_token( SVGA3DOP_BREAK
);
2075 return emit_instruction( emit
, inst
);
2080 * Emit simple instruction which operates on one scalar value (not
2081 * a vector). Ex: LG2, RCP, RSQ.
2084 emit_scalar_op1(struct svga_shader_emitter
*emit
,
2086 const struct tgsi_full_instruction
*insn
)
2088 SVGA3dShaderInstToken inst
;
2089 SVGA3dShaderDestToken dst
;
2090 struct src_register src
;
2092 inst
= inst_token( opcode
);
2093 dst
= translate_dst_register( emit
, insn
, 0 );
2094 src
= translate_src_register( emit
, &insn
->Src
[0] );
2095 src
= scalar( src
, TGSI_SWIZZLE_X
);
2097 return submit_op1( emit
, inst
, dst
, src
);
2102 * Translate/emit a simple instruction (one which has no special-case
2103 * code) such as ADD, MUL, MIN, MAX.
2106 emit_simple_instruction(struct svga_shader_emitter
*emit
,
2108 const struct tgsi_full_instruction
*insn
)
2110 const struct tgsi_full_src_register
*src
= insn
->Src
;
2111 SVGA3dShaderInstToken inst
;
2112 SVGA3dShaderDestToken dst
;
2114 inst
= inst_token( opcode
);
2115 dst
= translate_dst_register( emit
, insn
, 0 );
2117 switch (insn
->Instruction
.NumSrcRegs
) {
2119 return submit_op0( emit
, inst
, dst
);
2121 return submit_op1( emit
, inst
, dst
,
2122 translate_src_register( emit
, &src
[0] ));
2124 return submit_op2( emit
, inst
, dst
,
2125 translate_src_register( emit
, &src
[0] ),
2126 translate_src_register( emit
, &src
[1] ) );
2128 return submit_op3( emit
, inst
, dst
,
2129 translate_src_register( emit
, &src
[0] ),
2130 translate_src_register( emit
, &src
[1] ),
2131 translate_src_register( emit
, &src
[2] ) );
2140 * Translate/emit TGSI DDX, DDY instructions.
2143 emit_deriv(struct svga_shader_emitter
*emit
,
2144 const struct tgsi_full_instruction
*insn
)
2146 if (emit
->dynamic_branching_level
> 0 &&
2147 insn
->Src
[0].Register
.File
== TGSI_FILE_TEMPORARY
)
2149 SVGA3dShaderDestToken dst
=
2150 translate_dst_register( emit
, insn
, 0 );
2152 /* Deriv opcodes not valid inside dynamic branching, workaround
2153 * by zeroing out the destination.
2155 if (!submit_op1(emit
,
2156 inst_token( SVGA3DOP_MOV
),
2158 get_zero_immediate(emit
)))
2165 const struct tgsi_full_src_register
*reg
= &insn
->Src
[0];
2166 SVGA3dShaderInstToken inst
;
2167 SVGA3dShaderDestToken dst
;
2168 struct src_register src0
;
2170 switch (insn
->Instruction
.Opcode
) {
2171 case TGSI_OPCODE_DDX
:
2172 opcode
= SVGA3DOP_DSX
;
2174 case TGSI_OPCODE_DDY
:
2175 opcode
= SVGA3DOP_DSY
;
2181 inst
= inst_token( opcode
);
2182 dst
= translate_dst_register( emit
, insn
, 0 );
2183 src0
= translate_src_register( emit
, reg
);
2185 /* We cannot use negate or abs on source to dsx/dsy instruction.
2187 if (reg
->Register
.Absolute
||
2188 reg
->Register
.Negate
) {
2189 SVGA3dShaderDestToken temp
= get_temp( emit
);
2191 if (!emit_repl( emit
, temp
, &src0
))
2195 return submit_op1( emit
, inst
, dst
, src0
);
2201 * Translate/emit ARL (Address Register Load) instruction. Used to
2202 * move a value into the special 'address' register. Used to implement
2203 * indirect/variable indexing into arrays.
2206 emit_arl(struct svga_shader_emitter
*emit
,
2207 const struct tgsi_full_instruction
*insn
)
2209 ++emit
->current_arl
;
2210 if (emit
->unit
== PIPE_SHADER_FRAGMENT
) {
2211 /* MOVA not present in pixel shader instruction set.
2212 * Ignore this instruction altogether since it is
2213 * only used for loop counters -- and for that
2214 * we reference aL directly.
2218 if (svga_arl_needs_adjustment( emit
)) {
2219 return emit_fake_arl( emit
, insn
);
2221 /* no need to adjust, just emit straight arl */
2222 return emit_simple_instruction(emit
, SVGA3DOP_MOVA
, insn
);
2228 emit_pow(struct svga_shader_emitter
*emit
,
2229 const struct tgsi_full_instruction
*insn
)
2231 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
2232 struct src_register src0
= translate_src_register(
2233 emit
, &insn
->Src
[0] );
2234 struct src_register src1
= translate_src_register(
2235 emit
, &insn
->Src
[1] );
2236 boolean need_tmp
= FALSE
;
2238 /* POW can only output to a temporary */
2239 if (insn
->Dst
[0].Register
.File
!= TGSI_FILE_TEMPORARY
)
2242 /* POW src1 must not be the same register as dst */
2243 if (alias_src_dst( src1
, dst
))
2246 /* it's a scalar op */
2247 src0
= scalar( src0
, TGSI_SWIZZLE_X
);
2248 src1
= scalar( src1
, TGSI_SWIZZLE_X
);
2251 SVGA3dShaderDestToken tmp
=
2252 writemask(get_temp( emit
), TGSI_WRITEMASK_X
);
2254 if (!submit_op2(emit
, inst_token( SVGA3DOP_POW
), tmp
, src0
, src1
))
2257 return submit_op1(emit
, inst_token( SVGA3DOP_MOV
),
2258 dst
, scalar(src(tmp
), 0) );
2261 return submit_op2(emit
, inst_token( SVGA3DOP_POW
), dst
, src0
, src1
);
2267 * Translate/emit TGSI XPD (vector cross product) instruction.
2270 emit_xpd(struct svga_shader_emitter
*emit
,
2271 const struct tgsi_full_instruction
*insn
)
2273 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
2274 const struct src_register src0
= translate_src_register(
2275 emit
, &insn
->Src
[0] );
2276 const struct src_register src1
= translate_src_register(
2277 emit
, &insn
->Src
[1] );
2278 boolean need_dst_tmp
= FALSE
;
2280 /* XPD can only output to a temporary */
2281 if (SVGA3dShaderGetRegType(dst
.value
) != SVGA3DREG_TEMP
)
2282 need_dst_tmp
= TRUE
;
2284 /* The dst reg must not be the same as src0 or src1*/
2285 if (alias_src_dst(src0
, dst
) ||
2286 alias_src_dst(src1
, dst
))
2287 need_dst_tmp
= TRUE
;
2290 SVGA3dShaderDestToken tmp
= get_temp( emit
);
2292 /* Obey DX9 restrictions on mask:
2294 tmp
.mask
= dst
.mask
& TGSI_WRITEMASK_XYZ
;
2296 if (!submit_op2(emit
, inst_token( SVGA3DOP_CRS
), tmp
, src0
, src1
))
2299 if (!submit_op1(emit
, inst_token( SVGA3DOP_MOV
), dst
, src( tmp
)))
2303 if (!submit_op2(emit
, inst_token( SVGA3DOP_CRS
), dst
, src0
, src1
))
2307 /* Need to emit 1.0 to dst.w?
2309 if (dst
.mask
& TGSI_WRITEMASK_W
) {
2310 struct src_register one
= get_one_immediate( emit
);
2312 if (!submit_op1(emit
,
2313 inst_token( SVGA3DOP_MOV
),
2314 writemask(dst
, TGSI_WRITEMASK_W
),
2324 * Emit a LRP (linear interpolation) instruction.
2327 submit_lrp(struct svga_shader_emitter
*emit
,
2328 SVGA3dShaderDestToken dst
,
2329 struct src_register src0
,
2330 struct src_register src1
,
2331 struct src_register src2
)
2333 SVGA3dShaderDestToken tmp
;
2334 boolean need_dst_tmp
= FALSE
;
2336 /* The dst reg must be a temporary, and not be the same as src0 or src2 */
2337 if (SVGA3dShaderGetRegType(dst
.value
) != SVGA3DREG_TEMP
||
2338 alias_src_dst(src0
, dst
) ||
2339 alias_src_dst(src2
, dst
))
2340 need_dst_tmp
= TRUE
;
2343 tmp
= get_temp( emit
);
2344 tmp
.mask
= dst
.mask
;
2350 if (!submit_op3(emit
, inst_token( SVGA3DOP_LRP
), tmp
, src0
, src1
, src2
))
2354 if (!submit_op1(emit
, inst_token( SVGA3DOP_MOV
), dst
, src( tmp
)))
2363 * Translate/emit LRP (Linear Interpolation) instruction.
2366 emit_lrp(struct svga_shader_emitter
*emit
,
2367 const struct tgsi_full_instruction
*insn
)
2369 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
2370 const struct src_register src0
= translate_src_register(
2371 emit
, &insn
->Src
[0] );
2372 const struct src_register src1
= translate_src_register(
2373 emit
, &insn
->Src
[1] );
2374 const struct src_register src2
= translate_src_register(
2375 emit
, &insn
->Src
[2] );
2377 return submit_lrp(emit
, dst
, src0
, src1
, src2
);
2381 * Translate/emit DST (Distance function) instruction.
2384 emit_dst_insn(struct svga_shader_emitter
*emit
,
2385 const struct tgsi_full_instruction
*insn
)
2387 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
2388 /* SVGA/DX9 has a DST instruction, but only for vertex shaders:
2390 return emit_simple_instruction(emit
, SVGA3DOP_DST
, insn
);
2393 /* result[0] = 1 * 1;
2394 * result[1] = a[1] * b[1];
2395 * result[2] = a[2] * 1;
2396 * result[3] = 1 * b[3];
2398 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
2399 SVGA3dShaderDestToken tmp
;
2400 const struct src_register src0
= translate_src_register(
2401 emit
, &insn
->Src
[0] );
2402 const struct src_register src1
= translate_src_register(
2403 emit
, &insn
->Src
[1] );
2404 boolean need_tmp
= FALSE
;
2406 if (SVGA3dShaderGetRegType(dst
.value
) != SVGA3DREG_TEMP
||
2407 alias_src_dst(src0
, dst
) ||
2408 alias_src_dst(src1
, dst
))
2412 tmp
= get_temp( emit
);
2420 if (tmp
.mask
& TGSI_WRITEMASK_XW
) {
2421 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
2422 writemask(tmp
, TGSI_WRITEMASK_XW
),
2423 get_one_immediate(emit
)))
2429 if (tmp
.mask
& TGSI_WRITEMASK_YZ
) {
2430 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
2431 writemask(tmp
, TGSI_WRITEMASK_YZ
),
2436 /* tmp.yw = tmp * src1
2438 if (tmp
.mask
& TGSI_WRITEMASK_YW
) {
2439 if (!submit_op2( emit
, inst_token( SVGA3DOP_MUL
),
2440 writemask(tmp
, TGSI_WRITEMASK_YW
),
2449 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
2461 emit_exp(struct svga_shader_emitter
*emit
,
2462 const struct tgsi_full_instruction
*insn
)
2464 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
2465 struct src_register src0
=
2466 translate_src_register( emit
, &insn
->Src
[0] );
2467 SVGA3dShaderDestToken fraction
;
2469 if (dst
.mask
& TGSI_WRITEMASK_Y
)
2471 else if (dst
.mask
& TGSI_WRITEMASK_X
)
2472 fraction
= get_temp( emit
);
2476 /* If y is being written, fill it with src0 - floor(src0).
2478 if (dst
.mask
& TGSI_WRITEMASK_XY
) {
2479 if (!submit_op1( emit
, inst_token( SVGA3DOP_FRC
),
2480 writemask( fraction
, TGSI_WRITEMASK_Y
),
2485 /* If x is being written, fill it with 2 ^ floor(src0).
2487 if (dst
.mask
& TGSI_WRITEMASK_X
) {
2488 if (!submit_op2( emit
, inst_token( SVGA3DOP_ADD
),
2489 writemask( dst
, TGSI_WRITEMASK_X
),
2491 scalar( negate( src( fraction
) ), TGSI_SWIZZLE_Y
) ) )
2494 if (!submit_op1( emit
, inst_token( SVGA3DOP_EXP
),
2495 writemask( dst
, TGSI_WRITEMASK_X
),
2496 scalar( src( dst
), TGSI_SWIZZLE_X
) ) )
2499 if (!(dst
.mask
& TGSI_WRITEMASK_Y
))
2500 release_temp( emit
, fraction
);
2503 /* If z is being written, fill it with 2 ^ src0 (partial precision).
2505 if (dst
.mask
& TGSI_WRITEMASK_Z
) {
2506 if (!submit_op1( emit
, inst_token( SVGA3DOP_EXPP
),
2507 writemask( dst
, TGSI_WRITEMASK_Z
),
2512 /* If w is being written, fill it with one.
2514 if (dst
.mask
& TGSI_WRITEMASK_W
) {
2515 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
2516 writemask(dst
, TGSI_WRITEMASK_W
),
2517 get_one_immediate(emit
)))
2526 * Translate/emit LIT (Lighting helper) instruction.
2529 emit_lit(struct svga_shader_emitter
*emit
,
2530 const struct tgsi_full_instruction
*insn
)
2532 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
2533 /* SVGA/DX9 has a LIT instruction, but only for vertex shaders:
2535 return emit_simple_instruction(emit
, SVGA3DOP_LIT
, insn
);
2538 /* D3D vs. GL semantics can be fairly easily accomodated by
2539 * variations on this sequence.
2543 * tmp.z = pow(src.y,src.w)
2544 * p0 = src0.xxxx > 0
2545 * result = zero.wxxw
2546 * (p0) result.yz = tmp
2550 * tmp.z = pow(src.y,src.w)
2551 * p0 = src0.xxyy > 0
2552 * result = zero.wxxw
2553 * (p0) result.yz = tmp
2555 * Will implement the GL version for now.
2557 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
2558 SVGA3dShaderDestToken tmp
= get_temp( emit
);
2559 const struct src_register src0
= translate_src_register(
2560 emit
, &insn
->Src
[0] );
2562 /* tmp = pow(src.y, src.w)
2564 if (dst
.mask
& TGSI_WRITEMASK_Z
) {
2565 if (!submit_op2(emit
, inst_token( SVGA3DOP_POW
),
2574 if (dst
.mask
& TGSI_WRITEMASK_Y
) {
2575 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
2576 writemask(tmp
, TGSI_WRITEMASK_Y
),
2581 /* Can't quite do this with emit conditional due to the extra
2582 * writemask on the predicated mov:
2585 SVGA3dShaderDestToken pred_reg
= dst_register( SVGA3DREG_PREDICATE
, 0 );
2586 struct src_register predsrc
;
2588 /* D3D vs GL semantics:
2591 predsrc
= swizzle(src0
, 0, 0, 1, 1); /* D3D */
2593 predsrc
= swizzle(src0
, 0, 0, 0, 0); /* GL */
2595 /* SETP src0.xxyy, GT, {0}.x */
2596 if (!submit_op2( emit
,
2597 inst_token_setp(SVGA3DOPCOMP_GT
),
2600 get_zero_immediate(emit
)))
2604 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), dst
,
2605 get_immediate(emit
, 1.0f
, 0.0f
, 0.0f
, 1.0f
)))
2608 /* MOV dst.yz, tmp (predicated)
2610 * Note that the predicate reg (and possible modifiers) is passed
2611 * as the first source argument.
2613 if (dst
.mask
& TGSI_WRITEMASK_YZ
) {
2614 if (!submit_op2( emit
,
2615 inst_token_predicated(SVGA3DOP_MOV
),
2616 writemask(dst
, TGSI_WRITEMASK_YZ
),
2617 src( pred_reg
), src( tmp
) ))
2628 emit_ex2(struct svga_shader_emitter
*emit
,
2629 const struct tgsi_full_instruction
*insn
)
2631 SVGA3dShaderInstToken inst
;
2632 SVGA3dShaderDestToken dst
;
2633 struct src_register src0
;
2635 inst
= inst_token( SVGA3DOP_EXP
);
2636 dst
= translate_dst_register( emit
, insn
, 0 );
2637 src0
= translate_src_register( emit
, &insn
->Src
[0] );
2638 src0
= scalar( src0
, TGSI_SWIZZLE_X
);
2640 if (dst
.mask
!= TGSI_WRITEMASK_XYZW
) {
2641 SVGA3dShaderDestToken tmp
= get_temp( emit
);
2643 if (!submit_op1( emit
, inst
, tmp
, src0
))
2646 return submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
2648 scalar( src( tmp
), TGSI_SWIZZLE_X
) );
2651 return submit_op1( emit
, inst
, dst
, src0
);
2656 emit_log(struct svga_shader_emitter
*emit
,
2657 const struct tgsi_full_instruction
*insn
)
2659 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
2660 struct src_register src0
=
2661 translate_src_register( emit
, &insn
->Src
[0] );
2662 SVGA3dShaderDestToken abs_tmp
;
2663 struct src_register abs_src0
;
2664 SVGA3dShaderDestToken log2_abs
;
2668 if (dst
.mask
& TGSI_WRITEMASK_Z
)
2670 else if (dst
.mask
& TGSI_WRITEMASK_XY
)
2671 log2_abs
= get_temp( emit
);
2675 /* If z is being written, fill it with log2( abs( src0 ) ).
2677 if (dst
.mask
& TGSI_WRITEMASK_XYZ
) {
2678 if (!src0
.base
.srcMod
|| src0
.base
.srcMod
== SVGA3DSRCMOD_ABS
)
2681 abs_tmp
= get_temp( emit
);
2683 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
2688 abs_src0
= src( abs_tmp
);
2691 abs_src0
= absolute( scalar( abs_src0
, TGSI_SWIZZLE_X
) );
2693 if (!submit_op1( emit
, inst_token( SVGA3DOP_LOG
),
2694 writemask( log2_abs
, TGSI_WRITEMASK_Z
),
2699 if (dst
.mask
& TGSI_WRITEMASK_XY
) {
2700 SVGA3dShaderDestToken floor_log2
;
2702 if (dst
.mask
& TGSI_WRITEMASK_X
)
2705 floor_log2
= get_temp( emit
);
2707 /* If x is being written, fill it with floor( log2( abs( src0 ) ) ).
2709 if (!submit_op1( emit
, inst_token( SVGA3DOP_FRC
),
2710 writemask( floor_log2
, TGSI_WRITEMASK_X
),
2711 scalar( src( log2_abs
), TGSI_SWIZZLE_Z
) ) )
2714 if (!submit_op2( emit
, inst_token( SVGA3DOP_ADD
),
2715 writemask( floor_log2
, TGSI_WRITEMASK_X
),
2716 scalar( src( log2_abs
), TGSI_SWIZZLE_Z
),
2717 negate( src( floor_log2
) ) ) )
2720 /* If y is being written, fill it with
2721 * abs ( src0 ) / ( 2 ^ floor( log2( abs( src0 ) ) ) ).
2723 if (dst
.mask
& TGSI_WRITEMASK_Y
) {
2724 if (!submit_op1( emit
, inst_token( SVGA3DOP_EXP
),
2725 writemask( dst
, TGSI_WRITEMASK_Y
),
2726 negate( scalar( src( floor_log2
),
2727 TGSI_SWIZZLE_X
) ) ) )
2730 if (!submit_op2( emit
, inst_token( SVGA3DOP_MUL
),
2731 writemask( dst
, TGSI_WRITEMASK_Y
),
2737 if (!(dst
.mask
& TGSI_WRITEMASK_X
))
2738 release_temp( emit
, floor_log2
);
2740 if (!(dst
.mask
& TGSI_WRITEMASK_Z
))
2741 release_temp( emit
, log2_abs
);
2744 if (dst
.mask
& TGSI_WRITEMASK_XYZ
&& src0
.base
.srcMod
&&
2745 src0
.base
.srcMod
!= SVGA3DSRCMOD_ABS
)
2746 release_temp( emit
, abs_tmp
);
2748 /* If w is being written, fill it with one.
2750 if (dst
.mask
& TGSI_WRITEMASK_W
) {
2751 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
2752 writemask(dst
, TGSI_WRITEMASK_W
),
2753 get_one_immediate(emit
)))
2762 * Translate TGSI TRUNC or ROUND instruction.
2763 * We need to truncate toward zero. Ex: trunc(-1.9) = -1
2764 * Different approaches are needed for VS versus PS.
2767 emit_trunc_round(struct svga_shader_emitter
*emit
,
2768 const struct tgsi_full_instruction
*insn
,
2771 SVGA3dShaderDestToken dst
= translate_dst_register(emit
, insn
, 0);
2772 const struct src_register src0
=
2773 translate_src_register(emit
, &insn
->Src
[0] );
2774 SVGA3dShaderDestToken t1
= get_temp(emit
);
2777 SVGA3dShaderDestToken t0
= get_temp(emit
);
2778 struct src_register half
= get_half_immediate(emit
);
2780 /* t0 = abs(src0) + 0.5 */
2781 if (!submit_op2(emit
, inst_token(SVGA3DOP_ADD
), t0
,
2782 absolute(src0
), half
))
2785 /* t1 = fract(t0) */
2786 if (!submit_op1(emit
, inst_token(SVGA3DOP_FRC
), t1
, src(t0
)))
2790 if (!submit_op2(emit
, inst_token(SVGA3DOP_ADD
), t1
, src(t0
),
2797 /* t1 = fract(abs(src0)) */
2798 if (!submit_op1(emit
, inst_token(SVGA3DOP_FRC
), t1
, absolute(src0
)))
2801 /* t1 = abs(src0) - t1 */
2802 if (!submit_op2(emit
, inst_token(SVGA3DOP_ADD
), t1
, absolute(src0
),
2808 * Now we need to multiply t1 by the sign of the original value.
2810 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
2811 /* For VS: use SGN instruction */
2812 /* Need two extra/dummy registers: */
2813 SVGA3dShaderDestToken t2
= get_temp(emit
), t3
= get_temp(emit
),
2814 t4
= get_temp(emit
);
2816 /* t2 = sign(src0) */
2817 if (!submit_op3(emit
, inst_token(SVGA3DOP_SGN
), t2
, src0
,
2822 if (!submit_op2(emit
, inst_token(SVGA3DOP_MUL
), dst
, src(t1
), src(t2
)))
2826 /* For FS: Use CMP instruction */
2827 return submit_op3(emit
, inst_token( SVGA3DOP_CMP
), dst
,
2828 src0
, src(t1
), negate(src(t1
)));
2836 * Translate/emit "begin subroutine" instruction/marker/label.
2839 emit_bgnsub(struct svga_shader_emitter
*emit
,
2841 const struct tgsi_full_instruction
*insn
)
2845 /* Note that we've finished the main function and are now emitting
2846 * subroutines. This affects how we terminate the generated
2849 emit
->in_main_func
= FALSE
;
2851 for (i
= 0; i
< emit
->nr_labels
; i
++) {
2852 if (emit
->label
[i
] == position
) {
2853 return (emit_instruction( emit
, inst_token( SVGA3DOP_RET
) ) &&
2854 emit_instruction( emit
, inst_token( SVGA3DOP_LABEL
) ) &&
2855 emit_src( emit
, src_register( SVGA3DREG_LABEL
, i
)));
2865 * Translate/emit subroutine call instruction.
2868 emit_call(struct svga_shader_emitter
*emit
,
2869 const struct tgsi_full_instruction
*insn
)
2871 unsigned position
= insn
->Label
.Label
;
2874 for (i
= 0; i
< emit
->nr_labels
; i
++) {
2875 if (emit
->label
[i
] == position
)
2879 if (emit
->nr_labels
== Elements(emit
->label
))
2882 if (i
== emit
->nr_labels
) {
2883 emit
->label
[i
] = position
;
2887 return (emit_instruction( emit
, inst_token( SVGA3DOP_CALL
) ) &&
2888 emit_src( emit
, src_register( SVGA3DREG_LABEL
, i
)));
2893 * Called at the end of the shader. Actually, emit special "fix-up"
2894 * code for the vertex/fragment shader.
2897 emit_end(struct svga_shader_emitter
*emit
)
2899 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
2900 return emit_vs_postamble( emit
);
2903 return emit_ps_postamble( emit
);
2909 * Translate any TGSI instruction to SVGA.
2912 svga_emit_instruction(struct svga_shader_emitter
*emit
,
2914 const struct tgsi_full_instruction
*insn
)
2916 switch (insn
->Instruction
.Opcode
) {
2918 case TGSI_OPCODE_ARL
:
2919 return emit_arl( emit
, insn
);
2921 case TGSI_OPCODE_TEX
:
2922 case TGSI_OPCODE_TXB
:
2923 case TGSI_OPCODE_TXP
:
2924 case TGSI_OPCODE_TXL
:
2925 case TGSI_OPCODE_TXD
:
2926 return emit_tex( emit
, insn
);
2928 case TGSI_OPCODE_DDX
:
2929 case TGSI_OPCODE_DDY
:
2930 return emit_deriv( emit
, insn
);
2932 case TGSI_OPCODE_BGNSUB
:
2933 return emit_bgnsub( emit
, position
, insn
);
2935 case TGSI_OPCODE_ENDSUB
:
2938 case TGSI_OPCODE_CAL
:
2939 return emit_call( emit
, insn
);
2941 case TGSI_OPCODE_FLR
:
2942 return emit_floor( emit
, insn
);
2944 case TGSI_OPCODE_TRUNC
:
2945 return emit_trunc_round( emit
, insn
, FALSE
);
2947 case TGSI_OPCODE_ROUND
:
2948 return emit_trunc_round( emit
, insn
, TRUE
);
2950 case TGSI_OPCODE_CEIL
:
2951 return emit_ceil( emit
, insn
);
2953 case TGSI_OPCODE_CMP
:
2954 return emit_cmp( emit
, insn
);
2956 case TGSI_OPCODE_DIV
:
2957 return emit_div( emit
, insn
);
2959 case TGSI_OPCODE_DP2
:
2960 return emit_dp2( emit
, insn
);
2962 case TGSI_OPCODE_DPH
:
2963 return emit_dph( emit
, insn
);
2965 case TGSI_OPCODE_NRM
:
2966 return emit_nrm( emit
, insn
);
2968 case TGSI_OPCODE_COS
:
2969 return emit_cos( emit
, insn
);
2971 case TGSI_OPCODE_SIN
:
2972 return emit_sin( emit
, insn
);
2974 case TGSI_OPCODE_SCS
:
2975 return emit_sincos( emit
, insn
);
2977 case TGSI_OPCODE_END
:
2978 /* TGSI always finishes the main func with an END */
2979 return emit_end( emit
);
2981 case TGSI_OPCODE_KILL_IF
:
2982 return emit_kill_if( emit
, insn
);
2984 /* Selection opcodes. The underlying language is fairly
2985 * non-orthogonal about these.
2987 case TGSI_OPCODE_SEQ
:
2988 return emit_select_op( emit
, PIPE_FUNC_EQUAL
, insn
);
2990 case TGSI_OPCODE_SNE
:
2991 return emit_select_op( emit
, PIPE_FUNC_NOTEQUAL
, insn
);
2993 case TGSI_OPCODE_SGT
:
2994 return emit_select_op( emit
, PIPE_FUNC_GREATER
, insn
);
2996 case TGSI_OPCODE_SGE
:
2997 return emit_select_op( emit
, PIPE_FUNC_GEQUAL
, insn
);
2999 case TGSI_OPCODE_SLT
:
3000 return emit_select_op( emit
, PIPE_FUNC_LESS
, insn
);
3002 case TGSI_OPCODE_SLE
:
3003 return emit_select_op( emit
, PIPE_FUNC_LEQUAL
, insn
);
3005 case TGSI_OPCODE_SUB
:
3006 return emit_sub( emit
, insn
);
3008 case TGSI_OPCODE_POW
:
3009 return emit_pow( emit
, insn
);
3011 case TGSI_OPCODE_EX2
:
3012 return emit_ex2( emit
, insn
);
3014 case TGSI_OPCODE_EXP
:
3015 return emit_exp( emit
, insn
);
3017 case TGSI_OPCODE_LOG
:
3018 return emit_log( emit
, insn
);
3020 case TGSI_OPCODE_LG2
:
3021 return emit_scalar_op1( emit
, SVGA3DOP_LOG
, insn
);
3023 case TGSI_OPCODE_RSQ
:
3024 return emit_scalar_op1( emit
, SVGA3DOP_RSQ
, insn
);
3026 case TGSI_OPCODE_RCP
:
3027 return emit_scalar_op1( emit
, SVGA3DOP_RCP
, insn
);
3029 case TGSI_OPCODE_CONT
:
3030 /* not expected (we return PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED = 0) */
3033 case TGSI_OPCODE_RET
:
3034 /* This is a noop -- we tell mesa that we can't support RET
3035 * within a function (early return), so this will always be
3036 * followed by an ENDSUB.
3040 /* These aren't actually used by any of the frontends we care
3043 case TGSI_OPCODE_CLAMP
:
3044 case TGSI_OPCODE_AND
:
3045 case TGSI_OPCODE_OR
:
3046 case TGSI_OPCODE_I2F
:
3047 case TGSI_OPCODE_NOT
:
3048 case TGSI_OPCODE_SHL
:
3049 case TGSI_OPCODE_ISHR
:
3050 case TGSI_OPCODE_XOR
:
3053 case TGSI_OPCODE_IF
:
3054 return emit_if( emit
, insn
);
3055 case TGSI_OPCODE_ELSE
:
3056 return emit_else( emit
, insn
);
3057 case TGSI_OPCODE_ENDIF
:
3058 return emit_endif( emit
, insn
);
3060 case TGSI_OPCODE_BGNLOOP
:
3061 return emit_bgnloop( emit
, insn
);
3062 case TGSI_OPCODE_ENDLOOP
:
3063 return emit_endloop( emit
, insn
);
3064 case TGSI_OPCODE_BRK
:
3065 return emit_brk( emit
, insn
);
3067 case TGSI_OPCODE_XPD
:
3068 return emit_xpd( emit
, insn
);
3070 case TGSI_OPCODE_KILL
:
3071 return emit_kill( emit
, insn
);
3073 case TGSI_OPCODE_DST
:
3074 return emit_dst_insn( emit
, insn
);
3076 case TGSI_OPCODE_LIT
:
3077 return emit_lit( emit
, insn
);
3079 case TGSI_OPCODE_LRP
:
3080 return emit_lrp( emit
, insn
);
3082 case TGSI_OPCODE_SSG
:
3083 return emit_ssg( emit
, insn
);
3087 unsigned opcode
= translate_opcode(insn
->Instruction
.Opcode
);
3089 if (opcode
== SVGA3DOP_LAST_INST
)
3092 if (!emit_simple_instruction( emit
, opcode
, insn
))
3102 * Translate/emit a TGSI IMMEDIATE declaration.
3103 * An immediate vector is a constant that's hard-coded into the shader.
3106 svga_emit_immediate(struct svga_shader_emitter
*emit
,
3107 const struct tgsi_full_immediate
*imm
)
3109 static const float id
[4] = {0,0,0,1};
3113 assert(1 <= imm
->Immediate
.NrTokens
&& imm
->Immediate
.NrTokens
<= 5);
3114 for (i
= 0; i
< imm
->Immediate
.NrTokens
- 1; i
++) {
3115 float f
= imm
->u
[i
].Float
;
3116 value
[i
] = util_is_inf_or_nan(f
) ? 0.0f
: f
;
3119 /* If the immediate has less than four values, fill in the remaining
3120 * positions from id={0,0,0,1}.
3122 for ( ; i
< 4; i
++ )
3125 return emit_def_const( emit
, SVGA3D_CONST_TYPE_FLOAT
,
3126 emit
->imm_start
+ emit
->internal_imm_count
++,
3127 value
[0], value
[1], value
[2], value
[3]);
3132 make_immediate(struct svga_shader_emitter
*emit
,
3133 float a
, float b
, float c
, float d
,
3134 struct src_register
*out
)
3136 unsigned idx
= emit
->nr_hw_float_const
++;
3138 if (!emit_def_const( emit
, SVGA3D_CONST_TYPE_FLOAT
,
3142 *out
= src_register( SVGA3DREG_CONST
, idx
);
3149 * Emit special VS instructions at top of shader.
3152 emit_vs_preamble(struct svga_shader_emitter
*emit
)
3154 if (!emit
->key
.vkey
.need_prescale
) {
3155 if (!make_immediate( emit
, 0, 0, .5, .5,
3165 * Emit special PS instructions at top of shader.
3168 emit_ps_preamble(struct svga_shader_emitter
*emit
)
3170 if (emit
->ps_reads_pos
&& emit
->info
.reads_z
) {
3172 * Assemble the position from various bits of inputs. Depth and W are
3173 * passed in a texcoord this is due to D3D's vPos not hold Z or W.
3174 * Also fixup the perspective interpolation.
3176 * temp_pos.xy = vPos.xy
3177 * temp_pos.w = rcp(texcoord1.w);
3178 * temp_pos.z = texcoord1.z * temp_pos.w;
3180 if (!submit_op1( emit
,
3181 inst_token(SVGA3DOP_MOV
),
3182 writemask( emit
->ps_temp_pos
, TGSI_WRITEMASK_XY
),
3183 emit
->ps_true_pos
))
3186 if (!submit_op1( emit
,
3187 inst_token(SVGA3DOP_RCP
),
3188 writemask( emit
->ps_temp_pos
, TGSI_WRITEMASK_W
),
3189 scalar( emit
->ps_depth_pos
, TGSI_SWIZZLE_W
) ))
3192 if (!submit_op2( emit
,
3193 inst_token(SVGA3DOP_MUL
),
3194 writemask( emit
->ps_temp_pos
, TGSI_WRITEMASK_Z
),
3195 scalar( emit
->ps_depth_pos
, TGSI_SWIZZLE_Z
),
3196 scalar( src(emit
->ps_temp_pos
), TGSI_SWIZZLE_W
) ))
3205 * Emit special PS instructions at end of shader.
3208 emit_ps_postamble(struct svga_shader_emitter
*emit
)
3212 /* PS oDepth is incredibly fragile and it's very hard to catch the
3213 * types of usage that break it during shader emit. Easier just to
3214 * redirect the main program to a temporary and then only touch
3215 * oDepth with a hand-crafted MOV below.
3217 if (SVGA3dShaderGetRegType(emit
->true_pos
.value
) != 0) {
3218 if (!submit_op1( emit
,
3219 inst_token(SVGA3DOP_MOV
),
3221 scalar(src(emit
->temp_pos
), TGSI_SWIZZLE_Z
) ))
3225 for (i
= 0; i
< PIPE_MAX_COLOR_BUFS
; i
++) {
3226 if (SVGA3dShaderGetRegType(emit
->true_color_output
[i
].value
) != 0) {
3227 /* Potentially override output colors with white for XOR
3228 * logicop workaround.
3230 if (emit
->unit
== PIPE_SHADER_FRAGMENT
&&
3231 emit
->key
.fkey
.white_fragments
) {
3232 struct src_register one
= get_one_immediate(emit
);
3234 if (!submit_op1( emit
,
3235 inst_token(SVGA3DOP_MOV
),
3236 emit
->true_color_output
[i
],
3240 else if (emit
->unit
== PIPE_SHADER_FRAGMENT
&&
3241 i
< emit
->key
.fkey
.write_color0_to_n_cbufs
) {
3242 /* Write temp color output [0] to true output [i] */
3243 if (!submit_op1(emit
, inst_token(SVGA3DOP_MOV
),
3244 emit
->true_color_output
[i
],
3245 src(emit
->temp_color_output
[0]))) {
3250 if (!submit_op1( emit
,
3251 inst_token(SVGA3DOP_MOV
),
3252 emit
->true_color_output
[i
],
3253 src(emit
->temp_color_output
[i
]) ))
3264 * Emit special VS instructions at end of shader.
3267 emit_vs_postamble(struct svga_shader_emitter
*emit
)
3269 /* PSIZ output is incredibly fragile and it's very hard to catch
3270 * the types of usage that break it during shader emit. Easier
3271 * just to redirect the main program to a temporary and then only
3272 * touch PSIZ with a hand-crafted MOV below.
3274 if (SVGA3dShaderGetRegType(emit
->true_psiz
.value
) != 0) {
3275 if (!submit_op1( emit
,
3276 inst_token(SVGA3DOP_MOV
),
3278 scalar(src(emit
->temp_psiz
), TGSI_SWIZZLE_X
) ))
3282 /* Need to perform various manipulations on vertex position to cope
3283 * with the different GL and D3D clip spaces.
3285 if (emit
->key
.vkey
.need_prescale
) {
3286 SVGA3dShaderDestToken temp_pos
= emit
->temp_pos
;
3287 SVGA3dShaderDestToken depth
= emit
->depth_pos
;
3288 SVGA3dShaderDestToken pos
= emit
->true_pos
;
3289 unsigned offset
= emit
->info
.file_max
[TGSI_FILE_CONSTANT
] + 1;
3290 struct src_register prescale_scale
= src_register( SVGA3DREG_CONST
,
3292 struct src_register prescale_trans
= src_register( SVGA3DREG_CONST
,
3295 if (!submit_op1( emit
,
3296 inst_token(SVGA3DOP_MOV
),
3297 writemask(depth
, TGSI_WRITEMASK_W
),
3298 scalar(src(temp_pos
), TGSI_SWIZZLE_W
) ))
3301 /* MUL temp_pos.xyz, temp_pos, prescale.scale
3302 * MAD result.position, temp_pos.wwww, prescale.trans, temp_pos
3303 * --> Note that prescale.trans.w == 0
3305 if (!submit_op2( emit
,
3306 inst_token(SVGA3DOP_MUL
),
3307 writemask(temp_pos
, TGSI_WRITEMASK_XYZ
),
3312 if (!submit_op3( emit
,
3313 inst_token(SVGA3DOP_MAD
),
3315 swizzle(src(temp_pos
), 3, 3, 3, 3),
3320 /* Also write to depth value */
3321 if (!submit_op3( emit
,
3322 inst_token(SVGA3DOP_MAD
),
3323 writemask(depth
, TGSI_WRITEMASK_Z
),
3324 swizzle(src(temp_pos
), 3, 3, 3, 3),
3330 SVGA3dShaderDestToken temp_pos
= emit
->temp_pos
;
3331 SVGA3dShaderDestToken depth
= emit
->depth_pos
;
3332 SVGA3dShaderDestToken pos
= emit
->true_pos
;
3333 struct src_register imm_0055
= emit
->imm_0055
;
3335 /* Adjust GL clipping coordinate space to hardware (D3D-style):
3337 * DP4 temp_pos.z, {0,0,.5,.5}, temp_pos
3338 * MOV result.position, temp_pos
3340 if (!submit_op2( emit
,
3341 inst_token(SVGA3DOP_DP4
),
3342 writemask(temp_pos
, TGSI_WRITEMASK_Z
),
3347 if (!submit_op1( emit
,
3348 inst_token(SVGA3DOP_MOV
),
3353 /* Move the manipulated depth into the extra texcoord reg */
3354 if (!submit_op1( emit
,
3355 inst_token(SVGA3DOP_MOV
),
3356 writemask(depth
, TGSI_WRITEMASK_ZW
),
3366 * For the pixel shader: emit the code which chooses the front
3367 * or back face color depending on triangle orientation.
3368 * This happens at the top of the fragment shader.
3371 * 1: COLOR = FrontColor;
3373 * 3: COLOR = BackColor;
3377 emit_light_twoside(struct svga_shader_emitter
*emit
)
3379 struct src_register vface
, zero
;
3380 struct src_register front
[2];
3381 struct src_register back
[2];
3382 SVGA3dShaderDestToken color
[2];
3383 int count
= emit
->internal_color_count
;
3385 SVGA3dShaderInstToken if_token
;
3390 vface
= get_vface( emit
);
3391 zero
= get_zero_immediate(emit
);
3393 /* Can't use get_temp() to allocate the color reg as such
3394 * temporaries will be reclaimed after each instruction by the call
3395 * to reset_temp_regs().
3397 for (i
= 0; i
< count
; i
++) {
3398 color
[i
] = dst_register( SVGA3DREG_TEMP
, emit
->nr_hw_temp
++ );
3399 front
[i
] = emit
->input_map
[emit
->internal_color_idx
[i
]];
3401 /* Back is always the next input:
3404 back
[i
].base
.num
= front
[i
].base
.num
+ 1;
3406 /* Reassign the input_map to the actual front-face color:
3408 emit
->input_map
[emit
->internal_color_idx
[i
]] = src(color
[i
]);
3411 if_token
= inst_token( SVGA3DOP_IFC
);
3413 if (emit
->key
.fkey
.front_ccw
)
3414 if_token
.control
= SVGA3DOPCOMP_LT
;
3416 if_token
.control
= SVGA3DOPCOMP_GT
;
3418 if (!(emit_instruction( emit
, if_token
) &&
3419 emit_src( emit
, vface
) &&
3420 emit_src( emit
, zero
) ))
3423 for (i
= 0; i
< count
; i
++) {
3424 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), color
[i
], front
[i
] ))
3428 if (!(emit_instruction( emit
, inst_token( SVGA3DOP_ELSE
))))
3431 for (i
= 0; i
< count
; i
++) {
3432 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), color
[i
], back
[i
] ))
3436 if (!emit_instruction( emit
, inst_token( SVGA3DOP_ENDIF
) ))
3444 * Emit special setup code for the front/back face register in the FS.
3445 * 0: SETP_GT TEMP, VFACE, 0
3446 * where TEMP is a fake frontface register
3449 emit_frontface(struct svga_shader_emitter
*emit
)
3451 struct src_register vface
;
3452 SVGA3dShaderDestToken temp
;
3453 struct src_register pass
, fail
;
3455 vface
= get_vface( emit
);
3457 /* Can't use get_temp() to allocate the fake frontface reg as such
3458 * temporaries will be reclaimed after each instruction by the call
3459 * to reset_temp_regs().
3461 temp
= dst_register( SVGA3DREG_TEMP
,
3462 emit
->nr_hw_temp
++ );
3464 if (emit
->key
.fkey
.front_ccw
) {
3465 pass
= get_zero_immediate(emit
);
3466 fail
= get_one_immediate(emit
);
3468 pass
= get_one_immediate(emit
);
3469 fail
= get_zero_immediate(emit
);
3472 if (!emit_conditional(emit
, PIPE_FUNC_GREATER
,
3473 temp
, vface
, get_zero_immediate(emit
),
3477 /* Reassign the input_map to the actual front-face color:
3479 emit
->input_map
[emit
->internal_frontface_idx
] = src(temp
);
3486 * Emit code to invert the T component of the incoming texture coordinate.
3487 * This is used for drawing point sprites when
3488 * pipe_rasterizer_state::sprite_coord_mode == PIPE_SPRITE_COORD_LOWER_LEFT.
3491 emit_inverted_texcoords(struct svga_shader_emitter
*emit
)
3493 unsigned inverted_texcoords
= emit
->inverted_texcoords
;
3495 while (inverted_texcoords
) {
3496 const unsigned unit
= ffs(inverted_texcoords
) - 1;
3498 assert(emit
->inverted_texcoords
& (1 << unit
));
3500 assert(unit
< Elements(emit
->ps_true_texcoord
));
3502 assert(unit
< Elements(emit
->ps_inverted_texcoord_input
));
3504 assert(emit
->ps_inverted_texcoord_input
[unit
]
3505 < Elements(emit
->input_map
));
3507 /* inverted = coord * (1, -1, 1, 1) + (0, 1, 0, 0) */
3508 if (!submit_op3(emit
,
3509 inst_token(SVGA3DOP_MAD
),
3510 dst(emit
->ps_inverted_texcoord
[unit
]),
3511 emit
->ps_true_texcoord
[unit
],
3512 get_immediate(emit
, 1.0f
, -1.0f
, 1.0f
, 1.0f
),
3513 get_immediate(emit
, 0.0f
, 1.0f
, 0.0f
, 0.0f
)))
3516 /* Reassign the input_map entry to the new texcoord register */
3517 emit
->input_map
[emit
->ps_inverted_texcoord_input
[unit
]] =
3518 emit
->ps_inverted_texcoord
[unit
];
3520 inverted_texcoords
&= ~(1 << unit
);
3528 * Emit code to adjust vertex shader inputs/attributes:
3529 * - Change range from [0,1] to [-1,1] (for normalized byte/short attribs).
3530 * - Set attrib W component = 1.
3533 emit_adjusted_vertex_attribs(struct svga_shader_emitter
*emit
)
3535 unsigned adjust_mask
= (emit
->key
.vkey
.adjust_attrib_range
|
3536 emit
->key
.vkey
.adjust_attrib_w_1
);
3538 while (adjust_mask
) {
3539 /* Adjust vertex attrib range and/or set W component = 1 */
3540 const unsigned index
= u_bit_scan(&adjust_mask
);
3541 struct src_register tmp
;
3543 /* allocate a temp reg */
3544 tmp
= src_register(SVGA3DREG_TEMP
, emit
->nr_hw_temp
);
3547 if (emit
->key
.vkey
.adjust_attrib_range
& (1 << index
)) {
3548 /* The vertex input/attribute is supposed to be a signed value in
3549 * the range [-1,1] but we actually fetched/converted it to the
3550 * range [0,1]. This most likely happens when the app specifies a
3551 * signed byte attribute but we interpreted it as unsigned bytes.
3552 * See also svga_translate_vertex_format().
3554 * Here, we emit some extra instructions to adjust
3555 * the attribute values from [0,1] to [-1,1].
3557 * The adjustment we implement is:
3558 * new_attrib = attrib * 2.0;
3559 * if (attrib >= 0.5)
3560 * new_attrib = new_attrib - 2.0;
3561 * This isn't exactly right (it's off by a bit or so) but close enough.
3563 SVGA3dShaderDestToken pred_reg
= dst_register(SVGA3DREG_PREDICATE
, 0);
3565 /* tmp = attrib * 2.0 */
3566 if (!submit_op2(emit
,
3567 inst_token(SVGA3DOP_MUL
),
3569 emit
->input_map
[index
],
3570 get_two_immediate(emit
)))
3573 /* pred = (attrib >= 0.5) */
3574 if (!submit_op2(emit
,
3575 inst_token_setp(SVGA3DOPCOMP_GE
),
3577 emit
->input_map
[index
], /* vert attrib */
3578 get_half_immediate(emit
))) /* 0.5 */
3581 /* sub(pred) tmp, tmp, 2.0 */
3582 if (!submit_op3(emit
,
3583 inst_token_predicated(SVGA3DOP_SUB
),
3587 get_two_immediate(emit
)))
3591 /* just copy the vertex input attrib to the temp register */
3592 if (!submit_op1(emit
,
3593 inst_token(SVGA3DOP_MOV
),
3595 emit
->input_map
[index
]))
3599 if (emit
->key
.vkey
.adjust_attrib_w_1
& (1 << index
)) {
3600 /* move 1 into W position of tmp */
3601 if (!submit_op1(emit
,
3602 inst_token(SVGA3DOP_MOV
),
3603 writemask(dst(tmp
), TGSI_WRITEMASK_W
),
3604 get_one_immediate(emit
)))
3608 /* Reassign the input_map entry to the new tmp register */
3609 emit
->input_map
[index
] = tmp
;
3617 * Determine if we need to create the "common" immediate value which is
3618 * used for generating useful vector constants such as {0,0,0,0} and
3620 * We could just do this all the time except that we want to conserve
3621 * registers whenever possible.
3624 needs_to_create_common_immediate(const struct svga_shader_emitter
*emit
)
3628 if (emit
->unit
== PIPE_SHADER_FRAGMENT
) {
3629 if (emit
->key
.fkey
.light_twoside
)
3632 if (emit
->key
.fkey
.white_fragments
)
3635 if (emit
->emit_frontface
)
3638 if (emit
->info
.opcode_count
[TGSI_OPCODE_DST
] >= 1 ||
3639 emit
->info
.opcode_count
[TGSI_OPCODE_SSG
] >= 1 ||
3640 emit
->info
.opcode_count
[TGSI_OPCODE_LIT
] >= 1)
3643 if (emit
->inverted_texcoords
)
3646 /* look for any PIPE_SWIZZLE_ZERO/ONE terms */
3647 for (i
= 0; i
< emit
->key
.fkey
.num_textures
; i
++) {
3648 if (emit
->key
.fkey
.tex
[i
].swizzle_r
> PIPE_SWIZZLE_ALPHA
||
3649 emit
->key
.fkey
.tex
[i
].swizzle_g
> PIPE_SWIZZLE_ALPHA
||
3650 emit
->key
.fkey
.tex
[i
].swizzle_b
> PIPE_SWIZZLE_ALPHA
||
3651 emit
->key
.fkey
.tex
[i
].swizzle_a
> PIPE_SWIZZLE_ALPHA
)
3655 for (i
= 0; i
< emit
->key
.fkey
.num_textures
; i
++) {
3656 if (emit
->key
.fkey
.tex
[i
].compare_mode
3657 == PIPE_TEX_COMPARE_R_TO_TEXTURE
)
3661 else if (emit
->unit
== PIPE_SHADER_VERTEX
) {
3662 if (emit
->info
.opcode_count
[TGSI_OPCODE_CMP
] >= 1)
3664 if (emit
->key
.vkey
.adjust_attrib_range
||
3665 emit
->key
.vkey
.adjust_attrib_w_1
)
3669 if (emit
->info
.opcode_count
[TGSI_OPCODE_IF
] >= 1 ||
3670 emit
->info
.opcode_count
[TGSI_OPCODE_BGNLOOP
] >= 1 ||
3671 emit
->info
.opcode_count
[TGSI_OPCODE_DDX
] >= 1 ||
3672 emit
->info
.opcode_count
[TGSI_OPCODE_DDY
] >= 1 ||
3673 emit
->info
.opcode_count
[TGSI_OPCODE_ROUND
] >= 1 ||
3674 emit
->info
.opcode_count
[TGSI_OPCODE_SGE
] >= 1 ||
3675 emit
->info
.opcode_count
[TGSI_OPCODE_SGT
] >= 1 ||
3676 emit
->info
.opcode_count
[TGSI_OPCODE_SLE
] >= 1 ||
3677 emit
->info
.opcode_count
[TGSI_OPCODE_SLT
] >= 1 ||
3678 emit
->info
.opcode_count
[TGSI_OPCODE_SNE
] >= 1 ||
3679 emit
->info
.opcode_count
[TGSI_OPCODE_SEQ
] >= 1 ||
3680 emit
->info
.opcode_count
[TGSI_OPCODE_EXP
] >= 1 ||
3681 emit
->info
.opcode_count
[TGSI_OPCODE_LOG
] >= 1 ||
3682 emit
->info
.opcode_count
[TGSI_OPCODE_XPD
] >= 1 ||
3683 emit
->info
.opcode_count
[TGSI_OPCODE_KILL
] >= 1)
3691 * Do we need to create a looping constant?
3694 needs_to_create_loop_const(const struct svga_shader_emitter
*emit
)
3696 return (emit
->info
.opcode_count
[TGSI_OPCODE_BGNLOOP
] >= 1);
3701 needs_to_create_arl_consts(const struct svga_shader_emitter
*emit
)
3703 return (emit
->num_arl_consts
> 0);
3708 pre_parse_add_indirect( struct svga_shader_emitter
*emit
,
3709 int num
, int current_arl
)
3714 for (i
= 0; i
< emit
->num_arl_consts
; ++i
) {
3715 if (emit
->arl_consts
[i
].arl_num
== current_arl
)
3719 if (emit
->num_arl_consts
== i
) {
3720 ++emit
->num_arl_consts
;
3722 emit
->arl_consts
[i
].number
= (emit
->arl_consts
[i
].number
> num
) ?
3724 emit
->arl_consts
[i
].number
;
3725 emit
->arl_consts
[i
].arl_num
= current_arl
;
3731 pre_parse_instruction( struct svga_shader_emitter
*emit
,
3732 const struct tgsi_full_instruction
*insn
,
3735 if (insn
->Src
[0].Register
.Indirect
&&
3736 insn
->Src
[0].Indirect
.File
== TGSI_FILE_ADDRESS
) {
3737 const struct tgsi_full_src_register
*reg
= &insn
->Src
[0];
3738 if (reg
->Register
.Index
< 0) {
3739 pre_parse_add_indirect(emit
, reg
->Register
.Index
, current_arl
);
3743 if (insn
->Src
[1].Register
.Indirect
&&
3744 insn
->Src
[1].Indirect
.File
== TGSI_FILE_ADDRESS
) {
3745 const struct tgsi_full_src_register
*reg
= &insn
->Src
[1];
3746 if (reg
->Register
.Index
< 0) {
3747 pre_parse_add_indirect(emit
, reg
->Register
.Index
, current_arl
);
3751 if (insn
->Src
[2].Register
.Indirect
&&
3752 insn
->Src
[2].Indirect
.File
== TGSI_FILE_ADDRESS
) {
3753 const struct tgsi_full_src_register
*reg
= &insn
->Src
[2];
3754 if (reg
->Register
.Index
< 0) {
3755 pre_parse_add_indirect(emit
, reg
->Register
.Index
, current_arl
);
3764 pre_parse_tokens( struct svga_shader_emitter
*emit
,
3765 const struct tgsi_token
*tokens
)
3767 struct tgsi_parse_context parse
;
3768 int current_arl
= 0;
3770 tgsi_parse_init( &parse
, tokens
);
3772 while (!tgsi_parse_end_of_tokens( &parse
)) {
3773 tgsi_parse_token( &parse
);
3774 switch (parse
.FullToken
.Token
.Type
) {
3775 case TGSI_TOKEN_TYPE_IMMEDIATE
:
3776 case TGSI_TOKEN_TYPE_DECLARATION
:
3778 case TGSI_TOKEN_TYPE_INSTRUCTION
:
3779 if (parse
.FullToken
.FullInstruction
.Instruction
.Opcode
==
3783 if (!pre_parse_instruction( emit
, &parse
.FullToken
.FullInstruction
,
3797 svga_shader_emit_helpers(struct svga_shader_emitter
*emit
)
3799 if (needs_to_create_common_immediate( emit
)) {
3800 create_common_immediate( emit
);
3802 if (needs_to_create_loop_const( emit
)) {
3803 create_loop_const( emit
);
3805 if (needs_to_create_arl_consts( emit
)) {
3806 create_arl_consts( emit
);
3809 if (emit
->unit
== PIPE_SHADER_FRAGMENT
) {
3810 if (!emit_ps_preamble( emit
))
3813 if (emit
->key
.fkey
.light_twoside
) {
3814 if (!emit_light_twoside( emit
))
3817 if (emit
->emit_frontface
) {
3818 if (!emit_frontface( emit
))
3821 if (emit
->inverted_texcoords
) {
3822 if (!emit_inverted_texcoords( emit
))
3827 assert(emit
->unit
== PIPE_SHADER_VERTEX
);
3828 if (emit
->key
.vkey
.adjust_attrib_range
||
3829 emit
->key
.vkey
.adjust_attrib_w_1
) {
3830 if (!emit_adjusted_vertex_attribs(emit
))
3841 * This is the main entrypoint into the TGSI instruction translater.
3842 * Translate TGSI shader tokens into an SVGA shader.
3845 svga_shader_emit_instructions(struct svga_shader_emitter
*emit
,
3846 const struct tgsi_token
*tokens
)
3848 struct tgsi_parse_context parse
;
3850 boolean helpers_emitted
= FALSE
;
3851 unsigned line_nr
= 0;
3853 tgsi_parse_init( &parse
, tokens
);
3854 emit
->internal_imm_count
= 0;
3856 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
3857 ret
= emit_vs_preamble( emit
);
3862 pre_parse_tokens(emit
, tokens
);
3864 while (!tgsi_parse_end_of_tokens( &parse
)) {
3865 tgsi_parse_token( &parse
);
3867 switch (parse
.FullToken
.Token
.Type
) {
3868 case TGSI_TOKEN_TYPE_IMMEDIATE
:
3869 ret
= svga_emit_immediate( emit
, &parse
.FullToken
.FullImmediate
);
3874 case TGSI_TOKEN_TYPE_DECLARATION
:
3875 ret
= svga_translate_decl_sm30( emit
, &parse
.FullToken
.FullDeclaration
);
3880 case TGSI_TOKEN_TYPE_INSTRUCTION
:
3881 if (!helpers_emitted
) {
3882 if (!svga_shader_emit_helpers( emit
))
3884 helpers_emitted
= TRUE
;
3886 ret
= svga_emit_instruction( emit
,
3888 &parse
.FullToken
.FullInstruction
);
3896 reset_temp_regs( emit
);
3899 /* Need to terminate the current subroutine. Note that the
3900 * hardware doesn't tolerate shaders without sub-routines
3901 * terminating with RET+END.
3903 if (!emit
->in_main_func
) {
3904 ret
= emit_instruction( emit
, inst_token( SVGA3DOP_RET
) );
3909 assert(emit
->dynamic_branching_level
== 0);
3911 /* Need to terminate the whole shader:
3913 ret
= emit_instruction( emit
, inst_token( SVGA3DOP_END
) );
3918 tgsi_parse_free( &parse
);