1 /**********************************************************
2 * Copyright 2008-2009 VMware, Inc. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 **********************************************************/
27 #include "pipe/p_shader_tokens.h"
28 #include "tgsi/tgsi_parse.h"
29 #include "util/u_memory.h"
31 #include "svga_tgsi_emit.h"
32 #include "svga_context.h"
35 static boolean
emit_vs_postamble( struct svga_shader_emitter
*emit
);
36 static boolean
emit_ps_postamble( struct svga_shader_emitter
*emit
);
46 case TGSI_OPCODE_ABS
: return SVGA3DOP_ABS
;
47 case TGSI_OPCODE_ADD
: return SVGA3DOP_ADD
;
48 case TGSI_OPCODE_BREAKC
: return SVGA3DOP_BREAKC
;
49 case TGSI_OPCODE_DP2A
: return SVGA3DOP_DP2ADD
;
50 case TGSI_OPCODE_DP3
: return SVGA3DOP_DP3
;
51 case TGSI_OPCODE_DP4
: return SVGA3DOP_DP4
;
52 case TGSI_OPCODE_ENDFOR
: return SVGA3DOP_ENDLOOP
;
53 case TGSI_OPCODE_FRC
: return SVGA3DOP_FRC
;
54 case TGSI_OPCODE_BGNFOR
: return SVGA3DOP_LOOP
;
55 case TGSI_OPCODE_MAD
: return SVGA3DOP_MAD
;
56 case TGSI_OPCODE_MAX
: return SVGA3DOP_MAX
;
57 case TGSI_OPCODE_MIN
: return SVGA3DOP_MIN
;
58 case TGSI_OPCODE_MOV
: return SVGA3DOP_MOV
;
59 case TGSI_OPCODE_MUL
: return SVGA3DOP_MUL
;
60 case TGSI_OPCODE_NOP
: return SVGA3DOP_NOP
;
61 case TGSI_OPCODE_NRM4
: return SVGA3DOP_NRM
;
62 case TGSI_OPCODE_SSG
: return SVGA3DOP_SGN
;
64 debug_printf("Unkown opcode %u\n", opcode
);
66 return SVGA3DOP_LAST_INST
;
71 static unsigned translate_file( unsigned file
)
74 case TGSI_FILE_TEMPORARY
: return SVGA3DREG_TEMP
;
75 case TGSI_FILE_INPUT
: return SVGA3DREG_INPUT
;
76 case TGSI_FILE_OUTPUT
: return SVGA3DREG_OUTPUT
; /* VS3.0+ only */
77 case TGSI_FILE_IMMEDIATE
: return SVGA3DREG_CONST
;
78 case TGSI_FILE_CONSTANT
: return SVGA3DREG_CONST
;
79 case TGSI_FILE_SAMPLER
: return SVGA3DREG_SAMPLER
;
80 case TGSI_FILE_ADDRESS
: return SVGA3DREG_ADDR
;
83 return SVGA3DREG_TEMP
;
92 static SVGA3dShaderDestToken
93 translate_dst_register( struct svga_shader_emitter
*emit
,
94 const struct tgsi_full_instruction
*insn
,
97 const struct tgsi_full_dst_register
*reg
= &insn
->Dst
[idx
];
98 SVGA3dShaderDestToken dest
;
100 switch (reg
->Register
.File
) {
101 case TGSI_FILE_OUTPUT
:
102 /* Output registers encode semantic information in their name.
103 * Need to lookup a table built at decl time:
105 dest
= emit
->output_map
[reg
->Register
.Index
];
109 dest
= dst_register( translate_file( reg
->Register
.File
),
110 reg
->Register
.Index
);
114 dest
.mask
= reg
->Register
.WriteMask
;
116 if (insn
->Instruction
.Saturate
)
117 dest
.dstMod
= SVGA3DDSTMOD_SATURATE
;
123 static struct src_register
124 swizzle( struct src_register src
,
130 x
= (src
.base
.swizzle
>> (x
* 2)) & 0x3;
131 y
= (src
.base
.swizzle
>> (y
* 2)) & 0x3;
132 z
= (src
.base
.swizzle
>> (z
* 2)) & 0x3;
133 w
= (src
.base
.swizzle
>> (w
* 2)) & 0x3;
135 src
.base
.swizzle
= TRANSLATE_SWIZZLE(x
,y
,z
,w
);
140 static struct src_register
141 scalar( struct src_register src
,
144 return swizzle( src
, comp
, comp
, comp
, comp
);
147 static INLINE boolean
148 svga_arl_needs_adjustment( const struct svga_shader_emitter
*emit
)
152 for (i
= 0; i
< emit
->num_arl_consts
; ++i
) {
153 if (emit
->arl_consts
[i
].arl_num
== emit
->current_arl
)
160 svga_arl_adjustment( const struct svga_shader_emitter
*emit
)
164 for (i
= 0; i
< emit
->num_arl_consts
; ++i
) {
165 if (emit
->arl_consts
[i
].arl_num
== emit
->current_arl
)
166 return emit
->arl_consts
[i
].number
;
171 static struct src_register
172 translate_src_register( const struct svga_shader_emitter
*emit
,
173 const struct tgsi_full_src_register
*reg
)
175 struct src_register src
;
177 switch (reg
->Register
.File
) {
178 case TGSI_FILE_INPUT
:
179 /* Input registers are referred to by their semantic name rather
180 * than by index. Use the mapping build up from the decls:
182 src
= emit
->input_map
[reg
->Register
.Index
];
185 case TGSI_FILE_IMMEDIATE
:
186 /* Immediates are appended after TGSI constants in the D3D
189 src
= src_register( translate_file( reg
->Register
.File
),
190 reg
->Register
.Index
+
195 src
= src_register( translate_file( reg
->Register
.File
),
196 reg
->Register
.Index
);
201 /* Indirect addressing (for coninstant buffer lookups only)
203 if (reg
->Register
.Indirect
)
205 /* we shift the offset towards the minimum */
206 if (svga_arl_needs_adjustment( emit
)) {
207 src
.base
.num
-= svga_arl_adjustment( emit
);
209 src
.base
.relAddr
= 1;
211 /* Not really sure what should go in the second token:
213 src
.indirect
= src_token( SVGA3DREG_ADDR
,
214 reg
->Indirect
.Index
);
216 src
.indirect
.swizzle
= SWIZZLE_XXXX
;
220 reg
->Register
.SwizzleX
,
221 reg
->Register
.SwizzleY
,
222 reg
->Register
.SwizzleZ
,
223 reg
->Register
.SwizzleW
);
225 /* src.mod isn't a bitfield, unfortunately:
226 * See tgsi_util_get_full_src_register_sign_mode for implementation details.
228 if (reg
->Register
.Absolute
) {
229 if (reg
->Register
.Negate
)
230 src
.base
.srcMod
= SVGA3DSRCMOD_ABSNEG
;
232 src
.base
.srcMod
= SVGA3DSRCMOD_ABS
;
235 if (reg
->Register
.Negate
)
236 src
.base
.srcMod
= SVGA3DSRCMOD_NEG
;
238 src
.base
.srcMod
= SVGA3DSRCMOD_NONE
;
246 * Get a temporary register, return -1 if none available
248 static INLINE SVGA3dShaderDestToken
249 get_temp( struct svga_shader_emitter
*emit
)
251 int i
= emit
->nr_hw_temp
+ emit
->internal_temp_count
++;
253 return dst_register( SVGA3DREG_TEMP
, i
);
256 /* Release a single temp. Currently only effective if it was the last
257 * allocated temp, otherwise release will be delayed until the next
258 * call to reset_temp_regs().
261 release_temp( struct svga_shader_emitter
*emit
,
262 SVGA3dShaderDestToken temp
)
264 if (temp
.num
== emit
->internal_temp_count
- 1)
265 emit
->internal_temp_count
--;
268 static void reset_temp_regs( struct svga_shader_emitter
*emit
)
270 emit
->internal_temp_count
= 0;
274 static boolean
submit_op0( struct svga_shader_emitter
*emit
,
275 SVGA3dShaderInstToken inst
,
276 SVGA3dShaderDestToken dest
)
278 return (emit_instruction( emit
, inst
) &&
279 emit_dst( emit
, dest
));
282 static boolean
submit_op1( struct svga_shader_emitter
*emit
,
283 SVGA3dShaderInstToken inst
,
284 SVGA3dShaderDestToken dest
,
285 struct src_register src0
)
287 return emit_op1( emit
, inst
, dest
, src0
);
291 /* SVGA shaders may not refer to >1 constant register in a single
292 * instruction. This function checks for that usage and inserts a
293 * move to temporary if detected.
295 * The same applies to input registers -- at most a single input
296 * register may be read by any instruction.
298 static boolean
submit_op2( struct svga_shader_emitter
*emit
,
299 SVGA3dShaderInstToken inst
,
300 SVGA3dShaderDestToken dest
,
301 struct src_register src0
,
302 struct src_register src1
)
304 SVGA3dShaderDestToken temp
;
305 SVGA3dShaderRegType type0
, type1
;
306 boolean need_temp
= FALSE
;
309 type0
= SVGA3dShaderGetRegType( src0
.base
.value
);
310 type1
= SVGA3dShaderGetRegType( src1
.base
.value
);
312 if (type0
== SVGA3DREG_CONST
&&
313 type1
== SVGA3DREG_CONST
&&
314 src0
.base
.num
!= src1
.base
.num
)
317 if (type0
== SVGA3DREG_INPUT
&&
318 type1
== SVGA3DREG_INPUT
&&
319 src0
.base
.num
!= src1
.base
.num
)
324 temp
= get_temp( emit
);
326 if (!emit_op1( emit
, inst_token( SVGA3DOP_MOV
), temp
, src0
))
332 if (!emit_op2( emit
, inst
, dest
, src0
, src1
))
336 release_temp( emit
, temp
);
342 /* SVGA shaders may not refer to >1 constant register in a single
343 * instruction. This function checks for that usage and inserts a
344 * move to temporary if detected.
346 static boolean
submit_op3( struct svga_shader_emitter
*emit
,
347 SVGA3dShaderInstToken inst
,
348 SVGA3dShaderDestToken dest
,
349 struct src_register src0
,
350 struct src_register src1
,
351 struct src_register src2
)
353 SVGA3dShaderDestToken temp0
;
354 SVGA3dShaderDestToken temp1
;
355 boolean need_temp0
= FALSE
;
356 boolean need_temp1
= FALSE
;
357 SVGA3dShaderRegType type0
, type1
, type2
;
361 type0
= SVGA3dShaderGetRegType( src0
.base
.value
);
362 type1
= SVGA3dShaderGetRegType( src1
.base
.value
);
363 type2
= SVGA3dShaderGetRegType( src2
.base
.value
);
365 if (inst
.op
!= SVGA3DOP_SINCOS
) {
366 if (type0
== SVGA3DREG_CONST
&&
367 ((type1
== SVGA3DREG_CONST
&& src0
.base
.num
!= src1
.base
.num
) ||
368 (type2
== SVGA3DREG_CONST
&& src0
.base
.num
!= src2
.base
.num
)))
371 if (type1
== SVGA3DREG_CONST
&&
372 (type2
== SVGA3DREG_CONST
&& src1
.base
.num
!= src2
.base
.num
))
376 if (type0
== SVGA3DREG_INPUT
&&
377 ((type1
== SVGA3DREG_INPUT
&& src0
.base
.num
!= src1
.base
.num
) ||
378 (type2
== SVGA3DREG_INPUT
&& src0
.base
.num
!= src2
.base
.num
)))
381 if (type1
== SVGA3DREG_INPUT
&&
382 (type2
== SVGA3DREG_INPUT
&& src1
.base
.num
!= src2
.base
.num
))
387 temp0
= get_temp( emit
);
389 if (!emit_op1( emit
, inst_token( SVGA3DOP_MOV
), temp0
, src0
))
397 temp1
= get_temp( emit
);
399 if (!emit_op1( emit
, inst_token( SVGA3DOP_MOV
), temp1
, src1
))
405 if (!emit_op3( emit
, inst
, dest
, src0
, src1
, src2
))
409 release_temp( emit
, temp1
);
411 release_temp( emit
, temp0
);
418 /* SVGA shaders may not refer to >1 constant register in a single
419 * instruction. This function checks for that usage and inserts a
420 * move to temporary if detected.
422 static boolean
submit_op4( struct svga_shader_emitter
*emit
,
423 SVGA3dShaderInstToken inst
,
424 SVGA3dShaderDestToken dest
,
425 struct src_register src0
,
426 struct src_register src1
,
427 struct src_register src2
,
428 struct src_register src3
)
430 SVGA3dShaderDestToken temp0
;
431 SVGA3dShaderDestToken temp3
;
432 boolean need_temp0
= FALSE
;
433 boolean need_temp3
= FALSE
;
434 SVGA3dShaderRegType type0
, type1
, type2
, type3
;
438 type0
= SVGA3dShaderGetRegType( src0
.base
.value
);
439 type1
= SVGA3dShaderGetRegType( src1
.base
.value
);
440 type2
= SVGA3dShaderGetRegType( src2
.base
.value
);
441 type3
= SVGA3dShaderGetRegType( src2
.base
.value
);
443 /* Make life a little easier - this is only used by the TXD
444 * instruction which is guaranteed not to have a constant/input reg
445 * in one slot at least:
447 assert(type1
== SVGA3DREG_SAMPLER
);
449 if (type0
== SVGA3DREG_CONST
&&
450 ((type3
== SVGA3DREG_CONST
&& src0
.base
.num
!= src3
.base
.num
) ||
451 (type2
== SVGA3DREG_CONST
&& src0
.base
.num
!= src2
.base
.num
)))
454 if (type3
== SVGA3DREG_CONST
&&
455 (type2
== SVGA3DREG_CONST
&& src3
.base
.num
!= src2
.base
.num
))
458 if (type0
== SVGA3DREG_INPUT
&&
459 ((type3
== SVGA3DREG_INPUT
&& src0
.base
.num
!= src3
.base
.num
) ||
460 (type2
== SVGA3DREG_INPUT
&& src0
.base
.num
!= src2
.base
.num
)))
463 if (type3
== SVGA3DREG_INPUT
&&
464 (type2
== SVGA3DREG_INPUT
&& src3
.base
.num
!= src2
.base
.num
))
469 temp0
= get_temp( emit
);
471 if (!emit_op1( emit
, inst_token( SVGA3DOP_MOV
), temp0
, src0
))
479 temp3
= get_temp( emit
);
481 if (!emit_op1( emit
, inst_token( SVGA3DOP_MOV
), temp3
, src3
))
487 if (!emit_op4( emit
, inst
, dest
, src0
, src1
, src2
, src3
))
491 release_temp( emit
, temp3
);
493 release_temp( emit
, temp0
);
498 static boolean
emit_def_const( struct svga_shader_emitter
*emit
,
499 SVGA3dShaderConstType type
,
507 SVGA3dShaderInstToken opcode
;
510 case SVGA3D_CONST_TYPE_FLOAT
:
511 opcode
= inst_token( SVGA3DOP_DEF
);
512 def
.dst
= dst_register( SVGA3DREG_CONST
, idx
);
513 def
.constValues
[0] = a
;
514 def
.constValues
[1] = b
;
515 def
.constValues
[2] = c
;
516 def
.constValues
[3] = d
;
518 case SVGA3D_CONST_TYPE_INT
:
519 opcode
= inst_token( SVGA3DOP_DEFI
);
520 def
.dst
= dst_register( SVGA3DREG_CONSTINT
, idx
);
521 def
.constIValues
[0] = (int)a
;
522 def
.constIValues
[1] = (int)b
;
523 def
.constIValues
[2] = (int)c
;
524 def
.constIValues
[3] = (int)d
;
531 if (!emit_instruction(emit
, opcode
) ||
532 !svga_shader_emit_dwords( emit
, def
.values
, Elements(def
.values
)))
538 static INLINE boolean
539 create_zero_immediate( struct svga_shader_emitter
*emit
)
541 unsigned idx
= emit
->nr_hw_const
++;
543 if (!emit_def_const( emit
, SVGA3D_CONST_TYPE_FLOAT
,
547 emit
->zero_immediate_idx
= idx
;
548 emit
->created_zero_immediate
= TRUE
;
553 static INLINE boolean
554 create_loop_const( struct svga_shader_emitter
*emit
)
556 unsigned idx
= emit
->nr_hw_const
++;
558 if (!emit_def_const( emit
, SVGA3D_CONST_TYPE_INT
, idx
,
559 255, /* iteration count */
560 0, /* initial value */
562 0 /* not used, must be 0 */))
565 emit
->loop_const_idx
= idx
;
566 emit
->created_loop_const
= TRUE
;
571 static INLINE boolean
572 create_sincos_consts( struct svga_shader_emitter
*emit
)
574 unsigned idx
= emit
->nr_hw_const
++;
576 if (!emit_def_const( emit
, SVGA3D_CONST_TYPE_FLOAT
, idx
,
583 emit
->sincos_consts_idx
= idx
;
584 idx
= emit
->nr_hw_const
++;
586 if (!emit_def_const( emit
, SVGA3D_CONST_TYPE_FLOAT
, idx
,
593 emit
->created_sincos_consts
= TRUE
;
598 static INLINE boolean
599 create_arl_consts( struct svga_shader_emitter
*emit
)
603 for (i
= 0; i
< emit
->num_arl_consts
; i
+= 4) {
605 unsigned idx
= emit
->nr_hw_const
++;
607 for (j
= 0; j
< 4 && (j
+ i
) < emit
->num_arl_consts
; ++j
) {
608 vals
[j
] = emit
->arl_consts
[i
+ j
].number
;
609 emit
->arl_consts
[i
+ j
].idx
= idx
;
612 emit
->arl_consts
[i
+ 0].swizzle
= TGSI_SWIZZLE_X
;
615 emit
->arl_consts
[i
+ 0].swizzle
= TGSI_SWIZZLE_Y
;
618 emit
->arl_consts
[i
+ 0].swizzle
= TGSI_SWIZZLE_Z
;
621 emit
->arl_consts
[i
+ 0].swizzle
= TGSI_SWIZZLE_W
;
628 if (!emit_def_const( emit
, SVGA3D_CONST_TYPE_FLOAT
, idx
,
637 static INLINE
struct src_register
638 get_vface( struct svga_shader_emitter
*emit
)
640 assert(emit
->emitted_vface
);
641 return src_register(SVGA3DREG_MISCTYPE
,
645 /* returns {0, 0, 0, 1} immediate */
646 static INLINE
struct src_register
647 get_zero_immediate( struct svga_shader_emitter
*emit
)
649 assert(emit
->created_zero_immediate
);
650 assert(emit
->zero_immediate_idx
>= 0);
651 return src_register( SVGA3DREG_CONST
,
652 emit
->zero_immediate_idx
);
655 /* returns the loop const */
656 static INLINE
struct src_register
657 get_loop_const( struct svga_shader_emitter
*emit
)
659 assert(emit
->created_loop_const
);
660 assert(emit
->loop_const_idx
>= 0);
661 return src_register( SVGA3DREG_CONSTINT
,
662 emit
->loop_const_idx
);
665 /* returns a sincos const */
666 static INLINE
struct src_register
667 get_sincos_const( struct svga_shader_emitter
*emit
,
670 assert(emit
->created_sincos_consts
);
671 assert(emit
->sincos_consts_idx
>= 0);
672 assert(index
== 0 || index
== 1);
673 return src_register( SVGA3DREG_CONST
,
674 emit
->sincos_consts_idx
+ index
);
677 static INLINE
struct src_register
678 get_fake_arl_const( struct svga_shader_emitter
*emit
)
680 struct src_register reg
;
681 int idx
= 0, swizzle
= 0, i
;
683 for (i
= 0; i
< emit
->num_arl_consts
; ++ i
) {
684 if (emit
->arl_consts
[i
].arl_num
== emit
->current_arl
) {
685 idx
= emit
->arl_consts
[i
].idx
;
686 swizzle
= emit
->arl_consts
[i
].swizzle
;
690 reg
= src_register( SVGA3DREG_CONST
, idx
);
691 return scalar(reg
, swizzle
);
694 static INLINE
struct src_register
695 get_tex_dimensions( struct svga_shader_emitter
*emit
, int sampler_num
)
698 struct src_register reg
;
700 /* the width/height indexes start right after constants */
701 idx
= emit
->key
.fkey
.tex
[sampler_num
].width_height_idx
+
702 emit
->info
.file_max
[TGSI_FILE_CONSTANT
] + 1;
704 reg
= src_register( SVGA3DREG_CONST
, idx
);
708 static boolean
emit_fake_arl(struct svga_shader_emitter
*emit
,
709 const struct tgsi_full_instruction
*insn
)
711 const struct src_register src0
= translate_src_register(
712 emit
, &insn
->Src
[0] );
713 struct src_register src1
= get_fake_arl_const( emit
);
714 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
715 SVGA3dShaderDestToken tmp
= get_temp( emit
);
717 if (!submit_op1(emit
, inst_token( SVGA3DOP_MOV
), tmp
, src0
))
720 if (!submit_op2( emit
, inst_token( SVGA3DOP_ADD
), tmp
, src( tmp
),
724 /* replicate the original swizzle */
726 src1
.base
.swizzle
= src0
.base
.swizzle
;
728 return submit_op1( emit
, inst_token( SVGA3DOP_MOVA
),
732 static boolean
emit_if(struct svga_shader_emitter
*emit
,
733 const struct tgsi_full_instruction
*insn
)
735 const struct src_register src
= translate_src_register(
736 emit
, &insn
->Src
[0] );
737 struct src_register zero
= get_zero_immediate( emit
);
738 SVGA3dShaderInstToken if_token
= inst_token( SVGA3DOP_IFC
);
740 if_token
.control
= SVGA3DOPCOMPC_NE
;
741 zero
= scalar(zero
, TGSI_SWIZZLE_X
);
743 emit
->dynamic_branching_level
++;
745 return (emit_instruction( emit
, if_token
) &&
746 emit_src( emit
, src
) &&
747 emit_src( emit
, zero
) );
750 static boolean
emit_endif(struct svga_shader_emitter
*emit
,
751 const struct tgsi_full_instruction
*insn
)
753 emit
->dynamic_branching_level
--;
755 return (emit_instruction( emit
,
756 inst_token( SVGA3DOP_ENDIF
)));
759 static boolean
emit_else(struct svga_shader_emitter
*emit
,
760 const struct tgsi_full_instruction
*insn
)
762 return (emit_instruction( emit
,
763 inst_token( SVGA3DOP_ELSE
)));
766 /* Translate the following TGSI FLR instruction.
768 * To the following SVGA3D instruction sequence.
772 static boolean
emit_floor(struct svga_shader_emitter
*emit
,
773 const struct tgsi_full_instruction
*insn
)
775 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
776 const struct src_register src0
= translate_src_register(
777 emit
, &insn
->Src
[0] );
778 SVGA3dShaderDestToken temp
= get_temp( emit
);
781 if (!submit_op1( emit
, inst_token( SVGA3DOP_FRC
), temp
, src0
))
784 /* SUB DST, SRC, TMP */
785 if (!submit_op2( emit
, inst_token( SVGA3DOP_ADD
), dst
, src0
,
786 negate( src( temp
) ) ))
793 /* Translate the following TGSI CMP instruction.
794 * CMP DST, SRC0, SRC1, SRC2
795 * To the following SVGA3D instruction sequence.
796 * CMP DST, SRC0, SRC2, SRC1
798 static boolean
emit_cmp(struct svga_shader_emitter
*emit
,
799 const struct tgsi_full_instruction
*insn
)
801 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
802 const struct src_register src0
= translate_src_register(
803 emit
, &insn
->Src
[0] );
804 const struct src_register src1
= translate_src_register(
805 emit
, &insn
->Src
[1] );
806 const struct src_register src2
= translate_src_register(
807 emit
, &insn
->Src
[2] );
809 /* CMP DST, SRC0, SRC2, SRC1 */
810 return submit_op3( emit
, inst_token( SVGA3DOP_CMP
), dst
, src0
, src2
, src1
);
815 /* Translate the following TGSI DIV instruction.
816 * DIV DST.xy, SRC0, SRC1
817 * To the following SVGA3D instruction sequence.
818 * RCP TMP.x, SRC1.xxxx
819 * RCP TMP.y, SRC1.yyyy
820 * MUL DST.xy, SRC0, TMP
822 static boolean
emit_div(struct svga_shader_emitter
*emit
,
823 const struct tgsi_full_instruction
*insn
)
825 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
826 const struct src_register src0
= translate_src_register(
827 emit
, &insn
->Src
[0] );
828 const struct src_register src1
= translate_src_register(
829 emit
, &insn
->Src
[1] );
830 SVGA3dShaderDestToken temp
= get_temp( emit
);
833 /* For each enabled element, perform a RCP instruction. Note that
834 * RCP is scalar in SVGA3D:
836 for (i
= 0; i
< 4; i
++) {
837 unsigned channel
= 1 << i
;
838 if (dst
.mask
& channel
) {
839 /* RCP TMP.?, SRC1.???? */
840 if (!submit_op1( emit
, inst_token( SVGA3DOP_RCP
),
841 writemask(temp
, channel
),
847 /* Then multiply them out with a single mul:
851 if (!submit_op2( emit
, inst_token( SVGA3DOP_MUL
), dst
, src0
,
858 /* Translate the following TGSI DP2 instruction.
859 * DP2 DST, SRC1, SRC2
860 * To the following SVGA3D instruction sequence.
861 * MUL TMP, SRC1, SRC2
862 * ADD DST, TMP.xxxx, TMP.yyyy
864 static boolean
emit_dp2(struct svga_shader_emitter
*emit
,
865 const struct tgsi_full_instruction
*insn
)
867 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
868 const struct src_register src0
= translate_src_register(
869 emit
, &insn
->Src
[0] );
870 const struct src_register src1
= translate_src_register(
871 emit
, &insn
->Src
[1] );
872 SVGA3dShaderDestToken temp
= get_temp( emit
);
873 struct src_register temp_src0
, temp_src1
;
875 /* MUL TMP, SRC1, SRC2 */
876 if (!submit_op2( emit
, inst_token( SVGA3DOP_MUL
), temp
, src0
, src1
))
879 temp_src0
= scalar(src( temp
), TGSI_SWIZZLE_X
);
880 temp_src1
= scalar(src( temp
), TGSI_SWIZZLE_Y
);
882 /* ADD DST, TMP.xxxx, TMP.yyyy */
883 if (!submit_op2( emit
, inst_token( SVGA3DOP_ADD
), dst
,
884 temp_src0
, temp_src1
))
891 /* Translate the following TGSI DPH instruction.
892 * DPH DST, SRC1, SRC2
893 * To the following SVGA3D instruction sequence.
894 * DP3 TMP, SRC1, SRC2
895 * ADD DST, TMP, SRC2.wwww
897 static boolean
emit_dph(struct svga_shader_emitter
*emit
,
898 const struct tgsi_full_instruction
*insn
)
900 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
901 const struct src_register src0
= translate_src_register(
902 emit
, &insn
->Src
[0] );
903 struct src_register src1
= translate_src_register(
904 emit
, &insn
->Src
[1] );
905 SVGA3dShaderDestToken temp
= get_temp( emit
);
907 /* DP3 TMP, SRC1, SRC2 */
908 if (!submit_op2( emit
, inst_token( SVGA3DOP_DP3
), temp
, src0
, src1
))
911 src1
= scalar(src1
, TGSI_SWIZZLE_W
);
913 /* ADD DST, TMP, SRC2.wwww */
914 if (!submit_op2( emit
, inst_token( SVGA3DOP_ADD
), dst
,
921 /* Translate the following TGSI DST instruction.
923 * To the following SVGA3D instruction sequence.
928 static boolean
emit_nrm(struct svga_shader_emitter
*emit
,
929 const struct tgsi_full_instruction
*insn
)
931 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
932 const struct src_register src0
= translate_src_register(
933 emit
, &insn
->Src
[0] );
934 SVGA3dShaderDestToken temp
= get_temp( emit
);
936 /* DP3 TMP, SRC, SRC */
937 if (!submit_op2( emit
, inst_token( SVGA3DOP_DP3
), temp
, src0
, src0
))
941 if (!submit_op1( emit
, inst_token( SVGA3DOP_RSQ
), temp
, src( temp
)))
944 /* MUL DST, SRC, TMP */
945 if (!submit_op2( emit
, inst_token( SVGA3DOP_MUL
), dst
,
953 static boolean
do_emit_sincos(struct svga_shader_emitter
*emit
,
954 SVGA3dShaderDestToken dst
,
955 struct src_register src0
)
957 src0
= scalar(src0
, TGSI_SWIZZLE_X
);
959 if (emit
->use_sm30
) {
960 return submit_op1( emit
, inst_token( SVGA3DOP_SINCOS
),
963 struct src_register const1
= get_sincos_const( emit
, 0 );
964 struct src_register const2
= get_sincos_const( emit
, 1 );
966 return submit_op3( emit
, inst_token( SVGA3DOP_SINCOS
),
967 dst
, src0
, const1
, const2
);
971 static boolean
emit_sincos(struct svga_shader_emitter
*emit
,
972 const struct tgsi_full_instruction
*insn
)
974 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
975 struct src_register src0
= translate_src_register(
976 emit
, &insn
->Src
[0] );
977 SVGA3dShaderDestToken temp
= get_temp( emit
);
980 if (!do_emit_sincos(emit
, writemask(temp
, TGSI_WRITEMASK_XY
), src0
))
984 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), dst
, src( temp
) ))
994 static boolean
emit_sin(struct svga_shader_emitter
*emit
,
995 const struct tgsi_full_instruction
*insn
)
997 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
998 struct src_register src0
= translate_src_register(
999 emit
, &insn
->Src
[0] );
1000 SVGA3dShaderDestToken temp
= get_temp( emit
);
1003 if (!do_emit_sincos(emit
, writemask(temp
, TGSI_WRITEMASK_Y
), src0
))
1006 src0
= scalar(src( temp
), TGSI_SWIZZLE_Y
);
1008 /* MOV DST TMP.yyyy */
1009 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), dst
, src0
))
1019 static boolean
emit_cos(struct svga_shader_emitter
*emit
,
1020 const struct tgsi_full_instruction
*insn
)
1022 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1023 struct src_register src0
= translate_src_register(
1024 emit
, &insn
->Src
[0] );
1025 SVGA3dShaderDestToken temp
= get_temp( emit
);
1028 if (!do_emit_sincos( emit
, writemask(temp
, TGSI_WRITEMASK_X
), src0
))
1031 src0
= scalar(src( temp
), TGSI_SWIZZLE_X
);
1033 /* MOV DST TMP.xxxx */
1034 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), dst
, src0
))
1042 * ADD DST SRC0, negate(SRC0)
1044 static boolean
emit_sub(struct svga_shader_emitter
*emit
,
1045 const struct tgsi_full_instruction
*insn
)
1047 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1048 struct src_register src0
= translate_src_register(
1049 emit
, &insn
->Src
[0] );
1050 struct src_register src1
= translate_src_register(
1051 emit
, &insn
->Src
[1] );
1053 src1
= negate(src1
);
1055 if (!submit_op2( emit
, inst_token( SVGA3DOP_ADD
), dst
,
1063 static boolean
emit_kil(struct svga_shader_emitter
*emit
,
1064 const struct tgsi_full_instruction
*insn
)
1066 SVGA3dShaderInstToken inst
;
1067 const struct tgsi_full_src_register
*reg
= &insn
->Src
[0];
1068 struct src_register src0
;
1070 inst
= inst_token( SVGA3DOP_TEXKILL
);
1071 src0
= translate_src_register( emit
, reg
);
1073 if (reg
->Register
.Absolute
||
1074 reg
->Register
.Negate
||
1075 reg
->Register
.Indirect
||
1076 reg
->Register
.SwizzleX
!= 0 ||
1077 reg
->Register
.SwizzleY
!= 1 ||
1078 reg
->Register
.SwizzleZ
!= 2 ||
1079 reg
->Register
.File
!= TGSI_FILE_TEMPORARY
)
1081 SVGA3dShaderDestToken temp
= get_temp( emit
);
1083 submit_op1( emit
, inst_token( SVGA3DOP_MOV
), temp
, src0
);
1087 return submit_op0( emit
, inst
, dst(src0
) );
1091 /* mesa state tracker always emits kilp as an unconditional
1093 static boolean
emit_kilp(struct svga_shader_emitter
*emit
,
1094 const struct tgsi_full_instruction
*insn
)
1096 SVGA3dShaderInstToken inst
;
1097 SVGA3dShaderDestToken temp
;
1098 struct src_register one
= scalar( get_zero_immediate( emit
),
1101 inst
= inst_token( SVGA3DOP_TEXKILL
);
1103 /* texkill doesn't allow negation on the operand so lets move
1104 * negation of {1} to a temp register */
1105 temp
= get_temp( emit
);
1106 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), temp
,
1110 return submit_op0( emit
, inst
, temp
);
1113 /* Implement conditionals by initializing destination reg to 'fail',
1114 * then set predicate reg with UFOP_SETP, then move 'pass' to dest
1115 * based on predicate reg.
1117 * SETP src0, cmp, src1 -- do this first to avoid aliasing problems.
1122 emit_conditional(struct svga_shader_emitter
*emit
,
1123 unsigned compare_func
,
1124 SVGA3dShaderDestToken dst
,
1125 struct src_register src0
,
1126 struct src_register src1
,
1127 struct src_register pass
,
1128 struct src_register fail
)
1130 SVGA3dShaderDestToken pred_reg
= dst_register( SVGA3DREG_PREDICATE
, 0 );
1131 SVGA3dShaderInstToken setp_token
, mov_token
;
1132 setp_token
= inst_token( SVGA3DOP_SETP
);
1134 switch (compare_func
) {
1135 case PIPE_FUNC_NEVER
:
1136 return submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
1139 case PIPE_FUNC_LESS
:
1140 setp_token
.control
= SVGA3DOPCOMP_LT
;
1142 case PIPE_FUNC_EQUAL
:
1143 setp_token
.control
= SVGA3DOPCOMP_EQ
;
1145 case PIPE_FUNC_LEQUAL
:
1146 setp_token
.control
= SVGA3DOPCOMP_LE
;
1148 case PIPE_FUNC_GREATER
:
1149 setp_token
.control
= SVGA3DOPCOMP_GT
;
1151 case PIPE_FUNC_NOTEQUAL
:
1152 setp_token
.control
= SVGA3DOPCOMPC_NE
;
1154 case PIPE_FUNC_GEQUAL
:
1155 setp_token
.control
= SVGA3DOPCOMP_GE
;
1157 case PIPE_FUNC_ALWAYS
:
1158 return submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
1163 /* SETP src0, COMPOP, src1 */
1164 if (!submit_op2( emit
, setp_token
, pred_reg
,
1168 mov_token
= inst_token( SVGA3DOP_MOV
);
1171 if (!submit_op1( emit
, mov_token
, dst
,
1175 /* MOV dst, pass (predicated)
1177 * Note that the predicate reg (and possible modifiers) is passed
1178 * as the first source argument.
1180 mov_token
.predicated
= 1;
1181 if (!submit_op2( emit
, mov_token
, dst
,
1182 src( pred_reg
), pass
))
1190 emit_select(struct svga_shader_emitter
*emit
,
1191 unsigned compare_func
,
1192 SVGA3dShaderDestToken dst
,
1193 struct src_register src0
,
1194 struct src_register src1
)
1196 /* There are some SVGA instructions which implement some selects
1197 * directly, but they are only available in the vertex shader.
1199 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
1200 switch (compare_func
) {
1201 case PIPE_FUNC_GEQUAL
:
1202 return submit_op2( emit
, inst_token( SVGA3DOP_SGE
), dst
, src0
, src1
);
1203 case PIPE_FUNC_LEQUAL
:
1204 return submit_op2( emit
, inst_token( SVGA3DOP_SGE
), dst
, src1
, src0
);
1205 case PIPE_FUNC_GREATER
:
1206 return submit_op2( emit
, inst_token( SVGA3DOP_SLT
), dst
, src1
, src0
);
1207 case PIPE_FUNC_LESS
:
1208 return submit_op2( emit
, inst_token( SVGA3DOP_SLT
), dst
, src0
, src1
);
1215 /* Otherwise, need to use the setp approach:
1218 struct src_register one
, zero
;
1219 /* zero immediate is 0,0,0,1 */
1220 zero
= get_zero_immediate( emit
);
1221 one
= scalar( zero
, TGSI_SWIZZLE_W
);
1222 zero
= scalar( zero
, TGSI_SWIZZLE_X
);
1224 return emit_conditional(
1235 static boolean
emit_select_op(struct svga_shader_emitter
*emit
,
1237 const struct tgsi_full_instruction
*insn
)
1239 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1240 struct src_register src0
= translate_src_register(
1241 emit
, &insn
->Src
[0] );
1242 struct src_register src1
= translate_src_register(
1243 emit
, &insn
->Src
[1] );
1245 return emit_select( emit
, compare
, dst
, src0
, src1
);
1249 /* Translate texture instructions to SVGA3D representation.
1251 static boolean
emit_tex2(struct svga_shader_emitter
*emit
,
1252 const struct tgsi_full_instruction
*insn
,
1253 SVGA3dShaderDestToken dst
)
1255 SVGA3dShaderInstToken inst
;
1256 struct src_register texcoord
;
1257 struct src_register sampler
;
1258 SVGA3dShaderDestToken tmp
;
1262 switch (insn
->Instruction
.Opcode
) {
1263 case TGSI_OPCODE_TEX
:
1264 inst
.op
= SVGA3DOP_TEX
;
1266 case TGSI_OPCODE_TXP
:
1267 inst
.op
= SVGA3DOP_TEX
;
1268 inst
.control
= SVGA3DOPCONT_PROJECT
;
1270 case TGSI_OPCODE_TXB
:
1271 inst
.op
= SVGA3DOP_TEX
;
1272 inst
.control
= SVGA3DOPCONT_BIAS
;
1274 case TGSI_OPCODE_TXL
:
1275 inst
.op
= SVGA3DOP_TEXLDL
;
1282 texcoord
= translate_src_register( emit
, &insn
->Src
[0] );
1283 sampler
= translate_src_register( emit
, &insn
->Src
[1] );
1285 if (emit
->key
.fkey
.tex
[sampler
.base
.num
].unnormalized
||
1286 emit
->dynamic_branching_level
> 0)
1287 tmp
= get_temp( emit
);
1289 /* Can't do mipmapping inside dynamic branch constructs. Force LOD
1290 * zero in that case.
1292 if (emit
->dynamic_branching_level
> 0 &&
1293 inst
.op
== SVGA3DOP_TEX
&&
1294 SVGA3dShaderGetRegType(texcoord
.base
.value
) == SVGA3DREG_TEMP
) {
1295 struct src_register zero
= get_zero_immediate( emit
);
1297 /* MOV tmp, texcoord */
1298 if (!submit_op1( emit
,
1299 inst_token( SVGA3DOP_MOV
),
1304 /* MOV tmp.w, zero */
1305 if (!submit_op1( emit
,
1306 inst_token( SVGA3DOP_MOV
),
1307 writemask( tmp
, TGSI_WRITEMASK_W
),
1308 scalar( zero
, TGSI_SWIZZLE_X
)))
1311 texcoord
= src( tmp
);
1312 inst
.op
= SVGA3DOP_TEXLDL
;
1315 /* Explicit normalization of texcoords:
1317 if (emit
->key
.fkey
.tex
[sampler
.base
.num
].unnormalized
) {
1318 struct src_register wh
= get_tex_dimensions( emit
, sampler
.base
.num
);
1320 /* MUL tmp, SRC0, WH */
1321 if (!submit_op2( emit
, inst_token( SVGA3DOP_MUL
),
1322 tmp
, texcoord
, wh
))
1325 texcoord
= src( tmp
);
1328 return submit_op2( emit
, inst
, dst
, texcoord
, sampler
);
1334 /* Translate texture instructions to SVGA3D representation.
1336 static boolean
emit_tex4(struct svga_shader_emitter
*emit
,
1337 const struct tgsi_full_instruction
*insn
,
1338 SVGA3dShaderDestToken dst
)
1340 SVGA3dShaderInstToken inst
;
1341 struct src_register texcoord
;
1342 struct src_register ddx
;
1343 struct src_register ddy
;
1344 struct src_register sampler
;
1346 texcoord
= translate_src_register( emit
, &insn
->Src
[0] );
1347 ddx
= translate_src_register( emit
, &insn
->Src
[1] );
1348 ddy
= translate_src_register( emit
, &insn
->Src
[2] );
1349 sampler
= translate_src_register( emit
, &insn
->Src
[3] );
1353 switch (insn
->Instruction
.Opcode
) {
1354 case TGSI_OPCODE_TXD
:
1355 inst
.op
= SVGA3DOP_TEXLDD
; /* 4 args! */
1362 return submit_op4( emit
, inst
, dst
, texcoord
, sampler
, ddx
, ddy
);
1366 static boolean
emit_tex(struct svga_shader_emitter
*emit
,
1367 const struct tgsi_full_instruction
*insn
)
1369 SVGA3dShaderDestToken dst
=
1370 translate_dst_register( emit
, insn
, 0 );
1371 struct src_register src0
=
1372 translate_src_register( emit
, &insn
->Src
[0] );
1373 struct src_register src1
=
1374 translate_src_register( emit
, &insn
->Src
[1] );
1376 SVGA3dShaderDestToken tex_result
;
1378 /* check for shadow samplers */
1379 boolean compare
= (emit
->key
.fkey
.tex
[src1
.base
.num
].compare_mode
==
1380 PIPE_TEX_COMPARE_R_TO_TEXTURE
);
1383 /* If doing compare processing, need to put this value into a
1384 * temporary so it can be used as a source later on.
1387 (!emit
->use_sm30
&& dst
.mask
!= TGSI_WRITEMASK_XYZW
) ) {
1388 tex_result
= get_temp( emit
);
1394 switch(insn
->Instruction
.Opcode
) {
1395 case TGSI_OPCODE_TEX
:
1396 case TGSI_OPCODE_TXB
:
1397 case TGSI_OPCODE_TXP
:
1398 case TGSI_OPCODE_TXL
:
1399 if (!emit_tex2( emit
, insn
, tex_result
))
1402 case TGSI_OPCODE_TXD
:
1403 if (!emit_tex4( emit
, insn
, tex_result
))
1412 SVGA3dShaderDestToken src0_zdivw
= get_temp( emit
);
1413 struct src_register tex_src_x
= scalar(src(tex_result
), TGSI_SWIZZLE_Y
);
1414 struct src_register one
=
1415 scalar( get_zero_immediate( emit
), TGSI_SWIZZLE_W
);
1417 /* Divide texcoord R by Q */
1418 if (!submit_op1( emit
, inst_token( SVGA3DOP_RCP
),
1420 scalar(src0
, TGSI_SWIZZLE_W
) ))
1423 if (!submit_op2( emit
, inst_token( SVGA3DOP_MUL
),
1425 scalar(src0
, TGSI_SWIZZLE_Z
),
1431 emit
->key
.fkey
.tex
[src1
.base
.num
].compare_func
,
1437 return submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
1438 writemask( dst
, TGSI_WRITEMASK_W
),
1441 else if (!emit
->use_sm30
&& dst
.mask
!= TGSI_WRITEMASK_XYZW
)
1443 if (!emit_op1( emit
, inst_token( SVGA3DOP_MOV
), dst
, src(tex_result
) ))
1450 static boolean
emit_bgnloop2( struct svga_shader_emitter
*emit
,
1451 const struct tgsi_full_instruction
*insn
)
1453 SVGA3dShaderInstToken inst
= inst_token( SVGA3DOP_LOOP
);
1454 struct src_register loop_reg
= src_register( SVGA3DREG_LOOP
, 0 );
1455 struct src_register const_int
= get_loop_const( emit
);
1457 emit
->dynamic_branching_level
++;
1459 return (emit_instruction( emit
, inst
) &&
1460 emit_src( emit
, loop_reg
) &&
1461 emit_src( emit
, const_int
) );
1464 static boolean
emit_endloop2( struct svga_shader_emitter
*emit
,
1465 const struct tgsi_full_instruction
*insn
)
1467 SVGA3dShaderInstToken inst
= inst_token( SVGA3DOP_ENDLOOP
);
1469 emit
->dynamic_branching_level
--;
1471 return emit_instruction( emit
, inst
);
1474 static boolean
emit_brk( struct svga_shader_emitter
*emit
,
1475 const struct tgsi_full_instruction
*insn
)
1477 SVGA3dShaderInstToken inst
= inst_token( SVGA3DOP_BREAK
);
1478 return emit_instruction( emit
, inst
);
1481 static boolean
emit_scalar_op1( struct svga_shader_emitter
*emit
,
1483 const struct tgsi_full_instruction
*insn
)
1485 SVGA3dShaderInstToken inst
;
1486 SVGA3dShaderDestToken dst
;
1487 struct src_register src
;
1489 inst
= inst_token( opcode
);
1490 dst
= translate_dst_register( emit
, insn
, 0 );
1491 src
= translate_src_register( emit
, &insn
->Src
[0] );
1492 src
= scalar( src
, TGSI_SWIZZLE_X
);
1494 return submit_op1( emit
, inst
, dst
, src
);
1498 static boolean
emit_simple_instruction(struct svga_shader_emitter
*emit
,
1500 const struct tgsi_full_instruction
*insn
)
1502 const struct tgsi_full_src_register
*src
= insn
->Src
;
1503 SVGA3dShaderInstToken inst
;
1504 SVGA3dShaderDestToken dst
;
1506 inst
= inst_token( opcode
);
1507 dst
= translate_dst_register( emit
, insn
, 0 );
1509 switch (insn
->Instruction
.NumSrcRegs
) {
1511 return submit_op0( emit
, inst
, dst
);
1513 return submit_op1( emit
, inst
, dst
,
1514 translate_src_register( emit
, &src
[0] ));
1516 return submit_op2( emit
, inst
, dst
,
1517 translate_src_register( emit
, &src
[0] ),
1518 translate_src_register( emit
, &src
[1] ) );
1520 return submit_op3( emit
, inst
, dst
,
1521 translate_src_register( emit
, &src
[0] ),
1522 translate_src_register( emit
, &src
[1] ),
1523 translate_src_register( emit
, &src
[2] ) );
1531 static boolean
emit_deriv(struct svga_shader_emitter
*emit
,
1532 const struct tgsi_full_instruction
*insn
)
1534 if (emit
->dynamic_branching_level
> 0 &&
1535 insn
->Src
[0].Register
.File
== TGSI_FILE_TEMPORARY
)
1537 struct src_register zero
= get_zero_immediate( emit
);
1538 SVGA3dShaderDestToken dst
=
1539 translate_dst_register( emit
, insn
, 0 );
1541 /* Deriv opcodes not valid inside dynamic branching, workaround
1542 * by zeroing out the destination.
1544 if (!submit_op1(emit
,
1545 inst_token( SVGA3DOP_MOV
),
1547 scalar(zero
, TGSI_SWIZZLE_X
)))
1555 switch (insn
->Instruction
.Opcode
) {
1556 case TGSI_OPCODE_DDX
:
1557 opcode
= SVGA3DOP_DSX
;
1559 case TGSI_OPCODE_DDY
:
1560 opcode
= SVGA3DOP_DSY
;
1566 return emit_simple_instruction( emit
, opcode
, insn
);
1570 static boolean
emit_arl(struct svga_shader_emitter
*emit
,
1571 const struct tgsi_full_instruction
*insn
)
1573 ++emit
->current_arl
;
1574 if (svga_arl_needs_adjustment( emit
)) {
1575 return emit_fake_arl( emit
, insn
);
1577 /* no need to adjust, just emit straight arl */
1578 return emit_simple_instruction(emit
, SVGA3DOP_MOVA
, insn
);
1582 static boolean
alias_src_dst( struct src_register src
,
1583 SVGA3dShaderDestToken dst
)
1585 if (src
.base
.num
!= dst
.num
)
1588 if (SVGA3dShaderGetRegType(dst
.value
) !=
1589 SVGA3dShaderGetRegType(src
.base
.value
))
1595 static boolean
emit_pow(struct svga_shader_emitter
*emit
,
1596 const struct tgsi_full_instruction
*insn
)
1598 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1599 struct src_register src0
= translate_src_register(
1600 emit
, &insn
->Src
[0] );
1601 struct src_register src1
= translate_src_register(
1602 emit
, &insn
->Src
[1] );
1603 boolean need_tmp
= FALSE
;
1605 /* POW can only output to a temporary */
1606 if (insn
->Dst
[0].Register
.File
!= TGSI_FILE_TEMPORARY
)
1609 /* POW src1 must not be the same register as dst */
1610 if (alias_src_dst( src1
, dst
))
1613 /* it's a scalar op */
1614 src0
= scalar( src0
, TGSI_SWIZZLE_X
);
1615 src1
= scalar( src1
, TGSI_SWIZZLE_X
);
1618 SVGA3dShaderDestToken tmp
= writemask(get_temp( emit
), TGSI_WRITEMASK_X
);
1620 if (!submit_op2(emit
, inst_token( SVGA3DOP_POW
), tmp
, src0
, src1
))
1623 return submit_op1(emit
, inst_token( SVGA3DOP_MOV
), dst
, scalar(src(tmp
), 0) );
1626 return submit_op2(emit
, inst_token( SVGA3DOP_POW
), dst
, src0
, src1
);
1630 static boolean
emit_xpd(struct svga_shader_emitter
*emit
,
1631 const struct tgsi_full_instruction
*insn
)
1633 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1634 const struct src_register src0
= translate_src_register(
1635 emit
, &insn
->Src
[0] );
1636 const struct src_register src1
= translate_src_register(
1637 emit
, &insn
->Src
[1] );
1638 boolean need_dst_tmp
= FALSE
;
1640 /* XPD can only output to a temporary */
1641 if (SVGA3dShaderGetRegType(dst
.value
) != SVGA3DREG_TEMP
)
1642 need_dst_tmp
= TRUE
;
1644 /* The dst reg must not be the same as src0 or src1*/
1645 if (alias_src_dst(src0
, dst
) ||
1646 alias_src_dst(src1
, dst
))
1647 need_dst_tmp
= TRUE
;
1650 SVGA3dShaderDestToken tmp
= get_temp( emit
);
1652 /* Obey DX9 restrictions on mask:
1654 tmp
.mask
= dst
.mask
& TGSI_WRITEMASK_XYZ
;
1656 if (!submit_op2(emit
, inst_token( SVGA3DOP_CRS
), tmp
, src0
, src1
))
1659 if (!submit_op1(emit
, inst_token( SVGA3DOP_MOV
), dst
, src( tmp
)))
1663 if (!submit_op2(emit
, inst_token( SVGA3DOP_CRS
), dst
, src0
, src1
))
1667 /* Need to emit 1.0 to dst.w?
1669 if (dst
.mask
& TGSI_WRITEMASK_W
) {
1670 struct src_register zero
= get_zero_immediate( emit
);
1672 if (!submit_op1(emit
,
1673 inst_token( SVGA3DOP_MOV
),
1674 writemask(dst
, TGSI_WRITEMASK_W
),
1683 static boolean
emit_lrp(struct svga_shader_emitter
*emit
,
1684 const struct tgsi_full_instruction
*insn
)
1686 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1687 SVGA3dShaderDestToken tmp
;
1688 const struct src_register src0
= translate_src_register(
1689 emit
, &insn
->Src
[0] );
1690 const struct src_register src1
= translate_src_register(
1691 emit
, &insn
->Src
[1] );
1692 const struct src_register src2
= translate_src_register(
1693 emit
, &insn
->Src
[2] );
1694 boolean need_dst_tmp
= FALSE
;
1696 /* The dst reg must not be the same as src0 or src2 */
1697 if (alias_src_dst(src0
, dst
) ||
1698 alias_src_dst(src2
, dst
))
1699 need_dst_tmp
= TRUE
;
1702 tmp
= get_temp( emit
);
1703 tmp
.mask
= dst
.mask
;
1709 if (!submit_op3(emit
, inst_token( SVGA3DOP_LRP
), tmp
, src0
, src1
, src2
))
1713 if (!submit_op1(emit
, inst_token( SVGA3DOP_MOV
), dst
, src( tmp
)))
1721 static boolean
emit_dst_insn(struct svga_shader_emitter
*emit
,
1722 const struct tgsi_full_instruction
*insn
)
1724 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
1725 /* SVGA/DX9 has a DST instruction, but only for vertex shaders:
1727 return emit_simple_instruction(emit
, SVGA3DOP_DST
, insn
);
1731 /* result[0] = 1 * 1;
1732 * result[1] = a[1] * b[1];
1733 * result[2] = a[2] * 1;
1734 * result[3] = 1 * b[3];
1737 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1738 SVGA3dShaderDestToken tmp
;
1739 const struct src_register src0
= translate_src_register(
1740 emit
, &insn
->Src
[0] );
1741 const struct src_register src1
= translate_src_register(
1742 emit
, &insn
->Src
[1] );
1743 struct src_register zero
= get_zero_immediate( emit
);
1744 boolean need_tmp
= FALSE
;
1746 if (SVGA3dShaderGetRegType(dst
.value
) != SVGA3DREG_TEMP
||
1747 alias_src_dst(src0
, dst
) ||
1748 alias_src_dst(src1
, dst
))
1752 tmp
= get_temp( emit
);
1760 if (tmp
.mask
& TGSI_WRITEMASK_XW
) {
1761 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
1762 writemask(tmp
, TGSI_WRITEMASK_XW
),
1769 if (tmp
.mask
& TGSI_WRITEMASK_YZ
) {
1770 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
1771 writemask(tmp
, TGSI_WRITEMASK_YZ
),
1776 /* tmp.yw = tmp * src1
1778 if (tmp
.mask
& TGSI_WRITEMASK_YW
) {
1779 if (!submit_op2( emit
, inst_token( SVGA3DOP_MUL
),
1780 writemask(tmp
, TGSI_WRITEMASK_YW
),
1789 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
1800 static boolean
emit_exp(struct svga_shader_emitter
*emit
,
1801 const struct tgsi_full_instruction
*insn
)
1803 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1804 struct src_register src0
=
1805 translate_src_register( emit
, &insn
->Src
[0] );
1806 struct src_register zero
= get_zero_immediate( emit
);
1807 SVGA3dShaderDestToken fraction
;
1809 if (dst
.mask
& TGSI_WRITEMASK_Y
)
1811 else if (dst
.mask
& TGSI_WRITEMASK_X
)
1812 fraction
= get_temp( emit
);
1814 /* If y is being written, fill it with src0 - floor(src0).
1816 if (dst
.mask
& TGSI_WRITEMASK_XY
) {
1817 if (!submit_op1( emit
, inst_token( SVGA3DOP_FRC
),
1818 writemask( fraction
, TGSI_WRITEMASK_Y
),
1823 /* If x is being written, fill it with 2 ^ floor(src0).
1825 if (dst
.mask
& TGSI_WRITEMASK_X
) {
1826 if (!submit_op2( emit
, inst_token( SVGA3DOP_ADD
),
1827 writemask( dst
, dst
.mask
& TGSI_WRITEMASK_X
),
1829 scalar( negate( src( fraction
) ), TGSI_SWIZZLE_Y
) ) )
1832 if (!submit_op1( emit
, inst_token( SVGA3DOP_EXP
),
1833 writemask( dst
, dst
.mask
& TGSI_WRITEMASK_X
),
1834 scalar( src( dst
), TGSI_SWIZZLE_X
) ) )
1837 if (!(dst
.mask
& TGSI_WRITEMASK_Y
))
1838 release_temp( emit
, fraction
);
1841 /* If z is being written, fill it with 2 ^ src0 (partial precision).
1843 if (dst
.mask
& TGSI_WRITEMASK_Z
) {
1844 if (!submit_op1( emit
, inst_token( SVGA3DOP_EXPP
),
1845 writemask( dst
, dst
.mask
& TGSI_WRITEMASK_Z
),
1850 /* If w is being written, fill it with one.
1852 if (dst
.mask
& TGSI_WRITEMASK_W
) {
1853 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
1854 writemask(dst
, TGSI_WRITEMASK_W
),
1855 scalar( zero
, TGSI_SWIZZLE_W
) ))
1862 static boolean
emit_lit(struct svga_shader_emitter
*emit
,
1863 const struct tgsi_full_instruction
*insn
)
1865 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
1866 /* SVGA/DX9 has a LIT instruction, but only for vertex shaders:
1868 return emit_simple_instruction(emit
, SVGA3DOP_LIT
, insn
);
1872 /* D3D vs. GL semantics can be fairly easily accomodated by
1873 * variations on this sequence.
1877 * tmp.z = pow(src.y,src.w)
1878 * p0 = src0.xxxx > 0
1879 * result = zero.wxxw
1880 * (p0) result.yz = tmp
1884 * tmp.z = pow(src.y,src.w)
1885 * p0 = src0.xxyy > 0
1886 * result = zero.wxxw
1887 * (p0) result.yz = tmp
1889 * Will implement the GL version for now.
1892 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1893 SVGA3dShaderDestToken tmp
= get_temp( emit
);
1894 const struct src_register src0
= translate_src_register(
1895 emit
, &insn
->Src
[0] );
1896 struct src_register zero
= get_zero_immediate( emit
);
1898 /* tmp = pow(src.y, src.w)
1900 if (dst
.mask
& TGSI_WRITEMASK_Z
) {
1901 if (!submit_op2(emit
, inst_token( SVGA3DOP_POW
),
1910 if (dst
.mask
& TGSI_WRITEMASK_Y
) {
1911 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
1912 writemask(tmp
, TGSI_WRITEMASK_Y
),
1917 /* Can't quite do this with emit conditional due to the extra
1918 * writemask on the predicated mov:
1921 SVGA3dShaderDestToken pred_reg
= dst_register( SVGA3DREG_PREDICATE
, 0 );
1922 SVGA3dShaderInstToken setp_token
, mov_token
;
1923 struct src_register predsrc
;
1925 setp_token
= inst_token( SVGA3DOP_SETP
);
1926 mov_token
= inst_token( SVGA3DOP_MOV
);
1928 setp_token
.control
= SVGA3DOPCOMP_GT
;
1930 /* D3D vs GL semantics:
1933 predsrc
= swizzle(src0
, 0, 0, 1, 1); /* D3D */
1935 predsrc
= swizzle(src0
, 0, 0, 0, 0); /* GL */
1937 /* SETP src0.xxyy, GT, {0}.x */
1938 if (!submit_op2( emit
, setp_token
, pred_reg
,
1940 swizzle(zero
, 0, 0, 0, 0) ))
1944 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), dst
,
1945 swizzle(zero
, 3, 0, 0, 3 )))
1948 /* MOV dst.yz, tmp (predicated)
1950 * Note that the predicate reg (and possible modifiers) is passed
1951 * as the first source argument.
1953 if (dst
.mask
& TGSI_WRITEMASK_YZ
) {
1954 mov_token
.predicated
= 1;
1955 if (!submit_op2( emit
, mov_token
,
1956 writemask(dst
, TGSI_WRITEMASK_YZ
),
1957 src( pred_reg
), src( tmp
) ))
1969 static boolean
emit_ex2( struct svga_shader_emitter
*emit
,
1970 const struct tgsi_full_instruction
*insn
)
1972 SVGA3dShaderInstToken inst
;
1973 SVGA3dShaderDestToken dst
;
1974 struct src_register src0
;
1976 inst
= inst_token( SVGA3DOP_EXP
);
1977 dst
= translate_dst_register( emit
, insn
, 0 );
1978 src0
= translate_src_register( emit
, &insn
->Src
[0] );
1979 src0
= scalar( src0
, TGSI_SWIZZLE_X
);
1981 if (dst
.mask
!= TGSI_WRITEMASK_XYZW
) {
1982 SVGA3dShaderDestToken tmp
= get_temp( emit
);
1984 if (!submit_op1( emit
, inst
, tmp
, src0
))
1987 return submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
1989 scalar( src( tmp
), TGSI_SWIZZLE_X
) );
1992 return submit_op1( emit
, inst
, dst
, src0
);
1996 static boolean
emit_log(struct svga_shader_emitter
*emit
,
1997 const struct tgsi_full_instruction
*insn
)
1999 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
2000 struct src_register src0
=
2001 translate_src_register( emit
, &insn
->Src
[0] );
2002 struct src_register zero
= get_zero_immediate( emit
);
2003 SVGA3dShaderDestToken abs_tmp
;
2004 struct src_register abs_src0
;
2005 SVGA3dShaderDestToken log2_abs
;
2007 if (dst
.mask
& TGSI_WRITEMASK_Z
)
2009 else if (dst
.mask
& TGSI_WRITEMASK_XY
)
2010 log2_abs
= get_temp( emit
);
2012 /* If z is being written, fill it with log2( abs( src0 ) ).
2014 if (dst
.mask
& TGSI_WRITEMASK_XYZ
) {
2015 if (!src0
.base
.srcMod
|| src0
.base
.srcMod
== SVGA3DSRCMOD_ABS
)
2018 abs_tmp
= get_temp( emit
);
2020 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
2025 abs_src0
= src( abs_tmp
);
2028 abs_src0
= absolute( scalar( abs_src0
, TGSI_SWIZZLE_X
) );
2030 if (!submit_op1( emit
, inst_token( SVGA3DOP_LOG
),
2031 writemask( log2_abs
, TGSI_WRITEMASK_Z
),
2036 if (dst
.mask
& TGSI_WRITEMASK_XY
) {
2037 SVGA3dShaderDestToken floor_log2
;
2039 if (dst
.mask
& TGSI_WRITEMASK_X
)
2042 floor_log2
= get_temp( emit
);
2044 /* If x is being written, fill it with floor( log2( abs( src0 ) ) ).
2046 if (!submit_op1( emit
, inst_token( SVGA3DOP_FRC
),
2047 writemask( floor_log2
, TGSI_WRITEMASK_X
),
2048 scalar( src( log2_abs
), TGSI_SWIZZLE_Z
) ) )
2051 if (!submit_op2( emit
, inst_token( SVGA3DOP_ADD
),
2052 writemask( floor_log2
, TGSI_WRITEMASK_X
),
2053 scalar( src( log2_abs
), TGSI_SWIZZLE_Z
),
2054 negate( src( floor_log2
) ) ) )
2057 /* If y is being written, fill it with
2058 * abs ( src0 ) / ( 2 ^ floor( log2( abs( src0 ) ) ) ).
2060 if (dst
.mask
& TGSI_WRITEMASK_Y
) {
2061 if (!submit_op1( emit
, inst_token( SVGA3DOP_EXP
),
2062 writemask( dst
, TGSI_WRITEMASK_Y
),
2063 negate( scalar( src( floor_log2
),
2064 TGSI_SWIZZLE_X
) ) ) )
2067 if (!submit_op2( emit
, inst_token( SVGA3DOP_MUL
),
2068 writemask( dst
, TGSI_WRITEMASK_Y
),
2074 if (!(dst
.mask
& TGSI_WRITEMASK_X
))
2075 release_temp( emit
, floor_log2
);
2077 if (!(dst
.mask
& TGSI_WRITEMASK_Z
))
2078 release_temp( emit
, log2_abs
);
2081 if (dst
.mask
& TGSI_WRITEMASK_XYZ
&& src0
.base
.srcMod
&&
2082 src0
.base
.srcMod
!= SVGA3DSRCMOD_ABS
)
2083 release_temp( emit
, abs_tmp
);
2085 /* If w is being written, fill it with one.
2087 if (dst
.mask
& TGSI_WRITEMASK_W
) {
2088 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
2089 writemask(dst
, TGSI_WRITEMASK_W
),
2090 scalar( zero
, TGSI_SWIZZLE_W
) ))
2098 static boolean
emit_bgnsub( struct svga_shader_emitter
*emit
,
2100 const struct tgsi_full_instruction
*insn
)
2104 /* Note that we've finished the main function and are now emitting
2105 * subroutines. This affects how we terminate the generated
2108 emit
->in_main_func
= FALSE
;
2110 for (i
= 0; i
< emit
->nr_labels
; i
++) {
2111 if (emit
->label
[i
] == position
) {
2112 return (emit_instruction( emit
, inst_token( SVGA3DOP_RET
) ) &&
2113 emit_instruction( emit
, inst_token( SVGA3DOP_LABEL
) ) &&
2114 emit_src( emit
, src_register( SVGA3DREG_LABEL
, i
)));
2122 static boolean
emit_call( struct svga_shader_emitter
*emit
,
2123 const struct tgsi_full_instruction
*insn
)
2125 unsigned position
= insn
->Label
.Label
;
2128 for (i
= 0; i
< emit
->nr_labels
; i
++) {
2129 if (emit
->label
[i
] == position
)
2133 if (emit
->nr_labels
== Elements(emit
->label
))
2136 if (i
== emit
->nr_labels
) {
2137 emit
->label
[i
] = position
;
2141 return (emit_instruction( emit
, inst_token( SVGA3DOP_CALL
) ) &&
2142 emit_src( emit
, src_register( SVGA3DREG_LABEL
, i
)));
2146 static boolean
emit_end( struct svga_shader_emitter
*emit
)
2148 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
2149 return emit_vs_postamble( emit
);
2152 return emit_ps_postamble( emit
);
2158 static boolean
svga_emit_instruction( struct svga_shader_emitter
*emit
,
2160 const struct tgsi_full_instruction
*insn
)
2162 switch (insn
->Instruction
.Opcode
) {
2164 case TGSI_OPCODE_ARL
:
2165 return emit_arl( emit
, insn
);
2167 case TGSI_OPCODE_TEX
:
2168 case TGSI_OPCODE_TXB
:
2169 case TGSI_OPCODE_TXP
:
2170 case TGSI_OPCODE_TXL
:
2171 case TGSI_OPCODE_TXD
:
2172 return emit_tex( emit
, insn
);
2174 case TGSI_OPCODE_DDX
:
2175 case TGSI_OPCODE_DDY
:
2176 return emit_deriv( emit
, insn
);
2178 case TGSI_OPCODE_BGNSUB
:
2179 return emit_bgnsub( emit
, position
, insn
);
2181 case TGSI_OPCODE_ENDSUB
:
2184 case TGSI_OPCODE_CAL
:
2185 return emit_call( emit
, insn
);
2187 case TGSI_OPCODE_FLR
:
2188 case TGSI_OPCODE_TRUNC
: /* should be TRUNC, not FLR */
2189 return emit_floor( emit
, insn
);
2191 case TGSI_OPCODE_CMP
:
2192 return emit_cmp( emit
, insn
);
2194 case TGSI_OPCODE_DIV
:
2195 return emit_div( emit
, insn
);
2197 case TGSI_OPCODE_DP2
:
2198 return emit_dp2( emit
, insn
);
2200 case TGSI_OPCODE_DPH
:
2201 return emit_dph( emit
, insn
);
2203 case TGSI_OPCODE_NRM
:
2204 return emit_nrm( emit
, insn
);
2206 case TGSI_OPCODE_COS
:
2207 return emit_cos( emit
, insn
);
2209 case TGSI_OPCODE_SIN
:
2210 return emit_sin( emit
, insn
);
2212 case TGSI_OPCODE_SCS
:
2213 return emit_sincos( emit
, insn
);
2215 case TGSI_OPCODE_END
:
2216 /* TGSI always finishes the main func with an END */
2217 return emit_end( emit
);
2219 case TGSI_OPCODE_KIL
:
2220 return emit_kil( emit
, insn
);
2222 /* Selection opcodes. The underlying language is fairly
2223 * non-orthogonal about these.
2225 case TGSI_OPCODE_SEQ
:
2226 return emit_select_op( emit
, PIPE_FUNC_EQUAL
, insn
);
2228 case TGSI_OPCODE_SNE
:
2229 return emit_select_op( emit
, PIPE_FUNC_NOTEQUAL
, insn
);
2231 case TGSI_OPCODE_SGT
:
2232 return emit_select_op( emit
, PIPE_FUNC_GREATER
, insn
);
2234 case TGSI_OPCODE_SGE
:
2235 return emit_select_op( emit
, PIPE_FUNC_GEQUAL
, insn
);
2237 case TGSI_OPCODE_SLT
:
2238 return emit_select_op( emit
, PIPE_FUNC_LESS
, insn
);
2240 case TGSI_OPCODE_SLE
:
2241 return emit_select_op( emit
, PIPE_FUNC_LEQUAL
, insn
);
2243 case TGSI_OPCODE_SUB
:
2244 return emit_sub( emit
, insn
);
2246 case TGSI_OPCODE_POW
:
2247 return emit_pow( emit
, insn
);
2249 case TGSI_OPCODE_EX2
:
2250 return emit_ex2( emit
, insn
);
2252 case TGSI_OPCODE_EXP
:
2253 return emit_exp( emit
, insn
);
2255 case TGSI_OPCODE_LOG
:
2256 return emit_log( emit
, insn
);
2258 case TGSI_OPCODE_LG2
:
2259 return emit_scalar_op1( emit
, SVGA3DOP_LOG
, insn
);
2261 case TGSI_OPCODE_RSQ
:
2262 return emit_scalar_op1( emit
, SVGA3DOP_RSQ
, insn
);
2264 case TGSI_OPCODE_RCP
:
2265 return emit_scalar_op1( emit
, SVGA3DOP_RCP
, insn
);
2267 case TGSI_OPCODE_CONT
:
2268 case TGSI_OPCODE_RET
:
2269 /* This is a noop -- we tell mesa that we can't support RET
2270 * within a function (early return), so this will always be
2271 * followed by an ENDSUB.
2275 /* These aren't actually used by any of the frontends we care
2278 case TGSI_OPCODE_CLAMP
:
2279 case TGSI_OPCODE_ROUND
:
2280 case TGSI_OPCODE_AND
:
2281 case TGSI_OPCODE_OR
:
2282 case TGSI_OPCODE_I2F
:
2283 case TGSI_OPCODE_NOT
:
2284 case TGSI_OPCODE_SHL
:
2285 case TGSI_OPCODE_ISHR
:
2286 case TGSI_OPCODE_XOR
:
2289 case TGSI_OPCODE_IF
:
2290 return emit_if( emit
, insn
);
2291 case TGSI_OPCODE_ELSE
:
2292 return emit_else( emit
, insn
);
2293 case TGSI_OPCODE_ENDIF
:
2294 return emit_endif( emit
, insn
);
2296 case TGSI_OPCODE_BGNLOOP
:
2297 return emit_bgnloop2( emit
, insn
);
2298 case TGSI_OPCODE_ENDLOOP
:
2299 return emit_endloop2( emit
, insn
);
2300 case TGSI_OPCODE_BRK
:
2301 return emit_brk( emit
, insn
);
2303 case TGSI_OPCODE_XPD
:
2304 return emit_xpd( emit
, insn
);
2306 case TGSI_OPCODE_KILP
:
2307 return emit_kilp( emit
, insn
);
2309 case TGSI_OPCODE_DST
:
2310 return emit_dst_insn( emit
, insn
);
2312 case TGSI_OPCODE_LIT
:
2313 return emit_lit( emit
, insn
);
2315 case TGSI_OPCODE_LRP
:
2316 return emit_lrp( emit
, insn
);
2319 unsigned opcode
= translate_opcode(insn
->Instruction
.Opcode
);
2321 if (opcode
== SVGA3DOP_LAST_INST
)
2324 if (!emit_simple_instruction( emit
, opcode
, insn
))
2333 static boolean
svga_emit_immediate( struct svga_shader_emitter
*emit
,
2334 struct tgsi_full_immediate
*imm
)
2336 static const float id
[4] = {0,0,0,1};
2340 assert(1 <= imm
->Immediate
.NrTokens
&& imm
->Immediate
.NrTokens
<= 5);
2341 for (i
= 0; i
< imm
->Immediate
.NrTokens
- 1; i
++)
2342 value
[i
] = imm
->u
[i
].Float
;
2344 for ( ; i
< 4; i
++ )
2347 return emit_def_const( emit
, SVGA3D_CONST_TYPE_FLOAT
,
2348 emit
->imm_start
+ emit
->internal_imm_count
++,
2349 value
[0], value
[1], value
[2], value
[3]);
2352 static boolean
make_immediate( struct svga_shader_emitter
*emit
,
2357 struct src_register
*out
)
2359 unsigned idx
= emit
->nr_hw_const
++;
2361 if (!emit_def_const( emit
, SVGA3D_CONST_TYPE_FLOAT
,
2365 *out
= src_register( SVGA3DREG_CONST
, idx
);
2370 static boolean
emit_vs_preamble( struct svga_shader_emitter
*emit
)
2372 if (!emit
->key
.vkey
.need_prescale
) {
2373 if (!make_immediate( emit
, 0, 0, .5, .5,
2381 static boolean
emit_ps_preamble( struct svga_shader_emitter
*emit
)
2385 /* For SM20, need to initialize the temporaries we're using to hold
2386 * color outputs to some value. Shaders which don't set all of
2387 * these values are likely to be rejected by the DX9 runtime.
2389 if (!emit
->use_sm30
) {
2390 struct src_register zero
= get_zero_immediate( emit
);
2391 for (i
= 0; i
< PIPE_MAX_COLOR_BUFS
; i
++) {
2392 if (SVGA3dShaderGetRegType(emit
->true_col
[i
].value
) != 0) {
2394 if (!submit_op1( emit
,
2395 inst_token(SVGA3DOP_MOV
),
2406 static boolean
emit_ps_postamble( struct svga_shader_emitter
*emit
)
2410 /* PS oDepth is incredibly fragile and it's very hard to catch the
2411 * types of usage that break it during shader emit. Easier just to
2412 * redirect the main program to a temporary and then only touch
2413 * oDepth with a hand-crafted MOV below.
2415 if (SVGA3dShaderGetRegType(emit
->true_pos
.value
) != 0) {
2417 if (!submit_op1( emit
,
2418 inst_token(SVGA3DOP_MOV
),
2420 scalar(src(emit
->temp_pos
), TGSI_SWIZZLE_Z
) ))
2424 /* Similarly for SM20 color outputs... Luckily SM30 isn't so
2427 for (i
= 0; i
< PIPE_MAX_COLOR_BUFS
; i
++) {
2428 if (SVGA3dShaderGetRegType(emit
->true_col
[i
].value
) != 0) {
2430 /* Potentially override output colors with white for XOR
2431 * logicop workaround.
2433 if (emit
->unit
== PIPE_SHADER_FRAGMENT
&&
2434 emit
->key
.fkey
.white_fragments
) {
2436 struct src_register one
= scalar( get_zero_immediate( emit
),
2439 if (!submit_op1( emit
,
2440 inst_token(SVGA3DOP_MOV
),
2446 if (!submit_op1( emit
,
2447 inst_token(SVGA3DOP_MOV
),
2449 src(emit
->temp_col
[i
]) ))
2458 static boolean
emit_vs_postamble( struct svga_shader_emitter
*emit
)
2460 /* PSIZ output is incredibly fragile and it's very hard to catch
2461 * the types of usage that break it during shader emit. Easier
2462 * just to redirect the main program to a temporary and then only
2463 * touch PSIZ with a hand-crafted MOV below.
2465 if (SVGA3dShaderGetRegType(emit
->true_psiz
.value
) != 0) {
2467 if (!submit_op1( emit
,
2468 inst_token(SVGA3DOP_MOV
),
2470 scalar(src(emit
->temp_psiz
), TGSI_SWIZZLE_X
) ))
2474 /* Need to perform various manipulations on vertex position to cope
2475 * with the different GL and D3D clip spaces.
2477 if (emit
->key
.vkey
.need_prescale
) {
2478 SVGA3dShaderDestToken temp_pos
= emit
->temp_pos
;
2479 SVGA3dShaderDestToken pos
= emit
->true_pos
;
2480 unsigned offset
= emit
->info
.file_max
[TGSI_FILE_CONSTANT
] + 1;
2481 struct src_register prescale_scale
= src_register( SVGA3DREG_CONST
,
2483 struct src_register prescale_trans
= src_register( SVGA3DREG_CONST
,
2486 /* MUL temp_pos.xyz, temp_pos, prescale.scale
2487 * MAD result.position, temp_pos.wwww, prescale.trans, temp_pos
2488 * --> Note that prescale.trans.w == 0
2490 if (!submit_op2( emit
,
2491 inst_token(SVGA3DOP_MUL
),
2492 writemask(temp_pos
, TGSI_WRITEMASK_XYZ
),
2497 if (!submit_op3( emit
,
2498 inst_token(SVGA3DOP_MAD
),
2500 swizzle(src(temp_pos
), 3, 3, 3, 3),
2506 SVGA3dShaderDestToken temp_pos
= emit
->temp_pos
;
2507 SVGA3dShaderDestToken pos
= emit
->true_pos
;
2508 struct src_register imm_0055
= emit
->imm_0055
;
2510 /* Adjust GL clipping coordinate space to hardware (D3D-style):
2512 * DP4 temp_pos.z, {0,0,.5,.5}, temp_pos
2513 * MOV result.position, temp_pos
2515 if (!submit_op2( emit
,
2516 inst_token(SVGA3DOP_DP4
),
2517 writemask(temp_pos
, TGSI_WRITEMASK_Z
),
2522 if (!submit_op1( emit
,
2523 inst_token(SVGA3DOP_MOV
),
2534 1: COLOR = FrontColor;
2536 3: COLOR = BackColor;
2539 static boolean
emit_light_twoside( struct svga_shader_emitter
*emit
)
2541 struct src_register vface
, zero
;
2542 struct src_register front
[2];
2543 struct src_register back
[2];
2544 SVGA3dShaderDestToken color
[2];
2545 int count
= emit
->internal_color_count
;
2547 SVGA3dShaderInstToken if_token
;
2552 vface
= get_vface( emit
);
2553 zero
= get_zero_immediate( emit
);
2555 /* Can't use get_temp() to allocate the color reg as such
2556 * temporaries will be reclaimed after each instruction by the call
2557 * to reset_temp_regs().
2559 for (i
= 0; i
< count
; i
++) {
2560 color
[i
] = dst_register( SVGA3DREG_TEMP
,
2561 emit
->nr_hw_temp
++ );
2563 front
[i
] = emit
->input_map
[emit
->internal_color_idx
[i
]];
2565 /* Back is always the next input:
2568 back
[i
].base
.num
= front
[i
].base
.num
+ 1;
2570 /* Reassign the input_map to the actual front-face color:
2572 emit
->input_map
[emit
->internal_color_idx
[i
]] = src(color
[i
]);
2575 if_token
= inst_token( SVGA3DOP_IFC
);
2577 if (emit
->key
.fkey
.front_cw
)
2578 if_token
.control
= SVGA3DOPCOMP_GT
;
2580 if_token
.control
= SVGA3DOPCOMP_LT
;
2582 zero
= scalar(zero
, TGSI_SWIZZLE_X
);
2584 if (!(emit_instruction( emit
, if_token
) &&
2585 emit_src( emit
, vface
) &&
2586 emit_src( emit
, zero
) ))
2589 for (i
= 0; i
< count
; i
++) {
2590 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), color
[i
], front
[i
] ))
2594 if (!(emit_instruction( emit
, inst_token( SVGA3DOP_ELSE
))))
2597 for (i
= 0; i
< count
; i
++) {
2598 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), color
[i
], back
[i
] ))
2602 if (!emit_instruction( emit
, inst_token( SVGA3DOP_ENDIF
) ))
2609 0: SETP_GT TEMP, VFACE, 0
2610 where TEMP is a fake frontface register
2612 static boolean
emit_frontface( struct svga_shader_emitter
*emit
)
2614 struct src_register vface
, zero
;
2615 SVGA3dShaderDestToken temp
;
2616 struct src_register pass
, fail
;
2618 vface
= get_vface( emit
);
2619 zero
= get_zero_immediate( emit
);
2621 /* Can't use get_temp() to allocate the fake frontface reg as such
2622 * temporaries will be reclaimed after each instruction by the call
2623 * to reset_temp_regs().
2625 temp
= dst_register( SVGA3DREG_TEMP
,
2626 emit
->nr_hw_temp
++ );
2628 if (emit
->key
.fkey
.front_cw
) {
2629 pass
= scalar( zero
, TGSI_SWIZZLE_W
);
2630 fail
= scalar( zero
, TGSI_SWIZZLE_X
);
2632 pass
= scalar( zero
, TGSI_SWIZZLE_X
);
2633 fail
= scalar( zero
, TGSI_SWIZZLE_W
);
2636 if (!emit_conditional(emit
, PIPE_FUNC_GREATER
,
2637 temp
, vface
, scalar( zero
, TGSI_SWIZZLE_X
),
2641 /* Reassign the input_map to the actual front-face color:
2643 emit
->input_map
[emit
->internal_frontface_idx
] = src(temp
);
2648 static INLINE boolean
2649 needs_to_create_zero( struct svga_shader_emitter
*emit
)
2653 if (emit
->unit
== PIPE_SHADER_FRAGMENT
) {
2654 if (!emit
->use_sm30
)
2657 if (emit
->key
.fkey
.light_twoside
)
2660 if (emit
->key
.fkey
.white_fragments
)
2663 if (emit
->emit_frontface
)
2666 if (emit
->info
.opcode_count
[TGSI_OPCODE_DST
] >= 1 ||
2667 emit
->info
.opcode_count
[TGSI_OPCODE_LIT
] >= 1)
2671 if (emit
->info
.opcode_count
[TGSI_OPCODE_IF
] >= 1 ||
2672 emit
->info
.opcode_count
[TGSI_OPCODE_BGNLOOP
] >= 1 ||
2673 emit
->info
.opcode_count
[TGSI_OPCODE_BGNFOR
] >= 1 ||
2674 emit
->info
.opcode_count
[TGSI_OPCODE_DDX
] >= 1 ||
2675 emit
->info
.opcode_count
[TGSI_OPCODE_DDY
] >= 1 ||
2676 emit
->info
.opcode_count
[TGSI_OPCODE_SGE
] >= 1 ||
2677 emit
->info
.opcode_count
[TGSI_OPCODE_SGT
] >= 1 ||
2678 emit
->info
.opcode_count
[TGSI_OPCODE_SLE
] >= 1 ||
2679 emit
->info
.opcode_count
[TGSI_OPCODE_SLT
] >= 1 ||
2680 emit
->info
.opcode_count
[TGSI_OPCODE_SNE
] >= 1 ||
2681 emit
->info
.opcode_count
[TGSI_OPCODE_SEQ
] >= 1 ||
2682 emit
->info
.opcode_count
[TGSI_OPCODE_EXP
] >= 1 ||
2683 emit
->info
.opcode_count
[TGSI_OPCODE_LOG
] >= 1 ||
2684 emit
->info
.opcode_count
[TGSI_OPCODE_XPD
] >= 1 ||
2685 emit
->info
.opcode_count
[TGSI_OPCODE_KILP
] >= 1)
2688 for (i
= 0; i
< emit
->key
.fkey
.num_textures
; i
++) {
2689 if (emit
->key
.fkey
.tex
[i
].compare_mode
== PIPE_TEX_COMPARE_R_TO_TEXTURE
)
2696 static INLINE boolean
2697 needs_to_create_loop_const( struct svga_shader_emitter
*emit
)
2699 return (emit
->info
.opcode_count
[TGSI_OPCODE_BGNLOOP
] >= 1);
2702 static INLINE boolean
2703 needs_to_create_sincos_consts( struct svga_shader_emitter
*emit
)
2705 return !emit
->use_sm30
&& (emit
->info
.opcode_count
[TGSI_OPCODE_SIN
] >= 1 ||
2706 emit
->info
.opcode_count
[TGSI_OPCODE_COS
] >= 1 ||
2707 emit
->info
.opcode_count
[TGSI_OPCODE_SCS
] >= 1);
2710 static INLINE boolean
2711 needs_to_create_arl_consts( struct svga_shader_emitter
*emit
)
2713 return (emit
->num_arl_consts
> 0);
2716 static INLINE boolean
2717 pre_parse_add_indirect( struct svga_shader_emitter
*emit
,
2718 int num
, int current_arl
)
2723 for (i
= 0; i
< emit
->num_arl_consts
; ++i
) {
2724 if (emit
->arl_consts
[i
].arl_num
== current_arl
)
2728 if (emit
->num_arl_consts
== i
) {
2729 ++emit
->num_arl_consts
;
2731 emit
->arl_consts
[i
].number
= (emit
->arl_consts
[i
].number
> num
) ?
2733 emit
->arl_consts
[i
].number
;
2734 emit
->arl_consts
[i
].arl_num
= current_arl
;
2739 pre_parse_instruction( struct svga_shader_emitter
*emit
,
2740 const struct tgsi_full_instruction
*insn
,
2743 if (insn
->Src
[0].Register
.Indirect
&&
2744 insn
->Src
[0].Indirect
.File
== TGSI_FILE_ADDRESS
) {
2745 const struct tgsi_full_src_register
*reg
= &insn
->Src
[0];
2746 if (reg
->Register
.Index
< 0) {
2747 pre_parse_add_indirect(emit
, reg
->Register
.Index
, current_arl
);
2751 if (insn
->Src
[1].Register
.Indirect
&&
2752 insn
->Src
[1].Indirect
.File
== TGSI_FILE_ADDRESS
) {
2753 const struct tgsi_full_src_register
*reg
= &insn
->Src
[1];
2754 if (reg
->Register
.Index
< 0) {
2755 pre_parse_add_indirect(emit
, reg
->Register
.Index
, current_arl
);
2759 if (insn
->Src
[2].Register
.Indirect
&&
2760 insn
->Src
[2].Indirect
.File
== TGSI_FILE_ADDRESS
) {
2761 const struct tgsi_full_src_register
*reg
= &insn
->Src
[2];
2762 if (reg
->Register
.Index
< 0) {
2763 pre_parse_add_indirect(emit
, reg
->Register
.Index
, current_arl
);
2771 pre_parse_tokens( struct svga_shader_emitter
*emit
,
2772 const struct tgsi_token
*tokens
)
2774 struct tgsi_parse_context parse
;
2775 int current_arl
= 0;
2777 tgsi_parse_init( &parse
, tokens
);
2779 while (!tgsi_parse_end_of_tokens( &parse
)) {
2780 tgsi_parse_token( &parse
);
2781 switch (parse
.FullToken
.Token
.Type
) {
2782 case TGSI_TOKEN_TYPE_IMMEDIATE
:
2783 case TGSI_TOKEN_TYPE_DECLARATION
:
2785 case TGSI_TOKEN_TYPE_INSTRUCTION
:
2786 if (parse
.FullToken
.FullInstruction
.Instruction
.Opcode
==
2790 if (!pre_parse_instruction( emit
, &parse
.FullToken
.FullInstruction
,
2802 static boolean
svga_shader_emit_helpers( struct svga_shader_emitter
*emit
)
2805 if (needs_to_create_zero( emit
)) {
2806 create_zero_immediate( emit
);
2808 if (needs_to_create_loop_const( emit
)) {
2809 create_loop_const( emit
);
2811 if (needs_to_create_sincos_consts( emit
)) {
2812 create_sincos_consts( emit
);
2814 if (needs_to_create_arl_consts( emit
)) {
2815 create_arl_consts( emit
);
2818 if (emit
->unit
== PIPE_SHADER_FRAGMENT
) {
2819 if (!emit_ps_preamble( emit
))
2822 if (emit
->key
.fkey
.light_twoside
) {
2823 if (!emit_light_twoside( emit
))
2826 if (emit
->emit_frontface
) {
2827 if (!emit_frontface( emit
))
2835 boolean
svga_shader_emit_instructions( struct svga_shader_emitter
*emit
,
2836 const struct tgsi_token
*tokens
)
2838 struct tgsi_parse_context parse
;
2840 boolean helpers_emitted
= FALSE
;
2841 unsigned line_nr
= 0;
2843 tgsi_parse_init( &parse
, tokens
);
2844 emit
->internal_imm_count
= 0;
2846 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
2847 ret
= emit_vs_preamble( emit
);
2852 pre_parse_tokens(emit
, tokens
);
2854 while (!tgsi_parse_end_of_tokens( &parse
)) {
2855 tgsi_parse_token( &parse
);
2857 switch (parse
.FullToken
.Token
.Type
) {
2858 case TGSI_TOKEN_TYPE_IMMEDIATE
:
2859 ret
= svga_emit_immediate( emit
, &parse
.FullToken
.FullImmediate
);
2864 case TGSI_TOKEN_TYPE_DECLARATION
:
2866 ret
= svga_translate_decl_sm30( emit
, &parse
.FullToken
.FullDeclaration
);
2868 ret
= svga_translate_decl_sm20( emit
, &parse
.FullToken
.FullDeclaration
);
2873 case TGSI_TOKEN_TYPE_INSTRUCTION
:
2874 if (!helpers_emitted
) {
2875 if (!svga_shader_emit_helpers( emit
))
2877 helpers_emitted
= TRUE
;
2879 ret
= svga_emit_instruction( emit
,
2881 &parse
.FullToken
.FullInstruction
);
2889 reset_temp_regs( emit
);
2892 /* Need to terminate the current subroutine. Note that the
2893 * hardware doesn't tolerate shaders without sub-routines
2894 * terminating with RET+END.
2896 if (!emit
->in_main_func
) {
2897 ret
= emit_instruction( emit
, inst_token( SVGA3DOP_RET
) );
2902 assert(emit
->dynamic_branching_level
== 0);
2904 /* Need to terminate the whole shader:
2906 ret
= emit_instruction( emit
, inst_token( SVGA3DOP_END
) );
2912 tgsi_parse_free( &parse
);