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svga: Silence uninitialized variable warning.
[mesa.git] / src / gallium / drivers / svga / svga_tgsi_insn.c
1 /**********************************************************
2 * Copyright 2008-2009 VMware, Inc. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 **********************************************************/
25
26
27 #include "pipe/p_shader_tokens.h"
28 #include "tgsi/tgsi_parse.h"
29 #include "util/u_memory.h"
30
31 #include "svga_tgsi_emit.h"
32 #include "svga_context.h"
33
34
35 static boolean emit_vs_postamble( struct svga_shader_emitter *emit );
36 static boolean emit_ps_postamble( struct svga_shader_emitter *emit );
37
38
39
40
41 static unsigned
42 translate_opcode(
43 uint opcode )
44 {
45 switch (opcode) {
46 case TGSI_OPCODE_ABS: return SVGA3DOP_ABS;
47 case TGSI_OPCODE_ADD: return SVGA3DOP_ADD;
48 case TGSI_OPCODE_BREAKC: return SVGA3DOP_BREAKC;
49 case TGSI_OPCODE_DP2A: return SVGA3DOP_DP2ADD;
50 case TGSI_OPCODE_DP3: return SVGA3DOP_DP3;
51 case TGSI_OPCODE_DP4: return SVGA3DOP_DP4;
52 case TGSI_OPCODE_ENDFOR: return SVGA3DOP_ENDLOOP;
53 case TGSI_OPCODE_FRC: return SVGA3DOP_FRC;
54 case TGSI_OPCODE_BGNFOR: return SVGA3DOP_LOOP;
55 case TGSI_OPCODE_MAD: return SVGA3DOP_MAD;
56 case TGSI_OPCODE_MAX: return SVGA3DOP_MAX;
57 case TGSI_OPCODE_MIN: return SVGA3DOP_MIN;
58 case TGSI_OPCODE_MOV: return SVGA3DOP_MOV;
59 case TGSI_OPCODE_MUL: return SVGA3DOP_MUL;
60 case TGSI_OPCODE_NOP: return SVGA3DOP_NOP;
61 case TGSI_OPCODE_NRM4: return SVGA3DOP_NRM;
62 case TGSI_OPCODE_SSG: return SVGA3DOP_SGN;
63 default:
64 debug_printf("Unkown opcode %u\n", opcode);
65 assert( 0 );
66 return SVGA3DOP_LAST_INST;
67 }
68 }
69
70
71 static unsigned translate_file( unsigned file )
72 {
73 switch (file) {
74 case TGSI_FILE_TEMPORARY: return SVGA3DREG_TEMP;
75 case TGSI_FILE_INPUT: return SVGA3DREG_INPUT;
76 case TGSI_FILE_OUTPUT: return SVGA3DREG_OUTPUT; /* VS3.0+ only */
77 case TGSI_FILE_IMMEDIATE: return SVGA3DREG_CONST;
78 case TGSI_FILE_CONSTANT: return SVGA3DREG_CONST;
79 case TGSI_FILE_SAMPLER: return SVGA3DREG_SAMPLER;
80 case TGSI_FILE_ADDRESS: return SVGA3DREG_ADDR;
81 default:
82 assert( 0 );
83 return SVGA3DREG_TEMP;
84 }
85 }
86
87
88
89
90
91
92 static SVGA3dShaderDestToken
93 translate_dst_register( struct svga_shader_emitter *emit,
94 const struct tgsi_full_instruction *insn,
95 unsigned idx )
96 {
97 const struct tgsi_full_dst_register *reg = &insn->Dst[idx];
98 SVGA3dShaderDestToken dest;
99
100 switch (reg->Register.File) {
101 case TGSI_FILE_OUTPUT:
102 /* Output registers encode semantic information in their name.
103 * Need to lookup a table built at decl time:
104 */
105 dest = emit->output_map[reg->Register.Index];
106 break;
107
108 default:
109 dest = dst_register( translate_file( reg->Register.File ),
110 reg->Register.Index );
111 break;
112 }
113
114 dest.mask = reg->Register.WriteMask;
115
116 if (insn->Instruction.Saturate)
117 dest.dstMod = SVGA3DDSTMOD_SATURATE;
118
119 return dest;
120 }
121
122
123 static struct src_register
124 swizzle( struct src_register src,
125 int x,
126 int y,
127 int z,
128 int w )
129 {
130 x = (src.base.swizzle >> (x * 2)) & 0x3;
131 y = (src.base.swizzle >> (y * 2)) & 0x3;
132 z = (src.base.swizzle >> (z * 2)) & 0x3;
133 w = (src.base.swizzle >> (w * 2)) & 0x3;
134
135 src.base.swizzle = TRANSLATE_SWIZZLE(x,y,z,w);
136
137 return src;
138 }
139
140 static struct src_register
141 scalar( struct src_register src,
142 int comp )
143 {
144 return swizzle( src, comp, comp, comp, comp );
145 }
146
147 static INLINE boolean
148 svga_arl_needs_adjustment( const struct svga_shader_emitter *emit )
149 {
150 int i;
151
152 for (i = 0; i < emit->num_arl_consts; ++i) {
153 if (emit->arl_consts[i].arl_num == emit->current_arl)
154 return TRUE;
155 }
156 return FALSE;
157 }
158
159 static INLINE int
160 svga_arl_adjustment( const struct svga_shader_emitter *emit )
161 {
162 int i;
163
164 for (i = 0; i < emit->num_arl_consts; ++i) {
165 if (emit->arl_consts[i].arl_num == emit->current_arl)
166 return emit->arl_consts[i].number;
167 }
168 return 0;
169 }
170
171 static struct src_register
172 translate_src_register( const struct svga_shader_emitter *emit,
173 const struct tgsi_full_src_register *reg )
174 {
175 struct src_register src;
176
177 switch (reg->Register.File) {
178 case TGSI_FILE_INPUT:
179 /* Input registers are referred to by their semantic name rather
180 * than by index. Use the mapping build up from the decls:
181 */
182 src = emit->input_map[reg->Register.Index];
183 break;
184
185 case TGSI_FILE_IMMEDIATE:
186 /* Immediates are appended after TGSI constants in the D3D
187 * constant buffer.
188 */
189 src = src_register( translate_file( reg->Register.File ),
190 reg->Register.Index +
191 emit->imm_start );
192 break;
193
194 default:
195 src = src_register( translate_file( reg->Register.File ),
196 reg->Register.Index );
197
198 break;
199 }
200
201 /* Indirect addressing (for coninstant buffer lookups only)
202 */
203 if (reg->Register.Indirect)
204 {
205 /* we shift the offset towards the minimum */
206 if (svga_arl_needs_adjustment( emit )) {
207 src.base.num -= svga_arl_adjustment( emit );
208 }
209 src.base.relAddr = 1;
210
211 /* Not really sure what should go in the second token:
212 */
213 src.indirect = src_token( SVGA3DREG_ADDR,
214 reg->Indirect.Index );
215
216 src.indirect.swizzle = SWIZZLE_XXXX;
217 }
218
219 src = swizzle( src,
220 reg->Register.SwizzleX,
221 reg->Register.SwizzleY,
222 reg->Register.SwizzleZ,
223 reg->Register.SwizzleW );
224
225 /* src.mod isn't a bitfield, unfortunately:
226 * See tgsi_util_get_full_src_register_sign_mode for implementation details.
227 */
228 if (reg->Register.Absolute) {
229 if (reg->Register.Negate)
230 src.base.srcMod = SVGA3DSRCMOD_ABSNEG;
231 else
232 src.base.srcMod = SVGA3DSRCMOD_ABS;
233 }
234 else {
235 if (reg->Register.Negate)
236 src.base.srcMod = SVGA3DSRCMOD_NEG;
237 else
238 src.base.srcMod = SVGA3DSRCMOD_NONE;
239 }
240
241 return src;
242 }
243
244
245 /*
246 * Get a temporary register, return -1 if none available
247 */
248 static INLINE SVGA3dShaderDestToken
249 get_temp( struct svga_shader_emitter *emit )
250 {
251 int i = emit->nr_hw_temp + emit->internal_temp_count++;
252
253 return dst_register( SVGA3DREG_TEMP, i );
254 }
255
256 /* Release a single temp. Currently only effective if it was the last
257 * allocated temp, otherwise release will be delayed until the next
258 * call to reset_temp_regs().
259 */
260 static INLINE void
261 release_temp( struct svga_shader_emitter *emit,
262 SVGA3dShaderDestToken temp )
263 {
264 if (temp.num == emit->internal_temp_count - 1)
265 emit->internal_temp_count--;
266 }
267
268 static void reset_temp_regs( struct svga_shader_emitter *emit )
269 {
270 emit->internal_temp_count = 0;
271 }
272
273
274 static boolean submit_op0( struct svga_shader_emitter *emit,
275 SVGA3dShaderInstToken inst,
276 SVGA3dShaderDestToken dest )
277 {
278 return (emit_instruction( emit, inst ) &&
279 emit_dst( emit, dest ));
280 }
281
282 static boolean submit_op1( struct svga_shader_emitter *emit,
283 SVGA3dShaderInstToken inst,
284 SVGA3dShaderDestToken dest,
285 struct src_register src0 )
286 {
287 return emit_op1( emit, inst, dest, src0 );
288 }
289
290
291 /* SVGA shaders may not refer to >1 constant register in a single
292 * instruction. This function checks for that usage and inserts a
293 * move to temporary if detected.
294 *
295 * The same applies to input registers -- at most a single input
296 * register may be read by any instruction.
297 */
298 static boolean submit_op2( struct svga_shader_emitter *emit,
299 SVGA3dShaderInstToken inst,
300 SVGA3dShaderDestToken dest,
301 struct src_register src0,
302 struct src_register src1 )
303 {
304 SVGA3dShaderDestToken temp;
305 SVGA3dShaderRegType type0, type1;
306 boolean need_temp = FALSE;
307
308 temp.value = 0;
309 type0 = SVGA3dShaderGetRegType( src0.base.value );
310 type1 = SVGA3dShaderGetRegType( src1.base.value );
311
312 if (type0 == SVGA3DREG_CONST &&
313 type1 == SVGA3DREG_CONST &&
314 src0.base.num != src1.base.num)
315 need_temp = TRUE;
316
317 if (type0 == SVGA3DREG_INPUT &&
318 type1 == SVGA3DREG_INPUT &&
319 src0.base.num != src1.base.num)
320 need_temp = TRUE;
321
322 if (need_temp)
323 {
324 temp = get_temp( emit );
325
326 if (!emit_op1( emit, inst_token( SVGA3DOP_MOV ), temp, src0 ))
327 return FALSE;
328
329 src0 = src( temp );
330 }
331
332 if (!emit_op2( emit, inst, dest, src0, src1 ))
333 return FALSE;
334
335 if (need_temp)
336 release_temp( emit, temp );
337
338 return TRUE;
339 }
340
341
342 /* SVGA shaders may not refer to >1 constant register in a single
343 * instruction. This function checks for that usage and inserts a
344 * move to temporary if detected.
345 */
346 static boolean submit_op3( struct svga_shader_emitter *emit,
347 SVGA3dShaderInstToken inst,
348 SVGA3dShaderDestToken dest,
349 struct src_register src0,
350 struct src_register src1,
351 struct src_register src2 )
352 {
353 SVGA3dShaderDestToken temp0;
354 SVGA3dShaderDestToken temp1;
355 boolean need_temp0 = FALSE;
356 boolean need_temp1 = FALSE;
357 SVGA3dShaderRegType type0, type1, type2;
358
359 temp0.value = 0;
360 temp1.value = 0;
361 type0 = SVGA3dShaderGetRegType( src0.base.value );
362 type1 = SVGA3dShaderGetRegType( src1.base.value );
363 type2 = SVGA3dShaderGetRegType( src2.base.value );
364
365 if (inst.op != SVGA3DOP_SINCOS) {
366 if (type0 == SVGA3DREG_CONST &&
367 ((type1 == SVGA3DREG_CONST && src0.base.num != src1.base.num) ||
368 (type2 == SVGA3DREG_CONST && src0.base.num != src2.base.num)))
369 need_temp0 = TRUE;
370
371 if (type1 == SVGA3DREG_CONST &&
372 (type2 == SVGA3DREG_CONST && src1.base.num != src2.base.num))
373 need_temp1 = TRUE;
374 }
375
376 if (type0 == SVGA3DREG_INPUT &&
377 ((type1 == SVGA3DREG_INPUT && src0.base.num != src1.base.num) ||
378 (type2 == SVGA3DREG_INPUT && src0.base.num != src2.base.num)))
379 need_temp0 = TRUE;
380
381 if (type1 == SVGA3DREG_INPUT &&
382 (type2 == SVGA3DREG_INPUT && src1.base.num != src2.base.num))
383 need_temp1 = TRUE;
384
385 if (need_temp0)
386 {
387 temp0 = get_temp( emit );
388
389 if (!emit_op1( emit, inst_token( SVGA3DOP_MOV ), temp0, src0 ))
390 return FALSE;
391
392 src0 = src( temp0 );
393 }
394
395 if (need_temp1)
396 {
397 temp1 = get_temp( emit );
398
399 if (!emit_op1( emit, inst_token( SVGA3DOP_MOV ), temp1, src1 ))
400 return FALSE;
401
402 src1 = src( temp1 );
403 }
404
405 if (!emit_op3( emit, inst, dest, src0, src1, src2 ))
406 return FALSE;
407
408 if (need_temp1)
409 release_temp( emit, temp1 );
410 if (need_temp0)
411 release_temp( emit, temp0 );
412 return TRUE;
413 }
414
415
416
417
418 /* SVGA shaders may not refer to >1 constant register in a single
419 * instruction. This function checks for that usage and inserts a
420 * move to temporary if detected.
421 */
422 static boolean submit_op4( struct svga_shader_emitter *emit,
423 SVGA3dShaderInstToken inst,
424 SVGA3dShaderDestToken dest,
425 struct src_register src0,
426 struct src_register src1,
427 struct src_register src2,
428 struct src_register src3)
429 {
430 SVGA3dShaderDestToken temp0;
431 SVGA3dShaderDestToken temp3;
432 boolean need_temp0 = FALSE;
433 boolean need_temp3 = FALSE;
434 SVGA3dShaderRegType type0, type1, type2, type3;
435
436 temp0.value = 0;
437 temp3.value = 0;
438 type0 = SVGA3dShaderGetRegType( src0.base.value );
439 type1 = SVGA3dShaderGetRegType( src1.base.value );
440 type2 = SVGA3dShaderGetRegType( src2.base.value );
441 type3 = SVGA3dShaderGetRegType( src2.base.value );
442
443 /* Make life a little easier - this is only used by the TXD
444 * instruction which is guaranteed not to have a constant/input reg
445 * in one slot at least:
446 */
447 assert(type1 == SVGA3DREG_SAMPLER);
448
449 if (type0 == SVGA3DREG_CONST &&
450 ((type3 == SVGA3DREG_CONST && src0.base.num != src3.base.num) ||
451 (type2 == SVGA3DREG_CONST && src0.base.num != src2.base.num)))
452 need_temp0 = TRUE;
453
454 if (type3 == SVGA3DREG_CONST &&
455 (type2 == SVGA3DREG_CONST && src3.base.num != src2.base.num))
456 need_temp3 = TRUE;
457
458 if (type0 == SVGA3DREG_INPUT &&
459 ((type3 == SVGA3DREG_INPUT && src0.base.num != src3.base.num) ||
460 (type2 == SVGA3DREG_INPUT && src0.base.num != src2.base.num)))
461 need_temp0 = TRUE;
462
463 if (type3 == SVGA3DREG_INPUT &&
464 (type2 == SVGA3DREG_INPUT && src3.base.num != src2.base.num))
465 need_temp3 = TRUE;
466
467 if (need_temp0)
468 {
469 temp0 = get_temp( emit );
470
471 if (!emit_op1( emit, inst_token( SVGA3DOP_MOV ), temp0, src0 ))
472 return FALSE;
473
474 src0 = src( temp0 );
475 }
476
477 if (need_temp3)
478 {
479 temp3 = get_temp( emit );
480
481 if (!emit_op1( emit, inst_token( SVGA3DOP_MOV ), temp3, src3 ))
482 return FALSE;
483
484 src3 = src( temp3 );
485 }
486
487 if (!emit_op4( emit, inst, dest, src0, src1, src2, src3 ))
488 return FALSE;
489
490 if (need_temp3)
491 release_temp( emit, temp3 );
492 if (need_temp0)
493 release_temp( emit, temp0 );
494 return TRUE;
495 }
496
497
498 static boolean emit_def_const( struct svga_shader_emitter *emit,
499 SVGA3dShaderConstType type,
500 unsigned idx,
501 float a,
502 float b,
503 float c,
504 float d )
505 {
506 SVGA3DOpDefArgs def;
507 SVGA3dShaderInstToken opcode;
508
509 switch (type) {
510 case SVGA3D_CONST_TYPE_FLOAT:
511 opcode = inst_token( SVGA3DOP_DEF );
512 def.dst = dst_register( SVGA3DREG_CONST, idx );
513 def.constValues[0] = a;
514 def.constValues[1] = b;
515 def.constValues[2] = c;
516 def.constValues[3] = d;
517 break;
518 case SVGA3D_CONST_TYPE_INT:
519 opcode = inst_token( SVGA3DOP_DEFI );
520 def.dst = dst_register( SVGA3DREG_CONSTINT, idx );
521 def.constIValues[0] = (int)a;
522 def.constIValues[1] = (int)b;
523 def.constIValues[2] = (int)c;
524 def.constIValues[3] = (int)d;
525 break;
526 default:
527 assert(0);
528 break;
529 }
530
531 if (!emit_instruction(emit, opcode) ||
532 !svga_shader_emit_dwords( emit, def.values, Elements(def.values)))
533 return FALSE;
534
535 return TRUE;
536 }
537
538 static INLINE boolean
539 create_zero_immediate( struct svga_shader_emitter *emit )
540 {
541 unsigned idx = emit->nr_hw_const++;
542
543 if (!emit_def_const( emit, SVGA3D_CONST_TYPE_FLOAT,
544 idx, 0, 0, 0, 1 ))
545 return FALSE;
546
547 emit->zero_immediate_idx = idx;
548 emit->created_zero_immediate = TRUE;
549
550 return TRUE;
551 }
552
553 static INLINE boolean
554 create_loop_const( struct svga_shader_emitter *emit )
555 {
556 unsigned idx = emit->nr_hw_const++;
557
558 if (!emit_def_const( emit, SVGA3D_CONST_TYPE_INT, idx,
559 255, /* iteration count */
560 0, /* initial value */
561 1, /* step size */
562 0 /* not used, must be 0 */))
563 return FALSE;
564
565 emit->loop_const_idx = idx;
566 emit->created_loop_const = TRUE;
567
568 return TRUE;
569 }
570
571 static INLINE boolean
572 create_sincos_consts( struct svga_shader_emitter *emit )
573 {
574 unsigned idx = emit->nr_hw_const++;
575
576 if (!emit_def_const( emit, SVGA3D_CONST_TYPE_FLOAT, idx,
577 -1.5500992e-006f,
578 -2.1701389e-005f,
579 0.0026041667f,
580 0.00026041668f ))
581 return FALSE;
582
583 emit->sincos_consts_idx = idx;
584 idx = emit->nr_hw_const++;
585
586 if (!emit_def_const( emit, SVGA3D_CONST_TYPE_FLOAT, idx,
587 -0.020833334f,
588 -0.12500000f,
589 1.0f,
590 0.50000000f ))
591 return FALSE;
592
593 emit->created_sincos_consts = TRUE;
594
595 return TRUE;
596 }
597
598 static INLINE boolean
599 create_arl_consts( struct svga_shader_emitter *emit )
600 {
601 int i;
602
603 for (i = 0; i < emit->num_arl_consts; i += 4) {
604 int j;
605 unsigned idx = emit->nr_hw_const++;
606 float vals[4];
607 for (j = 0; j < 4 && (j + i) < emit->num_arl_consts; ++j) {
608 vals[j] = emit->arl_consts[i + j].number;
609 emit->arl_consts[i + j].idx = idx;
610 switch (j) {
611 case 0:
612 emit->arl_consts[i + 0].swizzle = TGSI_SWIZZLE_X;
613 break;
614 case 1:
615 emit->arl_consts[i + 0].swizzle = TGSI_SWIZZLE_Y;
616 break;
617 case 2:
618 emit->arl_consts[i + 0].swizzle = TGSI_SWIZZLE_Z;
619 break;
620 case 3:
621 emit->arl_consts[i + 0].swizzle = TGSI_SWIZZLE_W;
622 break;
623 }
624 }
625 while (j < 4)
626 vals[j++] = 0;
627
628 if (!emit_def_const( emit, SVGA3D_CONST_TYPE_FLOAT, idx,
629 vals[0], vals[1],
630 vals[2], vals[3]))
631 return FALSE;
632 }
633
634 return TRUE;
635 }
636
637 static INLINE struct src_register
638 get_vface( struct svga_shader_emitter *emit )
639 {
640 assert(emit->emitted_vface);
641 return src_register(SVGA3DREG_MISCTYPE,
642 SVGA3DMISCREG_FACE);
643 }
644
645 /* returns {0, 0, 0, 1} immediate */
646 static INLINE struct src_register
647 get_zero_immediate( struct svga_shader_emitter *emit )
648 {
649 assert(emit->created_zero_immediate);
650 assert(emit->zero_immediate_idx >= 0);
651 return src_register( SVGA3DREG_CONST,
652 emit->zero_immediate_idx );
653 }
654
655 /* returns the loop const */
656 static INLINE struct src_register
657 get_loop_const( struct svga_shader_emitter *emit )
658 {
659 assert(emit->created_loop_const);
660 assert(emit->loop_const_idx >= 0);
661 return src_register( SVGA3DREG_CONSTINT,
662 emit->loop_const_idx );
663 }
664
665 /* returns a sincos const */
666 static INLINE struct src_register
667 get_sincos_const( struct svga_shader_emitter *emit,
668 unsigned index )
669 {
670 assert(emit->created_sincos_consts);
671 assert(emit->sincos_consts_idx >= 0);
672 assert(index == 0 || index == 1);
673 return src_register( SVGA3DREG_CONST,
674 emit->sincos_consts_idx + index );
675 }
676
677 static INLINE struct src_register
678 get_fake_arl_const( struct svga_shader_emitter *emit )
679 {
680 struct src_register reg;
681 int idx = 0, swizzle = 0, i;
682
683 for (i = 0; i < emit->num_arl_consts; ++ i) {
684 if (emit->arl_consts[i].arl_num == emit->current_arl) {
685 idx = emit->arl_consts[i].idx;
686 swizzle = emit->arl_consts[i].swizzle;
687 }
688 }
689
690 reg = src_register( SVGA3DREG_CONST, idx );
691 return scalar(reg, swizzle);
692 }
693
694 static INLINE struct src_register
695 get_tex_dimensions( struct svga_shader_emitter *emit, int sampler_num )
696 {
697 int idx;
698 struct src_register reg;
699
700 /* the width/height indexes start right after constants */
701 idx = emit->key.fkey.tex[sampler_num].width_height_idx +
702 emit->info.file_max[TGSI_FILE_CONSTANT] + 1;
703
704 reg = src_register( SVGA3DREG_CONST, idx );
705 return reg;
706 }
707
708 static boolean emit_fake_arl(struct svga_shader_emitter *emit,
709 const struct tgsi_full_instruction *insn)
710 {
711 const struct src_register src0 = translate_src_register(
712 emit, &insn->Src[0] );
713 struct src_register src1 = get_fake_arl_const( emit );
714 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
715 SVGA3dShaderDestToken tmp = get_temp( emit );
716
717 if (!submit_op1(emit, inst_token( SVGA3DOP_MOV ), tmp, src0))
718 return FALSE;
719
720 if (!submit_op2( emit, inst_token( SVGA3DOP_ADD ), tmp, src( tmp ),
721 src1))
722 return FALSE;
723
724 /* replicate the original swizzle */
725 src1 = src(tmp);
726 src1.base.swizzle = src0.base.swizzle;
727
728 return submit_op1( emit, inst_token( SVGA3DOP_MOVA ),
729 dst, src1 );
730 }
731
732 static boolean emit_if(struct svga_shader_emitter *emit,
733 const struct tgsi_full_instruction *insn)
734 {
735 const struct src_register src = translate_src_register(
736 emit, &insn->Src[0] );
737 struct src_register zero = get_zero_immediate( emit );
738 SVGA3dShaderInstToken if_token = inst_token( SVGA3DOP_IFC );
739
740 if_token.control = SVGA3DOPCOMPC_NE;
741 zero = scalar(zero, TGSI_SWIZZLE_X);
742
743 emit->dynamic_branching_level++;
744
745 return (emit_instruction( emit, if_token ) &&
746 emit_src( emit, src ) &&
747 emit_src( emit, zero ) );
748 }
749
750 static boolean emit_endif(struct svga_shader_emitter *emit,
751 const struct tgsi_full_instruction *insn)
752 {
753 emit->dynamic_branching_level--;
754
755 return (emit_instruction( emit,
756 inst_token( SVGA3DOP_ENDIF )));
757 }
758
759 static boolean emit_else(struct svga_shader_emitter *emit,
760 const struct tgsi_full_instruction *insn)
761 {
762 return (emit_instruction( emit,
763 inst_token( SVGA3DOP_ELSE )));
764 }
765
766 /* Translate the following TGSI FLR instruction.
767 * FLR DST, SRC
768 * To the following SVGA3D instruction sequence.
769 * FRC TMP, SRC
770 * SUB DST, SRC, TMP
771 */
772 static boolean emit_floor(struct svga_shader_emitter *emit,
773 const struct tgsi_full_instruction *insn )
774 {
775 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
776 const struct src_register src0 = translate_src_register(
777 emit, &insn->Src[0] );
778 SVGA3dShaderDestToken temp = get_temp( emit );
779
780 /* FRC TMP, SRC */
781 if (!submit_op1( emit, inst_token( SVGA3DOP_FRC ), temp, src0 ))
782 return FALSE;
783
784 /* SUB DST, SRC, TMP */
785 if (!submit_op2( emit, inst_token( SVGA3DOP_ADD ), dst, src0,
786 negate( src( temp ) ) ))
787 return FALSE;
788
789 return TRUE;
790 }
791
792
793 /* Translate the following TGSI CMP instruction.
794 * CMP DST, SRC0, SRC1, SRC2
795 * To the following SVGA3D instruction sequence.
796 * CMP DST, SRC0, SRC2, SRC1
797 */
798 static boolean emit_cmp(struct svga_shader_emitter *emit,
799 const struct tgsi_full_instruction *insn )
800 {
801 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
802 const struct src_register src0 = translate_src_register(
803 emit, &insn->Src[0] );
804 const struct src_register src1 = translate_src_register(
805 emit, &insn->Src[1] );
806 const struct src_register src2 = translate_src_register(
807 emit, &insn->Src[2] );
808
809 /* CMP DST, SRC0, SRC2, SRC1 */
810 return submit_op3( emit, inst_token( SVGA3DOP_CMP ), dst, src0, src2, src1);
811 }
812
813
814
815 /* Translate the following TGSI DIV instruction.
816 * DIV DST.xy, SRC0, SRC1
817 * To the following SVGA3D instruction sequence.
818 * RCP TMP.x, SRC1.xxxx
819 * RCP TMP.y, SRC1.yyyy
820 * MUL DST.xy, SRC0, TMP
821 */
822 static boolean emit_div(struct svga_shader_emitter *emit,
823 const struct tgsi_full_instruction *insn )
824 {
825 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
826 const struct src_register src0 = translate_src_register(
827 emit, &insn->Src[0] );
828 const struct src_register src1 = translate_src_register(
829 emit, &insn->Src[1] );
830 SVGA3dShaderDestToken temp = get_temp( emit );
831 int i;
832
833 /* For each enabled element, perform a RCP instruction. Note that
834 * RCP is scalar in SVGA3D:
835 */
836 for (i = 0; i < 4; i++) {
837 unsigned channel = 1 << i;
838 if (dst.mask & channel) {
839 /* RCP TMP.?, SRC1.???? */
840 if (!submit_op1( emit, inst_token( SVGA3DOP_RCP ),
841 writemask(temp, channel),
842 scalar(src1, i) ))
843 return FALSE;
844 }
845 }
846
847 /* Then multiply them out with a single mul:
848 *
849 * MUL DST, SRC0, TMP
850 */
851 if (!submit_op2( emit, inst_token( SVGA3DOP_MUL ), dst, src0,
852 src( temp ) ))
853 return FALSE;
854
855 return TRUE;
856 }
857
858 /* Translate the following TGSI DP2 instruction.
859 * DP2 DST, SRC1, SRC2
860 * To the following SVGA3D instruction sequence.
861 * MUL TMP, SRC1, SRC2
862 * ADD DST, TMP.xxxx, TMP.yyyy
863 */
864 static boolean emit_dp2(struct svga_shader_emitter *emit,
865 const struct tgsi_full_instruction *insn )
866 {
867 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
868 const struct src_register src0 = translate_src_register(
869 emit, &insn->Src[0] );
870 const struct src_register src1 = translate_src_register(
871 emit, &insn->Src[1] );
872 SVGA3dShaderDestToken temp = get_temp( emit );
873 struct src_register temp_src0, temp_src1;
874
875 /* MUL TMP, SRC1, SRC2 */
876 if (!submit_op2( emit, inst_token( SVGA3DOP_MUL ), temp, src0, src1 ))
877 return FALSE;
878
879 temp_src0 = scalar(src( temp ), TGSI_SWIZZLE_X);
880 temp_src1 = scalar(src( temp ), TGSI_SWIZZLE_Y);
881
882 /* ADD DST, TMP.xxxx, TMP.yyyy */
883 if (!submit_op2( emit, inst_token( SVGA3DOP_ADD ), dst,
884 temp_src0, temp_src1 ))
885 return FALSE;
886
887 return TRUE;
888 }
889
890
891 /* Translate the following TGSI DPH instruction.
892 * DPH DST, SRC1, SRC2
893 * To the following SVGA3D instruction sequence.
894 * DP3 TMP, SRC1, SRC2
895 * ADD DST, TMP, SRC2.wwww
896 */
897 static boolean emit_dph(struct svga_shader_emitter *emit,
898 const struct tgsi_full_instruction *insn )
899 {
900 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
901 const struct src_register src0 = translate_src_register(
902 emit, &insn->Src[0] );
903 struct src_register src1 = translate_src_register(
904 emit, &insn->Src[1] );
905 SVGA3dShaderDestToken temp = get_temp( emit );
906
907 /* DP3 TMP, SRC1, SRC2 */
908 if (!submit_op2( emit, inst_token( SVGA3DOP_DP3 ), temp, src0, src1 ))
909 return FALSE;
910
911 src1 = scalar(src1, TGSI_SWIZZLE_W);
912
913 /* ADD DST, TMP, SRC2.wwww */
914 if (!submit_op2( emit, inst_token( SVGA3DOP_ADD ), dst,
915 src( temp ), src1 ))
916 return FALSE;
917
918 return TRUE;
919 }
920
921 /* Translate the following TGSI DST instruction.
922 * NRM DST, SRC
923 * To the following SVGA3D instruction sequence.
924 * DP3 TMP, SRC, SRC
925 * RSQ TMP, TMP
926 * MUL DST, SRC, TMP
927 */
928 static boolean emit_nrm(struct svga_shader_emitter *emit,
929 const struct tgsi_full_instruction *insn )
930 {
931 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
932 const struct src_register src0 = translate_src_register(
933 emit, &insn->Src[0] );
934 SVGA3dShaderDestToken temp = get_temp( emit );
935
936 /* DP3 TMP, SRC, SRC */
937 if (!submit_op2( emit, inst_token( SVGA3DOP_DP3 ), temp, src0, src0 ))
938 return FALSE;
939
940 /* RSQ TMP, TMP */
941 if (!submit_op1( emit, inst_token( SVGA3DOP_RSQ ), temp, src( temp )))
942 return FALSE;
943
944 /* MUL DST, SRC, TMP */
945 if (!submit_op2( emit, inst_token( SVGA3DOP_MUL ), dst,
946 src0, src( temp )))
947 return FALSE;
948
949 return TRUE;
950
951 }
952
953 static boolean do_emit_sincos(struct svga_shader_emitter *emit,
954 SVGA3dShaderDestToken dst,
955 struct src_register src0)
956 {
957 src0 = scalar(src0, TGSI_SWIZZLE_X);
958
959 if (emit->use_sm30) {
960 return submit_op1( emit, inst_token( SVGA3DOP_SINCOS ),
961 dst, src0 );
962 } else {
963 struct src_register const1 = get_sincos_const( emit, 0 );
964 struct src_register const2 = get_sincos_const( emit, 1 );
965
966 return submit_op3( emit, inst_token( SVGA3DOP_SINCOS ),
967 dst, src0, const1, const2 );
968 }
969 }
970
971 static boolean emit_sincos(struct svga_shader_emitter *emit,
972 const struct tgsi_full_instruction *insn)
973 {
974 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
975 struct src_register src0 = translate_src_register(
976 emit, &insn->Src[0] );
977 SVGA3dShaderDestToken temp = get_temp( emit );
978
979 /* SCS TMP SRC */
980 if (!do_emit_sincos(emit, writemask(temp, TGSI_WRITEMASK_XY), src0 ))
981 return FALSE;
982
983 /* MOV DST TMP */
984 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ), dst, src( temp ) ))
985 return FALSE;
986
987 return TRUE;
988 }
989
990 /*
991 * SCS TMP SRC
992 * MOV DST TMP.yyyy
993 */
994 static boolean emit_sin(struct svga_shader_emitter *emit,
995 const struct tgsi_full_instruction *insn )
996 {
997 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
998 struct src_register src0 = translate_src_register(
999 emit, &insn->Src[0] );
1000 SVGA3dShaderDestToken temp = get_temp( emit );
1001
1002 /* SCS TMP SRC */
1003 if (!do_emit_sincos(emit, writemask(temp, TGSI_WRITEMASK_Y), src0))
1004 return FALSE;
1005
1006 src0 = scalar(src( temp ), TGSI_SWIZZLE_Y);
1007
1008 /* MOV DST TMP.yyyy */
1009 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ), dst, src0 ))
1010 return FALSE;
1011
1012 return TRUE;
1013 }
1014
1015 /*
1016 * SCS TMP SRC
1017 * MOV DST TMP.xxxx
1018 */
1019 static boolean emit_cos(struct svga_shader_emitter *emit,
1020 const struct tgsi_full_instruction *insn )
1021 {
1022 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
1023 struct src_register src0 = translate_src_register(
1024 emit, &insn->Src[0] );
1025 SVGA3dShaderDestToken temp = get_temp( emit );
1026
1027 /* SCS TMP SRC */
1028 if (!do_emit_sincos( emit, writemask(temp, TGSI_WRITEMASK_X), src0 ))
1029 return FALSE;
1030
1031 src0 = scalar(src( temp ), TGSI_SWIZZLE_X);
1032
1033 /* MOV DST TMP.xxxx */
1034 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ), dst, src0 ))
1035 return FALSE;
1036
1037 return TRUE;
1038 }
1039
1040
1041 /*
1042 * ADD DST SRC0, negate(SRC0)
1043 */
1044 static boolean emit_sub(struct svga_shader_emitter *emit,
1045 const struct tgsi_full_instruction *insn)
1046 {
1047 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
1048 struct src_register src0 = translate_src_register(
1049 emit, &insn->Src[0] );
1050 struct src_register src1 = translate_src_register(
1051 emit, &insn->Src[1] );
1052
1053 src1 = negate(src1);
1054
1055 if (!submit_op2( emit, inst_token( SVGA3DOP_ADD ), dst,
1056 src0, src1 ))
1057 return FALSE;
1058
1059 return TRUE;
1060 }
1061
1062
1063 static boolean emit_kil(struct svga_shader_emitter *emit,
1064 const struct tgsi_full_instruction *insn )
1065 {
1066 SVGA3dShaderInstToken inst;
1067 const struct tgsi_full_src_register *reg = &insn->Src[0];
1068 struct src_register src0;
1069
1070 inst = inst_token( SVGA3DOP_TEXKILL );
1071 src0 = translate_src_register( emit, reg );
1072
1073 if (reg->Register.Absolute ||
1074 reg->Register.Negate ||
1075 reg->Register.Indirect ||
1076 reg->Register.SwizzleX != 0 ||
1077 reg->Register.SwizzleY != 1 ||
1078 reg->Register.SwizzleZ != 2 ||
1079 reg->Register.File != TGSI_FILE_TEMPORARY)
1080 {
1081 SVGA3dShaderDestToken temp = get_temp( emit );
1082
1083 submit_op1( emit, inst_token( SVGA3DOP_MOV ), temp, src0 );
1084 src0 = src( temp );
1085 }
1086
1087 return submit_op0( emit, inst, dst(src0) );
1088 }
1089
1090
1091 /* mesa state tracker always emits kilp as an unconditional
1092 * kil */
1093 static boolean emit_kilp(struct svga_shader_emitter *emit,
1094 const struct tgsi_full_instruction *insn )
1095 {
1096 SVGA3dShaderInstToken inst;
1097 SVGA3dShaderDestToken temp;
1098 struct src_register one = scalar( get_zero_immediate( emit ),
1099 TGSI_SWIZZLE_W );
1100
1101 inst = inst_token( SVGA3DOP_TEXKILL );
1102
1103 /* texkill doesn't allow negation on the operand so lets move
1104 * negation of {1} to a temp register */
1105 temp = get_temp( emit );
1106 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ), temp,
1107 negate( one ) ))
1108 return FALSE;
1109
1110 return submit_op0( emit, inst, temp );
1111 }
1112
1113 /* Implement conditionals by initializing destination reg to 'fail',
1114 * then set predicate reg with UFOP_SETP, then move 'pass' to dest
1115 * based on predicate reg.
1116 *
1117 * SETP src0, cmp, src1 -- do this first to avoid aliasing problems.
1118 * MOV dst, fail
1119 * MOV dst, pass, p0
1120 */
1121 static boolean
1122 emit_conditional(struct svga_shader_emitter *emit,
1123 unsigned compare_func,
1124 SVGA3dShaderDestToken dst,
1125 struct src_register src0,
1126 struct src_register src1,
1127 struct src_register pass,
1128 struct src_register fail)
1129 {
1130 SVGA3dShaderDestToken pred_reg = dst_register( SVGA3DREG_PREDICATE, 0 );
1131 SVGA3dShaderInstToken setp_token, mov_token;
1132 setp_token = inst_token( SVGA3DOP_SETP );
1133
1134 switch (compare_func) {
1135 case PIPE_FUNC_NEVER:
1136 return submit_op1( emit, inst_token( SVGA3DOP_MOV ),
1137 dst, fail );
1138 break;
1139 case PIPE_FUNC_LESS:
1140 setp_token.control = SVGA3DOPCOMP_LT;
1141 break;
1142 case PIPE_FUNC_EQUAL:
1143 setp_token.control = SVGA3DOPCOMP_EQ;
1144 break;
1145 case PIPE_FUNC_LEQUAL:
1146 setp_token.control = SVGA3DOPCOMP_LE;
1147 break;
1148 case PIPE_FUNC_GREATER:
1149 setp_token.control = SVGA3DOPCOMP_GT;
1150 break;
1151 case PIPE_FUNC_NOTEQUAL:
1152 setp_token.control = SVGA3DOPCOMPC_NE;
1153 break;
1154 case PIPE_FUNC_GEQUAL:
1155 setp_token.control = SVGA3DOPCOMP_GE;
1156 break;
1157 case PIPE_FUNC_ALWAYS:
1158 return submit_op1( emit, inst_token( SVGA3DOP_MOV ),
1159 dst, pass );
1160 break;
1161 }
1162
1163 /* SETP src0, COMPOP, src1 */
1164 if (!submit_op2( emit, setp_token, pred_reg,
1165 src0, src1 ))
1166 return FALSE;
1167
1168 mov_token = inst_token( SVGA3DOP_MOV );
1169
1170 /* MOV dst, fail */
1171 if (!submit_op1( emit, mov_token, dst,
1172 fail ))
1173 return FALSE;
1174
1175 /* MOV dst, pass (predicated)
1176 *
1177 * Note that the predicate reg (and possible modifiers) is passed
1178 * as the first source argument.
1179 */
1180 mov_token.predicated = 1;
1181 if (!submit_op2( emit, mov_token, dst,
1182 src( pred_reg ), pass ))
1183 return FALSE;
1184
1185 return TRUE;
1186 }
1187
1188
1189 static boolean
1190 emit_select(struct svga_shader_emitter *emit,
1191 unsigned compare_func,
1192 SVGA3dShaderDestToken dst,
1193 struct src_register src0,
1194 struct src_register src1 )
1195 {
1196 /* There are some SVGA instructions which implement some selects
1197 * directly, but they are only available in the vertex shader.
1198 */
1199 if (emit->unit == PIPE_SHADER_VERTEX) {
1200 switch (compare_func) {
1201 case PIPE_FUNC_GEQUAL:
1202 return submit_op2( emit, inst_token( SVGA3DOP_SGE ), dst, src0, src1 );
1203 case PIPE_FUNC_LEQUAL:
1204 return submit_op2( emit, inst_token( SVGA3DOP_SGE ), dst, src1, src0 );
1205 case PIPE_FUNC_GREATER:
1206 return submit_op2( emit, inst_token( SVGA3DOP_SLT ), dst, src1, src0 );
1207 case PIPE_FUNC_LESS:
1208 return submit_op2( emit, inst_token( SVGA3DOP_SLT ), dst, src0, src1 );
1209 default:
1210 break;
1211 }
1212 }
1213
1214
1215 /* Otherwise, need to use the setp approach:
1216 */
1217 {
1218 struct src_register one, zero;
1219 /* zero immediate is 0,0,0,1 */
1220 zero = get_zero_immediate( emit );
1221 one = scalar( zero, TGSI_SWIZZLE_W );
1222 zero = scalar( zero, TGSI_SWIZZLE_X );
1223
1224 return emit_conditional(
1225 emit,
1226 compare_func,
1227 dst,
1228 src0,
1229 src1,
1230 one, zero);
1231 }
1232 }
1233
1234
1235 static boolean emit_select_op(struct svga_shader_emitter *emit,
1236 unsigned compare,
1237 const struct tgsi_full_instruction *insn)
1238 {
1239 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
1240 struct src_register src0 = translate_src_register(
1241 emit, &insn->Src[0] );
1242 struct src_register src1 = translate_src_register(
1243 emit, &insn->Src[1] );
1244
1245 return emit_select( emit, compare, dst, src0, src1 );
1246 }
1247
1248
1249 /* Translate texture instructions to SVGA3D representation.
1250 */
1251 static boolean emit_tex2(struct svga_shader_emitter *emit,
1252 const struct tgsi_full_instruction *insn,
1253 SVGA3dShaderDestToken dst )
1254 {
1255 SVGA3dShaderInstToken inst;
1256 struct src_register texcoord;
1257 struct src_register sampler;
1258 SVGA3dShaderDestToken tmp;
1259
1260 inst.value = 0;
1261
1262 switch (insn->Instruction.Opcode) {
1263 case TGSI_OPCODE_TEX:
1264 inst.op = SVGA3DOP_TEX;
1265 break;
1266 case TGSI_OPCODE_TXP:
1267 inst.op = SVGA3DOP_TEX;
1268 inst.control = SVGA3DOPCONT_PROJECT;
1269 break;
1270 case TGSI_OPCODE_TXB:
1271 inst.op = SVGA3DOP_TEX;
1272 inst.control = SVGA3DOPCONT_BIAS;
1273 break;
1274 case TGSI_OPCODE_TXL:
1275 inst.op = SVGA3DOP_TEXLDL;
1276 break;
1277 default:
1278 assert(0);
1279 return FALSE;
1280 }
1281
1282 texcoord = translate_src_register( emit, &insn->Src[0] );
1283 sampler = translate_src_register( emit, &insn->Src[1] );
1284
1285 if (emit->key.fkey.tex[sampler.base.num].unnormalized ||
1286 emit->dynamic_branching_level > 0)
1287 tmp = get_temp( emit );
1288
1289 /* Can't do mipmapping inside dynamic branch constructs. Force LOD
1290 * zero in that case.
1291 */
1292 if (emit->dynamic_branching_level > 0 &&
1293 inst.op == SVGA3DOP_TEX &&
1294 SVGA3dShaderGetRegType(texcoord.base.value) == SVGA3DREG_TEMP) {
1295 struct src_register zero = get_zero_immediate( emit );
1296
1297 /* MOV tmp, texcoord */
1298 if (!submit_op1( emit,
1299 inst_token( SVGA3DOP_MOV ),
1300 tmp,
1301 texcoord ))
1302 return FALSE;
1303
1304 /* MOV tmp.w, zero */
1305 if (!submit_op1( emit,
1306 inst_token( SVGA3DOP_MOV ),
1307 writemask( tmp, TGSI_WRITEMASK_W ),
1308 scalar( zero, TGSI_SWIZZLE_X )))
1309 return FALSE;
1310
1311 texcoord = src( tmp );
1312 inst.op = SVGA3DOP_TEXLDL;
1313 }
1314
1315 /* Explicit normalization of texcoords:
1316 */
1317 if (emit->key.fkey.tex[sampler.base.num].unnormalized) {
1318 struct src_register wh = get_tex_dimensions( emit, sampler.base.num );
1319
1320 /* MUL tmp, SRC0, WH */
1321 if (!submit_op2( emit, inst_token( SVGA3DOP_MUL ),
1322 tmp, texcoord, wh ))
1323 return FALSE;
1324
1325 texcoord = src( tmp );
1326 }
1327
1328 return submit_op2( emit, inst, dst, texcoord, sampler );
1329 }
1330
1331
1332
1333
1334 /* Translate texture instructions to SVGA3D representation.
1335 */
1336 static boolean emit_tex4(struct svga_shader_emitter *emit,
1337 const struct tgsi_full_instruction *insn,
1338 SVGA3dShaderDestToken dst )
1339 {
1340 SVGA3dShaderInstToken inst;
1341 struct src_register texcoord;
1342 struct src_register ddx;
1343 struct src_register ddy;
1344 struct src_register sampler;
1345
1346 texcoord = translate_src_register( emit, &insn->Src[0] );
1347 ddx = translate_src_register( emit, &insn->Src[1] );
1348 ddy = translate_src_register( emit, &insn->Src[2] );
1349 sampler = translate_src_register( emit, &insn->Src[3] );
1350
1351 inst.value = 0;
1352
1353 switch (insn->Instruction.Opcode) {
1354 case TGSI_OPCODE_TXD:
1355 inst.op = SVGA3DOP_TEXLDD; /* 4 args! */
1356 break;
1357 default:
1358 assert(0);
1359 return FALSE;
1360 }
1361
1362 return submit_op4( emit, inst, dst, texcoord, sampler, ddx, ddy );
1363 }
1364
1365
1366 static boolean emit_tex(struct svga_shader_emitter *emit,
1367 const struct tgsi_full_instruction *insn )
1368 {
1369 SVGA3dShaderDestToken dst =
1370 translate_dst_register( emit, insn, 0 );
1371 struct src_register src0 =
1372 translate_src_register( emit, &insn->Src[0] );
1373 struct src_register src1 =
1374 translate_src_register( emit, &insn->Src[1] );
1375
1376 SVGA3dShaderDestToken tex_result;
1377
1378 /* check for shadow samplers */
1379 boolean compare = (emit->key.fkey.tex[src1.base.num].compare_mode ==
1380 PIPE_TEX_COMPARE_R_TO_TEXTURE);
1381
1382
1383 /* If doing compare processing, need to put this value into a
1384 * temporary so it can be used as a source later on.
1385 */
1386 if (compare ||
1387 (!emit->use_sm30 && dst.mask != TGSI_WRITEMASK_XYZW) ) {
1388 tex_result = get_temp( emit );
1389 }
1390 else {
1391 tex_result = dst;
1392 }
1393
1394 switch(insn->Instruction.Opcode) {
1395 case TGSI_OPCODE_TEX:
1396 case TGSI_OPCODE_TXB:
1397 case TGSI_OPCODE_TXP:
1398 case TGSI_OPCODE_TXL:
1399 if (!emit_tex2( emit, insn, tex_result ))
1400 return FALSE;
1401 break;
1402 case TGSI_OPCODE_TXD:
1403 if (!emit_tex4( emit, insn, tex_result ))
1404 return FALSE;
1405 break;
1406 default:
1407 assert(0);
1408 }
1409
1410
1411 if (compare) {
1412 SVGA3dShaderDestToken src0_zdivw = get_temp( emit );
1413 struct src_register tex_src_x = scalar(src(tex_result), TGSI_SWIZZLE_Y);
1414 struct src_register one =
1415 scalar( get_zero_immediate( emit ), TGSI_SWIZZLE_W );
1416
1417 /* Divide texcoord R by Q */
1418 if (!submit_op1( emit, inst_token( SVGA3DOP_RCP ),
1419 src0_zdivw,
1420 scalar(src0, TGSI_SWIZZLE_W) ))
1421 return FALSE;
1422
1423 if (!submit_op2( emit, inst_token( SVGA3DOP_MUL ),
1424 src0_zdivw,
1425 scalar(src0, TGSI_SWIZZLE_Z),
1426 src(src0_zdivw) ))
1427 return FALSE;
1428
1429 if (!emit_select(
1430 emit,
1431 emit->key.fkey.tex[src1.base.num].compare_func,
1432 dst,
1433 src(src0_zdivw),
1434 tex_src_x))
1435 return FALSE;
1436
1437 return submit_op1( emit, inst_token( SVGA3DOP_MOV ),
1438 writemask( dst, TGSI_WRITEMASK_W),
1439 one );
1440 }
1441 else if (!emit->use_sm30 && dst.mask != TGSI_WRITEMASK_XYZW)
1442 {
1443 if (!emit_op1( emit, inst_token( SVGA3DOP_MOV ), dst, src(tex_result) ))
1444 return FALSE;
1445 }
1446
1447 return TRUE;
1448 }
1449
1450 static boolean emit_bgnloop2( struct svga_shader_emitter *emit,
1451 const struct tgsi_full_instruction *insn )
1452 {
1453 SVGA3dShaderInstToken inst = inst_token( SVGA3DOP_LOOP );
1454 struct src_register loop_reg = src_register( SVGA3DREG_LOOP, 0 );
1455 struct src_register const_int = get_loop_const( emit );
1456
1457 emit->dynamic_branching_level++;
1458
1459 return (emit_instruction( emit, inst ) &&
1460 emit_src( emit, loop_reg ) &&
1461 emit_src( emit, const_int ) );
1462 }
1463
1464 static boolean emit_endloop2( struct svga_shader_emitter *emit,
1465 const struct tgsi_full_instruction *insn )
1466 {
1467 SVGA3dShaderInstToken inst = inst_token( SVGA3DOP_ENDLOOP );
1468
1469 emit->dynamic_branching_level--;
1470
1471 return emit_instruction( emit, inst );
1472 }
1473
1474 static boolean emit_brk( struct svga_shader_emitter *emit,
1475 const struct tgsi_full_instruction *insn )
1476 {
1477 SVGA3dShaderInstToken inst = inst_token( SVGA3DOP_BREAK );
1478 return emit_instruction( emit, inst );
1479 }
1480
1481 static boolean emit_scalar_op1( struct svga_shader_emitter *emit,
1482 unsigned opcode,
1483 const struct tgsi_full_instruction *insn )
1484 {
1485 SVGA3dShaderInstToken inst;
1486 SVGA3dShaderDestToken dst;
1487 struct src_register src;
1488
1489 inst = inst_token( opcode );
1490 dst = translate_dst_register( emit, insn, 0 );
1491 src = translate_src_register( emit, &insn->Src[0] );
1492 src = scalar( src, TGSI_SWIZZLE_X );
1493
1494 return submit_op1( emit, inst, dst, src );
1495 }
1496
1497
1498 static boolean emit_simple_instruction(struct svga_shader_emitter *emit,
1499 unsigned opcode,
1500 const struct tgsi_full_instruction *insn )
1501 {
1502 const struct tgsi_full_src_register *src = insn->Src;
1503 SVGA3dShaderInstToken inst;
1504 SVGA3dShaderDestToken dst;
1505
1506 inst = inst_token( opcode );
1507 dst = translate_dst_register( emit, insn, 0 );
1508
1509 switch (insn->Instruction.NumSrcRegs) {
1510 case 0:
1511 return submit_op0( emit, inst, dst );
1512 case 1:
1513 return submit_op1( emit, inst, dst,
1514 translate_src_register( emit, &src[0] ));
1515 case 2:
1516 return submit_op2( emit, inst, dst,
1517 translate_src_register( emit, &src[0] ),
1518 translate_src_register( emit, &src[1] ) );
1519 case 3:
1520 return submit_op3( emit, inst, dst,
1521 translate_src_register( emit, &src[0] ),
1522 translate_src_register( emit, &src[1] ),
1523 translate_src_register( emit, &src[2] ) );
1524 default:
1525 assert(0);
1526 return FALSE;
1527 }
1528 }
1529
1530
1531 static boolean emit_deriv(struct svga_shader_emitter *emit,
1532 const struct tgsi_full_instruction *insn )
1533 {
1534 if (emit->dynamic_branching_level > 0 &&
1535 insn->Src[0].Register.File == TGSI_FILE_TEMPORARY)
1536 {
1537 struct src_register zero = get_zero_immediate( emit );
1538 SVGA3dShaderDestToken dst =
1539 translate_dst_register( emit, insn, 0 );
1540
1541 /* Deriv opcodes not valid inside dynamic branching, workaround
1542 * by zeroing out the destination.
1543 */
1544 if (!submit_op1(emit,
1545 inst_token( SVGA3DOP_MOV ),
1546 dst,
1547 scalar(zero, TGSI_SWIZZLE_X)))
1548 return FALSE;
1549
1550 return TRUE;
1551 }
1552 else {
1553 unsigned opcode;
1554
1555 switch (insn->Instruction.Opcode) {
1556 case TGSI_OPCODE_DDX:
1557 opcode = SVGA3DOP_DSX;
1558 break;
1559 case TGSI_OPCODE_DDY:
1560 opcode = SVGA3DOP_DSY;
1561 break;
1562 default:
1563 return FALSE;
1564 }
1565
1566 return emit_simple_instruction( emit, opcode, insn );
1567 }
1568 }
1569
1570 static boolean emit_arl(struct svga_shader_emitter *emit,
1571 const struct tgsi_full_instruction *insn)
1572 {
1573 ++emit->current_arl;
1574 if (svga_arl_needs_adjustment( emit )) {
1575 return emit_fake_arl( emit, insn );
1576 } else {
1577 /* no need to adjust, just emit straight arl */
1578 return emit_simple_instruction(emit, SVGA3DOP_MOVA, insn);
1579 }
1580 }
1581
1582 static boolean alias_src_dst( struct src_register src,
1583 SVGA3dShaderDestToken dst )
1584 {
1585 if (src.base.num != dst.num)
1586 return FALSE;
1587
1588 if (SVGA3dShaderGetRegType(dst.value) !=
1589 SVGA3dShaderGetRegType(src.base.value))
1590 return FALSE;
1591
1592 return TRUE;
1593 }
1594
1595 static boolean emit_pow(struct svga_shader_emitter *emit,
1596 const struct tgsi_full_instruction *insn)
1597 {
1598 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
1599 struct src_register src0 = translate_src_register(
1600 emit, &insn->Src[0] );
1601 struct src_register src1 = translate_src_register(
1602 emit, &insn->Src[1] );
1603 boolean need_tmp = FALSE;
1604
1605 /* POW can only output to a temporary */
1606 if (insn->Dst[0].Register.File != TGSI_FILE_TEMPORARY)
1607 need_tmp = TRUE;
1608
1609 /* POW src1 must not be the same register as dst */
1610 if (alias_src_dst( src1, dst ))
1611 need_tmp = TRUE;
1612
1613 /* it's a scalar op */
1614 src0 = scalar( src0, TGSI_SWIZZLE_X );
1615 src1 = scalar( src1, TGSI_SWIZZLE_X );
1616
1617 if (need_tmp) {
1618 SVGA3dShaderDestToken tmp = writemask(get_temp( emit ), TGSI_WRITEMASK_X );
1619
1620 if (!submit_op2(emit, inst_token( SVGA3DOP_POW ), tmp, src0, src1))
1621 return FALSE;
1622
1623 return submit_op1(emit, inst_token( SVGA3DOP_MOV ), dst, scalar(src(tmp), 0) );
1624 }
1625 else {
1626 return submit_op2(emit, inst_token( SVGA3DOP_POW ), dst, src0, src1);
1627 }
1628 }
1629
1630 static boolean emit_xpd(struct svga_shader_emitter *emit,
1631 const struct tgsi_full_instruction *insn)
1632 {
1633 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
1634 const struct src_register src0 = translate_src_register(
1635 emit, &insn->Src[0] );
1636 const struct src_register src1 = translate_src_register(
1637 emit, &insn->Src[1] );
1638 boolean need_dst_tmp = FALSE;
1639
1640 /* XPD can only output to a temporary */
1641 if (SVGA3dShaderGetRegType(dst.value) != SVGA3DREG_TEMP)
1642 need_dst_tmp = TRUE;
1643
1644 /* The dst reg must not be the same as src0 or src1*/
1645 if (alias_src_dst(src0, dst) ||
1646 alias_src_dst(src1, dst))
1647 need_dst_tmp = TRUE;
1648
1649 if (need_dst_tmp) {
1650 SVGA3dShaderDestToken tmp = get_temp( emit );
1651
1652 /* Obey DX9 restrictions on mask:
1653 */
1654 tmp.mask = dst.mask & TGSI_WRITEMASK_XYZ;
1655
1656 if (!submit_op2(emit, inst_token( SVGA3DOP_CRS ), tmp, src0, src1))
1657 return FALSE;
1658
1659 if (!submit_op1(emit, inst_token( SVGA3DOP_MOV ), dst, src( tmp )))
1660 return FALSE;
1661 }
1662 else {
1663 if (!submit_op2(emit, inst_token( SVGA3DOP_CRS ), dst, src0, src1))
1664 return FALSE;
1665 }
1666
1667 /* Need to emit 1.0 to dst.w?
1668 */
1669 if (dst.mask & TGSI_WRITEMASK_W) {
1670 struct src_register zero = get_zero_immediate( emit );
1671
1672 if (!submit_op1(emit,
1673 inst_token( SVGA3DOP_MOV ),
1674 writemask(dst, TGSI_WRITEMASK_W),
1675 zero))
1676 return FALSE;
1677 }
1678
1679 return TRUE;
1680 }
1681
1682
1683 static boolean emit_lrp(struct svga_shader_emitter *emit,
1684 const struct tgsi_full_instruction *insn)
1685 {
1686 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
1687 SVGA3dShaderDestToken tmp;
1688 const struct src_register src0 = translate_src_register(
1689 emit, &insn->Src[0] );
1690 const struct src_register src1 = translate_src_register(
1691 emit, &insn->Src[1] );
1692 const struct src_register src2 = translate_src_register(
1693 emit, &insn->Src[2] );
1694 boolean need_dst_tmp = FALSE;
1695
1696 /* The dst reg must not be the same as src0 or src2 */
1697 if (alias_src_dst(src0, dst) ||
1698 alias_src_dst(src2, dst))
1699 need_dst_tmp = TRUE;
1700
1701 if (need_dst_tmp) {
1702 tmp = get_temp( emit );
1703 tmp.mask = dst.mask;
1704 }
1705 else {
1706 tmp = dst;
1707 }
1708
1709 if (!submit_op3(emit, inst_token( SVGA3DOP_LRP ), tmp, src0, src1, src2))
1710 return FALSE;
1711
1712 if (need_dst_tmp) {
1713 if (!submit_op1(emit, inst_token( SVGA3DOP_MOV ), dst, src( tmp )))
1714 return FALSE;
1715 }
1716
1717 return TRUE;
1718 }
1719
1720
1721 static boolean emit_dst_insn(struct svga_shader_emitter *emit,
1722 const struct tgsi_full_instruction *insn )
1723 {
1724 if (emit->unit == PIPE_SHADER_VERTEX) {
1725 /* SVGA/DX9 has a DST instruction, but only for vertex shaders:
1726 */
1727 return emit_simple_instruction(emit, SVGA3DOP_DST, insn);
1728 }
1729 else {
1730
1731 /* result[0] = 1 * 1;
1732 * result[1] = a[1] * b[1];
1733 * result[2] = a[2] * 1;
1734 * result[3] = 1 * b[3];
1735 */
1736
1737 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
1738 SVGA3dShaderDestToken tmp;
1739 const struct src_register src0 = translate_src_register(
1740 emit, &insn->Src[0] );
1741 const struct src_register src1 = translate_src_register(
1742 emit, &insn->Src[1] );
1743 struct src_register zero = get_zero_immediate( emit );
1744 boolean need_tmp = FALSE;
1745
1746 if (SVGA3dShaderGetRegType(dst.value) != SVGA3DREG_TEMP ||
1747 alias_src_dst(src0, dst) ||
1748 alias_src_dst(src1, dst))
1749 need_tmp = TRUE;
1750
1751 if (need_tmp) {
1752 tmp = get_temp( emit );
1753 }
1754 else {
1755 tmp = dst;
1756 }
1757
1758 /* tmp.xw = 1.0
1759 */
1760 if (tmp.mask & TGSI_WRITEMASK_XW) {
1761 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ),
1762 writemask(tmp, TGSI_WRITEMASK_XW ),
1763 scalar( zero, 3 )))
1764 return FALSE;
1765 }
1766
1767 /* tmp.yz = src0
1768 */
1769 if (tmp.mask & TGSI_WRITEMASK_YZ) {
1770 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ),
1771 writemask(tmp, TGSI_WRITEMASK_YZ ),
1772 src0))
1773 return FALSE;
1774 }
1775
1776 /* tmp.yw = tmp * src1
1777 */
1778 if (tmp.mask & TGSI_WRITEMASK_YW) {
1779 if (!submit_op2( emit, inst_token( SVGA3DOP_MUL ),
1780 writemask(tmp, TGSI_WRITEMASK_YW ),
1781 src(tmp),
1782 src1))
1783 return FALSE;
1784 }
1785
1786 /* dst = tmp
1787 */
1788 if (need_tmp) {
1789 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ),
1790 dst,
1791 src(tmp)))
1792 return FALSE;
1793 }
1794 }
1795
1796 return TRUE;
1797 }
1798
1799
1800 static boolean emit_exp(struct svga_shader_emitter *emit,
1801 const struct tgsi_full_instruction *insn)
1802 {
1803 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
1804 struct src_register src0 =
1805 translate_src_register( emit, &insn->Src[0] );
1806 struct src_register zero = get_zero_immediate( emit );
1807 SVGA3dShaderDestToken fraction;
1808
1809 if (dst.mask & TGSI_WRITEMASK_Y)
1810 fraction = dst;
1811 else if (dst.mask & TGSI_WRITEMASK_X)
1812 fraction = get_temp( emit );
1813
1814 /* If y is being written, fill it with src0 - floor(src0).
1815 */
1816 if (dst.mask & TGSI_WRITEMASK_XY) {
1817 if (!submit_op1( emit, inst_token( SVGA3DOP_FRC ),
1818 writemask( fraction, TGSI_WRITEMASK_Y ),
1819 src0 ))
1820 return FALSE;
1821 }
1822
1823 /* If x is being written, fill it with 2 ^ floor(src0).
1824 */
1825 if (dst.mask & TGSI_WRITEMASK_X) {
1826 if (!submit_op2( emit, inst_token( SVGA3DOP_ADD ),
1827 writemask( dst, dst.mask & TGSI_WRITEMASK_X ),
1828 src0,
1829 scalar( negate( src( fraction ) ), TGSI_SWIZZLE_Y ) ) )
1830 return FALSE;
1831
1832 if (!submit_op1( emit, inst_token( SVGA3DOP_EXP ),
1833 writemask( dst, dst.mask & TGSI_WRITEMASK_X ),
1834 scalar( src( dst ), TGSI_SWIZZLE_X ) ) )
1835 return FALSE;
1836
1837 if (!(dst.mask & TGSI_WRITEMASK_Y))
1838 release_temp( emit, fraction );
1839 }
1840
1841 /* If z is being written, fill it with 2 ^ src0 (partial precision).
1842 */
1843 if (dst.mask & TGSI_WRITEMASK_Z) {
1844 if (!submit_op1( emit, inst_token( SVGA3DOP_EXPP ),
1845 writemask( dst, dst.mask & TGSI_WRITEMASK_Z ),
1846 src0 ) )
1847 return FALSE;
1848 }
1849
1850 /* If w is being written, fill it with one.
1851 */
1852 if (dst.mask & TGSI_WRITEMASK_W) {
1853 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ),
1854 writemask(dst, TGSI_WRITEMASK_W),
1855 scalar( zero, TGSI_SWIZZLE_W ) ))
1856 return FALSE;
1857 }
1858
1859 return TRUE;
1860 }
1861
1862 static boolean emit_lit(struct svga_shader_emitter *emit,
1863 const struct tgsi_full_instruction *insn )
1864 {
1865 if (emit->unit == PIPE_SHADER_VERTEX) {
1866 /* SVGA/DX9 has a LIT instruction, but only for vertex shaders:
1867 */
1868 return emit_simple_instruction(emit, SVGA3DOP_LIT, insn);
1869 }
1870 else {
1871
1872 /* D3D vs. GL semantics can be fairly easily accomodated by
1873 * variations on this sequence.
1874 *
1875 * GL:
1876 * tmp.y = src.x
1877 * tmp.z = pow(src.y,src.w)
1878 * p0 = src0.xxxx > 0
1879 * result = zero.wxxw
1880 * (p0) result.yz = tmp
1881 *
1882 * D3D:
1883 * tmp.y = src.x
1884 * tmp.z = pow(src.y,src.w)
1885 * p0 = src0.xxyy > 0
1886 * result = zero.wxxw
1887 * (p0) result.yz = tmp
1888 *
1889 * Will implement the GL version for now.
1890 */
1891
1892 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
1893 SVGA3dShaderDestToken tmp = get_temp( emit );
1894 const struct src_register src0 = translate_src_register(
1895 emit, &insn->Src[0] );
1896 struct src_register zero = get_zero_immediate( emit );
1897
1898 /* tmp = pow(src.y, src.w)
1899 */
1900 if (dst.mask & TGSI_WRITEMASK_Z) {
1901 if (!submit_op2(emit, inst_token( SVGA3DOP_POW ),
1902 tmp,
1903 scalar(src0, 1),
1904 scalar(src0, 3)))
1905 return FALSE;
1906 }
1907
1908 /* tmp.y = src.x
1909 */
1910 if (dst.mask & TGSI_WRITEMASK_Y) {
1911 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ),
1912 writemask(tmp, TGSI_WRITEMASK_Y ),
1913 scalar(src0, 0)))
1914 return FALSE;
1915 }
1916
1917 /* Can't quite do this with emit conditional due to the extra
1918 * writemask on the predicated mov:
1919 */
1920 {
1921 SVGA3dShaderDestToken pred_reg = dst_register( SVGA3DREG_PREDICATE, 0 );
1922 SVGA3dShaderInstToken setp_token, mov_token;
1923 struct src_register predsrc;
1924
1925 setp_token = inst_token( SVGA3DOP_SETP );
1926 mov_token = inst_token( SVGA3DOP_MOV );
1927
1928 setp_token.control = SVGA3DOPCOMP_GT;
1929
1930 /* D3D vs GL semantics:
1931 */
1932 if (0)
1933 predsrc = swizzle(src0, 0, 0, 1, 1); /* D3D */
1934 else
1935 predsrc = swizzle(src0, 0, 0, 0, 0); /* GL */
1936
1937 /* SETP src0.xxyy, GT, {0}.x */
1938 if (!submit_op2( emit, setp_token, pred_reg,
1939 predsrc,
1940 swizzle(zero, 0, 0, 0, 0) ))
1941 return FALSE;
1942
1943 /* MOV dst, fail */
1944 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ), dst,
1945 swizzle(zero, 3, 0, 0, 3 )))
1946 return FALSE;
1947
1948 /* MOV dst.yz, tmp (predicated)
1949 *
1950 * Note that the predicate reg (and possible modifiers) is passed
1951 * as the first source argument.
1952 */
1953 if (dst.mask & TGSI_WRITEMASK_YZ) {
1954 mov_token.predicated = 1;
1955 if (!submit_op2( emit, mov_token,
1956 writemask(dst, TGSI_WRITEMASK_YZ),
1957 src( pred_reg ), src( tmp ) ))
1958 return FALSE;
1959 }
1960 }
1961 }
1962
1963 return TRUE;
1964 }
1965
1966
1967
1968
1969 static boolean emit_ex2( struct svga_shader_emitter *emit,
1970 const struct tgsi_full_instruction *insn )
1971 {
1972 SVGA3dShaderInstToken inst;
1973 SVGA3dShaderDestToken dst;
1974 struct src_register src0;
1975
1976 inst = inst_token( SVGA3DOP_EXP );
1977 dst = translate_dst_register( emit, insn, 0 );
1978 src0 = translate_src_register( emit, &insn->Src[0] );
1979 src0 = scalar( src0, TGSI_SWIZZLE_X );
1980
1981 if (dst.mask != TGSI_WRITEMASK_XYZW) {
1982 SVGA3dShaderDestToken tmp = get_temp( emit );
1983
1984 if (!submit_op1( emit, inst, tmp, src0 ))
1985 return FALSE;
1986
1987 return submit_op1( emit, inst_token( SVGA3DOP_MOV ),
1988 dst,
1989 scalar( src( tmp ), TGSI_SWIZZLE_X ) );
1990 }
1991
1992 return submit_op1( emit, inst, dst, src0 );
1993 }
1994
1995
1996 static boolean emit_log(struct svga_shader_emitter *emit,
1997 const struct tgsi_full_instruction *insn)
1998 {
1999 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
2000 struct src_register src0 =
2001 translate_src_register( emit, &insn->Src[0] );
2002 struct src_register zero = get_zero_immediate( emit );
2003 SVGA3dShaderDestToken abs_tmp;
2004 struct src_register abs_src0;
2005 SVGA3dShaderDestToken log2_abs;
2006
2007 if (dst.mask & TGSI_WRITEMASK_Z)
2008 log2_abs = dst;
2009 else if (dst.mask & TGSI_WRITEMASK_XY)
2010 log2_abs = get_temp( emit );
2011
2012 /* If z is being written, fill it with log2( abs( src0 ) ).
2013 */
2014 if (dst.mask & TGSI_WRITEMASK_XYZ) {
2015 if (!src0.base.srcMod || src0.base.srcMod == SVGA3DSRCMOD_ABS)
2016 abs_src0 = src0;
2017 else {
2018 abs_tmp = get_temp( emit );
2019
2020 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ),
2021 abs_tmp,
2022 src0 ) )
2023 return FALSE;
2024
2025 abs_src0 = src( abs_tmp );
2026 }
2027
2028 abs_src0 = absolute( scalar( abs_src0, TGSI_SWIZZLE_X ) );
2029
2030 if (!submit_op1( emit, inst_token( SVGA3DOP_LOG ),
2031 writemask( log2_abs, TGSI_WRITEMASK_Z ),
2032 abs_src0 ) )
2033 return FALSE;
2034 }
2035
2036 if (dst.mask & TGSI_WRITEMASK_XY) {
2037 SVGA3dShaderDestToken floor_log2;
2038
2039 if (dst.mask & TGSI_WRITEMASK_X)
2040 floor_log2 = dst;
2041 else
2042 floor_log2 = get_temp( emit );
2043
2044 /* If x is being written, fill it with floor( log2( abs( src0 ) ) ).
2045 */
2046 if (!submit_op1( emit, inst_token( SVGA3DOP_FRC ),
2047 writemask( floor_log2, TGSI_WRITEMASK_X ),
2048 scalar( src( log2_abs ), TGSI_SWIZZLE_Z ) ) )
2049 return FALSE;
2050
2051 if (!submit_op2( emit, inst_token( SVGA3DOP_ADD ),
2052 writemask( floor_log2, TGSI_WRITEMASK_X ),
2053 scalar( src( log2_abs ), TGSI_SWIZZLE_Z ),
2054 negate( src( floor_log2 ) ) ) )
2055 return FALSE;
2056
2057 /* If y is being written, fill it with
2058 * abs ( src0 ) / ( 2 ^ floor( log2( abs( src0 ) ) ) ).
2059 */
2060 if (dst.mask & TGSI_WRITEMASK_Y) {
2061 if (!submit_op1( emit, inst_token( SVGA3DOP_EXP ),
2062 writemask( dst, TGSI_WRITEMASK_Y ),
2063 negate( scalar( src( floor_log2 ),
2064 TGSI_SWIZZLE_X ) ) ) )
2065 return FALSE;
2066
2067 if (!submit_op2( emit, inst_token( SVGA3DOP_MUL ),
2068 writemask( dst, TGSI_WRITEMASK_Y ),
2069 src( dst ),
2070 abs_src0 ) )
2071 return FALSE;
2072 }
2073
2074 if (!(dst.mask & TGSI_WRITEMASK_X))
2075 release_temp( emit, floor_log2 );
2076
2077 if (!(dst.mask & TGSI_WRITEMASK_Z))
2078 release_temp( emit, log2_abs );
2079 }
2080
2081 if (dst.mask & TGSI_WRITEMASK_XYZ && src0.base.srcMod &&
2082 src0.base.srcMod != SVGA3DSRCMOD_ABS)
2083 release_temp( emit, abs_tmp );
2084
2085 /* If w is being written, fill it with one.
2086 */
2087 if (dst.mask & TGSI_WRITEMASK_W) {
2088 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ),
2089 writemask(dst, TGSI_WRITEMASK_W),
2090 scalar( zero, TGSI_SWIZZLE_W ) ))
2091 return FALSE;
2092 }
2093
2094 return TRUE;
2095 }
2096
2097
2098 static boolean emit_bgnsub( struct svga_shader_emitter *emit,
2099 unsigned position,
2100 const struct tgsi_full_instruction *insn )
2101 {
2102 unsigned i;
2103
2104 /* Note that we've finished the main function and are now emitting
2105 * subroutines. This affects how we terminate the generated
2106 * shader.
2107 */
2108 emit->in_main_func = FALSE;
2109
2110 for (i = 0; i < emit->nr_labels; i++) {
2111 if (emit->label[i] == position) {
2112 return (emit_instruction( emit, inst_token( SVGA3DOP_RET ) ) &&
2113 emit_instruction( emit, inst_token( SVGA3DOP_LABEL ) ) &&
2114 emit_src( emit, src_register( SVGA3DREG_LABEL, i )));
2115 }
2116 }
2117
2118 assert(0);
2119 return TRUE;
2120 }
2121
2122 static boolean emit_call( struct svga_shader_emitter *emit,
2123 const struct tgsi_full_instruction *insn )
2124 {
2125 unsigned position = insn->Label.Label;
2126 unsigned i;
2127
2128 for (i = 0; i < emit->nr_labels; i++) {
2129 if (emit->label[i] == position)
2130 break;
2131 }
2132
2133 if (emit->nr_labels == Elements(emit->label))
2134 return FALSE;
2135
2136 if (i == emit->nr_labels) {
2137 emit->label[i] = position;
2138 emit->nr_labels++;
2139 }
2140
2141 return (emit_instruction( emit, inst_token( SVGA3DOP_CALL ) ) &&
2142 emit_src( emit, src_register( SVGA3DREG_LABEL, i )));
2143 }
2144
2145
2146 static boolean emit_end( struct svga_shader_emitter *emit )
2147 {
2148 if (emit->unit == PIPE_SHADER_VERTEX) {
2149 return emit_vs_postamble( emit );
2150 }
2151 else {
2152 return emit_ps_postamble( emit );
2153 }
2154 }
2155
2156
2157
2158 static boolean svga_emit_instruction( struct svga_shader_emitter *emit,
2159 unsigned position,
2160 const struct tgsi_full_instruction *insn )
2161 {
2162 switch (insn->Instruction.Opcode) {
2163
2164 case TGSI_OPCODE_ARL:
2165 return emit_arl( emit, insn );
2166
2167 case TGSI_OPCODE_TEX:
2168 case TGSI_OPCODE_TXB:
2169 case TGSI_OPCODE_TXP:
2170 case TGSI_OPCODE_TXL:
2171 case TGSI_OPCODE_TXD:
2172 return emit_tex( emit, insn );
2173
2174 case TGSI_OPCODE_DDX:
2175 case TGSI_OPCODE_DDY:
2176 return emit_deriv( emit, insn );
2177
2178 case TGSI_OPCODE_BGNSUB:
2179 return emit_bgnsub( emit, position, insn );
2180
2181 case TGSI_OPCODE_ENDSUB:
2182 return TRUE;
2183
2184 case TGSI_OPCODE_CAL:
2185 return emit_call( emit, insn );
2186
2187 case TGSI_OPCODE_FLR:
2188 case TGSI_OPCODE_TRUNC: /* should be TRUNC, not FLR */
2189 return emit_floor( emit, insn );
2190
2191 case TGSI_OPCODE_CMP:
2192 return emit_cmp( emit, insn );
2193
2194 case TGSI_OPCODE_DIV:
2195 return emit_div( emit, insn );
2196
2197 case TGSI_OPCODE_DP2:
2198 return emit_dp2( emit, insn );
2199
2200 case TGSI_OPCODE_DPH:
2201 return emit_dph( emit, insn );
2202
2203 case TGSI_OPCODE_NRM:
2204 return emit_nrm( emit, insn );
2205
2206 case TGSI_OPCODE_COS:
2207 return emit_cos( emit, insn );
2208
2209 case TGSI_OPCODE_SIN:
2210 return emit_sin( emit, insn );
2211
2212 case TGSI_OPCODE_SCS:
2213 return emit_sincos( emit, insn );
2214
2215 case TGSI_OPCODE_END:
2216 /* TGSI always finishes the main func with an END */
2217 return emit_end( emit );
2218
2219 case TGSI_OPCODE_KIL:
2220 return emit_kil( emit, insn );
2221
2222 /* Selection opcodes. The underlying language is fairly
2223 * non-orthogonal about these.
2224 */
2225 case TGSI_OPCODE_SEQ:
2226 return emit_select_op( emit, PIPE_FUNC_EQUAL, insn );
2227
2228 case TGSI_OPCODE_SNE:
2229 return emit_select_op( emit, PIPE_FUNC_NOTEQUAL, insn );
2230
2231 case TGSI_OPCODE_SGT:
2232 return emit_select_op( emit, PIPE_FUNC_GREATER, insn );
2233
2234 case TGSI_OPCODE_SGE:
2235 return emit_select_op( emit, PIPE_FUNC_GEQUAL, insn );
2236
2237 case TGSI_OPCODE_SLT:
2238 return emit_select_op( emit, PIPE_FUNC_LESS, insn );
2239
2240 case TGSI_OPCODE_SLE:
2241 return emit_select_op( emit, PIPE_FUNC_LEQUAL, insn );
2242
2243 case TGSI_OPCODE_SUB:
2244 return emit_sub( emit, insn );
2245
2246 case TGSI_OPCODE_POW:
2247 return emit_pow( emit, insn );
2248
2249 case TGSI_OPCODE_EX2:
2250 return emit_ex2( emit, insn );
2251
2252 case TGSI_OPCODE_EXP:
2253 return emit_exp( emit, insn );
2254
2255 case TGSI_OPCODE_LOG:
2256 return emit_log( emit, insn );
2257
2258 case TGSI_OPCODE_LG2:
2259 return emit_scalar_op1( emit, SVGA3DOP_LOG, insn );
2260
2261 case TGSI_OPCODE_RSQ:
2262 return emit_scalar_op1( emit, SVGA3DOP_RSQ, insn );
2263
2264 case TGSI_OPCODE_RCP:
2265 return emit_scalar_op1( emit, SVGA3DOP_RCP, insn );
2266
2267 case TGSI_OPCODE_CONT:
2268 case TGSI_OPCODE_RET:
2269 /* This is a noop -- we tell mesa that we can't support RET
2270 * within a function (early return), so this will always be
2271 * followed by an ENDSUB.
2272 */
2273 return TRUE;
2274
2275 /* These aren't actually used by any of the frontends we care
2276 * about:
2277 */
2278 case TGSI_OPCODE_CLAMP:
2279 case TGSI_OPCODE_ROUND:
2280 case TGSI_OPCODE_AND:
2281 case TGSI_OPCODE_OR:
2282 case TGSI_OPCODE_I2F:
2283 case TGSI_OPCODE_NOT:
2284 case TGSI_OPCODE_SHL:
2285 case TGSI_OPCODE_ISHR:
2286 case TGSI_OPCODE_XOR:
2287 return FALSE;
2288
2289 case TGSI_OPCODE_IF:
2290 return emit_if( emit, insn );
2291 case TGSI_OPCODE_ELSE:
2292 return emit_else( emit, insn );
2293 case TGSI_OPCODE_ENDIF:
2294 return emit_endif( emit, insn );
2295
2296 case TGSI_OPCODE_BGNLOOP:
2297 return emit_bgnloop2( emit, insn );
2298 case TGSI_OPCODE_ENDLOOP:
2299 return emit_endloop2( emit, insn );
2300 case TGSI_OPCODE_BRK:
2301 return emit_brk( emit, insn );
2302
2303 case TGSI_OPCODE_XPD:
2304 return emit_xpd( emit, insn );
2305
2306 case TGSI_OPCODE_KILP:
2307 return emit_kilp( emit, insn );
2308
2309 case TGSI_OPCODE_DST:
2310 return emit_dst_insn( emit, insn );
2311
2312 case TGSI_OPCODE_LIT:
2313 return emit_lit( emit, insn );
2314
2315 case TGSI_OPCODE_LRP:
2316 return emit_lrp( emit, insn );
2317
2318 default: {
2319 unsigned opcode = translate_opcode(insn->Instruction.Opcode);
2320
2321 if (opcode == SVGA3DOP_LAST_INST)
2322 return FALSE;
2323
2324 if (!emit_simple_instruction( emit, opcode, insn ))
2325 return FALSE;
2326 }
2327 }
2328
2329 return TRUE;
2330 }
2331
2332
2333 static boolean svga_emit_immediate( struct svga_shader_emitter *emit,
2334 struct tgsi_full_immediate *imm)
2335 {
2336 static const float id[4] = {0,0,0,1};
2337 float value[4];
2338 unsigned i;
2339
2340 assert(1 <= imm->Immediate.NrTokens && imm->Immediate.NrTokens <= 5);
2341 for (i = 0; i < imm->Immediate.NrTokens - 1; i++)
2342 value[i] = imm->u[i].Float;
2343
2344 for ( ; i < 4; i++ )
2345 value[i] = id[i];
2346
2347 return emit_def_const( emit, SVGA3D_CONST_TYPE_FLOAT,
2348 emit->imm_start + emit->internal_imm_count++,
2349 value[0], value[1], value[2], value[3]);
2350 }
2351
2352 static boolean make_immediate( struct svga_shader_emitter *emit,
2353 float a,
2354 float b,
2355 float c,
2356 float d,
2357 struct src_register *out )
2358 {
2359 unsigned idx = emit->nr_hw_const++;
2360
2361 if (!emit_def_const( emit, SVGA3D_CONST_TYPE_FLOAT,
2362 idx, a, b, c, d ))
2363 return FALSE;
2364
2365 *out = src_register( SVGA3DREG_CONST, idx );
2366
2367 return TRUE;
2368 }
2369
2370 static boolean emit_vs_preamble( struct svga_shader_emitter *emit )
2371 {
2372 if (!emit->key.vkey.need_prescale) {
2373 if (!make_immediate( emit, 0, 0, .5, .5,
2374 &emit->imm_0055))
2375 return FALSE;
2376 }
2377
2378 return TRUE;
2379 }
2380
2381 static boolean emit_ps_preamble( struct svga_shader_emitter *emit )
2382 {
2383 unsigned i;
2384
2385 /* For SM20, need to initialize the temporaries we're using to hold
2386 * color outputs to some value. Shaders which don't set all of
2387 * these values are likely to be rejected by the DX9 runtime.
2388 */
2389 if (!emit->use_sm30) {
2390 struct src_register zero = get_zero_immediate( emit );
2391 for (i = 0; i < PIPE_MAX_COLOR_BUFS; i++) {
2392 if (SVGA3dShaderGetRegType(emit->true_col[i].value) != 0) {
2393
2394 if (!submit_op1( emit,
2395 inst_token(SVGA3DOP_MOV),
2396 emit->temp_col[i],
2397 zero ))
2398 return FALSE;
2399 }
2400 }
2401 }
2402
2403 return TRUE;
2404 }
2405
2406 static boolean emit_ps_postamble( struct svga_shader_emitter *emit )
2407 {
2408 unsigned i;
2409
2410 /* PS oDepth is incredibly fragile and it's very hard to catch the
2411 * types of usage that break it during shader emit. Easier just to
2412 * redirect the main program to a temporary and then only touch
2413 * oDepth with a hand-crafted MOV below.
2414 */
2415 if (SVGA3dShaderGetRegType(emit->true_pos.value) != 0) {
2416
2417 if (!submit_op1( emit,
2418 inst_token(SVGA3DOP_MOV),
2419 emit->true_pos,
2420 scalar(src(emit->temp_pos), TGSI_SWIZZLE_Z) ))
2421 return FALSE;
2422 }
2423
2424 /* Similarly for SM20 color outputs... Luckily SM30 isn't so
2425 * fragile.
2426 */
2427 for (i = 0; i < PIPE_MAX_COLOR_BUFS; i++) {
2428 if (SVGA3dShaderGetRegType(emit->true_col[i].value) != 0) {
2429
2430 /* Potentially override output colors with white for XOR
2431 * logicop workaround.
2432 */
2433 if (emit->unit == PIPE_SHADER_FRAGMENT &&
2434 emit->key.fkey.white_fragments) {
2435
2436 struct src_register one = scalar( get_zero_immediate( emit ),
2437 TGSI_SWIZZLE_W );
2438
2439 if (!submit_op1( emit,
2440 inst_token(SVGA3DOP_MOV),
2441 emit->true_col[i],
2442 one ))
2443 return FALSE;
2444 }
2445 else {
2446 if (!submit_op1( emit,
2447 inst_token(SVGA3DOP_MOV),
2448 emit->true_col[i],
2449 src(emit->temp_col[i]) ))
2450 return FALSE;
2451 }
2452 }
2453 }
2454
2455 return TRUE;
2456 }
2457
2458 static boolean emit_vs_postamble( struct svga_shader_emitter *emit )
2459 {
2460 /* PSIZ output is incredibly fragile and it's very hard to catch
2461 * the types of usage that break it during shader emit. Easier
2462 * just to redirect the main program to a temporary and then only
2463 * touch PSIZ with a hand-crafted MOV below.
2464 */
2465 if (SVGA3dShaderGetRegType(emit->true_psiz.value) != 0) {
2466
2467 if (!submit_op1( emit,
2468 inst_token(SVGA3DOP_MOV),
2469 emit->true_psiz,
2470 scalar(src(emit->temp_psiz), TGSI_SWIZZLE_X) ))
2471 return FALSE;
2472 }
2473
2474 /* Need to perform various manipulations on vertex position to cope
2475 * with the different GL and D3D clip spaces.
2476 */
2477 if (emit->key.vkey.need_prescale) {
2478 SVGA3dShaderDestToken temp_pos = emit->temp_pos;
2479 SVGA3dShaderDestToken pos = emit->true_pos;
2480 unsigned offset = emit->info.file_max[TGSI_FILE_CONSTANT] + 1;
2481 struct src_register prescale_scale = src_register( SVGA3DREG_CONST,
2482 offset + 0 );
2483 struct src_register prescale_trans = src_register( SVGA3DREG_CONST,
2484 offset + 1 );
2485
2486 /* MUL temp_pos.xyz, temp_pos, prescale.scale
2487 * MAD result.position, temp_pos.wwww, prescale.trans, temp_pos
2488 * --> Note that prescale.trans.w == 0
2489 */
2490 if (!submit_op2( emit,
2491 inst_token(SVGA3DOP_MUL),
2492 writemask(temp_pos, TGSI_WRITEMASK_XYZ),
2493 src(temp_pos),
2494 prescale_scale ))
2495 return FALSE;
2496
2497 if (!submit_op3( emit,
2498 inst_token(SVGA3DOP_MAD),
2499 pos,
2500 swizzle(src(temp_pos), 3, 3, 3, 3),
2501 prescale_trans,
2502 src(temp_pos)))
2503 return FALSE;
2504 }
2505 else {
2506 SVGA3dShaderDestToken temp_pos = emit->temp_pos;
2507 SVGA3dShaderDestToken pos = emit->true_pos;
2508 struct src_register imm_0055 = emit->imm_0055;
2509
2510 /* Adjust GL clipping coordinate space to hardware (D3D-style):
2511 *
2512 * DP4 temp_pos.z, {0,0,.5,.5}, temp_pos
2513 * MOV result.position, temp_pos
2514 */
2515 if (!submit_op2( emit,
2516 inst_token(SVGA3DOP_DP4),
2517 writemask(temp_pos, TGSI_WRITEMASK_Z),
2518 imm_0055,
2519 src(temp_pos) ))
2520 return FALSE;
2521
2522 if (!submit_op1( emit,
2523 inst_token(SVGA3DOP_MOV),
2524 pos,
2525 src(temp_pos) ))
2526 return FALSE;
2527 }
2528
2529 return TRUE;
2530 }
2531
2532 /*
2533 0: IF VFACE :4
2534 1: COLOR = FrontColor;
2535 2: ELSE
2536 3: COLOR = BackColor;
2537 4: ENDIF
2538 */
2539 static boolean emit_light_twoside( struct svga_shader_emitter *emit )
2540 {
2541 struct src_register vface, zero;
2542 struct src_register front[2];
2543 struct src_register back[2];
2544 SVGA3dShaderDestToken color[2];
2545 int count = emit->internal_color_count;
2546 int i;
2547 SVGA3dShaderInstToken if_token;
2548
2549 if (count == 0)
2550 return TRUE;
2551
2552 vface = get_vface( emit );
2553 zero = get_zero_immediate( emit );
2554
2555 /* Can't use get_temp() to allocate the color reg as such
2556 * temporaries will be reclaimed after each instruction by the call
2557 * to reset_temp_regs().
2558 */
2559 for (i = 0; i < count; i++) {
2560 color[i] = dst_register( SVGA3DREG_TEMP,
2561 emit->nr_hw_temp++ );
2562
2563 front[i] = emit->input_map[emit->internal_color_idx[i]];
2564
2565 /* Back is always the next input:
2566 */
2567 back[i] = front[i];
2568 back[i].base.num = front[i].base.num + 1;
2569
2570 /* Reassign the input_map to the actual front-face color:
2571 */
2572 emit->input_map[emit->internal_color_idx[i]] = src(color[i]);
2573 }
2574
2575 if_token = inst_token( SVGA3DOP_IFC );
2576
2577 if (emit->key.fkey.front_cw)
2578 if_token.control = SVGA3DOPCOMP_GT;
2579 else
2580 if_token.control = SVGA3DOPCOMP_LT;
2581
2582 zero = scalar(zero, TGSI_SWIZZLE_X);
2583
2584 if (!(emit_instruction( emit, if_token ) &&
2585 emit_src( emit, vface ) &&
2586 emit_src( emit, zero ) ))
2587 return FALSE;
2588
2589 for (i = 0; i < count; i++) {
2590 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ), color[i], front[i] ))
2591 return FALSE;
2592 }
2593
2594 if (!(emit_instruction( emit, inst_token( SVGA3DOP_ELSE))))
2595 return FALSE;
2596
2597 for (i = 0; i < count; i++) {
2598 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ), color[i], back[i] ))
2599 return FALSE;
2600 }
2601
2602 if (!emit_instruction( emit, inst_token( SVGA3DOP_ENDIF ) ))
2603 return FALSE;
2604
2605 return TRUE;
2606 }
2607
2608 /*
2609 0: SETP_GT TEMP, VFACE, 0
2610 where TEMP is a fake frontface register
2611 */
2612 static boolean emit_frontface( struct svga_shader_emitter *emit )
2613 {
2614 struct src_register vface, zero;
2615 SVGA3dShaderDestToken temp;
2616 struct src_register pass, fail;
2617
2618 vface = get_vface( emit );
2619 zero = get_zero_immediate( emit );
2620
2621 /* Can't use get_temp() to allocate the fake frontface reg as such
2622 * temporaries will be reclaimed after each instruction by the call
2623 * to reset_temp_regs().
2624 */
2625 temp = dst_register( SVGA3DREG_TEMP,
2626 emit->nr_hw_temp++ );
2627
2628 if (emit->key.fkey.front_cw) {
2629 pass = scalar( zero, TGSI_SWIZZLE_W );
2630 fail = scalar( zero, TGSI_SWIZZLE_X );
2631 } else {
2632 pass = scalar( zero, TGSI_SWIZZLE_X );
2633 fail = scalar( zero, TGSI_SWIZZLE_W );
2634 }
2635
2636 if (!emit_conditional(emit, PIPE_FUNC_GREATER,
2637 temp, vface, scalar( zero, TGSI_SWIZZLE_X ),
2638 pass, fail))
2639 return FALSE;
2640
2641 /* Reassign the input_map to the actual front-face color:
2642 */
2643 emit->input_map[emit->internal_frontface_idx] = src(temp);
2644
2645 return TRUE;
2646 }
2647
2648 static INLINE boolean
2649 needs_to_create_zero( struct svga_shader_emitter *emit )
2650 {
2651 int i;
2652
2653 if (emit->unit == PIPE_SHADER_FRAGMENT) {
2654 if (!emit->use_sm30)
2655 return TRUE;
2656
2657 if (emit->key.fkey.light_twoside)
2658 return TRUE;
2659
2660 if (emit->key.fkey.white_fragments)
2661 return TRUE;
2662
2663 if (emit->emit_frontface)
2664 return TRUE;
2665
2666 if (emit->info.opcode_count[TGSI_OPCODE_DST] >= 1 ||
2667 emit->info.opcode_count[TGSI_OPCODE_LIT] >= 1)
2668 return TRUE;
2669 }
2670
2671 if (emit->info.opcode_count[TGSI_OPCODE_IF] >= 1 ||
2672 emit->info.opcode_count[TGSI_OPCODE_BGNLOOP] >= 1 ||
2673 emit->info.opcode_count[TGSI_OPCODE_BGNFOR] >= 1 ||
2674 emit->info.opcode_count[TGSI_OPCODE_DDX] >= 1 ||
2675 emit->info.opcode_count[TGSI_OPCODE_DDY] >= 1 ||
2676 emit->info.opcode_count[TGSI_OPCODE_SGE] >= 1 ||
2677 emit->info.opcode_count[TGSI_OPCODE_SGT] >= 1 ||
2678 emit->info.opcode_count[TGSI_OPCODE_SLE] >= 1 ||
2679 emit->info.opcode_count[TGSI_OPCODE_SLT] >= 1 ||
2680 emit->info.opcode_count[TGSI_OPCODE_SNE] >= 1 ||
2681 emit->info.opcode_count[TGSI_OPCODE_SEQ] >= 1 ||
2682 emit->info.opcode_count[TGSI_OPCODE_EXP] >= 1 ||
2683 emit->info.opcode_count[TGSI_OPCODE_LOG] >= 1 ||
2684 emit->info.opcode_count[TGSI_OPCODE_XPD] >= 1 ||
2685 emit->info.opcode_count[TGSI_OPCODE_KILP] >= 1)
2686 return TRUE;
2687
2688 for (i = 0; i < emit->key.fkey.num_textures; i++) {
2689 if (emit->key.fkey.tex[i].compare_mode == PIPE_TEX_COMPARE_R_TO_TEXTURE)
2690 return TRUE;
2691 }
2692
2693 return FALSE;
2694 }
2695
2696 static INLINE boolean
2697 needs_to_create_loop_const( struct svga_shader_emitter *emit )
2698 {
2699 return (emit->info.opcode_count[TGSI_OPCODE_BGNLOOP] >= 1);
2700 }
2701
2702 static INLINE boolean
2703 needs_to_create_sincos_consts( struct svga_shader_emitter *emit )
2704 {
2705 return !emit->use_sm30 && (emit->info.opcode_count[TGSI_OPCODE_SIN] >= 1 ||
2706 emit->info.opcode_count[TGSI_OPCODE_COS] >= 1 ||
2707 emit->info.opcode_count[TGSI_OPCODE_SCS] >= 1);
2708 }
2709
2710 static INLINE boolean
2711 needs_to_create_arl_consts( struct svga_shader_emitter *emit )
2712 {
2713 return (emit->num_arl_consts > 0);
2714 }
2715
2716 static INLINE boolean
2717 pre_parse_add_indirect( struct svga_shader_emitter *emit,
2718 int num, int current_arl)
2719 {
2720 int i;
2721 assert(num < 0);
2722
2723 for (i = 0; i < emit->num_arl_consts; ++i) {
2724 if (emit->arl_consts[i].arl_num == current_arl)
2725 break;
2726 }
2727 /* new entry */
2728 if (emit->num_arl_consts == i) {
2729 ++emit->num_arl_consts;
2730 }
2731 emit->arl_consts[i].number = (emit->arl_consts[i].number > num) ?
2732 num :
2733 emit->arl_consts[i].number;
2734 emit->arl_consts[i].arl_num = current_arl;
2735 return TRUE;
2736 }
2737
2738 static boolean
2739 pre_parse_instruction( struct svga_shader_emitter *emit,
2740 const struct tgsi_full_instruction *insn,
2741 int current_arl)
2742 {
2743 if (insn->Src[0].Register.Indirect &&
2744 insn->Src[0].Indirect.File == TGSI_FILE_ADDRESS) {
2745 const struct tgsi_full_src_register *reg = &insn->Src[0];
2746 if (reg->Register.Index < 0) {
2747 pre_parse_add_indirect(emit, reg->Register.Index, current_arl);
2748 }
2749 }
2750
2751 if (insn->Src[1].Register.Indirect &&
2752 insn->Src[1].Indirect.File == TGSI_FILE_ADDRESS) {
2753 const struct tgsi_full_src_register *reg = &insn->Src[1];
2754 if (reg->Register.Index < 0) {
2755 pre_parse_add_indirect(emit, reg->Register.Index, current_arl);
2756 }
2757 }
2758
2759 if (insn->Src[2].Register.Indirect &&
2760 insn->Src[2].Indirect.File == TGSI_FILE_ADDRESS) {
2761 const struct tgsi_full_src_register *reg = &insn->Src[2];
2762 if (reg->Register.Index < 0) {
2763 pre_parse_add_indirect(emit, reg->Register.Index, current_arl);
2764 }
2765 }
2766
2767 return TRUE;
2768 }
2769
2770 static boolean
2771 pre_parse_tokens( struct svga_shader_emitter *emit,
2772 const struct tgsi_token *tokens )
2773 {
2774 struct tgsi_parse_context parse;
2775 int current_arl = 0;
2776
2777 tgsi_parse_init( &parse, tokens );
2778
2779 while (!tgsi_parse_end_of_tokens( &parse )) {
2780 tgsi_parse_token( &parse );
2781 switch (parse.FullToken.Token.Type) {
2782 case TGSI_TOKEN_TYPE_IMMEDIATE:
2783 case TGSI_TOKEN_TYPE_DECLARATION:
2784 break;
2785 case TGSI_TOKEN_TYPE_INSTRUCTION:
2786 if (parse.FullToken.FullInstruction.Instruction.Opcode ==
2787 TGSI_OPCODE_ARL) {
2788 ++current_arl;
2789 }
2790 if (!pre_parse_instruction( emit, &parse.FullToken.FullInstruction,
2791 current_arl ))
2792 return FALSE;
2793 break;
2794 default:
2795 break;
2796 }
2797
2798 }
2799 return TRUE;
2800 }
2801
2802 static boolean svga_shader_emit_helpers( struct svga_shader_emitter *emit )
2803
2804 {
2805 if (needs_to_create_zero( emit )) {
2806 create_zero_immediate( emit );
2807 }
2808 if (needs_to_create_loop_const( emit )) {
2809 create_loop_const( emit );
2810 }
2811 if (needs_to_create_sincos_consts( emit )) {
2812 create_sincos_consts( emit );
2813 }
2814 if (needs_to_create_arl_consts( emit )) {
2815 create_arl_consts( emit );
2816 }
2817
2818 if (emit->unit == PIPE_SHADER_FRAGMENT) {
2819 if (!emit_ps_preamble( emit ))
2820 return FALSE;
2821
2822 if (emit->key.fkey.light_twoside) {
2823 if (!emit_light_twoside( emit ))
2824 return FALSE;
2825 }
2826 if (emit->emit_frontface) {
2827 if (!emit_frontface( emit ))
2828 return FALSE;
2829 }
2830 }
2831
2832 return TRUE;
2833 }
2834
2835 boolean svga_shader_emit_instructions( struct svga_shader_emitter *emit,
2836 const struct tgsi_token *tokens )
2837 {
2838 struct tgsi_parse_context parse;
2839 boolean ret = TRUE;
2840 boolean helpers_emitted = FALSE;
2841 unsigned line_nr = 0;
2842
2843 tgsi_parse_init( &parse, tokens );
2844 emit->internal_imm_count = 0;
2845
2846 if (emit->unit == PIPE_SHADER_VERTEX) {
2847 ret = emit_vs_preamble( emit );
2848 if (!ret)
2849 goto done;
2850 }
2851
2852 pre_parse_tokens(emit, tokens);
2853
2854 while (!tgsi_parse_end_of_tokens( &parse )) {
2855 tgsi_parse_token( &parse );
2856
2857 switch (parse.FullToken.Token.Type) {
2858 case TGSI_TOKEN_TYPE_IMMEDIATE:
2859 ret = svga_emit_immediate( emit, &parse.FullToken.FullImmediate );
2860 if (!ret)
2861 goto done;
2862 break;
2863
2864 case TGSI_TOKEN_TYPE_DECLARATION:
2865 if (emit->use_sm30)
2866 ret = svga_translate_decl_sm30( emit, &parse.FullToken.FullDeclaration );
2867 else
2868 ret = svga_translate_decl_sm20( emit, &parse.FullToken.FullDeclaration );
2869 if (!ret)
2870 goto done;
2871 break;
2872
2873 case TGSI_TOKEN_TYPE_INSTRUCTION:
2874 if (!helpers_emitted) {
2875 if (!svga_shader_emit_helpers( emit ))
2876 goto done;
2877 helpers_emitted = TRUE;
2878 }
2879 ret = svga_emit_instruction( emit,
2880 line_nr++,
2881 &parse.FullToken.FullInstruction );
2882 if (!ret)
2883 goto done;
2884 break;
2885 default:
2886 break;
2887 }
2888
2889 reset_temp_regs( emit );
2890 }
2891
2892 /* Need to terminate the current subroutine. Note that the
2893 * hardware doesn't tolerate shaders without sub-routines
2894 * terminating with RET+END.
2895 */
2896 if (!emit->in_main_func) {
2897 ret = emit_instruction( emit, inst_token( SVGA3DOP_RET ) );
2898 if (!ret)
2899 goto done;
2900 }
2901
2902 assert(emit->dynamic_branching_level == 0);
2903
2904 /* Need to terminate the whole shader:
2905 */
2906 ret = emit_instruction( emit, inst_token( SVGA3DOP_END ) );
2907 if (!ret)
2908 goto done;
2909
2910 done:
2911 assert(ret);
2912 tgsi_parse_free( &parse );
2913 return ret;
2914 }
2915