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svga: rename color output variables
[mesa.git] / src / gallium / drivers / svga / svga_tgsi_insn.c
1 /**********************************************************
2 * Copyright 2008-2009 VMware, Inc. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 **********************************************************/
25
26
27 #include "pipe/p_shader_tokens.h"
28 #include "tgsi/tgsi_dump.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/u_memory.h"
31 #include "util/u_math.h"
32
33 #include "svga_tgsi_emit.h"
34 #include "svga_context.h"
35
36
37 static boolean emit_vs_postamble( struct svga_shader_emitter *emit );
38 static boolean emit_ps_postamble( struct svga_shader_emitter *emit );
39
40
41 static unsigned
42 translate_opcode(uint opcode)
43 {
44 switch (opcode) {
45 case TGSI_OPCODE_ABS: return SVGA3DOP_ABS;
46 case TGSI_OPCODE_ADD: return SVGA3DOP_ADD;
47 case TGSI_OPCODE_DP2A: return SVGA3DOP_DP2ADD;
48 case TGSI_OPCODE_DP3: return SVGA3DOP_DP3;
49 case TGSI_OPCODE_DP4: return SVGA3DOP_DP4;
50 case TGSI_OPCODE_FRC: return SVGA3DOP_FRC;
51 case TGSI_OPCODE_MAD: return SVGA3DOP_MAD;
52 case TGSI_OPCODE_MAX: return SVGA3DOP_MAX;
53 case TGSI_OPCODE_MIN: return SVGA3DOP_MIN;
54 case TGSI_OPCODE_MOV: return SVGA3DOP_MOV;
55 case TGSI_OPCODE_MUL: return SVGA3DOP_MUL;
56 case TGSI_OPCODE_NOP: return SVGA3DOP_NOP;
57 case TGSI_OPCODE_NRM4: return SVGA3DOP_NRM;
58 default:
59 debug_printf("Unkown opcode %u\n", opcode);
60 assert( 0 );
61 return SVGA3DOP_LAST_INST;
62 }
63 }
64
65
66 static unsigned
67 translate_file(unsigned file)
68 {
69 switch (file) {
70 case TGSI_FILE_TEMPORARY: return SVGA3DREG_TEMP;
71 case TGSI_FILE_INPUT: return SVGA3DREG_INPUT;
72 case TGSI_FILE_OUTPUT: return SVGA3DREG_OUTPUT; /* VS3.0+ only */
73 case TGSI_FILE_IMMEDIATE: return SVGA3DREG_CONST;
74 case TGSI_FILE_CONSTANT: return SVGA3DREG_CONST;
75 case TGSI_FILE_SAMPLER: return SVGA3DREG_SAMPLER;
76 case TGSI_FILE_ADDRESS: return SVGA3DREG_ADDR;
77 default:
78 assert( 0 );
79 return SVGA3DREG_TEMP;
80 }
81 }
82
83
84 static SVGA3dShaderDestToken
85 translate_dst_register( struct svga_shader_emitter *emit,
86 const struct tgsi_full_instruction *insn,
87 unsigned idx )
88 {
89 const struct tgsi_full_dst_register *reg = &insn->Dst[idx];
90 SVGA3dShaderDestToken dest;
91
92 switch (reg->Register.File) {
93 case TGSI_FILE_OUTPUT:
94 /* Output registers encode semantic information in their name.
95 * Need to lookup a table built at decl time:
96 */
97 dest = emit->output_map[reg->Register.Index];
98 break;
99
100 default:
101 {
102 unsigned index = reg->Register.Index;
103 assert(index < SVGA3D_TEMPREG_MAX);
104 index = MIN2(index, SVGA3D_TEMPREG_MAX - 1);
105 dest = dst_register(translate_file(reg->Register.File), index);
106 }
107 break;
108 }
109
110 if (reg->Register.Indirect) {
111 debug_warning("Indirect indexing of dest registers is not supported!\n");
112 }
113
114 dest.mask = reg->Register.WriteMask;
115 assert(dest.mask);
116
117 if (insn->Instruction.Saturate)
118 dest.dstMod = SVGA3DDSTMOD_SATURATE;
119
120 return dest;
121 }
122
123
124 /**
125 * Apply a swizzle to a src_register, returning a new src_register
126 * Ex: swizzle(SRC.ZZYY, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_X, SWIZZLE_Y)
127 * would return SRC.YYZZ
128 */
129 static struct src_register
130 swizzle(struct src_register src,
131 unsigned x, unsigned y, unsigned z, unsigned w)
132 {
133 assert(x < 4);
134 assert(y < 4);
135 assert(z < 4);
136 assert(w < 4);
137 x = (src.base.swizzle >> (x * 2)) & 0x3;
138 y = (src.base.swizzle >> (y * 2)) & 0x3;
139 z = (src.base.swizzle >> (z * 2)) & 0x3;
140 w = (src.base.swizzle >> (w * 2)) & 0x3;
141
142 src.base.swizzle = TRANSLATE_SWIZZLE(x, y, z, w);
143
144 return src;
145 }
146
147
148 /**
149 * Apply a "scalar" swizzle to a src_register returning a new
150 * src_register where all the swizzle terms are the same.
151 * Ex: scalar(SRC.WZYX, SWIZZLE_Y) would return SRC.ZZZZ
152 */
153 static struct src_register
154 scalar(struct src_register src, unsigned comp)
155 {
156 assert(comp < 4);
157 return swizzle( src, comp, comp, comp, comp );
158 }
159
160
161 static boolean
162 svga_arl_needs_adjustment( const struct svga_shader_emitter *emit )
163 {
164 int i;
165
166 for (i = 0; i < emit->num_arl_consts; ++i) {
167 if (emit->arl_consts[i].arl_num == emit->current_arl)
168 return TRUE;
169 }
170 return FALSE;
171 }
172
173
174 static int
175 svga_arl_adjustment( const struct svga_shader_emitter *emit )
176 {
177 int i;
178
179 for (i = 0; i < emit->num_arl_consts; ++i) {
180 if (emit->arl_consts[i].arl_num == emit->current_arl)
181 return emit->arl_consts[i].number;
182 }
183 return 0;
184 }
185
186
187 static struct src_register
188 translate_src_register( const struct svga_shader_emitter *emit,
189 const struct tgsi_full_src_register *reg )
190 {
191 struct src_register src;
192
193 switch (reg->Register.File) {
194 case TGSI_FILE_INPUT:
195 /* Input registers are referred to by their semantic name rather
196 * than by index. Use the mapping build up from the decls:
197 */
198 src = emit->input_map[reg->Register.Index];
199 break;
200
201 case TGSI_FILE_IMMEDIATE:
202 /* Immediates are appended after TGSI constants in the D3D
203 * constant buffer.
204 */
205 src = src_register( translate_file( reg->Register.File ),
206 reg->Register.Index + emit->imm_start );
207 break;
208
209 default:
210 src = src_register( translate_file( reg->Register.File ),
211 reg->Register.Index );
212 break;
213 }
214
215 /* Indirect addressing.
216 */
217 if (reg->Register.Indirect) {
218 if (emit->unit == PIPE_SHADER_FRAGMENT) {
219 /* Pixel shaders have only loop registers for relative
220 * addressing into inputs. Ignore the redundant address
221 * register, the contents of aL should be in sync with it.
222 */
223 if (reg->Register.File == TGSI_FILE_INPUT) {
224 src.base.relAddr = 1;
225 src.indirect = src_token(SVGA3DREG_LOOP, 0);
226 }
227 }
228 else {
229 /* Constant buffers only.
230 */
231 if (reg->Register.File == TGSI_FILE_CONSTANT) {
232 /* we shift the offset towards the minimum */
233 if (svga_arl_needs_adjustment( emit )) {
234 src.base.num -= svga_arl_adjustment( emit );
235 }
236 src.base.relAddr = 1;
237
238 /* Not really sure what should go in the second token:
239 */
240 src.indirect = src_token( SVGA3DREG_ADDR,
241 reg->Indirect.Index );
242
243 src.indirect.swizzle = SWIZZLE_XXXX;
244 }
245 }
246 }
247
248 src = swizzle( src,
249 reg->Register.SwizzleX,
250 reg->Register.SwizzleY,
251 reg->Register.SwizzleZ,
252 reg->Register.SwizzleW );
253
254 /* src.mod isn't a bitfield, unfortunately:
255 * See tgsi_util_get_full_src_register_sign_mode for implementation details.
256 */
257 if (reg->Register.Absolute) {
258 if (reg->Register.Negate)
259 src.base.srcMod = SVGA3DSRCMOD_ABSNEG;
260 else
261 src.base.srcMod = SVGA3DSRCMOD_ABS;
262 }
263 else {
264 if (reg->Register.Negate)
265 src.base.srcMod = SVGA3DSRCMOD_NEG;
266 else
267 src.base.srcMod = SVGA3DSRCMOD_NONE;
268 }
269
270 return src;
271 }
272
273
274 /*
275 * Get a temporary register.
276 * Note: if we exceed the temporary register limit we just use
277 * register SVGA3D_TEMPREG_MAX - 1.
278 */
279 static SVGA3dShaderDestToken
280 get_temp( struct svga_shader_emitter *emit )
281 {
282 int i = emit->nr_hw_temp + emit->internal_temp_count++;
283 assert(i < SVGA3D_TEMPREG_MAX);
284 i = MIN2(i, SVGA3D_TEMPREG_MAX - 1);
285 return dst_register( SVGA3DREG_TEMP, i );
286 }
287
288
289 /**
290 * Release a single temp. Currently only effective if it was the last
291 * allocated temp, otherwise release will be delayed until the next
292 * call to reset_temp_regs().
293 */
294 static void
295 release_temp( struct svga_shader_emitter *emit,
296 SVGA3dShaderDestToken temp )
297 {
298 if (temp.num == emit->internal_temp_count - 1)
299 emit->internal_temp_count--;
300 }
301
302
303 static void
304 reset_temp_regs(struct svga_shader_emitter *emit)
305 {
306 emit->internal_temp_count = 0;
307 }
308
309
310 /** Emit bytecode for a src_register */
311 static boolean
312 emit_src(struct svga_shader_emitter *emit, const struct src_register src)
313 {
314 if (src.base.relAddr) {
315 assert(src.base.reserved0);
316 assert(src.indirect.reserved0);
317 return (svga_shader_emit_dword( emit, src.base.value ) &&
318 svga_shader_emit_dword( emit, src.indirect.value ));
319 }
320 else {
321 assert(src.base.reserved0);
322 return svga_shader_emit_dword( emit, src.base.value );
323 }
324 }
325
326
327 /** Emit bytecode for a dst_register */
328 static boolean
329 emit_dst(struct svga_shader_emitter *emit, SVGA3dShaderDestToken dest)
330 {
331 assert(dest.reserved0);
332 assert(dest.mask);
333 return svga_shader_emit_dword( emit, dest.value );
334 }
335
336
337 /** Emit bytecode for a 1-operand instruction */
338 static boolean
339 emit_op1(struct svga_shader_emitter *emit,
340 SVGA3dShaderInstToken inst,
341 SVGA3dShaderDestToken dest,
342 struct src_register src0)
343 {
344 return (emit_instruction(emit, inst) &&
345 emit_dst(emit, dest) &&
346 emit_src(emit, src0));
347 }
348
349
350 /** Emit bytecode for a 2-operand instruction */
351 static boolean
352 emit_op2(struct svga_shader_emitter *emit,
353 SVGA3dShaderInstToken inst,
354 SVGA3dShaderDestToken dest,
355 struct src_register src0,
356 struct src_register src1)
357 {
358 return (emit_instruction(emit, inst) &&
359 emit_dst(emit, dest) &&
360 emit_src(emit, src0) &&
361 emit_src(emit, src1));
362 }
363
364
365 /** Emit bytecode for a 3-operand instruction */
366 static boolean
367 emit_op3(struct svga_shader_emitter *emit,
368 SVGA3dShaderInstToken inst,
369 SVGA3dShaderDestToken dest,
370 struct src_register src0,
371 struct src_register src1,
372 struct src_register src2)
373 {
374 return (emit_instruction(emit, inst) &&
375 emit_dst(emit, dest) &&
376 emit_src(emit, src0) &&
377 emit_src(emit, src1) &&
378 emit_src(emit, src2));
379 }
380
381
382 /** Emit bytecode for a 4-operand instruction */
383 static boolean
384 emit_op4(struct svga_shader_emitter *emit,
385 SVGA3dShaderInstToken inst,
386 SVGA3dShaderDestToken dest,
387 struct src_register src0,
388 struct src_register src1,
389 struct src_register src2,
390 struct src_register src3)
391 {
392 return (emit_instruction(emit, inst) &&
393 emit_dst(emit, dest) &&
394 emit_src(emit, src0) &&
395 emit_src(emit, src1) &&
396 emit_src(emit, src2) &&
397 emit_src(emit, src3));
398 }
399
400
401 /**
402 * Apply the absolute value modifier to the given src_register, returning
403 * a new src_register.
404 */
405 static struct src_register
406 absolute(struct src_register src)
407 {
408 src.base.srcMod = SVGA3DSRCMOD_ABS;
409 return src;
410 }
411
412
413 /**
414 * Apply the negation modifier to the given src_register, returning
415 * a new src_register.
416 */
417 static struct src_register
418 negate(struct src_register src)
419 {
420 switch (src.base.srcMod) {
421 case SVGA3DSRCMOD_ABS:
422 src.base.srcMod = SVGA3DSRCMOD_ABSNEG;
423 break;
424 case SVGA3DSRCMOD_ABSNEG:
425 src.base.srcMod = SVGA3DSRCMOD_ABS;
426 break;
427 case SVGA3DSRCMOD_NEG:
428 src.base.srcMod = SVGA3DSRCMOD_NONE;
429 break;
430 case SVGA3DSRCMOD_NONE:
431 src.base.srcMod = SVGA3DSRCMOD_NEG;
432 break;
433 }
434 return src;
435 }
436
437
438
439 /* Replace the src with the temporary specified in the dst, but copying
440 * only the necessary channels, and preserving the original swizzle (which is
441 * important given that several opcodes have constraints in the allowed
442 * swizzles).
443 */
444 static boolean
445 emit_repl(struct svga_shader_emitter *emit,
446 SVGA3dShaderDestToken dst,
447 struct src_register *src0)
448 {
449 unsigned src0_swizzle;
450 unsigned chan;
451
452 assert(SVGA3dShaderGetRegType(dst.value) == SVGA3DREG_TEMP);
453
454 src0_swizzle = src0->base.swizzle;
455
456 dst.mask = 0;
457 for (chan = 0; chan < 4; ++chan) {
458 unsigned swizzle = (src0_swizzle >> (chan *2)) & 0x3;
459 dst.mask |= 1 << swizzle;
460 }
461 assert(dst.mask);
462
463 src0->base.swizzle = SVGA3DSWIZZLE_NONE;
464
465 if (!emit_op1( emit, inst_token( SVGA3DOP_MOV ), dst, *src0 ))
466 return FALSE;
467
468 *src0 = src( dst );
469 src0->base.swizzle = src0_swizzle;
470
471 return TRUE;
472 }
473
474
475 static boolean
476 submit_op0(struct svga_shader_emitter *emit,
477 SVGA3dShaderInstToken inst,
478 SVGA3dShaderDestToken dest)
479 {
480 return (emit_instruction( emit, inst ) &&
481 emit_dst( emit, dest ));
482 }
483
484
485 static boolean
486 submit_op1(struct svga_shader_emitter *emit,
487 SVGA3dShaderInstToken inst,
488 SVGA3dShaderDestToken dest,
489 struct src_register src0)
490 {
491 return emit_op1( emit, inst, dest, src0 );
492 }
493
494
495 /**
496 * SVGA shaders may not refer to >1 constant register in a single
497 * instruction. This function checks for that usage and inserts a
498 * move to temporary if detected.
499 *
500 * The same applies to input registers -- at most a single input
501 * register may be read by any instruction.
502 */
503 static boolean
504 submit_op2(struct svga_shader_emitter *emit,
505 SVGA3dShaderInstToken inst,
506 SVGA3dShaderDestToken dest,
507 struct src_register src0,
508 struct src_register src1)
509 {
510 SVGA3dShaderDestToken temp;
511 SVGA3dShaderRegType type0, type1;
512 boolean need_temp = FALSE;
513
514 temp.value = 0;
515 type0 = SVGA3dShaderGetRegType( src0.base.value );
516 type1 = SVGA3dShaderGetRegType( src1.base.value );
517
518 if (type0 == SVGA3DREG_CONST &&
519 type1 == SVGA3DREG_CONST &&
520 src0.base.num != src1.base.num)
521 need_temp = TRUE;
522
523 if (type0 == SVGA3DREG_INPUT &&
524 type1 == SVGA3DREG_INPUT &&
525 src0.base.num != src1.base.num)
526 need_temp = TRUE;
527
528 if (need_temp) {
529 temp = get_temp( emit );
530
531 if (!emit_repl( emit, temp, &src0 ))
532 return FALSE;
533 }
534
535 if (!emit_op2( emit, inst, dest, src0, src1 ))
536 return FALSE;
537
538 if (need_temp)
539 release_temp( emit, temp );
540
541 return TRUE;
542 }
543
544
545 /**
546 * SVGA shaders may not refer to >1 constant register in a single
547 * instruction. This function checks for that usage and inserts a
548 * move to temporary if detected.
549 */
550 static boolean
551 submit_op3(struct svga_shader_emitter *emit,
552 SVGA3dShaderInstToken inst,
553 SVGA3dShaderDestToken dest,
554 struct src_register src0,
555 struct src_register src1,
556 struct src_register src2)
557 {
558 SVGA3dShaderDestToken temp0;
559 SVGA3dShaderDestToken temp1;
560 boolean need_temp0 = FALSE;
561 boolean need_temp1 = FALSE;
562 SVGA3dShaderRegType type0, type1, type2;
563
564 temp0.value = 0;
565 temp1.value = 0;
566 type0 = SVGA3dShaderGetRegType( src0.base.value );
567 type1 = SVGA3dShaderGetRegType( src1.base.value );
568 type2 = SVGA3dShaderGetRegType( src2.base.value );
569
570 if (inst.op != SVGA3DOP_SINCOS) {
571 if (type0 == SVGA3DREG_CONST &&
572 ((type1 == SVGA3DREG_CONST && src0.base.num != src1.base.num) ||
573 (type2 == SVGA3DREG_CONST && src0.base.num != src2.base.num)))
574 need_temp0 = TRUE;
575
576 if (type1 == SVGA3DREG_CONST &&
577 (type2 == SVGA3DREG_CONST && src1.base.num != src2.base.num))
578 need_temp1 = TRUE;
579 }
580
581 if (type0 == SVGA3DREG_INPUT &&
582 ((type1 == SVGA3DREG_INPUT && src0.base.num != src1.base.num) ||
583 (type2 == SVGA3DREG_INPUT && src0.base.num != src2.base.num)))
584 need_temp0 = TRUE;
585
586 if (type1 == SVGA3DREG_INPUT &&
587 (type2 == SVGA3DREG_INPUT && src1.base.num != src2.base.num))
588 need_temp1 = TRUE;
589
590 if (need_temp0) {
591 temp0 = get_temp( emit );
592
593 if (!emit_repl( emit, temp0, &src0 ))
594 return FALSE;
595 }
596
597 if (need_temp1) {
598 temp1 = get_temp( emit );
599
600 if (!emit_repl( emit, temp1, &src1 ))
601 return FALSE;
602 }
603
604 if (!emit_op3( emit, inst, dest, src0, src1, src2 ))
605 return FALSE;
606
607 if (need_temp1)
608 release_temp( emit, temp1 );
609 if (need_temp0)
610 release_temp( emit, temp0 );
611 return TRUE;
612 }
613
614
615 /**
616 * SVGA shaders may not refer to >1 constant register in a single
617 * instruction. This function checks for that usage and inserts a
618 * move to temporary if detected.
619 */
620 static boolean
621 submit_op4(struct svga_shader_emitter *emit,
622 SVGA3dShaderInstToken inst,
623 SVGA3dShaderDestToken dest,
624 struct src_register src0,
625 struct src_register src1,
626 struct src_register src2,
627 struct src_register src3)
628 {
629 SVGA3dShaderDestToken temp0;
630 SVGA3dShaderDestToken temp3;
631 boolean need_temp0 = FALSE;
632 boolean need_temp3 = FALSE;
633 SVGA3dShaderRegType type0, type1, type2, type3;
634
635 temp0.value = 0;
636 temp3.value = 0;
637 type0 = SVGA3dShaderGetRegType( src0.base.value );
638 type1 = SVGA3dShaderGetRegType( src1.base.value );
639 type2 = SVGA3dShaderGetRegType( src2.base.value );
640 type3 = SVGA3dShaderGetRegType( src2.base.value );
641
642 /* Make life a little easier - this is only used by the TXD
643 * instruction which is guaranteed not to have a constant/input reg
644 * in one slot at least:
645 */
646 assert(type1 == SVGA3DREG_SAMPLER);
647
648 if (type0 == SVGA3DREG_CONST &&
649 ((type3 == SVGA3DREG_CONST && src0.base.num != src3.base.num) ||
650 (type2 == SVGA3DREG_CONST && src0.base.num != src2.base.num)))
651 need_temp0 = TRUE;
652
653 if (type3 == SVGA3DREG_CONST &&
654 (type2 == SVGA3DREG_CONST && src3.base.num != src2.base.num))
655 need_temp3 = TRUE;
656
657 if (type0 == SVGA3DREG_INPUT &&
658 ((type3 == SVGA3DREG_INPUT && src0.base.num != src3.base.num) ||
659 (type2 == SVGA3DREG_INPUT && src0.base.num != src2.base.num)))
660 need_temp0 = TRUE;
661
662 if (type3 == SVGA3DREG_INPUT &&
663 (type2 == SVGA3DREG_INPUT && src3.base.num != src2.base.num))
664 need_temp3 = TRUE;
665
666 if (need_temp0) {
667 temp0 = get_temp( emit );
668
669 if (!emit_repl( emit, temp0, &src0 ))
670 return FALSE;
671 }
672
673 if (need_temp3) {
674 temp3 = get_temp( emit );
675
676 if (!emit_repl( emit, temp3, &src3 ))
677 return FALSE;
678 }
679
680 if (!emit_op4( emit, inst, dest, src0, src1, src2, src3 ))
681 return FALSE;
682
683 if (need_temp3)
684 release_temp( emit, temp3 );
685 if (need_temp0)
686 release_temp( emit, temp0 );
687 return TRUE;
688 }
689
690
691 /**
692 * Do the src and dest registers refer to the same register?
693 */
694 static boolean
695 alias_src_dst(struct src_register src,
696 SVGA3dShaderDestToken dst)
697 {
698 if (src.base.num != dst.num)
699 return FALSE;
700
701 if (SVGA3dShaderGetRegType(dst.value) !=
702 SVGA3dShaderGetRegType(src.base.value))
703 return FALSE;
704
705 return TRUE;
706 }
707
708
709 static boolean
710 submit_lrp(struct svga_shader_emitter *emit,
711 SVGA3dShaderDestToken dst,
712 struct src_register src0,
713 struct src_register src1,
714 struct src_register src2)
715 {
716 SVGA3dShaderDestToken tmp;
717 boolean need_dst_tmp = FALSE;
718
719 /* The dst reg must be a temporary, and not be the same as src0 or src2 */
720 if (SVGA3dShaderGetRegType(dst.value) != SVGA3DREG_TEMP ||
721 alias_src_dst(src0, dst) ||
722 alias_src_dst(src2, dst))
723 need_dst_tmp = TRUE;
724
725 if (need_dst_tmp) {
726 tmp = get_temp( emit );
727 tmp.mask = dst.mask;
728 }
729 else {
730 tmp = dst;
731 }
732
733 if (!submit_op3(emit, inst_token( SVGA3DOP_LRP ), tmp, src0, src1, src2))
734 return FALSE;
735
736 if (need_dst_tmp) {
737 if (!submit_op1(emit, inst_token( SVGA3DOP_MOV ), dst, src( tmp )))
738 return FALSE;
739 }
740
741 return TRUE;
742 }
743
744
745 static boolean
746 emit_def_const(struct svga_shader_emitter *emit,
747 SVGA3dShaderConstType type,
748 unsigned idx, float a, float b, float c, float d)
749 {
750 SVGA3DOpDefArgs def;
751 SVGA3dShaderInstToken opcode;
752
753 switch (type) {
754 case SVGA3D_CONST_TYPE_FLOAT:
755 opcode = inst_token( SVGA3DOP_DEF );
756 def.dst = dst_register( SVGA3DREG_CONST, idx );
757 def.constValues[0] = a;
758 def.constValues[1] = b;
759 def.constValues[2] = c;
760 def.constValues[3] = d;
761 break;
762 case SVGA3D_CONST_TYPE_INT:
763 opcode = inst_token( SVGA3DOP_DEFI );
764 def.dst = dst_register( SVGA3DREG_CONSTINT, idx );
765 def.constIValues[0] = (int)a;
766 def.constIValues[1] = (int)b;
767 def.constIValues[2] = (int)c;
768 def.constIValues[3] = (int)d;
769 break;
770 default:
771 assert(0);
772 opcode = inst_token( SVGA3DOP_NOP );
773 break;
774 }
775
776 if (!emit_instruction(emit, opcode) ||
777 !svga_shader_emit_dwords( emit, def.values, Elements(def.values)))
778 return FALSE;
779
780 return TRUE;
781 }
782
783
784 static boolean
785 create_zero_immediate( struct svga_shader_emitter *emit )
786 {
787 unsigned idx = emit->nr_hw_float_const++;
788
789 /* Emit the constant (0, 0.5, -1, 1) and use swizzling to generate
790 * other useful vectors.
791 */
792 if (!emit_def_const( emit, SVGA3D_CONST_TYPE_FLOAT,
793 idx, 0, 0.5, -1, 1 ))
794 return FALSE;
795
796 emit->zero_immediate_idx = idx;
797 emit->created_zero_immediate = TRUE;
798
799 return TRUE;
800 }
801
802
803 static boolean
804 create_loop_const( struct svga_shader_emitter *emit )
805 {
806 unsigned idx = emit->nr_hw_int_const++;
807
808 if (!emit_def_const( emit, SVGA3D_CONST_TYPE_INT, idx,
809 255, /* iteration count */
810 0, /* initial value */
811 1, /* step size */
812 0 /* not used, must be 0 */))
813 return FALSE;
814
815 emit->loop_const_idx = idx;
816 emit->created_loop_const = TRUE;
817
818 return TRUE;
819 }
820
821 static boolean
822 create_arl_consts( struct svga_shader_emitter *emit )
823 {
824 int i;
825
826 for (i = 0; i < emit->num_arl_consts; i += 4) {
827 int j;
828 unsigned idx = emit->nr_hw_float_const++;
829 float vals[4];
830 for (j = 0; j < 4 && (j + i) < emit->num_arl_consts; ++j) {
831 vals[j] = (float) emit->arl_consts[i + j].number;
832 emit->arl_consts[i + j].idx = idx;
833 switch (j) {
834 case 0:
835 emit->arl_consts[i + 0].swizzle = TGSI_SWIZZLE_X;
836 break;
837 case 1:
838 emit->arl_consts[i + 0].swizzle = TGSI_SWIZZLE_Y;
839 break;
840 case 2:
841 emit->arl_consts[i + 0].swizzle = TGSI_SWIZZLE_Z;
842 break;
843 case 3:
844 emit->arl_consts[i + 0].swizzle = TGSI_SWIZZLE_W;
845 break;
846 }
847 }
848 while (j < 4)
849 vals[j++] = 0;
850
851 if (!emit_def_const( emit, SVGA3D_CONST_TYPE_FLOAT, idx,
852 vals[0], vals[1],
853 vals[2], vals[3]))
854 return FALSE;
855 }
856
857 return TRUE;
858 }
859
860
861 /**
862 * Return the register which holds the pixel shaders front/back-
863 * facing value.
864 */
865 static struct src_register
866 get_vface( struct svga_shader_emitter *emit )
867 {
868 assert(emit->emitted_vface);
869 return src_register(SVGA3DREG_MISCTYPE, SVGA3DMISCREG_FACE);
870 }
871
872
873 /**
874 * returns {0, 0, 0, 1} immediate
875 */
876 static struct src_register
877 get_zero_immediate( struct svga_shader_emitter *emit )
878 {
879 assert(emit->created_zero_immediate);
880 assert(emit->zero_immediate_idx >= 0);
881 return swizzle(src_register( SVGA3DREG_CONST,
882 emit->zero_immediate_idx),
883 0, 0, 0, 3);
884 }
885
886
887 /**
888 * returns {1, 1, 1, -1} immediate
889 */
890 static struct src_register
891 get_pos_neg_one_immediate( struct svga_shader_emitter *emit )
892 {
893 assert(emit->created_zero_immediate);
894 assert(emit->zero_immediate_idx >= 0);
895 return swizzle(src_register( SVGA3DREG_CONST,
896 emit->zero_immediate_idx),
897 3, 3, 3, 2);
898 }
899
900
901 /**
902 * returns {0.5, 0.5, 0.5, 0.5} immediate
903 */
904 static struct src_register
905 get_half_immediate( struct svga_shader_emitter *emit )
906 {
907 assert(emit->created_zero_immediate);
908 assert(emit->zero_immediate_idx >= 0);
909 return swizzle(src_register(SVGA3DREG_CONST, emit->zero_immediate_idx),
910 1, 1, 1, 1);
911 }
912
913
914 /**
915 * returns the loop const
916 */
917 static struct src_register
918 get_loop_const( struct svga_shader_emitter *emit )
919 {
920 assert(emit->created_loop_const);
921 assert(emit->loop_const_idx >= 0);
922 return src_register( SVGA3DREG_CONSTINT,
923 emit->loop_const_idx );
924 }
925
926
927 static struct src_register
928 get_fake_arl_const( struct svga_shader_emitter *emit )
929 {
930 struct src_register reg;
931 int idx = 0, swizzle = 0, i;
932
933 for (i = 0; i < emit->num_arl_consts; ++ i) {
934 if (emit->arl_consts[i].arl_num == emit->current_arl) {
935 idx = emit->arl_consts[i].idx;
936 swizzle = emit->arl_consts[i].swizzle;
937 }
938 }
939
940 reg = src_register( SVGA3DREG_CONST, idx );
941 return scalar(reg, swizzle);
942 }
943
944
945 /**
946 * Return the register which holds the current dimenions of the
947 * texture bound to the given sampler
948 */
949 static struct src_register
950 get_tex_dimensions( struct svga_shader_emitter *emit, int sampler_num )
951 {
952 int idx;
953 struct src_register reg;
954
955 /* the width/height indexes start right after constants */
956 idx = emit->key.fkey.tex[sampler_num].width_height_idx +
957 emit->info.file_max[TGSI_FILE_CONSTANT] + 1;
958
959 reg = src_register( SVGA3DREG_CONST, idx );
960 return reg;
961 }
962
963
964 static boolean
965 emit_fake_arl(struct svga_shader_emitter *emit,
966 const struct tgsi_full_instruction *insn)
967 {
968 const struct src_register src0 =
969 translate_src_register(emit, &insn->Src[0] );
970 struct src_register src1 = get_fake_arl_const( emit );
971 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
972 SVGA3dShaderDestToken tmp = get_temp( emit );
973
974 if (!submit_op1(emit, inst_token( SVGA3DOP_MOV ), tmp, src0))
975 return FALSE;
976
977 if (!submit_op2( emit, inst_token( SVGA3DOP_ADD ), tmp, src( tmp ),
978 src1))
979 return FALSE;
980
981 /* replicate the original swizzle */
982 src1 = src(tmp);
983 src1.base.swizzle = src0.base.swizzle;
984
985 return submit_op1( emit, inst_token( SVGA3DOP_MOVA ),
986 dst, src1 );
987 }
988
989
990 static boolean
991 emit_if(struct svga_shader_emitter *emit,
992 const struct tgsi_full_instruction *insn)
993 {
994 struct src_register src0 =
995 translate_src_register(emit, &insn->Src[0]);
996 struct src_register zero = get_zero_immediate( emit );
997 SVGA3dShaderInstToken if_token = inst_token( SVGA3DOP_IFC );
998
999 if_token.control = SVGA3DOPCOMPC_NE;
1000 zero = scalar(zero, TGSI_SWIZZLE_X);
1001
1002 if (SVGA3dShaderGetRegType(src0.base.value) == SVGA3DREG_CONST) {
1003 /*
1004 * Max different constant registers readable per IFC instruction is 1.
1005 */
1006 SVGA3dShaderDestToken tmp = get_temp( emit );
1007
1008 if (!submit_op1(emit, inst_token( SVGA3DOP_MOV ), tmp, src0))
1009 return FALSE;
1010
1011 src0 = scalar(src( tmp ), TGSI_SWIZZLE_X);
1012 }
1013
1014 emit->dynamic_branching_level++;
1015
1016 return (emit_instruction( emit, if_token ) &&
1017 emit_src( emit, src0 ) &&
1018 emit_src( emit, zero ) );
1019 }
1020
1021
1022 static boolean
1023 emit_endif(struct svga_shader_emitter *emit,
1024 const struct tgsi_full_instruction *insn)
1025 {
1026 emit->dynamic_branching_level--;
1027
1028 return emit_instruction(emit, inst_token(SVGA3DOP_ENDIF));
1029 }
1030
1031
1032 static boolean
1033 emit_else(struct svga_shader_emitter *emit,
1034 const struct tgsi_full_instruction *insn)
1035 {
1036 return emit_instruction(emit, inst_token(SVGA3DOP_ELSE));
1037 }
1038
1039
1040 /**
1041 * Translate the following TGSI FLR instruction.
1042 * FLR DST, SRC
1043 * To the following SVGA3D instruction sequence.
1044 * FRC TMP, SRC
1045 * SUB DST, SRC, TMP
1046 */
1047 static boolean
1048 emit_floor(struct svga_shader_emitter *emit,
1049 const struct tgsi_full_instruction *insn )
1050 {
1051 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
1052 const struct src_register src0 =
1053 translate_src_register(emit, &insn->Src[0] );
1054 SVGA3dShaderDestToken temp = get_temp( emit );
1055
1056 /* FRC TMP, SRC */
1057 if (!submit_op1( emit, inst_token( SVGA3DOP_FRC ), temp, src0 ))
1058 return FALSE;
1059
1060 /* SUB DST, SRC, TMP */
1061 if (!submit_op2( emit, inst_token( SVGA3DOP_ADD ), dst, src0,
1062 negate( src( temp ) ) ))
1063 return FALSE;
1064
1065 return TRUE;
1066 }
1067
1068
1069 /**
1070 * Translate the following TGSI CEIL instruction.
1071 * CEIL DST, SRC
1072 * To the following SVGA3D instruction sequence.
1073 * FRC TMP, -SRC
1074 * ADD DST, SRC, TMP
1075 */
1076 static boolean
1077 emit_ceil(struct svga_shader_emitter *emit,
1078 const struct tgsi_full_instruction *insn)
1079 {
1080 SVGA3dShaderDestToken dst = translate_dst_register(emit, insn, 0);
1081 const struct src_register src0 =
1082 translate_src_register(emit, &insn->Src[0]);
1083 SVGA3dShaderDestToken temp = get_temp(emit);
1084
1085 /* FRC TMP, -SRC */
1086 if (!submit_op1(emit, inst_token(SVGA3DOP_FRC), temp, negate(src0)))
1087 return FALSE;
1088
1089 /* ADD DST, SRC, TMP */
1090 if (!submit_op2(emit, inst_token(SVGA3DOP_ADD), dst, src0, src(temp)))
1091 return FALSE;
1092
1093 return TRUE;
1094 }
1095
1096
1097 /**
1098 * Translate the following TGSI DIV instruction.
1099 * DIV DST.xy, SRC0, SRC1
1100 * To the following SVGA3D instruction sequence.
1101 * RCP TMP.x, SRC1.xxxx
1102 * RCP TMP.y, SRC1.yyyy
1103 * MUL DST.xy, SRC0, TMP
1104 */
1105 static boolean
1106 emit_div(struct svga_shader_emitter *emit,
1107 const struct tgsi_full_instruction *insn )
1108 {
1109 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
1110 const struct src_register src0 =
1111 translate_src_register(emit, &insn->Src[0] );
1112 const struct src_register src1 =
1113 translate_src_register(emit, &insn->Src[1] );
1114 SVGA3dShaderDestToken temp = get_temp( emit );
1115 int i;
1116
1117 /* For each enabled element, perform a RCP instruction. Note that
1118 * RCP is scalar in SVGA3D:
1119 */
1120 for (i = 0; i < 4; i++) {
1121 unsigned channel = 1 << i;
1122 if (dst.mask & channel) {
1123 /* RCP TMP.?, SRC1.???? */
1124 if (!submit_op1( emit, inst_token( SVGA3DOP_RCP ),
1125 writemask(temp, channel),
1126 scalar(src1, i) ))
1127 return FALSE;
1128 }
1129 }
1130
1131 /* Vector mul:
1132 * MUL DST, SRC0, TMP
1133 */
1134 if (!submit_op2( emit, inst_token( SVGA3DOP_MUL ), dst, src0,
1135 src( temp ) ))
1136 return FALSE;
1137
1138 return TRUE;
1139 }
1140
1141
1142 /**
1143 * Translate the following TGSI DP2 instruction.
1144 * DP2 DST, SRC1, SRC2
1145 * To the following SVGA3D instruction sequence.
1146 * MUL TMP, SRC1, SRC2
1147 * ADD DST, TMP.xxxx, TMP.yyyy
1148 */
1149 static boolean
1150 emit_dp2(struct svga_shader_emitter *emit,
1151 const struct tgsi_full_instruction *insn )
1152 {
1153 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
1154 const struct src_register src0 =
1155 translate_src_register(emit, &insn->Src[0]);
1156 const struct src_register src1 =
1157 translate_src_register(emit, &insn->Src[1]);
1158 SVGA3dShaderDestToken temp = get_temp( emit );
1159 struct src_register temp_src0, temp_src1;
1160
1161 /* MUL TMP, SRC1, SRC2 */
1162 if (!submit_op2( emit, inst_token( SVGA3DOP_MUL ), temp, src0, src1 ))
1163 return FALSE;
1164
1165 temp_src0 = scalar(src( temp ), TGSI_SWIZZLE_X);
1166 temp_src1 = scalar(src( temp ), TGSI_SWIZZLE_Y);
1167
1168 /* ADD DST, TMP.xxxx, TMP.yyyy */
1169 if (!submit_op2( emit, inst_token( SVGA3DOP_ADD ), dst,
1170 temp_src0, temp_src1 ))
1171 return FALSE;
1172
1173 return TRUE;
1174 }
1175
1176
1177 /**
1178 * Translate the following TGSI DPH instruction.
1179 * DPH DST, SRC1, SRC2
1180 * To the following SVGA3D instruction sequence.
1181 * DP3 TMP, SRC1, SRC2
1182 * ADD DST, TMP, SRC2.wwww
1183 */
1184 static boolean
1185 emit_dph(struct svga_shader_emitter *emit,
1186 const struct tgsi_full_instruction *insn )
1187 {
1188 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
1189 const struct src_register src0 = translate_src_register(
1190 emit, &insn->Src[0] );
1191 struct src_register src1 =
1192 translate_src_register(emit, &insn->Src[1]);
1193 SVGA3dShaderDestToken temp = get_temp( emit );
1194
1195 /* DP3 TMP, SRC1, SRC2 */
1196 if (!submit_op2( emit, inst_token( SVGA3DOP_DP3 ), temp, src0, src1 ))
1197 return FALSE;
1198
1199 src1 = scalar(src1, TGSI_SWIZZLE_W);
1200
1201 /* ADD DST, TMP, SRC2.wwww */
1202 if (!submit_op2( emit, inst_token( SVGA3DOP_ADD ), dst,
1203 src( temp ), src1 ))
1204 return FALSE;
1205
1206 return TRUE;
1207 }
1208
1209
1210 /**
1211 * Translate the following TGSI DST instruction.
1212 * NRM DST, SRC
1213 * To the following SVGA3D instruction sequence.
1214 * DP3 TMP, SRC, SRC
1215 * RSQ TMP, TMP
1216 * MUL DST, SRC, TMP
1217 */
1218 static boolean
1219 emit_nrm(struct svga_shader_emitter *emit,
1220 const struct tgsi_full_instruction *insn)
1221 {
1222 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
1223 const struct src_register src0 =
1224 translate_src_register(emit, &insn->Src[0]);
1225 SVGA3dShaderDestToken temp = get_temp( emit );
1226
1227 /* DP3 TMP, SRC, SRC */
1228 if (!submit_op2( emit, inst_token( SVGA3DOP_DP3 ), temp, src0, src0 ))
1229 return FALSE;
1230
1231 /* RSQ TMP, TMP */
1232 if (!submit_op1( emit, inst_token( SVGA3DOP_RSQ ), temp, src( temp )))
1233 return FALSE;
1234
1235 /* MUL DST, SRC, TMP */
1236 if (!submit_op2( emit, inst_token( SVGA3DOP_MUL ), dst,
1237 src0, src( temp )))
1238 return FALSE;
1239
1240 return TRUE;
1241 }
1242
1243
1244 static boolean
1245 do_emit_sincos(struct svga_shader_emitter *emit,
1246 SVGA3dShaderDestToken dst,
1247 struct src_register src0)
1248 {
1249 src0 = scalar(src0, TGSI_SWIZZLE_X);
1250 return submit_op1(emit, inst_token(SVGA3DOP_SINCOS), dst, src0);
1251 }
1252
1253
1254 static boolean
1255 emit_sincos(struct svga_shader_emitter *emit,
1256 const struct tgsi_full_instruction *insn)
1257 {
1258 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
1259 struct src_register src0 = translate_src_register(emit, &insn->Src[0]);
1260 SVGA3dShaderDestToken temp = get_temp( emit );
1261
1262 /* SCS TMP SRC */
1263 if (!do_emit_sincos(emit, writemask(temp, TGSI_WRITEMASK_XY), src0 ))
1264 return FALSE;
1265
1266 /* MOV DST TMP */
1267 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ), dst, src( temp ) ))
1268 return FALSE;
1269
1270 return TRUE;
1271 }
1272
1273
1274 /**
1275 * SCS TMP SRC
1276 * MOV DST TMP.yyyy
1277 */
1278 static boolean
1279 emit_sin(struct svga_shader_emitter *emit,
1280 const struct tgsi_full_instruction *insn )
1281 {
1282 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
1283 struct src_register src0 =
1284 translate_src_register(emit, &insn->Src[0] );
1285 SVGA3dShaderDestToken temp = get_temp( emit );
1286
1287 /* SCS TMP SRC */
1288 if (!do_emit_sincos(emit, writemask(temp, TGSI_WRITEMASK_Y), src0))
1289 return FALSE;
1290
1291 src0 = scalar(src( temp ), TGSI_SWIZZLE_Y);
1292
1293 /* MOV DST TMP.yyyy */
1294 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ), dst, src0 ))
1295 return FALSE;
1296
1297 return TRUE;
1298 }
1299
1300 /*
1301 * SCS TMP SRC
1302 * MOV DST TMP.xxxx
1303 */
1304 static boolean
1305 emit_cos(struct svga_shader_emitter *emit,
1306 const struct tgsi_full_instruction *insn)
1307 {
1308 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
1309 struct src_register src0 =
1310 translate_src_register(emit, &insn->Src[0] );
1311 SVGA3dShaderDestToken temp = get_temp( emit );
1312
1313 /* SCS TMP SRC */
1314 if (!do_emit_sincos( emit, writemask(temp, TGSI_WRITEMASK_X), src0 ))
1315 return FALSE;
1316
1317 src0 = scalar(src( temp ), TGSI_SWIZZLE_X);
1318
1319 /* MOV DST TMP.xxxx */
1320 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ), dst, src0 ))
1321 return FALSE;
1322
1323 return TRUE;
1324 }
1325
1326
1327 static boolean
1328 emit_ssg(struct svga_shader_emitter *emit,
1329 const struct tgsi_full_instruction *insn)
1330 {
1331 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
1332 struct src_register src0 =
1333 translate_src_register(emit, &insn->Src[0] );
1334 SVGA3dShaderDestToken temp0 = get_temp( emit );
1335 SVGA3dShaderDestToken temp1 = get_temp( emit );
1336 struct src_register zero, one;
1337
1338 if (emit->unit == PIPE_SHADER_VERTEX) {
1339 /* SGN DST, SRC0, TMP0, TMP1 */
1340 return submit_op3( emit, inst_token( SVGA3DOP_SGN ), dst, src0,
1341 src( temp0 ), src( temp1 ) );
1342 }
1343
1344 zero = get_zero_immediate( emit );
1345 one = scalar( zero, TGSI_SWIZZLE_W );
1346 zero = scalar( zero, TGSI_SWIZZLE_X );
1347
1348 /* CMP TMP0, SRC0, one, zero */
1349 if (!submit_op3( emit, inst_token( SVGA3DOP_CMP ),
1350 writemask( temp0, dst.mask ), src0, one, zero ))
1351 return FALSE;
1352
1353 /* CMP TMP1, negate(SRC0), negate(one), zero */
1354 if (!submit_op3( emit, inst_token( SVGA3DOP_CMP ),
1355 writemask( temp1, dst.mask ), negate( src0 ), negate( one ),
1356 zero ))
1357 return FALSE;
1358
1359 /* ADD DST, TMP0, TMP1 */
1360 return submit_op2( emit, inst_token( SVGA3DOP_ADD ), dst, src( temp0 ),
1361 src( temp1 ) );
1362 }
1363
1364
1365 /**
1366 * ADD DST SRC0, negate(SRC0)
1367 */
1368 static boolean
1369 emit_sub(struct svga_shader_emitter *emit,
1370 const struct tgsi_full_instruction *insn)
1371 {
1372 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
1373 struct src_register src0 = translate_src_register(
1374 emit, &insn->Src[0] );
1375 struct src_register src1 = translate_src_register(
1376 emit, &insn->Src[1] );
1377
1378 src1 = negate(src1);
1379
1380 if (!submit_op2( emit, inst_token( SVGA3DOP_ADD ), dst,
1381 src0, src1 ))
1382 return FALSE;
1383
1384 return TRUE;
1385 }
1386
1387
1388 static boolean
1389 emit_kill_if(struct svga_shader_emitter *emit,
1390 const struct tgsi_full_instruction *insn)
1391 {
1392 const struct tgsi_full_src_register *reg = &insn->Src[0];
1393 struct src_register src0, srcIn;
1394 const boolean special = (reg->Register.Absolute ||
1395 reg->Register.Negate ||
1396 reg->Register.Indirect ||
1397 reg->Register.SwizzleX != 0 ||
1398 reg->Register.SwizzleY != 1 ||
1399 reg->Register.SwizzleZ != 2 ||
1400 reg->Register.File != TGSI_FILE_TEMPORARY);
1401 SVGA3dShaderDestToken temp;
1402
1403 src0 = srcIn = translate_src_register( emit, reg );
1404
1405 if (special) {
1406 /* need a temp reg */
1407 temp = get_temp( emit );
1408 }
1409
1410 if (special) {
1411 /* move the source into a temp register */
1412 submit_op1(emit, inst_token(SVGA3DOP_MOV), temp, src0);
1413
1414 src0 = src( temp );
1415 }
1416
1417 /* Do the texkill by checking if any of the XYZW components are < 0.
1418 * Note that ps_2_0 and later take XYZW in consideration, while ps_1_x
1419 * only used XYZ. The MSDN documentation about this is incorrect.
1420 */
1421 if (!submit_op0( emit, inst_token( SVGA3DOP_TEXKILL ), dst(src0) ))
1422 return FALSE;
1423
1424 return TRUE;
1425 }
1426
1427
1428 /**
1429 * unconditional kill
1430 */
1431 static boolean
1432 emit_kill(struct svga_shader_emitter *emit,
1433 const struct tgsi_full_instruction *insn)
1434 {
1435 SVGA3dShaderDestToken temp;
1436 struct src_register one = scalar( get_zero_immediate( emit ),
1437 TGSI_SWIZZLE_W );
1438 SVGA3dShaderInstToken inst = inst_token( SVGA3DOP_TEXKILL );
1439
1440 /* texkill doesn't allow negation on the operand so lets move
1441 * negation of {1} to a temp register */
1442 temp = get_temp( emit );
1443 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ), temp,
1444 negate( one ) ))
1445 return FALSE;
1446
1447 return submit_op0( emit, inst, temp );
1448 }
1449
1450
1451 /**
1452 * Test if r1 and r2 are the same register.
1453 */
1454 static boolean
1455 same_register(struct src_register r1, struct src_register r2)
1456 {
1457 return (r1.base.num == r2.base.num &&
1458 r1.base.type_upper == r2.base.type_upper &&
1459 r1.base.type_lower == r2.base.type_lower);
1460 }
1461
1462
1463
1464 /* Implement conditionals by initializing destination reg to 'fail',
1465 * then set predicate reg with UFOP_SETP, then move 'pass' to dest
1466 * based on predicate reg.
1467 *
1468 * SETP src0, cmp, src1 -- do this first to avoid aliasing problems.
1469 * MOV dst, fail
1470 * MOV dst, pass, p0
1471 */
1472 static boolean
1473 emit_conditional(struct svga_shader_emitter *emit,
1474 unsigned compare_func,
1475 SVGA3dShaderDestToken dst,
1476 struct src_register src0,
1477 struct src_register src1,
1478 struct src_register pass,
1479 struct src_register fail)
1480 {
1481 SVGA3dShaderDestToken pred_reg = dst_register( SVGA3DREG_PREDICATE, 0 );
1482 SVGA3dShaderInstToken setp_token, mov_token;
1483 setp_token = inst_token( SVGA3DOP_SETP );
1484
1485 switch (compare_func) {
1486 case PIPE_FUNC_NEVER:
1487 return submit_op1( emit, inst_token( SVGA3DOP_MOV ),
1488 dst, fail );
1489 break;
1490 case PIPE_FUNC_LESS:
1491 setp_token.control = SVGA3DOPCOMP_LT;
1492 break;
1493 case PIPE_FUNC_EQUAL:
1494 setp_token.control = SVGA3DOPCOMP_EQ;
1495 break;
1496 case PIPE_FUNC_LEQUAL:
1497 setp_token.control = SVGA3DOPCOMP_LE;
1498 break;
1499 case PIPE_FUNC_GREATER:
1500 setp_token.control = SVGA3DOPCOMP_GT;
1501 break;
1502 case PIPE_FUNC_NOTEQUAL:
1503 setp_token.control = SVGA3DOPCOMPC_NE;
1504 break;
1505 case PIPE_FUNC_GEQUAL:
1506 setp_token.control = SVGA3DOPCOMP_GE;
1507 break;
1508 case PIPE_FUNC_ALWAYS:
1509 return submit_op1( emit, inst_token( SVGA3DOP_MOV ),
1510 dst, pass );
1511 break;
1512 }
1513
1514 if (same_register(src(dst), pass)) {
1515 /* We'll get bad results if the dst and pass registers are the same
1516 * so use a temp register containing pass.
1517 */
1518 SVGA3dShaderDestToken temp = get_temp(emit);
1519 if (!submit_op1(emit, inst_token(SVGA3DOP_MOV), temp, pass))
1520 return FALSE;
1521 pass = src(temp);
1522 }
1523
1524 /* SETP src0, COMPOP, src1 */
1525 if (!submit_op2( emit, setp_token, pred_reg,
1526 src0, src1 ))
1527 return FALSE;
1528
1529 mov_token = inst_token( SVGA3DOP_MOV );
1530
1531 /* MOV dst, fail */
1532 if (!submit_op1( emit, mov_token, dst,
1533 fail ))
1534 return FALSE;
1535
1536 /* MOV dst, pass (predicated)
1537 *
1538 * Note that the predicate reg (and possible modifiers) is passed
1539 * as the first source argument.
1540 */
1541 mov_token.predicated = 1;
1542 if (!submit_op2( emit, mov_token, dst,
1543 src( pred_reg ), pass ))
1544 return FALSE;
1545
1546 return TRUE;
1547 }
1548
1549
1550 static boolean
1551 emit_select(struct svga_shader_emitter *emit,
1552 unsigned compare_func,
1553 SVGA3dShaderDestToken dst,
1554 struct src_register src0,
1555 struct src_register src1 )
1556 {
1557 /* There are some SVGA instructions which implement some selects
1558 * directly, but they are only available in the vertex shader.
1559 */
1560 if (emit->unit == PIPE_SHADER_VERTEX) {
1561 switch (compare_func) {
1562 case PIPE_FUNC_GEQUAL:
1563 return submit_op2( emit, inst_token( SVGA3DOP_SGE ), dst, src0, src1 );
1564 case PIPE_FUNC_LEQUAL:
1565 return submit_op2( emit, inst_token( SVGA3DOP_SGE ), dst, src1, src0 );
1566 case PIPE_FUNC_GREATER:
1567 return submit_op2( emit, inst_token( SVGA3DOP_SLT ), dst, src1, src0 );
1568 case PIPE_FUNC_LESS:
1569 return submit_op2( emit, inst_token( SVGA3DOP_SLT ), dst, src0, src1 );
1570 default:
1571 break;
1572 }
1573 }
1574
1575 /* Otherwise, need to use the setp approach:
1576 */
1577 {
1578 struct src_register one, zero;
1579 /* zero immediate is 0,0,0,1 */
1580 zero = get_zero_immediate( emit );
1581 one = scalar( zero, TGSI_SWIZZLE_W );
1582 zero = scalar( zero, TGSI_SWIZZLE_X );
1583
1584 return emit_conditional(
1585 emit,
1586 compare_func,
1587 dst,
1588 src0,
1589 src1,
1590 one, zero);
1591 }
1592 }
1593
1594
1595 static boolean
1596 emit_select_op(struct svga_shader_emitter *emit,
1597 unsigned compare,
1598 const struct tgsi_full_instruction *insn)
1599 {
1600 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
1601 struct src_register src0 = translate_src_register(
1602 emit, &insn->Src[0] );
1603 struct src_register src1 = translate_src_register(
1604 emit, &insn->Src[1] );
1605
1606 return emit_select( emit, compare, dst, src0, src1 );
1607 }
1608
1609
1610 /**
1611 * Translate TGSI CMP instruction.
1612 */
1613 static boolean
1614 emit_cmp(struct svga_shader_emitter *emit,
1615 const struct tgsi_full_instruction *insn)
1616 {
1617 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
1618 const struct src_register src0 =
1619 translate_src_register(emit, &insn->Src[0] );
1620 const struct src_register src1 =
1621 translate_src_register(emit, &insn->Src[1] );
1622 const struct src_register src2 =
1623 translate_src_register(emit, &insn->Src[2] );
1624
1625 if (emit->unit == PIPE_SHADER_VERTEX) {
1626 struct src_register zero =
1627 scalar(get_zero_immediate(emit), TGSI_SWIZZLE_X);
1628 /* We used to simulate CMP with SLT+LRP. But that didn't work when
1629 * src1 or src2 was Inf/NaN. In particular, GLSL sqrt(0) failed
1630 * because it involves a CMP to handle the 0 case.
1631 * Use a conditional expression instead.
1632 */
1633 return emit_conditional(emit, PIPE_FUNC_LESS, dst,
1634 src0, zero, src1, src2);
1635 }
1636 else {
1637 assert(emit->unit == PIPE_SHADER_FRAGMENT);
1638
1639 /* CMP DST, SRC0, SRC2, SRC1 */
1640 return submit_op3( emit, inst_token( SVGA3DOP_CMP ), dst,
1641 src0, src2, src1);
1642 }
1643 }
1644
1645
1646 /**
1647 * Translate texture instructions to SVGA3D representation.
1648 */
1649 static boolean
1650 emit_tex2(struct svga_shader_emitter *emit,
1651 const struct tgsi_full_instruction *insn,
1652 SVGA3dShaderDestToken dst)
1653 {
1654 SVGA3dShaderInstToken inst;
1655 struct src_register texcoord;
1656 struct src_register sampler;
1657 SVGA3dShaderDestToken tmp;
1658
1659 inst.value = 0;
1660
1661 switch (insn->Instruction.Opcode) {
1662 case TGSI_OPCODE_TEX:
1663 inst.op = SVGA3DOP_TEX;
1664 break;
1665 case TGSI_OPCODE_TXP:
1666 inst.op = SVGA3DOP_TEX;
1667 inst.control = SVGA3DOPCONT_PROJECT;
1668 break;
1669 case TGSI_OPCODE_TXB:
1670 inst.op = SVGA3DOP_TEX;
1671 inst.control = SVGA3DOPCONT_BIAS;
1672 break;
1673 case TGSI_OPCODE_TXL:
1674 inst.op = SVGA3DOP_TEXLDL;
1675 break;
1676 default:
1677 assert(0);
1678 return FALSE;
1679 }
1680
1681 texcoord = translate_src_register( emit, &insn->Src[0] );
1682 sampler = translate_src_register( emit, &insn->Src[1] );
1683
1684 if (emit->key.fkey.tex[sampler.base.num].unnormalized ||
1685 emit->dynamic_branching_level > 0)
1686 tmp = get_temp( emit );
1687
1688 /* Can't do mipmapping inside dynamic branch constructs. Force LOD
1689 * zero in that case.
1690 */
1691 if (emit->dynamic_branching_level > 0 &&
1692 inst.op == SVGA3DOP_TEX &&
1693 SVGA3dShaderGetRegType(texcoord.base.value) == SVGA3DREG_TEMP) {
1694 struct src_register zero = get_zero_immediate( emit );
1695
1696 /* MOV tmp, texcoord */
1697 if (!submit_op1( emit,
1698 inst_token( SVGA3DOP_MOV ),
1699 tmp,
1700 texcoord ))
1701 return FALSE;
1702
1703 /* MOV tmp.w, zero */
1704 if (!submit_op1( emit,
1705 inst_token( SVGA3DOP_MOV ),
1706 writemask( tmp, TGSI_WRITEMASK_W ),
1707 scalar( zero, TGSI_SWIZZLE_X )))
1708 return FALSE;
1709
1710 texcoord = src( tmp );
1711 inst.op = SVGA3DOP_TEXLDL;
1712 }
1713
1714 /* Explicit normalization of texcoords:
1715 */
1716 if (emit->key.fkey.tex[sampler.base.num].unnormalized) {
1717 struct src_register wh = get_tex_dimensions( emit, sampler.base.num );
1718
1719 /* MUL tmp, SRC0, WH */
1720 if (!submit_op2( emit, inst_token( SVGA3DOP_MUL ),
1721 tmp, texcoord, wh ))
1722 return FALSE;
1723
1724 texcoord = src( tmp );
1725 }
1726
1727 return submit_op2( emit, inst, dst, texcoord, sampler );
1728 }
1729
1730
1731 /**
1732 * Translate texture instructions to SVGA3D representation.
1733 */
1734 static boolean
1735 emit_tex4(struct svga_shader_emitter *emit,
1736 const struct tgsi_full_instruction *insn,
1737 SVGA3dShaderDestToken dst )
1738 {
1739 SVGA3dShaderInstToken inst;
1740 struct src_register texcoord;
1741 struct src_register ddx;
1742 struct src_register ddy;
1743 struct src_register sampler;
1744
1745 texcoord = translate_src_register( emit, &insn->Src[0] );
1746 ddx = translate_src_register( emit, &insn->Src[1] );
1747 ddy = translate_src_register( emit, &insn->Src[2] );
1748 sampler = translate_src_register( emit, &insn->Src[3] );
1749
1750 inst.value = 0;
1751
1752 switch (insn->Instruction.Opcode) {
1753 case TGSI_OPCODE_TXD:
1754 inst.op = SVGA3DOP_TEXLDD; /* 4 args! */
1755 break;
1756 default:
1757 assert(0);
1758 return FALSE;
1759 }
1760
1761 return submit_op4( emit, inst, dst, texcoord, sampler, ddx, ddy );
1762 }
1763
1764
1765 /**
1766 * Emit texture swizzle code.
1767 */
1768 static boolean
1769 emit_tex_swizzle(struct svga_shader_emitter *emit,
1770 SVGA3dShaderDestToken dst,
1771 struct src_register src,
1772 unsigned swizzle_x,
1773 unsigned swizzle_y,
1774 unsigned swizzle_z,
1775 unsigned swizzle_w)
1776 {
1777 const unsigned swizzleIn[4] = {swizzle_x, swizzle_y, swizzle_z, swizzle_w};
1778 unsigned srcSwizzle[4];
1779 unsigned srcWritemask = 0x0, zeroWritemask = 0x0, oneWritemask = 0x0;
1780 int i;
1781
1782 /* build writemasks and srcSwizzle terms */
1783 for (i = 0; i < 4; i++) {
1784 if (swizzleIn[i] == PIPE_SWIZZLE_ZERO) {
1785 srcSwizzle[i] = TGSI_SWIZZLE_X + i;
1786 zeroWritemask |= (1 << i);
1787 }
1788 else if (swizzleIn[i] == PIPE_SWIZZLE_ONE) {
1789 srcSwizzle[i] = TGSI_SWIZZLE_X + i;
1790 oneWritemask |= (1 << i);
1791 }
1792 else {
1793 srcSwizzle[i] = swizzleIn[i];
1794 srcWritemask |= (1 << i);
1795 }
1796 }
1797
1798 /* write x/y/z/w comps */
1799 if (dst.mask & srcWritemask) {
1800 if (!submit_op1(emit,
1801 inst_token(SVGA3DOP_MOV),
1802 writemask(dst, srcWritemask),
1803 swizzle(src,
1804 srcSwizzle[0],
1805 srcSwizzle[1],
1806 srcSwizzle[2],
1807 srcSwizzle[3])))
1808 return FALSE;
1809 }
1810
1811 /* write 0 comps */
1812 if (dst.mask & zeroWritemask) {
1813 if (!submit_op1(emit,
1814 inst_token(SVGA3DOP_MOV),
1815 writemask(dst, zeroWritemask),
1816 scalar(get_zero_immediate(emit), TGSI_SWIZZLE_X)))
1817 return FALSE;
1818 }
1819
1820 /* write 1 comps */
1821 if (dst.mask & oneWritemask) {
1822 if (!submit_op1(emit,
1823 inst_token(SVGA3DOP_MOV),
1824 writemask(dst, oneWritemask),
1825 scalar(get_zero_immediate(emit), TGSI_SWIZZLE_W)))
1826 return FALSE;
1827 }
1828
1829 return TRUE;
1830 }
1831
1832
1833 static boolean
1834 emit_tex(struct svga_shader_emitter *emit,
1835 const struct tgsi_full_instruction *insn)
1836 {
1837 SVGA3dShaderDestToken dst =
1838 translate_dst_register( emit, insn, 0 );
1839 struct src_register src0 =
1840 translate_src_register( emit, &insn->Src[0] );
1841 struct src_register src1 =
1842 translate_src_register( emit, &insn->Src[1] );
1843
1844 SVGA3dShaderDestToken tex_result;
1845 const unsigned unit = src1.base.num;
1846
1847 /* check for shadow samplers */
1848 boolean compare = (emit->key.fkey.tex[unit].compare_mode ==
1849 PIPE_TEX_COMPARE_R_TO_TEXTURE);
1850
1851 /* texture swizzle */
1852 boolean swizzle = (emit->key.fkey.tex[unit].swizzle_r != PIPE_SWIZZLE_RED ||
1853 emit->key.fkey.tex[unit].swizzle_g != PIPE_SWIZZLE_GREEN ||
1854 emit->key.fkey.tex[unit].swizzle_b != PIPE_SWIZZLE_BLUE ||
1855 emit->key.fkey.tex[unit].swizzle_a != PIPE_SWIZZLE_ALPHA);
1856
1857 boolean saturate = insn->Instruction.Saturate != TGSI_SAT_NONE;
1858
1859 /* If doing compare processing or tex swizzle or saturation, we need to put
1860 * the fetched color into a temporary so it can be used as a source later on.
1861 */
1862 if (compare || swizzle || saturate) {
1863 tex_result = get_temp( emit );
1864 }
1865 else {
1866 tex_result = dst;
1867 }
1868
1869 switch(insn->Instruction.Opcode) {
1870 case TGSI_OPCODE_TEX:
1871 case TGSI_OPCODE_TXB:
1872 case TGSI_OPCODE_TXP:
1873 case TGSI_OPCODE_TXL:
1874 if (!emit_tex2( emit, insn, tex_result ))
1875 return FALSE;
1876 break;
1877 case TGSI_OPCODE_TXD:
1878 if (!emit_tex4( emit, insn, tex_result ))
1879 return FALSE;
1880 break;
1881 default:
1882 assert(0);
1883 }
1884
1885 if (compare) {
1886 SVGA3dShaderDestToken dst2;
1887
1888 if (swizzle || saturate)
1889 dst2 = tex_result;
1890 else
1891 dst2 = dst;
1892
1893 if (dst.mask & TGSI_WRITEMASK_XYZ) {
1894 SVGA3dShaderDestToken src0_zdivw = get_temp( emit );
1895 /* When sampling a depth texture, the result of the comparison is in
1896 * the Y component.
1897 */
1898 struct src_register tex_src_x = scalar(src(tex_result), TGSI_SWIZZLE_Y);
1899 struct src_register r_coord;
1900
1901 if (insn->Instruction.Opcode == TGSI_OPCODE_TXP) {
1902 /* Divide texcoord R by Q */
1903 if (!submit_op1( emit, inst_token( SVGA3DOP_RCP ),
1904 writemask(src0_zdivw, TGSI_WRITEMASK_X),
1905 scalar(src0, TGSI_SWIZZLE_W) ))
1906 return FALSE;
1907
1908 if (!submit_op2( emit, inst_token( SVGA3DOP_MUL ),
1909 writemask(src0_zdivw, TGSI_WRITEMASK_X),
1910 scalar(src0, TGSI_SWIZZLE_Z),
1911 scalar(src(src0_zdivw), TGSI_SWIZZLE_X) ))
1912 return FALSE;
1913
1914 r_coord = scalar(src(src0_zdivw), TGSI_SWIZZLE_X);
1915 }
1916 else {
1917 r_coord = scalar(src0, TGSI_SWIZZLE_Z);
1918 }
1919
1920 /* Compare texture sample value against R component of texcoord */
1921 if (!emit_select(emit,
1922 emit->key.fkey.tex[unit].compare_func,
1923 writemask( dst2, TGSI_WRITEMASK_XYZ ),
1924 r_coord,
1925 tex_src_x))
1926 return FALSE;
1927 }
1928
1929 if (dst.mask & TGSI_WRITEMASK_W) {
1930 struct src_register one =
1931 scalar( get_zero_immediate( emit ), TGSI_SWIZZLE_W );
1932
1933 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ),
1934 writemask( dst2, TGSI_WRITEMASK_W ),
1935 one ))
1936 return FALSE;
1937 }
1938 }
1939
1940 if (saturate && !swizzle) {
1941 /* MOV_SAT real_dst, dst */
1942 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ), dst, src(tex_result) ))
1943 return FALSE;
1944 }
1945 else if (swizzle) {
1946 /* swizzle from tex_result to dst (handles saturation too, if any) */
1947 emit_tex_swizzle(emit,
1948 dst, src(tex_result),
1949 emit->key.fkey.tex[unit].swizzle_r,
1950 emit->key.fkey.tex[unit].swizzle_g,
1951 emit->key.fkey.tex[unit].swizzle_b,
1952 emit->key.fkey.tex[unit].swizzle_a);
1953 }
1954
1955 return TRUE;
1956 }
1957
1958
1959 static boolean
1960 emit_bgnloop2(struct svga_shader_emitter *emit,
1961 const struct tgsi_full_instruction *insn)
1962 {
1963 SVGA3dShaderInstToken inst = inst_token( SVGA3DOP_LOOP );
1964 struct src_register loop_reg = src_register( SVGA3DREG_LOOP, 0 );
1965 struct src_register const_int = get_loop_const( emit );
1966
1967 emit->dynamic_branching_level++;
1968
1969 return (emit_instruction( emit, inst ) &&
1970 emit_src( emit, loop_reg ) &&
1971 emit_src( emit, const_int ) );
1972 }
1973
1974
1975 static boolean
1976 emit_endloop2(struct svga_shader_emitter *emit,
1977 const struct tgsi_full_instruction *insn)
1978 {
1979 SVGA3dShaderInstToken inst = inst_token( SVGA3DOP_ENDLOOP );
1980
1981 emit->dynamic_branching_level--;
1982
1983 return emit_instruction( emit, inst );
1984 }
1985
1986
1987 static boolean
1988 emit_brk(struct svga_shader_emitter *emit,
1989 const struct tgsi_full_instruction *insn)
1990 {
1991 SVGA3dShaderInstToken inst = inst_token( SVGA3DOP_BREAK );
1992 return emit_instruction( emit, inst );
1993 }
1994
1995
1996 static boolean
1997 emit_scalar_op1(struct svga_shader_emitter *emit,
1998 unsigned opcode,
1999 const struct tgsi_full_instruction *insn)
2000 {
2001 SVGA3dShaderInstToken inst;
2002 SVGA3dShaderDestToken dst;
2003 struct src_register src;
2004
2005 inst = inst_token( opcode );
2006 dst = translate_dst_register( emit, insn, 0 );
2007 src = translate_src_register( emit, &insn->Src[0] );
2008 src = scalar( src, TGSI_SWIZZLE_X );
2009
2010 return submit_op1( emit, inst, dst, src );
2011 }
2012
2013
2014 static boolean
2015 emit_simple_instruction(struct svga_shader_emitter *emit,
2016 unsigned opcode,
2017 const struct tgsi_full_instruction *insn)
2018 {
2019 const struct tgsi_full_src_register *src = insn->Src;
2020 SVGA3dShaderInstToken inst;
2021 SVGA3dShaderDestToken dst;
2022
2023 inst = inst_token( opcode );
2024 dst = translate_dst_register( emit, insn, 0 );
2025
2026 switch (insn->Instruction.NumSrcRegs) {
2027 case 0:
2028 return submit_op0( emit, inst, dst );
2029 case 1:
2030 return submit_op1( emit, inst, dst,
2031 translate_src_register( emit, &src[0] ));
2032 case 2:
2033 return submit_op2( emit, inst, dst,
2034 translate_src_register( emit, &src[0] ),
2035 translate_src_register( emit, &src[1] ) );
2036 case 3:
2037 return submit_op3( emit, inst, dst,
2038 translate_src_register( emit, &src[0] ),
2039 translate_src_register( emit, &src[1] ),
2040 translate_src_register( emit, &src[2] ) );
2041 default:
2042 assert(0);
2043 return FALSE;
2044 }
2045 }
2046
2047
2048 static boolean
2049 emit_deriv(struct svga_shader_emitter *emit,
2050 const struct tgsi_full_instruction *insn )
2051 {
2052 if (emit->dynamic_branching_level > 0 &&
2053 insn->Src[0].Register.File == TGSI_FILE_TEMPORARY)
2054 {
2055 struct src_register zero = get_zero_immediate( emit );
2056 SVGA3dShaderDestToken dst =
2057 translate_dst_register( emit, insn, 0 );
2058
2059 /* Deriv opcodes not valid inside dynamic branching, workaround
2060 * by zeroing out the destination.
2061 */
2062 if (!submit_op1(emit,
2063 inst_token( SVGA3DOP_MOV ),
2064 dst,
2065 scalar(zero, TGSI_SWIZZLE_X)))
2066 return FALSE;
2067
2068 return TRUE;
2069 }
2070 else {
2071 unsigned opcode;
2072 const struct tgsi_full_src_register *reg = &insn->Src[0];
2073 SVGA3dShaderInstToken inst;
2074 SVGA3dShaderDestToken dst;
2075 struct src_register src0;
2076
2077 switch (insn->Instruction.Opcode) {
2078 case TGSI_OPCODE_DDX:
2079 opcode = SVGA3DOP_DSX;
2080 break;
2081 case TGSI_OPCODE_DDY:
2082 opcode = SVGA3DOP_DSY;
2083 break;
2084 default:
2085 return FALSE;
2086 }
2087
2088 inst = inst_token( opcode );
2089 dst = translate_dst_register( emit, insn, 0 );
2090 src0 = translate_src_register( emit, reg );
2091
2092 /* We cannot use negate or abs on source to dsx/dsy instruction.
2093 */
2094 if (reg->Register.Absolute ||
2095 reg->Register.Negate) {
2096 SVGA3dShaderDestToken temp = get_temp( emit );
2097
2098 if (!emit_repl( emit, temp, &src0 ))
2099 return FALSE;
2100 }
2101
2102 return submit_op1( emit, inst, dst, src0 );
2103 }
2104 }
2105
2106
2107 static boolean
2108 emit_arl(struct svga_shader_emitter *emit,
2109 const struct tgsi_full_instruction *insn)
2110 {
2111 ++emit->current_arl;
2112 if (emit->unit == PIPE_SHADER_FRAGMENT) {
2113 /* MOVA not present in pixel shader instruction set.
2114 * Ignore this instruction altogether since it is
2115 * only used for loop counters -- and for that
2116 * we reference aL directly.
2117 */
2118 return TRUE;
2119 }
2120 if (svga_arl_needs_adjustment( emit )) {
2121 return emit_fake_arl( emit, insn );
2122 } else {
2123 /* no need to adjust, just emit straight arl */
2124 return emit_simple_instruction(emit, SVGA3DOP_MOVA, insn);
2125 }
2126 }
2127
2128
2129 static boolean
2130 emit_pow(struct svga_shader_emitter *emit,
2131 const struct tgsi_full_instruction *insn)
2132 {
2133 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
2134 struct src_register src0 = translate_src_register(
2135 emit, &insn->Src[0] );
2136 struct src_register src1 = translate_src_register(
2137 emit, &insn->Src[1] );
2138 boolean need_tmp = FALSE;
2139
2140 /* POW can only output to a temporary */
2141 if (insn->Dst[0].Register.File != TGSI_FILE_TEMPORARY)
2142 need_tmp = TRUE;
2143
2144 /* POW src1 must not be the same register as dst */
2145 if (alias_src_dst( src1, dst ))
2146 need_tmp = TRUE;
2147
2148 /* it's a scalar op */
2149 src0 = scalar( src0, TGSI_SWIZZLE_X );
2150 src1 = scalar( src1, TGSI_SWIZZLE_X );
2151
2152 if (need_tmp) {
2153 SVGA3dShaderDestToken tmp =
2154 writemask(get_temp( emit ), TGSI_WRITEMASK_X );
2155
2156 if (!submit_op2(emit, inst_token( SVGA3DOP_POW ), tmp, src0, src1))
2157 return FALSE;
2158
2159 return submit_op1(emit, inst_token( SVGA3DOP_MOV ),
2160 dst, scalar(src(tmp), 0) );
2161 }
2162 else {
2163 return submit_op2(emit, inst_token( SVGA3DOP_POW ), dst, src0, src1);
2164 }
2165 }
2166
2167
2168 static boolean
2169 emit_xpd(struct svga_shader_emitter *emit,
2170 const struct tgsi_full_instruction *insn)
2171 {
2172 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
2173 const struct src_register src0 = translate_src_register(
2174 emit, &insn->Src[0] );
2175 const struct src_register src1 = translate_src_register(
2176 emit, &insn->Src[1] );
2177 boolean need_dst_tmp = FALSE;
2178
2179 /* XPD can only output to a temporary */
2180 if (SVGA3dShaderGetRegType(dst.value) != SVGA3DREG_TEMP)
2181 need_dst_tmp = TRUE;
2182
2183 /* The dst reg must not be the same as src0 or src1*/
2184 if (alias_src_dst(src0, dst) ||
2185 alias_src_dst(src1, dst))
2186 need_dst_tmp = TRUE;
2187
2188 if (need_dst_tmp) {
2189 SVGA3dShaderDestToken tmp = get_temp( emit );
2190
2191 /* Obey DX9 restrictions on mask:
2192 */
2193 tmp.mask = dst.mask & TGSI_WRITEMASK_XYZ;
2194
2195 if (!submit_op2(emit, inst_token( SVGA3DOP_CRS ), tmp, src0, src1))
2196 return FALSE;
2197
2198 if (!submit_op1(emit, inst_token( SVGA3DOP_MOV ), dst, src( tmp )))
2199 return FALSE;
2200 }
2201 else {
2202 if (!submit_op2(emit, inst_token( SVGA3DOP_CRS ), dst, src0, src1))
2203 return FALSE;
2204 }
2205
2206 /* Need to emit 1.0 to dst.w?
2207 */
2208 if (dst.mask & TGSI_WRITEMASK_W) {
2209 struct src_register zero = get_zero_immediate( emit );
2210
2211 if (!submit_op1(emit,
2212 inst_token( SVGA3DOP_MOV ),
2213 writemask(dst, TGSI_WRITEMASK_W),
2214 zero))
2215 return FALSE;
2216 }
2217
2218 return TRUE;
2219 }
2220
2221
2222 static boolean
2223 emit_lrp(struct svga_shader_emitter *emit,
2224 const struct tgsi_full_instruction *insn)
2225 {
2226 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
2227 const struct src_register src0 = translate_src_register(
2228 emit, &insn->Src[0] );
2229 const struct src_register src1 = translate_src_register(
2230 emit, &insn->Src[1] );
2231 const struct src_register src2 = translate_src_register(
2232 emit, &insn->Src[2] );
2233
2234 return submit_lrp(emit, dst, src0, src1, src2);
2235 }
2236
2237
2238 static boolean
2239 emit_dst_insn(struct svga_shader_emitter *emit,
2240 const struct tgsi_full_instruction *insn)
2241 {
2242 if (emit->unit == PIPE_SHADER_VERTEX) {
2243 /* SVGA/DX9 has a DST instruction, but only for vertex shaders:
2244 */
2245 return emit_simple_instruction(emit, SVGA3DOP_DST, insn);
2246 }
2247 else {
2248 /* result[0] = 1 * 1;
2249 * result[1] = a[1] * b[1];
2250 * result[2] = a[2] * 1;
2251 * result[3] = 1 * b[3];
2252 */
2253 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
2254 SVGA3dShaderDestToken tmp;
2255 const struct src_register src0 = translate_src_register(
2256 emit, &insn->Src[0] );
2257 const struct src_register src1 = translate_src_register(
2258 emit, &insn->Src[1] );
2259 struct src_register zero = get_zero_immediate( emit );
2260 boolean need_tmp = FALSE;
2261
2262 if (SVGA3dShaderGetRegType(dst.value) != SVGA3DREG_TEMP ||
2263 alias_src_dst(src0, dst) ||
2264 alias_src_dst(src1, dst))
2265 need_tmp = TRUE;
2266
2267 if (need_tmp) {
2268 tmp = get_temp( emit );
2269 }
2270 else {
2271 tmp = dst;
2272 }
2273
2274 /* tmp.xw = 1.0
2275 */
2276 if (tmp.mask & TGSI_WRITEMASK_XW) {
2277 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ),
2278 writemask(tmp, TGSI_WRITEMASK_XW ),
2279 scalar( zero, 3 )))
2280 return FALSE;
2281 }
2282
2283 /* tmp.yz = src0
2284 */
2285 if (tmp.mask & TGSI_WRITEMASK_YZ) {
2286 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ),
2287 writemask(tmp, TGSI_WRITEMASK_YZ ),
2288 src0))
2289 return FALSE;
2290 }
2291
2292 /* tmp.yw = tmp * src1
2293 */
2294 if (tmp.mask & TGSI_WRITEMASK_YW) {
2295 if (!submit_op2( emit, inst_token( SVGA3DOP_MUL ),
2296 writemask(tmp, TGSI_WRITEMASK_YW ),
2297 src(tmp),
2298 src1))
2299 return FALSE;
2300 }
2301
2302 /* dst = tmp
2303 */
2304 if (need_tmp) {
2305 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ),
2306 dst,
2307 src(tmp)))
2308 return FALSE;
2309 }
2310 }
2311
2312 return TRUE;
2313 }
2314
2315
2316 static boolean
2317 emit_exp(struct svga_shader_emitter *emit,
2318 const struct tgsi_full_instruction *insn)
2319 {
2320 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
2321 struct src_register src0 =
2322 translate_src_register( emit, &insn->Src[0] );
2323 struct src_register zero = get_zero_immediate( emit );
2324 SVGA3dShaderDestToken fraction;
2325
2326 if (dst.mask & TGSI_WRITEMASK_Y)
2327 fraction = dst;
2328 else if (dst.mask & TGSI_WRITEMASK_X)
2329 fraction = get_temp( emit );
2330 else
2331 fraction.value = 0;
2332
2333 /* If y is being written, fill it with src0 - floor(src0).
2334 */
2335 if (dst.mask & TGSI_WRITEMASK_XY) {
2336 if (!submit_op1( emit, inst_token( SVGA3DOP_FRC ),
2337 writemask( fraction, TGSI_WRITEMASK_Y ),
2338 src0 ))
2339 return FALSE;
2340 }
2341
2342 /* If x is being written, fill it with 2 ^ floor(src0).
2343 */
2344 if (dst.mask & TGSI_WRITEMASK_X) {
2345 if (!submit_op2( emit, inst_token( SVGA3DOP_ADD ),
2346 writemask( dst, TGSI_WRITEMASK_X ),
2347 src0,
2348 scalar( negate( src( fraction ) ), TGSI_SWIZZLE_Y ) ) )
2349 return FALSE;
2350
2351 if (!submit_op1( emit, inst_token( SVGA3DOP_EXP ),
2352 writemask( dst, TGSI_WRITEMASK_X ),
2353 scalar( src( dst ), TGSI_SWIZZLE_X ) ) )
2354 return FALSE;
2355
2356 if (!(dst.mask & TGSI_WRITEMASK_Y))
2357 release_temp( emit, fraction );
2358 }
2359
2360 /* If z is being written, fill it with 2 ^ src0 (partial precision).
2361 */
2362 if (dst.mask & TGSI_WRITEMASK_Z) {
2363 if (!submit_op1( emit, inst_token( SVGA3DOP_EXPP ),
2364 writemask( dst, TGSI_WRITEMASK_Z ),
2365 src0 ) )
2366 return FALSE;
2367 }
2368
2369 /* If w is being written, fill it with one.
2370 */
2371 if (dst.mask & TGSI_WRITEMASK_W) {
2372 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ),
2373 writemask(dst, TGSI_WRITEMASK_W),
2374 scalar( zero, TGSI_SWIZZLE_W ) ))
2375 return FALSE;
2376 }
2377
2378 return TRUE;
2379 }
2380
2381
2382 static boolean
2383 emit_lit(struct svga_shader_emitter *emit,
2384 const struct tgsi_full_instruction *insn)
2385 {
2386 if (emit->unit == PIPE_SHADER_VERTEX) {
2387 /* SVGA/DX9 has a LIT instruction, but only for vertex shaders:
2388 */
2389 return emit_simple_instruction(emit, SVGA3DOP_LIT, insn);
2390 }
2391 else {
2392 /* D3D vs. GL semantics can be fairly easily accomodated by
2393 * variations on this sequence.
2394 *
2395 * GL:
2396 * tmp.y = src.x
2397 * tmp.z = pow(src.y,src.w)
2398 * p0 = src0.xxxx > 0
2399 * result = zero.wxxw
2400 * (p0) result.yz = tmp
2401 *
2402 * D3D:
2403 * tmp.y = src.x
2404 * tmp.z = pow(src.y,src.w)
2405 * p0 = src0.xxyy > 0
2406 * result = zero.wxxw
2407 * (p0) result.yz = tmp
2408 *
2409 * Will implement the GL version for now.
2410 */
2411 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
2412 SVGA3dShaderDestToken tmp = get_temp( emit );
2413 const struct src_register src0 = translate_src_register(
2414 emit, &insn->Src[0] );
2415 struct src_register zero = get_zero_immediate( emit );
2416
2417 /* tmp = pow(src.y, src.w)
2418 */
2419 if (dst.mask & TGSI_WRITEMASK_Z) {
2420 if (!submit_op2(emit, inst_token( SVGA3DOP_POW ),
2421 tmp,
2422 scalar(src0, 1),
2423 scalar(src0, 3)))
2424 return FALSE;
2425 }
2426
2427 /* tmp.y = src.x
2428 */
2429 if (dst.mask & TGSI_WRITEMASK_Y) {
2430 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ),
2431 writemask(tmp, TGSI_WRITEMASK_Y ),
2432 scalar(src0, 0)))
2433 return FALSE;
2434 }
2435
2436 /* Can't quite do this with emit conditional due to the extra
2437 * writemask on the predicated mov:
2438 */
2439 {
2440 SVGA3dShaderDestToken pred_reg = dst_register( SVGA3DREG_PREDICATE, 0 );
2441 SVGA3dShaderInstToken setp_token, mov_token;
2442 struct src_register predsrc;
2443
2444 setp_token = inst_token( SVGA3DOP_SETP );
2445 mov_token = inst_token( SVGA3DOP_MOV );
2446
2447 setp_token.control = SVGA3DOPCOMP_GT;
2448
2449 /* D3D vs GL semantics:
2450 */
2451 if (0)
2452 predsrc = swizzle(src0, 0, 0, 1, 1); /* D3D */
2453 else
2454 predsrc = swizzle(src0, 0, 0, 0, 0); /* GL */
2455
2456 /* SETP src0.xxyy, GT, {0}.x */
2457 if (!submit_op2( emit, setp_token, pred_reg,
2458 predsrc,
2459 swizzle(zero, 0, 0, 0, 0) ))
2460 return FALSE;
2461
2462 /* MOV dst, fail */
2463 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ), dst,
2464 swizzle(zero, 3, 0, 0, 3 )))
2465 return FALSE;
2466
2467 /* MOV dst.yz, tmp (predicated)
2468 *
2469 * Note that the predicate reg (and possible modifiers) is passed
2470 * as the first source argument.
2471 */
2472 if (dst.mask & TGSI_WRITEMASK_YZ) {
2473 mov_token.predicated = 1;
2474 if (!submit_op2( emit, mov_token,
2475 writemask(dst, TGSI_WRITEMASK_YZ),
2476 src( pred_reg ), src( tmp ) ))
2477 return FALSE;
2478 }
2479 }
2480 }
2481
2482 return TRUE;
2483 }
2484
2485
2486 static boolean
2487 emit_ex2(struct svga_shader_emitter *emit,
2488 const struct tgsi_full_instruction *insn)
2489 {
2490 SVGA3dShaderInstToken inst;
2491 SVGA3dShaderDestToken dst;
2492 struct src_register src0;
2493
2494 inst = inst_token( SVGA3DOP_EXP );
2495 dst = translate_dst_register( emit, insn, 0 );
2496 src0 = translate_src_register( emit, &insn->Src[0] );
2497 src0 = scalar( src0, TGSI_SWIZZLE_X );
2498
2499 if (dst.mask != TGSI_WRITEMASK_XYZW) {
2500 SVGA3dShaderDestToken tmp = get_temp( emit );
2501
2502 if (!submit_op1( emit, inst, tmp, src0 ))
2503 return FALSE;
2504
2505 return submit_op1( emit, inst_token( SVGA3DOP_MOV ),
2506 dst,
2507 scalar( src( tmp ), TGSI_SWIZZLE_X ) );
2508 }
2509
2510 return submit_op1( emit, inst, dst, src0 );
2511 }
2512
2513
2514 static boolean
2515 emit_log(struct svga_shader_emitter *emit,
2516 const struct tgsi_full_instruction *insn)
2517 {
2518 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
2519 struct src_register src0 =
2520 translate_src_register( emit, &insn->Src[0] );
2521 struct src_register zero = get_zero_immediate( emit );
2522 SVGA3dShaderDestToken abs_tmp;
2523 struct src_register abs_src0;
2524 SVGA3dShaderDestToken log2_abs;
2525
2526 abs_tmp.value = 0;
2527
2528 if (dst.mask & TGSI_WRITEMASK_Z)
2529 log2_abs = dst;
2530 else if (dst.mask & TGSI_WRITEMASK_XY)
2531 log2_abs = get_temp( emit );
2532 else
2533 log2_abs.value = 0;
2534
2535 /* If z is being written, fill it with log2( abs( src0 ) ).
2536 */
2537 if (dst.mask & TGSI_WRITEMASK_XYZ) {
2538 if (!src0.base.srcMod || src0.base.srcMod == SVGA3DSRCMOD_ABS)
2539 abs_src0 = src0;
2540 else {
2541 abs_tmp = get_temp( emit );
2542
2543 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ),
2544 abs_tmp,
2545 src0 ) )
2546 return FALSE;
2547
2548 abs_src0 = src( abs_tmp );
2549 }
2550
2551 abs_src0 = absolute( scalar( abs_src0, TGSI_SWIZZLE_X ) );
2552
2553 if (!submit_op1( emit, inst_token( SVGA3DOP_LOG ),
2554 writemask( log2_abs, TGSI_WRITEMASK_Z ),
2555 abs_src0 ) )
2556 return FALSE;
2557 }
2558
2559 if (dst.mask & TGSI_WRITEMASK_XY) {
2560 SVGA3dShaderDestToken floor_log2;
2561
2562 if (dst.mask & TGSI_WRITEMASK_X)
2563 floor_log2 = dst;
2564 else
2565 floor_log2 = get_temp( emit );
2566
2567 /* If x is being written, fill it with floor( log2( abs( src0 ) ) ).
2568 */
2569 if (!submit_op1( emit, inst_token( SVGA3DOP_FRC ),
2570 writemask( floor_log2, TGSI_WRITEMASK_X ),
2571 scalar( src( log2_abs ), TGSI_SWIZZLE_Z ) ) )
2572 return FALSE;
2573
2574 if (!submit_op2( emit, inst_token( SVGA3DOP_ADD ),
2575 writemask( floor_log2, TGSI_WRITEMASK_X ),
2576 scalar( src( log2_abs ), TGSI_SWIZZLE_Z ),
2577 negate( src( floor_log2 ) ) ) )
2578 return FALSE;
2579
2580 /* If y is being written, fill it with
2581 * abs ( src0 ) / ( 2 ^ floor( log2( abs( src0 ) ) ) ).
2582 */
2583 if (dst.mask & TGSI_WRITEMASK_Y) {
2584 if (!submit_op1( emit, inst_token( SVGA3DOP_EXP ),
2585 writemask( dst, TGSI_WRITEMASK_Y ),
2586 negate( scalar( src( floor_log2 ),
2587 TGSI_SWIZZLE_X ) ) ) )
2588 return FALSE;
2589
2590 if (!submit_op2( emit, inst_token( SVGA3DOP_MUL ),
2591 writemask( dst, TGSI_WRITEMASK_Y ),
2592 src( dst ),
2593 abs_src0 ) )
2594 return FALSE;
2595 }
2596
2597 if (!(dst.mask & TGSI_WRITEMASK_X))
2598 release_temp( emit, floor_log2 );
2599
2600 if (!(dst.mask & TGSI_WRITEMASK_Z))
2601 release_temp( emit, log2_abs );
2602 }
2603
2604 if (dst.mask & TGSI_WRITEMASK_XYZ && src0.base.srcMod &&
2605 src0.base.srcMod != SVGA3DSRCMOD_ABS)
2606 release_temp( emit, abs_tmp );
2607
2608 /* If w is being written, fill it with one.
2609 */
2610 if (dst.mask & TGSI_WRITEMASK_W) {
2611 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ),
2612 writemask(dst, TGSI_WRITEMASK_W),
2613 scalar( zero, TGSI_SWIZZLE_W ) ))
2614 return FALSE;
2615 }
2616
2617 return TRUE;
2618 }
2619
2620
2621 /**
2622 * Translate TGSI TRUNC or ROUND instruction.
2623 * We need to truncate toward zero. Ex: trunc(-1.9) = -1
2624 * Different approaches are needed for VS versus PS.
2625 */
2626 static boolean
2627 emit_trunc_round(struct svga_shader_emitter *emit,
2628 const struct tgsi_full_instruction *insn,
2629 boolean round)
2630 {
2631 SVGA3dShaderDestToken dst = translate_dst_register(emit, insn, 0);
2632 const struct src_register src0 =
2633 translate_src_register(emit, &insn->Src[0] );
2634 SVGA3dShaderDestToken t1 = get_temp(emit);
2635
2636 if (round) {
2637 SVGA3dShaderDestToken t0 = get_temp(emit);
2638 struct src_register half = get_half_immediate(emit);
2639
2640 /* t0 = abs(src0) + 0.5 */
2641 if (!submit_op2(emit, inst_token(SVGA3DOP_ADD), t0,
2642 absolute(src0), half))
2643 return FALSE;
2644
2645 /* t1 = fract(t0) */
2646 if (!submit_op1(emit, inst_token(SVGA3DOP_FRC), t1, src(t0)))
2647 return FALSE;
2648
2649 /* t1 = t0 - t1 */
2650 if (!submit_op2(emit, inst_token(SVGA3DOP_ADD), t1, src(t0),
2651 negate(src(t1))))
2652 return FALSE;
2653 }
2654 else {
2655 /* trunc */
2656
2657 /* t1 = fract(abs(src0)) */
2658 if (!submit_op1(emit, inst_token(SVGA3DOP_FRC), t1, absolute(src0)))
2659 return FALSE;
2660
2661 /* t1 = abs(src0) - t1 */
2662 if (!submit_op2(emit, inst_token(SVGA3DOP_ADD), t1, absolute(src0),
2663 negate(src(t1))))
2664 return FALSE;
2665 }
2666
2667 /*
2668 * Now we need to multiply t1 by the sign of the original value.
2669 */
2670 if (emit->unit == PIPE_SHADER_VERTEX) {
2671 /* For VS: use SGN instruction */
2672 /* Need two extra/dummy registers: */
2673 SVGA3dShaderDestToken t2 = get_temp(emit), t3 = get_temp(emit),
2674 t4 = get_temp(emit);
2675
2676 /* t2 = sign(src0) */
2677 if (!submit_op3(emit, inst_token(SVGA3DOP_SGN), t2, src0,
2678 src(t3), src(t4)))
2679 return FALSE;
2680
2681 /* dst = t1 * t2 */
2682 if (!submit_op2(emit, inst_token(SVGA3DOP_MUL), dst, src(t1), src(t2)))
2683 return FALSE;
2684 }
2685 else {
2686 /* For FS: Use CMP instruction */
2687 return submit_op3(emit, inst_token( SVGA3DOP_CMP ), dst,
2688 src0, src(t1), negate(src(t1)));
2689 }
2690
2691 return TRUE;
2692 }
2693
2694
2695 static boolean
2696 emit_bgnsub(struct svga_shader_emitter *emit,
2697 unsigned position,
2698 const struct tgsi_full_instruction *insn)
2699 {
2700 unsigned i;
2701
2702 /* Note that we've finished the main function and are now emitting
2703 * subroutines. This affects how we terminate the generated
2704 * shader.
2705 */
2706 emit->in_main_func = FALSE;
2707
2708 for (i = 0; i < emit->nr_labels; i++) {
2709 if (emit->label[i] == position) {
2710 return (emit_instruction( emit, inst_token( SVGA3DOP_RET ) ) &&
2711 emit_instruction( emit, inst_token( SVGA3DOP_LABEL ) ) &&
2712 emit_src( emit, src_register( SVGA3DREG_LABEL, i )));
2713 }
2714 }
2715
2716 assert(0);
2717 return TRUE;
2718 }
2719
2720
2721 static boolean
2722 emit_call(struct svga_shader_emitter *emit,
2723 const struct tgsi_full_instruction *insn)
2724 {
2725 unsigned position = insn->Label.Label;
2726 unsigned i;
2727
2728 for (i = 0; i < emit->nr_labels; i++) {
2729 if (emit->label[i] == position)
2730 break;
2731 }
2732
2733 if (emit->nr_labels == Elements(emit->label))
2734 return FALSE;
2735
2736 if (i == emit->nr_labels) {
2737 emit->label[i] = position;
2738 emit->nr_labels++;
2739 }
2740
2741 return (emit_instruction( emit, inst_token( SVGA3DOP_CALL ) ) &&
2742 emit_src( emit, src_register( SVGA3DREG_LABEL, i )));
2743 }
2744
2745
2746 /**
2747 * Called at the end of the shader. Actually, emit special "fix-up"
2748 * code for the vertex/fragment shader.
2749 */
2750 static boolean
2751 emit_end(struct svga_shader_emitter *emit)
2752 {
2753 if (emit->unit == PIPE_SHADER_VERTEX) {
2754 return emit_vs_postamble( emit );
2755 }
2756 else {
2757 return emit_ps_postamble( emit );
2758 }
2759 }
2760
2761
2762
2763 static boolean
2764 svga_emit_instruction(struct svga_shader_emitter *emit,
2765 unsigned position,
2766 const struct tgsi_full_instruction *insn)
2767 {
2768 switch (insn->Instruction.Opcode) {
2769
2770 case TGSI_OPCODE_ARL:
2771 return emit_arl( emit, insn );
2772
2773 case TGSI_OPCODE_TEX:
2774 case TGSI_OPCODE_TXB:
2775 case TGSI_OPCODE_TXP:
2776 case TGSI_OPCODE_TXL:
2777 case TGSI_OPCODE_TXD:
2778 return emit_tex( emit, insn );
2779
2780 case TGSI_OPCODE_DDX:
2781 case TGSI_OPCODE_DDY:
2782 return emit_deriv( emit, insn );
2783
2784 case TGSI_OPCODE_BGNSUB:
2785 return emit_bgnsub( emit, position, insn );
2786
2787 case TGSI_OPCODE_ENDSUB:
2788 return TRUE;
2789
2790 case TGSI_OPCODE_CAL:
2791 return emit_call( emit, insn );
2792
2793 case TGSI_OPCODE_FLR:
2794 return emit_floor( emit, insn );
2795
2796 case TGSI_OPCODE_TRUNC:
2797 return emit_trunc_round( emit, insn, FALSE );
2798
2799 case TGSI_OPCODE_ROUND:
2800 return emit_trunc_round( emit, insn, TRUE );
2801
2802 case TGSI_OPCODE_CEIL:
2803 return emit_ceil( emit, insn );
2804
2805 case TGSI_OPCODE_CMP:
2806 return emit_cmp( emit, insn );
2807
2808 case TGSI_OPCODE_DIV:
2809 return emit_div( emit, insn );
2810
2811 case TGSI_OPCODE_DP2:
2812 return emit_dp2( emit, insn );
2813
2814 case TGSI_OPCODE_DPH:
2815 return emit_dph( emit, insn );
2816
2817 case TGSI_OPCODE_NRM:
2818 return emit_nrm( emit, insn );
2819
2820 case TGSI_OPCODE_COS:
2821 return emit_cos( emit, insn );
2822
2823 case TGSI_OPCODE_SIN:
2824 return emit_sin( emit, insn );
2825
2826 case TGSI_OPCODE_SCS:
2827 return emit_sincos( emit, insn );
2828
2829 case TGSI_OPCODE_END:
2830 /* TGSI always finishes the main func with an END */
2831 return emit_end( emit );
2832
2833 case TGSI_OPCODE_KILL_IF:
2834 return emit_kill_if( emit, insn );
2835
2836 /* Selection opcodes. The underlying language is fairly
2837 * non-orthogonal about these.
2838 */
2839 case TGSI_OPCODE_SEQ:
2840 return emit_select_op( emit, PIPE_FUNC_EQUAL, insn );
2841
2842 case TGSI_OPCODE_SNE:
2843 return emit_select_op( emit, PIPE_FUNC_NOTEQUAL, insn );
2844
2845 case TGSI_OPCODE_SGT:
2846 return emit_select_op( emit, PIPE_FUNC_GREATER, insn );
2847
2848 case TGSI_OPCODE_SGE:
2849 return emit_select_op( emit, PIPE_FUNC_GEQUAL, insn );
2850
2851 case TGSI_OPCODE_SLT:
2852 return emit_select_op( emit, PIPE_FUNC_LESS, insn );
2853
2854 case TGSI_OPCODE_SLE:
2855 return emit_select_op( emit, PIPE_FUNC_LEQUAL, insn );
2856
2857 case TGSI_OPCODE_SUB:
2858 return emit_sub( emit, insn );
2859
2860 case TGSI_OPCODE_POW:
2861 return emit_pow( emit, insn );
2862
2863 case TGSI_OPCODE_EX2:
2864 return emit_ex2( emit, insn );
2865
2866 case TGSI_OPCODE_EXP:
2867 return emit_exp( emit, insn );
2868
2869 case TGSI_OPCODE_LOG:
2870 return emit_log( emit, insn );
2871
2872 case TGSI_OPCODE_LG2:
2873 return emit_scalar_op1( emit, SVGA3DOP_LOG, insn );
2874
2875 case TGSI_OPCODE_RSQ:
2876 return emit_scalar_op1( emit, SVGA3DOP_RSQ, insn );
2877
2878 case TGSI_OPCODE_RCP:
2879 return emit_scalar_op1( emit, SVGA3DOP_RCP, insn );
2880
2881 case TGSI_OPCODE_CONT:
2882 /* not expected (we return PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED = 0) */
2883 return FALSE;
2884
2885 case TGSI_OPCODE_RET:
2886 /* This is a noop -- we tell mesa that we can't support RET
2887 * within a function (early return), so this will always be
2888 * followed by an ENDSUB.
2889 */
2890 return TRUE;
2891
2892 /* These aren't actually used by any of the frontends we care
2893 * about:
2894 */
2895 case TGSI_OPCODE_CLAMP:
2896 case TGSI_OPCODE_AND:
2897 case TGSI_OPCODE_OR:
2898 case TGSI_OPCODE_I2F:
2899 case TGSI_OPCODE_NOT:
2900 case TGSI_OPCODE_SHL:
2901 case TGSI_OPCODE_ISHR:
2902 case TGSI_OPCODE_XOR:
2903 return FALSE;
2904
2905 case TGSI_OPCODE_IF:
2906 return emit_if( emit, insn );
2907 case TGSI_OPCODE_ELSE:
2908 return emit_else( emit, insn );
2909 case TGSI_OPCODE_ENDIF:
2910 return emit_endif( emit, insn );
2911
2912 case TGSI_OPCODE_BGNLOOP:
2913 return emit_bgnloop2( emit, insn );
2914 case TGSI_OPCODE_ENDLOOP:
2915 return emit_endloop2( emit, insn );
2916 case TGSI_OPCODE_BRK:
2917 return emit_brk( emit, insn );
2918
2919 case TGSI_OPCODE_XPD:
2920 return emit_xpd( emit, insn );
2921
2922 case TGSI_OPCODE_KILL:
2923 return emit_kill( emit, insn );
2924
2925 case TGSI_OPCODE_DST:
2926 return emit_dst_insn( emit, insn );
2927
2928 case TGSI_OPCODE_LIT:
2929 return emit_lit( emit, insn );
2930
2931 case TGSI_OPCODE_LRP:
2932 return emit_lrp( emit, insn );
2933
2934 case TGSI_OPCODE_SSG:
2935 return emit_ssg( emit, insn );
2936
2937 default:
2938 {
2939 unsigned opcode = translate_opcode(insn->Instruction.Opcode);
2940
2941 if (opcode == SVGA3DOP_LAST_INST)
2942 return FALSE;
2943
2944 if (!emit_simple_instruction( emit, opcode, insn ))
2945 return FALSE;
2946 }
2947 }
2948
2949 return TRUE;
2950 }
2951
2952
2953 static boolean
2954 svga_emit_immediate(struct svga_shader_emitter *emit,
2955 struct tgsi_full_immediate *imm)
2956 {
2957 static const float id[4] = {0,0,0,1};
2958 float value[4];
2959 unsigned i;
2960
2961 assert(1 <= imm->Immediate.NrTokens && imm->Immediate.NrTokens <= 5);
2962 for (i = 0; i < imm->Immediate.NrTokens - 1; i++) {
2963 float f = imm->u[i].Float;
2964 value[i] = util_is_inf_or_nan(f) ? 0.0f : f;
2965 }
2966
2967 for ( ; i < 4; i++ )
2968 value[i] = id[i];
2969
2970 return emit_def_const( emit, SVGA3D_CONST_TYPE_FLOAT,
2971 emit->imm_start + emit->internal_imm_count++,
2972 value[0], value[1], value[2], value[3]);
2973 }
2974
2975
2976 static boolean
2977 make_immediate(struct svga_shader_emitter *emit,
2978 float a, float b, float c, float d,
2979 struct src_register *out )
2980 {
2981 unsigned idx = emit->nr_hw_float_const++;
2982
2983 if (!emit_def_const( emit, SVGA3D_CONST_TYPE_FLOAT,
2984 idx, a, b, c, d ))
2985 return FALSE;
2986
2987 *out = src_register( SVGA3DREG_CONST, idx );
2988
2989 return TRUE;
2990 }
2991
2992
2993 static boolean
2994 emit_vs_preamble(struct svga_shader_emitter *emit)
2995 {
2996 if (!emit->key.vkey.need_prescale) {
2997 if (!make_immediate( emit, 0, 0, .5, .5,
2998 &emit->imm_0055))
2999 return FALSE;
3000 }
3001
3002 return TRUE;
3003 }
3004
3005
3006 static boolean
3007 emit_ps_preamble(struct svga_shader_emitter *emit)
3008 {
3009 if (emit->ps_reads_pos && emit->info.reads_z) {
3010 /*
3011 * Assemble the position from various bits of inputs. Depth and W are
3012 * passed in a texcoord this is due to D3D's vPos not hold Z or W.
3013 * Also fixup the perspective interpolation.
3014 *
3015 * temp_pos.xy = vPos.xy
3016 * temp_pos.w = rcp(texcoord1.w);
3017 * temp_pos.z = texcoord1.z * temp_pos.w;
3018 */
3019 if (!submit_op1( emit,
3020 inst_token(SVGA3DOP_MOV),
3021 writemask( emit->ps_temp_pos, TGSI_WRITEMASK_XY ),
3022 emit->ps_true_pos ))
3023 return FALSE;
3024
3025 if (!submit_op1( emit,
3026 inst_token(SVGA3DOP_RCP),
3027 writemask( emit->ps_temp_pos, TGSI_WRITEMASK_W ),
3028 scalar( emit->ps_depth_pos, TGSI_SWIZZLE_W ) ))
3029 return FALSE;
3030
3031 if (!submit_op2( emit,
3032 inst_token(SVGA3DOP_MUL),
3033 writemask( emit->ps_temp_pos, TGSI_WRITEMASK_Z ),
3034 scalar( emit->ps_depth_pos, TGSI_SWIZZLE_Z ),
3035 scalar( src(emit->ps_temp_pos), TGSI_SWIZZLE_W ) ))
3036 return FALSE;
3037 }
3038
3039 return TRUE;
3040 }
3041
3042
3043 static boolean
3044 emit_ps_postamble(struct svga_shader_emitter *emit)
3045 {
3046 unsigned i;
3047
3048 /* PS oDepth is incredibly fragile and it's very hard to catch the
3049 * types of usage that break it during shader emit. Easier just to
3050 * redirect the main program to a temporary and then only touch
3051 * oDepth with a hand-crafted MOV below.
3052 */
3053 if (SVGA3dShaderGetRegType(emit->true_pos.value) != 0) {
3054 if (!submit_op1( emit,
3055 inst_token(SVGA3DOP_MOV),
3056 emit->true_pos,
3057 scalar(src(emit->temp_pos), TGSI_SWIZZLE_Z) ))
3058 return FALSE;
3059 }
3060
3061 for (i = 0; i < PIPE_MAX_COLOR_BUFS; i++) {
3062 if (SVGA3dShaderGetRegType(emit->true_color_output[i].value) != 0) {
3063 /* Potentially override output colors with white for XOR
3064 * logicop workaround.
3065 */
3066 if (emit->unit == PIPE_SHADER_FRAGMENT &&
3067 emit->key.fkey.white_fragments) {
3068 struct src_register one = scalar( get_zero_immediate( emit ),
3069 TGSI_SWIZZLE_W );
3070
3071 if (!submit_op1( emit,
3072 inst_token(SVGA3DOP_MOV),
3073 emit->true_color_output[i],
3074 one ))
3075 return FALSE;
3076 }
3077 else {
3078 if (!submit_op1( emit,
3079 inst_token(SVGA3DOP_MOV),
3080 emit->true_color_output[i],
3081 src(emit->temp_color_output[i]) ))
3082 return FALSE;
3083 }
3084 }
3085 }
3086
3087 return TRUE;
3088 }
3089
3090
3091 static boolean
3092 emit_vs_postamble(struct svga_shader_emitter *emit)
3093 {
3094 /* PSIZ output is incredibly fragile and it's very hard to catch
3095 * the types of usage that break it during shader emit. Easier
3096 * just to redirect the main program to a temporary and then only
3097 * touch PSIZ with a hand-crafted MOV below.
3098 */
3099 if (SVGA3dShaderGetRegType(emit->true_psiz.value) != 0) {
3100 if (!submit_op1( emit,
3101 inst_token(SVGA3DOP_MOV),
3102 emit->true_psiz,
3103 scalar(src(emit->temp_psiz), TGSI_SWIZZLE_X) ))
3104 return FALSE;
3105 }
3106
3107 /* Need to perform various manipulations on vertex position to cope
3108 * with the different GL and D3D clip spaces.
3109 */
3110 if (emit->key.vkey.need_prescale) {
3111 SVGA3dShaderDestToken temp_pos = emit->temp_pos;
3112 SVGA3dShaderDestToken depth = emit->depth_pos;
3113 SVGA3dShaderDestToken pos = emit->true_pos;
3114 unsigned offset = emit->info.file_max[TGSI_FILE_CONSTANT] + 1;
3115 struct src_register prescale_scale = src_register( SVGA3DREG_CONST,
3116 offset + 0 );
3117 struct src_register prescale_trans = src_register( SVGA3DREG_CONST,
3118 offset + 1 );
3119
3120 if (!submit_op1( emit,
3121 inst_token(SVGA3DOP_MOV),
3122 writemask(depth, TGSI_WRITEMASK_W),
3123 scalar(src(temp_pos), TGSI_SWIZZLE_W) ))
3124 return FALSE;
3125
3126 /* MUL temp_pos.xyz, temp_pos, prescale.scale
3127 * MAD result.position, temp_pos.wwww, prescale.trans, temp_pos
3128 * --> Note that prescale.trans.w == 0
3129 */
3130 if (!submit_op2( emit,
3131 inst_token(SVGA3DOP_MUL),
3132 writemask(temp_pos, TGSI_WRITEMASK_XYZ),
3133 src(temp_pos),
3134 prescale_scale ))
3135 return FALSE;
3136
3137 if (!submit_op3( emit,
3138 inst_token(SVGA3DOP_MAD),
3139 pos,
3140 swizzle(src(temp_pos), 3, 3, 3, 3),
3141 prescale_trans,
3142 src(temp_pos)))
3143 return FALSE;
3144
3145 /* Also write to depth value */
3146 if (!submit_op3( emit,
3147 inst_token(SVGA3DOP_MAD),
3148 writemask(depth, TGSI_WRITEMASK_Z),
3149 swizzle(src(temp_pos), 3, 3, 3, 3),
3150 prescale_trans,
3151 src(temp_pos) ))
3152 return FALSE;
3153 }
3154 else {
3155 SVGA3dShaderDestToken temp_pos = emit->temp_pos;
3156 SVGA3dShaderDestToken depth = emit->depth_pos;
3157 SVGA3dShaderDestToken pos = emit->true_pos;
3158 struct src_register imm_0055 = emit->imm_0055;
3159
3160 /* Adjust GL clipping coordinate space to hardware (D3D-style):
3161 *
3162 * DP4 temp_pos.z, {0,0,.5,.5}, temp_pos
3163 * MOV result.position, temp_pos
3164 */
3165 if (!submit_op2( emit,
3166 inst_token(SVGA3DOP_DP4),
3167 writemask(temp_pos, TGSI_WRITEMASK_Z),
3168 imm_0055,
3169 src(temp_pos) ))
3170 return FALSE;
3171
3172 if (!submit_op1( emit,
3173 inst_token(SVGA3DOP_MOV),
3174 pos,
3175 src(temp_pos) ))
3176 return FALSE;
3177
3178 /* Move the manipulated depth into the extra texcoord reg */
3179 if (!submit_op1( emit,
3180 inst_token(SVGA3DOP_MOV),
3181 writemask(depth, TGSI_WRITEMASK_ZW),
3182 src(temp_pos) ))
3183 return FALSE;
3184 }
3185
3186 return TRUE;
3187 }
3188
3189
3190 /**
3191 * For the pixel shader: emit the code which chooses the front
3192 * or back face color depending on triangle orientation.
3193 *
3194 * 0: IF VFACE :4
3195 * 1: COLOR = FrontColor;
3196 * 2: ELSE
3197 * 3: COLOR = BackColor;
3198 * 4: ENDIF
3199 */
3200 static boolean
3201 emit_light_twoside(struct svga_shader_emitter *emit)
3202 {
3203 struct src_register vface, zero;
3204 struct src_register front[2];
3205 struct src_register back[2];
3206 SVGA3dShaderDestToken color[2];
3207 int count = emit->internal_color_count;
3208 int i;
3209 SVGA3dShaderInstToken if_token;
3210
3211 if (count == 0)
3212 return TRUE;
3213
3214 vface = get_vface( emit );
3215 zero = get_zero_immediate( emit );
3216
3217 /* Can't use get_temp() to allocate the color reg as such
3218 * temporaries will be reclaimed after each instruction by the call
3219 * to reset_temp_regs().
3220 */
3221 for (i = 0; i < count; i++) {
3222 color[i] = dst_register( SVGA3DREG_TEMP, emit->nr_hw_temp++ );
3223 front[i] = emit->input_map[emit->internal_color_idx[i]];
3224
3225 /* Back is always the next input:
3226 */
3227 back[i] = front[i];
3228 back[i].base.num = front[i].base.num + 1;
3229
3230 /* Reassign the input_map to the actual front-face color:
3231 */
3232 emit->input_map[emit->internal_color_idx[i]] = src(color[i]);
3233 }
3234
3235 if_token = inst_token( SVGA3DOP_IFC );
3236
3237 if (emit->key.fkey.front_ccw)
3238 if_token.control = SVGA3DOPCOMP_LT;
3239 else
3240 if_token.control = SVGA3DOPCOMP_GT;
3241
3242 zero = scalar(zero, TGSI_SWIZZLE_X);
3243
3244 if (!(emit_instruction( emit, if_token ) &&
3245 emit_src( emit, vface ) &&
3246 emit_src( emit, zero ) ))
3247 return FALSE;
3248
3249 for (i = 0; i < count; i++) {
3250 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ), color[i], front[i] ))
3251 return FALSE;
3252 }
3253
3254 if (!(emit_instruction( emit, inst_token( SVGA3DOP_ELSE))))
3255 return FALSE;
3256
3257 for (i = 0; i < count; i++) {
3258 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ), color[i], back[i] ))
3259 return FALSE;
3260 }
3261
3262 if (!emit_instruction( emit, inst_token( SVGA3DOP_ENDIF ) ))
3263 return FALSE;
3264
3265 return TRUE;
3266 }
3267
3268
3269 /**
3270 * 0: SETP_GT TEMP, VFACE, 0
3271 * where TEMP is a fake frontface register
3272 */
3273 static boolean
3274 emit_frontface(struct svga_shader_emitter *emit)
3275 {
3276 struct src_register vface, zero;
3277 SVGA3dShaderDestToken temp;
3278 struct src_register pass, fail;
3279
3280 vface = get_vface( emit );
3281 zero = get_zero_immediate( emit );
3282
3283 /* Can't use get_temp() to allocate the fake frontface reg as such
3284 * temporaries will be reclaimed after each instruction by the call
3285 * to reset_temp_regs().
3286 */
3287 temp = dst_register( SVGA3DREG_TEMP,
3288 emit->nr_hw_temp++ );
3289
3290 if (emit->key.fkey.front_ccw) {
3291 pass = scalar( zero, TGSI_SWIZZLE_X );
3292 fail = scalar( zero, TGSI_SWIZZLE_W );
3293 } else {
3294 pass = scalar( zero, TGSI_SWIZZLE_W );
3295 fail = scalar( zero, TGSI_SWIZZLE_X );
3296 }
3297
3298 if (!emit_conditional(emit, PIPE_FUNC_GREATER,
3299 temp, vface, scalar( zero, TGSI_SWIZZLE_X ),
3300 pass, fail))
3301 return FALSE;
3302
3303 /* Reassign the input_map to the actual front-face color:
3304 */
3305 emit->input_map[emit->internal_frontface_idx] = src(temp);
3306
3307 return TRUE;
3308 }
3309
3310
3311 /**
3312 * Emit code to invert the T component of the incoming texture coordinate.
3313 * This is used for drawing point sprites when
3314 * pipe_rasterizer_state::sprite_coord_mode == PIPE_SPRITE_COORD_LOWER_LEFT.
3315 */
3316 static boolean
3317 emit_inverted_texcoords(struct svga_shader_emitter *emit)
3318 {
3319 struct src_register zero = get_zero_immediate(emit);
3320 struct src_register pos_neg_one = get_pos_neg_one_immediate( emit );
3321 unsigned inverted_texcoords = emit->inverted_texcoords;
3322
3323 while (inverted_texcoords) {
3324 const unsigned unit = ffs(inverted_texcoords) - 1;
3325
3326 assert(emit->inverted_texcoords & (1 << unit));
3327
3328 assert(unit < Elements(emit->ps_true_texcoord));
3329
3330 assert(unit < Elements(emit->ps_inverted_texcoord_input));
3331
3332 assert(emit->ps_inverted_texcoord_input[unit]
3333 < Elements(emit->input_map));
3334
3335 /* inverted = coord * (1, -1, 1, 1) + (0, 1, 0, 0) */
3336 if (!submit_op3(emit,
3337 inst_token(SVGA3DOP_MAD),
3338 dst(emit->ps_inverted_texcoord[unit]),
3339 emit->ps_true_texcoord[unit],
3340 swizzle(pos_neg_one, 0, 3, 0, 0), /* (1, -1, 1, 1) */
3341 swizzle(zero, 0, 3, 0, 0))) /* (0, 1, 0, 0) */
3342 return FALSE;
3343
3344 /* Reassign the input_map entry to the new texcoord register */
3345 emit->input_map[emit->ps_inverted_texcoord_input[unit]] =
3346 emit->ps_inverted_texcoord[unit];
3347
3348 inverted_texcoords &= ~(1 << unit);
3349 }
3350
3351 return TRUE;
3352 }
3353
3354
3355 static boolean
3356 needs_to_create_zero( struct svga_shader_emitter *emit )
3357 {
3358 unsigned i;
3359
3360 if (emit->unit == PIPE_SHADER_FRAGMENT) {
3361 if (emit->key.fkey.light_twoside)
3362 return TRUE;
3363
3364 if (emit->key.fkey.white_fragments)
3365 return TRUE;
3366
3367 if (emit->emit_frontface)
3368 return TRUE;
3369
3370 if (emit->info.opcode_count[TGSI_OPCODE_DST] >= 1 ||
3371 emit->info.opcode_count[TGSI_OPCODE_SSG] >= 1 ||
3372 emit->info.opcode_count[TGSI_OPCODE_LIT] >= 1)
3373 return TRUE;
3374
3375 if (emit->inverted_texcoords)
3376 return TRUE;
3377
3378 /* look for any PIPE_SWIZZLE_ZERO/ONE terms */
3379 for (i = 0; i < emit->key.fkey.num_textures; i++) {
3380 if (emit->key.fkey.tex[i].swizzle_r > PIPE_SWIZZLE_ALPHA ||
3381 emit->key.fkey.tex[i].swizzle_g > PIPE_SWIZZLE_ALPHA ||
3382 emit->key.fkey.tex[i].swizzle_b > PIPE_SWIZZLE_ALPHA ||
3383 emit->key.fkey.tex[i].swizzle_a > PIPE_SWIZZLE_ALPHA)
3384 return TRUE;
3385 }
3386
3387 for (i = 0; i < emit->key.fkey.num_textures; i++) {
3388 if (emit->key.fkey.tex[i].compare_mode
3389 == PIPE_TEX_COMPARE_R_TO_TEXTURE)
3390 return TRUE;
3391 }
3392 }
3393
3394 if (emit->unit == PIPE_SHADER_VERTEX) {
3395 if (emit->info.opcode_count[TGSI_OPCODE_CMP] >= 1)
3396 return TRUE;
3397 }
3398
3399 if (emit->info.opcode_count[TGSI_OPCODE_IF] >= 1 ||
3400 emit->info.opcode_count[TGSI_OPCODE_BGNLOOP] >= 1 ||
3401 emit->info.opcode_count[TGSI_OPCODE_DDX] >= 1 ||
3402 emit->info.opcode_count[TGSI_OPCODE_DDY] >= 1 ||
3403 emit->info.opcode_count[TGSI_OPCODE_ROUND] >= 1 ||
3404 emit->info.opcode_count[TGSI_OPCODE_SGE] >= 1 ||
3405 emit->info.opcode_count[TGSI_OPCODE_SGT] >= 1 ||
3406 emit->info.opcode_count[TGSI_OPCODE_SLE] >= 1 ||
3407 emit->info.opcode_count[TGSI_OPCODE_SLT] >= 1 ||
3408 emit->info.opcode_count[TGSI_OPCODE_SNE] >= 1 ||
3409 emit->info.opcode_count[TGSI_OPCODE_SEQ] >= 1 ||
3410 emit->info.opcode_count[TGSI_OPCODE_EXP] >= 1 ||
3411 emit->info.opcode_count[TGSI_OPCODE_LOG] >= 1 ||
3412 emit->info.opcode_count[TGSI_OPCODE_XPD] >= 1 ||
3413 emit->info.opcode_count[TGSI_OPCODE_KILL] >= 1)
3414 return TRUE;
3415
3416 return FALSE;
3417 }
3418
3419
3420 static boolean
3421 needs_to_create_loop_const( struct svga_shader_emitter *emit )
3422 {
3423 return (emit->info.opcode_count[TGSI_OPCODE_BGNLOOP] >= 1);
3424 }
3425
3426
3427 static boolean
3428 needs_to_create_arl_consts( struct svga_shader_emitter *emit )
3429 {
3430 return (emit->num_arl_consts > 0);
3431 }
3432
3433
3434 static boolean
3435 pre_parse_add_indirect( struct svga_shader_emitter *emit,
3436 int num, int current_arl)
3437 {
3438 int i;
3439 assert(num < 0);
3440
3441 for (i = 0; i < emit->num_arl_consts; ++i) {
3442 if (emit->arl_consts[i].arl_num == current_arl)
3443 break;
3444 }
3445 /* new entry */
3446 if (emit->num_arl_consts == i) {
3447 ++emit->num_arl_consts;
3448 }
3449 emit->arl_consts[i].number = (emit->arl_consts[i].number > num) ?
3450 num :
3451 emit->arl_consts[i].number;
3452 emit->arl_consts[i].arl_num = current_arl;
3453 return TRUE;
3454 }
3455
3456
3457 static boolean
3458 pre_parse_instruction( struct svga_shader_emitter *emit,
3459 const struct tgsi_full_instruction *insn,
3460 int current_arl)
3461 {
3462 if (insn->Src[0].Register.Indirect &&
3463 insn->Src[0].Indirect.File == TGSI_FILE_ADDRESS) {
3464 const struct tgsi_full_src_register *reg = &insn->Src[0];
3465 if (reg->Register.Index < 0) {
3466 pre_parse_add_indirect(emit, reg->Register.Index, current_arl);
3467 }
3468 }
3469
3470 if (insn->Src[1].Register.Indirect &&
3471 insn->Src[1].Indirect.File == TGSI_FILE_ADDRESS) {
3472 const struct tgsi_full_src_register *reg = &insn->Src[1];
3473 if (reg->Register.Index < 0) {
3474 pre_parse_add_indirect(emit, reg->Register.Index, current_arl);
3475 }
3476 }
3477
3478 if (insn->Src[2].Register.Indirect &&
3479 insn->Src[2].Indirect.File == TGSI_FILE_ADDRESS) {
3480 const struct tgsi_full_src_register *reg = &insn->Src[2];
3481 if (reg->Register.Index < 0) {
3482 pre_parse_add_indirect(emit, reg->Register.Index, current_arl);
3483 }
3484 }
3485
3486 return TRUE;
3487 }
3488
3489
3490 static boolean
3491 pre_parse_tokens( struct svga_shader_emitter *emit,
3492 const struct tgsi_token *tokens )
3493 {
3494 struct tgsi_parse_context parse;
3495 int current_arl = 0;
3496
3497 tgsi_parse_init( &parse, tokens );
3498
3499 while (!tgsi_parse_end_of_tokens( &parse )) {
3500 tgsi_parse_token( &parse );
3501 switch (parse.FullToken.Token.Type) {
3502 case TGSI_TOKEN_TYPE_IMMEDIATE:
3503 case TGSI_TOKEN_TYPE_DECLARATION:
3504 break;
3505 case TGSI_TOKEN_TYPE_INSTRUCTION:
3506 if (parse.FullToken.FullInstruction.Instruction.Opcode ==
3507 TGSI_OPCODE_ARL) {
3508 ++current_arl;
3509 }
3510 if (!pre_parse_instruction( emit, &parse.FullToken.FullInstruction,
3511 current_arl ))
3512 return FALSE;
3513 break;
3514 default:
3515 break;
3516 }
3517
3518 }
3519 return TRUE;
3520 }
3521
3522
3523 static boolean
3524 svga_shader_emit_helpers(struct svga_shader_emitter *emit)
3525 {
3526 if (needs_to_create_zero( emit )) {
3527 create_zero_immediate( emit );
3528 }
3529 if (needs_to_create_loop_const( emit )) {
3530 create_loop_const( emit );
3531 }
3532 if (needs_to_create_arl_consts( emit )) {
3533 create_arl_consts( emit );
3534 }
3535
3536 if (emit->unit == PIPE_SHADER_FRAGMENT) {
3537 if (!emit_ps_preamble( emit ))
3538 return FALSE;
3539
3540 if (emit->key.fkey.light_twoside) {
3541 if (!emit_light_twoside( emit ))
3542 return FALSE;
3543 }
3544 if (emit->emit_frontface) {
3545 if (!emit_frontface( emit ))
3546 return FALSE;
3547 }
3548 if (emit->inverted_texcoords) {
3549 if (!emit_inverted_texcoords( emit ))
3550 return FALSE;
3551 }
3552 }
3553
3554 return TRUE;
3555 }
3556
3557
3558 boolean
3559 svga_shader_emit_instructions(struct svga_shader_emitter *emit,
3560 const struct tgsi_token *tokens)
3561 {
3562 struct tgsi_parse_context parse;
3563 boolean ret = TRUE;
3564 boolean helpers_emitted = FALSE;
3565 unsigned line_nr = 0;
3566
3567 tgsi_parse_init( &parse, tokens );
3568 emit->internal_imm_count = 0;
3569
3570 if (emit->unit == PIPE_SHADER_VERTEX) {
3571 ret = emit_vs_preamble( emit );
3572 if (!ret)
3573 goto done;
3574 }
3575
3576 pre_parse_tokens(emit, tokens);
3577
3578 while (!tgsi_parse_end_of_tokens( &parse )) {
3579 tgsi_parse_token( &parse );
3580
3581 switch (parse.FullToken.Token.Type) {
3582 case TGSI_TOKEN_TYPE_IMMEDIATE:
3583 ret = svga_emit_immediate( emit, &parse.FullToken.FullImmediate );
3584 if (!ret)
3585 goto done;
3586 break;
3587
3588 case TGSI_TOKEN_TYPE_DECLARATION:
3589 ret = svga_translate_decl_sm30( emit, &parse.FullToken.FullDeclaration );
3590 if (!ret)
3591 goto done;
3592 break;
3593
3594 case TGSI_TOKEN_TYPE_INSTRUCTION:
3595 if (!helpers_emitted) {
3596 if (!svga_shader_emit_helpers( emit ))
3597 goto done;
3598 helpers_emitted = TRUE;
3599 }
3600 ret = svga_emit_instruction( emit,
3601 line_nr++,
3602 &parse.FullToken.FullInstruction );
3603 if (!ret)
3604 goto done;
3605 break;
3606 default:
3607 break;
3608 }
3609
3610 reset_temp_regs( emit );
3611 }
3612
3613 /* Need to terminate the current subroutine. Note that the
3614 * hardware doesn't tolerate shaders without sub-routines
3615 * terminating with RET+END.
3616 */
3617 if (!emit->in_main_func) {
3618 ret = emit_instruction( emit, inst_token( SVGA3DOP_RET ) );
3619 if (!ret)
3620 goto done;
3621 }
3622
3623 assert(emit->dynamic_branching_level == 0);
3624
3625 /* Need to terminate the whole shader:
3626 */
3627 ret = emit_instruction( emit, inst_token( SVGA3DOP_END ) );
3628 if (!ret)
3629 goto done;
3630
3631 done:
3632 tgsi_parse_free( &parse );
3633 return ret;
3634 }