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gallium: remove TGSI opcode DPH
[mesa.git] / src / gallium / drivers / svga / svga_tgsi_insn.c
1 /**********************************************************
2 * Copyright 2008-2009 VMware, Inc. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 **********************************************************/
25
26
27 #include "pipe/p_shader_tokens.h"
28 #include "tgsi/tgsi_dump.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/u_memory.h"
31 #include "util/u_math.h"
32 #include "util/u_pstipple.h"
33
34 #include "svga_tgsi_emit.h"
35 #include "svga_context.h"
36
37
38 static boolean emit_vs_postamble( struct svga_shader_emitter *emit );
39 static boolean emit_ps_postamble( struct svga_shader_emitter *emit );
40
41
42 static unsigned
43 translate_opcode(uint opcode)
44 {
45 switch (opcode) {
46 case TGSI_OPCODE_ADD: return SVGA3DOP_ADD;
47 case TGSI_OPCODE_DP3: return SVGA3DOP_DP3;
48 case TGSI_OPCODE_DP4: return SVGA3DOP_DP4;
49 case TGSI_OPCODE_FRC: return SVGA3DOP_FRC;
50 case TGSI_OPCODE_MAD: return SVGA3DOP_MAD;
51 case TGSI_OPCODE_MAX: return SVGA3DOP_MAX;
52 case TGSI_OPCODE_MIN: return SVGA3DOP_MIN;
53 case TGSI_OPCODE_MOV: return SVGA3DOP_MOV;
54 case TGSI_OPCODE_MUL: return SVGA3DOP_MUL;
55 case TGSI_OPCODE_NOP: return SVGA3DOP_NOP;
56 default:
57 assert(!"svga: unexpected opcode in translate_opcode()");
58 return SVGA3DOP_LAST_INST;
59 }
60 }
61
62
63 static unsigned
64 translate_file(unsigned file)
65 {
66 switch (file) {
67 case TGSI_FILE_TEMPORARY: return SVGA3DREG_TEMP;
68 case TGSI_FILE_INPUT: return SVGA3DREG_INPUT;
69 case TGSI_FILE_OUTPUT: return SVGA3DREG_OUTPUT; /* VS3.0+ only */
70 case TGSI_FILE_IMMEDIATE: return SVGA3DREG_CONST;
71 case TGSI_FILE_CONSTANT: return SVGA3DREG_CONST;
72 case TGSI_FILE_SAMPLER: return SVGA3DREG_SAMPLER;
73 case TGSI_FILE_ADDRESS: return SVGA3DREG_ADDR;
74 default:
75 assert(!"svga: unexpected register file in translate_file()");
76 return SVGA3DREG_TEMP;
77 }
78 }
79
80
81 /**
82 * Translate a TGSI destination register to an SVGA3DShaderDestToken.
83 * \param insn the TGSI instruction
84 * \param idx which TGSI dest register to translate (usually (always?) zero)
85 */
86 static SVGA3dShaderDestToken
87 translate_dst_register( struct svga_shader_emitter *emit,
88 const struct tgsi_full_instruction *insn,
89 unsigned idx )
90 {
91 const struct tgsi_full_dst_register *reg = &insn->Dst[idx];
92 SVGA3dShaderDestToken dest;
93
94 switch (reg->Register.File) {
95 case TGSI_FILE_OUTPUT:
96 /* Output registers encode semantic information in their name.
97 * Need to lookup a table built at decl time:
98 */
99 dest = emit->output_map[reg->Register.Index];
100 emit->num_output_writes++;
101 break;
102
103 default:
104 {
105 unsigned index = reg->Register.Index;
106 assert(index < SVGA3D_TEMPREG_MAX);
107 index = MIN2(index, SVGA3D_TEMPREG_MAX - 1);
108 dest = dst_register(translate_file(reg->Register.File), index);
109 }
110 break;
111 }
112
113 if (reg->Register.Indirect) {
114 debug_warning("Indirect indexing of dest registers is not supported!\n");
115 }
116
117 dest.mask = reg->Register.WriteMask;
118 assert(dest.mask);
119
120 if (insn->Instruction.Saturate)
121 dest.dstMod = SVGA3DDSTMOD_SATURATE;
122
123 return dest;
124 }
125
126
127 /**
128 * Apply a swizzle to a src_register, returning a new src_register
129 * Ex: swizzle(SRC.ZZYY, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_X, SWIZZLE_Y)
130 * would return SRC.YYZZ
131 */
132 static struct src_register
133 swizzle(struct src_register src,
134 unsigned x, unsigned y, unsigned z, unsigned w)
135 {
136 assert(x < 4);
137 assert(y < 4);
138 assert(z < 4);
139 assert(w < 4);
140 x = (src.base.swizzle >> (x * 2)) & 0x3;
141 y = (src.base.swizzle >> (y * 2)) & 0x3;
142 z = (src.base.swizzle >> (z * 2)) & 0x3;
143 w = (src.base.swizzle >> (w * 2)) & 0x3;
144
145 src.base.swizzle = TRANSLATE_SWIZZLE(x, y, z, w);
146
147 return src;
148 }
149
150
151 /**
152 * Apply a "scalar" swizzle to a src_register returning a new
153 * src_register where all the swizzle terms are the same.
154 * Ex: scalar(SRC.WZYX, SWIZZLE_Y) would return SRC.ZZZZ
155 */
156 static struct src_register
157 scalar(struct src_register src, unsigned comp)
158 {
159 assert(comp < 4);
160 return swizzle( src, comp, comp, comp, comp );
161 }
162
163
164 static boolean
165 svga_arl_needs_adjustment( const struct svga_shader_emitter *emit )
166 {
167 unsigned i;
168
169 for (i = 0; i < emit->num_arl_consts; ++i) {
170 if (emit->arl_consts[i].arl_num == emit->current_arl)
171 return TRUE;
172 }
173 return FALSE;
174 }
175
176
177 static int
178 svga_arl_adjustment( const struct svga_shader_emitter *emit )
179 {
180 unsigned i;
181
182 for (i = 0; i < emit->num_arl_consts; ++i) {
183 if (emit->arl_consts[i].arl_num == emit->current_arl)
184 return emit->arl_consts[i].number;
185 }
186 return 0;
187 }
188
189
190 /**
191 * Translate a TGSI src register to a src_register.
192 */
193 static struct src_register
194 translate_src_register( const struct svga_shader_emitter *emit,
195 const struct tgsi_full_src_register *reg )
196 {
197 struct src_register src;
198
199 switch (reg->Register.File) {
200 case TGSI_FILE_INPUT:
201 /* Input registers are referred to by their semantic name rather
202 * than by index. Use the mapping build up from the decls:
203 */
204 src = emit->input_map[reg->Register.Index];
205 break;
206
207 case TGSI_FILE_IMMEDIATE:
208 /* Immediates are appended after TGSI constants in the D3D
209 * constant buffer.
210 */
211 src = src_register( translate_file( reg->Register.File ),
212 reg->Register.Index + emit->imm_start );
213 break;
214
215 default:
216 src = src_register( translate_file( reg->Register.File ),
217 reg->Register.Index );
218 break;
219 }
220
221 /* Indirect addressing.
222 */
223 if (reg->Register.Indirect) {
224 if (emit->unit == PIPE_SHADER_FRAGMENT) {
225 /* Pixel shaders have only loop registers for relative
226 * addressing into inputs. Ignore the redundant address
227 * register, the contents of aL should be in sync with it.
228 */
229 if (reg->Register.File == TGSI_FILE_INPUT) {
230 src.base.relAddr = 1;
231 src.indirect = src_token(SVGA3DREG_LOOP, 0);
232 }
233 }
234 else {
235 /* Constant buffers only.
236 */
237 if (reg->Register.File == TGSI_FILE_CONSTANT) {
238 /* we shift the offset towards the minimum */
239 if (svga_arl_needs_adjustment( emit )) {
240 src.base.num -= svga_arl_adjustment( emit );
241 }
242 src.base.relAddr = 1;
243
244 /* Not really sure what should go in the second token:
245 */
246 src.indirect = src_token( SVGA3DREG_ADDR,
247 reg->Indirect.Index );
248
249 src.indirect.swizzle = SWIZZLE_XXXX;
250 }
251 }
252 }
253
254 src = swizzle( src,
255 reg->Register.SwizzleX,
256 reg->Register.SwizzleY,
257 reg->Register.SwizzleZ,
258 reg->Register.SwizzleW );
259
260 /* src.mod isn't a bitfield, unfortunately:
261 * See tgsi_util_get_full_src_register_sign_mode for implementation details.
262 */
263 if (reg->Register.Absolute) {
264 if (reg->Register.Negate)
265 src.base.srcMod = SVGA3DSRCMOD_ABSNEG;
266 else
267 src.base.srcMod = SVGA3DSRCMOD_ABS;
268 }
269 else {
270 if (reg->Register.Negate)
271 src.base.srcMod = SVGA3DSRCMOD_NEG;
272 else
273 src.base.srcMod = SVGA3DSRCMOD_NONE;
274 }
275
276 return src;
277 }
278
279
280 /*
281 * Get a temporary register.
282 * Note: if we exceed the temporary register limit we just use
283 * register SVGA3D_TEMPREG_MAX - 1.
284 */
285 static SVGA3dShaderDestToken
286 get_temp( struct svga_shader_emitter *emit )
287 {
288 int i = emit->nr_hw_temp + emit->internal_temp_count++;
289 if (i >= SVGA3D_TEMPREG_MAX) {
290 debug_warn_once("svga: Too many temporary registers used in shader\n");
291 i = SVGA3D_TEMPREG_MAX - 1;
292 }
293 return dst_register( SVGA3DREG_TEMP, i );
294 }
295
296
297 /**
298 * Release a single temp. Currently only effective if it was the last
299 * allocated temp, otherwise release will be delayed until the next
300 * call to reset_temp_regs().
301 */
302 static void
303 release_temp( struct svga_shader_emitter *emit,
304 SVGA3dShaderDestToken temp )
305 {
306 if (temp.num == emit->internal_temp_count - 1)
307 emit->internal_temp_count--;
308 }
309
310
311 /**
312 * Release all temps.
313 */
314 static void
315 reset_temp_regs(struct svga_shader_emitter *emit)
316 {
317 emit->internal_temp_count = 0;
318 }
319
320
321 /** Emit bytecode for a src_register */
322 static boolean
323 emit_src(struct svga_shader_emitter *emit, const struct src_register src)
324 {
325 if (src.base.relAddr) {
326 assert(src.base.reserved0);
327 assert(src.indirect.reserved0);
328 return (svga_shader_emit_dword( emit, src.base.value ) &&
329 svga_shader_emit_dword( emit, src.indirect.value ));
330 }
331 else {
332 assert(src.base.reserved0);
333 return svga_shader_emit_dword( emit, src.base.value );
334 }
335 }
336
337
338 /** Emit bytecode for a dst_register */
339 static boolean
340 emit_dst(struct svga_shader_emitter *emit, SVGA3dShaderDestToken dest)
341 {
342 assert(dest.reserved0);
343 assert(dest.mask);
344 return svga_shader_emit_dword( emit, dest.value );
345 }
346
347
348 /** Emit bytecode for a 1-operand instruction */
349 static boolean
350 emit_op1(struct svga_shader_emitter *emit,
351 SVGA3dShaderInstToken inst,
352 SVGA3dShaderDestToken dest,
353 struct src_register src0)
354 {
355 return (emit_instruction(emit, inst) &&
356 emit_dst(emit, dest) &&
357 emit_src(emit, src0));
358 }
359
360
361 /** Emit bytecode for a 2-operand instruction */
362 static boolean
363 emit_op2(struct svga_shader_emitter *emit,
364 SVGA3dShaderInstToken inst,
365 SVGA3dShaderDestToken dest,
366 struct src_register src0,
367 struct src_register src1)
368 {
369 return (emit_instruction(emit, inst) &&
370 emit_dst(emit, dest) &&
371 emit_src(emit, src0) &&
372 emit_src(emit, src1));
373 }
374
375
376 /** Emit bytecode for a 3-operand instruction */
377 static boolean
378 emit_op3(struct svga_shader_emitter *emit,
379 SVGA3dShaderInstToken inst,
380 SVGA3dShaderDestToken dest,
381 struct src_register src0,
382 struct src_register src1,
383 struct src_register src2)
384 {
385 return (emit_instruction(emit, inst) &&
386 emit_dst(emit, dest) &&
387 emit_src(emit, src0) &&
388 emit_src(emit, src1) &&
389 emit_src(emit, src2));
390 }
391
392
393 /** Emit bytecode for a 4-operand instruction */
394 static boolean
395 emit_op4(struct svga_shader_emitter *emit,
396 SVGA3dShaderInstToken inst,
397 SVGA3dShaderDestToken dest,
398 struct src_register src0,
399 struct src_register src1,
400 struct src_register src2,
401 struct src_register src3)
402 {
403 return (emit_instruction(emit, inst) &&
404 emit_dst(emit, dest) &&
405 emit_src(emit, src0) &&
406 emit_src(emit, src1) &&
407 emit_src(emit, src2) &&
408 emit_src(emit, src3));
409 }
410
411
412 /**
413 * Apply the absolute value modifier to the given src_register, returning
414 * a new src_register.
415 */
416 static struct src_register
417 absolute(struct src_register src)
418 {
419 src.base.srcMod = SVGA3DSRCMOD_ABS;
420 return src;
421 }
422
423
424 /**
425 * Apply the negation modifier to the given src_register, returning
426 * a new src_register.
427 */
428 static struct src_register
429 negate(struct src_register src)
430 {
431 switch (src.base.srcMod) {
432 case SVGA3DSRCMOD_ABS:
433 src.base.srcMod = SVGA3DSRCMOD_ABSNEG;
434 break;
435 case SVGA3DSRCMOD_ABSNEG:
436 src.base.srcMod = SVGA3DSRCMOD_ABS;
437 break;
438 case SVGA3DSRCMOD_NEG:
439 src.base.srcMod = SVGA3DSRCMOD_NONE;
440 break;
441 case SVGA3DSRCMOD_NONE:
442 src.base.srcMod = SVGA3DSRCMOD_NEG;
443 break;
444 }
445 return src;
446 }
447
448
449
450 /* Replace the src with the temporary specified in the dst, but copying
451 * only the necessary channels, and preserving the original swizzle (which is
452 * important given that several opcodes have constraints in the allowed
453 * swizzles).
454 */
455 static boolean
456 emit_repl(struct svga_shader_emitter *emit,
457 SVGA3dShaderDestToken dst,
458 struct src_register *src0)
459 {
460 unsigned src0_swizzle;
461 unsigned chan;
462
463 assert(SVGA3dShaderGetRegType(dst.value) == SVGA3DREG_TEMP);
464
465 src0_swizzle = src0->base.swizzle;
466
467 dst.mask = 0;
468 for (chan = 0; chan < 4; ++chan) {
469 unsigned swizzle = (src0_swizzle >> (chan *2)) & 0x3;
470 dst.mask |= 1 << swizzle;
471 }
472 assert(dst.mask);
473
474 src0->base.swizzle = SVGA3DSWIZZLE_NONE;
475
476 if (!emit_op1( emit, inst_token( SVGA3DOP_MOV ), dst, *src0 ))
477 return FALSE;
478
479 *src0 = src( dst );
480 src0->base.swizzle = src0_swizzle;
481
482 return TRUE;
483 }
484
485
486 /**
487 * Submit/emit an instruction with zero operands.
488 */
489 static boolean
490 submit_op0(struct svga_shader_emitter *emit,
491 SVGA3dShaderInstToken inst,
492 SVGA3dShaderDestToken dest)
493 {
494 return (emit_instruction( emit, inst ) &&
495 emit_dst( emit, dest ));
496 }
497
498
499 /**
500 * Submit/emit an instruction with one operand.
501 */
502 static boolean
503 submit_op1(struct svga_shader_emitter *emit,
504 SVGA3dShaderInstToken inst,
505 SVGA3dShaderDestToken dest,
506 struct src_register src0)
507 {
508 return emit_op1( emit, inst, dest, src0 );
509 }
510
511
512 /**
513 * Submit/emit an instruction with two operands.
514 *
515 * SVGA shaders may not refer to >1 constant register in a single
516 * instruction. This function checks for that usage and inserts a
517 * move to temporary if detected.
518 *
519 * The same applies to input registers -- at most a single input
520 * register may be read by any instruction.
521 */
522 static boolean
523 submit_op2(struct svga_shader_emitter *emit,
524 SVGA3dShaderInstToken inst,
525 SVGA3dShaderDestToken dest,
526 struct src_register src0,
527 struct src_register src1)
528 {
529 SVGA3dShaderDestToken temp;
530 SVGA3dShaderRegType type0, type1;
531 boolean need_temp = FALSE;
532
533 temp.value = 0;
534 type0 = SVGA3dShaderGetRegType( src0.base.value );
535 type1 = SVGA3dShaderGetRegType( src1.base.value );
536
537 if (type0 == SVGA3DREG_CONST &&
538 type1 == SVGA3DREG_CONST &&
539 src0.base.num != src1.base.num)
540 need_temp = TRUE;
541
542 if (type0 == SVGA3DREG_INPUT &&
543 type1 == SVGA3DREG_INPUT &&
544 src0.base.num != src1.base.num)
545 need_temp = TRUE;
546
547 if (need_temp) {
548 temp = get_temp( emit );
549
550 if (!emit_repl( emit, temp, &src0 ))
551 return FALSE;
552 }
553
554 if (!emit_op2( emit, inst, dest, src0, src1 ))
555 return FALSE;
556
557 if (need_temp)
558 release_temp( emit, temp );
559
560 return TRUE;
561 }
562
563
564 /**
565 * Submit/emit an instruction with three operands.
566 *
567 * SVGA shaders may not refer to >1 constant register in a single
568 * instruction. This function checks for that usage and inserts a
569 * move to temporary if detected.
570 */
571 static boolean
572 submit_op3(struct svga_shader_emitter *emit,
573 SVGA3dShaderInstToken inst,
574 SVGA3dShaderDestToken dest,
575 struct src_register src0,
576 struct src_register src1,
577 struct src_register src2)
578 {
579 SVGA3dShaderDestToken temp0;
580 SVGA3dShaderDestToken temp1;
581 boolean need_temp0 = FALSE;
582 boolean need_temp1 = FALSE;
583 SVGA3dShaderRegType type0, type1, type2;
584
585 temp0.value = 0;
586 temp1.value = 0;
587 type0 = SVGA3dShaderGetRegType( src0.base.value );
588 type1 = SVGA3dShaderGetRegType( src1.base.value );
589 type2 = SVGA3dShaderGetRegType( src2.base.value );
590
591 if (inst.op != SVGA3DOP_SINCOS) {
592 if (type0 == SVGA3DREG_CONST &&
593 ((type1 == SVGA3DREG_CONST && src0.base.num != src1.base.num) ||
594 (type2 == SVGA3DREG_CONST && src0.base.num != src2.base.num)))
595 need_temp0 = TRUE;
596
597 if (type1 == SVGA3DREG_CONST &&
598 (type2 == SVGA3DREG_CONST && src1.base.num != src2.base.num))
599 need_temp1 = TRUE;
600 }
601
602 if (type0 == SVGA3DREG_INPUT &&
603 ((type1 == SVGA3DREG_INPUT && src0.base.num != src1.base.num) ||
604 (type2 == SVGA3DREG_INPUT && src0.base.num != src2.base.num)))
605 need_temp0 = TRUE;
606
607 if (type1 == SVGA3DREG_INPUT &&
608 (type2 == SVGA3DREG_INPUT && src1.base.num != src2.base.num))
609 need_temp1 = TRUE;
610
611 if (need_temp0) {
612 temp0 = get_temp( emit );
613
614 if (!emit_repl( emit, temp0, &src0 ))
615 return FALSE;
616 }
617
618 if (need_temp1) {
619 temp1 = get_temp( emit );
620
621 if (!emit_repl( emit, temp1, &src1 ))
622 return FALSE;
623 }
624
625 if (!emit_op3( emit, inst, dest, src0, src1, src2 ))
626 return FALSE;
627
628 if (need_temp1)
629 release_temp( emit, temp1 );
630 if (need_temp0)
631 release_temp( emit, temp0 );
632 return TRUE;
633 }
634
635
636 /**
637 * Submit/emit an instruction with four operands.
638 *
639 * SVGA shaders may not refer to >1 constant register in a single
640 * instruction. This function checks for that usage and inserts a
641 * move to temporary if detected.
642 */
643 static boolean
644 submit_op4(struct svga_shader_emitter *emit,
645 SVGA3dShaderInstToken inst,
646 SVGA3dShaderDestToken dest,
647 struct src_register src0,
648 struct src_register src1,
649 struct src_register src2,
650 struct src_register src3)
651 {
652 SVGA3dShaderDestToken temp0;
653 SVGA3dShaderDestToken temp3;
654 boolean need_temp0 = FALSE;
655 boolean need_temp3 = FALSE;
656 SVGA3dShaderRegType type0, type1, type2, type3;
657
658 temp0.value = 0;
659 temp3.value = 0;
660 type0 = SVGA3dShaderGetRegType( src0.base.value );
661 type1 = SVGA3dShaderGetRegType( src1.base.value );
662 type2 = SVGA3dShaderGetRegType( src2.base.value );
663 type3 = SVGA3dShaderGetRegType( src2.base.value );
664
665 /* Make life a little easier - this is only used by the TXD
666 * instruction which is guaranteed not to have a constant/input reg
667 * in one slot at least:
668 */
669 assert(type1 == SVGA3DREG_SAMPLER);
670 (void) type1;
671
672 if (type0 == SVGA3DREG_CONST &&
673 ((type3 == SVGA3DREG_CONST && src0.base.num != src3.base.num) ||
674 (type2 == SVGA3DREG_CONST && src0.base.num != src2.base.num)))
675 need_temp0 = TRUE;
676
677 if (type3 == SVGA3DREG_CONST &&
678 (type2 == SVGA3DREG_CONST && src3.base.num != src2.base.num))
679 need_temp3 = TRUE;
680
681 if (type0 == SVGA3DREG_INPUT &&
682 ((type3 == SVGA3DREG_INPUT && src0.base.num != src3.base.num) ||
683 (type2 == SVGA3DREG_INPUT && src0.base.num != src2.base.num)))
684 need_temp0 = TRUE;
685
686 if (type3 == SVGA3DREG_INPUT &&
687 (type2 == SVGA3DREG_INPUT && src3.base.num != src2.base.num))
688 need_temp3 = TRUE;
689
690 if (need_temp0) {
691 temp0 = get_temp( emit );
692
693 if (!emit_repl( emit, temp0, &src0 ))
694 return FALSE;
695 }
696
697 if (need_temp3) {
698 temp3 = get_temp( emit );
699
700 if (!emit_repl( emit, temp3, &src3 ))
701 return FALSE;
702 }
703
704 if (!emit_op4( emit, inst, dest, src0, src1, src2, src3 ))
705 return FALSE;
706
707 if (need_temp3)
708 release_temp( emit, temp3 );
709 if (need_temp0)
710 release_temp( emit, temp0 );
711 return TRUE;
712 }
713
714
715 /**
716 * Do the src and dest registers refer to the same register?
717 */
718 static boolean
719 alias_src_dst(struct src_register src,
720 SVGA3dShaderDestToken dst)
721 {
722 if (src.base.num != dst.num)
723 return FALSE;
724
725 if (SVGA3dShaderGetRegType(dst.value) !=
726 SVGA3dShaderGetRegType(src.base.value))
727 return FALSE;
728
729 return TRUE;
730 }
731
732
733 /**
734 * Helper for emitting SVGA immediate values using the SVGA3DOP_DEF[I]
735 * instructions.
736 */
737 static boolean
738 emit_def_const(struct svga_shader_emitter *emit,
739 SVGA3dShaderConstType type,
740 unsigned idx, float a, float b, float c, float d)
741 {
742 SVGA3DOpDefArgs def;
743 SVGA3dShaderInstToken opcode;
744
745 switch (type) {
746 case SVGA3D_CONST_TYPE_FLOAT:
747 opcode = inst_token( SVGA3DOP_DEF );
748 def.dst = dst_register( SVGA3DREG_CONST, idx );
749 def.constValues[0] = a;
750 def.constValues[1] = b;
751 def.constValues[2] = c;
752 def.constValues[3] = d;
753 break;
754 case SVGA3D_CONST_TYPE_INT:
755 opcode = inst_token( SVGA3DOP_DEFI );
756 def.dst = dst_register( SVGA3DREG_CONSTINT, idx );
757 def.constIValues[0] = (int)a;
758 def.constIValues[1] = (int)b;
759 def.constIValues[2] = (int)c;
760 def.constIValues[3] = (int)d;
761 break;
762 default:
763 assert(0);
764 opcode = inst_token( SVGA3DOP_NOP );
765 break;
766 }
767
768 if (!emit_instruction(emit, opcode) ||
769 !svga_shader_emit_dwords( emit, def.values, ARRAY_SIZE(def.values)))
770 return FALSE;
771
772 return TRUE;
773 }
774
775
776 static boolean
777 create_loop_const( struct svga_shader_emitter *emit )
778 {
779 unsigned idx = emit->nr_hw_int_const++;
780
781 if (!emit_def_const( emit, SVGA3D_CONST_TYPE_INT, idx,
782 255, /* iteration count */
783 0, /* initial value */
784 1, /* step size */
785 0 /* not used, must be 0 */))
786 return FALSE;
787
788 emit->loop_const_idx = idx;
789 emit->created_loop_const = TRUE;
790
791 return TRUE;
792 }
793
794 static boolean
795 create_arl_consts( struct svga_shader_emitter *emit )
796 {
797 int i;
798
799 for (i = 0; i < emit->num_arl_consts; i += 4) {
800 int j;
801 unsigned idx = emit->nr_hw_float_const++;
802 float vals[4];
803 for (j = 0; j < 4 && (j + i) < emit->num_arl_consts; ++j) {
804 vals[j] = (float) emit->arl_consts[i + j].number;
805 emit->arl_consts[i + j].idx = idx;
806 switch (j) {
807 case 0:
808 emit->arl_consts[i + 0].swizzle = TGSI_SWIZZLE_X;
809 break;
810 case 1:
811 emit->arl_consts[i + 0].swizzle = TGSI_SWIZZLE_Y;
812 break;
813 case 2:
814 emit->arl_consts[i + 0].swizzle = TGSI_SWIZZLE_Z;
815 break;
816 case 3:
817 emit->arl_consts[i + 0].swizzle = TGSI_SWIZZLE_W;
818 break;
819 }
820 }
821 while (j < 4)
822 vals[j++] = 0;
823
824 if (!emit_def_const( emit, SVGA3D_CONST_TYPE_FLOAT, idx,
825 vals[0], vals[1],
826 vals[2], vals[3]))
827 return FALSE;
828 }
829
830 return TRUE;
831 }
832
833
834 /**
835 * Return the register which holds the pixel shaders front/back-
836 * facing value.
837 */
838 static struct src_register
839 get_vface( struct svga_shader_emitter *emit )
840 {
841 assert(emit->emitted_vface);
842 return src_register(SVGA3DREG_MISCTYPE, SVGA3DMISCREG_FACE);
843 }
844
845
846 /**
847 * Create/emit a "common" constant with values {0, 0.5, -1, 1}.
848 * We can swizzle this to produce other useful constants such as
849 * {0, 0, 0, 0}, {1, 1, 1, 1}, etc.
850 */
851 static boolean
852 create_common_immediate( struct svga_shader_emitter *emit )
853 {
854 unsigned idx = emit->nr_hw_float_const++;
855
856 /* Emit the constant (0, 0.5, -1, 1) and use swizzling to generate
857 * other useful vectors.
858 */
859 if (!emit_def_const( emit, SVGA3D_CONST_TYPE_FLOAT,
860 idx, 0.0f, 0.5f, -1.0f, 1.0f ))
861 return FALSE;
862 emit->common_immediate_idx[0] = idx;
863 idx++;
864
865 /* Emit constant {2, 0, 0, 0} (only the 2 is used for now) */
866 if (emit->key.vs.adjust_attrib_range) {
867 if (!emit_def_const( emit, SVGA3D_CONST_TYPE_FLOAT,
868 idx, 2.0f, 0.0f, 0.0f, 0.0f ))
869 return FALSE;
870 emit->common_immediate_idx[1] = idx;
871 }
872 else {
873 emit->common_immediate_idx[1] = -1;
874 }
875
876 emit->created_common_immediate = TRUE;
877
878 return TRUE;
879 }
880
881
882 /**
883 * Return swizzle/position for the given value in the "common" immediate.
884 */
885 static inline unsigned
886 common_immediate_swizzle(float value)
887 {
888 if (value == 0.0f)
889 return TGSI_SWIZZLE_X;
890 else if (value == 0.5f)
891 return TGSI_SWIZZLE_Y;
892 else if (value == -1.0f)
893 return TGSI_SWIZZLE_Z;
894 else if (value == 1.0f)
895 return TGSI_SWIZZLE_W;
896 else {
897 assert(!"illegal value in common_immediate_swizzle");
898 return TGSI_SWIZZLE_X;
899 }
900 }
901
902
903 /**
904 * Returns an immediate reg where all the terms are either 0, 1, 2 or 0.5
905 */
906 static struct src_register
907 get_immediate(struct svga_shader_emitter *emit,
908 float x, float y, float z, float w)
909 {
910 unsigned sx = common_immediate_swizzle(x);
911 unsigned sy = common_immediate_swizzle(y);
912 unsigned sz = common_immediate_swizzle(z);
913 unsigned sw = common_immediate_swizzle(w);
914 assert(emit->created_common_immediate);
915 assert(emit->common_immediate_idx[0] >= 0);
916 return swizzle(src_register(SVGA3DREG_CONST, emit->common_immediate_idx[0]),
917 sx, sy, sz, sw);
918 }
919
920
921 /**
922 * returns {0, 0, 0, 0} immediate
923 */
924 static struct src_register
925 get_zero_immediate( struct svga_shader_emitter *emit )
926 {
927 assert(emit->created_common_immediate);
928 assert(emit->common_immediate_idx[0] >= 0);
929 return swizzle(src_register( SVGA3DREG_CONST,
930 emit->common_immediate_idx[0]),
931 0, 0, 0, 0);
932 }
933
934
935 /**
936 * returns {1, 1, 1, 1} immediate
937 */
938 static struct src_register
939 get_one_immediate( struct svga_shader_emitter *emit )
940 {
941 assert(emit->created_common_immediate);
942 assert(emit->common_immediate_idx[0] >= 0);
943 return swizzle(src_register( SVGA3DREG_CONST,
944 emit->common_immediate_idx[0]),
945 3, 3, 3, 3);
946 }
947
948
949 /**
950 * returns {0.5, 0.5, 0.5, 0.5} immediate
951 */
952 static struct src_register
953 get_half_immediate( struct svga_shader_emitter *emit )
954 {
955 assert(emit->created_common_immediate);
956 assert(emit->common_immediate_idx[0] >= 0);
957 return swizzle(src_register(SVGA3DREG_CONST, emit->common_immediate_idx[0]),
958 1, 1, 1, 1);
959 }
960
961
962 /**
963 * returns {2, 2, 2, 2} immediate
964 */
965 static struct src_register
966 get_two_immediate( struct svga_shader_emitter *emit )
967 {
968 /* Note we use the second common immediate here */
969 assert(emit->created_common_immediate);
970 assert(emit->common_immediate_idx[1] >= 0);
971 return swizzle(src_register( SVGA3DREG_CONST,
972 emit->common_immediate_idx[1]),
973 0, 0, 0, 0);
974 }
975
976
977 /**
978 * returns the loop const
979 */
980 static struct src_register
981 get_loop_const( struct svga_shader_emitter *emit )
982 {
983 assert(emit->created_loop_const);
984 assert(emit->loop_const_idx >= 0);
985 return src_register( SVGA3DREG_CONSTINT,
986 emit->loop_const_idx );
987 }
988
989
990 static struct src_register
991 get_fake_arl_const( struct svga_shader_emitter *emit )
992 {
993 struct src_register reg;
994 int idx = 0, swizzle = 0, i;
995
996 for (i = 0; i < emit->num_arl_consts; ++ i) {
997 if (emit->arl_consts[i].arl_num == emit->current_arl) {
998 idx = emit->arl_consts[i].idx;
999 swizzle = emit->arl_consts[i].swizzle;
1000 }
1001 }
1002
1003 reg = src_register( SVGA3DREG_CONST, idx );
1004 return scalar(reg, swizzle);
1005 }
1006
1007
1008 /**
1009 * Return a register which holds the width and height of the texture
1010 * currently bound to the given sampler.
1011 */
1012 static struct src_register
1013 get_tex_dimensions( struct svga_shader_emitter *emit, int sampler_num )
1014 {
1015 int idx;
1016 struct src_register reg;
1017
1018 /* the width/height indexes start right after constants */
1019 idx = emit->key.tex[sampler_num].width_height_idx +
1020 emit->info.file_max[TGSI_FILE_CONSTANT] + 1;
1021
1022 reg = src_register( SVGA3DREG_CONST, idx );
1023 return reg;
1024 }
1025
1026
1027 static boolean
1028 emit_fake_arl(struct svga_shader_emitter *emit,
1029 const struct tgsi_full_instruction *insn)
1030 {
1031 const struct src_register src0 =
1032 translate_src_register(emit, &insn->Src[0] );
1033 struct src_register src1 = get_fake_arl_const( emit );
1034 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
1035 SVGA3dShaderDestToken tmp = get_temp( emit );
1036
1037 if (!submit_op1(emit, inst_token( SVGA3DOP_MOV ), tmp, src0))
1038 return FALSE;
1039
1040 if (!submit_op2( emit, inst_token( SVGA3DOP_ADD ), tmp, src( tmp ),
1041 src1))
1042 return FALSE;
1043
1044 /* replicate the original swizzle */
1045 src1 = src(tmp);
1046 src1.base.swizzle = src0.base.swizzle;
1047
1048 return submit_op1( emit, inst_token( SVGA3DOP_MOVA ),
1049 dst, src1 );
1050 }
1051
1052
1053 static boolean
1054 emit_if(struct svga_shader_emitter *emit,
1055 const struct tgsi_full_instruction *insn)
1056 {
1057 struct src_register src0 =
1058 translate_src_register(emit, &insn->Src[0]);
1059 struct src_register zero = get_zero_immediate(emit);
1060 SVGA3dShaderInstToken if_token = inst_token( SVGA3DOP_IFC );
1061
1062 if_token.control = SVGA3DOPCOMPC_NE;
1063
1064 if (SVGA3dShaderGetRegType(src0.base.value) == SVGA3DREG_CONST) {
1065 /*
1066 * Max different constant registers readable per IFC instruction is 1.
1067 */
1068 SVGA3dShaderDestToken tmp = get_temp( emit );
1069
1070 if (!submit_op1(emit, inst_token( SVGA3DOP_MOV ), tmp, src0))
1071 return FALSE;
1072
1073 src0 = scalar(src( tmp ), TGSI_SWIZZLE_X);
1074 }
1075
1076 emit->dynamic_branching_level++;
1077
1078 return (emit_instruction( emit, if_token ) &&
1079 emit_src( emit, src0 ) &&
1080 emit_src( emit, zero ) );
1081 }
1082
1083
1084 static boolean
1085 emit_else(struct svga_shader_emitter *emit,
1086 const struct tgsi_full_instruction *insn)
1087 {
1088 return emit_instruction(emit, inst_token(SVGA3DOP_ELSE));
1089 }
1090
1091
1092 static boolean
1093 emit_endif(struct svga_shader_emitter *emit,
1094 const struct tgsi_full_instruction *insn)
1095 {
1096 emit->dynamic_branching_level--;
1097
1098 return emit_instruction(emit, inst_token(SVGA3DOP_ENDIF));
1099 }
1100
1101
1102 /**
1103 * Translate the following TGSI FLR instruction.
1104 * FLR DST, SRC
1105 * To the following SVGA3D instruction sequence.
1106 * FRC TMP, SRC
1107 * SUB DST, SRC, TMP
1108 */
1109 static boolean
1110 emit_floor(struct svga_shader_emitter *emit,
1111 const struct tgsi_full_instruction *insn )
1112 {
1113 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
1114 const struct src_register src0 =
1115 translate_src_register(emit, &insn->Src[0] );
1116 SVGA3dShaderDestToken temp = get_temp( emit );
1117
1118 /* FRC TMP, SRC */
1119 if (!submit_op1( emit, inst_token( SVGA3DOP_FRC ), temp, src0 ))
1120 return FALSE;
1121
1122 /* SUB DST, SRC, TMP */
1123 if (!submit_op2( emit, inst_token( SVGA3DOP_ADD ), dst, src0,
1124 negate( src( temp ) ) ))
1125 return FALSE;
1126
1127 return TRUE;
1128 }
1129
1130
1131 /**
1132 * Translate the following TGSI CEIL instruction.
1133 * CEIL DST, SRC
1134 * To the following SVGA3D instruction sequence.
1135 * FRC TMP, -SRC
1136 * ADD DST, SRC, TMP
1137 */
1138 static boolean
1139 emit_ceil(struct svga_shader_emitter *emit,
1140 const struct tgsi_full_instruction *insn)
1141 {
1142 SVGA3dShaderDestToken dst = translate_dst_register(emit, insn, 0);
1143 const struct src_register src0 =
1144 translate_src_register(emit, &insn->Src[0]);
1145 SVGA3dShaderDestToken temp = get_temp(emit);
1146
1147 /* FRC TMP, -SRC */
1148 if (!submit_op1(emit, inst_token(SVGA3DOP_FRC), temp, negate(src0)))
1149 return FALSE;
1150
1151 /* ADD DST, SRC, TMP */
1152 if (!submit_op2(emit, inst_token(SVGA3DOP_ADD), dst, src0, src(temp)))
1153 return FALSE;
1154
1155 return TRUE;
1156 }
1157
1158
1159 /**
1160 * Translate the following TGSI DIV instruction.
1161 * DIV DST.xy, SRC0, SRC1
1162 * To the following SVGA3D instruction sequence.
1163 * RCP TMP.x, SRC1.xxxx
1164 * RCP TMP.y, SRC1.yyyy
1165 * MUL DST.xy, SRC0, TMP
1166 */
1167 static boolean
1168 emit_div(struct svga_shader_emitter *emit,
1169 const struct tgsi_full_instruction *insn )
1170 {
1171 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
1172 const struct src_register src0 =
1173 translate_src_register(emit, &insn->Src[0] );
1174 const struct src_register src1 =
1175 translate_src_register(emit, &insn->Src[1] );
1176 SVGA3dShaderDestToken temp = get_temp( emit );
1177 unsigned i;
1178
1179 /* For each enabled element, perform a RCP instruction. Note that
1180 * RCP is scalar in SVGA3D:
1181 */
1182 for (i = 0; i < 4; i++) {
1183 unsigned channel = 1 << i;
1184 if (dst.mask & channel) {
1185 /* RCP TMP.?, SRC1.???? */
1186 if (!submit_op1( emit, inst_token( SVGA3DOP_RCP ),
1187 writemask(temp, channel),
1188 scalar(src1, i) ))
1189 return FALSE;
1190 }
1191 }
1192
1193 /* Vector mul:
1194 * MUL DST, SRC0, TMP
1195 */
1196 if (!submit_op2( emit, inst_token( SVGA3DOP_MUL ), dst, src0,
1197 src( temp ) ))
1198 return FALSE;
1199
1200 return TRUE;
1201 }
1202
1203
1204 /**
1205 * Translate the following TGSI DP2 instruction.
1206 * DP2 DST, SRC1, SRC2
1207 * To the following SVGA3D instruction sequence.
1208 * MUL TMP, SRC1, SRC2
1209 * ADD DST, TMP.xxxx, TMP.yyyy
1210 */
1211 static boolean
1212 emit_dp2(struct svga_shader_emitter *emit,
1213 const struct tgsi_full_instruction *insn )
1214 {
1215 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
1216 const struct src_register src0 =
1217 translate_src_register(emit, &insn->Src[0]);
1218 const struct src_register src1 =
1219 translate_src_register(emit, &insn->Src[1]);
1220 SVGA3dShaderDestToken temp = get_temp( emit );
1221 struct src_register temp_src0, temp_src1;
1222
1223 /* MUL TMP, SRC1, SRC2 */
1224 if (!submit_op2( emit, inst_token( SVGA3DOP_MUL ), temp, src0, src1 ))
1225 return FALSE;
1226
1227 temp_src0 = scalar(src( temp ), TGSI_SWIZZLE_X);
1228 temp_src1 = scalar(src( temp ), TGSI_SWIZZLE_Y);
1229
1230 /* ADD DST, TMP.xxxx, TMP.yyyy */
1231 if (!submit_op2( emit, inst_token( SVGA3DOP_ADD ), dst,
1232 temp_src0, temp_src1 ))
1233 return FALSE;
1234
1235 return TRUE;
1236 }
1237
1238
1239 /**
1240 * Sine / Cosine helper function.
1241 */
1242 static boolean
1243 do_emit_sincos(struct svga_shader_emitter *emit,
1244 SVGA3dShaderDestToken dst,
1245 struct src_register src0)
1246 {
1247 src0 = scalar(src0, TGSI_SWIZZLE_X);
1248 return submit_op1(emit, inst_token(SVGA3DOP_SINCOS), dst, src0);
1249 }
1250
1251
1252 /**
1253 * Translate/emit a TGSI SIN, COS or CSC instruction.
1254 */
1255 static boolean
1256 emit_sincos(struct svga_shader_emitter *emit,
1257 const struct tgsi_full_instruction *insn)
1258 {
1259 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
1260 struct src_register src0 = translate_src_register(emit, &insn->Src[0]);
1261 SVGA3dShaderDestToken temp = get_temp( emit );
1262
1263 /* SCS TMP SRC */
1264 if (!do_emit_sincos(emit, writemask(temp, TGSI_WRITEMASK_XY), src0 ))
1265 return FALSE;
1266
1267 /* MOV DST TMP */
1268 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ), dst, src( temp ) ))
1269 return FALSE;
1270
1271 return TRUE;
1272 }
1273
1274
1275 /**
1276 * Translate TGSI SIN instruction into:
1277 * SCS TMP SRC
1278 * MOV DST TMP.yyyy
1279 */
1280 static boolean
1281 emit_sin(struct svga_shader_emitter *emit,
1282 const struct tgsi_full_instruction *insn )
1283 {
1284 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
1285 struct src_register src0 =
1286 translate_src_register(emit, &insn->Src[0] );
1287 SVGA3dShaderDestToken temp = get_temp( emit );
1288
1289 /* SCS TMP SRC */
1290 if (!do_emit_sincos(emit, writemask(temp, TGSI_WRITEMASK_Y), src0))
1291 return FALSE;
1292
1293 src0 = scalar(src( temp ), TGSI_SWIZZLE_Y);
1294
1295 /* MOV DST TMP.yyyy */
1296 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ), dst, src0 ))
1297 return FALSE;
1298
1299 return TRUE;
1300 }
1301
1302
1303 /*
1304 * Translate TGSI COS instruction into:
1305 * SCS TMP SRC
1306 * MOV DST TMP.xxxx
1307 */
1308 static boolean
1309 emit_cos(struct svga_shader_emitter *emit,
1310 const struct tgsi_full_instruction *insn)
1311 {
1312 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
1313 struct src_register src0 =
1314 translate_src_register(emit, &insn->Src[0] );
1315 SVGA3dShaderDestToken temp = get_temp( emit );
1316
1317 /* SCS TMP SRC */
1318 if (!do_emit_sincos( emit, writemask(temp, TGSI_WRITEMASK_X), src0 ))
1319 return FALSE;
1320
1321 src0 = scalar(src( temp ), TGSI_SWIZZLE_X);
1322
1323 /* MOV DST TMP.xxxx */
1324 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ), dst, src0 ))
1325 return FALSE;
1326
1327 return TRUE;
1328 }
1329
1330
1331 /**
1332 * Translate/emit TGSI SSG (Set Sign: -1, 0, +1) instruction.
1333 */
1334 static boolean
1335 emit_ssg(struct svga_shader_emitter *emit,
1336 const struct tgsi_full_instruction *insn)
1337 {
1338 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
1339 struct src_register src0 =
1340 translate_src_register(emit, &insn->Src[0] );
1341 SVGA3dShaderDestToken temp0 = get_temp( emit );
1342 SVGA3dShaderDestToken temp1 = get_temp( emit );
1343 struct src_register zero, one;
1344
1345 if (emit->unit == PIPE_SHADER_VERTEX) {
1346 /* SGN DST, SRC0, TMP0, TMP1 */
1347 return submit_op3( emit, inst_token( SVGA3DOP_SGN ), dst, src0,
1348 src( temp0 ), src( temp1 ) );
1349 }
1350
1351 one = get_one_immediate(emit);
1352 zero = get_zero_immediate(emit);
1353
1354 /* CMP TMP0, SRC0, one, zero */
1355 if (!submit_op3( emit, inst_token( SVGA3DOP_CMP ),
1356 writemask( temp0, dst.mask ), src0, one, zero ))
1357 return FALSE;
1358
1359 /* CMP TMP1, negate(SRC0), negate(one), zero */
1360 if (!submit_op3( emit, inst_token( SVGA3DOP_CMP ),
1361 writemask( temp1, dst.mask ), negate( src0 ), negate( one ),
1362 zero ))
1363 return FALSE;
1364
1365 /* ADD DST, TMP0, TMP1 */
1366 return submit_op2( emit, inst_token( SVGA3DOP_ADD ), dst, src( temp0 ),
1367 src( temp1 ) );
1368 }
1369
1370
1371 /**
1372 * Translate/emit KILL_IF instruction (kill if any of X,Y,Z,W are negative).
1373 */
1374 static boolean
1375 emit_kill_if(struct svga_shader_emitter *emit,
1376 const struct tgsi_full_instruction *insn)
1377 {
1378 const struct tgsi_full_src_register *reg = &insn->Src[0];
1379 struct src_register src0, srcIn;
1380 const boolean special = (reg->Register.Absolute ||
1381 reg->Register.Negate ||
1382 reg->Register.Indirect ||
1383 reg->Register.SwizzleX != 0 ||
1384 reg->Register.SwizzleY != 1 ||
1385 reg->Register.SwizzleZ != 2 ||
1386 reg->Register.File != TGSI_FILE_TEMPORARY);
1387 SVGA3dShaderDestToken temp;
1388
1389 src0 = srcIn = translate_src_register( emit, reg );
1390
1391 if (special) {
1392 /* need a temp reg */
1393 temp = get_temp( emit );
1394 }
1395
1396 if (special) {
1397 /* move the source into a temp register */
1398 submit_op1(emit, inst_token(SVGA3DOP_MOV), temp, src0);
1399
1400 src0 = src( temp );
1401 }
1402
1403 /* Do the texkill by checking if any of the XYZW components are < 0.
1404 * Note that ps_2_0 and later take XYZW in consideration, while ps_1_x
1405 * only used XYZ. The MSDN documentation about this is incorrect.
1406 */
1407 if (!submit_op0( emit, inst_token( SVGA3DOP_TEXKILL ), dst(src0) ))
1408 return FALSE;
1409
1410 return TRUE;
1411 }
1412
1413
1414 /**
1415 * Translate/emit unconditional kill instruction (usually found inside
1416 * an IF/ELSE/ENDIF block).
1417 */
1418 static boolean
1419 emit_kill(struct svga_shader_emitter *emit,
1420 const struct tgsi_full_instruction *insn)
1421 {
1422 SVGA3dShaderDestToken temp;
1423 struct src_register one = get_one_immediate(emit);
1424 SVGA3dShaderInstToken inst = inst_token( SVGA3DOP_TEXKILL );
1425
1426 /* texkill doesn't allow negation on the operand so lets move
1427 * negation of {1} to a temp register */
1428 temp = get_temp( emit );
1429 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ), temp,
1430 negate( one ) ))
1431 return FALSE;
1432
1433 return submit_op0( emit, inst, temp );
1434 }
1435
1436
1437 /**
1438 * Test if r1 and r2 are the same register.
1439 */
1440 static boolean
1441 same_register(struct src_register r1, struct src_register r2)
1442 {
1443 return (r1.base.num == r2.base.num &&
1444 r1.base.type_upper == r2.base.type_upper &&
1445 r1.base.type_lower == r2.base.type_lower);
1446 }
1447
1448
1449
1450 /**
1451 * Implement conditionals by initializing destination reg to 'fail',
1452 * then set predicate reg with UFOP_SETP, then move 'pass' to dest
1453 * based on predicate reg.
1454 *
1455 * SETP src0, cmp, src1 -- do this first to avoid aliasing problems.
1456 * MOV dst, fail
1457 * MOV dst, pass, p0
1458 */
1459 static boolean
1460 emit_conditional(struct svga_shader_emitter *emit,
1461 unsigned compare_func,
1462 SVGA3dShaderDestToken dst,
1463 struct src_register src0,
1464 struct src_register src1,
1465 struct src_register pass,
1466 struct src_register fail)
1467 {
1468 SVGA3dShaderDestToken pred_reg = dst_register( SVGA3DREG_PREDICATE, 0 );
1469 SVGA3dShaderInstToken setp_token;
1470
1471 switch (compare_func) {
1472 case PIPE_FUNC_NEVER:
1473 return submit_op1( emit, inst_token( SVGA3DOP_MOV ),
1474 dst, fail );
1475 break;
1476 case PIPE_FUNC_LESS:
1477 setp_token = inst_token_setp(SVGA3DOPCOMP_LT);
1478 break;
1479 case PIPE_FUNC_EQUAL:
1480 setp_token = inst_token_setp(SVGA3DOPCOMP_EQ);
1481 break;
1482 case PIPE_FUNC_LEQUAL:
1483 setp_token = inst_token_setp(SVGA3DOPCOMP_LE);
1484 break;
1485 case PIPE_FUNC_GREATER:
1486 setp_token = inst_token_setp(SVGA3DOPCOMP_GT);
1487 break;
1488 case PIPE_FUNC_NOTEQUAL:
1489 setp_token = inst_token_setp(SVGA3DOPCOMPC_NE);
1490 break;
1491 case PIPE_FUNC_GEQUAL:
1492 setp_token = inst_token_setp(SVGA3DOPCOMP_GE);
1493 break;
1494 case PIPE_FUNC_ALWAYS:
1495 return submit_op1( emit, inst_token( SVGA3DOP_MOV ),
1496 dst, pass );
1497 break;
1498 }
1499
1500 if (same_register(src(dst), pass)) {
1501 /* We'll get bad results if the dst and pass registers are the same
1502 * so use a temp register containing pass.
1503 */
1504 SVGA3dShaderDestToken temp = get_temp(emit);
1505 if (!submit_op1(emit, inst_token(SVGA3DOP_MOV), temp, pass))
1506 return FALSE;
1507 pass = src(temp);
1508 }
1509
1510 /* SETP src0, COMPOP, src1 */
1511 if (!submit_op2( emit, setp_token, pred_reg,
1512 src0, src1 ))
1513 return FALSE;
1514
1515 /* MOV dst, fail */
1516 if (!submit_op1(emit, inst_token(SVGA3DOP_MOV), dst, fail))
1517 return FALSE;
1518
1519 /* MOV dst, pass (predicated)
1520 *
1521 * Note that the predicate reg (and possible modifiers) is passed
1522 * as the first source argument.
1523 */
1524 if (!submit_op2(emit,
1525 inst_token_predicated(SVGA3DOP_MOV), dst,
1526 src(pred_reg), pass))
1527 return FALSE;
1528
1529 return TRUE;
1530 }
1531
1532
1533 /**
1534 * Helper for emiting 'selection' commands. Basically:
1535 * if (src0 OP src1)
1536 * dst = 1.0;
1537 * else
1538 * dst = 0.0;
1539 */
1540 static boolean
1541 emit_select(struct svga_shader_emitter *emit,
1542 unsigned compare_func,
1543 SVGA3dShaderDestToken dst,
1544 struct src_register src0,
1545 struct src_register src1 )
1546 {
1547 /* There are some SVGA instructions which implement some selects
1548 * directly, but they are only available in the vertex shader.
1549 */
1550 if (emit->unit == PIPE_SHADER_VERTEX) {
1551 switch (compare_func) {
1552 case PIPE_FUNC_GEQUAL:
1553 return submit_op2( emit, inst_token( SVGA3DOP_SGE ), dst, src0, src1 );
1554 case PIPE_FUNC_LEQUAL:
1555 return submit_op2( emit, inst_token( SVGA3DOP_SGE ), dst, src1, src0 );
1556 case PIPE_FUNC_GREATER:
1557 return submit_op2( emit, inst_token( SVGA3DOP_SLT ), dst, src1, src0 );
1558 case PIPE_FUNC_LESS:
1559 return submit_op2( emit, inst_token( SVGA3DOP_SLT ), dst, src0, src1 );
1560 default:
1561 break;
1562 }
1563 }
1564
1565 /* Otherwise, need to use the setp approach:
1566 */
1567 {
1568 struct src_register one, zero;
1569 /* zero immediate is 0,0,0,1 */
1570 zero = get_zero_immediate(emit);
1571 one = get_one_immediate(emit);
1572
1573 return emit_conditional(emit, compare_func, dst, src0, src1, one, zero);
1574 }
1575 }
1576
1577
1578 /**
1579 * Translate/emit a TGSI SEQ, SNE, SLT, SGE, etc. instruction.
1580 */
1581 static boolean
1582 emit_select_op(struct svga_shader_emitter *emit,
1583 unsigned compare,
1584 const struct tgsi_full_instruction *insn)
1585 {
1586 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
1587 struct src_register src0 = translate_src_register(
1588 emit, &insn->Src[0] );
1589 struct src_register src1 = translate_src_register(
1590 emit, &insn->Src[1] );
1591
1592 return emit_select( emit, compare, dst, src0, src1 );
1593 }
1594
1595
1596 /**
1597 * Translate TGSI CMP instruction. Component-wise:
1598 * dst = (src0 < 0.0) ? src1 : src2
1599 */
1600 static boolean
1601 emit_cmp(struct svga_shader_emitter *emit,
1602 const struct tgsi_full_instruction *insn)
1603 {
1604 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
1605 const struct src_register src0 =
1606 translate_src_register(emit, &insn->Src[0] );
1607 const struct src_register src1 =
1608 translate_src_register(emit, &insn->Src[1] );
1609 const struct src_register src2 =
1610 translate_src_register(emit, &insn->Src[2] );
1611
1612 if (emit->unit == PIPE_SHADER_VERTEX) {
1613 struct src_register zero = get_zero_immediate(emit);
1614 /* We used to simulate CMP with SLT+LRP. But that didn't work when
1615 * src1 or src2 was Inf/NaN. In particular, GLSL sqrt(0) failed
1616 * because it involves a CMP to handle the 0 case.
1617 * Use a conditional expression instead.
1618 */
1619 return emit_conditional(emit, PIPE_FUNC_LESS, dst,
1620 src0, zero, src1, src2);
1621 }
1622 else {
1623 assert(emit->unit == PIPE_SHADER_FRAGMENT);
1624
1625 /* CMP DST, SRC0, SRC2, SRC1 */
1626 return submit_op3( emit, inst_token( SVGA3DOP_CMP ), dst,
1627 src0, src2, src1);
1628 }
1629 }
1630
1631
1632 /**
1633 * Translate/emit 2-operand (coord, sampler) texture instructions.
1634 */
1635 static boolean
1636 emit_tex2(struct svga_shader_emitter *emit,
1637 const struct tgsi_full_instruction *insn,
1638 SVGA3dShaderDestToken dst)
1639 {
1640 SVGA3dShaderInstToken inst;
1641 struct src_register texcoord;
1642 struct src_register sampler;
1643 SVGA3dShaderDestToken tmp;
1644
1645 inst.value = 0;
1646
1647 switch (insn->Instruction.Opcode) {
1648 case TGSI_OPCODE_TEX:
1649 inst.op = SVGA3DOP_TEX;
1650 break;
1651 case TGSI_OPCODE_TXP:
1652 inst.op = SVGA3DOP_TEX;
1653 inst.control = SVGA3DOPCONT_PROJECT;
1654 break;
1655 case TGSI_OPCODE_TXB:
1656 inst.op = SVGA3DOP_TEX;
1657 inst.control = SVGA3DOPCONT_BIAS;
1658 break;
1659 case TGSI_OPCODE_TXL:
1660 inst.op = SVGA3DOP_TEXLDL;
1661 break;
1662 default:
1663 assert(0);
1664 return FALSE;
1665 }
1666
1667 texcoord = translate_src_register( emit, &insn->Src[0] );
1668 sampler = translate_src_register( emit, &insn->Src[1] );
1669
1670 if (emit->key.tex[sampler.base.num].unnormalized ||
1671 emit->dynamic_branching_level > 0)
1672 tmp = get_temp( emit );
1673
1674 /* Can't do mipmapping inside dynamic branch constructs. Force LOD
1675 * zero in that case.
1676 */
1677 if (emit->dynamic_branching_level > 0 &&
1678 inst.op == SVGA3DOP_TEX &&
1679 SVGA3dShaderGetRegType(texcoord.base.value) == SVGA3DREG_TEMP) {
1680 struct src_register zero = get_zero_immediate(emit);
1681
1682 /* MOV tmp, texcoord */
1683 if (!submit_op1( emit,
1684 inst_token( SVGA3DOP_MOV ),
1685 tmp,
1686 texcoord ))
1687 return FALSE;
1688
1689 /* MOV tmp.w, zero */
1690 if (!submit_op1( emit,
1691 inst_token( SVGA3DOP_MOV ),
1692 writemask( tmp, TGSI_WRITEMASK_W ),
1693 zero ))
1694 return FALSE;
1695
1696 texcoord = src( tmp );
1697 inst.op = SVGA3DOP_TEXLDL;
1698 }
1699
1700 /* Explicit normalization of texcoords:
1701 */
1702 if (emit->key.tex[sampler.base.num].unnormalized) {
1703 struct src_register wh = get_tex_dimensions( emit, sampler.base.num );
1704
1705 /* MUL tmp, SRC0, WH */
1706 if (!submit_op2( emit, inst_token( SVGA3DOP_MUL ),
1707 tmp, texcoord, wh ))
1708 return FALSE;
1709
1710 texcoord = src( tmp );
1711 }
1712
1713 return submit_op2( emit, inst, dst, texcoord, sampler );
1714 }
1715
1716
1717 /**
1718 * Translate/emit 4-operand (coord, ddx, ddy, sampler) texture instructions.
1719 */
1720 static boolean
1721 emit_tex4(struct svga_shader_emitter *emit,
1722 const struct tgsi_full_instruction *insn,
1723 SVGA3dShaderDestToken dst )
1724 {
1725 SVGA3dShaderInstToken inst;
1726 struct src_register texcoord;
1727 struct src_register ddx;
1728 struct src_register ddy;
1729 struct src_register sampler;
1730
1731 texcoord = translate_src_register( emit, &insn->Src[0] );
1732 ddx = translate_src_register( emit, &insn->Src[1] );
1733 ddy = translate_src_register( emit, &insn->Src[2] );
1734 sampler = translate_src_register( emit, &insn->Src[3] );
1735
1736 inst.value = 0;
1737
1738 switch (insn->Instruction.Opcode) {
1739 case TGSI_OPCODE_TXD:
1740 inst.op = SVGA3DOP_TEXLDD; /* 4 args! */
1741 break;
1742 default:
1743 assert(0);
1744 return FALSE;
1745 }
1746
1747 return submit_op4( emit, inst, dst, texcoord, sampler, ddx, ddy );
1748 }
1749
1750
1751 /**
1752 * Emit texture swizzle code. We do this here since SVGA samplers don't
1753 * directly support swizzles.
1754 */
1755 static boolean
1756 emit_tex_swizzle(struct svga_shader_emitter *emit,
1757 SVGA3dShaderDestToken dst,
1758 struct src_register src,
1759 unsigned swizzle_x,
1760 unsigned swizzle_y,
1761 unsigned swizzle_z,
1762 unsigned swizzle_w)
1763 {
1764 const unsigned swizzleIn[4] = {swizzle_x, swizzle_y, swizzle_z, swizzle_w};
1765 unsigned srcSwizzle[4];
1766 unsigned srcWritemask = 0x0, zeroWritemask = 0x0, oneWritemask = 0x0;
1767 unsigned i;
1768
1769 /* build writemasks and srcSwizzle terms */
1770 for (i = 0; i < 4; i++) {
1771 if (swizzleIn[i] == PIPE_SWIZZLE_0) {
1772 srcSwizzle[i] = TGSI_SWIZZLE_X + i;
1773 zeroWritemask |= (1 << i);
1774 }
1775 else if (swizzleIn[i] == PIPE_SWIZZLE_1) {
1776 srcSwizzle[i] = TGSI_SWIZZLE_X + i;
1777 oneWritemask |= (1 << i);
1778 }
1779 else {
1780 srcSwizzle[i] = swizzleIn[i];
1781 srcWritemask |= (1 << i);
1782 }
1783 }
1784
1785 /* write x/y/z/w comps */
1786 if (dst.mask & srcWritemask) {
1787 if (!submit_op1(emit,
1788 inst_token(SVGA3DOP_MOV),
1789 writemask(dst, srcWritemask),
1790 swizzle(src,
1791 srcSwizzle[0],
1792 srcSwizzle[1],
1793 srcSwizzle[2],
1794 srcSwizzle[3])))
1795 return FALSE;
1796 }
1797
1798 /* write 0 comps */
1799 if (dst.mask & zeroWritemask) {
1800 if (!submit_op1(emit,
1801 inst_token(SVGA3DOP_MOV),
1802 writemask(dst, zeroWritemask),
1803 get_zero_immediate(emit)))
1804 return FALSE;
1805 }
1806
1807 /* write 1 comps */
1808 if (dst.mask & oneWritemask) {
1809 if (!submit_op1(emit,
1810 inst_token(SVGA3DOP_MOV),
1811 writemask(dst, oneWritemask),
1812 get_one_immediate(emit)))
1813 return FALSE;
1814 }
1815
1816 return TRUE;
1817 }
1818
1819
1820 /**
1821 * Translate/emit a TGSI texture sample instruction.
1822 */
1823 static boolean
1824 emit_tex(struct svga_shader_emitter *emit,
1825 const struct tgsi_full_instruction *insn)
1826 {
1827 SVGA3dShaderDestToken dst =
1828 translate_dst_register( emit, insn, 0 );
1829 struct src_register src0 =
1830 translate_src_register( emit, &insn->Src[0] );
1831 struct src_register src1 =
1832 translate_src_register( emit, &insn->Src[1] );
1833
1834 SVGA3dShaderDestToken tex_result;
1835 const unsigned unit = src1.base.num;
1836
1837 /* check for shadow samplers */
1838 boolean compare = (emit->key.tex[unit].compare_mode ==
1839 PIPE_TEX_COMPARE_R_TO_TEXTURE);
1840
1841 /* texture swizzle */
1842 boolean swizzle = (emit->key.tex[unit].swizzle_r != PIPE_SWIZZLE_X ||
1843 emit->key.tex[unit].swizzle_g != PIPE_SWIZZLE_Y ||
1844 emit->key.tex[unit].swizzle_b != PIPE_SWIZZLE_Z ||
1845 emit->key.tex[unit].swizzle_a != PIPE_SWIZZLE_W);
1846
1847 boolean saturate = insn->Instruction.Saturate;
1848
1849 /* If doing compare processing or tex swizzle or saturation, we need to put
1850 * the fetched color into a temporary so it can be used as a source later on.
1851 */
1852 if (compare || swizzle || saturate) {
1853 tex_result = get_temp( emit );
1854 }
1855 else {
1856 tex_result = dst;
1857 }
1858
1859 switch(insn->Instruction.Opcode) {
1860 case TGSI_OPCODE_TEX:
1861 case TGSI_OPCODE_TXB:
1862 case TGSI_OPCODE_TXP:
1863 case TGSI_OPCODE_TXL:
1864 if (!emit_tex2( emit, insn, tex_result ))
1865 return FALSE;
1866 break;
1867 case TGSI_OPCODE_TXD:
1868 if (!emit_tex4( emit, insn, tex_result ))
1869 return FALSE;
1870 break;
1871 default:
1872 assert(0);
1873 }
1874
1875 if (compare) {
1876 SVGA3dShaderDestToken dst2;
1877
1878 if (swizzle || saturate)
1879 dst2 = tex_result;
1880 else
1881 dst2 = dst;
1882
1883 if (dst.mask & TGSI_WRITEMASK_XYZ) {
1884 SVGA3dShaderDestToken src0_zdivw = get_temp( emit );
1885 /* When sampling a depth texture, the result of the comparison is in
1886 * the Y component.
1887 */
1888 struct src_register tex_src_x = scalar(src(tex_result), TGSI_SWIZZLE_Y);
1889 struct src_register r_coord;
1890
1891 if (insn->Instruction.Opcode == TGSI_OPCODE_TXP) {
1892 /* Divide texcoord R by Q */
1893 if (!submit_op1( emit, inst_token( SVGA3DOP_RCP ),
1894 writemask(src0_zdivw, TGSI_WRITEMASK_X),
1895 scalar(src0, TGSI_SWIZZLE_W) ))
1896 return FALSE;
1897
1898 if (!submit_op2( emit, inst_token( SVGA3DOP_MUL ),
1899 writemask(src0_zdivw, TGSI_WRITEMASK_X),
1900 scalar(src0, TGSI_SWIZZLE_Z),
1901 scalar(src(src0_zdivw), TGSI_SWIZZLE_X) ))
1902 return FALSE;
1903
1904 r_coord = scalar(src(src0_zdivw), TGSI_SWIZZLE_X);
1905 }
1906 else {
1907 r_coord = scalar(src0, TGSI_SWIZZLE_Z);
1908 }
1909
1910 /* Compare texture sample value against R component of texcoord */
1911 if (!emit_select(emit,
1912 emit->key.tex[unit].compare_func,
1913 writemask( dst2, TGSI_WRITEMASK_XYZ ),
1914 r_coord,
1915 tex_src_x))
1916 return FALSE;
1917 }
1918
1919 if (dst.mask & TGSI_WRITEMASK_W) {
1920 struct src_register one = get_one_immediate(emit);
1921
1922 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ),
1923 writemask( dst2, TGSI_WRITEMASK_W ),
1924 one ))
1925 return FALSE;
1926 }
1927 }
1928
1929 if (saturate && !swizzle) {
1930 /* MOV_SAT real_dst, dst */
1931 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ), dst, src(tex_result) ))
1932 return FALSE;
1933 }
1934 else if (swizzle) {
1935 /* swizzle from tex_result to dst (handles saturation too, if any) */
1936 emit_tex_swizzle(emit,
1937 dst, src(tex_result),
1938 emit->key.tex[unit].swizzle_r,
1939 emit->key.tex[unit].swizzle_g,
1940 emit->key.tex[unit].swizzle_b,
1941 emit->key.tex[unit].swizzle_a);
1942 }
1943
1944 return TRUE;
1945 }
1946
1947
1948 static boolean
1949 emit_bgnloop(struct svga_shader_emitter *emit,
1950 const struct tgsi_full_instruction *insn)
1951 {
1952 SVGA3dShaderInstToken inst = inst_token( SVGA3DOP_LOOP );
1953 struct src_register loop_reg = src_register( SVGA3DREG_LOOP, 0 );
1954 struct src_register const_int = get_loop_const( emit );
1955
1956 emit->dynamic_branching_level++;
1957
1958 return (emit_instruction( emit, inst ) &&
1959 emit_src( emit, loop_reg ) &&
1960 emit_src( emit, const_int ) );
1961 }
1962
1963
1964 static boolean
1965 emit_endloop(struct svga_shader_emitter *emit,
1966 const struct tgsi_full_instruction *insn)
1967 {
1968 SVGA3dShaderInstToken inst = inst_token( SVGA3DOP_ENDLOOP );
1969
1970 emit->dynamic_branching_level--;
1971
1972 return emit_instruction( emit, inst );
1973 }
1974
1975
1976 /**
1977 * Translate/emit TGSI BREAK (out of loop) instruction.
1978 */
1979 static boolean
1980 emit_brk(struct svga_shader_emitter *emit,
1981 const struct tgsi_full_instruction *insn)
1982 {
1983 SVGA3dShaderInstToken inst = inst_token( SVGA3DOP_BREAK );
1984 return emit_instruction( emit, inst );
1985 }
1986
1987
1988 /**
1989 * Emit simple instruction which operates on one scalar value (not
1990 * a vector). Ex: LG2, RCP, RSQ.
1991 */
1992 static boolean
1993 emit_scalar_op1(struct svga_shader_emitter *emit,
1994 unsigned opcode,
1995 const struct tgsi_full_instruction *insn)
1996 {
1997 SVGA3dShaderInstToken inst;
1998 SVGA3dShaderDestToken dst;
1999 struct src_register src;
2000
2001 inst = inst_token( opcode );
2002 dst = translate_dst_register( emit, insn, 0 );
2003 src = translate_src_register( emit, &insn->Src[0] );
2004 src = scalar( src, TGSI_SWIZZLE_X );
2005
2006 return submit_op1( emit, inst, dst, src );
2007 }
2008
2009
2010 /**
2011 * Translate/emit a simple instruction (one which has no special-case
2012 * code) such as ADD, MUL, MIN, MAX.
2013 */
2014 static boolean
2015 emit_simple_instruction(struct svga_shader_emitter *emit,
2016 unsigned opcode,
2017 const struct tgsi_full_instruction *insn)
2018 {
2019 const struct tgsi_full_src_register *src = insn->Src;
2020 SVGA3dShaderInstToken inst;
2021 SVGA3dShaderDestToken dst;
2022
2023 inst = inst_token( opcode );
2024 dst = translate_dst_register( emit, insn, 0 );
2025
2026 switch (insn->Instruction.NumSrcRegs) {
2027 case 0:
2028 return submit_op0( emit, inst, dst );
2029 case 1:
2030 return submit_op1( emit, inst, dst,
2031 translate_src_register( emit, &src[0] ));
2032 case 2:
2033 return submit_op2( emit, inst, dst,
2034 translate_src_register( emit, &src[0] ),
2035 translate_src_register( emit, &src[1] ) );
2036 case 3:
2037 return submit_op3( emit, inst, dst,
2038 translate_src_register( emit, &src[0] ),
2039 translate_src_register( emit, &src[1] ),
2040 translate_src_register( emit, &src[2] ) );
2041 default:
2042 assert(0);
2043 return FALSE;
2044 }
2045 }
2046
2047
2048 /**
2049 * TGSI_OPCODE_MOVE is only special-cased here to detect the
2050 * svga_fragment_shader::constant_color_output case.
2051 */
2052 static boolean
2053 emit_mov(struct svga_shader_emitter *emit,
2054 const struct tgsi_full_instruction *insn)
2055 {
2056 const struct tgsi_full_src_register *src = &insn->Src[0];
2057 const struct tgsi_full_dst_register *dst = &insn->Dst[0];
2058
2059 if (emit->unit == PIPE_SHADER_FRAGMENT &&
2060 dst->Register.File == TGSI_FILE_OUTPUT &&
2061 dst->Register.Index == 0 &&
2062 src->Register.File == TGSI_FILE_CONSTANT &&
2063 !src->Register.Indirect) {
2064 emit->constant_color_output = TRUE;
2065 }
2066
2067 return emit_simple_instruction(emit, SVGA3DOP_MOV, insn);
2068 }
2069
2070
2071 /**
2072 * Translate/emit TGSI DDX, DDY instructions.
2073 */
2074 static boolean
2075 emit_deriv(struct svga_shader_emitter *emit,
2076 const struct tgsi_full_instruction *insn )
2077 {
2078 if (emit->dynamic_branching_level > 0 &&
2079 insn->Src[0].Register.File == TGSI_FILE_TEMPORARY)
2080 {
2081 SVGA3dShaderDestToken dst =
2082 translate_dst_register( emit, insn, 0 );
2083
2084 /* Deriv opcodes not valid inside dynamic branching, workaround
2085 * by zeroing out the destination.
2086 */
2087 if (!submit_op1(emit,
2088 inst_token( SVGA3DOP_MOV ),
2089 dst,
2090 get_zero_immediate(emit)))
2091 return FALSE;
2092
2093 return TRUE;
2094 }
2095 else {
2096 unsigned opcode;
2097 const struct tgsi_full_src_register *reg = &insn->Src[0];
2098 SVGA3dShaderInstToken inst;
2099 SVGA3dShaderDestToken dst;
2100 struct src_register src0;
2101
2102 switch (insn->Instruction.Opcode) {
2103 case TGSI_OPCODE_DDX:
2104 opcode = SVGA3DOP_DSX;
2105 break;
2106 case TGSI_OPCODE_DDY:
2107 opcode = SVGA3DOP_DSY;
2108 break;
2109 default:
2110 return FALSE;
2111 }
2112
2113 inst = inst_token( opcode );
2114 dst = translate_dst_register( emit, insn, 0 );
2115 src0 = translate_src_register( emit, reg );
2116
2117 /* We cannot use negate or abs on source to dsx/dsy instruction.
2118 */
2119 if (reg->Register.Absolute ||
2120 reg->Register.Negate) {
2121 SVGA3dShaderDestToken temp = get_temp( emit );
2122
2123 if (!emit_repl( emit, temp, &src0 ))
2124 return FALSE;
2125 }
2126
2127 return submit_op1( emit, inst, dst, src0 );
2128 }
2129 }
2130
2131
2132 /**
2133 * Translate/emit ARL (Address Register Load) instruction. Used to
2134 * move a value into the special 'address' register. Used to implement
2135 * indirect/variable indexing into arrays.
2136 */
2137 static boolean
2138 emit_arl(struct svga_shader_emitter *emit,
2139 const struct tgsi_full_instruction *insn)
2140 {
2141 ++emit->current_arl;
2142 if (emit->unit == PIPE_SHADER_FRAGMENT) {
2143 /* MOVA not present in pixel shader instruction set.
2144 * Ignore this instruction altogether since it is
2145 * only used for loop counters -- and for that
2146 * we reference aL directly.
2147 */
2148 return TRUE;
2149 }
2150 if (svga_arl_needs_adjustment( emit )) {
2151 return emit_fake_arl( emit, insn );
2152 } else {
2153 /* no need to adjust, just emit straight arl */
2154 return emit_simple_instruction(emit, SVGA3DOP_MOVA, insn);
2155 }
2156 }
2157
2158
2159 static boolean
2160 emit_pow(struct svga_shader_emitter *emit,
2161 const struct tgsi_full_instruction *insn)
2162 {
2163 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
2164 struct src_register src0 = translate_src_register(
2165 emit, &insn->Src[0] );
2166 struct src_register src1 = translate_src_register(
2167 emit, &insn->Src[1] );
2168 boolean need_tmp = FALSE;
2169
2170 /* POW can only output to a temporary */
2171 if (insn->Dst[0].Register.File != TGSI_FILE_TEMPORARY)
2172 need_tmp = TRUE;
2173
2174 /* POW src1 must not be the same register as dst */
2175 if (alias_src_dst( src1, dst ))
2176 need_tmp = TRUE;
2177
2178 /* it's a scalar op */
2179 src0 = scalar( src0, TGSI_SWIZZLE_X );
2180 src1 = scalar( src1, TGSI_SWIZZLE_X );
2181
2182 if (need_tmp) {
2183 SVGA3dShaderDestToken tmp =
2184 writemask(get_temp( emit ), TGSI_WRITEMASK_X );
2185
2186 if (!submit_op2(emit, inst_token( SVGA3DOP_POW ), tmp, src0, src1))
2187 return FALSE;
2188
2189 return submit_op1(emit, inst_token( SVGA3DOP_MOV ),
2190 dst, scalar(src(tmp), 0) );
2191 }
2192 else {
2193 return submit_op2(emit, inst_token( SVGA3DOP_POW ), dst, src0, src1);
2194 }
2195 }
2196
2197
2198 /**
2199 * Translate/emit TGSI XPD (vector cross product) instruction.
2200 */
2201 static boolean
2202 emit_xpd(struct svga_shader_emitter *emit,
2203 const struct tgsi_full_instruction *insn)
2204 {
2205 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
2206 const struct src_register src0 = translate_src_register(
2207 emit, &insn->Src[0] );
2208 const struct src_register src1 = translate_src_register(
2209 emit, &insn->Src[1] );
2210 boolean need_dst_tmp = FALSE;
2211
2212 /* XPD can only output to a temporary */
2213 if (SVGA3dShaderGetRegType(dst.value) != SVGA3DREG_TEMP)
2214 need_dst_tmp = TRUE;
2215
2216 /* The dst reg must not be the same as src0 or src1*/
2217 if (alias_src_dst(src0, dst) ||
2218 alias_src_dst(src1, dst))
2219 need_dst_tmp = TRUE;
2220
2221 if (need_dst_tmp) {
2222 SVGA3dShaderDestToken tmp = get_temp( emit );
2223
2224 /* Obey DX9 restrictions on mask:
2225 */
2226 tmp.mask = dst.mask & TGSI_WRITEMASK_XYZ;
2227
2228 if (!submit_op2(emit, inst_token( SVGA3DOP_CRS ), tmp, src0, src1))
2229 return FALSE;
2230
2231 if (!submit_op1(emit, inst_token( SVGA3DOP_MOV ), dst, src( tmp )))
2232 return FALSE;
2233 }
2234 else {
2235 if (!submit_op2(emit, inst_token( SVGA3DOP_CRS ), dst, src0, src1))
2236 return FALSE;
2237 }
2238
2239 /* Need to emit 1.0 to dst.w?
2240 */
2241 if (dst.mask & TGSI_WRITEMASK_W) {
2242 struct src_register one = get_one_immediate( emit );
2243
2244 if (!submit_op1(emit,
2245 inst_token( SVGA3DOP_MOV ),
2246 writemask(dst, TGSI_WRITEMASK_W),
2247 one))
2248 return FALSE;
2249 }
2250
2251 return TRUE;
2252 }
2253
2254
2255 /**
2256 * Emit a LRP (linear interpolation) instruction.
2257 */
2258 static boolean
2259 submit_lrp(struct svga_shader_emitter *emit,
2260 SVGA3dShaderDestToken dst,
2261 struct src_register src0,
2262 struct src_register src1,
2263 struct src_register src2)
2264 {
2265 SVGA3dShaderDestToken tmp;
2266 boolean need_dst_tmp = FALSE;
2267
2268 /* The dst reg must be a temporary, and not be the same as src0 or src2 */
2269 if (SVGA3dShaderGetRegType(dst.value) != SVGA3DREG_TEMP ||
2270 alias_src_dst(src0, dst) ||
2271 alias_src_dst(src2, dst))
2272 need_dst_tmp = TRUE;
2273
2274 if (need_dst_tmp) {
2275 tmp = get_temp( emit );
2276 tmp.mask = dst.mask;
2277 }
2278 else {
2279 tmp = dst;
2280 }
2281
2282 if (!submit_op3(emit, inst_token( SVGA3DOP_LRP ), tmp, src0, src1, src2))
2283 return FALSE;
2284
2285 if (need_dst_tmp) {
2286 if (!submit_op1(emit, inst_token( SVGA3DOP_MOV ), dst, src( tmp )))
2287 return FALSE;
2288 }
2289
2290 return TRUE;
2291 }
2292
2293
2294 /**
2295 * Translate/emit LRP (Linear Interpolation) instruction.
2296 */
2297 static boolean
2298 emit_lrp(struct svga_shader_emitter *emit,
2299 const struct tgsi_full_instruction *insn)
2300 {
2301 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
2302 const struct src_register src0 = translate_src_register(
2303 emit, &insn->Src[0] );
2304 const struct src_register src1 = translate_src_register(
2305 emit, &insn->Src[1] );
2306 const struct src_register src2 = translate_src_register(
2307 emit, &insn->Src[2] );
2308
2309 return submit_lrp(emit, dst, src0, src1, src2);
2310 }
2311
2312 /**
2313 * Translate/emit DST (Distance function) instruction.
2314 */
2315 static boolean
2316 emit_dst_insn(struct svga_shader_emitter *emit,
2317 const struct tgsi_full_instruction *insn)
2318 {
2319 if (emit->unit == PIPE_SHADER_VERTEX) {
2320 /* SVGA/DX9 has a DST instruction, but only for vertex shaders:
2321 */
2322 return emit_simple_instruction(emit, SVGA3DOP_DST, insn);
2323 }
2324 else {
2325 /* result[0] = 1 * 1;
2326 * result[1] = a[1] * b[1];
2327 * result[2] = a[2] * 1;
2328 * result[3] = 1 * b[3];
2329 */
2330 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
2331 SVGA3dShaderDestToken tmp;
2332 const struct src_register src0 = translate_src_register(
2333 emit, &insn->Src[0] );
2334 const struct src_register src1 = translate_src_register(
2335 emit, &insn->Src[1] );
2336 boolean need_tmp = FALSE;
2337
2338 if (SVGA3dShaderGetRegType(dst.value) != SVGA3DREG_TEMP ||
2339 alias_src_dst(src0, dst) ||
2340 alias_src_dst(src1, dst))
2341 need_tmp = TRUE;
2342
2343 if (need_tmp) {
2344 tmp = get_temp( emit );
2345 }
2346 else {
2347 tmp = dst;
2348 }
2349
2350 /* tmp.xw = 1.0
2351 */
2352 if (tmp.mask & TGSI_WRITEMASK_XW) {
2353 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ),
2354 writemask(tmp, TGSI_WRITEMASK_XW ),
2355 get_one_immediate(emit)))
2356 return FALSE;
2357 }
2358
2359 /* tmp.yz = src0
2360 */
2361 if (tmp.mask & TGSI_WRITEMASK_YZ) {
2362 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ),
2363 writemask(tmp, TGSI_WRITEMASK_YZ ),
2364 src0))
2365 return FALSE;
2366 }
2367
2368 /* tmp.yw = tmp * src1
2369 */
2370 if (tmp.mask & TGSI_WRITEMASK_YW) {
2371 if (!submit_op2( emit, inst_token( SVGA3DOP_MUL ),
2372 writemask(tmp, TGSI_WRITEMASK_YW ),
2373 src(tmp),
2374 src1))
2375 return FALSE;
2376 }
2377
2378 /* dst = tmp
2379 */
2380 if (need_tmp) {
2381 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ),
2382 dst,
2383 src(tmp)))
2384 return FALSE;
2385 }
2386 }
2387
2388 return TRUE;
2389 }
2390
2391
2392 static boolean
2393 emit_exp(struct svga_shader_emitter *emit,
2394 const struct tgsi_full_instruction *insn)
2395 {
2396 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
2397 struct src_register src0 =
2398 translate_src_register( emit, &insn->Src[0] );
2399 SVGA3dShaderDestToken fraction;
2400
2401 if (dst.mask & TGSI_WRITEMASK_Y)
2402 fraction = dst;
2403 else if (dst.mask & TGSI_WRITEMASK_X)
2404 fraction = get_temp( emit );
2405 else
2406 fraction.value = 0;
2407
2408 /* If y is being written, fill it with src0 - floor(src0).
2409 */
2410 if (dst.mask & TGSI_WRITEMASK_XY) {
2411 if (!submit_op1( emit, inst_token( SVGA3DOP_FRC ),
2412 writemask( fraction, TGSI_WRITEMASK_Y ),
2413 src0 ))
2414 return FALSE;
2415 }
2416
2417 /* If x is being written, fill it with 2 ^ floor(src0).
2418 */
2419 if (dst.mask & TGSI_WRITEMASK_X) {
2420 if (!submit_op2( emit, inst_token( SVGA3DOP_ADD ),
2421 writemask( dst, TGSI_WRITEMASK_X ),
2422 src0,
2423 scalar( negate( src( fraction ) ), TGSI_SWIZZLE_Y ) ) )
2424 return FALSE;
2425
2426 if (!submit_op1( emit, inst_token( SVGA3DOP_EXP ),
2427 writemask( dst, TGSI_WRITEMASK_X ),
2428 scalar( src( dst ), TGSI_SWIZZLE_X ) ) )
2429 return FALSE;
2430
2431 if (!(dst.mask & TGSI_WRITEMASK_Y))
2432 release_temp( emit, fraction );
2433 }
2434
2435 /* If z is being written, fill it with 2 ^ src0 (partial precision).
2436 */
2437 if (dst.mask & TGSI_WRITEMASK_Z) {
2438 if (!submit_op1( emit, inst_token( SVGA3DOP_EXPP ),
2439 writemask( dst, TGSI_WRITEMASK_Z ),
2440 src0 ) )
2441 return FALSE;
2442 }
2443
2444 /* If w is being written, fill it with one.
2445 */
2446 if (dst.mask & TGSI_WRITEMASK_W) {
2447 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ),
2448 writemask(dst, TGSI_WRITEMASK_W),
2449 get_one_immediate(emit)))
2450 return FALSE;
2451 }
2452
2453 return TRUE;
2454 }
2455
2456
2457 /**
2458 * Translate/emit LIT (Lighting helper) instruction.
2459 */
2460 static boolean
2461 emit_lit(struct svga_shader_emitter *emit,
2462 const struct tgsi_full_instruction *insn)
2463 {
2464 if (emit->unit == PIPE_SHADER_VERTEX) {
2465 /* SVGA/DX9 has a LIT instruction, but only for vertex shaders:
2466 */
2467 return emit_simple_instruction(emit, SVGA3DOP_LIT, insn);
2468 }
2469 else {
2470 /* D3D vs. GL semantics can be fairly easily accomodated by
2471 * variations on this sequence.
2472 *
2473 * GL:
2474 * tmp.y = src.x
2475 * tmp.z = pow(src.y,src.w)
2476 * p0 = src0.xxxx > 0
2477 * result = zero.wxxw
2478 * (p0) result.yz = tmp
2479 *
2480 * D3D:
2481 * tmp.y = src.x
2482 * tmp.z = pow(src.y,src.w)
2483 * p0 = src0.xxyy > 0
2484 * result = zero.wxxw
2485 * (p0) result.yz = tmp
2486 *
2487 * Will implement the GL version for now.
2488 */
2489 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
2490 SVGA3dShaderDestToken tmp = get_temp( emit );
2491 const struct src_register src0 = translate_src_register(
2492 emit, &insn->Src[0] );
2493
2494 /* tmp = pow(src.y, src.w)
2495 */
2496 if (dst.mask & TGSI_WRITEMASK_Z) {
2497 if (!submit_op2(emit, inst_token( SVGA3DOP_POW ),
2498 tmp,
2499 scalar(src0, 1),
2500 scalar(src0, 3)))
2501 return FALSE;
2502 }
2503
2504 /* tmp.y = src.x
2505 */
2506 if (dst.mask & TGSI_WRITEMASK_Y) {
2507 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ),
2508 writemask(tmp, TGSI_WRITEMASK_Y ),
2509 scalar(src0, 0)))
2510 return FALSE;
2511 }
2512
2513 /* Can't quite do this with emit conditional due to the extra
2514 * writemask on the predicated mov:
2515 */
2516 {
2517 SVGA3dShaderDestToken pred_reg = dst_register( SVGA3DREG_PREDICATE, 0 );
2518 struct src_register predsrc;
2519
2520 /* D3D vs GL semantics:
2521 */
2522 if (0)
2523 predsrc = swizzle(src0, 0, 0, 1, 1); /* D3D */
2524 else
2525 predsrc = swizzle(src0, 0, 0, 0, 0); /* GL */
2526
2527 /* SETP src0.xxyy, GT, {0}.x */
2528 if (!submit_op2( emit,
2529 inst_token_setp(SVGA3DOPCOMP_GT),
2530 pred_reg,
2531 predsrc,
2532 get_zero_immediate(emit)))
2533 return FALSE;
2534
2535 /* MOV dst, fail */
2536 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ), dst,
2537 get_immediate(emit, 1.0f, 0.0f, 0.0f, 1.0f)))
2538 return FALSE;
2539
2540 /* MOV dst.yz, tmp (predicated)
2541 *
2542 * Note that the predicate reg (and possible modifiers) is passed
2543 * as the first source argument.
2544 */
2545 if (dst.mask & TGSI_WRITEMASK_YZ) {
2546 if (!submit_op2( emit,
2547 inst_token_predicated(SVGA3DOP_MOV),
2548 writemask(dst, TGSI_WRITEMASK_YZ),
2549 src( pred_reg ), src( tmp ) ))
2550 return FALSE;
2551 }
2552 }
2553 }
2554
2555 return TRUE;
2556 }
2557
2558
2559 static boolean
2560 emit_ex2(struct svga_shader_emitter *emit,
2561 const struct tgsi_full_instruction *insn)
2562 {
2563 SVGA3dShaderInstToken inst;
2564 SVGA3dShaderDestToken dst;
2565 struct src_register src0;
2566
2567 inst = inst_token( SVGA3DOP_EXP );
2568 dst = translate_dst_register( emit, insn, 0 );
2569 src0 = translate_src_register( emit, &insn->Src[0] );
2570 src0 = scalar( src0, TGSI_SWIZZLE_X );
2571
2572 if (dst.mask != TGSI_WRITEMASK_XYZW) {
2573 SVGA3dShaderDestToken tmp = get_temp( emit );
2574
2575 if (!submit_op1( emit, inst, tmp, src0 ))
2576 return FALSE;
2577
2578 return submit_op1( emit, inst_token( SVGA3DOP_MOV ),
2579 dst,
2580 scalar( src( tmp ), TGSI_SWIZZLE_X ) );
2581 }
2582
2583 return submit_op1( emit, inst, dst, src0 );
2584 }
2585
2586
2587 static boolean
2588 emit_log(struct svga_shader_emitter *emit,
2589 const struct tgsi_full_instruction *insn)
2590 {
2591 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
2592 struct src_register src0 =
2593 translate_src_register( emit, &insn->Src[0] );
2594 SVGA3dShaderDestToken abs_tmp;
2595 struct src_register abs_src0;
2596 SVGA3dShaderDestToken log2_abs;
2597
2598 abs_tmp.value = 0;
2599
2600 if (dst.mask & TGSI_WRITEMASK_Z)
2601 log2_abs = dst;
2602 else if (dst.mask & TGSI_WRITEMASK_XY)
2603 log2_abs = get_temp( emit );
2604 else
2605 log2_abs.value = 0;
2606
2607 /* If z is being written, fill it with log2( abs( src0 ) ).
2608 */
2609 if (dst.mask & TGSI_WRITEMASK_XYZ) {
2610 if (!src0.base.srcMod || src0.base.srcMod == SVGA3DSRCMOD_ABS)
2611 abs_src0 = src0;
2612 else {
2613 abs_tmp = get_temp( emit );
2614
2615 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ),
2616 abs_tmp,
2617 src0 ) )
2618 return FALSE;
2619
2620 abs_src0 = src( abs_tmp );
2621 }
2622
2623 abs_src0 = absolute( scalar( abs_src0, TGSI_SWIZZLE_X ) );
2624
2625 if (!submit_op1( emit, inst_token( SVGA3DOP_LOG ),
2626 writemask( log2_abs, TGSI_WRITEMASK_Z ),
2627 abs_src0 ) )
2628 return FALSE;
2629 }
2630
2631 if (dst.mask & TGSI_WRITEMASK_XY) {
2632 SVGA3dShaderDestToken floor_log2;
2633
2634 if (dst.mask & TGSI_WRITEMASK_X)
2635 floor_log2 = dst;
2636 else
2637 floor_log2 = get_temp( emit );
2638
2639 /* If x is being written, fill it with floor( log2( abs( src0 ) ) ).
2640 */
2641 if (!submit_op1( emit, inst_token( SVGA3DOP_FRC ),
2642 writemask( floor_log2, TGSI_WRITEMASK_X ),
2643 scalar( src( log2_abs ), TGSI_SWIZZLE_Z ) ) )
2644 return FALSE;
2645
2646 if (!submit_op2( emit, inst_token( SVGA3DOP_ADD ),
2647 writemask( floor_log2, TGSI_WRITEMASK_X ),
2648 scalar( src( log2_abs ), TGSI_SWIZZLE_Z ),
2649 negate( src( floor_log2 ) ) ) )
2650 return FALSE;
2651
2652 /* If y is being written, fill it with
2653 * abs ( src0 ) / ( 2 ^ floor( log2( abs( src0 ) ) ) ).
2654 */
2655 if (dst.mask & TGSI_WRITEMASK_Y) {
2656 if (!submit_op1( emit, inst_token( SVGA3DOP_EXP ),
2657 writemask( dst, TGSI_WRITEMASK_Y ),
2658 negate( scalar( src( floor_log2 ),
2659 TGSI_SWIZZLE_X ) ) ) )
2660 return FALSE;
2661
2662 if (!submit_op2( emit, inst_token( SVGA3DOP_MUL ),
2663 writemask( dst, TGSI_WRITEMASK_Y ),
2664 src( dst ),
2665 abs_src0 ) )
2666 return FALSE;
2667 }
2668
2669 if (!(dst.mask & TGSI_WRITEMASK_X))
2670 release_temp( emit, floor_log2 );
2671
2672 if (!(dst.mask & TGSI_WRITEMASK_Z))
2673 release_temp( emit, log2_abs );
2674 }
2675
2676 if (dst.mask & TGSI_WRITEMASK_XYZ && src0.base.srcMod &&
2677 src0.base.srcMod != SVGA3DSRCMOD_ABS)
2678 release_temp( emit, abs_tmp );
2679
2680 /* If w is being written, fill it with one.
2681 */
2682 if (dst.mask & TGSI_WRITEMASK_W) {
2683 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ),
2684 writemask(dst, TGSI_WRITEMASK_W),
2685 get_one_immediate(emit)))
2686 return FALSE;
2687 }
2688
2689 return TRUE;
2690 }
2691
2692
2693 /**
2694 * Translate TGSI TRUNC or ROUND instruction.
2695 * We need to truncate toward zero. Ex: trunc(-1.9) = -1
2696 * Different approaches are needed for VS versus PS.
2697 */
2698 static boolean
2699 emit_trunc_round(struct svga_shader_emitter *emit,
2700 const struct tgsi_full_instruction *insn,
2701 boolean round)
2702 {
2703 SVGA3dShaderDestToken dst = translate_dst_register(emit, insn, 0);
2704 const struct src_register src0 =
2705 translate_src_register(emit, &insn->Src[0] );
2706 SVGA3dShaderDestToken t1 = get_temp(emit);
2707
2708 if (round) {
2709 SVGA3dShaderDestToken t0 = get_temp(emit);
2710 struct src_register half = get_half_immediate(emit);
2711
2712 /* t0 = abs(src0) + 0.5 */
2713 if (!submit_op2(emit, inst_token(SVGA3DOP_ADD), t0,
2714 absolute(src0), half))
2715 return FALSE;
2716
2717 /* t1 = fract(t0) */
2718 if (!submit_op1(emit, inst_token(SVGA3DOP_FRC), t1, src(t0)))
2719 return FALSE;
2720
2721 /* t1 = t0 - t1 */
2722 if (!submit_op2(emit, inst_token(SVGA3DOP_ADD), t1, src(t0),
2723 negate(src(t1))))
2724 return FALSE;
2725 }
2726 else {
2727 /* trunc */
2728
2729 /* t1 = fract(abs(src0)) */
2730 if (!submit_op1(emit, inst_token(SVGA3DOP_FRC), t1, absolute(src0)))
2731 return FALSE;
2732
2733 /* t1 = abs(src0) - t1 */
2734 if (!submit_op2(emit, inst_token(SVGA3DOP_ADD), t1, absolute(src0),
2735 negate(src(t1))))
2736 return FALSE;
2737 }
2738
2739 /*
2740 * Now we need to multiply t1 by the sign of the original value.
2741 */
2742 if (emit->unit == PIPE_SHADER_VERTEX) {
2743 /* For VS: use SGN instruction */
2744 /* Need two extra/dummy registers: */
2745 SVGA3dShaderDestToken t2 = get_temp(emit), t3 = get_temp(emit),
2746 t4 = get_temp(emit);
2747
2748 /* t2 = sign(src0) */
2749 if (!submit_op3(emit, inst_token(SVGA3DOP_SGN), t2, src0,
2750 src(t3), src(t4)))
2751 return FALSE;
2752
2753 /* dst = t1 * t2 */
2754 if (!submit_op2(emit, inst_token(SVGA3DOP_MUL), dst, src(t1), src(t2)))
2755 return FALSE;
2756 }
2757 else {
2758 /* For FS: Use CMP instruction */
2759 return submit_op3(emit, inst_token( SVGA3DOP_CMP ), dst,
2760 src0, src(t1), negate(src(t1)));
2761 }
2762
2763 return TRUE;
2764 }
2765
2766
2767 /**
2768 * Translate/emit "begin subroutine" instruction/marker/label.
2769 */
2770 static boolean
2771 emit_bgnsub(struct svga_shader_emitter *emit,
2772 unsigned position,
2773 const struct tgsi_full_instruction *insn)
2774 {
2775 unsigned i;
2776
2777 /* Note that we've finished the main function and are now emitting
2778 * subroutines. This affects how we terminate the generated
2779 * shader.
2780 */
2781 emit->in_main_func = FALSE;
2782
2783 for (i = 0; i < emit->nr_labels; i++) {
2784 if (emit->label[i] == position) {
2785 return (emit_instruction( emit, inst_token( SVGA3DOP_RET ) ) &&
2786 emit_instruction( emit, inst_token( SVGA3DOP_LABEL ) ) &&
2787 emit_src( emit, src_register( SVGA3DREG_LABEL, i )));
2788 }
2789 }
2790
2791 assert(0);
2792 return TRUE;
2793 }
2794
2795
2796 /**
2797 * Translate/emit subroutine call instruction.
2798 */
2799 static boolean
2800 emit_call(struct svga_shader_emitter *emit,
2801 const struct tgsi_full_instruction *insn)
2802 {
2803 unsigned position = insn->Label.Label;
2804 unsigned i;
2805
2806 for (i = 0; i < emit->nr_labels; i++) {
2807 if (emit->label[i] == position)
2808 break;
2809 }
2810
2811 if (emit->nr_labels == ARRAY_SIZE(emit->label))
2812 return FALSE;
2813
2814 if (i == emit->nr_labels) {
2815 emit->label[i] = position;
2816 emit->nr_labels++;
2817 }
2818
2819 return (emit_instruction( emit, inst_token( SVGA3DOP_CALL ) ) &&
2820 emit_src( emit, src_register( SVGA3DREG_LABEL, i )));
2821 }
2822
2823
2824 /**
2825 * Called at the end of the shader. Actually, emit special "fix-up"
2826 * code for the vertex/fragment shader.
2827 */
2828 static boolean
2829 emit_end(struct svga_shader_emitter *emit)
2830 {
2831 if (emit->unit == PIPE_SHADER_VERTEX) {
2832 return emit_vs_postamble( emit );
2833 }
2834 else {
2835 return emit_ps_postamble( emit );
2836 }
2837 }
2838
2839
2840 /**
2841 * Translate any TGSI instruction to SVGA.
2842 */
2843 static boolean
2844 svga_emit_instruction(struct svga_shader_emitter *emit,
2845 unsigned position,
2846 const struct tgsi_full_instruction *insn)
2847 {
2848 switch (insn->Instruction.Opcode) {
2849
2850 case TGSI_OPCODE_ARL:
2851 return emit_arl( emit, insn );
2852
2853 case TGSI_OPCODE_TEX:
2854 case TGSI_OPCODE_TXB:
2855 case TGSI_OPCODE_TXP:
2856 case TGSI_OPCODE_TXL:
2857 case TGSI_OPCODE_TXD:
2858 return emit_tex( emit, insn );
2859
2860 case TGSI_OPCODE_DDX:
2861 case TGSI_OPCODE_DDY:
2862 return emit_deriv( emit, insn );
2863
2864 case TGSI_OPCODE_BGNSUB:
2865 return emit_bgnsub( emit, position, insn );
2866
2867 case TGSI_OPCODE_ENDSUB:
2868 return TRUE;
2869
2870 case TGSI_OPCODE_CAL:
2871 return emit_call( emit, insn );
2872
2873 case TGSI_OPCODE_FLR:
2874 return emit_floor( emit, insn );
2875
2876 case TGSI_OPCODE_TRUNC:
2877 return emit_trunc_round( emit, insn, FALSE );
2878
2879 case TGSI_OPCODE_ROUND:
2880 return emit_trunc_round( emit, insn, TRUE );
2881
2882 case TGSI_OPCODE_CEIL:
2883 return emit_ceil( emit, insn );
2884
2885 case TGSI_OPCODE_CMP:
2886 return emit_cmp( emit, insn );
2887
2888 case TGSI_OPCODE_DIV:
2889 return emit_div( emit, insn );
2890
2891 case TGSI_OPCODE_DP2:
2892 return emit_dp2( emit, insn );
2893
2894 case TGSI_OPCODE_COS:
2895 return emit_cos( emit, insn );
2896
2897 case TGSI_OPCODE_SIN:
2898 return emit_sin( emit, insn );
2899
2900 case TGSI_OPCODE_SCS:
2901 return emit_sincos( emit, insn );
2902
2903 case TGSI_OPCODE_END:
2904 /* TGSI always finishes the main func with an END */
2905 return emit_end( emit );
2906
2907 case TGSI_OPCODE_KILL_IF:
2908 return emit_kill_if( emit, insn );
2909
2910 /* Selection opcodes. The underlying language is fairly
2911 * non-orthogonal about these.
2912 */
2913 case TGSI_OPCODE_SEQ:
2914 return emit_select_op( emit, PIPE_FUNC_EQUAL, insn );
2915
2916 case TGSI_OPCODE_SNE:
2917 return emit_select_op( emit, PIPE_FUNC_NOTEQUAL, insn );
2918
2919 case TGSI_OPCODE_SGT:
2920 return emit_select_op( emit, PIPE_FUNC_GREATER, insn );
2921
2922 case TGSI_OPCODE_SGE:
2923 return emit_select_op( emit, PIPE_FUNC_GEQUAL, insn );
2924
2925 case TGSI_OPCODE_SLT:
2926 return emit_select_op( emit, PIPE_FUNC_LESS, insn );
2927
2928 case TGSI_OPCODE_SLE:
2929 return emit_select_op( emit, PIPE_FUNC_LEQUAL, insn );
2930
2931 case TGSI_OPCODE_POW:
2932 return emit_pow( emit, insn );
2933
2934 case TGSI_OPCODE_EX2:
2935 return emit_ex2( emit, insn );
2936
2937 case TGSI_OPCODE_EXP:
2938 return emit_exp( emit, insn );
2939
2940 case TGSI_OPCODE_LOG:
2941 return emit_log( emit, insn );
2942
2943 case TGSI_OPCODE_LG2:
2944 return emit_scalar_op1( emit, SVGA3DOP_LOG, insn );
2945
2946 case TGSI_OPCODE_RSQ:
2947 return emit_scalar_op1( emit, SVGA3DOP_RSQ, insn );
2948
2949 case TGSI_OPCODE_RCP:
2950 return emit_scalar_op1( emit, SVGA3DOP_RCP, insn );
2951
2952 case TGSI_OPCODE_CONT:
2953 /* not expected (we return PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED = 0) */
2954 return FALSE;
2955
2956 case TGSI_OPCODE_RET:
2957 /* This is a noop -- we tell mesa that we can't support RET
2958 * within a function (early return), so this will always be
2959 * followed by an ENDSUB.
2960 */
2961 return TRUE;
2962
2963 /* These aren't actually used by any of the frontends we care
2964 * about:
2965 */
2966 case TGSI_OPCODE_AND:
2967 case TGSI_OPCODE_OR:
2968 case TGSI_OPCODE_I2F:
2969 case TGSI_OPCODE_NOT:
2970 case TGSI_OPCODE_SHL:
2971 case TGSI_OPCODE_ISHR:
2972 case TGSI_OPCODE_XOR:
2973 return FALSE;
2974
2975 case TGSI_OPCODE_IF:
2976 return emit_if( emit, insn );
2977 case TGSI_OPCODE_ELSE:
2978 return emit_else( emit, insn );
2979 case TGSI_OPCODE_ENDIF:
2980 return emit_endif( emit, insn );
2981
2982 case TGSI_OPCODE_BGNLOOP:
2983 return emit_bgnloop( emit, insn );
2984 case TGSI_OPCODE_ENDLOOP:
2985 return emit_endloop( emit, insn );
2986 case TGSI_OPCODE_BRK:
2987 return emit_brk( emit, insn );
2988
2989 case TGSI_OPCODE_XPD:
2990 return emit_xpd( emit, insn );
2991
2992 case TGSI_OPCODE_KILL:
2993 return emit_kill( emit, insn );
2994
2995 case TGSI_OPCODE_DST:
2996 return emit_dst_insn( emit, insn );
2997
2998 case TGSI_OPCODE_LIT:
2999 return emit_lit( emit, insn );
3000
3001 case TGSI_OPCODE_LRP:
3002 return emit_lrp( emit, insn );
3003
3004 case TGSI_OPCODE_SSG:
3005 return emit_ssg( emit, insn );
3006
3007 case TGSI_OPCODE_MOV:
3008 return emit_mov( emit, insn );
3009
3010 default:
3011 {
3012 unsigned opcode = translate_opcode(insn->Instruction.Opcode);
3013
3014 if (opcode == SVGA3DOP_LAST_INST)
3015 return FALSE;
3016
3017 if (!emit_simple_instruction( emit, opcode, insn ))
3018 return FALSE;
3019 }
3020 }
3021
3022 return TRUE;
3023 }
3024
3025
3026 /**
3027 * Translate/emit a TGSI IMMEDIATE declaration.
3028 * An immediate vector is a constant that's hard-coded into the shader.
3029 */
3030 static boolean
3031 svga_emit_immediate(struct svga_shader_emitter *emit,
3032 const struct tgsi_full_immediate *imm)
3033 {
3034 static const float id[4] = {0,0,0,1};
3035 float value[4];
3036 unsigned i;
3037
3038 assert(1 <= imm->Immediate.NrTokens && imm->Immediate.NrTokens <= 5);
3039 for (i = 0; i < imm->Immediate.NrTokens - 1; i++) {
3040 float f = imm->u[i].Float;
3041 value[i] = util_is_inf_or_nan(f) ? 0.0f : f;
3042 }
3043
3044 /* If the immediate has less than four values, fill in the remaining
3045 * positions from id={0,0,0,1}.
3046 */
3047 for ( ; i < 4; i++ )
3048 value[i] = id[i];
3049
3050 return emit_def_const( emit, SVGA3D_CONST_TYPE_FLOAT,
3051 emit->imm_start + emit->internal_imm_count++,
3052 value[0], value[1], value[2], value[3]);
3053 }
3054
3055
3056 static boolean
3057 make_immediate(struct svga_shader_emitter *emit,
3058 float a, float b, float c, float d,
3059 struct src_register *out )
3060 {
3061 unsigned idx = emit->nr_hw_float_const++;
3062
3063 if (!emit_def_const( emit, SVGA3D_CONST_TYPE_FLOAT,
3064 idx, a, b, c, d ))
3065 return FALSE;
3066
3067 *out = src_register( SVGA3DREG_CONST, idx );
3068
3069 return TRUE;
3070 }
3071
3072
3073 /**
3074 * Emit special VS instructions at top of shader.
3075 */
3076 static boolean
3077 emit_vs_preamble(struct svga_shader_emitter *emit)
3078 {
3079 if (!emit->key.vs.need_prescale) {
3080 if (!make_immediate( emit, 0, 0, .5, .5,
3081 &emit->imm_0055))
3082 return FALSE;
3083 }
3084
3085 return TRUE;
3086 }
3087
3088
3089 /**
3090 * Emit special PS instructions at top of shader.
3091 */
3092 static boolean
3093 emit_ps_preamble(struct svga_shader_emitter *emit)
3094 {
3095 if (emit->ps_reads_pos && emit->info.reads_z) {
3096 /*
3097 * Assemble the position from various bits of inputs. Depth and W are
3098 * passed in a texcoord this is due to D3D's vPos not hold Z or W.
3099 * Also fixup the perspective interpolation.
3100 *
3101 * temp_pos.xy = vPos.xy
3102 * temp_pos.w = rcp(texcoord1.w);
3103 * temp_pos.z = texcoord1.z * temp_pos.w;
3104 */
3105 if (!submit_op1( emit,
3106 inst_token(SVGA3DOP_MOV),
3107 writemask( emit->ps_temp_pos, TGSI_WRITEMASK_XY ),
3108 emit->ps_true_pos ))
3109 return FALSE;
3110
3111 if (!submit_op1( emit,
3112 inst_token(SVGA3DOP_RCP),
3113 writemask( emit->ps_temp_pos, TGSI_WRITEMASK_W ),
3114 scalar( emit->ps_depth_pos, TGSI_SWIZZLE_W ) ))
3115 return FALSE;
3116
3117 if (!submit_op2( emit,
3118 inst_token(SVGA3DOP_MUL),
3119 writemask( emit->ps_temp_pos, TGSI_WRITEMASK_Z ),
3120 scalar( emit->ps_depth_pos, TGSI_SWIZZLE_Z ),
3121 scalar( src(emit->ps_temp_pos), TGSI_SWIZZLE_W ) ))
3122 return FALSE;
3123 }
3124
3125 return TRUE;
3126 }
3127
3128
3129 /**
3130 * Emit special PS instructions at end of shader.
3131 */
3132 static boolean
3133 emit_ps_postamble(struct svga_shader_emitter *emit)
3134 {
3135 unsigned i;
3136
3137 /* PS oDepth is incredibly fragile and it's very hard to catch the
3138 * types of usage that break it during shader emit. Easier just to
3139 * redirect the main program to a temporary and then only touch
3140 * oDepth with a hand-crafted MOV below.
3141 */
3142 if (SVGA3dShaderGetRegType(emit->true_pos.value) != 0) {
3143 if (!submit_op1( emit,
3144 inst_token(SVGA3DOP_MOV),
3145 emit->true_pos,
3146 scalar(src(emit->temp_pos), TGSI_SWIZZLE_Z) ))
3147 return FALSE;
3148 }
3149
3150 for (i = 0; i < PIPE_MAX_COLOR_BUFS; i++) {
3151 if (SVGA3dShaderGetRegType(emit->true_color_output[i].value) != 0) {
3152 /* Potentially override output colors with white for XOR
3153 * logicop workaround.
3154 */
3155 if (emit->unit == PIPE_SHADER_FRAGMENT &&
3156 emit->key.fs.white_fragments) {
3157 struct src_register one = get_one_immediate(emit);
3158
3159 if (!submit_op1( emit,
3160 inst_token(SVGA3DOP_MOV),
3161 emit->true_color_output[i],
3162 one ))
3163 return FALSE;
3164 }
3165 else if (emit->unit == PIPE_SHADER_FRAGMENT &&
3166 i < emit->key.fs.write_color0_to_n_cbufs) {
3167 /* Write temp color output [0] to true output [i] */
3168 if (!submit_op1(emit, inst_token(SVGA3DOP_MOV),
3169 emit->true_color_output[i],
3170 src(emit->temp_color_output[0]))) {
3171 return FALSE;
3172 }
3173 }
3174 else {
3175 if (!submit_op1( emit,
3176 inst_token(SVGA3DOP_MOV),
3177 emit->true_color_output[i],
3178 src(emit->temp_color_output[i]) ))
3179 return FALSE;
3180 }
3181 }
3182 }
3183
3184 return TRUE;
3185 }
3186
3187
3188 /**
3189 * Emit special VS instructions at end of shader.
3190 */
3191 static boolean
3192 emit_vs_postamble(struct svga_shader_emitter *emit)
3193 {
3194 /* PSIZ output is incredibly fragile and it's very hard to catch
3195 * the types of usage that break it during shader emit. Easier
3196 * just to redirect the main program to a temporary and then only
3197 * touch PSIZ with a hand-crafted MOV below.
3198 */
3199 if (SVGA3dShaderGetRegType(emit->true_psiz.value) != 0) {
3200 if (!submit_op1( emit,
3201 inst_token(SVGA3DOP_MOV),
3202 emit->true_psiz,
3203 scalar(src(emit->temp_psiz), TGSI_SWIZZLE_X) ))
3204 return FALSE;
3205 }
3206
3207 /* Need to perform various manipulations on vertex position to cope
3208 * with the different GL and D3D clip spaces.
3209 */
3210 if (emit->key.vs.need_prescale) {
3211 SVGA3dShaderDestToken temp_pos = emit->temp_pos;
3212 SVGA3dShaderDestToken depth = emit->depth_pos;
3213 SVGA3dShaderDestToken pos = emit->true_pos;
3214 unsigned offset = emit->info.file_max[TGSI_FILE_CONSTANT] + 1;
3215 struct src_register prescale_scale = src_register( SVGA3DREG_CONST,
3216 offset + 0 );
3217 struct src_register prescale_trans = src_register( SVGA3DREG_CONST,
3218 offset + 1 );
3219
3220 if (!submit_op1( emit,
3221 inst_token(SVGA3DOP_MOV),
3222 writemask(depth, TGSI_WRITEMASK_W),
3223 scalar(src(temp_pos), TGSI_SWIZZLE_W) ))
3224 return FALSE;
3225
3226 /* MUL temp_pos.xyz, temp_pos, prescale.scale
3227 * MAD result.position, temp_pos.wwww, prescale.trans, temp_pos
3228 * --> Note that prescale.trans.w == 0
3229 */
3230 if (!submit_op2( emit,
3231 inst_token(SVGA3DOP_MUL),
3232 writemask(temp_pos, TGSI_WRITEMASK_XYZ),
3233 src(temp_pos),
3234 prescale_scale ))
3235 return FALSE;
3236
3237 if (!submit_op3( emit,
3238 inst_token(SVGA3DOP_MAD),
3239 pos,
3240 swizzle(src(temp_pos), 3, 3, 3, 3),
3241 prescale_trans,
3242 src(temp_pos)))
3243 return FALSE;
3244
3245 /* Also write to depth value */
3246 if (!submit_op3( emit,
3247 inst_token(SVGA3DOP_MAD),
3248 writemask(depth, TGSI_WRITEMASK_Z),
3249 swizzle(src(temp_pos), 3, 3, 3, 3),
3250 prescale_trans,
3251 src(temp_pos) ))
3252 return FALSE;
3253 }
3254 else {
3255 SVGA3dShaderDestToken temp_pos = emit->temp_pos;
3256 SVGA3dShaderDestToken depth = emit->depth_pos;
3257 SVGA3dShaderDestToken pos = emit->true_pos;
3258 struct src_register imm_0055 = emit->imm_0055;
3259
3260 /* Adjust GL clipping coordinate space to hardware (D3D-style):
3261 *
3262 * DP4 temp_pos.z, {0,0,.5,.5}, temp_pos
3263 * MOV result.position, temp_pos
3264 */
3265 if (!submit_op2( emit,
3266 inst_token(SVGA3DOP_DP4),
3267 writemask(temp_pos, TGSI_WRITEMASK_Z),
3268 imm_0055,
3269 src(temp_pos) ))
3270 return FALSE;
3271
3272 if (!submit_op1( emit,
3273 inst_token(SVGA3DOP_MOV),
3274 pos,
3275 src(temp_pos) ))
3276 return FALSE;
3277
3278 /* Move the manipulated depth into the extra texcoord reg */
3279 if (!submit_op1( emit,
3280 inst_token(SVGA3DOP_MOV),
3281 writemask(depth, TGSI_WRITEMASK_ZW),
3282 src(temp_pos) ))
3283 return FALSE;
3284 }
3285
3286 return TRUE;
3287 }
3288
3289
3290 /**
3291 * For the pixel shader: emit the code which chooses the front
3292 * or back face color depending on triangle orientation.
3293 * This happens at the top of the fragment shader.
3294 *
3295 * 0: IF VFACE :4
3296 * 1: COLOR = FrontColor;
3297 * 2: ELSE
3298 * 3: COLOR = BackColor;
3299 * 4: ENDIF
3300 */
3301 static boolean
3302 emit_light_twoside(struct svga_shader_emitter *emit)
3303 {
3304 struct src_register vface, zero;
3305 struct src_register front[2];
3306 struct src_register back[2];
3307 SVGA3dShaderDestToken color[2];
3308 int count = emit->internal_color_count;
3309 unsigned i;
3310 SVGA3dShaderInstToken if_token;
3311
3312 if (count == 0)
3313 return TRUE;
3314
3315 vface = get_vface( emit );
3316 zero = get_zero_immediate(emit);
3317
3318 /* Can't use get_temp() to allocate the color reg as such
3319 * temporaries will be reclaimed after each instruction by the call
3320 * to reset_temp_regs().
3321 */
3322 for (i = 0; i < count; i++) {
3323 color[i] = dst_register( SVGA3DREG_TEMP, emit->nr_hw_temp++ );
3324 front[i] = emit->input_map[emit->internal_color_idx[i]];
3325
3326 /* Back is always the next input:
3327 */
3328 back[i] = front[i];
3329 back[i].base.num = front[i].base.num + 1;
3330
3331 /* Reassign the input_map to the actual front-face color:
3332 */
3333 emit->input_map[emit->internal_color_idx[i]] = src(color[i]);
3334 }
3335
3336 if_token = inst_token( SVGA3DOP_IFC );
3337
3338 if (emit->key.fs.front_ccw)
3339 if_token.control = SVGA3DOPCOMP_LT;
3340 else
3341 if_token.control = SVGA3DOPCOMP_GT;
3342
3343 if (!(emit_instruction( emit, if_token ) &&
3344 emit_src( emit, vface ) &&
3345 emit_src( emit, zero ) ))
3346 return FALSE;
3347
3348 for (i = 0; i < count; i++) {
3349 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ), color[i], front[i] ))
3350 return FALSE;
3351 }
3352
3353 if (!(emit_instruction( emit, inst_token( SVGA3DOP_ELSE))))
3354 return FALSE;
3355
3356 for (i = 0; i < count; i++) {
3357 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ), color[i], back[i] ))
3358 return FALSE;
3359 }
3360
3361 if (!emit_instruction( emit, inst_token( SVGA3DOP_ENDIF ) ))
3362 return FALSE;
3363
3364 return TRUE;
3365 }
3366
3367
3368 /**
3369 * Emit special setup code for the front/back face register in the FS.
3370 * 0: SETP_GT TEMP, VFACE, 0
3371 * where TEMP is a fake frontface register
3372 */
3373 static boolean
3374 emit_frontface(struct svga_shader_emitter *emit)
3375 {
3376 struct src_register vface;
3377 SVGA3dShaderDestToken temp;
3378 struct src_register pass, fail;
3379
3380 vface = get_vface( emit );
3381
3382 /* Can't use get_temp() to allocate the fake frontface reg as such
3383 * temporaries will be reclaimed after each instruction by the call
3384 * to reset_temp_regs().
3385 */
3386 temp = dst_register( SVGA3DREG_TEMP,
3387 emit->nr_hw_temp++ );
3388
3389 if (emit->key.fs.front_ccw) {
3390 pass = get_zero_immediate(emit);
3391 fail = get_one_immediate(emit);
3392 } else {
3393 pass = get_one_immediate(emit);
3394 fail = get_zero_immediate(emit);
3395 }
3396
3397 if (!emit_conditional(emit, PIPE_FUNC_GREATER,
3398 temp, vface, get_zero_immediate(emit),
3399 pass, fail))
3400 return FALSE;
3401
3402 /* Reassign the input_map to the actual front-face color:
3403 */
3404 emit->input_map[emit->internal_frontface_idx] = src(temp);
3405
3406 return TRUE;
3407 }
3408
3409
3410 /**
3411 * Emit code to invert the T component of the incoming texture coordinate.
3412 * This is used for drawing point sprites when
3413 * pipe_rasterizer_state::sprite_coord_mode == PIPE_SPRITE_COORD_LOWER_LEFT.
3414 */
3415 static boolean
3416 emit_inverted_texcoords(struct svga_shader_emitter *emit)
3417 {
3418 unsigned inverted_texcoords = emit->inverted_texcoords;
3419
3420 while (inverted_texcoords) {
3421 const unsigned unit = ffs(inverted_texcoords) - 1;
3422
3423 assert(emit->inverted_texcoords & (1 << unit));
3424
3425 assert(unit < ARRAY_SIZE(emit->ps_true_texcoord));
3426
3427 assert(unit < ARRAY_SIZE(emit->ps_inverted_texcoord_input));
3428
3429 assert(emit->ps_inverted_texcoord_input[unit]
3430 < ARRAY_SIZE(emit->input_map));
3431
3432 /* inverted = coord * (1, -1, 1, 1) + (0, 1, 0, 0) */
3433 if (!submit_op3(emit,
3434 inst_token(SVGA3DOP_MAD),
3435 dst(emit->ps_inverted_texcoord[unit]),
3436 emit->ps_true_texcoord[unit],
3437 get_immediate(emit, 1.0f, -1.0f, 1.0f, 1.0f),
3438 get_immediate(emit, 0.0f, 1.0f, 0.0f, 0.0f)))
3439 return FALSE;
3440
3441 /* Reassign the input_map entry to the new texcoord register */
3442 emit->input_map[emit->ps_inverted_texcoord_input[unit]] =
3443 emit->ps_inverted_texcoord[unit];
3444
3445 inverted_texcoords &= ~(1 << unit);
3446 }
3447
3448 return TRUE;
3449 }
3450
3451
3452 /**
3453 * Emit code to adjust vertex shader inputs/attributes:
3454 * - Change range from [0,1] to [-1,1] (for normalized byte/short attribs).
3455 * - Set attrib W component = 1.
3456 */
3457 static boolean
3458 emit_adjusted_vertex_attribs(struct svga_shader_emitter *emit)
3459 {
3460 unsigned adjust_mask = (emit->key.vs.adjust_attrib_range |
3461 emit->key.vs.adjust_attrib_w_1);
3462
3463 while (adjust_mask) {
3464 /* Adjust vertex attrib range and/or set W component = 1 */
3465 const unsigned index = u_bit_scan(&adjust_mask);
3466 struct src_register tmp;
3467
3468 /* allocate a temp reg */
3469 tmp = src_register(SVGA3DREG_TEMP, emit->nr_hw_temp);
3470 emit->nr_hw_temp++;
3471
3472 if (emit->key.vs.adjust_attrib_range & (1 << index)) {
3473 /* The vertex input/attribute is supposed to be a signed value in
3474 * the range [-1,1] but we actually fetched/converted it to the
3475 * range [0,1]. This most likely happens when the app specifies a
3476 * signed byte attribute but we interpreted it as unsigned bytes.
3477 * See also svga_translate_vertex_format().
3478 *
3479 * Here, we emit some extra instructions to adjust
3480 * the attribute values from [0,1] to [-1,1].
3481 *
3482 * The adjustment we implement is:
3483 * new_attrib = attrib * 2.0;
3484 * if (attrib >= 0.5)
3485 * new_attrib = new_attrib - 2.0;
3486 * This isn't exactly right (it's off by a bit or so) but close enough.
3487 */
3488 SVGA3dShaderDestToken pred_reg = dst_register(SVGA3DREG_PREDICATE, 0);
3489
3490 /* tmp = attrib * 2.0 */
3491 if (!submit_op2(emit,
3492 inst_token(SVGA3DOP_MUL),
3493 dst(tmp),
3494 emit->input_map[index],
3495 get_two_immediate(emit)))
3496 return FALSE;
3497
3498 /* pred = (attrib >= 0.5) */
3499 if (!submit_op2(emit,
3500 inst_token_setp(SVGA3DOPCOMP_GE),
3501 pred_reg,
3502 emit->input_map[index], /* vert attrib */
3503 get_half_immediate(emit))) /* 0.5 */
3504 return FALSE;
3505
3506 /* sub(pred) tmp, tmp, 2.0 */
3507 if (!submit_op3(emit,
3508 inst_token_predicated(SVGA3DOP_SUB),
3509 dst(tmp),
3510 src(pred_reg),
3511 tmp,
3512 get_two_immediate(emit)))
3513 return FALSE;
3514 }
3515 else {
3516 /* just copy the vertex input attrib to the temp register */
3517 if (!submit_op1(emit,
3518 inst_token(SVGA3DOP_MOV),
3519 dst(tmp),
3520 emit->input_map[index]))
3521 return FALSE;
3522 }
3523
3524 if (emit->key.vs.adjust_attrib_w_1 & (1 << index)) {
3525 /* move 1 into W position of tmp */
3526 if (!submit_op1(emit,
3527 inst_token(SVGA3DOP_MOV),
3528 writemask(dst(tmp), TGSI_WRITEMASK_W),
3529 get_one_immediate(emit)))
3530 return FALSE;
3531 }
3532
3533 /* Reassign the input_map entry to the new tmp register */
3534 emit->input_map[index] = tmp;
3535 }
3536
3537 return TRUE;
3538 }
3539
3540
3541 /**
3542 * Determine if we need to create the "common" immediate value which is
3543 * used for generating useful vector constants such as {0,0,0,0} and
3544 * {1,1,1,1}.
3545 * We could just do this all the time except that we want to conserve
3546 * registers whenever possible.
3547 */
3548 static boolean
3549 needs_to_create_common_immediate(const struct svga_shader_emitter *emit)
3550 {
3551 unsigned i;
3552
3553 if (emit->unit == PIPE_SHADER_FRAGMENT) {
3554 if (emit->key.fs.light_twoside)
3555 return TRUE;
3556
3557 if (emit->key.fs.white_fragments)
3558 return TRUE;
3559
3560 if (emit->emit_frontface)
3561 return TRUE;
3562
3563 if (emit->info.opcode_count[TGSI_OPCODE_DST] >= 1 ||
3564 emit->info.opcode_count[TGSI_OPCODE_SSG] >= 1 ||
3565 emit->info.opcode_count[TGSI_OPCODE_LIT] >= 1)
3566 return TRUE;
3567
3568 if (emit->inverted_texcoords)
3569 return TRUE;
3570
3571 /* look for any PIPE_SWIZZLE_0/ONE terms */
3572 for (i = 0; i < emit->key.num_textures; i++) {
3573 if (emit->key.tex[i].swizzle_r > PIPE_SWIZZLE_W ||
3574 emit->key.tex[i].swizzle_g > PIPE_SWIZZLE_W ||
3575 emit->key.tex[i].swizzle_b > PIPE_SWIZZLE_W ||
3576 emit->key.tex[i].swizzle_a > PIPE_SWIZZLE_W)
3577 return TRUE;
3578 }
3579
3580 for (i = 0; i < emit->key.num_textures; i++) {
3581 if (emit->key.tex[i].compare_mode
3582 == PIPE_TEX_COMPARE_R_TO_TEXTURE)
3583 return TRUE;
3584 }
3585 }
3586 else if (emit->unit == PIPE_SHADER_VERTEX) {
3587 if (emit->info.opcode_count[TGSI_OPCODE_CMP] >= 1)
3588 return TRUE;
3589 if (emit->key.vs.adjust_attrib_range ||
3590 emit->key.vs.adjust_attrib_w_1)
3591 return TRUE;
3592 }
3593
3594 if (emit->info.opcode_count[TGSI_OPCODE_IF] >= 1 ||
3595 emit->info.opcode_count[TGSI_OPCODE_BGNLOOP] >= 1 ||
3596 emit->info.opcode_count[TGSI_OPCODE_DDX] >= 1 ||
3597 emit->info.opcode_count[TGSI_OPCODE_DDY] >= 1 ||
3598 emit->info.opcode_count[TGSI_OPCODE_ROUND] >= 1 ||
3599 emit->info.opcode_count[TGSI_OPCODE_SGE] >= 1 ||
3600 emit->info.opcode_count[TGSI_OPCODE_SGT] >= 1 ||
3601 emit->info.opcode_count[TGSI_OPCODE_SLE] >= 1 ||
3602 emit->info.opcode_count[TGSI_OPCODE_SLT] >= 1 ||
3603 emit->info.opcode_count[TGSI_OPCODE_SNE] >= 1 ||
3604 emit->info.opcode_count[TGSI_OPCODE_SEQ] >= 1 ||
3605 emit->info.opcode_count[TGSI_OPCODE_EXP] >= 1 ||
3606 emit->info.opcode_count[TGSI_OPCODE_LOG] >= 1 ||
3607 emit->info.opcode_count[TGSI_OPCODE_XPD] >= 1 ||
3608 emit->info.opcode_count[TGSI_OPCODE_KILL] >= 1)
3609 return TRUE;
3610
3611 return FALSE;
3612 }
3613
3614
3615 /**
3616 * Do we need to create a looping constant?
3617 */
3618 static boolean
3619 needs_to_create_loop_const(const struct svga_shader_emitter *emit)
3620 {
3621 return (emit->info.opcode_count[TGSI_OPCODE_BGNLOOP] >= 1);
3622 }
3623
3624
3625 static boolean
3626 needs_to_create_arl_consts(const struct svga_shader_emitter *emit)
3627 {
3628 return (emit->num_arl_consts > 0);
3629 }
3630
3631
3632 static boolean
3633 pre_parse_add_indirect( struct svga_shader_emitter *emit,
3634 int num, int current_arl)
3635 {
3636 unsigned i;
3637 assert(num < 0);
3638
3639 for (i = 0; i < emit->num_arl_consts; ++i) {
3640 if (emit->arl_consts[i].arl_num == current_arl)
3641 break;
3642 }
3643 /* new entry */
3644 if (emit->num_arl_consts == i) {
3645 ++emit->num_arl_consts;
3646 }
3647 emit->arl_consts[i].number = (emit->arl_consts[i].number > num) ?
3648 num :
3649 emit->arl_consts[i].number;
3650 emit->arl_consts[i].arl_num = current_arl;
3651 return TRUE;
3652 }
3653
3654
3655 static boolean
3656 pre_parse_instruction( struct svga_shader_emitter *emit,
3657 const struct tgsi_full_instruction *insn,
3658 int current_arl)
3659 {
3660 if (insn->Src[0].Register.Indirect &&
3661 insn->Src[0].Indirect.File == TGSI_FILE_ADDRESS) {
3662 const struct tgsi_full_src_register *reg = &insn->Src[0];
3663 if (reg->Register.Index < 0) {
3664 pre_parse_add_indirect(emit, reg->Register.Index, current_arl);
3665 }
3666 }
3667
3668 if (insn->Src[1].Register.Indirect &&
3669 insn->Src[1].Indirect.File == TGSI_FILE_ADDRESS) {
3670 const struct tgsi_full_src_register *reg = &insn->Src[1];
3671 if (reg->Register.Index < 0) {
3672 pre_parse_add_indirect(emit, reg->Register.Index, current_arl);
3673 }
3674 }
3675
3676 if (insn->Src[2].Register.Indirect &&
3677 insn->Src[2].Indirect.File == TGSI_FILE_ADDRESS) {
3678 const struct tgsi_full_src_register *reg = &insn->Src[2];
3679 if (reg->Register.Index < 0) {
3680 pre_parse_add_indirect(emit, reg->Register.Index, current_arl);
3681 }
3682 }
3683
3684 return TRUE;
3685 }
3686
3687
3688 static boolean
3689 pre_parse_tokens( struct svga_shader_emitter *emit,
3690 const struct tgsi_token *tokens )
3691 {
3692 struct tgsi_parse_context parse;
3693 int current_arl = 0;
3694
3695 tgsi_parse_init( &parse, tokens );
3696
3697 while (!tgsi_parse_end_of_tokens( &parse )) {
3698 tgsi_parse_token( &parse );
3699 switch (parse.FullToken.Token.Type) {
3700 case TGSI_TOKEN_TYPE_IMMEDIATE:
3701 case TGSI_TOKEN_TYPE_DECLARATION:
3702 break;
3703 case TGSI_TOKEN_TYPE_INSTRUCTION:
3704 if (parse.FullToken.FullInstruction.Instruction.Opcode ==
3705 TGSI_OPCODE_ARL) {
3706 ++current_arl;
3707 }
3708 if (!pre_parse_instruction( emit, &parse.FullToken.FullInstruction,
3709 current_arl ))
3710 return FALSE;
3711 break;
3712 default:
3713 break;
3714 }
3715
3716 }
3717 return TRUE;
3718 }
3719
3720
3721 static boolean
3722 svga_shader_emit_helpers(struct svga_shader_emitter *emit)
3723 {
3724 if (needs_to_create_common_immediate( emit )) {
3725 create_common_immediate( emit );
3726 }
3727 if (needs_to_create_loop_const( emit )) {
3728 create_loop_const( emit );
3729 }
3730 if (needs_to_create_arl_consts( emit )) {
3731 create_arl_consts( emit );
3732 }
3733
3734 if (emit->unit == PIPE_SHADER_FRAGMENT) {
3735 if (!svga_shader_emit_samplers_decl( emit ))
3736 return FALSE;
3737
3738 if (!emit_ps_preamble( emit ))
3739 return FALSE;
3740
3741 if (emit->key.fs.light_twoside) {
3742 if (!emit_light_twoside( emit ))
3743 return FALSE;
3744 }
3745 if (emit->emit_frontface) {
3746 if (!emit_frontface( emit ))
3747 return FALSE;
3748 }
3749 if (emit->inverted_texcoords) {
3750 if (!emit_inverted_texcoords( emit ))
3751 return FALSE;
3752 }
3753 }
3754 else {
3755 assert(emit->unit == PIPE_SHADER_VERTEX);
3756 if (emit->key.vs.adjust_attrib_range) {
3757 if (!emit_adjusted_vertex_attribs(emit) ||
3758 emit->key.vs.adjust_attrib_w_1) {
3759 return FALSE;
3760 }
3761 }
3762 }
3763
3764 return TRUE;
3765 }
3766
3767
3768 /**
3769 * This is the main entrypoint into the TGSI instruction translater.
3770 * Translate TGSI shader tokens into an SVGA shader.
3771 */
3772 boolean
3773 svga_shader_emit_instructions(struct svga_shader_emitter *emit,
3774 const struct tgsi_token *tokens)
3775 {
3776 struct tgsi_parse_context parse;
3777 const struct tgsi_token *new_tokens = NULL;
3778 boolean ret = TRUE;
3779 boolean helpers_emitted = FALSE;
3780 unsigned line_nr = 0;
3781
3782 if (emit->unit == PIPE_SHADER_FRAGMENT && emit->key.fs.pstipple) {
3783 unsigned unit;
3784
3785 new_tokens = util_pstipple_create_fragment_shader(tokens, &unit, 0,
3786 TGSI_FILE_INPUT);
3787
3788 if (new_tokens) {
3789 /* Setup texture state for stipple */
3790 emit->sampler_target[unit] = TGSI_TEXTURE_2D;
3791 emit->key.tex[unit].swizzle_r = TGSI_SWIZZLE_X;
3792 emit->key.tex[unit].swizzle_g = TGSI_SWIZZLE_Y;
3793 emit->key.tex[unit].swizzle_b = TGSI_SWIZZLE_Z;
3794 emit->key.tex[unit].swizzle_a = TGSI_SWIZZLE_W;
3795
3796 emit->pstipple_sampler_unit = unit;
3797
3798 tokens = new_tokens;
3799 }
3800 }
3801
3802 tgsi_parse_init( &parse, tokens );
3803 emit->internal_imm_count = 0;
3804
3805 if (emit->unit == PIPE_SHADER_VERTEX) {
3806 ret = emit_vs_preamble( emit );
3807 if (!ret)
3808 goto done;
3809 }
3810
3811 pre_parse_tokens(emit, tokens);
3812
3813 while (!tgsi_parse_end_of_tokens( &parse )) {
3814 tgsi_parse_token( &parse );
3815
3816 switch (parse.FullToken.Token.Type) {
3817 case TGSI_TOKEN_TYPE_IMMEDIATE:
3818 ret = svga_emit_immediate( emit, &parse.FullToken.FullImmediate );
3819 if (!ret)
3820 goto done;
3821 break;
3822
3823 case TGSI_TOKEN_TYPE_DECLARATION:
3824 ret = svga_translate_decl_sm30( emit, &parse.FullToken.FullDeclaration );
3825 if (!ret)
3826 goto done;
3827 break;
3828
3829 case TGSI_TOKEN_TYPE_INSTRUCTION:
3830 if (!helpers_emitted) {
3831 if (!svga_shader_emit_helpers( emit ))
3832 goto done;
3833 helpers_emitted = TRUE;
3834 }
3835 ret = svga_emit_instruction( emit,
3836 line_nr++,
3837 &parse.FullToken.FullInstruction );
3838 if (!ret)
3839 goto done;
3840 break;
3841 default:
3842 break;
3843 }
3844
3845 reset_temp_regs( emit );
3846 }
3847
3848 /* Need to terminate the current subroutine. Note that the
3849 * hardware doesn't tolerate shaders without sub-routines
3850 * terminating with RET+END.
3851 */
3852 if (!emit->in_main_func) {
3853 ret = emit_instruction( emit, inst_token( SVGA3DOP_RET ) );
3854 if (!ret)
3855 goto done;
3856 }
3857
3858 assert(emit->dynamic_branching_level == 0);
3859
3860 /* Need to terminate the whole shader:
3861 */
3862 ret = emit_instruction( emit, inst_token( SVGA3DOP_END ) );
3863 if (!ret)
3864 goto done;
3865
3866 done:
3867 tgsi_parse_free( &parse );
3868 if (new_tokens) {
3869 tgsi_free_tokens(new_tokens);
3870 }
3871
3872 return ret;
3873 }