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svga: check that we don't exceed input/ouput register limits
[mesa.git] / src / gallium / drivers / svga / svga_tgsi_insn.c
1 /**********************************************************
2 * Copyright 2008-2009 VMware, Inc. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 **********************************************************/
25
26
27 #include "pipe/p_shader_tokens.h"
28 #include "tgsi/tgsi_parse.h"
29 #include "util/u_memory.h"
30 #include "util/u_math.h"
31
32 #include "svga_tgsi_emit.h"
33 #include "svga_context.h"
34
35
36 static boolean emit_vs_postamble( struct svga_shader_emitter *emit );
37 static boolean emit_ps_postamble( struct svga_shader_emitter *emit );
38
39
40
41
42 static unsigned
43 translate_opcode(
44 uint opcode )
45 {
46 switch (opcode) {
47 case TGSI_OPCODE_ABS: return SVGA3DOP_ABS;
48 case TGSI_OPCODE_ADD: return SVGA3DOP_ADD;
49 case TGSI_OPCODE_BREAKC: return SVGA3DOP_BREAKC;
50 case TGSI_OPCODE_DP2A: return SVGA3DOP_DP2ADD;
51 case TGSI_OPCODE_DP3: return SVGA3DOP_DP3;
52 case TGSI_OPCODE_DP4: return SVGA3DOP_DP4;
53 case TGSI_OPCODE_FRC: return SVGA3DOP_FRC;
54 case TGSI_OPCODE_MAD: return SVGA3DOP_MAD;
55 case TGSI_OPCODE_MAX: return SVGA3DOP_MAX;
56 case TGSI_OPCODE_MIN: return SVGA3DOP_MIN;
57 case TGSI_OPCODE_MOV: return SVGA3DOP_MOV;
58 case TGSI_OPCODE_MUL: return SVGA3DOP_MUL;
59 case TGSI_OPCODE_NOP: return SVGA3DOP_NOP;
60 case TGSI_OPCODE_NRM4: return SVGA3DOP_NRM;
61 default:
62 debug_printf("Unkown opcode %u\n", opcode);
63 assert( 0 );
64 return SVGA3DOP_LAST_INST;
65 }
66 }
67
68
69 static unsigned translate_file( unsigned file )
70 {
71 switch (file) {
72 case TGSI_FILE_TEMPORARY: return SVGA3DREG_TEMP;
73 case TGSI_FILE_INPUT: return SVGA3DREG_INPUT;
74 case TGSI_FILE_OUTPUT: return SVGA3DREG_OUTPUT; /* VS3.0+ only */
75 case TGSI_FILE_IMMEDIATE: return SVGA3DREG_CONST;
76 case TGSI_FILE_CONSTANT: return SVGA3DREG_CONST;
77 case TGSI_FILE_SAMPLER: return SVGA3DREG_SAMPLER;
78 case TGSI_FILE_ADDRESS: return SVGA3DREG_ADDR;
79 default:
80 assert( 0 );
81 return SVGA3DREG_TEMP;
82 }
83 }
84
85
86
87
88
89
90 static SVGA3dShaderDestToken
91 translate_dst_register( struct svga_shader_emitter *emit,
92 const struct tgsi_full_instruction *insn,
93 unsigned idx )
94 {
95 const struct tgsi_full_dst_register *reg = &insn->Dst[idx];
96 SVGA3dShaderDestToken dest;
97
98 switch (reg->Register.File) {
99 case TGSI_FILE_OUTPUT:
100 /* Output registers encode semantic information in their name.
101 * Need to lookup a table built at decl time:
102 */
103 dest = emit->output_map[reg->Register.Index];
104 break;
105
106 default:
107 dest = dst_register( translate_file( reg->Register.File ),
108 reg->Register.Index );
109 break;
110 }
111
112 dest.mask = reg->Register.WriteMask;
113 assert(dest.mask);
114
115 if (insn->Instruction.Saturate)
116 dest.dstMod = SVGA3DDSTMOD_SATURATE;
117
118 return dest;
119 }
120
121
122 static struct src_register
123 swizzle( struct src_register src,
124 int x,
125 int y,
126 int z,
127 int w )
128 {
129 x = (src.base.swizzle >> (x * 2)) & 0x3;
130 y = (src.base.swizzle >> (y * 2)) & 0x3;
131 z = (src.base.swizzle >> (z * 2)) & 0x3;
132 w = (src.base.swizzle >> (w * 2)) & 0x3;
133
134 src.base.swizzle = TRANSLATE_SWIZZLE(x,y,z,w);
135
136 return src;
137 }
138
139 static struct src_register
140 scalar( struct src_register src,
141 int comp )
142 {
143 return swizzle( src, comp, comp, comp, comp );
144 }
145
146 static INLINE boolean
147 svga_arl_needs_adjustment( const struct svga_shader_emitter *emit )
148 {
149 int i;
150
151 for (i = 0; i < emit->num_arl_consts; ++i) {
152 if (emit->arl_consts[i].arl_num == emit->current_arl)
153 return TRUE;
154 }
155 return FALSE;
156 }
157
158 static INLINE int
159 svga_arl_adjustment( const struct svga_shader_emitter *emit )
160 {
161 int i;
162
163 for (i = 0; i < emit->num_arl_consts; ++i) {
164 if (emit->arl_consts[i].arl_num == emit->current_arl)
165 return emit->arl_consts[i].number;
166 }
167 return 0;
168 }
169
170 static struct src_register
171 translate_src_register( const struct svga_shader_emitter *emit,
172 const struct tgsi_full_src_register *reg )
173 {
174 struct src_register src;
175
176 switch (reg->Register.File) {
177 case TGSI_FILE_INPUT:
178 /* Input registers are referred to by their semantic name rather
179 * than by index. Use the mapping build up from the decls:
180 */
181 src = emit->input_map[reg->Register.Index];
182 break;
183
184 case TGSI_FILE_IMMEDIATE:
185 /* Immediates are appended after TGSI constants in the D3D
186 * constant buffer.
187 */
188 src = src_register( translate_file( reg->Register.File ),
189 reg->Register.Index +
190 emit->imm_start );
191 break;
192
193 default:
194 src = src_register( translate_file( reg->Register.File ),
195 reg->Register.Index );
196
197 break;
198 }
199
200 /* Indirect addressing.
201 */
202 if (reg->Register.Indirect) {
203 if (emit->unit == PIPE_SHADER_FRAGMENT) {
204 /* Pixel shaders have only loop registers for relative
205 * addressing into inputs. Ignore the redundant address
206 * register, the contents of aL should be in sync with it.
207 */
208 if (reg->Register.File == TGSI_FILE_INPUT) {
209 src.base.relAddr = 1;
210 src.indirect = src_token(SVGA3DREG_LOOP, 0);
211 }
212 }
213 else {
214 /* Constant buffers only.
215 */
216 if (reg->Register.File == TGSI_FILE_CONSTANT) {
217 /* we shift the offset towards the minimum */
218 if (svga_arl_needs_adjustment( emit )) {
219 src.base.num -= svga_arl_adjustment( emit );
220 }
221 src.base.relAddr = 1;
222
223 /* Not really sure what should go in the second token:
224 */
225 src.indirect = src_token( SVGA3DREG_ADDR,
226 reg->Indirect.Index );
227
228 src.indirect.swizzle = SWIZZLE_XXXX;
229 }
230 }
231 }
232
233 src = swizzle( src,
234 reg->Register.SwizzleX,
235 reg->Register.SwizzleY,
236 reg->Register.SwizzleZ,
237 reg->Register.SwizzleW );
238
239 /* src.mod isn't a bitfield, unfortunately:
240 * See tgsi_util_get_full_src_register_sign_mode for implementation details.
241 */
242 if (reg->Register.Absolute) {
243 if (reg->Register.Negate)
244 src.base.srcMod = SVGA3DSRCMOD_ABSNEG;
245 else
246 src.base.srcMod = SVGA3DSRCMOD_ABS;
247 }
248 else {
249 if (reg->Register.Negate)
250 src.base.srcMod = SVGA3DSRCMOD_NEG;
251 else
252 src.base.srcMod = SVGA3DSRCMOD_NONE;
253 }
254
255 return src;
256 }
257
258
259 /*
260 * Get a temporary register, return -1 if none available
261 */
262 static INLINE SVGA3dShaderDestToken
263 get_temp( struct svga_shader_emitter *emit )
264 {
265 int i = emit->nr_hw_temp + emit->internal_temp_count++;
266
267 return dst_register( SVGA3DREG_TEMP, i );
268 }
269
270 /* Release a single temp. Currently only effective if it was the last
271 * allocated temp, otherwise release will be delayed until the next
272 * call to reset_temp_regs().
273 */
274 static INLINE void
275 release_temp( struct svga_shader_emitter *emit,
276 SVGA3dShaderDestToken temp )
277 {
278 if (temp.num == emit->internal_temp_count - 1)
279 emit->internal_temp_count--;
280 }
281
282 static void reset_temp_regs( struct svga_shader_emitter *emit )
283 {
284 emit->internal_temp_count = 0;
285 }
286
287
288 /* Replace the src with the temporary specified in the dst, but copying
289 * only the necessary channels, and preserving the original swizzle (which is
290 * important given that several opcodes have constraints in the allowed
291 * swizzles).
292 */
293 static boolean emit_repl( struct svga_shader_emitter *emit,
294 SVGA3dShaderDestToken dst,
295 struct src_register *src0)
296 {
297 unsigned src0_swizzle;
298 unsigned chan;
299
300 assert(SVGA3dShaderGetRegType(dst.value) == SVGA3DREG_TEMP);
301
302 src0_swizzle = src0->base.swizzle;
303
304 dst.mask = 0;
305 for (chan = 0; chan < 4; ++chan) {
306 unsigned swizzle = (src0_swizzle >> (chan *2)) & 0x3;
307 dst.mask |= 1 << swizzle;
308 }
309 assert(dst.mask);
310
311 src0->base.swizzle = SVGA3DSWIZZLE_NONE;
312
313 if (!emit_op1( emit, inst_token( SVGA3DOP_MOV ), dst, *src0 ))
314 return FALSE;
315
316 *src0 = src( dst );
317 src0->base.swizzle = src0_swizzle;
318
319 return TRUE;
320 }
321
322
323 static boolean submit_op0( struct svga_shader_emitter *emit,
324 SVGA3dShaderInstToken inst,
325 SVGA3dShaderDestToken dest )
326 {
327 return (emit_instruction( emit, inst ) &&
328 emit_dst( emit, dest ));
329 }
330
331 static boolean submit_op1( struct svga_shader_emitter *emit,
332 SVGA3dShaderInstToken inst,
333 SVGA3dShaderDestToken dest,
334 struct src_register src0 )
335 {
336 return emit_op1( emit, inst, dest, src0 );
337 }
338
339
340 /* SVGA shaders may not refer to >1 constant register in a single
341 * instruction. This function checks for that usage and inserts a
342 * move to temporary if detected.
343 *
344 * The same applies to input registers -- at most a single input
345 * register may be read by any instruction.
346 */
347 static boolean submit_op2( struct svga_shader_emitter *emit,
348 SVGA3dShaderInstToken inst,
349 SVGA3dShaderDestToken dest,
350 struct src_register src0,
351 struct src_register src1 )
352 {
353 SVGA3dShaderDestToken temp;
354 SVGA3dShaderRegType type0, type1;
355 boolean need_temp = FALSE;
356
357 temp.value = 0;
358 type0 = SVGA3dShaderGetRegType( src0.base.value );
359 type1 = SVGA3dShaderGetRegType( src1.base.value );
360
361 if (type0 == SVGA3DREG_CONST &&
362 type1 == SVGA3DREG_CONST &&
363 src0.base.num != src1.base.num)
364 need_temp = TRUE;
365
366 if (type0 == SVGA3DREG_INPUT &&
367 type1 == SVGA3DREG_INPUT &&
368 src0.base.num != src1.base.num)
369 need_temp = TRUE;
370
371 if (need_temp) {
372 temp = get_temp( emit );
373
374 if (!emit_repl( emit, temp, &src0 ))
375 return FALSE;
376 }
377
378 if (!emit_op2( emit, inst, dest, src0, src1 ))
379 return FALSE;
380
381 if (need_temp)
382 release_temp( emit, temp );
383
384 return TRUE;
385 }
386
387
388 /* SVGA shaders may not refer to >1 constant register in a single
389 * instruction. This function checks for that usage and inserts a
390 * move to temporary if detected.
391 */
392 static boolean submit_op3( struct svga_shader_emitter *emit,
393 SVGA3dShaderInstToken inst,
394 SVGA3dShaderDestToken dest,
395 struct src_register src0,
396 struct src_register src1,
397 struct src_register src2 )
398 {
399 SVGA3dShaderDestToken temp0;
400 SVGA3dShaderDestToken temp1;
401 boolean need_temp0 = FALSE;
402 boolean need_temp1 = FALSE;
403 SVGA3dShaderRegType type0, type1, type2;
404
405 temp0.value = 0;
406 temp1.value = 0;
407 type0 = SVGA3dShaderGetRegType( src0.base.value );
408 type1 = SVGA3dShaderGetRegType( src1.base.value );
409 type2 = SVGA3dShaderGetRegType( src2.base.value );
410
411 if (inst.op != SVGA3DOP_SINCOS) {
412 if (type0 == SVGA3DREG_CONST &&
413 ((type1 == SVGA3DREG_CONST && src0.base.num != src1.base.num) ||
414 (type2 == SVGA3DREG_CONST && src0.base.num != src2.base.num)))
415 need_temp0 = TRUE;
416
417 if (type1 == SVGA3DREG_CONST &&
418 (type2 == SVGA3DREG_CONST && src1.base.num != src2.base.num))
419 need_temp1 = TRUE;
420 }
421
422 if (type0 == SVGA3DREG_INPUT &&
423 ((type1 == SVGA3DREG_INPUT && src0.base.num != src1.base.num) ||
424 (type2 == SVGA3DREG_INPUT && src0.base.num != src2.base.num)))
425 need_temp0 = TRUE;
426
427 if (type1 == SVGA3DREG_INPUT &&
428 (type2 == SVGA3DREG_INPUT && src1.base.num != src2.base.num))
429 need_temp1 = TRUE;
430
431 if (need_temp0) {
432 temp0 = get_temp( emit );
433
434 if (!emit_repl( emit, temp0, &src0 ))
435 return FALSE;
436 }
437
438 if (need_temp1) {
439 temp1 = get_temp( emit );
440
441 if (!emit_repl( emit, temp1, &src1 ))
442 return FALSE;
443 }
444
445 if (!emit_op3( emit, inst, dest, src0, src1, src2 ))
446 return FALSE;
447
448 if (need_temp1)
449 release_temp( emit, temp1 );
450 if (need_temp0)
451 release_temp( emit, temp0 );
452 return TRUE;
453 }
454
455
456
457
458 /* SVGA shaders may not refer to >1 constant register in a single
459 * instruction. This function checks for that usage and inserts a
460 * move to temporary if detected.
461 */
462 static boolean submit_op4( struct svga_shader_emitter *emit,
463 SVGA3dShaderInstToken inst,
464 SVGA3dShaderDestToken dest,
465 struct src_register src0,
466 struct src_register src1,
467 struct src_register src2,
468 struct src_register src3)
469 {
470 SVGA3dShaderDestToken temp0;
471 SVGA3dShaderDestToken temp3;
472 boolean need_temp0 = FALSE;
473 boolean need_temp3 = FALSE;
474 SVGA3dShaderRegType type0, type1, type2, type3;
475
476 temp0.value = 0;
477 temp3.value = 0;
478 type0 = SVGA3dShaderGetRegType( src0.base.value );
479 type1 = SVGA3dShaderGetRegType( src1.base.value );
480 type2 = SVGA3dShaderGetRegType( src2.base.value );
481 type3 = SVGA3dShaderGetRegType( src2.base.value );
482
483 /* Make life a little easier - this is only used by the TXD
484 * instruction which is guaranteed not to have a constant/input reg
485 * in one slot at least:
486 */
487 assert(type1 == SVGA3DREG_SAMPLER);
488
489 if (type0 == SVGA3DREG_CONST &&
490 ((type3 == SVGA3DREG_CONST && src0.base.num != src3.base.num) ||
491 (type2 == SVGA3DREG_CONST && src0.base.num != src2.base.num)))
492 need_temp0 = TRUE;
493
494 if (type3 == SVGA3DREG_CONST &&
495 (type2 == SVGA3DREG_CONST && src3.base.num != src2.base.num))
496 need_temp3 = TRUE;
497
498 if (type0 == SVGA3DREG_INPUT &&
499 ((type3 == SVGA3DREG_INPUT && src0.base.num != src3.base.num) ||
500 (type2 == SVGA3DREG_INPUT && src0.base.num != src2.base.num)))
501 need_temp0 = TRUE;
502
503 if (type3 == SVGA3DREG_INPUT &&
504 (type2 == SVGA3DREG_INPUT && src3.base.num != src2.base.num))
505 need_temp3 = TRUE;
506
507 if (need_temp0) {
508 temp0 = get_temp( emit );
509
510 if (!emit_repl( emit, temp0, &src0 ))
511 return FALSE;
512 }
513
514 if (need_temp3) {
515 temp3 = get_temp( emit );
516
517 if (!emit_repl( emit, temp3, &src3 ))
518 return FALSE;
519 }
520
521 if (!emit_op4( emit, inst, dest, src0, src1, src2, src3 ))
522 return FALSE;
523
524 if (need_temp3)
525 release_temp( emit, temp3 );
526 if (need_temp0)
527 release_temp( emit, temp0 );
528 return TRUE;
529 }
530
531
532 static boolean alias_src_dst( struct src_register src,
533 SVGA3dShaderDestToken dst )
534 {
535 if (src.base.num != dst.num)
536 return FALSE;
537
538 if (SVGA3dShaderGetRegType(dst.value) !=
539 SVGA3dShaderGetRegType(src.base.value))
540 return FALSE;
541
542 return TRUE;
543 }
544
545
546 static boolean submit_lrp(struct svga_shader_emitter *emit,
547 SVGA3dShaderDestToken dst,
548 struct src_register src0,
549 struct src_register src1,
550 struct src_register src2)
551 {
552 SVGA3dShaderDestToken tmp;
553 boolean need_dst_tmp = FALSE;
554
555 /* The dst reg must be a temporary, and not be the same as src0 or src2 */
556 if (SVGA3dShaderGetRegType(dst.value) != SVGA3DREG_TEMP ||
557 alias_src_dst(src0, dst) ||
558 alias_src_dst(src2, dst))
559 need_dst_tmp = TRUE;
560
561 if (need_dst_tmp) {
562 tmp = get_temp( emit );
563 tmp.mask = dst.mask;
564 }
565 else {
566 tmp = dst;
567 }
568
569 if (!submit_op3(emit, inst_token( SVGA3DOP_LRP ), tmp, src0, src1, src2))
570 return FALSE;
571
572 if (need_dst_tmp) {
573 if (!submit_op1(emit, inst_token( SVGA3DOP_MOV ), dst, src( tmp )))
574 return FALSE;
575 }
576
577 return TRUE;
578 }
579
580
581 static boolean emit_def_const( struct svga_shader_emitter *emit,
582 SVGA3dShaderConstType type,
583 unsigned idx,
584 float a,
585 float b,
586 float c,
587 float d )
588 {
589 SVGA3DOpDefArgs def;
590 SVGA3dShaderInstToken opcode;
591
592 switch (type) {
593 case SVGA3D_CONST_TYPE_FLOAT:
594 opcode = inst_token( SVGA3DOP_DEF );
595 def.dst = dst_register( SVGA3DREG_CONST, idx );
596 def.constValues[0] = a;
597 def.constValues[1] = b;
598 def.constValues[2] = c;
599 def.constValues[3] = d;
600 break;
601 case SVGA3D_CONST_TYPE_INT:
602 opcode = inst_token( SVGA3DOP_DEFI );
603 def.dst = dst_register( SVGA3DREG_CONSTINT, idx );
604 def.constIValues[0] = (int)a;
605 def.constIValues[1] = (int)b;
606 def.constIValues[2] = (int)c;
607 def.constIValues[3] = (int)d;
608 break;
609 default:
610 assert(0);
611 opcode = inst_token( SVGA3DOP_NOP );
612 break;
613 }
614
615 if (!emit_instruction(emit, opcode) ||
616 !svga_shader_emit_dwords( emit, def.values, Elements(def.values)))
617 return FALSE;
618
619 return TRUE;
620 }
621
622 static INLINE boolean
623 create_zero_immediate( struct svga_shader_emitter *emit )
624 {
625 unsigned idx = emit->nr_hw_float_const++;
626
627 /* Emit the constant (0, 0, -1, 1) and use swizzling to generate
628 * other useful vectors.
629 */
630 if (!emit_def_const( emit, SVGA3D_CONST_TYPE_FLOAT,
631 idx, 0, 0, -1, 1 ))
632 return FALSE;
633
634 emit->zero_immediate_idx = idx;
635 emit->created_zero_immediate = TRUE;
636
637 return TRUE;
638 }
639
640 static INLINE boolean
641 create_loop_const( struct svga_shader_emitter *emit )
642 {
643 unsigned idx = emit->nr_hw_int_const++;
644
645 if (!emit_def_const( emit, SVGA3D_CONST_TYPE_INT, idx,
646 255, /* iteration count */
647 0, /* initial value */
648 1, /* step size */
649 0 /* not used, must be 0 */))
650 return FALSE;
651
652 emit->loop_const_idx = idx;
653 emit->created_loop_const = TRUE;
654
655 return TRUE;
656 }
657
658 static INLINE boolean
659 create_sincos_consts( struct svga_shader_emitter *emit )
660 {
661 unsigned idx = emit->nr_hw_float_const++;
662
663 if (!emit_def_const( emit, SVGA3D_CONST_TYPE_FLOAT, idx,
664 -1.5500992e-006f,
665 -2.1701389e-005f,
666 0.0026041667f,
667 0.00026041668f ))
668 return FALSE;
669
670 emit->sincos_consts_idx = idx;
671 idx = emit->nr_hw_float_const++;
672
673 if (!emit_def_const( emit, SVGA3D_CONST_TYPE_FLOAT, idx,
674 -0.020833334f,
675 -0.12500000f,
676 1.0f,
677 0.50000000f ))
678 return FALSE;
679
680 emit->created_sincos_consts = TRUE;
681
682 return TRUE;
683 }
684
685 static INLINE boolean
686 create_arl_consts( struct svga_shader_emitter *emit )
687 {
688 int i;
689
690 for (i = 0; i < emit->num_arl_consts; i += 4) {
691 int j;
692 unsigned idx = emit->nr_hw_float_const++;
693 float vals[4];
694 for (j = 0; j < 4 && (j + i) < emit->num_arl_consts; ++j) {
695 vals[j] = emit->arl_consts[i + j].number;
696 emit->arl_consts[i + j].idx = idx;
697 switch (j) {
698 case 0:
699 emit->arl_consts[i + 0].swizzle = TGSI_SWIZZLE_X;
700 break;
701 case 1:
702 emit->arl_consts[i + 0].swizzle = TGSI_SWIZZLE_Y;
703 break;
704 case 2:
705 emit->arl_consts[i + 0].swizzle = TGSI_SWIZZLE_Z;
706 break;
707 case 3:
708 emit->arl_consts[i + 0].swizzle = TGSI_SWIZZLE_W;
709 break;
710 }
711 }
712 while (j < 4)
713 vals[j++] = 0;
714
715 if (!emit_def_const( emit, SVGA3D_CONST_TYPE_FLOAT, idx,
716 vals[0], vals[1],
717 vals[2], vals[3]))
718 return FALSE;
719 }
720
721 return TRUE;
722 }
723
724 static INLINE struct src_register
725 get_vface( struct svga_shader_emitter *emit )
726 {
727 assert(emit->emitted_vface);
728 return src_register(SVGA3DREG_MISCTYPE,
729 SVGA3DMISCREG_FACE);
730 }
731
732 /* returns {0, 0, 0, 1} immediate */
733 static INLINE struct src_register
734 get_zero_immediate( struct svga_shader_emitter *emit )
735 {
736 assert(emit->created_zero_immediate);
737 assert(emit->zero_immediate_idx >= 0);
738 return swizzle(src_register( SVGA3DREG_CONST,
739 emit->zero_immediate_idx),
740 0, 0, 0, 3);
741 }
742
743 /* returns {1, 1, 1, -1} immediate */
744 static INLINE struct src_register
745 get_pos_neg_one_immediate( struct svga_shader_emitter *emit )
746 {
747 assert(emit->created_zero_immediate);
748 assert(emit->zero_immediate_idx >= 0);
749 return swizzle(src_register( SVGA3DREG_CONST,
750 emit->zero_immediate_idx),
751 3, 3, 3, 2);
752 }
753
754 /* returns the loop const */
755 static INLINE struct src_register
756 get_loop_const( struct svga_shader_emitter *emit )
757 {
758 assert(emit->created_loop_const);
759 assert(emit->loop_const_idx >= 0);
760 return src_register( SVGA3DREG_CONSTINT,
761 emit->loop_const_idx );
762 }
763
764 /* returns a sincos const */
765 static INLINE struct src_register
766 get_sincos_const( struct svga_shader_emitter *emit,
767 unsigned index )
768 {
769 assert(emit->created_sincos_consts);
770 assert(emit->sincos_consts_idx >= 0);
771 assert(index == 0 || index == 1);
772 return src_register( SVGA3DREG_CONST,
773 emit->sincos_consts_idx + index );
774 }
775
776 static INLINE struct src_register
777 get_fake_arl_const( struct svga_shader_emitter *emit )
778 {
779 struct src_register reg;
780 int idx = 0, swizzle = 0, i;
781
782 for (i = 0; i < emit->num_arl_consts; ++ i) {
783 if (emit->arl_consts[i].arl_num == emit->current_arl) {
784 idx = emit->arl_consts[i].idx;
785 swizzle = emit->arl_consts[i].swizzle;
786 }
787 }
788
789 reg = src_register( SVGA3DREG_CONST, idx );
790 return scalar(reg, swizzle);
791 }
792
793 static INLINE struct src_register
794 get_tex_dimensions( struct svga_shader_emitter *emit, int sampler_num )
795 {
796 int idx;
797 struct src_register reg;
798
799 /* the width/height indexes start right after constants */
800 idx = emit->key.fkey.tex[sampler_num].width_height_idx +
801 emit->info.file_max[TGSI_FILE_CONSTANT] + 1;
802
803 reg = src_register( SVGA3DREG_CONST, idx );
804 return reg;
805 }
806
807 static boolean emit_fake_arl(struct svga_shader_emitter *emit,
808 const struct tgsi_full_instruction *insn)
809 {
810 const struct src_register src0 = translate_src_register(
811 emit, &insn->Src[0] );
812 struct src_register src1 = get_fake_arl_const( emit );
813 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
814 SVGA3dShaderDestToken tmp = get_temp( emit );
815
816 if (!submit_op1(emit, inst_token( SVGA3DOP_MOV ), tmp, src0))
817 return FALSE;
818
819 if (!submit_op2( emit, inst_token( SVGA3DOP_ADD ), tmp, src( tmp ),
820 src1))
821 return FALSE;
822
823 /* replicate the original swizzle */
824 src1 = src(tmp);
825 src1.base.swizzle = src0.base.swizzle;
826
827 return submit_op1( emit, inst_token( SVGA3DOP_MOVA ),
828 dst, src1 );
829 }
830
831 static boolean emit_if(struct svga_shader_emitter *emit,
832 const struct tgsi_full_instruction *insn)
833 {
834 struct src_register src0 = translate_src_register(
835 emit, &insn->Src[0] );
836 struct src_register zero = get_zero_immediate( emit );
837 SVGA3dShaderInstToken if_token = inst_token( SVGA3DOP_IFC );
838
839 if_token.control = SVGA3DOPCOMPC_NE;
840 zero = scalar(zero, TGSI_SWIZZLE_X);
841
842 if (SVGA3dShaderGetRegType(src0.base.value) == SVGA3DREG_CONST) {
843 /*
844 * Max different constant registers readable per IFC instruction is 1.
845 */
846
847 SVGA3dShaderDestToken tmp = get_temp( emit );
848
849 if (!submit_op1(emit, inst_token( SVGA3DOP_MOV ), tmp, src0))
850 return FALSE;
851
852 src0 = scalar(src( tmp ), TGSI_SWIZZLE_X);
853 }
854
855 emit->dynamic_branching_level++;
856
857 return (emit_instruction( emit, if_token ) &&
858 emit_src( emit, src0 ) &&
859 emit_src( emit, zero ) );
860 }
861
862 static boolean emit_endif(struct svga_shader_emitter *emit,
863 const struct tgsi_full_instruction *insn)
864 {
865 emit->dynamic_branching_level--;
866
867 return (emit_instruction( emit,
868 inst_token( SVGA3DOP_ENDIF )));
869 }
870
871 static boolean emit_else(struct svga_shader_emitter *emit,
872 const struct tgsi_full_instruction *insn)
873 {
874 return (emit_instruction( emit,
875 inst_token( SVGA3DOP_ELSE )));
876 }
877
878 /* Translate the following TGSI FLR instruction.
879 * FLR DST, SRC
880 * To the following SVGA3D instruction sequence.
881 * FRC TMP, SRC
882 * SUB DST, SRC, TMP
883 */
884 static boolean emit_floor(struct svga_shader_emitter *emit,
885 const struct tgsi_full_instruction *insn )
886 {
887 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
888 const struct src_register src0 = translate_src_register(
889 emit, &insn->Src[0] );
890 SVGA3dShaderDestToken temp = get_temp( emit );
891
892 /* FRC TMP, SRC */
893 if (!submit_op1( emit, inst_token( SVGA3DOP_FRC ), temp, src0 ))
894 return FALSE;
895
896 /* SUB DST, SRC, TMP */
897 if (!submit_op2( emit, inst_token( SVGA3DOP_ADD ), dst, src0,
898 negate( src( temp ) ) ))
899 return FALSE;
900
901 return TRUE;
902 }
903
904
905 /* Translate the following TGSI CMP instruction.
906 * CMP DST, SRC0, SRC1, SRC2
907 * To the following SVGA3D instruction sequence.
908 * CMP DST, SRC0, SRC2, SRC1
909 */
910 static boolean emit_cmp(struct svga_shader_emitter *emit,
911 const struct tgsi_full_instruction *insn )
912 {
913 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
914 const struct src_register src0 = translate_src_register(
915 emit, &insn->Src[0] );
916 const struct src_register src1 = translate_src_register(
917 emit, &insn->Src[1] );
918 const struct src_register src2 = translate_src_register(
919 emit, &insn->Src[2] );
920
921 if (emit->unit == PIPE_SHADER_VERTEX) {
922 SVGA3dShaderDestToken temp = get_temp(emit);
923 struct src_register zero = scalar(get_zero_immediate(emit), TGSI_SWIZZLE_X);
924
925 /* Since vertex shaders don't support the CMP instruction,
926 * simulate it with SLT and LRP instructions.
927 * SLT TMP, SRC0, 0.0
928 * LRP DST, TMP, SRC1, SRC2
929 */
930 if (!submit_op2(emit, inst_token(SVGA3DOP_SLT), temp, src0, zero))
931 return FALSE;
932 return submit_lrp(emit, dst, src(temp), src1, src2);
933 }
934
935 /* CMP DST, SRC0, SRC2, SRC1 */
936 return submit_op3( emit, inst_token( SVGA3DOP_CMP ), dst, src0, src2, src1);
937 }
938
939
940
941 /* Translate the following TGSI DIV instruction.
942 * DIV DST.xy, SRC0, SRC1
943 * To the following SVGA3D instruction sequence.
944 * RCP TMP.x, SRC1.xxxx
945 * RCP TMP.y, SRC1.yyyy
946 * MUL DST.xy, SRC0, TMP
947 */
948 static boolean emit_div(struct svga_shader_emitter *emit,
949 const struct tgsi_full_instruction *insn )
950 {
951 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
952 const struct src_register src0 = translate_src_register(
953 emit, &insn->Src[0] );
954 const struct src_register src1 = translate_src_register(
955 emit, &insn->Src[1] );
956 SVGA3dShaderDestToken temp = get_temp( emit );
957 int i;
958
959 /* For each enabled element, perform a RCP instruction. Note that
960 * RCP is scalar in SVGA3D:
961 */
962 for (i = 0; i < 4; i++) {
963 unsigned channel = 1 << i;
964 if (dst.mask & channel) {
965 /* RCP TMP.?, SRC1.???? */
966 if (!submit_op1( emit, inst_token( SVGA3DOP_RCP ),
967 writemask(temp, channel),
968 scalar(src1, i) ))
969 return FALSE;
970 }
971 }
972
973 /* Then multiply them out with a single mul:
974 *
975 * MUL DST, SRC0, TMP
976 */
977 if (!submit_op2( emit, inst_token( SVGA3DOP_MUL ), dst, src0,
978 src( temp ) ))
979 return FALSE;
980
981 return TRUE;
982 }
983
984 /* Translate the following TGSI DP2 instruction.
985 * DP2 DST, SRC1, SRC2
986 * To the following SVGA3D instruction sequence.
987 * MUL TMP, SRC1, SRC2
988 * ADD DST, TMP.xxxx, TMP.yyyy
989 */
990 static boolean emit_dp2(struct svga_shader_emitter *emit,
991 const struct tgsi_full_instruction *insn )
992 {
993 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
994 const struct src_register src0 = translate_src_register(
995 emit, &insn->Src[0] );
996 const struct src_register src1 = translate_src_register(
997 emit, &insn->Src[1] );
998 SVGA3dShaderDestToken temp = get_temp( emit );
999 struct src_register temp_src0, temp_src1;
1000
1001 /* MUL TMP, SRC1, SRC2 */
1002 if (!submit_op2( emit, inst_token( SVGA3DOP_MUL ), temp, src0, src1 ))
1003 return FALSE;
1004
1005 temp_src0 = scalar(src( temp ), TGSI_SWIZZLE_X);
1006 temp_src1 = scalar(src( temp ), TGSI_SWIZZLE_Y);
1007
1008 /* ADD DST, TMP.xxxx, TMP.yyyy */
1009 if (!submit_op2( emit, inst_token( SVGA3DOP_ADD ), dst,
1010 temp_src0, temp_src1 ))
1011 return FALSE;
1012
1013 return TRUE;
1014 }
1015
1016
1017 /* Translate the following TGSI DPH instruction.
1018 * DPH DST, SRC1, SRC2
1019 * To the following SVGA3D instruction sequence.
1020 * DP3 TMP, SRC1, SRC2
1021 * ADD DST, TMP, SRC2.wwww
1022 */
1023 static boolean emit_dph(struct svga_shader_emitter *emit,
1024 const struct tgsi_full_instruction *insn )
1025 {
1026 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
1027 const struct src_register src0 = translate_src_register(
1028 emit, &insn->Src[0] );
1029 struct src_register src1 = translate_src_register(
1030 emit, &insn->Src[1] );
1031 SVGA3dShaderDestToken temp = get_temp( emit );
1032
1033 /* DP3 TMP, SRC1, SRC2 */
1034 if (!submit_op2( emit, inst_token( SVGA3DOP_DP3 ), temp, src0, src1 ))
1035 return FALSE;
1036
1037 src1 = scalar(src1, TGSI_SWIZZLE_W);
1038
1039 /* ADD DST, TMP, SRC2.wwww */
1040 if (!submit_op2( emit, inst_token( SVGA3DOP_ADD ), dst,
1041 src( temp ), src1 ))
1042 return FALSE;
1043
1044 return TRUE;
1045 }
1046
1047 /* Translate the following TGSI DST instruction.
1048 * NRM DST, SRC
1049 * To the following SVGA3D instruction sequence.
1050 * DP3 TMP, SRC, SRC
1051 * RSQ TMP, TMP
1052 * MUL DST, SRC, TMP
1053 */
1054 static boolean emit_nrm(struct svga_shader_emitter *emit,
1055 const struct tgsi_full_instruction *insn )
1056 {
1057 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
1058 const struct src_register src0 = translate_src_register(
1059 emit, &insn->Src[0] );
1060 SVGA3dShaderDestToken temp = get_temp( emit );
1061
1062 /* DP3 TMP, SRC, SRC */
1063 if (!submit_op2( emit, inst_token( SVGA3DOP_DP3 ), temp, src0, src0 ))
1064 return FALSE;
1065
1066 /* RSQ TMP, TMP */
1067 if (!submit_op1( emit, inst_token( SVGA3DOP_RSQ ), temp, src( temp )))
1068 return FALSE;
1069
1070 /* MUL DST, SRC, TMP */
1071 if (!submit_op2( emit, inst_token( SVGA3DOP_MUL ), dst,
1072 src0, src( temp )))
1073 return FALSE;
1074
1075 return TRUE;
1076
1077 }
1078
1079 static boolean do_emit_sincos(struct svga_shader_emitter *emit,
1080 SVGA3dShaderDestToken dst,
1081 struct src_register src0)
1082 {
1083 src0 = scalar(src0, TGSI_SWIZZLE_X);
1084
1085 if (emit->use_sm30) {
1086 return submit_op1( emit, inst_token( SVGA3DOP_SINCOS ),
1087 dst, src0 );
1088 } else {
1089 struct src_register const1 = get_sincos_const( emit, 0 );
1090 struct src_register const2 = get_sincos_const( emit, 1 );
1091
1092 return submit_op3( emit, inst_token( SVGA3DOP_SINCOS ),
1093 dst, src0, const1, const2 );
1094 }
1095 }
1096
1097 static boolean emit_sincos(struct svga_shader_emitter *emit,
1098 const struct tgsi_full_instruction *insn)
1099 {
1100 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
1101 struct src_register src0 = translate_src_register(
1102 emit, &insn->Src[0] );
1103 SVGA3dShaderDestToken temp = get_temp( emit );
1104
1105 /* SCS TMP SRC */
1106 if (!do_emit_sincos(emit, writemask(temp, TGSI_WRITEMASK_XY), src0 ))
1107 return FALSE;
1108
1109 /* MOV DST TMP */
1110 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ), dst, src( temp ) ))
1111 return FALSE;
1112
1113 return TRUE;
1114 }
1115
1116 /*
1117 * SCS TMP SRC
1118 * MOV DST TMP.yyyy
1119 */
1120 static boolean emit_sin(struct svga_shader_emitter *emit,
1121 const struct tgsi_full_instruction *insn )
1122 {
1123 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
1124 struct src_register src0 = translate_src_register(
1125 emit, &insn->Src[0] );
1126 SVGA3dShaderDestToken temp = get_temp( emit );
1127
1128 /* SCS TMP SRC */
1129 if (!do_emit_sincos(emit, writemask(temp, TGSI_WRITEMASK_Y), src0))
1130 return FALSE;
1131
1132 src0 = scalar(src( temp ), TGSI_SWIZZLE_Y);
1133
1134 /* MOV DST TMP.yyyy */
1135 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ), dst, src0 ))
1136 return FALSE;
1137
1138 return TRUE;
1139 }
1140
1141 /*
1142 * SCS TMP SRC
1143 * MOV DST TMP.xxxx
1144 */
1145 static boolean emit_cos(struct svga_shader_emitter *emit,
1146 const struct tgsi_full_instruction *insn )
1147 {
1148 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
1149 struct src_register src0 = translate_src_register(
1150 emit, &insn->Src[0] );
1151 SVGA3dShaderDestToken temp = get_temp( emit );
1152
1153 /* SCS TMP SRC */
1154 if (!do_emit_sincos( emit, writemask(temp, TGSI_WRITEMASK_X), src0 ))
1155 return FALSE;
1156
1157 src0 = scalar(src( temp ), TGSI_SWIZZLE_X);
1158
1159 /* MOV DST TMP.xxxx */
1160 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ), dst, src0 ))
1161 return FALSE;
1162
1163 return TRUE;
1164 }
1165
1166 static boolean emit_ssg(struct svga_shader_emitter *emit,
1167 const struct tgsi_full_instruction *insn )
1168 {
1169 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
1170 struct src_register src0 = translate_src_register(
1171 emit, &insn->Src[0] );
1172 SVGA3dShaderDestToken temp0 = get_temp( emit );
1173 SVGA3dShaderDestToken temp1 = get_temp( emit );
1174 struct src_register zero, one;
1175
1176 if (emit->unit == PIPE_SHADER_VERTEX) {
1177 /* SGN DST, SRC0, TMP0, TMP1 */
1178 return submit_op3( emit, inst_token( SVGA3DOP_SGN ), dst, src0,
1179 src( temp0 ), src( temp1 ) );
1180 }
1181
1182 zero = get_zero_immediate( emit );
1183 one = scalar( zero, TGSI_SWIZZLE_W );
1184 zero = scalar( zero, TGSI_SWIZZLE_X );
1185
1186 /* CMP TMP0, SRC0, one, zero */
1187 if (!submit_op3( emit, inst_token( SVGA3DOP_CMP ),
1188 writemask( temp0, dst.mask ), src0, one, zero ))
1189 return FALSE;
1190
1191 /* CMP TMP1, negate(SRC0), negate(one), zero */
1192 if (!submit_op3( emit, inst_token( SVGA3DOP_CMP ),
1193 writemask( temp1, dst.mask ), negate( src0 ), negate( one ),
1194 zero ))
1195 return FALSE;
1196
1197 /* ADD DST, TMP0, TMP1 */
1198 return submit_op2( emit, inst_token( SVGA3DOP_ADD ), dst, src( temp0 ),
1199 src( temp1 ) );
1200 }
1201
1202 /*
1203 * ADD DST SRC0, negate(SRC0)
1204 */
1205 static boolean emit_sub(struct svga_shader_emitter *emit,
1206 const struct tgsi_full_instruction *insn)
1207 {
1208 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
1209 struct src_register src0 = translate_src_register(
1210 emit, &insn->Src[0] );
1211 struct src_register src1 = translate_src_register(
1212 emit, &insn->Src[1] );
1213
1214 src1 = negate(src1);
1215
1216 if (!submit_op2( emit, inst_token( SVGA3DOP_ADD ), dst,
1217 src0, src1 ))
1218 return FALSE;
1219
1220 return TRUE;
1221 }
1222
1223
1224 static boolean emit_kil(struct svga_shader_emitter *emit,
1225 const struct tgsi_full_instruction *insn )
1226 {
1227 SVGA3dShaderInstToken inst;
1228 const struct tgsi_full_src_register *reg = &insn->Src[0];
1229 struct src_register src0;
1230
1231 inst = inst_token( SVGA3DOP_TEXKILL );
1232 src0 = translate_src_register( emit, reg );
1233
1234 if (reg->Register.Absolute ||
1235 reg->Register.Negate ||
1236 reg->Register.Indirect ||
1237 reg->Register.SwizzleX != 0 ||
1238 reg->Register.SwizzleY != 1 ||
1239 reg->Register.SwizzleZ != 2 ||
1240 reg->Register.File != TGSI_FILE_TEMPORARY)
1241 {
1242 SVGA3dShaderDestToken temp = get_temp( emit );
1243
1244 submit_op1( emit, inst_token( SVGA3DOP_MOV ), temp, src0 );
1245 src0 = src( temp );
1246 }
1247
1248 return submit_op0( emit, inst, dst(src0) );
1249 }
1250
1251
1252 /* mesa state tracker always emits kilp as an unconditional
1253 * kil */
1254 static boolean emit_kilp(struct svga_shader_emitter *emit,
1255 const struct tgsi_full_instruction *insn )
1256 {
1257 SVGA3dShaderInstToken inst;
1258 SVGA3dShaderDestToken temp;
1259 struct src_register one = scalar( get_zero_immediate( emit ),
1260 TGSI_SWIZZLE_W );
1261
1262 inst = inst_token( SVGA3DOP_TEXKILL );
1263
1264 /* texkill doesn't allow negation on the operand so lets move
1265 * negation of {1} to a temp register */
1266 temp = get_temp( emit );
1267 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ), temp,
1268 negate( one ) ))
1269 return FALSE;
1270
1271 return submit_op0( emit, inst, temp );
1272 }
1273
1274 /* Implement conditionals by initializing destination reg to 'fail',
1275 * then set predicate reg with UFOP_SETP, then move 'pass' to dest
1276 * based on predicate reg.
1277 *
1278 * SETP src0, cmp, src1 -- do this first to avoid aliasing problems.
1279 * MOV dst, fail
1280 * MOV dst, pass, p0
1281 */
1282 static boolean
1283 emit_conditional(struct svga_shader_emitter *emit,
1284 unsigned compare_func,
1285 SVGA3dShaderDestToken dst,
1286 struct src_register src0,
1287 struct src_register src1,
1288 struct src_register pass,
1289 struct src_register fail)
1290 {
1291 SVGA3dShaderDestToken pred_reg = dst_register( SVGA3DREG_PREDICATE, 0 );
1292 SVGA3dShaderInstToken setp_token, mov_token;
1293 setp_token = inst_token( SVGA3DOP_SETP );
1294
1295 switch (compare_func) {
1296 case PIPE_FUNC_NEVER:
1297 return submit_op1( emit, inst_token( SVGA3DOP_MOV ),
1298 dst, fail );
1299 break;
1300 case PIPE_FUNC_LESS:
1301 setp_token.control = SVGA3DOPCOMP_LT;
1302 break;
1303 case PIPE_FUNC_EQUAL:
1304 setp_token.control = SVGA3DOPCOMP_EQ;
1305 break;
1306 case PIPE_FUNC_LEQUAL:
1307 setp_token.control = SVGA3DOPCOMP_LE;
1308 break;
1309 case PIPE_FUNC_GREATER:
1310 setp_token.control = SVGA3DOPCOMP_GT;
1311 break;
1312 case PIPE_FUNC_NOTEQUAL:
1313 setp_token.control = SVGA3DOPCOMPC_NE;
1314 break;
1315 case PIPE_FUNC_GEQUAL:
1316 setp_token.control = SVGA3DOPCOMP_GE;
1317 break;
1318 case PIPE_FUNC_ALWAYS:
1319 return submit_op1( emit, inst_token( SVGA3DOP_MOV ),
1320 dst, pass );
1321 break;
1322 }
1323
1324 /* SETP src0, COMPOP, src1 */
1325 if (!submit_op2( emit, setp_token, pred_reg,
1326 src0, src1 ))
1327 return FALSE;
1328
1329 mov_token = inst_token( SVGA3DOP_MOV );
1330
1331 /* MOV dst, fail */
1332 if (!submit_op1( emit, mov_token, dst,
1333 fail ))
1334 return FALSE;
1335
1336 /* MOV dst, pass (predicated)
1337 *
1338 * Note that the predicate reg (and possible modifiers) is passed
1339 * as the first source argument.
1340 */
1341 mov_token.predicated = 1;
1342 if (!submit_op2( emit, mov_token, dst,
1343 src( pred_reg ), pass ))
1344 return FALSE;
1345
1346 return TRUE;
1347 }
1348
1349
1350 static boolean
1351 emit_select(struct svga_shader_emitter *emit,
1352 unsigned compare_func,
1353 SVGA3dShaderDestToken dst,
1354 struct src_register src0,
1355 struct src_register src1 )
1356 {
1357 /* There are some SVGA instructions which implement some selects
1358 * directly, but they are only available in the vertex shader.
1359 */
1360 if (emit->unit == PIPE_SHADER_VERTEX) {
1361 switch (compare_func) {
1362 case PIPE_FUNC_GEQUAL:
1363 return submit_op2( emit, inst_token( SVGA3DOP_SGE ), dst, src0, src1 );
1364 case PIPE_FUNC_LEQUAL:
1365 return submit_op2( emit, inst_token( SVGA3DOP_SGE ), dst, src1, src0 );
1366 case PIPE_FUNC_GREATER:
1367 return submit_op2( emit, inst_token( SVGA3DOP_SLT ), dst, src1, src0 );
1368 case PIPE_FUNC_LESS:
1369 return submit_op2( emit, inst_token( SVGA3DOP_SLT ), dst, src0, src1 );
1370 default:
1371 break;
1372 }
1373 }
1374
1375
1376 /* Otherwise, need to use the setp approach:
1377 */
1378 {
1379 struct src_register one, zero;
1380 /* zero immediate is 0,0,0,1 */
1381 zero = get_zero_immediate( emit );
1382 one = scalar( zero, TGSI_SWIZZLE_W );
1383 zero = scalar( zero, TGSI_SWIZZLE_X );
1384
1385 return emit_conditional(
1386 emit,
1387 compare_func,
1388 dst,
1389 src0,
1390 src1,
1391 one, zero);
1392 }
1393 }
1394
1395
1396 static boolean emit_select_op(struct svga_shader_emitter *emit,
1397 unsigned compare,
1398 const struct tgsi_full_instruction *insn)
1399 {
1400 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
1401 struct src_register src0 = translate_src_register(
1402 emit, &insn->Src[0] );
1403 struct src_register src1 = translate_src_register(
1404 emit, &insn->Src[1] );
1405
1406 return emit_select( emit, compare, dst, src0, src1 );
1407 }
1408
1409
1410 /* Translate texture instructions to SVGA3D representation.
1411 */
1412 static boolean emit_tex2(struct svga_shader_emitter *emit,
1413 const struct tgsi_full_instruction *insn,
1414 SVGA3dShaderDestToken dst )
1415 {
1416 SVGA3dShaderInstToken inst;
1417 struct src_register texcoord;
1418 struct src_register sampler;
1419 SVGA3dShaderDestToken tmp;
1420
1421 inst.value = 0;
1422
1423 switch (insn->Instruction.Opcode) {
1424 case TGSI_OPCODE_TEX:
1425 inst.op = SVGA3DOP_TEX;
1426 break;
1427 case TGSI_OPCODE_TXP:
1428 inst.op = SVGA3DOP_TEX;
1429 inst.control = SVGA3DOPCONT_PROJECT;
1430 break;
1431 case TGSI_OPCODE_TXB:
1432 inst.op = SVGA3DOP_TEX;
1433 inst.control = SVGA3DOPCONT_BIAS;
1434 break;
1435 case TGSI_OPCODE_TXL:
1436 inst.op = SVGA3DOP_TEXLDL;
1437 break;
1438 default:
1439 assert(0);
1440 return FALSE;
1441 }
1442
1443 texcoord = translate_src_register( emit, &insn->Src[0] );
1444 sampler = translate_src_register( emit, &insn->Src[1] );
1445
1446 if (emit->key.fkey.tex[sampler.base.num].unnormalized ||
1447 emit->dynamic_branching_level > 0)
1448 tmp = get_temp( emit );
1449
1450 /* Can't do mipmapping inside dynamic branch constructs. Force LOD
1451 * zero in that case.
1452 */
1453 if (emit->dynamic_branching_level > 0 &&
1454 inst.op == SVGA3DOP_TEX &&
1455 SVGA3dShaderGetRegType(texcoord.base.value) == SVGA3DREG_TEMP) {
1456 struct src_register zero = get_zero_immediate( emit );
1457
1458 /* MOV tmp, texcoord */
1459 if (!submit_op1( emit,
1460 inst_token( SVGA3DOP_MOV ),
1461 tmp,
1462 texcoord ))
1463 return FALSE;
1464
1465 /* MOV tmp.w, zero */
1466 if (!submit_op1( emit,
1467 inst_token( SVGA3DOP_MOV ),
1468 writemask( tmp, TGSI_WRITEMASK_W ),
1469 scalar( zero, TGSI_SWIZZLE_X )))
1470 return FALSE;
1471
1472 texcoord = src( tmp );
1473 inst.op = SVGA3DOP_TEXLDL;
1474 }
1475
1476 /* Explicit normalization of texcoords:
1477 */
1478 if (emit->key.fkey.tex[sampler.base.num].unnormalized) {
1479 struct src_register wh = get_tex_dimensions( emit, sampler.base.num );
1480
1481 /* MUL tmp, SRC0, WH */
1482 if (!submit_op2( emit, inst_token( SVGA3DOP_MUL ),
1483 tmp, texcoord, wh ))
1484 return FALSE;
1485
1486 texcoord = src( tmp );
1487 }
1488
1489 return submit_op2( emit, inst, dst, texcoord, sampler );
1490 }
1491
1492
1493
1494
1495 /* Translate texture instructions to SVGA3D representation.
1496 */
1497 static boolean emit_tex4(struct svga_shader_emitter *emit,
1498 const struct tgsi_full_instruction *insn,
1499 SVGA3dShaderDestToken dst )
1500 {
1501 SVGA3dShaderInstToken inst;
1502 struct src_register texcoord;
1503 struct src_register ddx;
1504 struct src_register ddy;
1505 struct src_register sampler;
1506
1507 texcoord = translate_src_register( emit, &insn->Src[0] );
1508 ddx = translate_src_register( emit, &insn->Src[1] );
1509 ddy = translate_src_register( emit, &insn->Src[2] );
1510 sampler = translate_src_register( emit, &insn->Src[3] );
1511
1512 inst.value = 0;
1513
1514 switch (insn->Instruction.Opcode) {
1515 case TGSI_OPCODE_TXD:
1516 inst.op = SVGA3DOP_TEXLDD; /* 4 args! */
1517 break;
1518 default:
1519 assert(0);
1520 return FALSE;
1521 }
1522
1523 return submit_op4( emit, inst, dst, texcoord, sampler, ddx, ddy );
1524 }
1525
1526
1527 static boolean emit_tex(struct svga_shader_emitter *emit,
1528 const struct tgsi_full_instruction *insn )
1529 {
1530 SVGA3dShaderDestToken dst =
1531 translate_dst_register( emit, insn, 0 );
1532 struct src_register src0 =
1533 translate_src_register( emit, &insn->Src[0] );
1534 struct src_register src1 =
1535 translate_src_register( emit, &insn->Src[1] );
1536
1537 SVGA3dShaderDestToken tex_result;
1538
1539 /* check for shadow samplers */
1540 boolean compare = (emit->key.fkey.tex[src1.base.num].compare_mode ==
1541 PIPE_TEX_COMPARE_R_TO_TEXTURE);
1542
1543
1544 /* If doing compare processing, need to put this value into a
1545 * temporary so it can be used as a source later on.
1546 */
1547 if (compare ||
1548 (!emit->use_sm30 && dst.mask != TGSI_WRITEMASK_XYZW) ) {
1549 tex_result = get_temp( emit );
1550 }
1551 else {
1552 tex_result = dst;
1553 }
1554
1555 switch(insn->Instruction.Opcode) {
1556 case TGSI_OPCODE_TEX:
1557 case TGSI_OPCODE_TXB:
1558 case TGSI_OPCODE_TXP:
1559 case TGSI_OPCODE_TXL:
1560 if (!emit_tex2( emit, insn, tex_result ))
1561 return FALSE;
1562 break;
1563 case TGSI_OPCODE_TXD:
1564 if (!emit_tex4( emit, insn, tex_result ))
1565 return FALSE;
1566 break;
1567 default:
1568 assert(0);
1569 }
1570
1571
1572 if (compare) {
1573 if (dst.mask & TGSI_WRITEMASK_XYZ) {
1574 SVGA3dShaderDestToken src0_zdivw = get_temp( emit );
1575 struct src_register tex_src_x = scalar(src(tex_result), TGSI_SWIZZLE_Y);
1576
1577 /* Divide texcoord R by Q */
1578 if (!submit_op1( emit, inst_token( SVGA3DOP_RCP ),
1579 writemask(src0_zdivw, TGSI_WRITEMASK_X),
1580 scalar(src0, TGSI_SWIZZLE_W) ))
1581 return FALSE;
1582
1583 if (!submit_op2( emit, inst_token( SVGA3DOP_MUL ),
1584 writemask(src0_zdivw, TGSI_WRITEMASK_X),
1585 scalar(src0, TGSI_SWIZZLE_Z),
1586 scalar(src(src0_zdivw), TGSI_SWIZZLE_X) ))
1587 return FALSE;
1588
1589 if (!emit_select(
1590 emit,
1591 emit->key.fkey.tex[src1.base.num].compare_func,
1592 writemask( dst, TGSI_WRITEMASK_XYZ ),
1593 scalar(src(src0_zdivw), TGSI_SWIZZLE_X),
1594 tex_src_x))
1595 return FALSE;
1596 }
1597
1598 if (dst.mask & TGSI_WRITEMASK_W) {
1599 struct src_register one =
1600 scalar( get_zero_immediate( emit ), TGSI_SWIZZLE_W );
1601
1602 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ),
1603 writemask( dst, TGSI_WRITEMASK_W ),
1604 one ))
1605 return FALSE;
1606 }
1607
1608 return TRUE;
1609 }
1610 else if (!emit->use_sm30 && dst.mask != TGSI_WRITEMASK_XYZW)
1611 {
1612 if (!emit_op1( emit, inst_token( SVGA3DOP_MOV ), dst, src(tex_result) ))
1613 return FALSE;
1614 }
1615
1616 return TRUE;
1617 }
1618
1619 static boolean emit_bgnloop2( struct svga_shader_emitter *emit,
1620 const struct tgsi_full_instruction *insn )
1621 {
1622 SVGA3dShaderInstToken inst = inst_token( SVGA3DOP_LOOP );
1623 struct src_register loop_reg = src_register( SVGA3DREG_LOOP, 0 );
1624 struct src_register const_int = get_loop_const( emit );
1625
1626 emit->dynamic_branching_level++;
1627
1628 return (emit_instruction( emit, inst ) &&
1629 emit_src( emit, loop_reg ) &&
1630 emit_src( emit, const_int ) );
1631 }
1632
1633 static boolean emit_endloop2( struct svga_shader_emitter *emit,
1634 const struct tgsi_full_instruction *insn )
1635 {
1636 SVGA3dShaderInstToken inst = inst_token( SVGA3DOP_ENDLOOP );
1637
1638 emit->dynamic_branching_level--;
1639
1640 return emit_instruction( emit, inst );
1641 }
1642
1643 static boolean emit_brk( struct svga_shader_emitter *emit,
1644 const struct tgsi_full_instruction *insn )
1645 {
1646 SVGA3dShaderInstToken inst = inst_token( SVGA3DOP_BREAK );
1647 return emit_instruction( emit, inst );
1648 }
1649
1650 static boolean emit_scalar_op1( struct svga_shader_emitter *emit,
1651 unsigned opcode,
1652 const struct tgsi_full_instruction *insn )
1653 {
1654 SVGA3dShaderInstToken inst;
1655 SVGA3dShaderDestToken dst;
1656 struct src_register src;
1657
1658 inst = inst_token( opcode );
1659 dst = translate_dst_register( emit, insn, 0 );
1660 src = translate_src_register( emit, &insn->Src[0] );
1661 src = scalar( src, TGSI_SWIZZLE_X );
1662
1663 return submit_op1( emit, inst, dst, src );
1664 }
1665
1666
1667 static boolean emit_simple_instruction(struct svga_shader_emitter *emit,
1668 unsigned opcode,
1669 const struct tgsi_full_instruction *insn )
1670 {
1671 const struct tgsi_full_src_register *src = insn->Src;
1672 SVGA3dShaderInstToken inst;
1673 SVGA3dShaderDestToken dst;
1674
1675 inst = inst_token( opcode );
1676 dst = translate_dst_register( emit, insn, 0 );
1677
1678 switch (insn->Instruction.NumSrcRegs) {
1679 case 0:
1680 return submit_op0( emit, inst, dst );
1681 case 1:
1682 return submit_op1( emit, inst, dst,
1683 translate_src_register( emit, &src[0] ));
1684 case 2:
1685 return submit_op2( emit, inst, dst,
1686 translate_src_register( emit, &src[0] ),
1687 translate_src_register( emit, &src[1] ) );
1688 case 3:
1689 return submit_op3( emit, inst, dst,
1690 translate_src_register( emit, &src[0] ),
1691 translate_src_register( emit, &src[1] ),
1692 translate_src_register( emit, &src[2] ) );
1693 default:
1694 assert(0);
1695 return FALSE;
1696 }
1697 }
1698
1699
1700 static boolean emit_deriv(struct svga_shader_emitter *emit,
1701 const struct tgsi_full_instruction *insn )
1702 {
1703 if (emit->dynamic_branching_level > 0 &&
1704 insn->Src[0].Register.File == TGSI_FILE_TEMPORARY)
1705 {
1706 struct src_register zero = get_zero_immediate( emit );
1707 SVGA3dShaderDestToken dst =
1708 translate_dst_register( emit, insn, 0 );
1709
1710 /* Deriv opcodes not valid inside dynamic branching, workaround
1711 * by zeroing out the destination.
1712 */
1713 if (!submit_op1(emit,
1714 inst_token( SVGA3DOP_MOV ),
1715 dst,
1716 scalar(zero, TGSI_SWIZZLE_X)))
1717 return FALSE;
1718
1719 return TRUE;
1720 }
1721 else {
1722 unsigned opcode;
1723 const struct tgsi_full_src_register *reg = &insn->Src[0];
1724 SVGA3dShaderInstToken inst;
1725 SVGA3dShaderDestToken dst;
1726 struct src_register src0;
1727
1728 switch (insn->Instruction.Opcode) {
1729 case TGSI_OPCODE_DDX:
1730 opcode = SVGA3DOP_DSX;
1731 break;
1732 case TGSI_OPCODE_DDY:
1733 opcode = SVGA3DOP_DSY;
1734 break;
1735 default:
1736 return FALSE;
1737 }
1738
1739 inst = inst_token( opcode );
1740 dst = translate_dst_register( emit, insn, 0 );
1741 src0 = translate_src_register( emit, reg );
1742
1743 /* We cannot use negate or abs on source to dsx/dsy instruction.
1744 */
1745 if (reg->Register.Absolute ||
1746 reg->Register.Negate) {
1747 SVGA3dShaderDestToken temp = get_temp( emit );
1748
1749 if (!emit_repl( emit, temp, &src0 ))
1750 return FALSE;
1751 }
1752
1753 return submit_op1( emit, inst, dst, src0 );
1754 }
1755 }
1756
1757 static boolean emit_arl(struct svga_shader_emitter *emit,
1758 const struct tgsi_full_instruction *insn)
1759 {
1760 ++emit->current_arl;
1761 if (emit->unit == PIPE_SHADER_FRAGMENT) {
1762 /* MOVA not present in pixel shader instruction set.
1763 * Ignore this instruction altogether since it is
1764 * only used for loop counters -- and for that
1765 * we reference aL directly.
1766 */
1767 return TRUE;
1768 }
1769 if (svga_arl_needs_adjustment( emit )) {
1770 return emit_fake_arl( emit, insn );
1771 } else {
1772 /* no need to adjust, just emit straight arl */
1773 return emit_simple_instruction(emit, SVGA3DOP_MOVA, insn);
1774 }
1775 }
1776
1777 static boolean emit_pow(struct svga_shader_emitter *emit,
1778 const struct tgsi_full_instruction *insn)
1779 {
1780 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
1781 struct src_register src0 = translate_src_register(
1782 emit, &insn->Src[0] );
1783 struct src_register src1 = translate_src_register(
1784 emit, &insn->Src[1] );
1785 boolean need_tmp = FALSE;
1786
1787 /* POW can only output to a temporary */
1788 if (insn->Dst[0].Register.File != TGSI_FILE_TEMPORARY)
1789 need_tmp = TRUE;
1790
1791 /* POW src1 must not be the same register as dst */
1792 if (alias_src_dst( src1, dst ))
1793 need_tmp = TRUE;
1794
1795 /* it's a scalar op */
1796 src0 = scalar( src0, TGSI_SWIZZLE_X );
1797 src1 = scalar( src1, TGSI_SWIZZLE_X );
1798
1799 if (need_tmp) {
1800 SVGA3dShaderDestToken tmp = writemask(get_temp( emit ), TGSI_WRITEMASK_X );
1801
1802 if (!submit_op2(emit, inst_token( SVGA3DOP_POW ), tmp, src0, src1))
1803 return FALSE;
1804
1805 return submit_op1(emit, inst_token( SVGA3DOP_MOV ), dst, scalar(src(tmp), 0) );
1806 }
1807 else {
1808 return submit_op2(emit, inst_token( SVGA3DOP_POW ), dst, src0, src1);
1809 }
1810 }
1811
1812 static boolean emit_xpd(struct svga_shader_emitter *emit,
1813 const struct tgsi_full_instruction *insn)
1814 {
1815 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
1816 const struct src_register src0 = translate_src_register(
1817 emit, &insn->Src[0] );
1818 const struct src_register src1 = translate_src_register(
1819 emit, &insn->Src[1] );
1820 boolean need_dst_tmp = FALSE;
1821
1822 /* XPD can only output to a temporary */
1823 if (SVGA3dShaderGetRegType(dst.value) != SVGA3DREG_TEMP)
1824 need_dst_tmp = TRUE;
1825
1826 /* The dst reg must not be the same as src0 or src1*/
1827 if (alias_src_dst(src0, dst) ||
1828 alias_src_dst(src1, dst))
1829 need_dst_tmp = TRUE;
1830
1831 if (need_dst_tmp) {
1832 SVGA3dShaderDestToken tmp = get_temp( emit );
1833
1834 /* Obey DX9 restrictions on mask:
1835 */
1836 tmp.mask = dst.mask & TGSI_WRITEMASK_XYZ;
1837
1838 if (!submit_op2(emit, inst_token( SVGA3DOP_CRS ), tmp, src0, src1))
1839 return FALSE;
1840
1841 if (!submit_op1(emit, inst_token( SVGA3DOP_MOV ), dst, src( tmp )))
1842 return FALSE;
1843 }
1844 else {
1845 if (!submit_op2(emit, inst_token( SVGA3DOP_CRS ), dst, src0, src1))
1846 return FALSE;
1847 }
1848
1849 /* Need to emit 1.0 to dst.w?
1850 */
1851 if (dst.mask & TGSI_WRITEMASK_W) {
1852 struct src_register zero = get_zero_immediate( emit );
1853
1854 if (!submit_op1(emit,
1855 inst_token( SVGA3DOP_MOV ),
1856 writemask(dst, TGSI_WRITEMASK_W),
1857 zero))
1858 return FALSE;
1859 }
1860
1861 return TRUE;
1862 }
1863
1864
1865 static boolean emit_lrp(struct svga_shader_emitter *emit,
1866 const struct tgsi_full_instruction *insn)
1867 {
1868 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
1869 const struct src_register src0 = translate_src_register(
1870 emit, &insn->Src[0] );
1871 const struct src_register src1 = translate_src_register(
1872 emit, &insn->Src[1] );
1873 const struct src_register src2 = translate_src_register(
1874 emit, &insn->Src[2] );
1875
1876 return submit_lrp(emit, dst, src0, src1, src2);
1877 }
1878
1879
1880 static boolean emit_dst_insn(struct svga_shader_emitter *emit,
1881 const struct tgsi_full_instruction *insn )
1882 {
1883 if (emit->unit == PIPE_SHADER_VERTEX) {
1884 /* SVGA/DX9 has a DST instruction, but only for vertex shaders:
1885 */
1886 return emit_simple_instruction(emit, SVGA3DOP_DST, insn);
1887 }
1888 else {
1889
1890 /* result[0] = 1 * 1;
1891 * result[1] = a[1] * b[1];
1892 * result[2] = a[2] * 1;
1893 * result[3] = 1 * b[3];
1894 */
1895
1896 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
1897 SVGA3dShaderDestToken tmp;
1898 const struct src_register src0 = translate_src_register(
1899 emit, &insn->Src[0] );
1900 const struct src_register src1 = translate_src_register(
1901 emit, &insn->Src[1] );
1902 struct src_register zero = get_zero_immediate( emit );
1903 boolean need_tmp = FALSE;
1904
1905 if (SVGA3dShaderGetRegType(dst.value) != SVGA3DREG_TEMP ||
1906 alias_src_dst(src0, dst) ||
1907 alias_src_dst(src1, dst))
1908 need_tmp = TRUE;
1909
1910 if (need_tmp) {
1911 tmp = get_temp( emit );
1912 }
1913 else {
1914 tmp = dst;
1915 }
1916
1917 /* tmp.xw = 1.0
1918 */
1919 if (tmp.mask & TGSI_WRITEMASK_XW) {
1920 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ),
1921 writemask(tmp, TGSI_WRITEMASK_XW ),
1922 scalar( zero, 3 )))
1923 return FALSE;
1924 }
1925
1926 /* tmp.yz = src0
1927 */
1928 if (tmp.mask & TGSI_WRITEMASK_YZ) {
1929 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ),
1930 writemask(tmp, TGSI_WRITEMASK_YZ ),
1931 src0))
1932 return FALSE;
1933 }
1934
1935 /* tmp.yw = tmp * src1
1936 */
1937 if (tmp.mask & TGSI_WRITEMASK_YW) {
1938 if (!submit_op2( emit, inst_token( SVGA3DOP_MUL ),
1939 writemask(tmp, TGSI_WRITEMASK_YW ),
1940 src(tmp),
1941 src1))
1942 return FALSE;
1943 }
1944
1945 /* dst = tmp
1946 */
1947 if (need_tmp) {
1948 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ),
1949 dst,
1950 src(tmp)))
1951 return FALSE;
1952 }
1953 }
1954
1955 return TRUE;
1956 }
1957
1958
1959 static boolean emit_exp(struct svga_shader_emitter *emit,
1960 const struct tgsi_full_instruction *insn)
1961 {
1962 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
1963 struct src_register src0 =
1964 translate_src_register( emit, &insn->Src[0] );
1965 struct src_register zero = get_zero_immediate( emit );
1966 SVGA3dShaderDestToken fraction;
1967
1968 if (dst.mask & TGSI_WRITEMASK_Y)
1969 fraction = dst;
1970 else if (dst.mask & TGSI_WRITEMASK_X)
1971 fraction = get_temp( emit );
1972 else
1973 fraction.value = 0;
1974
1975 /* If y is being written, fill it with src0 - floor(src0).
1976 */
1977 if (dst.mask & TGSI_WRITEMASK_XY) {
1978 if (!submit_op1( emit, inst_token( SVGA3DOP_FRC ),
1979 writemask( fraction, TGSI_WRITEMASK_Y ),
1980 src0 ))
1981 return FALSE;
1982 }
1983
1984 /* If x is being written, fill it with 2 ^ floor(src0).
1985 */
1986 if (dst.mask & TGSI_WRITEMASK_X) {
1987 if (!submit_op2( emit, inst_token( SVGA3DOP_ADD ),
1988 writemask( dst, TGSI_WRITEMASK_X ),
1989 src0,
1990 scalar( negate( src( fraction ) ), TGSI_SWIZZLE_Y ) ) )
1991 return FALSE;
1992
1993 if (!submit_op1( emit, inst_token( SVGA3DOP_EXP ),
1994 writemask( dst, TGSI_WRITEMASK_X ),
1995 scalar( src( dst ), TGSI_SWIZZLE_X ) ) )
1996 return FALSE;
1997
1998 if (!(dst.mask & TGSI_WRITEMASK_Y))
1999 release_temp( emit, fraction );
2000 }
2001
2002 /* If z is being written, fill it with 2 ^ src0 (partial precision).
2003 */
2004 if (dst.mask & TGSI_WRITEMASK_Z) {
2005 if (!submit_op1( emit, inst_token( SVGA3DOP_EXPP ),
2006 writemask( dst, TGSI_WRITEMASK_Z ),
2007 src0 ) )
2008 return FALSE;
2009 }
2010
2011 /* If w is being written, fill it with one.
2012 */
2013 if (dst.mask & TGSI_WRITEMASK_W) {
2014 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ),
2015 writemask(dst, TGSI_WRITEMASK_W),
2016 scalar( zero, TGSI_SWIZZLE_W ) ))
2017 return FALSE;
2018 }
2019
2020 return TRUE;
2021 }
2022
2023 static boolean emit_lit(struct svga_shader_emitter *emit,
2024 const struct tgsi_full_instruction *insn )
2025 {
2026 if (emit->unit == PIPE_SHADER_VERTEX) {
2027 /* SVGA/DX9 has a LIT instruction, but only for vertex shaders:
2028 */
2029 return emit_simple_instruction(emit, SVGA3DOP_LIT, insn);
2030 }
2031 else {
2032
2033 /* D3D vs. GL semantics can be fairly easily accomodated by
2034 * variations on this sequence.
2035 *
2036 * GL:
2037 * tmp.y = src.x
2038 * tmp.z = pow(src.y,src.w)
2039 * p0 = src0.xxxx > 0
2040 * result = zero.wxxw
2041 * (p0) result.yz = tmp
2042 *
2043 * D3D:
2044 * tmp.y = src.x
2045 * tmp.z = pow(src.y,src.w)
2046 * p0 = src0.xxyy > 0
2047 * result = zero.wxxw
2048 * (p0) result.yz = tmp
2049 *
2050 * Will implement the GL version for now.
2051 */
2052
2053 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
2054 SVGA3dShaderDestToken tmp = get_temp( emit );
2055 const struct src_register src0 = translate_src_register(
2056 emit, &insn->Src[0] );
2057 struct src_register zero = get_zero_immediate( emit );
2058
2059 /* tmp = pow(src.y, src.w)
2060 */
2061 if (dst.mask & TGSI_WRITEMASK_Z) {
2062 if (!submit_op2(emit, inst_token( SVGA3DOP_POW ),
2063 tmp,
2064 scalar(src0, 1),
2065 scalar(src0, 3)))
2066 return FALSE;
2067 }
2068
2069 /* tmp.y = src.x
2070 */
2071 if (dst.mask & TGSI_WRITEMASK_Y) {
2072 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ),
2073 writemask(tmp, TGSI_WRITEMASK_Y ),
2074 scalar(src0, 0)))
2075 return FALSE;
2076 }
2077
2078 /* Can't quite do this with emit conditional due to the extra
2079 * writemask on the predicated mov:
2080 */
2081 {
2082 SVGA3dShaderDestToken pred_reg = dst_register( SVGA3DREG_PREDICATE, 0 );
2083 SVGA3dShaderInstToken setp_token, mov_token;
2084 struct src_register predsrc;
2085
2086 setp_token = inst_token( SVGA3DOP_SETP );
2087 mov_token = inst_token( SVGA3DOP_MOV );
2088
2089 setp_token.control = SVGA3DOPCOMP_GT;
2090
2091 /* D3D vs GL semantics:
2092 */
2093 if (0)
2094 predsrc = swizzle(src0, 0, 0, 1, 1); /* D3D */
2095 else
2096 predsrc = swizzle(src0, 0, 0, 0, 0); /* GL */
2097
2098 /* SETP src0.xxyy, GT, {0}.x */
2099 if (!submit_op2( emit, setp_token, pred_reg,
2100 predsrc,
2101 swizzle(zero, 0, 0, 0, 0) ))
2102 return FALSE;
2103
2104 /* MOV dst, fail */
2105 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ), dst,
2106 swizzle(zero, 3, 0, 0, 3 )))
2107 return FALSE;
2108
2109 /* MOV dst.yz, tmp (predicated)
2110 *
2111 * Note that the predicate reg (and possible modifiers) is passed
2112 * as the first source argument.
2113 */
2114 if (dst.mask & TGSI_WRITEMASK_YZ) {
2115 mov_token.predicated = 1;
2116 if (!submit_op2( emit, mov_token,
2117 writemask(dst, TGSI_WRITEMASK_YZ),
2118 src( pred_reg ), src( tmp ) ))
2119 return FALSE;
2120 }
2121 }
2122 }
2123
2124 return TRUE;
2125 }
2126
2127
2128
2129
2130 static boolean emit_ex2( struct svga_shader_emitter *emit,
2131 const struct tgsi_full_instruction *insn )
2132 {
2133 SVGA3dShaderInstToken inst;
2134 SVGA3dShaderDestToken dst;
2135 struct src_register src0;
2136
2137 inst = inst_token( SVGA3DOP_EXP );
2138 dst = translate_dst_register( emit, insn, 0 );
2139 src0 = translate_src_register( emit, &insn->Src[0] );
2140 src0 = scalar( src0, TGSI_SWIZZLE_X );
2141
2142 if (dst.mask != TGSI_WRITEMASK_XYZW) {
2143 SVGA3dShaderDestToken tmp = get_temp( emit );
2144
2145 if (!submit_op1( emit, inst, tmp, src0 ))
2146 return FALSE;
2147
2148 return submit_op1( emit, inst_token( SVGA3DOP_MOV ),
2149 dst,
2150 scalar( src( tmp ), TGSI_SWIZZLE_X ) );
2151 }
2152
2153 return submit_op1( emit, inst, dst, src0 );
2154 }
2155
2156
2157 static boolean emit_log(struct svga_shader_emitter *emit,
2158 const struct tgsi_full_instruction *insn)
2159 {
2160 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
2161 struct src_register src0 =
2162 translate_src_register( emit, &insn->Src[0] );
2163 struct src_register zero = get_zero_immediate( emit );
2164 SVGA3dShaderDestToken abs_tmp;
2165 struct src_register abs_src0;
2166 SVGA3dShaderDestToken log2_abs;
2167
2168 abs_tmp.value = 0;
2169
2170 if (dst.mask & TGSI_WRITEMASK_Z)
2171 log2_abs = dst;
2172 else if (dst.mask & TGSI_WRITEMASK_XY)
2173 log2_abs = get_temp( emit );
2174 else
2175 log2_abs.value = 0;
2176
2177 /* If z is being written, fill it with log2( abs( src0 ) ).
2178 */
2179 if (dst.mask & TGSI_WRITEMASK_XYZ) {
2180 if (!src0.base.srcMod || src0.base.srcMod == SVGA3DSRCMOD_ABS)
2181 abs_src0 = src0;
2182 else {
2183 abs_tmp = get_temp( emit );
2184
2185 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ),
2186 abs_tmp,
2187 src0 ) )
2188 return FALSE;
2189
2190 abs_src0 = src( abs_tmp );
2191 }
2192
2193 abs_src0 = absolute( scalar( abs_src0, TGSI_SWIZZLE_X ) );
2194
2195 if (!submit_op1( emit, inst_token( SVGA3DOP_LOG ),
2196 writemask( log2_abs, TGSI_WRITEMASK_Z ),
2197 abs_src0 ) )
2198 return FALSE;
2199 }
2200
2201 if (dst.mask & TGSI_WRITEMASK_XY) {
2202 SVGA3dShaderDestToken floor_log2;
2203
2204 if (dst.mask & TGSI_WRITEMASK_X)
2205 floor_log2 = dst;
2206 else
2207 floor_log2 = get_temp( emit );
2208
2209 /* If x is being written, fill it with floor( log2( abs( src0 ) ) ).
2210 */
2211 if (!submit_op1( emit, inst_token( SVGA3DOP_FRC ),
2212 writemask( floor_log2, TGSI_WRITEMASK_X ),
2213 scalar( src( log2_abs ), TGSI_SWIZZLE_Z ) ) )
2214 return FALSE;
2215
2216 if (!submit_op2( emit, inst_token( SVGA3DOP_ADD ),
2217 writemask( floor_log2, TGSI_WRITEMASK_X ),
2218 scalar( src( log2_abs ), TGSI_SWIZZLE_Z ),
2219 negate( src( floor_log2 ) ) ) )
2220 return FALSE;
2221
2222 /* If y is being written, fill it with
2223 * abs ( src0 ) / ( 2 ^ floor( log2( abs( src0 ) ) ) ).
2224 */
2225 if (dst.mask & TGSI_WRITEMASK_Y) {
2226 if (!submit_op1( emit, inst_token( SVGA3DOP_EXP ),
2227 writemask( dst, TGSI_WRITEMASK_Y ),
2228 negate( scalar( src( floor_log2 ),
2229 TGSI_SWIZZLE_X ) ) ) )
2230 return FALSE;
2231
2232 if (!submit_op2( emit, inst_token( SVGA3DOP_MUL ),
2233 writemask( dst, TGSI_WRITEMASK_Y ),
2234 src( dst ),
2235 abs_src0 ) )
2236 return FALSE;
2237 }
2238
2239 if (!(dst.mask & TGSI_WRITEMASK_X))
2240 release_temp( emit, floor_log2 );
2241
2242 if (!(dst.mask & TGSI_WRITEMASK_Z))
2243 release_temp( emit, log2_abs );
2244 }
2245
2246 if (dst.mask & TGSI_WRITEMASK_XYZ && src0.base.srcMod &&
2247 src0.base.srcMod != SVGA3DSRCMOD_ABS)
2248 release_temp( emit, abs_tmp );
2249
2250 /* If w is being written, fill it with one.
2251 */
2252 if (dst.mask & TGSI_WRITEMASK_W) {
2253 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ),
2254 writemask(dst, TGSI_WRITEMASK_W),
2255 scalar( zero, TGSI_SWIZZLE_W ) ))
2256 return FALSE;
2257 }
2258
2259 return TRUE;
2260 }
2261
2262
2263 static boolean emit_bgnsub( struct svga_shader_emitter *emit,
2264 unsigned position,
2265 const struct tgsi_full_instruction *insn )
2266 {
2267 unsigned i;
2268
2269 /* Note that we've finished the main function and are now emitting
2270 * subroutines. This affects how we terminate the generated
2271 * shader.
2272 */
2273 emit->in_main_func = FALSE;
2274
2275 for (i = 0; i < emit->nr_labels; i++) {
2276 if (emit->label[i] == position) {
2277 return (emit_instruction( emit, inst_token( SVGA3DOP_RET ) ) &&
2278 emit_instruction( emit, inst_token( SVGA3DOP_LABEL ) ) &&
2279 emit_src( emit, src_register( SVGA3DREG_LABEL, i )));
2280 }
2281 }
2282
2283 assert(0);
2284 return TRUE;
2285 }
2286
2287 static boolean emit_call( struct svga_shader_emitter *emit,
2288 const struct tgsi_full_instruction *insn )
2289 {
2290 unsigned position = insn->Label.Label;
2291 unsigned i;
2292
2293 for (i = 0; i < emit->nr_labels; i++) {
2294 if (emit->label[i] == position)
2295 break;
2296 }
2297
2298 if (emit->nr_labels == Elements(emit->label))
2299 return FALSE;
2300
2301 if (i == emit->nr_labels) {
2302 emit->label[i] = position;
2303 emit->nr_labels++;
2304 }
2305
2306 return (emit_instruction( emit, inst_token( SVGA3DOP_CALL ) ) &&
2307 emit_src( emit, src_register( SVGA3DREG_LABEL, i )));
2308 }
2309
2310
2311 static boolean emit_end( struct svga_shader_emitter *emit )
2312 {
2313 if (emit->unit == PIPE_SHADER_VERTEX) {
2314 return emit_vs_postamble( emit );
2315 }
2316 else {
2317 return emit_ps_postamble( emit );
2318 }
2319 }
2320
2321
2322
2323 static boolean svga_emit_instruction( struct svga_shader_emitter *emit,
2324 unsigned position,
2325 const struct tgsi_full_instruction *insn )
2326 {
2327 switch (insn->Instruction.Opcode) {
2328
2329 case TGSI_OPCODE_ARL:
2330 return emit_arl( emit, insn );
2331
2332 case TGSI_OPCODE_TEX:
2333 case TGSI_OPCODE_TXB:
2334 case TGSI_OPCODE_TXP:
2335 case TGSI_OPCODE_TXL:
2336 case TGSI_OPCODE_TXD:
2337 return emit_tex( emit, insn );
2338
2339 case TGSI_OPCODE_DDX:
2340 case TGSI_OPCODE_DDY:
2341 return emit_deriv( emit, insn );
2342
2343 case TGSI_OPCODE_BGNSUB:
2344 return emit_bgnsub( emit, position, insn );
2345
2346 case TGSI_OPCODE_ENDSUB:
2347 return TRUE;
2348
2349 case TGSI_OPCODE_CAL:
2350 return emit_call( emit, insn );
2351
2352 case TGSI_OPCODE_FLR:
2353 case TGSI_OPCODE_TRUNC: /* should be TRUNC, not FLR */
2354 return emit_floor( emit, insn );
2355
2356 case TGSI_OPCODE_CMP:
2357 return emit_cmp( emit, insn );
2358
2359 case TGSI_OPCODE_DIV:
2360 return emit_div( emit, insn );
2361
2362 case TGSI_OPCODE_DP2:
2363 return emit_dp2( emit, insn );
2364
2365 case TGSI_OPCODE_DPH:
2366 return emit_dph( emit, insn );
2367
2368 case TGSI_OPCODE_NRM:
2369 return emit_nrm( emit, insn );
2370
2371 case TGSI_OPCODE_COS:
2372 return emit_cos( emit, insn );
2373
2374 case TGSI_OPCODE_SIN:
2375 return emit_sin( emit, insn );
2376
2377 case TGSI_OPCODE_SCS:
2378 return emit_sincos( emit, insn );
2379
2380 case TGSI_OPCODE_END:
2381 /* TGSI always finishes the main func with an END */
2382 return emit_end( emit );
2383
2384 case TGSI_OPCODE_KIL:
2385 return emit_kil( emit, insn );
2386
2387 /* Selection opcodes. The underlying language is fairly
2388 * non-orthogonal about these.
2389 */
2390 case TGSI_OPCODE_SEQ:
2391 return emit_select_op( emit, PIPE_FUNC_EQUAL, insn );
2392
2393 case TGSI_OPCODE_SNE:
2394 return emit_select_op( emit, PIPE_FUNC_NOTEQUAL, insn );
2395
2396 case TGSI_OPCODE_SGT:
2397 return emit_select_op( emit, PIPE_FUNC_GREATER, insn );
2398
2399 case TGSI_OPCODE_SGE:
2400 return emit_select_op( emit, PIPE_FUNC_GEQUAL, insn );
2401
2402 case TGSI_OPCODE_SLT:
2403 return emit_select_op( emit, PIPE_FUNC_LESS, insn );
2404
2405 case TGSI_OPCODE_SLE:
2406 return emit_select_op( emit, PIPE_FUNC_LEQUAL, insn );
2407
2408 case TGSI_OPCODE_SUB:
2409 return emit_sub( emit, insn );
2410
2411 case TGSI_OPCODE_POW:
2412 return emit_pow( emit, insn );
2413
2414 case TGSI_OPCODE_EX2:
2415 return emit_ex2( emit, insn );
2416
2417 case TGSI_OPCODE_EXP:
2418 return emit_exp( emit, insn );
2419
2420 case TGSI_OPCODE_LOG:
2421 return emit_log( emit, insn );
2422
2423 case TGSI_OPCODE_LG2:
2424 return emit_scalar_op1( emit, SVGA3DOP_LOG, insn );
2425
2426 case TGSI_OPCODE_RSQ:
2427 return emit_scalar_op1( emit, SVGA3DOP_RSQ, insn );
2428
2429 case TGSI_OPCODE_RCP:
2430 return emit_scalar_op1( emit, SVGA3DOP_RCP, insn );
2431
2432 case TGSI_OPCODE_CONT:
2433 case TGSI_OPCODE_RET:
2434 /* This is a noop -- we tell mesa that we can't support RET
2435 * within a function (early return), so this will always be
2436 * followed by an ENDSUB.
2437 */
2438 return TRUE;
2439
2440 /* These aren't actually used by any of the frontends we care
2441 * about:
2442 */
2443 case TGSI_OPCODE_CLAMP:
2444 case TGSI_OPCODE_ROUND:
2445 case TGSI_OPCODE_AND:
2446 case TGSI_OPCODE_OR:
2447 case TGSI_OPCODE_I2F:
2448 case TGSI_OPCODE_NOT:
2449 case TGSI_OPCODE_SHL:
2450 case TGSI_OPCODE_ISHR:
2451 case TGSI_OPCODE_XOR:
2452 return FALSE;
2453
2454 case TGSI_OPCODE_IF:
2455 return emit_if( emit, insn );
2456 case TGSI_OPCODE_ELSE:
2457 return emit_else( emit, insn );
2458 case TGSI_OPCODE_ENDIF:
2459 return emit_endif( emit, insn );
2460
2461 case TGSI_OPCODE_BGNLOOP:
2462 return emit_bgnloop2( emit, insn );
2463 case TGSI_OPCODE_ENDLOOP:
2464 return emit_endloop2( emit, insn );
2465 case TGSI_OPCODE_BRK:
2466 return emit_brk( emit, insn );
2467
2468 case TGSI_OPCODE_XPD:
2469 return emit_xpd( emit, insn );
2470
2471 case TGSI_OPCODE_KILP:
2472 return emit_kilp( emit, insn );
2473
2474 case TGSI_OPCODE_DST:
2475 return emit_dst_insn( emit, insn );
2476
2477 case TGSI_OPCODE_LIT:
2478 return emit_lit( emit, insn );
2479
2480 case TGSI_OPCODE_LRP:
2481 return emit_lrp( emit, insn );
2482
2483 case TGSI_OPCODE_SSG:
2484 return emit_ssg( emit, insn );
2485
2486 default: {
2487 unsigned opcode = translate_opcode(insn->Instruction.Opcode);
2488
2489 if (opcode == SVGA3DOP_LAST_INST)
2490 return FALSE;
2491
2492 if (!emit_simple_instruction( emit, opcode, insn ))
2493 return FALSE;
2494 }
2495 }
2496
2497 return TRUE;
2498 }
2499
2500
2501 static boolean svga_emit_immediate( struct svga_shader_emitter *emit,
2502 struct tgsi_full_immediate *imm)
2503 {
2504 static const float id[4] = {0,0,0,1};
2505 float value[4];
2506 unsigned i;
2507
2508 assert(1 <= imm->Immediate.NrTokens && imm->Immediate.NrTokens <= 5);
2509 for (i = 0; i < imm->Immediate.NrTokens - 1; i++)
2510 value[i] = imm->u[i].Float;
2511
2512 for ( ; i < 4; i++ )
2513 value[i] = id[i];
2514
2515 return emit_def_const( emit, SVGA3D_CONST_TYPE_FLOAT,
2516 emit->imm_start + emit->internal_imm_count++,
2517 value[0], value[1], value[2], value[3]);
2518 }
2519
2520 static boolean make_immediate( struct svga_shader_emitter *emit,
2521 float a,
2522 float b,
2523 float c,
2524 float d,
2525 struct src_register *out )
2526 {
2527 unsigned idx = emit->nr_hw_float_const++;
2528
2529 if (!emit_def_const( emit, SVGA3D_CONST_TYPE_FLOAT,
2530 idx, a, b, c, d ))
2531 return FALSE;
2532
2533 *out = src_register( SVGA3DREG_CONST, idx );
2534
2535 return TRUE;
2536 }
2537
2538 static boolean emit_vs_preamble( struct svga_shader_emitter *emit )
2539 {
2540 if (!emit->key.vkey.need_prescale) {
2541 if (!make_immediate( emit, 0, 0, .5, .5,
2542 &emit->imm_0055))
2543 return FALSE;
2544 }
2545
2546 return TRUE;
2547 }
2548
2549 static boolean emit_ps_preamble( struct svga_shader_emitter *emit )
2550 {
2551 unsigned i;
2552
2553 /* For SM20, need to initialize the temporaries we're using to hold
2554 * color outputs to some value. Shaders which don't set all of
2555 * these values are likely to be rejected by the DX9 runtime.
2556 */
2557 if (!emit->use_sm30) {
2558 struct src_register zero = get_zero_immediate( emit );
2559 for (i = 0; i < PIPE_MAX_COLOR_BUFS; i++) {
2560 if (SVGA3dShaderGetRegType(emit->true_col[i].value) != 0) {
2561
2562 if (!submit_op1( emit,
2563 inst_token(SVGA3DOP_MOV),
2564 emit->temp_col[i],
2565 zero ))
2566 return FALSE;
2567 }
2568 }
2569 } else if (emit->ps_reads_pos && emit->info.reads_z) {
2570 /*
2571 * Assemble the position from various bits of inputs. Depth and W are
2572 * passed in a texcoord this is due to D3D's vPos not hold Z or W.
2573 * Also fixup the perspective interpolation.
2574 *
2575 * temp_pos.xy = vPos.xy
2576 * temp_pos.w = rcp(texcoord1.w);
2577 * temp_pos.z = texcoord1.z * temp_pos.w;
2578 */
2579 if (!submit_op1( emit,
2580 inst_token(SVGA3DOP_MOV),
2581 writemask( emit->ps_temp_pos, TGSI_WRITEMASK_XY ),
2582 emit->ps_true_pos ))
2583 return FALSE;
2584
2585 if (!submit_op1( emit,
2586 inst_token(SVGA3DOP_RCP),
2587 writemask( emit->ps_temp_pos, TGSI_WRITEMASK_W ),
2588 scalar( emit->ps_depth_pos, TGSI_SWIZZLE_W ) ))
2589 return FALSE;
2590
2591 if (!submit_op2( emit,
2592 inst_token(SVGA3DOP_MUL),
2593 writemask( emit->ps_temp_pos, TGSI_WRITEMASK_Z ),
2594 scalar( emit->ps_depth_pos, TGSI_SWIZZLE_Z ),
2595 scalar( src(emit->ps_temp_pos), TGSI_SWIZZLE_W ) ))
2596 return FALSE;
2597 }
2598
2599 return TRUE;
2600 }
2601
2602 static boolean emit_ps_postamble( struct svga_shader_emitter *emit )
2603 {
2604 unsigned i;
2605
2606 /* PS oDepth is incredibly fragile and it's very hard to catch the
2607 * types of usage that break it during shader emit. Easier just to
2608 * redirect the main program to a temporary and then only touch
2609 * oDepth with a hand-crafted MOV below.
2610 */
2611 if (SVGA3dShaderGetRegType(emit->true_pos.value) != 0) {
2612
2613 if (!submit_op1( emit,
2614 inst_token(SVGA3DOP_MOV),
2615 emit->true_pos,
2616 scalar(src(emit->temp_pos), TGSI_SWIZZLE_Z) ))
2617 return FALSE;
2618 }
2619
2620 /* Similarly for SM20 color outputs... Luckily SM30 isn't so
2621 * fragile.
2622 */
2623 for (i = 0; i < PIPE_MAX_COLOR_BUFS; i++) {
2624 if (SVGA3dShaderGetRegType(emit->true_col[i].value) != 0) {
2625
2626 /* Potentially override output colors with white for XOR
2627 * logicop workaround.
2628 */
2629 if (emit->unit == PIPE_SHADER_FRAGMENT &&
2630 emit->key.fkey.white_fragments) {
2631
2632 struct src_register one = scalar( get_zero_immediate( emit ),
2633 TGSI_SWIZZLE_W );
2634
2635 if (!submit_op1( emit,
2636 inst_token(SVGA3DOP_MOV),
2637 emit->true_col[i],
2638 one ))
2639 return FALSE;
2640 }
2641 else {
2642 if (!submit_op1( emit,
2643 inst_token(SVGA3DOP_MOV),
2644 emit->true_col[i],
2645 src(emit->temp_col[i]) ))
2646 return FALSE;
2647 }
2648 }
2649 }
2650
2651 return TRUE;
2652 }
2653
2654 static boolean emit_vs_postamble( struct svga_shader_emitter *emit )
2655 {
2656 /* PSIZ output is incredibly fragile and it's very hard to catch
2657 * the types of usage that break it during shader emit. Easier
2658 * just to redirect the main program to a temporary and then only
2659 * touch PSIZ with a hand-crafted MOV below.
2660 */
2661 if (SVGA3dShaderGetRegType(emit->true_psiz.value) != 0) {
2662
2663 if (!submit_op1( emit,
2664 inst_token(SVGA3DOP_MOV),
2665 emit->true_psiz,
2666 scalar(src(emit->temp_psiz), TGSI_SWIZZLE_X) ))
2667 return FALSE;
2668 }
2669
2670 /* Need to perform various manipulations on vertex position to cope
2671 * with the different GL and D3D clip spaces.
2672 */
2673 if (emit->key.vkey.need_prescale) {
2674 SVGA3dShaderDestToken temp_pos = emit->temp_pos;
2675 SVGA3dShaderDestToken depth = emit->depth_pos;
2676 SVGA3dShaderDestToken pos = emit->true_pos;
2677 unsigned offset = emit->info.file_max[TGSI_FILE_CONSTANT] + 1;
2678 struct src_register prescale_scale = src_register( SVGA3DREG_CONST,
2679 offset + 0 );
2680 struct src_register prescale_trans = src_register( SVGA3DREG_CONST,
2681 offset + 1 );
2682
2683 if (!submit_op1( emit,
2684 inst_token(SVGA3DOP_MOV),
2685 writemask(depth, TGSI_WRITEMASK_W),
2686 scalar(src(temp_pos), TGSI_SWIZZLE_W) ))
2687 return FALSE;
2688
2689 /* MUL temp_pos.xyz, temp_pos, prescale.scale
2690 * MAD result.position, temp_pos.wwww, prescale.trans, temp_pos
2691 * --> Note that prescale.trans.w == 0
2692 */
2693 if (!submit_op2( emit,
2694 inst_token(SVGA3DOP_MUL),
2695 writemask(temp_pos, TGSI_WRITEMASK_XYZ),
2696 src(temp_pos),
2697 prescale_scale ))
2698 return FALSE;
2699
2700 if (!submit_op3( emit,
2701 inst_token(SVGA3DOP_MAD),
2702 pos,
2703 swizzle(src(temp_pos), 3, 3, 3, 3),
2704 prescale_trans,
2705 src(temp_pos)))
2706 return FALSE;
2707
2708 /* Also write to depth value */
2709 if (!submit_op3( emit,
2710 inst_token(SVGA3DOP_MAD),
2711 writemask(depth, TGSI_WRITEMASK_Z),
2712 swizzle(src(temp_pos), 3, 3, 3, 3),
2713 prescale_trans,
2714 src(temp_pos) ))
2715 return FALSE;
2716 }
2717 else {
2718 SVGA3dShaderDestToken temp_pos = emit->temp_pos;
2719 SVGA3dShaderDestToken depth = emit->depth_pos;
2720 SVGA3dShaderDestToken pos = emit->true_pos;
2721 struct src_register imm_0055 = emit->imm_0055;
2722
2723 /* Adjust GL clipping coordinate space to hardware (D3D-style):
2724 *
2725 * DP4 temp_pos.z, {0,0,.5,.5}, temp_pos
2726 * MOV result.position, temp_pos
2727 */
2728 if (!submit_op2( emit,
2729 inst_token(SVGA3DOP_DP4),
2730 writemask(temp_pos, TGSI_WRITEMASK_Z),
2731 imm_0055,
2732 src(temp_pos) ))
2733 return FALSE;
2734
2735 if (!submit_op1( emit,
2736 inst_token(SVGA3DOP_MOV),
2737 pos,
2738 src(temp_pos) ))
2739 return FALSE;
2740
2741 /* Move the manipulated depth into the extra texcoord reg */
2742 if (!submit_op1( emit,
2743 inst_token(SVGA3DOP_MOV),
2744 writemask(depth, TGSI_WRITEMASK_ZW),
2745 src(temp_pos) ))
2746 return FALSE;
2747 }
2748
2749 return TRUE;
2750 }
2751
2752 /*
2753 0: IF VFACE :4
2754 1: COLOR = FrontColor;
2755 2: ELSE
2756 3: COLOR = BackColor;
2757 4: ENDIF
2758 */
2759 static boolean emit_light_twoside( struct svga_shader_emitter *emit )
2760 {
2761 struct src_register vface, zero;
2762 struct src_register front[2];
2763 struct src_register back[2];
2764 SVGA3dShaderDestToken color[2];
2765 int count = emit->internal_color_count;
2766 int i;
2767 SVGA3dShaderInstToken if_token;
2768
2769 if (count == 0)
2770 return TRUE;
2771
2772 vface = get_vface( emit );
2773 zero = get_zero_immediate( emit );
2774
2775 /* Can't use get_temp() to allocate the color reg as such
2776 * temporaries will be reclaimed after each instruction by the call
2777 * to reset_temp_regs().
2778 */
2779 for (i = 0; i < count; i++) {
2780 color[i] = dst_register( SVGA3DREG_TEMP,
2781 emit->nr_hw_temp++ );
2782
2783 front[i] = emit->input_map[emit->internal_color_idx[i]];
2784
2785 /* Back is always the next input:
2786 */
2787 back[i] = front[i];
2788 back[i].base.num = front[i].base.num + 1;
2789
2790 /* Reassign the input_map to the actual front-face color:
2791 */
2792 emit->input_map[emit->internal_color_idx[i]] = src(color[i]);
2793 }
2794
2795 if_token = inst_token( SVGA3DOP_IFC );
2796
2797 if (emit->key.fkey.front_ccw)
2798 if_token.control = SVGA3DOPCOMP_LT;
2799 else
2800 if_token.control = SVGA3DOPCOMP_GT;
2801
2802 zero = scalar(zero, TGSI_SWIZZLE_X);
2803
2804 if (!(emit_instruction( emit, if_token ) &&
2805 emit_src( emit, vface ) &&
2806 emit_src( emit, zero ) ))
2807 return FALSE;
2808
2809 for (i = 0; i < count; i++) {
2810 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ), color[i], front[i] ))
2811 return FALSE;
2812 }
2813
2814 if (!(emit_instruction( emit, inst_token( SVGA3DOP_ELSE))))
2815 return FALSE;
2816
2817 for (i = 0; i < count; i++) {
2818 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ), color[i], back[i] ))
2819 return FALSE;
2820 }
2821
2822 if (!emit_instruction( emit, inst_token( SVGA3DOP_ENDIF ) ))
2823 return FALSE;
2824
2825 return TRUE;
2826 }
2827
2828 /*
2829 0: SETP_GT TEMP, VFACE, 0
2830 where TEMP is a fake frontface register
2831 */
2832 static boolean emit_frontface( struct svga_shader_emitter *emit )
2833 {
2834 struct src_register vface, zero;
2835 SVGA3dShaderDestToken temp;
2836 struct src_register pass, fail;
2837
2838 vface = get_vface( emit );
2839 zero = get_zero_immediate( emit );
2840
2841 /* Can't use get_temp() to allocate the fake frontface reg as such
2842 * temporaries will be reclaimed after each instruction by the call
2843 * to reset_temp_regs().
2844 */
2845 temp = dst_register( SVGA3DREG_TEMP,
2846 emit->nr_hw_temp++ );
2847
2848 if (emit->key.fkey.front_ccw) {
2849 pass = scalar( zero, TGSI_SWIZZLE_X );
2850 fail = scalar( zero, TGSI_SWIZZLE_W );
2851 } else {
2852 pass = scalar( zero, TGSI_SWIZZLE_W );
2853 fail = scalar( zero, TGSI_SWIZZLE_X );
2854 }
2855
2856 if (!emit_conditional(emit, PIPE_FUNC_GREATER,
2857 temp, vface, scalar( zero, TGSI_SWIZZLE_X ),
2858 pass, fail))
2859 return FALSE;
2860
2861 /* Reassign the input_map to the actual front-face color:
2862 */
2863 emit->input_map[emit->internal_frontface_idx] = src(temp);
2864
2865 return TRUE;
2866 }
2867
2868
2869 /**
2870 * Emit code to invert the T component of the incoming texture coordinate.
2871 * This is used for drawing point sprites when
2872 * pipe_rasterizer_state::sprite_coord_mode == PIPE_SPRITE_COORD_LOWER_LEFT.
2873 */
2874 static boolean emit_inverted_texcoords( struct svga_shader_emitter *emit )
2875 {
2876 struct src_register zero = get_zero_immediate(emit);
2877 struct src_register pos_neg_one = get_pos_neg_one_immediate( emit );
2878 unsigned inverted_texcoords = emit->inverted_texcoords;
2879
2880 while (inverted_texcoords) {
2881 const unsigned unit = ffs(inverted_texcoords) - 1;
2882
2883 assert(emit->inverted_texcoords & (1 << unit));
2884
2885 assert(unit < Elements(emit->ps_true_texcoord));
2886
2887 assert(unit < Elements(emit->ps_inverted_texcoord_input));
2888
2889 assert(emit->ps_inverted_texcoord_input[unit]
2890 < Elements(emit->input_map));
2891
2892 /* inverted = coord * (1, -1, 1, 1) + (0, 1, 0, 0) */
2893 if (!submit_op3(emit,
2894 inst_token(SVGA3DOP_MAD),
2895 dst(emit->ps_inverted_texcoord[unit]),
2896 emit->ps_true_texcoord[unit],
2897 swizzle(pos_neg_one, 0, 3, 0, 0), /* (1, -1, 1, 1) */
2898 swizzle(zero, 0, 3, 0, 0))) /* (0, 1, 0, 0) */
2899 return FALSE;
2900
2901 /* Reassign the input_map entry to the new texcoord register */
2902 emit->input_map[emit->ps_inverted_texcoord_input[unit]] =
2903 emit->ps_inverted_texcoord[unit];
2904
2905 inverted_texcoords &= ~(1 << unit);
2906 }
2907
2908 return TRUE;
2909 }
2910
2911
2912 static INLINE boolean
2913 needs_to_create_zero( struct svga_shader_emitter *emit )
2914 {
2915 int i;
2916
2917 if (emit->unit == PIPE_SHADER_FRAGMENT) {
2918 if (!emit->use_sm30)
2919 return TRUE;
2920
2921 if (emit->key.fkey.light_twoside)
2922 return TRUE;
2923
2924 if (emit->key.fkey.white_fragments)
2925 return TRUE;
2926
2927 if (emit->emit_frontface)
2928 return TRUE;
2929
2930 if (emit->info.opcode_count[TGSI_OPCODE_DST] >= 1 ||
2931 emit->info.opcode_count[TGSI_OPCODE_SSG] >= 1 ||
2932 emit->info.opcode_count[TGSI_OPCODE_LIT] >= 1)
2933 return TRUE;
2934
2935 if (emit->inverted_texcoords)
2936 return TRUE;
2937 }
2938
2939 if (emit->unit == PIPE_SHADER_VERTEX) {
2940 if (emit->info.opcode_count[TGSI_OPCODE_CMP] >= 1)
2941 return TRUE;
2942 }
2943
2944 if (emit->info.opcode_count[TGSI_OPCODE_IF] >= 1 ||
2945 emit->info.opcode_count[TGSI_OPCODE_BGNLOOP] >= 1 ||
2946 emit->info.opcode_count[TGSI_OPCODE_DDX] >= 1 ||
2947 emit->info.opcode_count[TGSI_OPCODE_DDY] >= 1 ||
2948 emit->info.opcode_count[TGSI_OPCODE_SGE] >= 1 ||
2949 emit->info.opcode_count[TGSI_OPCODE_SGT] >= 1 ||
2950 emit->info.opcode_count[TGSI_OPCODE_SLE] >= 1 ||
2951 emit->info.opcode_count[TGSI_OPCODE_SLT] >= 1 ||
2952 emit->info.opcode_count[TGSI_OPCODE_SNE] >= 1 ||
2953 emit->info.opcode_count[TGSI_OPCODE_SEQ] >= 1 ||
2954 emit->info.opcode_count[TGSI_OPCODE_EXP] >= 1 ||
2955 emit->info.opcode_count[TGSI_OPCODE_LOG] >= 1 ||
2956 emit->info.opcode_count[TGSI_OPCODE_XPD] >= 1 ||
2957 emit->info.opcode_count[TGSI_OPCODE_KILP] >= 1)
2958 return TRUE;
2959
2960 for (i = 0; i < emit->key.fkey.num_textures; i++) {
2961 if (emit->key.fkey.tex[i].compare_mode == PIPE_TEX_COMPARE_R_TO_TEXTURE)
2962 return TRUE;
2963 }
2964
2965 return FALSE;
2966 }
2967
2968 static INLINE boolean
2969 needs_to_create_loop_const( struct svga_shader_emitter *emit )
2970 {
2971 return (emit->info.opcode_count[TGSI_OPCODE_BGNLOOP] >= 1);
2972 }
2973
2974 static INLINE boolean
2975 needs_to_create_sincos_consts( struct svga_shader_emitter *emit )
2976 {
2977 return !emit->use_sm30 && (emit->info.opcode_count[TGSI_OPCODE_SIN] >= 1 ||
2978 emit->info.opcode_count[TGSI_OPCODE_COS] >= 1 ||
2979 emit->info.opcode_count[TGSI_OPCODE_SCS] >= 1);
2980 }
2981
2982 static INLINE boolean
2983 needs_to_create_arl_consts( struct svga_shader_emitter *emit )
2984 {
2985 return (emit->num_arl_consts > 0);
2986 }
2987
2988 static INLINE boolean
2989 pre_parse_add_indirect( struct svga_shader_emitter *emit,
2990 int num, int current_arl)
2991 {
2992 int i;
2993 assert(num < 0);
2994
2995 for (i = 0; i < emit->num_arl_consts; ++i) {
2996 if (emit->arl_consts[i].arl_num == current_arl)
2997 break;
2998 }
2999 /* new entry */
3000 if (emit->num_arl_consts == i) {
3001 ++emit->num_arl_consts;
3002 }
3003 emit->arl_consts[i].number = (emit->arl_consts[i].number > num) ?
3004 num :
3005 emit->arl_consts[i].number;
3006 emit->arl_consts[i].arl_num = current_arl;
3007 return TRUE;
3008 }
3009
3010 static boolean
3011 pre_parse_instruction( struct svga_shader_emitter *emit,
3012 const struct tgsi_full_instruction *insn,
3013 int current_arl)
3014 {
3015 if (insn->Src[0].Register.Indirect &&
3016 insn->Src[0].Indirect.File == TGSI_FILE_ADDRESS) {
3017 const struct tgsi_full_src_register *reg = &insn->Src[0];
3018 if (reg->Register.Index < 0) {
3019 pre_parse_add_indirect(emit, reg->Register.Index, current_arl);
3020 }
3021 }
3022
3023 if (insn->Src[1].Register.Indirect &&
3024 insn->Src[1].Indirect.File == TGSI_FILE_ADDRESS) {
3025 const struct tgsi_full_src_register *reg = &insn->Src[1];
3026 if (reg->Register.Index < 0) {
3027 pre_parse_add_indirect(emit, reg->Register.Index, current_arl);
3028 }
3029 }
3030
3031 if (insn->Src[2].Register.Indirect &&
3032 insn->Src[2].Indirect.File == TGSI_FILE_ADDRESS) {
3033 const struct tgsi_full_src_register *reg = &insn->Src[2];
3034 if (reg->Register.Index < 0) {
3035 pre_parse_add_indirect(emit, reg->Register.Index, current_arl);
3036 }
3037 }
3038
3039 return TRUE;
3040 }
3041
3042 static boolean
3043 pre_parse_tokens( struct svga_shader_emitter *emit,
3044 const struct tgsi_token *tokens )
3045 {
3046 struct tgsi_parse_context parse;
3047 int current_arl = 0;
3048
3049 tgsi_parse_init( &parse, tokens );
3050
3051 while (!tgsi_parse_end_of_tokens( &parse )) {
3052 tgsi_parse_token( &parse );
3053 switch (parse.FullToken.Token.Type) {
3054 case TGSI_TOKEN_TYPE_IMMEDIATE:
3055 case TGSI_TOKEN_TYPE_DECLARATION:
3056 break;
3057 case TGSI_TOKEN_TYPE_INSTRUCTION:
3058 if (parse.FullToken.FullInstruction.Instruction.Opcode ==
3059 TGSI_OPCODE_ARL) {
3060 ++current_arl;
3061 }
3062 if (!pre_parse_instruction( emit, &parse.FullToken.FullInstruction,
3063 current_arl ))
3064 return FALSE;
3065 break;
3066 default:
3067 break;
3068 }
3069
3070 }
3071 return TRUE;
3072 }
3073
3074 static boolean svga_shader_emit_helpers( struct svga_shader_emitter *emit )
3075
3076 {
3077 if (needs_to_create_zero( emit )) {
3078 create_zero_immediate( emit );
3079 }
3080 if (needs_to_create_loop_const( emit )) {
3081 create_loop_const( emit );
3082 }
3083 if (needs_to_create_sincos_consts( emit )) {
3084 create_sincos_consts( emit );
3085 }
3086 if (needs_to_create_arl_consts( emit )) {
3087 create_arl_consts( emit );
3088 }
3089
3090 if (emit->unit == PIPE_SHADER_FRAGMENT) {
3091 if (!emit_ps_preamble( emit ))
3092 return FALSE;
3093
3094 if (emit->key.fkey.light_twoside) {
3095 if (!emit_light_twoside( emit ))
3096 return FALSE;
3097 }
3098 if (emit->emit_frontface) {
3099 if (!emit_frontface( emit ))
3100 return FALSE;
3101 }
3102 if (emit->inverted_texcoords) {
3103 if (!emit_inverted_texcoords( emit ))
3104 return FALSE;
3105 }
3106 }
3107
3108 return TRUE;
3109 }
3110
3111 boolean svga_shader_emit_instructions( struct svga_shader_emitter *emit,
3112 const struct tgsi_token *tokens )
3113 {
3114 struct tgsi_parse_context parse;
3115 boolean ret = TRUE;
3116 boolean helpers_emitted = FALSE;
3117 unsigned line_nr = 0;
3118
3119 tgsi_parse_init( &parse, tokens );
3120 emit->internal_imm_count = 0;
3121
3122 if (emit->unit == PIPE_SHADER_VERTEX) {
3123 ret = emit_vs_preamble( emit );
3124 if (!ret)
3125 goto done;
3126 }
3127
3128 pre_parse_tokens(emit, tokens);
3129
3130 while (!tgsi_parse_end_of_tokens( &parse )) {
3131 tgsi_parse_token( &parse );
3132
3133 switch (parse.FullToken.Token.Type) {
3134 case TGSI_TOKEN_TYPE_IMMEDIATE:
3135 ret = svga_emit_immediate( emit, &parse.FullToken.FullImmediate );
3136 if (!ret)
3137 goto done;
3138 break;
3139
3140 case TGSI_TOKEN_TYPE_DECLARATION:
3141 if (emit->use_sm30)
3142 ret = svga_translate_decl_sm30( emit, &parse.FullToken.FullDeclaration );
3143 else
3144 ret = svga_translate_decl_sm20( emit, &parse.FullToken.FullDeclaration );
3145 if (!ret)
3146 goto done;
3147 break;
3148
3149 case TGSI_TOKEN_TYPE_INSTRUCTION:
3150 if (!helpers_emitted) {
3151 if (!svga_shader_emit_helpers( emit ))
3152 goto done;
3153 helpers_emitted = TRUE;
3154 }
3155 ret = svga_emit_instruction( emit,
3156 line_nr++,
3157 &parse.FullToken.FullInstruction );
3158 if (!ret)
3159 goto done;
3160 break;
3161 default:
3162 break;
3163 }
3164
3165 reset_temp_regs( emit );
3166 }
3167
3168 /* Need to terminate the current subroutine. Note that the
3169 * hardware doesn't tolerate shaders without sub-routines
3170 * terminating with RET+END.
3171 */
3172 if (!emit->in_main_func) {
3173 ret = emit_instruction( emit, inst_token( SVGA3DOP_RET ) );
3174 if (!ret)
3175 goto done;
3176 }
3177
3178 assert(emit->dynamic_branching_level == 0);
3179
3180 /* Need to terminate the whole shader:
3181 */
3182 ret = emit_instruction( emit, inst_token( SVGA3DOP_END ) );
3183 if (!ret)
3184 goto done;
3185
3186 done:
3187 tgsi_parse_free( &parse );
3188 return ret;
3189 }
3190