1 /**********************************************************
2 * Copyright 2008-2009 VMware, Inc. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 **********************************************************/
27 #include "pipe/p_shader_tokens.h"
28 #include "tgsi/tgsi_parse.h"
29 #include "util/u_memory.h"
31 #include "svga_tgsi_emit.h"
32 #include "svga_context.h"
35 static boolean
emit_vs_postamble( struct svga_shader_emitter
*emit
);
36 static boolean
emit_ps_postamble( struct svga_shader_emitter
*emit
);
46 case TGSI_OPCODE_ABS
: return SVGA3DOP_ABS
;
47 case TGSI_OPCODE_ADD
: return SVGA3DOP_ADD
;
48 case TGSI_OPCODE_BREAKC
: return SVGA3DOP_BREAKC
;
49 case TGSI_OPCODE_DDX
: return SVGA3DOP_DSX
;
50 case TGSI_OPCODE_DDY
: return SVGA3DOP_DSY
;
51 case TGSI_OPCODE_DP2A
: return SVGA3DOP_DP2ADD
;
52 case TGSI_OPCODE_DP3
: return SVGA3DOP_DP3
;
53 case TGSI_OPCODE_DP4
: return SVGA3DOP_DP4
;
54 case TGSI_OPCODE_ENDFOR
: return SVGA3DOP_ENDLOOP
;
55 case TGSI_OPCODE_FRC
: return SVGA3DOP_FRC
;
56 case TGSI_OPCODE_BGNFOR
: return SVGA3DOP_LOOP
;
57 case TGSI_OPCODE_MAD
: return SVGA3DOP_MAD
;
58 case TGSI_OPCODE_MAX
: return SVGA3DOP_MAX
;
59 case TGSI_OPCODE_MIN
: return SVGA3DOP_MIN
;
60 case TGSI_OPCODE_MOV
: return SVGA3DOP_MOV
;
61 case TGSI_OPCODE_MUL
: return SVGA3DOP_MUL
;
62 case TGSI_OPCODE_NOP
: return SVGA3DOP_NOP
;
63 case TGSI_OPCODE_NRM4
: return SVGA3DOP_NRM
;
64 case TGSI_OPCODE_SSG
: return SVGA3DOP_SGN
;
66 debug_printf("Unkown opcode %u\n", opcode
);
68 return SVGA3DOP_LAST_INST
;
73 static unsigned translate_file( unsigned file
)
76 case TGSI_FILE_TEMPORARY
: return SVGA3DREG_TEMP
;
77 case TGSI_FILE_INPUT
: return SVGA3DREG_INPUT
;
78 case TGSI_FILE_OUTPUT
: return SVGA3DREG_OUTPUT
; /* VS3.0+ only */
79 case TGSI_FILE_IMMEDIATE
: return SVGA3DREG_CONST
;
80 case TGSI_FILE_CONSTANT
: return SVGA3DREG_CONST
;
81 case TGSI_FILE_SAMPLER
: return SVGA3DREG_SAMPLER
;
82 case TGSI_FILE_ADDRESS
: return SVGA3DREG_ADDR
;
85 return SVGA3DREG_TEMP
;
94 static SVGA3dShaderDestToken
95 translate_dst_register( struct svga_shader_emitter
*emit
,
96 const struct tgsi_full_instruction
*insn
,
99 const struct tgsi_full_dst_register
*reg
= &insn
->Dst
[idx
];
100 SVGA3dShaderDestToken dest
;
102 switch (reg
->Register
.File
) {
103 case TGSI_FILE_OUTPUT
:
104 /* Output registers encode semantic information in their name.
105 * Need to lookup a table built at decl time:
107 dest
= emit
->output_map
[reg
->Register
.Index
];
111 dest
= dst_register( translate_file( reg
->Register
.File
),
112 reg
->Register
.Index
);
116 dest
.mask
= reg
->Register
.WriteMask
;
118 if (insn
->Instruction
.Saturate
)
119 dest
.dstMod
= SVGA3DDSTMOD_SATURATE
;
125 static struct src_register
126 swizzle( struct src_register src
,
132 x
= (src
.base
.swizzle
>> (x
* 2)) & 0x3;
133 y
= (src
.base
.swizzle
>> (y
* 2)) & 0x3;
134 z
= (src
.base
.swizzle
>> (z
* 2)) & 0x3;
135 w
= (src
.base
.swizzle
>> (w
* 2)) & 0x3;
137 src
.base
.swizzle
= TRANSLATE_SWIZZLE(x
,y
,z
,w
);
142 static struct src_register
143 scalar( struct src_register src
,
146 return swizzle( src
, comp
, comp
, comp
, comp
);
149 static INLINE boolean
150 svga_arl_needs_adjustment( const struct svga_shader_emitter
*emit
)
154 for (i
= 0; i
< emit
->num_arl_consts
; ++i
) {
155 if (emit
->arl_consts
[i
].arl_num
== emit
->current_arl
)
162 svga_arl_adjustment( const struct svga_shader_emitter
*emit
)
166 for (i
= 0; i
< emit
->num_arl_consts
; ++i
) {
167 if (emit
->arl_consts
[i
].arl_num
== emit
->current_arl
)
168 return emit
->arl_consts
[i
].number
;
173 static struct src_register
174 translate_src_register( const struct svga_shader_emitter
*emit
,
175 const struct tgsi_full_src_register
*reg
)
177 struct src_register src
;
179 switch (reg
->SrcRegister
.File
) {
180 case TGSI_FILE_INPUT
:
181 /* Input registers are referred to by their semantic name rather
182 * than by index. Use the mapping build up from the decls:
184 src
= emit
->input_map
[reg
->SrcRegister
.Index
];
187 case TGSI_FILE_IMMEDIATE
:
188 /* Immediates are appended after TGSI constants in the D3D
191 src
= src_register( translate_file( reg
->SrcRegister
.File
),
192 reg
->SrcRegister
.Index
+
197 src
= src_register( translate_file( reg
->SrcRegister
.File
),
198 reg
->SrcRegister
.Index
);
203 /* Indirect addressing (for coninstant buffer lookups only)
205 if (reg
->SrcRegister
.Indirect
)
207 /* we shift the offset towards the minimum */
208 if (svga_arl_needs_adjustment( emit
)) {
209 src
.base
.num
-= svga_arl_adjustment( emit
);
211 src
.base
.relAddr
= 1;
213 /* Not really sure what should go in the second token:
215 src
.indirect
= src_token( SVGA3DREG_ADDR
,
216 reg
->SrcRegisterInd
.Index
);
218 src
.indirect
.swizzle
= SWIZZLE_XXXX
;
222 reg
->SrcRegister
.SwizzleX
,
223 reg
->SrcRegister
.SwizzleY
,
224 reg
->SrcRegister
.SwizzleZ
,
225 reg
->SrcRegister
.SwizzleW
);
227 /* src.mod isn't a bitfield, unfortunately:
228 * See tgsi_util_get_full_src_register_sign_mode for implementation details.
230 if (reg
->SrcRegister
.Absolute
) {
231 if (reg
->SrcRegister
.Negate
)
232 src
.base
.srcMod
= SVGA3DSRCMOD_ABSNEG
;
234 src
.base
.srcMod
= SVGA3DSRCMOD_ABS
;
237 if (reg
->SrcRegister
.Negate
)
238 src
.base
.srcMod
= SVGA3DSRCMOD_NEG
;
240 src
.base
.srcMod
= SVGA3DSRCMOD_NONE
;
248 * Get a temporary register, return -1 if none available
250 static INLINE SVGA3dShaderDestToken
251 get_temp( struct svga_shader_emitter
*emit
)
253 int i
= emit
->nr_hw_temp
+ emit
->internal_temp_count
++;
255 return dst_register( SVGA3DREG_TEMP
, i
);
258 /* Release a single temp. Currently only effective if it was the last
259 * allocated temp, otherwise release will be delayed until the next
260 * call to reset_temp_regs().
263 release_temp( struct svga_shader_emitter
*emit
,
264 SVGA3dShaderDestToken temp
)
266 if (temp
.num
== emit
->internal_temp_count
- 1)
267 emit
->internal_temp_count
--;
270 static void reset_temp_regs( struct svga_shader_emitter
*emit
)
272 emit
->internal_temp_count
= 0;
276 static boolean
submit_op0( struct svga_shader_emitter
*emit
,
277 SVGA3dShaderInstToken inst
,
278 SVGA3dShaderDestToken dest
)
280 return (emit_instruction( emit
, inst
) &&
281 emit_dst( emit
, dest
));
284 static boolean
submit_op1( struct svga_shader_emitter
*emit
,
285 SVGA3dShaderInstToken inst
,
286 SVGA3dShaderDestToken dest
,
287 struct src_register src0
)
289 return emit_op1( emit
, inst
, dest
, src0
);
293 /* SVGA shaders may not refer to >1 constant register in a single
294 * instruction. This function checks for that usage and inserts a
295 * move to temporary if detected.
297 * The same applies to input registers -- at most a single input
298 * register may be read by any instruction.
300 static boolean
submit_op2( struct svga_shader_emitter
*emit
,
301 SVGA3dShaderInstToken inst
,
302 SVGA3dShaderDestToken dest
,
303 struct src_register src0
,
304 struct src_register src1
)
306 SVGA3dShaderDestToken temp
;
307 SVGA3dShaderRegType type0
, type1
;
308 boolean need_temp
= FALSE
;
311 type0
= SVGA3dShaderGetRegType( src0
.base
.value
);
312 type1
= SVGA3dShaderGetRegType( src1
.base
.value
);
314 if (type0
== SVGA3DREG_CONST
&&
315 type1
== SVGA3DREG_CONST
&&
316 src0
.base
.num
!= src1
.base
.num
)
319 if (type0
== SVGA3DREG_INPUT
&&
320 type1
== SVGA3DREG_INPUT
&&
321 src0
.base
.num
!= src1
.base
.num
)
326 temp
= get_temp( emit
);
328 if (!emit_op1( emit
, inst_token( SVGA3DOP_MOV
), temp
, src0
))
334 if (!emit_op2( emit
, inst
, dest
, src0
, src1
))
338 release_temp( emit
, temp
);
344 /* SVGA shaders may not refer to >1 constant register in a single
345 * instruction. This function checks for that usage and inserts a
346 * move to temporary if detected.
348 static boolean
submit_op3( struct svga_shader_emitter
*emit
,
349 SVGA3dShaderInstToken inst
,
350 SVGA3dShaderDestToken dest
,
351 struct src_register src0
,
352 struct src_register src1
,
353 struct src_register src2
)
355 SVGA3dShaderDestToken temp0
;
356 SVGA3dShaderDestToken temp1
;
357 boolean need_temp0
= FALSE
;
358 boolean need_temp1
= FALSE
;
359 SVGA3dShaderRegType type0
, type1
, type2
;
363 type0
= SVGA3dShaderGetRegType( src0
.base
.value
);
364 type1
= SVGA3dShaderGetRegType( src1
.base
.value
);
365 type2
= SVGA3dShaderGetRegType( src2
.base
.value
);
367 if (inst
.op
!= SVGA3DOP_SINCOS
) {
368 if (type0
== SVGA3DREG_CONST
&&
369 ((type1
== SVGA3DREG_CONST
&& src0
.base
.num
!= src1
.base
.num
) ||
370 (type2
== SVGA3DREG_CONST
&& src0
.base
.num
!= src2
.base
.num
)))
373 if (type1
== SVGA3DREG_CONST
&&
374 (type2
== SVGA3DREG_CONST
&& src1
.base
.num
!= src2
.base
.num
))
378 if (type0
== SVGA3DREG_INPUT
&&
379 ((type1
== SVGA3DREG_INPUT
&& src0
.base
.num
!= src1
.base
.num
) ||
380 (type2
== SVGA3DREG_INPUT
&& src0
.base
.num
!= src2
.base
.num
)))
383 if (type1
== SVGA3DREG_INPUT
&&
384 (type2
== SVGA3DREG_INPUT
&& src1
.base
.num
!= src2
.base
.num
))
389 temp0
= get_temp( emit
);
391 if (!emit_op1( emit
, inst_token( SVGA3DOP_MOV
), temp0
, src0
))
399 temp1
= get_temp( emit
);
401 if (!emit_op1( emit
, inst_token( SVGA3DOP_MOV
), temp1
, src1
))
407 if (!emit_op3( emit
, inst
, dest
, src0
, src1
, src2
))
411 release_temp( emit
, temp1
);
413 release_temp( emit
, temp0
);
418 static boolean
emit_def_const( struct svga_shader_emitter
*emit
,
419 SVGA3dShaderConstType type
,
427 SVGA3dShaderInstToken opcode
;
430 case SVGA3D_CONST_TYPE_FLOAT
:
431 opcode
= inst_token( SVGA3DOP_DEF
);
432 def
.dst
= dst_register( SVGA3DREG_CONST
, idx
);
433 def
.constValues
[0] = a
;
434 def
.constValues
[1] = b
;
435 def
.constValues
[2] = c
;
436 def
.constValues
[3] = d
;
438 case SVGA3D_CONST_TYPE_INT
:
439 opcode
= inst_token( SVGA3DOP_DEFI
);
440 def
.dst
= dst_register( SVGA3DREG_CONSTINT
, idx
);
441 def
.constIValues
[0] = (int)a
;
442 def
.constIValues
[1] = (int)b
;
443 def
.constIValues
[2] = (int)c
;
444 def
.constIValues
[3] = (int)d
;
451 if (!emit_instruction(emit
, opcode
) ||
452 !svga_shader_emit_dwords( emit
, def
.values
, Elements(def
.values
)))
458 static INLINE boolean
459 create_zero_immediate( struct svga_shader_emitter
*emit
)
461 unsigned idx
= emit
->nr_hw_const
++;
463 if (!emit_def_const( emit
, SVGA3D_CONST_TYPE_FLOAT
,
467 emit
->zero_immediate_idx
= idx
;
468 emit
->created_zero_immediate
= TRUE
;
473 static INLINE boolean
474 create_loop_const( struct svga_shader_emitter
*emit
)
476 unsigned idx
= emit
->nr_hw_const
++;
478 if (!emit_def_const( emit
, SVGA3D_CONST_TYPE_INT
, idx
,
479 255, /* iteration count */
480 0, /* initial value */
482 0 /* not used, must be 0 */))
485 emit
->loop_const_idx
= idx
;
486 emit
->created_loop_const
= TRUE
;
491 static INLINE boolean
492 create_sincos_consts( struct svga_shader_emitter
*emit
)
494 unsigned idx
= emit
->nr_hw_const
++;
496 if (!emit_def_const( emit
, SVGA3D_CONST_TYPE_FLOAT
, idx
,
503 emit
->sincos_consts_idx
= idx
;
504 idx
= emit
->nr_hw_const
++;
506 if (!emit_def_const( emit
, SVGA3D_CONST_TYPE_FLOAT
, idx
,
513 emit
->created_sincos_consts
= TRUE
;
518 static INLINE boolean
519 create_arl_consts( struct svga_shader_emitter
*emit
)
523 for (i
= 0; i
< emit
->num_arl_consts
; i
+= 4) {
525 unsigned idx
= emit
->nr_hw_const
++;
527 for (j
= 0; j
< 4 && (j
+ i
) < emit
->num_arl_consts
; ++j
) {
528 vals
[j
] = emit
->arl_consts
[i
+ j
].number
;
529 emit
->arl_consts
[i
+ j
].idx
= idx
;
532 emit
->arl_consts
[i
+ 0].swizzle
= TGSI_SWIZZLE_X
;
535 emit
->arl_consts
[i
+ 0].swizzle
= TGSI_SWIZZLE_Y
;
538 emit
->arl_consts
[i
+ 0].swizzle
= TGSI_SWIZZLE_Z
;
541 emit
->arl_consts
[i
+ 0].swizzle
= TGSI_SWIZZLE_W
;
548 if (!emit_def_const( emit
, SVGA3D_CONST_TYPE_FLOAT
, idx
,
557 static INLINE
struct src_register
558 get_vface( struct svga_shader_emitter
*emit
)
560 assert(emit
->emitted_vface
);
561 return src_register(SVGA3DREG_MISCTYPE
,
565 /* returns {0, 0, 0, 1} immediate */
566 static INLINE
struct src_register
567 get_zero_immediate( struct svga_shader_emitter
*emit
)
569 assert(emit
->created_zero_immediate
);
570 assert(emit
->zero_immediate_idx
>= 0);
571 return src_register( SVGA3DREG_CONST
,
572 emit
->zero_immediate_idx
);
575 /* returns the loop const */
576 static INLINE
struct src_register
577 get_loop_const( struct svga_shader_emitter
*emit
)
579 assert(emit
->created_loop_const
);
580 assert(emit
->loop_const_idx
>= 0);
581 return src_register( SVGA3DREG_CONSTINT
,
582 emit
->loop_const_idx
);
585 /* returns a sincos const */
586 static INLINE
struct src_register
587 get_sincos_const( struct svga_shader_emitter
*emit
,
590 assert(emit
->created_sincos_consts
);
591 assert(emit
->sincos_consts_idx
>= 0);
592 assert(index
== 0 || index
== 1);
593 return src_register( SVGA3DREG_CONST
,
594 emit
->sincos_consts_idx
+ index
);
597 static INLINE
struct src_register
598 get_fake_arl_const( struct svga_shader_emitter
*emit
)
600 struct src_register reg
;
601 int idx
= 0, swizzle
= 0, i
;
603 for (i
= 0; i
< emit
->num_arl_consts
; ++ i
) {
604 if (emit
->arl_consts
[i
].arl_num
== emit
->current_arl
) {
605 idx
= emit
->arl_consts
[i
].idx
;
606 swizzle
= emit
->arl_consts
[i
].swizzle
;
610 reg
= src_register( SVGA3DREG_CONST
, idx
);
611 return scalar(reg
, swizzle
);
614 static INLINE
struct src_register
615 get_tex_dimensions( struct svga_shader_emitter
*emit
, int sampler_num
)
618 struct src_register reg
;
620 /* the width/height indexes start right after constants */
621 idx
= emit
->key
.fkey
.tex
[sampler_num
].width_height_idx
+
622 emit
->info
.file_max
[TGSI_FILE_CONSTANT
] + 1;
624 reg
= src_register( SVGA3DREG_CONST
, idx
);
628 static boolean
emit_fake_arl(struct svga_shader_emitter
*emit
,
629 const struct tgsi_full_instruction
*insn
)
631 const struct src_register src0
= translate_src_register(
632 emit
, &insn
->Src
[0] );
633 struct src_register src1
= get_fake_arl_const( emit
);
634 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
635 SVGA3dShaderDestToken tmp
= get_temp( emit
);
637 if (!submit_op1(emit
, inst_token( SVGA3DOP_MOV
), tmp
, src0
))
640 if (!submit_op2( emit
, inst_token( SVGA3DOP_ADD
), tmp
, src( tmp
),
644 /* replicate the original swizzle */
646 src1
.base
.swizzle
= src0
.base
.swizzle
;
648 return submit_op1( emit
, inst_token( SVGA3DOP_MOVA
),
652 static boolean
emit_if(struct svga_shader_emitter
*emit
,
653 const struct tgsi_full_instruction
*insn
)
655 const struct src_register src
= translate_src_register(
656 emit
, &insn
->Src
[0] );
657 struct src_register zero
= get_zero_immediate( emit
);
658 SVGA3dShaderInstToken if_token
= inst_token( SVGA3DOP_IFC
);
660 if_token
.control
= SVGA3DOPCOMPC_NE
;
661 zero
= scalar(zero
, TGSI_SWIZZLE_X
);
663 return (emit_instruction( emit
, if_token
) &&
664 emit_src( emit
, src
) &&
665 emit_src( emit
, zero
) );
668 static boolean
emit_endif(struct svga_shader_emitter
*emit
,
669 const struct tgsi_full_instruction
*insn
)
671 return (emit_instruction( emit
,
672 inst_token( SVGA3DOP_ENDIF
)));
675 static boolean
emit_else(struct svga_shader_emitter
*emit
,
676 const struct tgsi_full_instruction
*insn
)
678 return (emit_instruction( emit
,
679 inst_token( SVGA3DOP_ELSE
)));
682 /* Translate the following TGSI FLR instruction.
684 * To the following SVGA3D instruction sequence.
688 static boolean
emit_floor(struct svga_shader_emitter
*emit
,
689 const struct tgsi_full_instruction
*insn
)
691 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
692 const struct src_register src0
= translate_src_register(
693 emit
, &insn
->Src
[0] );
694 SVGA3dShaderDestToken temp
= get_temp( emit
);
697 if (!submit_op1( emit
, inst_token( SVGA3DOP_FRC
), temp
, src0
))
700 /* SUB DST, SRC, TMP */
701 if (!submit_op2( emit
, inst_token( SVGA3DOP_ADD
), dst
, src0
,
702 negate( src( temp
) ) ))
709 /* Translate the following TGSI CMP instruction.
710 * CMP DST, SRC0, SRC1, SRC2
711 * To the following SVGA3D instruction sequence.
712 * CMP DST, SRC0, SRC2, SRC1
714 static boolean
emit_cmp(struct svga_shader_emitter
*emit
,
715 const struct tgsi_full_instruction
*insn
)
717 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
718 const struct src_register src0
= translate_src_register(
719 emit
, &insn
->Src
[0] );
720 const struct src_register src1
= translate_src_register(
721 emit
, &insn
->Src
[1] );
722 const struct src_register src2
= translate_src_register(
723 emit
, &insn
->Src
[2] );
725 /* CMP DST, SRC0, SRC2, SRC1 */
726 return submit_op3( emit
, inst_token( SVGA3DOP_CMP
), dst
, src0
, src2
, src1
);
731 /* Translate the following TGSI DIV instruction.
732 * DIV DST.xy, SRC0, SRC1
733 * To the following SVGA3D instruction sequence.
734 * RCP TMP.x, SRC1.xxxx
735 * RCP TMP.y, SRC1.yyyy
736 * MUL DST.xy, SRC0, TMP
738 static boolean
emit_div(struct svga_shader_emitter
*emit
,
739 const struct tgsi_full_instruction
*insn
)
741 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
742 const struct src_register src0
= translate_src_register(
743 emit
, &insn
->Src
[0] );
744 const struct src_register src1
= translate_src_register(
745 emit
, &insn
->Src
[1] );
746 SVGA3dShaderDestToken temp
= get_temp( emit
);
749 /* For each enabled element, perform a RCP instruction. Note that
750 * RCP is scalar in SVGA3D:
752 for (i
= 0; i
< 4; i
++) {
753 unsigned channel
= 1 << i
;
754 if (dst
.mask
& channel
) {
755 /* RCP TMP.?, SRC1.???? */
756 if (!submit_op1( emit
, inst_token( SVGA3DOP_RCP
),
757 writemask(temp
, channel
),
763 /* Then multiply them out with a single mul:
767 if (!submit_op2( emit
, inst_token( SVGA3DOP_MUL
), dst
, src0
,
774 /* Translate the following TGSI DP2 instruction.
775 * DP2 DST, SRC1, SRC2
776 * To the following SVGA3D instruction sequence.
777 * MUL TMP, SRC1, SRC2
778 * ADD DST, TMP.xxxx, TMP.yyyy
780 static boolean
emit_dp2(struct svga_shader_emitter
*emit
,
781 const struct tgsi_full_instruction
*insn
)
783 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
784 const struct src_register src0
= translate_src_register(
785 emit
, &insn
->Src
[0] );
786 const struct src_register src1
= translate_src_register(
787 emit
, &insn
->Src
[1] );
788 SVGA3dShaderDestToken temp
= get_temp( emit
);
789 struct src_register temp_src0
, temp_src1
;
791 /* MUL TMP, SRC1, SRC2 */
792 if (!submit_op2( emit
, inst_token( SVGA3DOP_MUL
), temp
, src0
, src1
))
795 temp_src0
= scalar(src( temp
), TGSI_SWIZZLE_X
);
796 temp_src1
= scalar(src( temp
), TGSI_SWIZZLE_Y
);
798 /* ADD DST, TMP.xxxx, TMP.yyyy */
799 if (!submit_op2( emit
, inst_token( SVGA3DOP_ADD
), dst
,
800 temp_src0
, temp_src1
))
807 /* Translate the following TGSI DPH instruction.
808 * DPH DST, SRC1, SRC2
809 * To the following SVGA3D instruction sequence.
810 * DP3 TMP, SRC1, SRC2
811 * ADD DST, TMP, SRC2.wwww
813 static boolean
emit_dph(struct svga_shader_emitter
*emit
,
814 const struct tgsi_full_instruction
*insn
)
816 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
817 const struct src_register src0
= translate_src_register(
818 emit
, &insn
->Src
[0] );
819 struct src_register src1
= translate_src_register(
820 emit
, &insn
->Src
[1] );
821 SVGA3dShaderDestToken temp
= get_temp( emit
);
823 /* DP3 TMP, SRC1, SRC2 */
824 if (!submit_op2( emit
, inst_token( SVGA3DOP_DP3
), temp
, src0
, src1
))
827 src1
= scalar(src1
, TGSI_SWIZZLE_W
);
829 /* ADD DST, TMP, SRC2.wwww */
830 if (!submit_op2( emit
, inst_token( SVGA3DOP_ADD
), dst
,
837 /* Translate the following TGSI DST instruction.
839 * To the following SVGA3D instruction sequence.
844 static boolean
emit_nrm(struct svga_shader_emitter
*emit
,
845 const struct tgsi_full_instruction
*insn
)
847 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
848 const struct src_register src0
= translate_src_register(
849 emit
, &insn
->Src
[0] );
850 SVGA3dShaderDestToken temp
= get_temp( emit
);
852 /* DP3 TMP, SRC, SRC */
853 if (!submit_op2( emit
, inst_token( SVGA3DOP_DP3
), temp
, src0
, src0
))
857 if (!submit_op1( emit
, inst_token( SVGA3DOP_RSQ
), temp
, src( temp
)))
860 /* MUL DST, SRC, TMP */
861 if (!submit_op2( emit
, inst_token( SVGA3DOP_MUL
), dst
,
869 static boolean
do_emit_sincos(struct svga_shader_emitter
*emit
,
870 SVGA3dShaderDestToken dst
,
871 struct src_register src0
)
873 src0
= scalar(src0
, TGSI_SWIZZLE_X
);
875 if (emit
->use_sm30
) {
876 return submit_op1( emit
, inst_token( SVGA3DOP_SINCOS
),
879 struct src_register const1
= get_sincos_const( emit
, 0 );
880 struct src_register const2
= get_sincos_const( emit
, 1 );
882 return submit_op3( emit
, inst_token( SVGA3DOP_SINCOS
),
883 dst
, src0
, const1
, const2
);
887 static boolean
emit_sincos(struct svga_shader_emitter
*emit
,
888 const struct tgsi_full_instruction
*insn
)
890 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
891 struct src_register src0
= translate_src_register(
892 emit
, &insn
->Src
[0] );
893 SVGA3dShaderDestToken temp
= get_temp( emit
);
896 if (!do_emit_sincos(emit
, writemask(temp
, TGSI_WRITEMASK_XY
), src0
))
900 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), dst
, src( temp
) ))
910 static boolean
emit_sin(struct svga_shader_emitter
*emit
,
911 const struct tgsi_full_instruction
*insn
)
913 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
914 struct src_register src0
= translate_src_register(
915 emit
, &insn
->Src
[0] );
916 SVGA3dShaderDestToken temp
= get_temp( emit
);
919 if (!do_emit_sincos(emit
, writemask(temp
, TGSI_WRITEMASK_Y
), src0
))
922 src0
= scalar(src( temp
), TGSI_SWIZZLE_Y
);
924 /* MOV DST TMP.yyyy */
925 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), dst
, src0
))
935 static boolean
emit_cos(struct svga_shader_emitter
*emit
,
936 const struct tgsi_full_instruction
*insn
)
938 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
939 struct src_register src0
= translate_src_register(
940 emit
, &insn
->Src
[0] );
941 SVGA3dShaderDestToken temp
= get_temp( emit
);
944 if (!do_emit_sincos( emit
, writemask(temp
, TGSI_WRITEMASK_X
), src0
))
947 src0
= scalar(src( temp
), TGSI_SWIZZLE_X
);
949 /* MOV DST TMP.xxxx */
950 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), dst
, src0
))
958 * ADD DST SRC0, negate(SRC0)
960 static boolean
emit_sub(struct svga_shader_emitter
*emit
,
961 const struct tgsi_full_instruction
*insn
)
963 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
964 struct src_register src0
= translate_src_register(
965 emit
, &insn
->Src
[0] );
966 struct src_register src1
= translate_src_register(
967 emit
, &insn
->Src
[1] );
971 if (!submit_op2( emit
, inst_token( SVGA3DOP_ADD
), dst
,
979 static boolean
emit_kil(struct svga_shader_emitter
*emit
,
980 const struct tgsi_full_instruction
*insn
)
982 SVGA3dShaderInstToken inst
;
983 const struct tgsi_full_src_register
*reg
= &insn
->Src
[0];
984 struct src_register src0
;
986 inst
= inst_token( SVGA3DOP_TEXKILL
);
987 src0
= translate_src_register( emit
, reg
);
989 if (reg
->SrcRegister
.Absolute
||
990 reg
->SrcRegister
.Negate
||
991 reg
->SrcRegister
.Indirect
||
992 reg
->SrcRegister
.SwizzleX
!= 0 ||
993 reg
->SrcRegister
.SwizzleY
!= 1 ||
994 reg
->SrcRegister
.SwizzleZ
!= 2 ||
995 reg
->SrcRegister
.File
!= TGSI_FILE_TEMPORARY
)
997 SVGA3dShaderDestToken temp
= get_temp( emit
);
999 submit_op1( emit
, inst_token( SVGA3DOP_MOV
), temp
, src0
);
1003 return submit_op0( emit
, inst
, dst(src0
) );
1007 /* mesa state tracker always emits kilp as an unconditional
1009 static boolean
emit_kilp(struct svga_shader_emitter
*emit
,
1010 const struct tgsi_full_instruction
*insn
)
1012 SVGA3dShaderInstToken inst
;
1013 SVGA3dShaderDestToken temp
;
1014 struct src_register one
= get_zero_immediate( emit
);
1016 inst
= inst_token( SVGA3DOP_TEXKILL
);
1017 one
= scalar( one
, TGSI_SWIZZLE_W
);
1019 /* texkill doesn't allow negation on the operand so lets move
1020 * negation of {1} to a temp register */
1021 temp
= get_temp( emit
);
1022 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), temp
,
1026 return submit_op0( emit
, inst
, temp
);
1029 /* Implement conditionals by initializing destination reg to 'fail',
1030 * then set predicate reg with UFOP_SETP, then move 'pass' to dest
1031 * based on predicate reg.
1033 * SETP src0, cmp, src1 -- do this first to avoid aliasing problems.
1038 emit_conditional(struct svga_shader_emitter
*emit
,
1039 unsigned compare_func
,
1040 SVGA3dShaderDestToken dst
,
1041 struct src_register src0
,
1042 struct src_register src1
,
1043 struct src_register pass
,
1044 struct src_register fail
)
1046 SVGA3dShaderDestToken pred_reg
= dst_register( SVGA3DREG_PREDICATE
, 0 );
1047 SVGA3dShaderInstToken setp_token
, mov_token
;
1048 setp_token
= inst_token( SVGA3DOP_SETP
);
1050 switch (compare_func
) {
1051 case PIPE_FUNC_NEVER
:
1052 return submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
1055 case PIPE_FUNC_LESS
:
1056 setp_token
.control
= SVGA3DOPCOMP_LT
;
1058 case PIPE_FUNC_EQUAL
:
1059 setp_token
.control
= SVGA3DOPCOMP_EQ
;
1061 case PIPE_FUNC_LEQUAL
:
1062 setp_token
.control
= SVGA3DOPCOMP_LE
;
1064 case PIPE_FUNC_GREATER
:
1065 setp_token
.control
= SVGA3DOPCOMP_GT
;
1067 case PIPE_FUNC_NOTEQUAL
:
1068 setp_token
.control
= SVGA3DOPCOMPC_NE
;
1070 case PIPE_FUNC_GEQUAL
:
1071 setp_token
.control
= SVGA3DOPCOMP_GE
;
1073 case PIPE_FUNC_ALWAYS
:
1074 return submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
1079 /* SETP src0, COMPOP, src1 */
1080 if (!submit_op2( emit
, setp_token
, pred_reg
,
1084 mov_token
= inst_token( SVGA3DOP_MOV
);
1087 if (!submit_op1( emit
, mov_token
, dst
,
1091 /* MOV dst, pass (predicated)
1093 * Note that the predicate reg (and possible modifiers) is passed
1094 * as the first source argument.
1096 mov_token
.predicated
= 1;
1097 if (!submit_op2( emit
, mov_token
, dst
,
1098 src( pred_reg
), pass
))
1106 emit_select(struct svga_shader_emitter
*emit
,
1107 unsigned compare_func
,
1108 SVGA3dShaderDestToken dst
,
1109 struct src_register src0
,
1110 struct src_register src1
)
1112 /* There are some SVGA instructions which implement some selects
1113 * directly, but they are only available in the vertex shader.
1115 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
1116 switch (compare_func
) {
1117 case PIPE_FUNC_GEQUAL
:
1118 return submit_op2( emit
, inst_token( SVGA3DOP_SGE
), dst
, src0
, src1
);
1119 case PIPE_FUNC_LEQUAL
:
1120 return submit_op2( emit
, inst_token( SVGA3DOP_SGE
), dst
, src1
, src0
);
1121 case PIPE_FUNC_GREATER
:
1122 return submit_op2( emit
, inst_token( SVGA3DOP_SLT
), dst
, src1
, src0
);
1123 case PIPE_FUNC_LESS
:
1124 return submit_op2( emit
, inst_token( SVGA3DOP_SLT
), dst
, src0
, src1
);
1131 /* Otherwise, need to use the setp approach:
1134 struct src_register one
, zero
;
1135 /* zero immediate is 0,0,0,1 */
1136 zero
= get_zero_immediate( emit
);
1137 one
= scalar( zero
, TGSI_SWIZZLE_W
);
1138 zero
= scalar( zero
, TGSI_SWIZZLE_X
);
1140 return emit_conditional(
1151 static boolean
emit_select_op(struct svga_shader_emitter
*emit
,
1153 const struct tgsi_full_instruction
*insn
)
1155 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1156 struct src_register src0
= translate_src_register(
1157 emit
, &insn
->Src
[0] );
1158 struct src_register src1
= translate_src_register(
1159 emit
, &insn
->Src
[1] );
1161 return emit_select( emit
, compare
, dst
, src0
, src1
);
1165 /* Translate texture instructions to SVGA3D representation.
1167 static boolean
emit_tex2(struct svga_shader_emitter
*emit
,
1168 const struct tgsi_full_instruction
*insn
,
1169 SVGA3dShaderDestToken dst
)
1171 SVGA3dShaderInstToken inst
;
1172 struct src_register src0
;
1173 struct src_register src1
;
1176 inst
.op
= SVGA3DOP_TEX
;
1178 switch (insn
->Instruction
.Opcode
) {
1179 case TGSI_OPCODE_TEX
:
1181 case TGSI_OPCODE_TXP
:
1182 inst
.control
= SVGA3DOPCONT_PROJECT
;
1184 case TGSI_OPCODE_TXB
:
1185 inst
.control
= SVGA3DOPCONT_BIAS
;
1192 src0
= translate_src_register( emit
, &insn
->Src
[0] );
1193 src1
= translate_src_register( emit
, &insn
->Src
[1] );
1195 if (emit
->key
.fkey
.tex
[src1
.base
.num
].unnormalized
) {
1196 struct src_register wh
= get_tex_dimensions( emit
, src1
.base
.num
);
1197 SVGA3dShaderDestToken tmp
= get_temp( emit
);
1199 /* MUL tmp, SRC0, WH */
1200 if (!submit_op2( emit
, inst_token( SVGA3DOP_MUL
),
1206 return submit_op2( emit
, inst
, dst
, src0
, src1
);
1212 /* Translate texture instructions to SVGA3D representation.
1214 static boolean
emit_tex3(struct svga_shader_emitter
*emit
,
1215 const struct tgsi_full_instruction
*insn
,
1216 SVGA3dShaderDestToken dst
)
1218 SVGA3dShaderInstToken inst
;
1219 struct src_register src0
;
1220 struct src_register src1
;
1221 struct src_register src2
;
1225 switch (insn
->Instruction
.Opcode
) {
1226 case TGSI_OPCODE_TXD
:
1227 inst
.op
= SVGA3DOP_TEXLDD
;
1229 case TGSI_OPCODE_TXL
:
1230 inst
.op
= SVGA3DOP_TEXLDL
;
1234 src0
= translate_src_register( emit
, &insn
->Src
[0] );
1235 src1
= translate_src_register( emit
, &insn
->Src
[1] );
1236 src2
= translate_src_register( emit
, &insn
->Src
[2] );
1238 return submit_op3( emit
, inst
, dst
, src0
, src1
, src2
);
1242 static boolean
emit_tex(struct svga_shader_emitter
*emit
,
1243 const struct tgsi_full_instruction
*insn
)
1245 SVGA3dShaderDestToken dst
=
1246 translate_dst_register( emit
, insn
, 0 );
1247 struct src_register src0
=
1248 translate_src_register( emit
, &insn
->Src
[0] );
1249 struct src_register src1
=
1250 translate_src_register( emit
, &insn
->Src
[1] );
1252 SVGA3dShaderDestToken tex_result
;
1254 /* check for shadow samplers */
1255 boolean compare
= (emit
->key
.fkey
.tex
[src1
.base
.num
].compare_mode
==
1256 PIPE_TEX_COMPARE_R_TO_TEXTURE
);
1259 /* If doing compare processing, need to put this value into a
1260 * temporary so it can be used as a source later on.
1263 (!emit
->use_sm30
&& dst
.mask
!= TGSI_WRITEMASK_XYZW
) ) {
1264 tex_result
= get_temp( emit
);
1270 switch(insn
->Instruction
.Opcode
) {
1271 case TGSI_OPCODE_TEX
:
1272 case TGSI_OPCODE_TXB
:
1273 case TGSI_OPCODE_TXP
:
1274 if (!emit_tex2( emit
, insn
, tex_result
))
1277 case TGSI_OPCODE_TXL
:
1278 case TGSI_OPCODE_TXD
:
1279 if (!emit_tex3( emit
, insn
, tex_result
))
1288 SVGA3dShaderDestToken src0_zdivw
= get_temp( emit
);
1289 struct src_register tex_src_x
= scalar(src(tex_result
), TGSI_SWIZZLE_Y
);
1290 struct src_register one
=
1291 scalar( get_zero_immediate( emit
), TGSI_SWIZZLE_W
);
1293 /* Divide texcoord R by Q */
1294 if (!submit_op1( emit
, inst_token( SVGA3DOP_RCP
),
1296 scalar(src0
, TGSI_SWIZZLE_W
) ))
1299 if (!submit_op2( emit
, inst_token( SVGA3DOP_MUL
),
1301 scalar(src0
, TGSI_SWIZZLE_Z
),
1307 emit
->key
.fkey
.tex
[src1
.base
.num
].compare_func
,
1313 return submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
1314 writemask( dst
, TGSI_WRITEMASK_W
),
1317 else if (!emit
->use_sm30
&& dst
.mask
!= TGSI_WRITEMASK_XYZW
)
1319 if (!emit_op1( emit
, inst_token( SVGA3DOP_MOV
), dst
, src(tex_result
) ))
1326 static boolean
emit_bgnloop2( struct svga_shader_emitter
*emit
,
1327 const struct tgsi_full_instruction
*insn
)
1329 SVGA3dShaderInstToken inst
= inst_token( SVGA3DOP_LOOP
);
1330 struct src_register loop_reg
= src_register( SVGA3DREG_LOOP
, 0 );
1331 struct src_register const_int
= get_loop_const( emit
);
1333 return (emit_instruction( emit
, inst
) &&
1334 emit_src( emit
, loop_reg
) &&
1335 emit_src( emit
, const_int
) );
1338 static boolean
emit_endloop2( struct svga_shader_emitter
*emit
,
1339 const struct tgsi_full_instruction
*insn
)
1341 SVGA3dShaderInstToken inst
= inst_token( SVGA3DOP_ENDLOOP
);
1342 return emit_instruction( emit
, inst
);
1345 static boolean
emit_brk( struct svga_shader_emitter
*emit
,
1346 const struct tgsi_full_instruction
*insn
)
1348 SVGA3dShaderInstToken inst
= inst_token( SVGA3DOP_BREAK
);
1349 return emit_instruction( emit
, inst
);
1352 static boolean
emit_scalar_op1( struct svga_shader_emitter
*emit
,
1354 const struct tgsi_full_instruction
*insn
)
1356 SVGA3dShaderInstToken inst
;
1357 SVGA3dShaderDestToken dst
;
1358 struct src_register src
;
1360 inst
= inst_token( opcode
);
1361 dst
= translate_dst_register( emit
, insn
, 0 );
1362 src
= translate_src_register( emit
, &insn
->Src
[0] );
1363 src
= scalar( src
, TGSI_SWIZZLE_X
);
1365 return submit_op1( emit
, inst
, dst
, src
);
1369 static boolean
emit_simple_instruction(struct svga_shader_emitter
*emit
,
1371 const struct tgsi_full_instruction
*insn
)
1373 const struct tgsi_full_src_register
*src
= insn
->Src
;
1374 SVGA3dShaderInstToken inst
;
1375 SVGA3dShaderDestToken dst
;
1377 inst
= inst_token( opcode
);
1378 dst
= translate_dst_register( emit
, insn
, 0 );
1380 switch (insn
->Instruction
.NumSrcRegs
) {
1382 return submit_op0( emit
, inst
, dst
);
1384 return submit_op1( emit
, inst
, dst
,
1385 translate_src_register( emit
, &src
[0] ));
1387 return submit_op2( emit
, inst
, dst
,
1388 translate_src_register( emit
, &src
[0] ),
1389 translate_src_register( emit
, &src
[1] ) );
1391 return submit_op3( emit
, inst
, dst
,
1392 translate_src_register( emit
, &src
[0] ),
1393 translate_src_register( emit
, &src
[1] ),
1394 translate_src_register( emit
, &src
[2] ) );
1401 static boolean
emit_arl(struct svga_shader_emitter
*emit
,
1402 const struct tgsi_full_instruction
*insn
)
1404 ++emit
->current_arl
;
1405 if (svga_arl_needs_adjustment( emit
)) {
1406 return emit_fake_arl( emit
, insn
);
1408 /* no need to adjust, just emit straight arl */
1409 return emit_simple_instruction(emit
, SVGA3DOP_MOVA
, insn
);
1413 static boolean
alias_src_dst( struct src_register src
,
1414 SVGA3dShaderDestToken dst
)
1416 if (src
.base
.num
!= dst
.num
)
1419 if (SVGA3dShaderGetRegType(dst
.value
) !=
1420 SVGA3dShaderGetRegType(src
.base
.value
))
1426 static boolean
emit_pow(struct svga_shader_emitter
*emit
,
1427 const struct tgsi_full_instruction
*insn
)
1429 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1430 struct src_register src0
= translate_src_register(
1431 emit
, &insn
->Src
[0] );
1432 struct src_register src1
= translate_src_register(
1433 emit
, &insn
->Src
[1] );
1434 boolean need_tmp
= FALSE
;
1436 /* POW can only output to a temporary */
1437 if (insn
->Dst
[0].Register
.File
!= TGSI_FILE_TEMPORARY
)
1440 /* POW src1 must not be the same register as dst */
1441 if (alias_src_dst( src1
, dst
))
1444 /* it's a scalar op */
1445 src0
= scalar( src0
, TGSI_SWIZZLE_X
);
1446 src1
= scalar( src1
, TGSI_SWIZZLE_X
);
1449 SVGA3dShaderDestToken tmp
= writemask(get_temp( emit
), TGSI_WRITEMASK_X
);
1451 if (!submit_op2(emit
, inst_token( SVGA3DOP_POW
), tmp
, src0
, src1
))
1454 return submit_op1(emit
, inst_token( SVGA3DOP_MOV
), dst
, scalar(src(tmp
), 0) );
1457 return submit_op2(emit
, inst_token( SVGA3DOP_POW
), dst
, src0
, src1
);
1461 static boolean
emit_xpd(struct svga_shader_emitter
*emit
,
1462 const struct tgsi_full_instruction
*insn
)
1464 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1465 const struct src_register src0
= translate_src_register(
1466 emit
, &insn
->Src
[0] );
1467 const struct src_register src1
= translate_src_register(
1468 emit
, &insn
->Src
[1] );
1469 boolean need_dst_tmp
= FALSE
;
1471 /* XPD can only output to a temporary */
1472 if (SVGA3dShaderGetRegType(dst
.value
) != SVGA3DREG_TEMP
)
1473 need_dst_tmp
= TRUE
;
1475 /* The dst reg must not be the same as src0 or src1*/
1476 if (alias_src_dst(src0
, dst
) ||
1477 alias_src_dst(src1
, dst
))
1478 need_dst_tmp
= TRUE
;
1481 SVGA3dShaderDestToken tmp
= get_temp( emit
);
1483 /* Obey DX9 restrictions on mask:
1485 tmp
.mask
= dst
.mask
& TGSI_WRITEMASK_XYZ
;
1487 if (!submit_op2(emit
, inst_token( SVGA3DOP_CRS
), tmp
, src0
, src1
))
1490 if (!submit_op1(emit
, inst_token( SVGA3DOP_MOV
), dst
, src( tmp
)))
1494 if (!submit_op2(emit
, inst_token( SVGA3DOP_CRS
), dst
, src0
, src1
))
1498 /* Need to emit 1.0 to dst.w?
1500 if (dst
.mask
& TGSI_WRITEMASK_W
) {
1501 struct src_register zero
= get_zero_immediate( emit
);
1503 if (!submit_op1(emit
,
1504 inst_token( SVGA3DOP_MOV
),
1505 writemask(dst
, TGSI_WRITEMASK_W
),
1514 static boolean
emit_lrp(struct svga_shader_emitter
*emit
,
1515 const struct tgsi_full_instruction
*insn
)
1517 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1518 SVGA3dShaderDestToken tmp
;
1519 const struct src_register src0
= translate_src_register(
1520 emit
, &insn
->Src
[0] );
1521 const struct src_register src1
= translate_src_register(
1522 emit
, &insn
->Src
[1] );
1523 const struct src_register src2
= translate_src_register(
1524 emit
, &insn
->Src
[2] );
1525 boolean need_dst_tmp
= FALSE
;
1527 /* The dst reg must not be the same as src0 or src2 */
1528 if (alias_src_dst(src0
, dst
) ||
1529 alias_src_dst(src2
, dst
))
1530 need_dst_tmp
= TRUE
;
1533 tmp
= get_temp( emit
);
1534 tmp
.mask
= dst
.mask
;
1540 if (!submit_op3(emit
, inst_token( SVGA3DOP_LRP
), tmp
, src0
, src1
, src2
))
1544 if (!submit_op1(emit
, inst_token( SVGA3DOP_MOV
), dst
, src( tmp
)))
1552 static boolean
emit_dst_insn(struct svga_shader_emitter
*emit
,
1553 const struct tgsi_full_instruction
*insn
)
1555 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
1556 /* SVGA/DX9 has a DST instruction, but only for vertex shaders:
1558 return emit_simple_instruction(emit
, SVGA3DOP_DST
, insn
);
1562 /* result[0] = 1 * 1;
1563 * result[1] = a[1] * b[1];
1564 * result[2] = a[2] * 1;
1565 * result[3] = 1 * b[3];
1568 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1569 SVGA3dShaderDestToken tmp
;
1570 const struct src_register src0
= translate_src_register(
1571 emit
, &insn
->Src
[0] );
1572 const struct src_register src1
= translate_src_register(
1573 emit
, &insn
->Src
[1] );
1574 struct src_register zero
= get_zero_immediate( emit
);
1575 boolean need_tmp
= FALSE
;
1577 if (SVGA3dShaderGetRegType(dst
.value
) != SVGA3DREG_TEMP
||
1578 alias_src_dst(src0
, dst
) ||
1579 alias_src_dst(src1
, dst
))
1583 tmp
= get_temp( emit
);
1591 if (tmp
.mask
& TGSI_WRITEMASK_XW
) {
1592 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
1593 writemask(tmp
, TGSI_WRITEMASK_XW
),
1600 if (tmp
.mask
& TGSI_WRITEMASK_YZ
) {
1601 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
1602 writemask(tmp
, TGSI_WRITEMASK_YZ
),
1607 /* tmp.yw = tmp * src1
1609 if (tmp
.mask
& TGSI_WRITEMASK_YW
) {
1610 if (!submit_op2( emit
, inst_token( SVGA3DOP_MUL
),
1611 writemask(tmp
, TGSI_WRITEMASK_YW
),
1620 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
1631 static boolean
emit_exp(struct svga_shader_emitter
*emit
,
1632 const struct tgsi_full_instruction
*insn
)
1634 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1635 struct src_register src0
=
1636 translate_src_register( emit
, &insn
->Src
[0] );
1637 struct src_register zero
= get_zero_immediate( emit
);
1638 SVGA3dShaderDestToken fraction
;
1640 if (dst
.mask
& TGSI_WRITEMASK_Y
)
1642 else if (dst
.mask
& TGSI_WRITEMASK_X
)
1643 fraction
= get_temp( emit
);
1645 /* If y is being written, fill it with src0 - floor(src0).
1647 if (dst
.mask
& TGSI_WRITEMASK_XY
) {
1648 if (!submit_op1( emit
, inst_token( SVGA3DOP_FRC
),
1649 writemask( fraction
, TGSI_WRITEMASK_Y
),
1654 /* If x is being written, fill it with 2 ^ floor(src0).
1656 if (dst
.mask
& TGSI_WRITEMASK_X
) {
1657 if (!submit_op2( emit
, inst_token( SVGA3DOP_ADD
),
1658 writemask( dst
, dst
.mask
& TGSI_WRITEMASK_X
),
1660 scalar( negate( src( fraction
) ), TGSI_SWIZZLE_Y
) ) )
1663 if (!submit_op1( emit
, inst_token( SVGA3DOP_EXP
),
1664 writemask( dst
, dst
.mask
& TGSI_WRITEMASK_X
),
1665 scalar( src( dst
), TGSI_SWIZZLE_X
) ) )
1668 if (!(dst
.mask
& TGSI_WRITEMASK_Y
))
1669 release_temp( emit
, fraction
);
1672 /* If z is being written, fill it with 2 ^ src0 (partial precision).
1674 if (dst
.mask
& TGSI_WRITEMASK_Z
) {
1675 if (!submit_op1( emit
, inst_token( SVGA3DOP_EXPP
),
1676 writemask( dst
, dst
.mask
& TGSI_WRITEMASK_Z
),
1681 /* If w is being written, fill it with one.
1683 if (dst
.mask
& TGSI_WRITEMASK_W
) {
1684 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
1685 writemask(dst
, TGSI_WRITEMASK_W
),
1686 scalar( zero
, TGSI_SWIZZLE_W
) ))
1693 static boolean
emit_lit(struct svga_shader_emitter
*emit
,
1694 const struct tgsi_full_instruction
*insn
)
1696 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
1697 /* SVGA/DX9 has a LIT instruction, but only for vertex shaders:
1699 return emit_simple_instruction(emit
, SVGA3DOP_LIT
, insn
);
1703 /* D3D vs. GL semantics can be fairly easily accomodated by
1704 * variations on this sequence.
1708 * tmp.z = pow(src.y,src.w)
1709 * p0 = src0.xxxx > 0
1710 * result = zero.wxxw
1711 * (p0) result.yz = tmp
1715 * tmp.z = pow(src.y,src.w)
1716 * p0 = src0.xxyy > 0
1717 * result = zero.wxxw
1718 * (p0) result.yz = tmp
1720 * Will implement the GL version for now.
1723 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1724 SVGA3dShaderDestToken tmp
= get_temp( emit
);
1725 const struct src_register src0
= translate_src_register(
1726 emit
, &insn
->Src
[0] );
1727 struct src_register zero
= get_zero_immediate( emit
);
1729 /* tmp = pow(src.y, src.w)
1731 if (dst
.mask
& TGSI_WRITEMASK_Z
) {
1732 if (!submit_op2(emit
, inst_token( SVGA3DOP_POW
),
1741 if (dst
.mask
& TGSI_WRITEMASK_Y
) {
1742 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
1743 writemask(tmp
, TGSI_WRITEMASK_Y
),
1748 /* Can't quite do this with emit conditional due to the extra
1749 * writemask on the predicated mov:
1752 SVGA3dShaderDestToken pred_reg
= dst_register( SVGA3DREG_PREDICATE
, 0 );
1753 SVGA3dShaderInstToken setp_token
, mov_token
;
1754 struct src_register predsrc
;
1756 setp_token
= inst_token( SVGA3DOP_SETP
);
1757 mov_token
= inst_token( SVGA3DOP_MOV
);
1759 setp_token
.control
= SVGA3DOPCOMP_GT
;
1761 /* D3D vs GL semantics:
1764 predsrc
= swizzle(src0
, 0, 0, 1, 1); /* D3D */
1766 predsrc
= swizzle(src0
, 0, 0, 0, 0); /* GL */
1768 /* SETP src0.xxyy, GT, {0}.x */
1769 if (!submit_op2( emit
, setp_token
, pred_reg
,
1771 swizzle(zero
, 0, 0, 0, 0) ))
1775 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), dst
,
1776 swizzle(zero
, 3, 0, 0, 3 )))
1779 /* MOV dst.yz, tmp (predicated)
1781 * Note that the predicate reg (and possible modifiers) is passed
1782 * as the first source argument.
1784 if (dst
.mask
& TGSI_WRITEMASK_YZ
) {
1785 mov_token
.predicated
= 1;
1786 if (!submit_op2( emit
, mov_token
,
1787 writemask(dst
, TGSI_WRITEMASK_YZ
),
1788 src( pred_reg
), src( tmp
) ))
1800 static boolean
emit_ex2( struct svga_shader_emitter
*emit
,
1801 const struct tgsi_full_instruction
*insn
)
1803 SVGA3dShaderInstToken inst
;
1804 SVGA3dShaderDestToken dst
;
1805 struct src_register src0
;
1807 inst
= inst_token( SVGA3DOP_EXP
);
1808 dst
= translate_dst_register( emit
, insn
, 0 );
1809 src0
= translate_src_register( emit
, &insn
->Src
[0] );
1810 src0
= scalar( src0
, TGSI_SWIZZLE_X
);
1812 if (dst
.mask
!= TGSI_WRITEMASK_XYZW
) {
1813 SVGA3dShaderDestToken tmp
= get_temp( emit
);
1815 if (!submit_op1( emit
, inst
, tmp
, src0
))
1818 return submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
1820 scalar( src( tmp
), TGSI_SWIZZLE_X
) );
1823 return submit_op1( emit
, inst
, dst
, src0
);
1827 static boolean
emit_log(struct svga_shader_emitter
*emit
,
1828 const struct tgsi_full_instruction
*insn
)
1830 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1831 struct src_register src0
=
1832 translate_src_register( emit
, &insn
->Src
[0] );
1833 struct src_register zero
= get_zero_immediate( emit
);
1834 SVGA3dShaderDestToken abs_tmp
;
1835 struct src_register abs_src0
;
1836 SVGA3dShaderDestToken log2_abs
;
1838 if (dst
.mask
& TGSI_WRITEMASK_Z
)
1840 else if (dst
.mask
& TGSI_WRITEMASK_XY
)
1841 log2_abs
= get_temp( emit
);
1843 /* If z is being written, fill it with log2( abs( src0 ) ).
1845 if (dst
.mask
& TGSI_WRITEMASK_XYZ
) {
1846 if (!src0
.base
.srcMod
|| src0
.base
.srcMod
== SVGA3DSRCMOD_ABS
)
1849 abs_tmp
= get_temp( emit
);
1851 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
1856 abs_src0
= src( abs_tmp
);
1859 abs_src0
= absolute( scalar( abs_src0
, TGSI_SWIZZLE_X
) );
1861 if (!submit_op1( emit
, inst_token( SVGA3DOP_LOG
),
1862 writemask( log2_abs
, TGSI_WRITEMASK_Z
),
1867 if (dst
.mask
& TGSI_WRITEMASK_XY
) {
1868 SVGA3dShaderDestToken floor_log2
;
1870 if (dst
.mask
& TGSI_WRITEMASK_X
)
1873 floor_log2
= get_temp( emit
);
1875 /* If x is being written, fill it with floor( log2( abs( src0 ) ) ).
1877 if (!submit_op1( emit
, inst_token( SVGA3DOP_FRC
),
1878 writemask( floor_log2
, TGSI_WRITEMASK_X
),
1879 scalar( src( log2_abs
), TGSI_SWIZZLE_Z
) ) )
1882 if (!submit_op2( emit
, inst_token( SVGA3DOP_ADD
),
1883 writemask( floor_log2
, TGSI_WRITEMASK_X
),
1884 scalar( src( log2_abs
), TGSI_SWIZZLE_Z
),
1885 negate( src( floor_log2
) ) ) )
1888 /* If y is being written, fill it with
1889 * abs ( src0 ) / ( 2 ^ floor( log2( abs( src0 ) ) ) ).
1891 if (dst
.mask
& TGSI_WRITEMASK_Y
) {
1892 if (!submit_op1( emit
, inst_token( SVGA3DOP_EXP
),
1893 writemask( dst
, TGSI_WRITEMASK_Y
),
1894 negate( scalar( src( floor_log2
),
1895 TGSI_SWIZZLE_X
) ) ) )
1898 if (!submit_op2( emit
, inst_token( SVGA3DOP_MUL
),
1899 writemask( dst
, TGSI_WRITEMASK_Y
),
1905 if (!(dst
.mask
& TGSI_WRITEMASK_X
))
1906 release_temp( emit
, floor_log2
);
1908 if (!(dst
.mask
& TGSI_WRITEMASK_Z
))
1909 release_temp( emit
, log2_abs
);
1912 if (dst
.mask
& TGSI_WRITEMASK_XYZ
&& src0
.base
.srcMod
&&
1913 src0
.base
.srcMod
!= SVGA3DSRCMOD_ABS
)
1914 release_temp( emit
, abs_tmp
);
1916 /* If w is being written, fill it with one.
1918 if (dst
.mask
& TGSI_WRITEMASK_W
) {
1919 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
1920 writemask(dst
, TGSI_WRITEMASK_W
),
1921 scalar( zero
, TGSI_SWIZZLE_W
) ))
1929 static boolean
emit_bgnsub( struct svga_shader_emitter
*emit
,
1931 const struct tgsi_full_instruction
*insn
)
1935 /* Note that we've finished the main function and are now emitting
1936 * subroutines. This affects how we terminate the generated
1939 emit
->in_main_func
= FALSE
;
1941 for (i
= 0; i
< emit
->nr_labels
; i
++) {
1942 if (emit
->label
[i
] == position
) {
1943 return (emit_instruction( emit
, inst_token( SVGA3DOP_RET
) ) &&
1944 emit_instruction( emit
, inst_token( SVGA3DOP_LABEL
) ) &&
1945 emit_src( emit
, src_register( SVGA3DREG_LABEL
, i
)));
1953 static boolean
emit_call( struct svga_shader_emitter
*emit
,
1954 const struct tgsi_full_instruction
*insn
)
1956 unsigned position
= insn
->Label
.Label
;
1959 for (i
= 0; i
< emit
->nr_labels
; i
++) {
1960 if (emit
->label
[i
] == position
)
1964 if (emit
->nr_labels
== Elements(emit
->label
))
1967 if (i
== emit
->nr_labels
) {
1968 emit
->label
[i
] = position
;
1972 return (emit_instruction( emit
, inst_token( SVGA3DOP_CALL
) ) &&
1973 emit_src( emit
, src_register( SVGA3DREG_LABEL
, i
)));
1977 static boolean
emit_end( struct svga_shader_emitter
*emit
)
1979 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
1980 return emit_vs_postamble( emit
);
1983 return emit_ps_postamble( emit
);
1989 static boolean
svga_emit_instruction( struct svga_shader_emitter
*emit
,
1991 const struct tgsi_full_instruction
*insn
)
1993 switch (insn
->Instruction
.Opcode
) {
1995 case TGSI_OPCODE_ARL
:
1996 return emit_arl( emit
, insn
);
1998 case TGSI_OPCODE_TEX
:
1999 case TGSI_OPCODE_TXB
:
2000 case TGSI_OPCODE_TXP
:
2001 case TGSI_OPCODE_TXL
:
2002 case TGSI_OPCODE_TXD
:
2003 return emit_tex( emit
, insn
);
2005 case TGSI_OPCODE_BGNSUB
:
2006 return emit_bgnsub( emit
, position
, insn
);
2008 case TGSI_OPCODE_ENDSUB
:
2011 case TGSI_OPCODE_CAL
:
2012 return emit_call( emit
, insn
);
2014 case TGSI_OPCODE_FLR
:
2015 case TGSI_OPCODE_TRUNC
: /* should be TRUNC, not FLR */
2016 return emit_floor( emit
, insn
);
2018 case TGSI_OPCODE_CMP
:
2019 return emit_cmp( emit
, insn
);
2021 case TGSI_OPCODE_DIV
:
2022 return emit_div( emit
, insn
);
2024 case TGSI_OPCODE_DP2
:
2025 return emit_dp2( emit
, insn
);
2027 case TGSI_OPCODE_DPH
:
2028 return emit_dph( emit
, insn
);
2030 case TGSI_OPCODE_NRM
:
2031 return emit_nrm( emit
, insn
);
2033 case TGSI_OPCODE_COS
:
2034 return emit_cos( emit
, insn
);
2036 case TGSI_OPCODE_SIN
:
2037 return emit_sin( emit
, insn
);
2039 case TGSI_OPCODE_SCS
:
2040 return emit_sincos( emit
, insn
);
2042 case TGSI_OPCODE_END
:
2043 /* TGSI always finishes the main func with an END */
2044 return emit_end( emit
);
2046 case TGSI_OPCODE_KIL
:
2047 return emit_kil( emit
, insn
);
2049 /* Selection opcodes. The underlying language is fairly
2050 * non-orthogonal about these.
2052 case TGSI_OPCODE_SEQ
:
2053 return emit_select_op( emit
, PIPE_FUNC_EQUAL
, insn
);
2055 case TGSI_OPCODE_SNE
:
2056 return emit_select_op( emit
, PIPE_FUNC_NOTEQUAL
, insn
);
2058 case TGSI_OPCODE_SGT
:
2059 return emit_select_op( emit
, PIPE_FUNC_GREATER
, insn
);
2061 case TGSI_OPCODE_SGE
:
2062 return emit_select_op( emit
, PIPE_FUNC_GEQUAL
, insn
);
2064 case TGSI_OPCODE_SLT
:
2065 return emit_select_op( emit
, PIPE_FUNC_LESS
, insn
);
2067 case TGSI_OPCODE_SLE
:
2068 return emit_select_op( emit
, PIPE_FUNC_LEQUAL
, insn
);
2070 case TGSI_OPCODE_SUB
:
2071 return emit_sub( emit
, insn
);
2073 case TGSI_OPCODE_POW
:
2074 return emit_pow( emit
, insn
);
2076 case TGSI_OPCODE_EX2
:
2077 return emit_ex2( emit
, insn
);
2079 case TGSI_OPCODE_EXP
:
2080 return emit_exp( emit
, insn
);
2082 case TGSI_OPCODE_LOG
:
2083 return emit_log( emit
, insn
);
2085 case TGSI_OPCODE_LG2
:
2086 return emit_scalar_op1( emit
, SVGA3DOP_LOG
, insn
);
2088 case TGSI_OPCODE_RSQ
:
2089 return emit_scalar_op1( emit
, SVGA3DOP_RSQ
, insn
);
2091 case TGSI_OPCODE_RCP
:
2092 return emit_scalar_op1( emit
, SVGA3DOP_RCP
, insn
);
2094 case TGSI_OPCODE_CONT
:
2095 case TGSI_OPCODE_RET
:
2096 /* This is a noop -- we tell mesa that we can't support RET
2097 * within a function (early return), so this will always be
2098 * followed by an ENDSUB.
2102 /* These aren't actually used by any of the frontends we care
2105 case TGSI_OPCODE_CLAMP
:
2106 case TGSI_OPCODE_ROUND
:
2107 case TGSI_OPCODE_AND
:
2108 case TGSI_OPCODE_OR
:
2109 case TGSI_OPCODE_I2F
:
2110 case TGSI_OPCODE_NOT
:
2111 case TGSI_OPCODE_SHL
:
2112 case TGSI_OPCODE_SHR
:
2113 case TGSI_OPCODE_XOR
:
2116 case TGSI_OPCODE_IF
:
2117 return emit_if( emit
, insn
);
2118 case TGSI_OPCODE_ELSE
:
2119 return emit_else( emit
, insn
);
2120 case TGSI_OPCODE_ENDIF
:
2121 return emit_endif( emit
, insn
);
2123 case TGSI_OPCODE_BGNLOOP
:
2124 return emit_bgnloop2( emit
, insn
);
2125 case TGSI_OPCODE_ENDLOOP
:
2126 return emit_endloop2( emit
, insn
);
2127 case TGSI_OPCODE_BRK
:
2128 return emit_brk( emit
, insn
);
2130 case TGSI_OPCODE_XPD
:
2131 return emit_xpd( emit
, insn
);
2133 case TGSI_OPCODE_KILP
:
2134 return emit_kilp( emit
, insn
);
2136 case TGSI_OPCODE_DST
:
2137 return emit_dst_insn( emit
, insn
);
2139 case TGSI_OPCODE_LIT
:
2140 return emit_lit( emit
, insn
);
2142 case TGSI_OPCODE_LRP
:
2143 return emit_lrp( emit
, insn
);
2146 unsigned opcode
= translate_opcode(insn
->Instruction
.Opcode
);
2148 if (opcode
== SVGA3DOP_LAST_INST
)
2151 if (!emit_simple_instruction( emit
, opcode
, insn
))
2160 static boolean
svga_emit_immediate( struct svga_shader_emitter
*emit
,
2161 struct tgsi_full_immediate
*imm
)
2163 static const float id
[4] = {0,0,0,1};
2167 assert(1 <= imm
->Immediate
.NrTokens
&& imm
->Immediate
.NrTokens
<= 5);
2168 for (i
= 0; i
< imm
->Immediate
.NrTokens
- 1; i
++)
2169 value
[i
] = imm
->u
[i
].Float
;
2171 for ( ; i
< 4; i
++ )
2174 return emit_def_const( emit
, SVGA3D_CONST_TYPE_FLOAT
,
2175 emit
->imm_start
+ emit
->internal_imm_count
++,
2176 value
[0], value
[1], value
[2], value
[3]);
2179 static boolean
make_immediate( struct svga_shader_emitter
*emit
,
2184 struct src_register
*out
)
2186 unsigned idx
= emit
->nr_hw_const
++;
2188 if (!emit_def_const( emit
, SVGA3D_CONST_TYPE_FLOAT
,
2192 *out
= src_register( SVGA3DREG_CONST
, idx
);
2197 static boolean
emit_vs_preamble( struct svga_shader_emitter
*emit
)
2199 if (!emit
->key
.vkey
.need_prescale
) {
2200 if (!make_immediate( emit
, 0, 0, .5, .5,
2208 static boolean
emit_ps_preamble( struct svga_shader_emitter
*emit
)
2212 /* For SM20, need to initialize the temporaries we're using to hold
2213 * color outputs to some value. Shaders which don't set all of
2214 * these values are likely to be rejected by the DX9 runtime.
2216 if (!emit
->use_sm30
) {
2217 struct src_register zero
= get_zero_immediate( emit
);
2218 for (i
= 0; i
< PIPE_MAX_COLOR_BUFS
; i
++) {
2219 if (SVGA3dShaderGetRegType(emit
->true_col
[i
].value
) != 0) {
2221 if (!submit_op1( emit
,
2222 inst_token(SVGA3DOP_MOV
),
2233 static boolean
emit_ps_postamble( struct svga_shader_emitter
*emit
)
2237 /* PS oDepth is incredibly fragile and it's very hard to catch the
2238 * types of usage that break it during shader emit. Easier just to
2239 * redirect the main program to a temporary and then only touch
2240 * oDepth with a hand-crafted MOV below.
2242 if (SVGA3dShaderGetRegType(emit
->true_pos
.value
) != 0) {
2244 if (!submit_op1( emit
,
2245 inst_token(SVGA3DOP_MOV
),
2247 scalar(src(emit
->temp_pos
), TGSI_SWIZZLE_Z
) ))
2251 /* Similarly for SM20 color outputs... Luckily SM30 isn't so
2254 for (i
= 0; i
< PIPE_MAX_COLOR_BUFS
; i
++) {
2255 if (SVGA3dShaderGetRegType(emit
->true_col
[i
].value
) != 0) {
2257 if (!submit_op1( emit
,
2258 inst_token(SVGA3DOP_MOV
),
2260 src(emit
->temp_col
[i
]) ))
2268 static boolean
emit_vs_postamble( struct svga_shader_emitter
*emit
)
2270 /* PSIZ output is incredibly fragile and it's very hard to catch
2271 * the types of usage that break it during shader emit. Easier
2272 * just to redirect the main program to a temporary and then only
2273 * touch PSIZ with a hand-crafted MOV below.
2275 if (SVGA3dShaderGetRegType(emit
->true_psiz
.value
) != 0) {
2277 if (!submit_op1( emit
,
2278 inst_token(SVGA3DOP_MOV
),
2280 scalar(src(emit
->temp_psiz
), TGSI_SWIZZLE_X
) ))
2284 /* Need to perform various manipulations on vertex position to cope
2285 * with the different GL and D3D clip spaces.
2287 if (emit
->key
.vkey
.need_prescale
) {
2288 SVGA3dShaderDestToken temp_pos
= emit
->temp_pos
;
2289 SVGA3dShaderDestToken pos
= emit
->true_pos
;
2290 unsigned offset
= emit
->info
.file_max
[TGSI_FILE_CONSTANT
] + 1;
2291 struct src_register prescale_scale
= src_register( SVGA3DREG_CONST
,
2293 struct src_register prescale_trans
= src_register( SVGA3DREG_CONST
,
2296 /* MUL temp_pos.xyz, temp_pos, prescale.scale
2297 * MAD result.position, temp_pos.wwww, prescale.trans, temp_pos
2298 * --> Note that prescale.trans.w == 0
2300 if (!submit_op2( emit
,
2301 inst_token(SVGA3DOP_MUL
),
2302 writemask(temp_pos
, TGSI_WRITEMASK_XYZ
),
2307 if (!submit_op3( emit
,
2308 inst_token(SVGA3DOP_MAD
),
2310 swizzle(src(temp_pos
), 3, 3, 3, 3),
2316 SVGA3dShaderDestToken temp_pos
= emit
->temp_pos
;
2317 SVGA3dShaderDestToken pos
= emit
->true_pos
;
2318 struct src_register imm_0055
= emit
->imm_0055
;
2320 /* Adjust GL clipping coordinate space to hardware (D3D-style):
2322 * DP4 temp_pos.z, {0,0,.5,.5}, temp_pos
2323 * MOV result.position, temp_pos
2325 if (!submit_op2( emit
,
2326 inst_token(SVGA3DOP_DP4
),
2327 writemask(temp_pos
, TGSI_WRITEMASK_Z
),
2332 if (!submit_op1( emit
,
2333 inst_token(SVGA3DOP_MOV
),
2344 1: COLOR = FrontColor;
2346 3: COLOR = BackColor;
2349 static boolean
emit_light_twoside( struct svga_shader_emitter
*emit
)
2351 struct src_register vface
, zero
;
2352 struct src_register front
[2];
2353 struct src_register back
[2];
2354 SVGA3dShaderDestToken color
[2];
2355 int count
= emit
->internal_color_count
;
2357 SVGA3dShaderInstToken if_token
;
2362 vface
= get_vface( emit
);
2363 zero
= get_zero_immediate( emit
);
2365 /* Can't use get_temp() to allocate the color reg as such
2366 * temporaries will be reclaimed after each instruction by the call
2367 * to reset_temp_regs().
2369 for (i
= 0; i
< count
; i
++) {
2370 color
[i
] = dst_register( SVGA3DREG_TEMP
,
2371 emit
->nr_hw_temp
++ );
2373 front
[i
] = emit
->input_map
[emit
->internal_color_idx
[i
]];
2375 /* Back is always the next input:
2378 back
[i
].base
.num
= front
[i
].base
.num
+ 1;
2380 /* Reassign the input_map to the actual front-face color:
2382 emit
->input_map
[emit
->internal_color_idx
[i
]] = src(color
[i
]);
2385 if_token
= inst_token( SVGA3DOP_IFC
);
2387 if (emit
->key
.fkey
.front_cw
)
2388 if_token
.control
= SVGA3DOPCOMP_GT
;
2390 if_token
.control
= SVGA3DOPCOMP_LT
;
2392 zero
= scalar(zero
, TGSI_SWIZZLE_X
);
2394 if (!(emit_instruction( emit
, if_token
) &&
2395 emit_src( emit
, vface
) &&
2396 emit_src( emit
, zero
) ))
2399 for (i
= 0; i
< count
; i
++) {
2400 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), color
[i
], front
[i
] ))
2404 if (!(emit_instruction( emit
, inst_token( SVGA3DOP_ELSE
))))
2407 for (i
= 0; i
< count
; i
++) {
2408 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), color
[i
], back
[i
] ))
2412 if (!emit_instruction( emit
, inst_token( SVGA3DOP_ENDIF
) ))
2419 0: SETP_GT TEMP, VFACE, 0
2420 where TEMP is a fake frontface register
2422 static boolean
emit_frontface( struct svga_shader_emitter
*emit
)
2424 struct src_register vface
, zero
;
2425 SVGA3dShaderDestToken temp
;
2426 struct src_register pass
, fail
;
2428 vface
= get_vface( emit
);
2429 zero
= get_zero_immediate( emit
);
2431 /* Can't use get_temp() to allocate the fake frontface reg as such
2432 * temporaries will be reclaimed after each instruction by the call
2433 * to reset_temp_regs().
2435 temp
= dst_register( SVGA3DREG_TEMP
,
2436 emit
->nr_hw_temp
++ );
2438 if (emit
->key
.fkey
.front_cw
) {
2439 pass
= scalar( zero
, TGSI_SWIZZLE_W
);
2440 fail
= scalar( zero
, TGSI_SWIZZLE_X
);
2442 pass
= scalar( zero
, TGSI_SWIZZLE_X
);
2443 fail
= scalar( zero
, TGSI_SWIZZLE_W
);
2446 if (!emit_conditional(emit
, PIPE_FUNC_GREATER
,
2447 temp
, vface
, scalar( zero
, TGSI_SWIZZLE_X
),
2451 /* Reassign the input_map to the actual front-face color:
2453 emit
->input_map
[emit
->internal_frontface_idx
] = src(temp
);
2458 static INLINE boolean
2459 needs_to_create_zero( struct svga_shader_emitter
*emit
)
2463 if (emit
->unit
== PIPE_SHADER_FRAGMENT
) {
2464 if (!emit
->use_sm30
)
2467 if (emit
->key
.fkey
.light_twoside
)
2470 if (emit
->emit_frontface
)
2473 if (emit
->info
.opcode_count
[TGSI_OPCODE_DST
] >= 1 ||
2474 emit
->info
.opcode_count
[TGSI_OPCODE_LIT
] >= 1)
2478 if (emit
->info
.opcode_count
[TGSI_OPCODE_IF
] >= 1 ||
2479 emit
->info
.opcode_count
[TGSI_OPCODE_SGE
] >= 1 ||
2480 emit
->info
.opcode_count
[TGSI_OPCODE_SGT
] >= 1 ||
2481 emit
->info
.opcode_count
[TGSI_OPCODE_SLE
] >= 1 ||
2482 emit
->info
.opcode_count
[TGSI_OPCODE_SLT
] >= 1 ||
2483 emit
->info
.opcode_count
[TGSI_OPCODE_SNE
] >= 1 ||
2484 emit
->info
.opcode_count
[TGSI_OPCODE_SEQ
] >= 1 ||
2485 emit
->info
.opcode_count
[TGSI_OPCODE_EXP
] >= 1 ||
2486 emit
->info
.opcode_count
[TGSI_OPCODE_LOG
] >= 1 ||
2487 emit
->info
.opcode_count
[TGSI_OPCODE_XPD
] >= 1 ||
2488 emit
->info
.opcode_count
[TGSI_OPCODE_KILP
] >= 1)
2491 for (i
= 0; i
< emit
->key
.fkey
.num_textures
; i
++) {
2492 if (emit
->key
.fkey
.tex
[i
].compare_mode
== PIPE_TEX_COMPARE_R_TO_TEXTURE
)
2499 static INLINE boolean
2500 needs_to_create_loop_const( struct svga_shader_emitter
*emit
)
2502 return (emit
->info
.opcode_count
[TGSI_OPCODE_BGNLOOP
] >= 1);
2505 static INLINE boolean
2506 needs_to_create_sincos_consts( struct svga_shader_emitter
*emit
)
2508 return !emit
->use_sm30
&& (emit
->info
.opcode_count
[TGSI_OPCODE_SIN
] >= 1 ||
2509 emit
->info
.opcode_count
[TGSI_OPCODE_COS
] >= 1 ||
2510 emit
->info
.opcode_count
[TGSI_OPCODE_SCS
] >= 1);
2513 static INLINE boolean
2514 needs_to_create_arl_consts( struct svga_shader_emitter
*emit
)
2516 return (emit
->num_arl_consts
> 0);
2519 static INLINE boolean
2520 pre_parse_add_indirect( struct svga_shader_emitter
*emit
,
2521 int num
, int current_arl
)
2526 for (i
= 0; i
< emit
->num_arl_consts
; ++i
) {
2527 if (emit
->arl_consts
[i
].arl_num
== current_arl
)
2531 if (emit
->num_arl_consts
== i
) {
2532 ++emit
->num_arl_consts
;
2534 emit
->arl_consts
[i
].number
= (emit
->arl_consts
[i
].number
> num
) ?
2536 emit
->arl_consts
[i
].number
;
2537 emit
->arl_consts
[i
].arl_num
= current_arl
;
2542 pre_parse_instruction( struct svga_shader_emitter
*emit
,
2543 const struct tgsi_full_instruction
*insn
,
2546 if (insn
->Src
[0].SrcRegister
.Indirect
&&
2547 insn
->Src
[0].SrcRegisterInd
.File
== TGSI_FILE_ADDRESS
) {
2548 const struct tgsi_full_src_register
*reg
= &insn
->Src
[0];
2549 if (reg
->SrcRegister
.Index
< 0) {
2550 pre_parse_add_indirect(emit
, reg
->SrcRegister
.Index
, current_arl
);
2554 if (insn
->Src
[1].SrcRegister
.Indirect
&&
2555 insn
->Src
[1].SrcRegisterInd
.File
== TGSI_FILE_ADDRESS
) {
2556 const struct tgsi_full_src_register
*reg
= &insn
->Src
[1];
2557 if (reg
->SrcRegister
.Index
< 0) {
2558 pre_parse_add_indirect(emit
, reg
->SrcRegister
.Index
, current_arl
);
2562 if (insn
->Src
[2].SrcRegister
.Indirect
&&
2563 insn
->Src
[2].SrcRegisterInd
.File
== TGSI_FILE_ADDRESS
) {
2564 const struct tgsi_full_src_register
*reg
= &insn
->Src
[2];
2565 if (reg
->SrcRegister
.Index
< 0) {
2566 pre_parse_add_indirect(emit
, reg
->SrcRegister
.Index
, current_arl
);
2574 pre_parse_tokens( struct svga_shader_emitter
*emit
,
2575 const struct tgsi_token
*tokens
)
2577 struct tgsi_parse_context parse
;
2578 int current_arl
= 0;
2580 tgsi_parse_init( &parse
, tokens
);
2582 while (!tgsi_parse_end_of_tokens( &parse
)) {
2583 tgsi_parse_token( &parse
);
2584 switch (parse
.FullToken
.Token
.Type
) {
2585 case TGSI_TOKEN_TYPE_IMMEDIATE
:
2586 case TGSI_TOKEN_TYPE_DECLARATION
:
2588 case TGSI_TOKEN_TYPE_INSTRUCTION
:
2589 if (parse
.FullToken
.FullInstruction
.Instruction
.Opcode
==
2593 if (!pre_parse_instruction( emit
, &parse
.FullToken
.FullInstruction
,
2605 static boolean
svga_shader_emit_helpers( struct svga_shader_emitter
*emit
)
2608 if (needs_to_create_zero( emit
)) {
2609 create_zero_immediate( emit
);
2611 if (needs_to_create_loop_const( emit
)) {
2612 create_loop_const( emit
);
2614 if (needs_to_create_sincos_consts( emit
)) {
2615 create_sincos_consts( emit
);
2617 if (needs_to_create_arl_consts( emit
)) {
2618 create_arl_consts( emit
);
2621 if (emit
->unit
== PIPE_SHADER_FRAGMENT
) {
2622 if (!emit_ps_preamble( emit
))
2625 if (emit
->key
.fkey
.light_twoside
) {
2626 if (!emit_light_twoside( emit
))
2629 if (emit
->emit_frontface
) {
2630 if (!emit_frontface( emit
))
2638 boolean
svga_shader_emit_instructions( struct svga_shader_emitter
*emit
,
2639 const struct tgsi_token
*tokens
)
2641 struct tgsi_parse_context parse
;
2643 boolean helpers_emitted
= FALSE
;
2644 unsigned line_nr
= 0;
2646 tgsi_parse_init( &parse
, tokens
);
2647 emit
->internal_imm_count
= 0;
2649 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
2650 ret
= emit_vs_preamble( emit
);
2655 pre_parse_tokens(emit
, tokens
);
2657 while (!tgsi_parse_end_of_tokens( &parse
)) {
2658 tgsi_parse_token( &parse
);
2660 switch (parse
.FullToken
.Token
.Type
) {
2661 case TGSI_TOKEN_TYPE_IMMEDIATE
:
2662 ret
= svga_emit_immediate( emit
, &parse
.FullToken
.FullImmediate
);
2667 case TGSI_TOKEN_TYPE_DECLARATION
:
2669 ret
= svga_translate_decl_sm30( emit
, &parse
.FullToken
.FullDeclaration
);
2671 ret
= svga_translate_decl_sm20( emit
, &parse
.FullToken
.FullDeclaration
);
2676 case TGSI_TOKEN_TYPE_INSTRUCTION
:
2677 if (!helpers_emitted
) {
2678 if (!svga_shader_emit_helpers( emit
))
2680 helpers_emitted
= TRUE
;
2682 ret
= svga_emit_instruction( emit
,
2684 &parse
.FullToken
.FullInstruction
);
2692 reset_temp_regs( emit
);
2695 /* Need to terminate the current subroutine. Note that the
2696 * hardware doesn't tolerate shaders without sub-routines
2697 * terminating with RET+END.
2699 if (!emit
->in_main_func
) {
2700 ret
= emit_instruction( emit
, inst_token( SVGA3DOP_RET
) );
2705 /* Need to terminate the whole shader:
2707 ret
= emit_instruction( emit
, inst_token( SVGA3DOP_END
) );
2713 tgsi_parse_free( &parse
);