1 /**********************************************************
2 * Copyright 2008-2009 VMware, Inc. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 **********************************************************/
27 #include "pipe/p_shader_tokens.h"
28 #include "tgsi/tgsi_dump.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/u_memory.h"
31 #include "util/u_math.h"
33 #include "svga_tgsi_emit.h"
34 #include "svga_context.h"
37 static boolean
emit_vs_postamble( struct svga_shader_emitter
*emit
);
38 static boolean
emit_ps_postamble( struct svga_shader_emitter
*emit
);
42 translate_opcode(uint opcode
)
45 case TGSI_OPCODE_ABS
: return SVGA3DOP_ABS
;
46 case TGSI_OPCODE_ADD
: return SVGA3DOP_ADD
;
47 case TGSI_OPCODE_DP2A
: return SVGA3DOP_DP2ADD
;
48 case TGSI_OPCODE_DP3
: return SVGA3DOP_DP3
;
49 case TGSI_OPCODE_DP4
: return SVGA3DOP_DP4
;
50 case TGSI_OPCODE_FRC
: return SVGA3DOP_FRC
;
51 case TGSI_OPCODE_MAD
: return SVGA3DOP_MAD
;
52 case TGSI_OPCODE_MAX
: return SVGA3DOP_MAX
;
53 case TGSI_OPCODE_MIN
: return SVGA3DOP_MIN
;
54 case TGSI_OPCODE_MOV
: return SVGA3DOP_MOV
;
55 case TGSI_OPCODE_MUL
: return SVGA3DOP_MUL
;
56 case TGSI_OPCODE_NOP
: return SVGA3DOP_NOP
;
58 assert(!"svga: unexpected opcode in translate_opcode()");
59 return SVGA3DOP_LAST_INST
;
65 translate_file(unsigned file
)
68 case TGSI_FILE_TEMPORARY
: return SVGA3DREG_TEMP
;
69 case TGSI_FILE_INPUT
: return SVGA3DREG_INPUT
;
70 case TGSI_FILE_OUTPUT
: return SVGA3DREG_OUTPUT
; /* VS3.0+ only */
71 case TGSI_FILE_IMMEDIATE
: return SVGA3DREG_CONST
;
72 case TGSI_FILE_CONSTANT
: return SVGA3DREG_CONST
;
73 case TGSI_FILE_SAMPLER
: return SVGA3DREG_SAMPLER
;
74 case TGSI_FILE_ADDRESS
: return SVGA3DREG_ADDR
;
76 assert(!"svga: unexpected register file in translate_file()");
77 return SVGA3DREG_TEMP
;
83 * Translate a TGSI destination register to an SVGA3DShaderDestToken.
84 * \param insn the TGSI instruction
85 * \param idx which TGSI dest register to translate (usually (always?) zero)
87 static SVGA3dShaderDestToken
88 translate_dst_register( struct svga_shader_emitter
*emit
,
89 const struct tgsi_full_instruction
*insn
,
92 const struct tgsi_full_dst_register
*reg
= &insn
->Dst
[idx
];
93 SVGA3dShaderDestToken dest
;
95 switch (reg
->Register
.File
) {
96 case TGSI_FILE_OUTPUT
:
97 /* Output registers encode semantic information in their name.
98 * Need to lookup a table built at decl time:
100 dest
= emit
->output_map
[reg
->Register
.Index
];
105 unsigned index
= reg
->Register
.Index
;
106 assert(index
< SVGA3D_TEMPREG_MAX
);
107 index
= MIN2(index
, SVGA3D_TEMPREG_MAX
- 1);
108 dest
= dst_register(translate_file(reg
->Register
.File
), index
);
113 if (reg
->Register
.Indirect
) {
114 debug_warning("Indirect indexing of dest registers is not supported!\n");
117 dest
.mask
= reg
->Register
.WriteMask
;
120 if (insn
->Instruction
.Saturate
)
121 dest
.dstMod
= SVGA3DDSTMOD_SATURATE
;
128 * Apply a swizzle to a src_register, returning a new src_register
129 * Ex: swizzle(SRC.ZZYY, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_X, SWIZZLE_Y)
130 * would return SRC.YYZZ
132 static struct src_register
133 swizzle(struct src_register src
,
134 unsigned x
, unsigned y
, unsigned z
, unsigned w
)
140 x
= (src
.base
.swizzle
>> (x
* 2)) & 0x3;
141 y
= (src
.base
.swizzle
>> (y
* 2)) & 0x3;
142 z
= (src
.base
.swizzle
>> (z
* 2)) & 0x3;
143 w
= (src
.base
.swizzle
>> (w
* 2)) & 0x3;
145 src
.base
.swizzle
= TRANSLATE_SWIZZLE(x
, y
, z
, w
);
152 * Apply a "scalar" swizzle to a src_register returning a new
153 * src_register where all the swizzle terms are the same.
154 * Ex: scalar(SRC.WZYX, SWIZZLE_Y) would return SRC.ZZZZ
156 static struct src_register
157 scalar(struct src_register src
, unsigned comp
)
160 return swizzle( src
, comp
, comp
, comp
, comp
);
165 svga_arl_needs_adjustment( const struct svga_shader_emitter
*emit
)
169 for (i
= 0; i
< emit
->num_arl_consts
; ++i
) {
170 if (emit
->arl_consts
[i
].arl_num
== emit
->current_arl
)
178 svga_arl_adjustment( const struct svga_shader_emitter
*emit
)
182 for (i
= 0; i
< emit
->num_arl_consts
; ++i
) {
183 if (emit
->arl_consts
[i
].arl_num
== emit
->current_arl
)
184 return emit
->arl_consts
[i
].number
;
191 * Translate a TGSI src register to a src_register.
193 static struct src_register
194 translate_src_register( const struct svga_shader_emitter
*emit
,
195 const struct tgsi_full_src_register
*reg
)
197 struct src_register src
;
199 switch (reg
->Register
.File
) {
200 case TGSI_FILE_INPUT
:
201 /* Input registers are referred to by their semantic name rather
202 * than by index. Use the mapping build up from the decls:
204 src
= emit
->input_map
[reg
->Register
.Index
];
207 case TGSI_FILE_IMMEDIATE
:
208 /* Immediates are appended after TGSI constants in the D3D
211 src
= src_register( translate_file( reg
->Register
.File
),
212 reg
->Register
.Index
+ emit
->imm_start
);
216 src
= src_register( translate_file( reg
->Register
.File
),
217 reg
->Register
.Index
);
221 /* Indirect addressing.
223 if (reg
->Register
.Indirect
) {
224 if (emit
->unit
== PIPE_SHADER_FRAGMENT
) {
225 /* Pixel shaders have only loop registers for relative
226 * addressing into inputs. Ignore the redundant address
227 * register, the contents of aL should be in sync with it.
229 if (reg
->Register
.File
== TGSI_FILE_INPUT
) {
230 src
.base
.relAddr
= 1;
231 src
.indirect
= src_token(SVGA3DREG_LOOP
, 0);
235 /* Constant buffers only.
237 if (reg
->Register
.File
== TGSI_FILE_CONSTANT
) {
238 /* we shift the offset towards the minimum */
239 if (svga_arl_needs_adjustment( emit
)) {
240 src
.base
.num
-= svga_arl_adjustment( emit
);
242 src
.base
.relAddr
= 1;
244 /* Not really sure what should go in the second token:
246 src
.indirect
= src_token( SVGA3DREG_ADDR
,
247 reg
->Indirect
.Index
);
249 src
.indirect
.swizzle
= SWIZZLE_XXXX
;
255 reg
->Register
.SwizzleX
,
256 reg
->Register
.SwizzleY
,
257 reg
->Register
.SwizzleZ
,
258 reg
->Register
.SwizzleW
);
260 /* src.mod isn't a bitfield, unfortunately:
261 * See tgsi_util_get_full_src_register_sign_mode for implementation details.
263 if (reg
->Register
.Absolute
) {
264 if (reg
->Register
.Negate
)
265 src
.base
.srcMod
= SVGA3DSRCMOD_ABSNEG
;
267 src
.base
.srcMod
= SVGA3DSRCMOD_ABS
;
270 if (reg
->Register
.Negate
)
271 src
.base
.srcMod
= SVGA3DSRCMOD_NEG
;
273 src
.base
.srcMod
= SVGA3DSRCMOD_NONE
;
281 * Get a temporary register.
282 * Note: if we exceed the temporary register limit we just use
283 * register SVGA3D_TEMPREG_MAX - 1.
285 static SVGA3dShaderDestToken
286 get_temp( struct svga_shader_emitter
*emit
)
288 int i
= emit
->nr_hw_temp
+ emit
->internal_temp_count
++;
289 if (i
>= SVGA3D_TEMPREG_MAX
) {
290 debug_warn_once("svga: Too many temporary registers used in shader\n");
291 i
= SVGA3D_TEMPREG_MAX
- 1;
293 return dst_register( SVGA3DREG_TEMP
, i
);
298 * Release a single temp. Currently only effective if it was the last
299 * allocated temp, otherwise release will be delayed until the next
300 * call to reset_temp_regs().
303 release_temp( struct svga_shader_emitter
*emit
,
304 SVGA3dShaderDestToken temp
)
306 if (temp
.num
== emit
->internal_temp_count
- 1)
307 emit
->internal_temp_count
--;
315 reset_temp_regs(struct svga_shader_emitter
*emit
)
317 emit
->internal_temp_count
= 0;
321 /** Emit bytecode for a src_register */
323 emit_src(struct svga_shader_emitter
*emit
, const struct src_register src
)
325 if (src
.base
.relAddr
) {
326 assert(src
.base
.reserved0
);
327 assert(src
.indirect
.reserved0
);
328 return (svga_shader_emit_dword( emit
, src
.base
.value
) &&
329 svga_shader_emit_dword( emit
, src
.indirect
.value
));
332 assert(src
.base
.reserved0
);
333 return svga_shader_emit_dword( emit
, src
.base
.value
);
338 /** Emit bytecode for a dst_register */
340 emit_dst(struct svga_shader_emitter
*emit
, SVGA3dShaderDestToken dest
)
342 assert(dest
.reserved0
);
344 return svga_shader_emit_dword( emit
, dest
.value
);
348 /** Emit bytecode for a 1-operand instruction */
350 emit_op1(struct svga_shader_emitter
*emit
,
351 SVGA3dShaderInstToken inst
,
352 SVGA3dShaderDestToken dest
,
353 struct src_register src0
)
355 return (emit_instruction(emit
, inst
) &&
356 emit_dst(emit
, dest
) &&
357 emit_src(emit
, src0
));
361 /** Emit bytecode for a 2-operand instruction */
363 emit_op2(struct svga_shader_emitter
*emit
,
364 SVGA3dShaderInstToken inst
,
365 SVGA3dShaderDestToken dest
,
366 struct src_register src0
,
367 struct src_register src1
)
369 return (emit_instruction(emit
, inst
) &&
370 emit_dst(emit
, dest
) &&
371 emit_src(emit
, src0
) &&
372 emit_src(emit
, src1
));
376 /** Emit bytecode for a 3-operand instruction */
378 emit_op3(struct svga_shader_emitter
*emit
,
379 SVGA3dShaderInstToken inst
,
380 SVGA3dShaderDestToken dest
,
381 struct src_register src0
,
382 struct src_register src1
,
383 struct src_register src2
)
385 return (emit_instruction(emit
, inst
) &&
386 emit_dst(emit
, dest
) &&
387 emit_src(emit
, src0
) &&
388 emit_src(emit
, src1
) &&
389 emit_src(emit
, src2
));
393 /** Emit bytecode for a 4-operand instruction */
395 emit_op4(struct svga_shader_emitter
*emit
,
396 SVGA3dShaderInstToken inst
,
397 SVGA3dShaderDestToken dest
,
398 struct src_register src0
,
399 struct src_register src1
,
400 struct src_register src2
,
401 struct src_register src3
)
403 return (emit_instruction(emit
, inst
) &&
404 emit_dst(emit
, dest
) &&
405 emit_src(emit
, src0
) &&
406 emit_src(emit
, src1
) &&
407 emit_src(emit
, src2
) &&
408 emit_src(emit
, src3
));
413 * Apply the absolute value modifier to the given src_register, returning
414 * a new src_register.
416 static struct src_register
417 absolute(struct src_register src
)
419 src
.base
.srcMod
= SVGA3DSRCMOD_ABS
;
425 * Apply the negation modifier to the given src_register, returning
426 * a new src_register.
428 static struct src_register
429 negate(struct src_register src
)
431 switch (src
.base
.srcMod
) {
432 case SVGA3DSRCMOD_ABS
:
433 src
.base
.srcMod
= SVGA3DSRCMOD_ABSNEG
;
435 case SVGA3DSRCMOD_ABSNEG
:
436 src
.base
.srcMod
= SVGA3DSRCMOD_ABS
;
438 case SVGA3DSRCMOD_NEG
:
439 src
.base
.srcMod
= SVGA3DSRCMOD_NONE
;
441 case SVGA3DSRCMOD_NONE
:
442 src
.base
.srcMod
= SVGA3DSRCMOD_NEG
;
450 /* Replace the src with the temporary specified in the dst, but copying
451 * only the necessary channels, and preserving the original swizzle (which is
452 * important given that several opcodes have constraints in the allowed
456 emit_repl(struct svga_shader_emitter
*emit
,
457 SVGA3dShaderDestToken dst
,
458 struct src_register
*src0
)
460 unsigned src0_swizzle
;
463 assert(SVGA3dShaderGetRegType(dst
.value
) == SVGA3DREG_TEMP
);
465 src0_swizzle
= src0
->base
.swizzle
;
468 for (chan
= 0; chan
< 4; ++chan
) {
469 unsigned swizzle
= (src0_swizzle
>> (chan
*2)) & 0x3;
470 dst
.mask
|= 1 << swizzle
;
474 src0
->base
.swizzle
= SVGA3DSWIZZLE_NONE
;
476 if (!emit_op1( emit
, inst_token( SVGA3DOP_MOV
), dst
, *src0
))
480 src0
->base
.swizzle
= src0_swizzle
;
487 * Submit/emit an instruction with zero operands.
490 submit_op0(struct svga_shader_emitter
*emit
,
491 SVGA3dShaderInstToken inst
,
492 SVGA3dShaderDestToken dest
)
494 return (emit_instruction( emit
, inst
) &&
495 emit_dst( emit
, dest
));
500 * Submit/emit an instruction with one operand.
503 submit_op1(struct svga_shader_emitter
*emit
,
504 SVGA3dShaderInstToken inst
,
505 SVGA3dShaderDestToken dest
,
506 struct src_register src0
)
508 return emit_op1( emit
, inst
, dest
, src0
);
513 * Submit/emit an instruction with two operands.
515 * SVGA shaders may not refer to >1 constant register in a single
516 * instruction. This function checks for that usage and inserts a
517 * move to temporary if detected.
519 * The same applies to input registers -- at most a single input
520 * register may be read by any instruction.
523 submit_op2(struct svga_shader_emitter
*emit
,
524 SVGA3dShaderInstToken inst
,
525 SVGA3dShaderDestToken dest
,
526 struct src_register src0
,
527 struct src_register src1
)
529 SVGA3dShaderDestToken temp
;
530 SVGA3dShaderRegType type0
, type1
;
531 boolean need_temp
= FALSE
;
534 type0
= SVGA3dShaderGetRegType( src0
.base
.value
);
535 type1
= SVGA3dShaderGetRegType( src1
.base
.value
);
537 if (type0
== SVGA3DREG_CONST
&&
538 type1
== SVGA3DREG_CONST
&&
539 src0
.base
.num
!= src1
.base
.num
)
542 if (type0
== SVGA3DREG_INPUT
&&
543 type1
== SVGA3DREG_INPUT
&&
544 src0
.base
.num
!= src1
.base
.num
)
548 temp
= get_temp( emit
);
550 if (!emit_repl( emit
, temp
, &src0
))
554 if (!emit_op2( emit
, inst
, dest
, src0
, src1
))
558 release_temp( emit
, temp
);
565 * Submit/emit an instruction with three operands.
567 * SVGA shaders may not refer to >1 constant register in a single
568 * instruction. This function checks for that usage and inserts a
569 * move to temporary if detected.
572 submit_op3(struct svga_shader_emitter
*emit
,
573 SVGA3dShaderInstToken inst
,
574 SVGA3dShaderDestToken dest
,
575 struct src_register src0
,
576 struct src_register src1
,
577 struct src_register src2
)
579 SVGA3dShaderDestToken temp0
;
580 SVGA3dShaderDestToken temp1
;
581 boolean need_temp0
= FALSE
;
582 boolean need_temp1
= FALSE
;
583 SVGA3dShaderRegType type0
, type1
, type2
;
587 type0
= SVGA3dShaderGetRegType( src0
.base
.value
);
588 type1
= SVGA3dShaderGetRegType( src1
.base
.value
);
589 type2
= SVGA3dShaderGetRegType( src2
.base
.value
);
591 if (inst
.op
!= SVGA3DOP_SINCOS
) {
592 if (type0
== SVGA3DREG_CONST
&&
593 ((type1
== SVGA3DREG_CONST
&& src0
.base
.num
!= src1
.base
.num
) ||
594 (type2
== SVGA3DREG_CONST
&& src0
.base
.num
!= src2
.base
.num
)))
597 if (type1
== SVGA3DREG_CONST
&&
598 (type2
== SVGA3DREG_CONST
&& src1
.base
.num
!= src2
.base
.num
))
602 if (type0
== SVGA3DREG_INPUT
&&
603 ((type1
== SVGA3DREG_INPUT
&& src0
.base
.num
!= src1
.base
.num
) ||
604 (type2
== SVGA3DREG_INPUT
&& src0
.base
.num
!= src2
.base
.num
)))
607 if (type1
== SVGA3DREG_INPUT
&&
608 (type2
== SVGA3DREG_INPUT
&& src1
.base
.num
!= src2
.base
.num
))
612 temp0
= get_temp( emit
);
614 if (!emit_repl( emit
, temp0
, &src0
))
619 temp1
= get_temp( emit
);
621 if (!emit_repl( emit
, temp1
, &src1
))
625 if (!emit_op3( emit
, inst
, dest
, src0
, src1
, src2
))
629 release_temp( emit
, temp1
);
631 release_temp( emit
, temp0
);
637 * Submit/emit an instruction with four operands.
639 * SVGA shaders may not refer to >1 constant register in a single
640 * instruction. This function checks for that usage and inserts a
641 * move to temporary if detected.
644 submit_op4(struct svga_shader_emitter
*emit
,
645 SVGA3dShaderInstToken inst
,
646 SVGA3dShaderDestToken dest
,
647 struct src_register src0
,
648 struct src_register src1
,
649 struct src_register src2
,
650 struct src_register src3
)
652 SVGA3dShaderDestToken temp0
;
653 SVGA3dShaderDestToken temp3
;
654 boolean need_temp0
= FALSE
;
655 boolean need_temp3
= FALSE
;
656 SVGA3dShaderRegType type0
, type1
, type2
, type3
;
660 type0
= SVGA3dShaderGetRegType( src0
.base
.value
);
661 type1
= SVGA3dShaderGetRegType( src1
.base
.value
);
662 type2
= SVGA3dShaderGetRegType( src2
.base
.value
);
663 type3
= SVGA3dShaderGetRegType( src2
.base
.value
);
665 /* Make life a little easier - this is only used by the TXD
666 * instruction which is guaranteed not to have a constant/input reg
667 * in one slot at least:
669 assert(type1
== SVGA3DREG_SAMPLER
);
671 if (type0
== SVGA3DREG_CONST
&&
672 ((type3
== SVGA3DREG_CONST
&& src0
.base
.num
!= src3
.base
.num
) ||
673 (type2
== SVGA3DREG_CONST
&& src0
.base
.num
!= src2
.base
.num
)))
676 if (type3
== SVGA3DREG_CONST
&&
677 (type2
== SVGA3DREG_CONST
&& src3
.base
.num
!= src2
.base
.num
))
680 if (type0
== SVGA3DREG_INPUT
&&
681 ((type3
== SVGA3DREG_INPUT
&& src0
.base
.num
!= src3
.base
.num
) ||
682 (type2
== SVGA3DREG_INPUT
&& src0
.base
.num
!= src2
.base
.num
)))
685 if (type3
== SVGA3DREG_INPUT
&&
686 (type2
== SVGA3DREG_INPUT
&& src3
.base
.num
!= src2
.base
.num
))
690 temp0
= get_temp( emit
);
692 if (!emit_repl( emit
, temp0
, &src0
))
697 temp3
= get_temp( emit
);
699 if (!emit_repl( emit
, temp3
, &src3
))
703 if (!emit_op4( emit
, inst
, dest
, src0
, src1
, src2
, src3
))
707 release_temp( emit
, temp3
);
709 release_temp( emit
, temp0
);
715 * Do the src and dest registers refer to the same register?
718 alias_src_dst(struct src_register src
,
719 SVGA3dShaderDestToken dst
)
721 if (src
.base
.num
!= dst
.num
)
724 if (SVGA3dShaderGetRegType(dst
.value
) !=
725 SVGA3dShaderGetRegType(src
.base
.value
))
733 * Helper for emitting SVGA immediate values using the SVGA3DOP_DEF[I]
737 emit_def_const(struct svga_shader_emitter
*emit
,
738 SVGA3dShaderConstType type
,
739 unsigned idx
, float a
, float b
, float c
, float d
)
742 SVGA3dShaderInstToken opcode
;
745 case SVGA3D_CONST_TYPE_FLOAT
:
746 opcode
= inst_token( SVGA3DOP_DEF
);
747 def
.dst
= dst_register( SVGA3DREG_CONST
, idx
);
748 def
.constValues
[0] = a
;
749 def
.constValues
[1] = b
;
750 def
.constValues
[2] = c
;
751 def
.constValues
[3] = d
;
753 case SVGA3D_CONST_TYPE_INT
:
754 opcode
= inst_token( SVGA3DOP_DEFI
);
755 def
.dst
= dst_register( SVGA3DREG_CONSTINT
, idx
);
756 def
.constIValues
[0] = (int)a
;
757 def
.constIValues
[1] = (int)b
;
758 def
.constIValues
[2] = (int)c
;
759 def
.constIValues
[3] = (int)d
;
763 opcode
= inst_token( SVGA3DOP_NOP
);
767 if (!emit_instruction(emit
, opcode
) ||
768 !svga_shader_emit_dwords( emit
, def
.values
, Elements(def
.values
)))
776 create_loop_const( struct svga_shader_emitter
*emit
)
778 unsigned idx
= emit
->nr_hw_int_const
++;
780 if (!emit_def_const( emit
, SVGA3D_CONST_TYPE_INT
, idx
,
781 255, /* iteration count */
782 0, /* initial value */
784 0 /* not used, must be 0 */))
787 emit
->loop_const_idx
= idx
;
788 emit
->created_loop_const
= TRUE
;
794 create_arl_consts( struct svga_shader_emitter
*emit
)
798 for (i
= 0; i
< emit
->num_arl_consts
; i
+= 4) {
800 unsigned idx
= emit
->nr_hw_float_const
++;
802 for (j
= 0; j
< 4 && (j
+ i
) < emit
->num_arl_consts
; ++j
) {
803 vals
[j
] = (float) emit
->arl_consts
[i
+ j
].number
;
804 emit
->arl_consts
[i
+ j
].idx
= idx
;
807 emit
->arl_consts
[i
+ 0].swizzle
= TGSI_SWIZZLE_X
;
810 emit
->arl_consts
[i
+ 0].swizzle
= TGSI_SWIZZLE_Y
;
813 emit
->arl_consts
[i
+ 0].swizzle
= TGSI_SWIZZLE_Z
;
816 emit
->arl_consts
[i
+ 0].swizzle
= TGSI_SWIZZLE_W
;
823 if (!emit_def_const( emit
, SVGA3D_CONST_TYPE_FLOAT
, idx
,
834 * Return the register which holds the pixel shaders front/back-
837 static struct src_register
838 get_vface( struct svga_shader_emitter
*emit
)
840 assert(emit
->emitted_vface
);
841 return src_register(SVGA3DREG_MISCTYPE
, SVGA3DMISCREG_FACE
);
846 * Create/emit a "common" constant with values {0, 0.5, -1, 1}.
847 * We can swizzle this to produce other useful constants such as
848 * {0, 0, 0, 0}, {1, 1, 1, 1}, etc.
851 create_common_immediate( struct svga_shader_emitter
*emit
)
853 unsigned idx
= emit
->nr_hw_float_const
++;
855 /* Emit the constant (0, 0.5, -1, 1) and use swizzling to generate
856 * other useful vectors.
858 if (!emit_def_const( emit
, SVGA3D_CONST_TYPE_FLOAT
,
859 idx
, 0.0f
, 0.5f
, -1.0f
, 1.0f
))
861 emit
->common_immediate_idx
[0] = idx
;
864 /* Emit constant {2, 0, 0, 0} (only the 2 is used for now) */
865 if (emit
->key
.vkey
.adjust_attrib_range
) {
866 if (!emit_def_const( emit
, SVGA3D_CONST_TYPE_FLOAT
,
867 idx
, 2.0f
, 0.0f
, 0.0f
, 0.0f
))
869 emit
->common_immediate_idx
[1] = idx
;
872 emit
->common_immediate_idx
[1] = -1;
875 emit
->created_common_immediate
= TRUE
;
882 * Return swizzle/position for the given value in the "common" immediate.
884 static inline unsigned
885 common_immediate_swizzle(float value
)
888 return TGSI_SWIZZLE_X
;
889 else if (value
== 0.5f
)
890 return TGSI_SWIZZLE_Y
;
891 else if (value
== -1.0f
)
892 return TGSI_SWIZZLE_Z
;
893 else if (value
== 1.0f
)
894 return TGSI_SWIZZLE_W
;
896 assert(!"illegal value in common_immediate_swizzle");
897 return TGSI_SWIZZLE_X
;
903 * Returns an immediate reg where all the terms are either 0, 1, 2 or 0.5
905 static struct src_register
906 get_immediate(struct svga_shader_emitter
*emit
,
907 float x
, float y
, float z
, float w
)
909 unsigned sx
= common_immediate_swizzle(x
);
910 unsigned sy
= common_immediate_swizzle(y
);
911 unsigned sz
= common_immediate_swizzle(z
);
912 unsigned sw
= common_immediate_swizzle(w
);
913 assert(emit
->created_common_immediate
);
914 assert(emit
->common_immediate_idx
[0] >= 0);
915 return swizzle(src_register(SVGA3DREG_CONST
, emit
->common_immediate_idx
[0]),
921 * returns {0, 0, 0, 0} immediate
923 static struct src_register
924 get_zero_immediate( struct svga_shader_emitter
*emit
)
926 assert(emit
->created_common_immediate
);
927 assert(emit
->common_immediate_idx
[0] >= 0);
928 return swizzle(src_register( SVGA3DREG_CONST
,
929 emit
->common_immediate_idx
[0]),
935 * returns {1, 1, 1, 1} immediate
937 static struct src_register
938 get_one_immediate( struct svga_shader_emitter
*emit
)
940 assert(emit
->created_common_immediate
);
941 assert(emit
->common_immediate_idx
[0] >= 0);
942 return swizzle(src_register( SVGA3DREG_CONST
,
943 emit
->common_immediate_idx
[0]),
949 * returns {0.5, 0.5, 0.5, 0.5} immediate
951 static struct src_register
952 get_half_immediate( struct svga_shader_emitter
*emit
)
954 assert(emit
->created_common_immediate
);
955 assert(emit
->common_immediate_idx
[0] >= 0);
956 return swizzle(src_register(SVGA3DREG_CONST
, emit
->common_immediate_idx
[0]),
962 * returns {2, 2, 2, 2} immediate
964 static struct src_register
965 get_two_immediate( struct svga_shader_emitter
*emit
)
967 /* Note we use the second common immediate here */
968 assert(emit
->created_common_immediate
);
969 assert(emit
->common_immediate_idx
[1] >= 0);
970 return swizzle(src_register( SVGA3DREG_CONST
,
971 emit
->common_immediate_idx
[1]),
977 * returns the loop const
979 static struct src_register
980 get_loop_const( struct svga_shader_emitter
*emit
)
982 assert(emit
->created_loop_const
);
983 assert(emit
->loop_const_idx
>= 0);
984 return src_register( SVGA3DREG_CONSTINT
,
985 emit
->loop_const_idx
);
989 static struct src_register
990 get_fake_arl_const( struct svga_shader_emitter
*emit
)
992 struct src_register reg
;
993 int idx
= 0, swizzle
= 0, i
;
995 for (i
= 0; i
< emit
->num_arl_consts
; ++ i
) {
996 if (emit
->arl_consts
[i
].arl_num
== emit
->current_arl
) {
997 idx
= emit
->arl_consts
[i
].idx
;
998 swizzle
= emit
->arl_consts
[i
].swizzle
;
1002 reg
= src_register( SVGA3DREG_CONST
, idx
);
1003 return scalar(reg
, swizzle
);
1008 * Return a register which holds the width and height of the texture
1009 * currently bound to the given sampler.
1011 static struct src_register
1012 get_tex_dimensions( struct svga_shader_emitter
*emit
, int sampler_num
)
1015 struct src_register reg
;
1017 /* the width/height indexes start right after constants */
1018 idx
= emit
->key
.fkey
.tex
[sampler_num
].width_height_idx
+
1019 emit
->info
.file_max
[TGSI_FILE_CONSTANT
] + 1;
1021 reg
= src_register( SVGA3DREG_CONST
, idx
);
1027 emit_fake_arl(struct svga_shader_emitter
*emit
,
1028 const struct tgsi_full_instruction
*insn
)
1030 const struct src_register src0
=
1031 translate_src_register(emit
, &insn
->Src
[0] );
1032 struct src_register src1
= get_fake_arl_const( emit
);
1033 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1034 SVGA3dShaderDestToken tmp
= get_temp( emit
);
1036 if (!submit_op1(emit
, inst_token( SVGA3DOP_MOV
), tmp
, src0
))
1039 if (!submit_op2( emit
, inst_token( SVGA3DOP_ADD
), tmp
, src( tmp
),
1043 /* replicate the original swizzle */
1045 src1
.base
.swizzle
= src0
.base
.swizzle
;
1047 return submit_op1( emit
, inst_token( SVGA3DOP_MOVA
),
1053 emit_if(struct svga_shader_emitter
*emit
,
1054 const struct tgsi_full_instruction
*insn
)
1056 struct src_register src0
=
1057 translate_src_register(emit
, &insn
->Src
[0]);
1058 struct src_register zero
= get_zero_immediate(emit
);
1059 SVGA3dShaderInstToken if_token
= inst_token( SVGA3DOP_IFC
);
1061 if_token
.control
= SVGA3DOPCOMPC_NE
;
1063 if (SVGA3dShaderGetRegType(src0
.base
.value
) == SVGA3DREG_CONST
) {
1065 * Max different constant registers readable per IFC instruction is 1.
1067 SVGA3dShaderDestToken tmp
= get_temp( emit
);
1069 if (!submit_op1(emit
, inst_token( SVGA3DOP_MOV
), tmp
, src0
))
1072 src0
= scalar(src( tmp
), TGSI_SWIZZLE_X
);
1075 emit
->dynamic_branching_level
++;
1077 return (emit_instruction( emit
, if_token
) &&
1078 emit_src( emit
, src0
) &&
1079 emit_src( emit
, zero
) );
1084 emit_else(struct svga_shader_emitter
*emit
,
1085 const struct tgsi_full_instruction
*insn
)
1087 return emit_instruction(emit
, inst_token(SVGA3DOP_ELSE
));
1092 emit_endif(struct svga_shader_emitter
*emit
,
1093 const struct tgsi_full_instruction
*insn
)
1095 emit
->dynamic_branching_level
--;
1097 return emit_instruction(emit
, inst_token(SVGA3DOP_ENDIF
));
1102 * Translate the following TGSI FLR instruction.
1104 * To the following SVGA3D instruction sequence.
1109 emit_floor(struct svga_shader_emitter
*emit
,
1110 const struct tgsi_full_instruction
*insn
)
1112 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1113 const struct src_register src0
=
1114 translate_src_register(emit
, &insn
->Src
[0] );
1115 SVGA3dShaderDestToken temp
= get_temp( emit
);
1118 if (!submit_op1( emit
, inst_token( SVGA3DOP_FRC
), temp
, src0
))
1121 /* SUB DST, SRC, TMP */
1122 if (!submit_op2( emit
, inst_token( SVGA3DOP_ADD
), dst
, src0
,
1123 negate( src( temp
) ) ))
1131 * Translate the following TGSI CEIL instruction.
1133 * To the following SVGA3D instruction sequence.
1138 emit_ceil(struct svga_shader_emitter
*emit
,
1139 const struct tgsi_full_instruction
*insn
)
1141 SVGA3dShaderDestToken dst
= translate_dst_register(emit
, insn
, 0);
1142 const struct src_register src0
=
1143 translate_src_register(emit
, &insn
->Src
[0]);
1144 SVGA3dShaderDestToken temp
= get_temp(emit
);
1147 if (!submit_op1(emit
, inst_token(SVGA3DOP_FRC
), temp
, negate(src0
)))
1150 /* ADD DST, SRC, TMP */
1151 if (!submit_op2(emit
, inst_token(SVGA3DOP_ADD
), dst
, src0
, src(temp
)))
1159 * Translate the following TGSI DIV instruction.
1160 * DIV DST.xy, SRC0, SRC1
1161 * To the following SVGA3D instruction sequence.
1162 * RCP TMP.x, SRC1.xxxx
1163 * RCP TMP.y, SRC1.yyyy
1164 * MUL DST.xy, SRC0, TMP
1167 emit_div(struct svga_shader_emitter
*emit
,
1168 const struct tgsi_full_instruction
*insn
)
1170 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1171 const struct src_register src0
=
1172 translate_src_register(emit
, &insn
->Src
[0] );
1173 const struct src_register src1
=
1174 translate_src_register(emit
, &insn
->Src
[1] );
1175 SVGA3dShaderDestToken temp
= get_temp( emit
);
1178 /* For each enabled element, perform a RCP instruction. Note that
1179 * RCP is scalar in SVGA3D:
1181 for (i
= 0; i
< 4; i
++) {
1182 unsigned channel
= 1 << i
;
1183 if (dst
.mask
& channel
) {
1184 /* RCP TMP.?, SRC1.???? */
1185 if (!submit_op1( emit
, inst_token( SVGA3DOP_RCP
),
1186 writemask(temp
, channel
),
1193 * MUL DST, SRC0, TMP
1195 if (!submit_op2( emit
, inst_token( SVGA3DOP_MUL
), dst
, src0
,
1204 * Translate the following TGSI DP2 instruction.
1205 * DP2 DST, SRC1, SRC2
1206 * To the following SVGA3D instruction sequence.
1207 * MUL TMP, SRC1, SRC2
1208 * ADD DST, TMP.xxxx, TMP.yyyy
1211 emit_dp2(struct svga_shader_emitter
*emit
,
1212 const struct tgsi_full_instruction
*insn
)
1214 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1215 const struct src_register src0
=
1216 translate_src_register(emit
, &insn
->Src
[0]);
1217 const struct src_register src1
=
1218 translate_src_register(emit
, &insn
->Src
[1]);
1219 SVGA3dShaderDestToken temp
= get_temp( emit
);
1220 struct src_register temp_src0
, temp_src1
;
1222 /* MUL TMP, SRC1, SRC2 */
1223 if (!submit_op2( emit
, inst_token( SVGA3DOP_MUL
), temp
, src0
, src1
))
1226 temp_src0
= scalar(src( temp
), TGSI_SWIZZLE_X
);
1227 temp_src1
= scalar(src( temp
), TGSI_SWIZZLE_Y
);
1229 /* ADD DST, TMP.xxxx, TMP.yyyy */
1230 if (!submit_op2( emit
, inst_token( SVGA3DOP_ADD
), dst
,
1231 temp_src0
, temp_src1
))
1239 * Translate the following TGSI DPH instruction.
1240 * DPH DST, SRC1, SRC2
1241 * To the following SVGA3D instruction sequence.
1242 * DP3 TMP, SRC1, SRC2
1243 * ADD DST, TMP, SRC2.wwww
1246 emit_dph(struct svga_shader_emitter
*emit
,
1247 const struct tgsi_full_instruction
*insn
)
1249 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1250 const struct src_register src0
= translate_src_register(
1251 emit
, &insn
->Src
[0] );
1252 struct src_register src1
=
1253 translate_src_register(emit
, &insn
->Src
[1]);
1254 SVGA3dShaderDestToken temp
= get_temp( emit
);
1256 /* DP3 TMP, SRC1, SRC2 */
1257 if (!submit_op2( emit
, inst_token( SVGA3DOP_DP3
), temp
, src0
, src1
))
1260 src1
= scalar(src1
, TGSI_SWIZZLE_W
);
1262 /* ADD DST, TMP, SRC2.wwww */
1263 if (!submit_op2( emit
, inst_token( SVGA3DOP_ADD
), dst
,
1264 src( temp
), src1
))
1272 * Sine / Cosine helper function.
1275 do_emit_sincos(struct svga_shader_emitter
*emit
,
1276 SVGA3dShaderDestToken dst
,
1277 struct src_register src0
)
1279 src0
= scalar(src0
, TGSI_SWIZZLE_X
);
1280 return submit_op1(emit
, inst_token(SVGA3DOP_SINCOS
), dst
, src0
);
1285 * Translate/emit a TGSI SIN, COS or CSC instruction.
1288 emit_sincos(struct svga_shader_emitter
*emit
,
1289 const struct tgsi_full_instruction
*insn
)
1291 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1292 struct src_register src0
= translate_src_register(emit
, &insn
->Src
[0]);
1293 SVGA3dShaderDestToken temp
= get_temp( emit
);
1296 if (!do_emit_sincos(emit
, writemask(temp
, TGSI_WRITEMASK_XY
), src0
))
1300 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), dst
, src( temp
) ))
1308 * Translate TGSI SIN instruction into:
1313 emit_sin(struct svga_shader_emitter
*emit
,
1314 const struct tgsi_full_instruction
*insn
)
1316 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1317 struct src_register src0
=
1318 translate_src_register(emit
, &insn
->Src
[0] );
1319 SVGA3dShaderDestToken temp
= get_temp( emit
);
1322 if (!do_emit_sincos(emit
, writemask(temp
, TGSI_WRITEMASK_Y
), src0
))
1325 src0
= scalar(src( temp
), TGSI_SWIZZLE_Y
);
1327 /* MOV DST TMP.yyyy */
1328 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), dst
, src0
))
1336 * Translate TGSI COS instruction into:
1341 emit_cos(struct svga_shader_emitter
*emit
,
1342 const struct tgsi_full_instruction
*insn
)
1344 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1345 struct src_register src0
=
1346 translate_src_register(emit
, &insn
->Src
[0] );
1347 SVGA3dShaderDestToken temp
= get_temp( emit
);
1350 if (!do_emit_sincos( emit
, writemask(temp
, TGSI_WRITEMASK_X
), src0
))
1353 src0
= scalar(src( temp
), TGSI_SWIZZLE_X
);
1355 /* MOV DST TMP.xxxx */
1356 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), dst
, src0
))
1364 * Translate/emit TGSI SSG (Set Sign: -1, 0, +1) instruction.
1367 emit_ssg(struct svga_shader_emitter
*emit
,
1368 const struct tgsi_full_instruction
*insn
)
1370 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1371 struct src_register src0
=
1372 translate_src_register(emit
, &insn
->Src
[0] );
1373 SVGA3dShaderDestToken temp0
= get_temp( emit
);
1374 SVGA3dShaderDestToken temp1
= get_temp( emit
);
1375 struct src_register zero
, one
;
1377 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
1378 /* SGN DST, SRC0, TMP0, TMP1 */
1379 return submit_op3( emit
, inst_token( SVGA3DOP_SGN
), dst
, src0
,
1380 src( temp0
), src( temp1
) );
1383 one
= get_one_immediate(emit
);
1384 zero
= get_zero_immediate(emit
);
1386 /* CMP TMP0, SRC0, one, zero */
1387 if (!submit_op3( emit
, inst_token( SVGA3DOP_CMP
),
1388 writemask( temp0
, dst
.mask
), src0
, one
, zero
))
1391 /* CMP TMP1, negate(SRC0), negate(one), zero */
1392 if (!submit_op3( emit
, inst_token( SVGA3DOP_CMP
),
1393 writemask( temp1
, dst
.mask
), negate( src0
), negate( one
),
1397 /* ADD DST, TMP0, TMP1 */
1398 return submit_op2( emit
, inst_token( SVGA3DOP_ADD
), dst
, src( temp0
),
1404 * Translate/emit TGSI SUB instruction as:
1405 * ADD DST, SRC0, negate(SRC1)
1408 emit_sub(struct svga_shader_emitter
*emit
,
1409 const struct tgsi_full_instruction
*insn
)
1411 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1412 struct src_register src0
= translate_src_register(
1413 emit
, &insn
->Src
[0] );
1414 struct src_register src1
= translate_src_register(
1415 emit
, &insn
->Src
[1] );
1417 src1
= negate(src1
);
1419 if (!submit_op2( emit
, inst_token( SVGA3DOP_ADD
), dst
,
1428 * Translate/emit KILL_IF instruction (kill if any of X,Y,Z,W are negative).
1431 emit_kill_if(struct svga_shader_emitter
*emit
,
1432 const struct tgsi_full_instruction
*insn
)
1434 const struct tgsi_full_src_register
*reg
= &insn
->Src
[0];
1435 struct src_register src0
, srcIn
;
1436 const boolean special
= (reg
->Register
.Absolute
||
1437 reg
->Register
.Negate
||
1438 reg
->Register
.Indirect
||
1439 reg
->Register
.SwizzleX
!= 0 ||
1440 reg
->Register
.SwizzleY
!= 1 ||
1441 reg
->Register
.SwizzleZ
!= 2 ||
1442 reg
->Register
.File
!= TGSI_FILE_TEMPORARY
);
1443 SVGA3dShaderDestToken temp
;
1445 src0
= srcIn
= translate_src_register( emit
, reg
);
1448 /* need a temp reg */
1449 temp
= get_temp( emit
);
1453 /* move the source into a temp register */
1454 submit_op1(emit
, inst_token(SVGA3DOP_MOV
), temp
, src0
);
1459 /* Do the texkill by checking if any of the XYZW components are < 0.
1460 * Note that ps_2_0 and later take XYZW in consideration, while ps_1_x
1461 * only used XYZ. The MSDN documentation about this is incorrect.
1463 if (!submit_op0( emit
, inst_token( SVGA3DOP_TEXKILL
), dst(src0
) ))
1471 * Translate/emit unconditional kill instruction (usually found inside
1472 * an IF/ELSE/ENDIF block).
1475 emit_kill(struct svga_shader_emitter
*emit
,
1476 const struct tgsi_full_instruction
*insn
)
1478 SVGA3dShaderDestToken temp
;
1479 struct src_register one
= get_one_immediate(emit
);
1480 SVGA3dShaderInstToken inst
= inst_token( SVGA3DOP_TEXKILL
);
1482 /* texkill doesn't allow negation on the operand so lets move
1483 * negation of {1} to a temp register */
1484 temp
= get_temp( emit
);
1485 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), temp
,
1489 return submit_op0( emit
, inst
, temp
);
1494 * Test if r1 and r2 are the same register.
1497 same_register(struct src_register r1
, struct src_register r2
)
1499 return (r1
.base
.num
== r2
.base
.num
&&
1500 r1
.base
.type_upper
== r2
.base
.type_upper
&&
1501 r1
.base
.type_lower
== r2
.base
.type_lower
);
1507 * Implement conditionals by initializing destination reg to 'fail',
1508 * then set predicate reg with UFOP_SETP, then move 'pass' to dest
1509 * based on predicate reg.
1511 * SETP src0, cmp, src1 -- do this first to avoid aliasing problems.
1516 emit_conditional(struct svga_shader_emitter
*emit
,
1517 unsigned compare_func
,
1518 SVGA3dShaderDestToken dst
,
1519 struct src_register src0
,
1520 struct src_register src1
,
1521 struct src_register pass
,
1522 struct src_register fail
)
1524 SVGA3dShaderDestToken pred_reg
= dst_register( SVGA3DREG_PREDICATE
, 0 );
1525 SVGA3dShaderInstToken setp_token
;
1527 switch (compare_func
) {
1528 case PIPE_FUNC_NEVER
:
1529 return submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
1532 case PIPE_FUNC_LESS
:
1533 setp_token
= inst_token_setp(SVGA3DOPCOMP_LT
);
1535 case PIPE_FUNC_EQUAL
:
1536 setp_token
= inst_token_setp(SVGA3DOPCOMP_EQ
);
1538 case PIPE_FUNC_LEQUAL
:
1539 setp_token
= inst_token_setp(SVGA3DOPCOMP_LE
);
1541 case PIPE_FUNC_GREATER
:
1542 setp_token
= inst_token_setp(SVGA3DOPCOMP_GT
);
1544 case PIPE_FUNC_NOTEQUAL
:
1545 setp_token
= inst_token_setp(SVGA3DOPCOMPC_NE
);
1547 case PIPE_FUNC_GEQUAL
:
1548 setp_token
= inst_token_setp(SVGA3DOPCOMP_GE
);
1550 case PIPE_FUNC_ALWAYS
:
1551 return submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
1556 if (same_register(src(dst
), pass
)) {
1557 /* We'll get bad results if the dst and pass registers are the same
1558 * so use a temp register containing pass.
1560 SVGA3dShaderDestToken temp
= get_temp(emit
);
1561 if (!submit_op1(emit
, inst_token(SVGA3DOP_MOV
), temp
, pass
))
1566 /* SETP src0, COMPOP, src1 */
1567 if (!submit_op2( emit
, setp_token
, pred_reg
,
1572 if (!submit_op1(emit
, inst_token(SVGA3DOP_MOV
), dst
, fail
))
1575 /* MOV dst, pass (predicated)
1577 * Note that the predicate reg (and possible modifiers) is passed
1578 * as the first source argument.
1580 if (!submit_op2(emit
,
1581 inst_token_predicated(SVGA3DOP_MOV
), dst
,
1582 src(pred_reg
), pass
))
1590 * Helper for emiting 'selection' commands. Basically:
1597 emit_select(struct svga_shader_emitter
*emit
,
1598 unsigned compare_func
,
1599 SVGA3dShaderDestToken dst
,
1600 struct src_register src0
,
1601 struct src_register src1
)
1603 /* There are some SVGA instructions which implement some selects
1604 * directly, but they are only available in the vertex shader.
1606 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
1607 switch (compare_func
) {
1608 case PIPE_FUNC_GEQUAL
:
1609 return submit_op2( emit
, inst_token( SVGA3DOP_SGE
), dst
, src0
, src1
);
1610 case PIPE_FUNC_LEQUAL
:
1611 return submit_op2( emit
, inst_token( SVGA3DOP_SGE
), dst
, src1
, src0
);
1612 case PIPE_FUNC_GREATER
:
1613 return submit_op2( emit
, inst_token( SVGA3DOP_SLT
), dst
, src1
, src0
);
1614 case PIPE_FUNC_LESS
:
1615 return submit_op2( emit
, inst_token( SVGA3DOP_SLT
), dst
, src0
, src1
);
1621 /* Otherwise, need to use the setp approach:
1624 struct src_register one
, zero
;
1625 /* zero immediate is 0,0,0,1 */
1626 zero
= get_zero_immediate(emit
);
1627 one
= get_one_immediate(emit
);
1629 return emit_conditional(emit
, compare_func
, dst
, src0
, src1
, one
, zero
);
1635 * Translate/emit a TGSI SEQ, SNE, SLT, SGE, etc. instruction.
1638 emit_select_op(struct svga_shader_emitter
*emit
,
1640 const struct tgsi_full_instruction
*insn
)
1642 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1643 struct src_register src0
= translate_src_register(
1644 emit
, &insn
->Src
[0] );
1645 struct src_register src1
= translate_src_register(
1646 emit
, &insn
->Src
[1] );
1648 return emit_select( emit
, compare
, dst
, src0
, src1
);
1653 * Translate TGSI CMP instruction. Component-wise:
1654 * dst = (src0 < 0.0) ? src1 : src2
1657 emit_cmp(struct svga_shader_emitter
*emit
,
1658 const struct tgsi_full_instruction
*insn
)
1660 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1661 const struct src_register src0
=
1662 translate_src_register(emit
, &insn
->Src
[0] );
1663 const struct src_register src1
=
1664 translate_src_register(emit
, &insn
->Src
[1] );
1665 const struct src_register src2
=
1666 translate_src_register(emit
, &insn
->Src
[2] );
1668 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
1669 struct src_register zero
= get_zero_immediate(emit
);
1670 /* We used to simulate CMP with SLT+LRP. But that didn't work when
1671 * src1 or src2 was Inf/NaN. In particular, GLSL sqrt(0) failed
1672 * because it involves a CMP to handle the 0 case.
1673 * Use a conditional expression instead.
1675 return emit_conditional(emit
, PIPE_FUNC_LESS
, dst
,
1676 src0
, zero
, src1
, src2
);
1679 assert(emit
->unit
== PIPE_SHADER_FRAGMENT
);
1681 /* CMP DST, SRC0, SRC2, SRC1 */
1682 return submit_op3( emit
, inst_token( SVGA3DOP_CMP
), dst
,
1689 * Translate/emit 2-operand (coord, sampler) texture instructions.
1692 emit_tex2(struct svga_shader_emitter
*emit
,
1693 const struct tgsi_full_instruction
*insn
,
1694 SVGA3dShaderDestToken dst
)
1696 SVGA3dShaderInstToken inst
;
1697 struct src_register texcoord
;
1698 struct src_register sampler
;
1699 SVGA3dShaderDestToken tmp
;
1703 switch (insn
->Instruction
.Opcode
) {
1704 case TGSI_OPCODE_TEX
:
1705 inst
.op
= SVGA3DOP_TEX
;
1707 case TGSI_OPCODE_TXP
:
1708 inst
.op
= SVGA3DOP_TEX
;
1709 inst
.control
= SVGA3DOPCONT_PROJECT
;
1711 case TGSI_OPCODE_TXB
:
1712 inst
.op
= SVGA3DOP_TEX
;
1713 inst
.control
= SVGA3DOPCONT_BIAS
;
1715 case TGSI_OPCODE_TXL
:
1716 inst
.op
= SVGA3DOP_TEXLDL
;
1723 texcoord
= translate_src_register( emit
, &insn
->Src
[0] );
1724 sampler
= translate_src_register( emit
, &insn
->Src
[1] );
1726 if (emit
->key
.fkey
.tex
[sampler
.base
.num
].unnormalized
||
1727 emit
->dynamic_branching_level
> 0)
1728 tmp
= get_temp( emit
);
1730 /* Can't do mipmapping inside dynamic branch constructs. Force LOD
1731 * zero in that case.
1733 if (emit
->dynamic_branching_level
> 0 &&
1734 inst
.op
== SVGA3DOP_TEX
&&
1735 SVGA3dShaderGetRegType(texcoord
.base
.value
) == SVGA3DREG_TEMP
) {
1736 struct src_register zero
= get_zero_immediate(emit
);
1738 /* MOV tmp, texcoord */
1739 if (!submit_op1( emit
,
1740 inst_token( SVGA3DOP_MOV
),
1745 /* MOV tmp.w, zero */
1746 if (!submit_op1( emit
,
1747 inst_token( SVGA3DOP_MOV
),
1748 writemask( tmp
, TGSI_WRITEMASK_W
),
1752 texcoord
= src( tmp
);
1753 inst
.op
= SVGA3DOP_TEXLDL
;
1756 /* Explicit normalization of texcoords:
1758 if (emit
->key
.fkey
.tex
[sampler
.base
.num
].unnormalized
) {
1759 struct src_register wh
= get_tex_dimensions( emit
, sampler
.base
.num
);
1761 /* MUL tmp, SRC0, WH */
1762 if (!submit_op2( emit
, inst_token( SVGA3DOP_MUL
),
1763 tmp
, texcoord
, wh
))
1766 texcoord
= src( tmp
);
1769 return submit_op2( emit
, inst
, dst
, texcoord
, sampler
);
1774 * Translate/emit 4-operand (coord, ddx, ddy, sampler) texture instructions.
1777 emit_tex4(struct svga_shader_emitter
*emit
,
1778 const struct tgsi_full_instruction
*insn
,
1779 SVGA3dShaderDestToken dst
)
1781 SVGA3dShaderInstToken inst
;
1782 struct src_register texcoord
;
1783 struct src_register ddx
;
1784 struct src_register ddy
;
1785 struct src_register sampler
;
1787 texcoord
= translate_src_register( emit
, &insn
->Src
[0] );
1788 ddx
= translate_src_register( emit
, &insn
->Src
[1] );
1789 ddy
= translate_src_register( emit
, &insn
->Src
[2] );
1790 sampler
= translate_src_register( emit
, &insn
->Src
[3] );
1794 switch (insn
->Instruction
.Opcode
) {
1795 case TGSI_OPCODE_TXD
:
1796 inst
.op
= SVGA3DOP_TEXLDD
; /* 4 args! */
1803 return submit_op4( emit
, inst
, dst
, texcoord
, sampler
, ddx
, ddy
);
1808 * Emit texture swizzle code. We do this here since SVGA samplers don't
1809 * directly support swizzles.
1812 emit_tex_swizzle(struct svga_shader_emitter
*emit
,
1813 SVGA3dShaderDestToken dst
,
1814 struct src_register src
,
1820 const unsigned swizzleIn
[4] = {swizzle_x
, swizzle_y
, swizzle_z
, swizzle_w
};
1821 unsigned srcSwizzle
[4];
1822 unsigned srcWritemask
= 0x0, zeroWritemask
= 0x0, oneWritemask
= 0x0;
1825 /* build writemasks and srcSwizzle terms */
1826 for (i
= 0; i
< 4; i
++) {
1827 if (swizzleIn
[i
] == PIPE_SWIZZLE_ZERO
) {
1828 srcSwizzle
[i
] = TGSI_SWIZZLE_X
+ i
;
1829 zeroWritemask
|= (1 << i
);
1831 else if (swizzleIn
[i
] == PIPE_SWIZZLE_ONE
) {
1832 srcSwizzle
[i
] = TGSI_SWIZZLE_X
+ i
;
1833 oneWritemask
|= (1 << i
);
1836 srcSwizzle
[i
] = swizzleIn
[i
];
1837 srcWritemask
|= (1 << i
);
1841 /* write x/y/z/w comps */
1842 if (dst
.mask
& srcWritemask
) {
1843 if (!submit_op1(emit
,
1844 inst_token(SVGA3DOP_MOV
),
1845 writemask(dst
, srcWritemask
),
1855 if (dst
.mask
& zeroWritemask
) {
1856 if (!submit_op1(emit
,
1857 inst_token(SVGA3DOP_MOV
),
1858 writemask(dst
, zeroWritemask
),
1859 get_zero_immediate(emit
)))
1864 if (dst
.mask
& oneWritemask
) {
1865 if (!submit_op1(emit
,
1866 inst_token(SVGA3DOP_MOV
),
1867 writemask(dst
, oneWritemask
),
1868 get_one_immediate(emit
)))
1877 * Translate/emit a TGSI texture sample instruction.
1880 emit_tex(struct svga_shader_emitter
*emit
,
1881 const struct tgsi_full_instruction
*insn
)
1883 SVGA3dShaderDestToken dst
=
1884 translate_dst_register( emit
, insn
, 0 );
1885 struct src_register src0
=
1886 translate_src_register( emit
, &insn
->Src
[0] );
1887 struct src_register src1
=
1888 translate_src_register( emit
, &insn
->Src
[1] );
1890 SVGA3dShaderDestToken tex_result
;
1891 const unsigned unit
= src1
.base
.num
;
1893 /* check for shadow samplers */
1894 boolean compare
= (emit
->key
.fkey
.tex
[unit
].compare_mode
==
1895 PIPE_TEX_COMPARE_R_TO_TEXTURE
);
1897 /* texture swizzle */
1898 boolean swizzle
= (emit
->key
.fkey
.tex
[unit
].swizzle_r
!= PIPE_SWIZZLE_RED
||
1899 emit
->key
.fkey
.tex
[unit
].swizzle_g
!= PIPE_SWIZZLE_GREEN
||
1900 emit
->key
.fkey
.tex
[unit
].swizzle_b
!= PIPE_SWIZZLE_BLUE
||
1901 emit
->key
.fkey
.tex
[unit
].swizzle_a
!= PIPE_SWIZZLE_ALPHA
);
1903 boolean saturate
= insn
->Instruction
.Saturate
;
1905 /* If doing compare processing or tex swizzle or saturation, we need to put
1906 * the fetched color into a temporary so it can be used as a source later on.
1908 if (compare
|| swizzle
|| saturate
) {
1909 tex_result
= get_temp( emit
);
1915 switch(insn
->Instruction
.Opcode
) {
1916 case TGSI_OPCODE_TEX
:
1917 case TGSI_OPCODE_TXB
:
1918 case TGSI_OPCODE_TXP
:
1919 case TGSI_OPCODE_TXL
:
1920 if (!emit_tex2( emit
, insn
, tex_result
))
1923 case TGSI_OPCODE_TXD
:
1924 if (!emit_tex4( emit
, insn
, tex_result
))
1932 SVGA3dShaderDestToken dst2
;
1934 if (swizzle
|| saturate
)
1939 if (dst
.mask
& TGSI_WRITEMASK_XYZ
) {
1940 SVGA3dShaderDestToken src0_zdivw
= get_temp( emit
);
1941 /* When sampling a depth texture, the result of the comparison is in
1944 struct src_register tex_src_x
= scalar(src(tex_result
), TGSI_SWIZZLE_Y
);
1945 struct src_register r_coord
;
1947 if (insn
->Instruction
.Opcode
== TGSI_OPCODE_TXP
) {
1948 /* Divide texcoord R by Q */
1949 if (!submit_op1( emit
, inst_token( SVGA3DOP_RCP
),
1950 writemask(src0_zdivw
, TGSI_WRITEMASK_X
),
1951 scalar(src0
, TGSI_SWIZZLE_W
) ))
1954 if (!submit_op2( emit
, inst_token( SVGA3DOP_MUL
),
1955 writemask(src0_zdivw
, TGSI_WRITEMASK_X
),
1956 scalar(src0
, TGSI_SWIZZLE_Z
),
1957 scalar(src(src0_zdivw
), TGSI_SWIZZLE_X
) ))
1960 r_coord
= scalar(src(src0_zdivw
), TGSI_SWIZZLE_X
);
1963 r_coord
= scalar(src0
, TGSI_SWIZZLE_Z
);
1966 /* Compare texture sample value against R component of texcoord */
1967 if (!emit_select(emit
,
1968 emit
->key
.fkey
.tex
[unit
].compare_func
,
1969 writemask( dst2
, TGSI_WRITEMASK_XYZ
),
1975 if (dst
.mask
& TGSI_WRITEMASK_W
) {
1976 struct src_register one
= get_one_immediate(emit
);
1978 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
1979 writemask( dst2
, TGSI_WRITEMASK_W
),
1985 if (saturate
&& !swizzle
) {
1986 /* MOV_SAT real_dst, dst */
1987 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), dst
, src(tex_result
) ))
1991 /* swizzle from tex_result to dst (handles saturation too, if any) */
1992 emit_tex_swizzle(emit
,
1993 dst
, src(tex_result
),
1994 emit
->key
.fkey
.tex
[unit
].swizzle_r
,
1995 emit
->key
.fkey
.tex
[unit
].swizzle_g
,
1996 emit
->key
.fkey
.tex
[unit
].swizzle_b
,
1997 emit
->key
.fkey
.tex
[unit
].swizzle_a
);
2005 emit_bgnloop(struct svga_shader_emitter
*emit
,
2006 const struct tgsi_full_instruction
*insn
)
2008 SVGA3dShaderInstToken inst
= inst_token( SVGA3DOP_LOOP
);
2009 struct src_register loop_reg
= src_register( SVGA3DREG_LOOP
, 0 );
2010 struct src_register const_int
= get_loop_const( emit
);
2012 emit
->dynamic_branching_level
++;
2014 return (emit_instruction( emit
, inst
) &&
2015 emit_src( emit
, loop_reg
) &&
2016 emit_src( emit
, const_int
) );
2021 emit_endloop(struct svga_shader_emitter
*emit
,
2022 const struct tgsi_full_instruction
*insn
)
2024 SVGA3dShaderInstToken inst
= inst_token( SVGA3DOP_ENDLOOP
);
2026 emit
->dynamic_branching_level
--;
2028 return emit_instruction( emit
, inst
);
2033 * Translate/emit TGSI BREAK (out of loop) instruction.
2036 emit_brk(struct svga_shader_emitter
*emit
,
2037 const struct tgsi_full_instruction
*insn
)
2039 SVGA3dShaderInstToken inst
= inst_token( SVGA3DOP_BREAK
);
2040 return emit_instruction( emit
, inst
);
2045 * Emit simple instruction which operates on one scalar value (not
2046 * a vector). Ex: LG2, RCP, RSQ.
2049 emit_scalar_op1(struct svga_shader_emitter
*emit
,
2051 const struct tgsi_full_instruction
*insn
)
2053 SVGA3dShaderInstToken inst
;
2054 SVGA3dShaderDestToken dst
;
2055 struct src_register src
;
2057 inst
= inst_token( opcode
);
2058 dst
= translate_dst_register( emit
, insn
, 0 );
2059 src
= translate_src_register( emit
, &insn
->Src
[0] );
2060 src
= scalar( src
, TGSI_SWIZZLE_X
);
2062 return submit_op1( emit
, inst
, dst
, src
);
2067 * Translate/emit a simple instruction (one which has no special-case
2068 * code) such as ADD, MUL, MIN, MAX.
2071 emit_simple_instruction(struct svga_shader_emitter
*emit
,
2073 const struct tgsi_full_instruction
*insn
)
2075 const struct tgsi_full_src_register
*src
= insn
->Src
;
2076 SVGA3dShaderInstToken inst
;
2077 SVGA3dShaderDestToken dst
;
2079 inst
= inst_token( opcode
);
2080 dst
= translate_dst_register( emit
, insn
, 0 );
2082 switch (insn
->Instruction
.NumSrcRegs
) {
2084 return submit_op0( emit
, inst
, dst
);
2086 return submit_op1( emit
, inst
, dst
,
2087 translate_src_register( emit
, &src
[0] ));
2089 return submit_op2( emit
, inst
, dst
,
2090 translate_src_register( emit
, &src
[0] ),
2091 translate_src_register( emit
, &src
[1] ) );
2093 return submit_op3( emit
, inst
, dst
,
2094 translate_src_register( emit
, &src
[0] ),
2095 translate_src_register( emit
, &src
[1] ),
2096 translate_src_register( emit
, &src
[2] ) );
2105 * Translate/emit TGSI DDX, DDY instructions.
2108 emit_deriv(struct svga_shader_emitter
*emit
,
2109 const struct tgsi_full_instruction
*insn
)
2111 if (emit
->dynamic_branching_level
> 0 &&
2112 insn
->Src
[0].Register
.File
== TGSI_FILE_TEMPORARY
)
2114 SVGA3dShaderDestToken dst
=
2115 translate_dst_register( emit
, insn
, 0 );
2117 /* Deriv opcodes not valid inside dynamic branching, workaround
2118 * by zeroing out the destination.
2120 if (!submit_op1(emit
,
2121 inst_token( SVGA3DOP_MOV
),
2123 get_zero_immediate(emit
)))
2130 const struct tgsi_full_src_register
*reg
= &insn
->Src
[0];
2131 SVGA3dShaderInstToken inst
;
2132 SVGA3dShaderDestToken dst
;
2133 struct src_register src0
;
2135 switch (insn
->Instruction
.Opcode
) {
2136 case TGSI_OPCODE_DDX
:
2137 opcode
= SVGA3DOP_DSX
;
2139 case TGSI_OPCODE_DDY
:
2140 opcode
= SVGA3DOP_DSY
;
2146 inst
= inst_token( opcode
);
2147 dst
= translate_dst_register( emit
, insn
, 0 );
2148 src0
= translate_src_register( emit
, reg
);
2150 /* We cannot use negate or abs on source to dsx/dsy instruction.
2152 if (reg
->Register
.Absolute
||
2153 reg
->Register
.Negate
) {
2154 SVGA3dShaderDestToken temp
= get_temp( emit
);
2156 if (!emit_repl( emit
, temp
, &src0
))
2160 return submit_op1( emit
, inst
, dst
, src0
);
2166 * Translate/emit ARL (Address Register Load) instruction. Used to
2167 * move a value into the special 'address' register. Used to implement
2168 * indirect/variable indexing into arrays.
2171 emit_arl(struct svga_shader_emitter
*emit
,
2172 const struct tgsi_full_instruction
*insn
)
2174 ++emit
->current_arl
;
2175 if (emit
->unit
== PIPE_SHADER_FRAGMENT
) {
2176 /* MOVA not present in pixel shader instruction set.
2177 * Ignore this instruction altogether since it is
2178 * only used for loop counters -- and for that
2179 * we reference aL directly.
2183 if (svga_arl_needs_adjustment( emit
)) {
2184 return emit_fake_arl( emit
, insn
);
2186 /* no need to adjust, just emit straight arl */
2187 return emit_simple_instruction(emit
, SVGA3DOP_MOVA
, insn
);
2193 emit_pow(struct svga_shader_emitter
*emit
,
2194 const struct tgsi_full_instruction
*insn
)
2196 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
2197 struct src_register src0
= translate_src_register(
2198 emit
, &insn
->Src
[0] );
2199 struct src_register src1
= translate_src_register(
2200 emit
, &insn
->Src
[1] );
2201 boolean need_tmp
= FALSE
;
2203 /* POW can only output to a temporary */
2204 if (insn
->Dst
[0].Register
.File
!= TGSI_FILE_TEMPORARY
)
2207 /* POW src1 must not be the same register as dst */
2208 if (alias_src_dst( src1
, dst
))
2211 /* it's a scalar op */
2212 src0
= scalar( src0
, TGSI_SWIZZLE_X
);
2213 src1
= scalar( src1
, TGSI_SWIZZLE_X
);
2216 SVGA3dShaderDestToken tmp
=
2217 writemask(get_temp( emit
), TGSI_WRITEMASK_X
);
2219 if (!submit_op2(emit
, inst_token( SVGA3DOP_POW
), tmp
, src0
, src1
))
2222 return submit_op1(emit
, inst_token( SVGA3DOP_MOV
),
2223 dst
, scalar(src(tmp
), 0) );
2226 return submit_op2(emit
, inst_token( SVGA3DOP_POW
), dst
, src0
, src1
);
2232 * Translate/emit TGSI XPD (vector cross product) instruction.
2235 emit_xpd(struct svga_shader_emitter
*emit
,
2236 const struct tgsi_full_instruction
*insn
)
2238 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
2239 const struct src_register src0
= translate_src_register(
2240 emit
, &insn
->Src
[0] );
2241 const struct src_register src1
= translate_src_register(
2242 emit
, &insn
->Src
[1] );
2243 boolean need_dst_tmp
= FALSE
;
2245 /* XPD can only output to a temporary */
2246 if (SVGA3dShaderGetRegType(dst
.value
) != SVGA3DREG_TEMP
)
2247 need_dst_tmp
= TRUE
;
2249 /* The dst reg must not be the same as src0 or src1*/
2250 if (alias_src_dst(src0
, dst
) ||
2251 alias_src_dst(src1
, dst
))
2252 need_dst_tmp
= TRUE
;
2255 SVGA3dShaderDestToken tmp
= get_temp( emit
);
2257 /* Obey DX9 restrictions on mask:
2259 tmp
.mask
= dst
.mask
& TGSI_WRITEMASK_XYZ
;
2261 if (!submit_op2(emit
, inst_token( SVGA3DOP_CRS
), tmp
, src0
, src1
))
2264 if (!submit_op1(emit
, inst_token( SVGA3DOP_MOV
), dst
, src( tmp
)))
2268 if (!submit_op2(emit
, inst_token( SVGA3DOP_CRS
), dst
, src0
, src1
))
2272 /* Need to emit 1.0 to dst.w?
2274 if (dst
.mask
& TGSI_WRITEMASK_W
) {
2275 struct src_register one
= get_one_immediate( emit
);
2277 if (!submit_op1(emit
,
2278 inst_token( SVGA3DOP_MOV
),
2279 writemask(dst
, TGSI_WRITEMASK_W
),
2289 * Emit a LRP (linear interpolation) instruction.
2292 submit_lrp(struct svga_shader_emitter
*emit
,
2293 SVGA3dShaderDestToken dst
,
2294 struct src_register src0
,
2295 struct src_register src1
,
2296 struct src_register src2
)
2298 SVGA3dShaderDestToken tmp
;
2299 boolean need_dst_tmp
= FALSE
;
2301 /* The dst reg must be a temporary, and not be the same as src0 or src2 */
2302 if (SVGA3dShaderGetRegType(dst
.value
) != SVGA3DREG_TEMP
||
2303 alias_src_dst(src0
, dst
) ||
2304 alias_src_dst(src2
, dst
))
2305 need_dst_tmp
= TRUE
;
2308 tmp
= get_temp( emit
);
2309 tmp
.mask
= dst
.mask
;
2315 if (!submit_op3(emit
, inst_token( SVGA3DOP_LRP
), tmp
, src0
, src1
, src2
))
2319 if (!submit_op1(emit
, inst_token( SVGA3DOP_MOV
), dst
, src( tmp
)))
2328 * Translate/emit LRP (Linear Interpolation) instruction.
2331 emit_lrp(struct svga_shader_emitter
*emit
,
2332 const struct tgsi_full_instruction
*insn
)
2334 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
2335 const struct src_register src0
= translate_src_register(
2336 emit
, &insn
->Src
[0] );
2337 const struct src_register src1
= translate_src_register(
2338 emit
, &insn
->Src
[1] );
2339 const struct src_register src2
= translate_src_register(
2340 emit
, &insn
->Src
[2] );
2342 return submit_lrp(emit
, dst
, src0
, src1
, src2
);
2346 * Translate/emit DST (Distance function) instruction.
2349 emit_dst_insn(struct svga_shader_emitter
*emit
,
2350 const struct tgsi_full_instruction
*insn
)
2352 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
2353 /* SVGA/DX9 has a DST instruction, but only for vertex shaders:
2355 return emit_simple_instruction(emit
, SVGA3DOP_DST
, insn
);
2358 /* result[0] = 1 * 1;
2359 * result[1] = a[1] * b[1];
2360 * result[2] = a[2] * 1;
2361 * result[3] = 1 * b[3];
2363 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
2364 SVGA3dShaderDestToken tmp
;
2365 const struct src_register src0
= translate_src_register(
2366 emit
, &insn
->Src
[0] );
2367 const struct src_register src1
= translate_src_register(
2368 emit
, &insn
->Src
[1] );
2369 boolean need_tmp
= FALSE
;
2371 if (SVGA3dShaderGetRegType(dst
.value
) != SVGA3DREG_TEMP
||
2372 alias_src_dst(src0
, dst
) ||
2373 alias_src_dst(src1
, dst
))
2377 tmp
= get_temp( emit
);
2385 if (tmp
.mask
& TGSI_WRITEMASK_XW
) {
2386 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
2387 writemask(tmp
, TGSI_WRITEMASK_XW
),
2388 get_one_immediate(emit
)))
2394 if (tmp
.mask
& TGSI_WRITEMASK_YZ
) {
2395 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
2396 writemask(tmp
, TGSI_WRITEMASK_YZ
),
2401 /* tmp.yw = tmp * src1
2403 if (tmp
.mask
& TGSI_WRITEMASK_YW
) {
2404 if (!submit_op2( emit
, inst_token( SVGA3DOP_MUL
),
2405 writemask(tmp
, TGSI_WRITEMASK_YW
),
2414 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
2426 emit_exp(struct svga_shader_emitter
*emit
,
2427 const struct tgsi_full_instruction
*insn
)
2429 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
2430 struct src_register src0
=
2431 translate_src_register( emit
, &insn
->Src
[0] );
2432 SVGA3dShaderDestToken fraction
;
2434 if (dst
.mask
& TGSI_WRITEMASK_Y
)
2436 else if (dst
.mask
& TGSI_WRITEMASK_X
)
2437 fraction
= get_temp( emit
);
2441 /* If y is being written, fill it with src0 - floor(src0).
2443 if (dst
.mask
& TGSI_WRITEMASK_XY
) {
2444 if (!submit_op1( emit
, inst_token( SVGA3DOP_FRC
),
2445 writemask( fraction
, TGSI_WRITEMASK_Y
),
2450 /* If x is being written, fill it with 2 ^ floor(src0).
2452 if (dst
.mask
& TGSI_WRITEMASK_X
) {
2453 if (!submit_op2( emit
, inst_token( SVGA3DOP_ADD
),
2454 writemask( dst
, TGSI_WRITEMASK_X
),
2456 scalar( negate( src( fraction
) ), TGSI_SWIZZLE_Y
) ) )
2459 if (!submit_op1( emit
, inst_token( SVGA3DOP_EXP
),
2460 writemask( dst
, TGSI_WRITEMASK_X
),
2461 scalar( src( dst
), TGSI_SWIZZLE_X
) ) )
2464 if (!(dst
.mask
& TGSI_WRITEMASK_Y
))
2465 release_temp( emit
, fraction
);
2468 /* If z is being written, fill it with 2 ^ src0 (partial precision).
2470 if (dst
.mask
& TGSI_WRITEMASK_Z
) {
2471 if (!submit_op1( emit
, inst_token( SVGA3DOP_EXPP
),
2472 writemask( dst
, TGSI_WRITEMASK_Z
),
2477 /* If w is being written, fill it with one.
2479 if (dst
.mask
& TGSI_WRITEMASK_W
) {
2480 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
2481 writemask(dst
, TGSI_WRITEMASK_W
),
2482 get_one_immediate(emit
)))
2491 * Translate/emit LIT (Lighting helper) instruction.
2494 emit_lit(struct svga_shader_emitter
*emit
,
2495 const struct tgsi_full_instruction
*insn
)
2497 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
2498 /* SVGA/DX9 has a LIT instruction, but only for vertex shaders:
2500 return emit_simple_instruction(emit
, SVGA3DOP_LIT
, insn
);
2503 /* D3D vs. GL semantics can be fairly easily accomodated by
2504 * variations on this sequence.
2508 * tmp.z = pow(src.y,src.w)
2509 * p0 = src0.xxxx > 0
2510 * result = zero.wxxw
2511 * (p0) result.yz = tmp
2515 * tmp.z = pow(src.y,src.w)
2516 * p0 = src0.xxyy > 0
2517 * result = zero.wxxw
2518 * (p0) result.yz = tmp
2520 * Will implement the GL version for now.
2522 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
2523 SVGA3dShaderDestToken tmp
= get_temp( emit
);
2524 const struct src_register src0
= translate_src_register(
2525 emit
, &insn
->Src
[0] );
2527 /* tmp = pow(src.y, src.w)
2529 if (dst
.mask
& TGSI_WRITEMASK_Z
) {
2530 if (!submit_op2(emit
, inst_token( SVGA3DOP_POW
),
2539 if (dst
.mask
& TGSI_WRITEMASK_Y
) {
2540 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
2541 writemask(tmp
, TGSI_WRITEMASK_Y
),
2546 /* Can't quite do this with emit conditional due to the extra
2547 * writemask on the predicated mov:
2550 SVGA3dShaderDestToken pred_reg
= dst_register( SVGA3DREG_PREDICATE
, 0 );
2551 struct src_register predsrc
;
2553 /* D3D vs GL semantics:
2556 predsrc
= swizzle(src0
, 0, 0, 1, 1); /* D3D */
2558 predsrc
= swizzle(src0
, 0, 0, 0, 0); /* GL */
2560 /* SETP src0.xxyy, GT, {0}.x */
2561 if (!submit_op2( emit
,
2562 inst_token_setp(SVGA3DOPCOMP_GT
),
2565 get_zero_immediate(emit
)))
2569 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), dst
,
2570 get_immediate(emit
, 1.0f
, 0.0f
, 0.0f
, 1.0f
)))
2573 /* MOV dst.yz, tmp (predicated)
2575 * Note that the predicate reg (and possible modifiers) is passed
2576 * as the first source argument.
2578 if (dst
.mask
& TGSI_WRITEMASK_YZ
) {
2579 if (!submit_op2( emit
,
2580 inst_token_predicated(SVGA3DOP_MOV
),
2581 writemask(dst
, TGSI_WRITEMASK_YZ
),
2582 src( pred_reg
), src( tmp
) ))
2593 emit_ex2(struct svga_shader_emitter
*emit
,
2594 const struct tgsi_full_instruction
*insn
)
2596 SVGA3dShaderInstToken inst
;
2597 SVGA3dShaderDestToken dst
;
2598 struct src_register src0
;
2600 inst
= inst_token( SVGA3DOP_EXP
);
2601 dst
= translate_dst_register( emit
, insn
, 0 );
2602 src0
= translate_src_register( emit
, &insn
->Src
[0] );
2603 src0
= scalar( src0
, TGSI_SWIZZLE_X
);
2605 if (dst
.mask
!= TGSI_WRITEMASK_XYZW
) {
2606 SVGA3dShaderDestToken tmp
= get_temp( emit
);
2608 if (!submit_op1( emit
, inst
, tmp
, src0
))
2611 return submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
2613 scalar( src( tmp
), TGSI_SWIZZLE_X
) );
2616 return submit_op1( emit
, inst
, dst
, src0
);
2621 emit_log(struct svga_shader_emitter
*emit
,
2622 const struct tgsi_full_instruction
*insn
)
2624 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
2625 struct src_register src0
=
2626 translate_src_register( emit
, &insn
->Src
[0] );
2627 SVGA3dShaderDestToken abs_tmp
;
2628 struct src_register abs_src0
;
2629 SVGA3dShaderDestToken log2_abs
;
2633 if (dst
.mask
& TGSI_WRITEMASK_Z
)
2635 else if (dst
.mask
& TGSI_WRITEMASK_XY
)
2636 log2_abs
= get_temp( emit
);
2640 /* If z is being written, fill it with log2( abs( src0 ) ).
2642 if (dst
.mask
& TGSI_WRITEMASK_XYZ
) {
2643 if (!src0
.base
.srcMod
|| src0
.base
.srcMod
== SVGA3DSRCMOD_ABS
)
2646 abs_tmp
= get_temp( emit
);
2648 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
2653 abs_src0
= src( abs_tmp
);
2656 abs_src0
= absolute( scalar( abs_src0
, TGSI_SWIZZLE_X
) );
2658 if (!submit_op1( emit
, inst_token( SVGA3DOP_LOG
),
2659 writemask( log2_abs
, TGSI_WRITEMASK_Z
),
2664 if (dst
.mask
& TGSI_WRITEMASK_XY
) {
2665 SVGA3dShaderDestToken floor_log2
;
2667 if (dst
.mask
& TGSI_WRITEMASK_X
)
2670 floor_log2
= get_temp( emit
);
2672 /* If x is being written, fill it with floor( log2( abs( src0 ) ) ).
2674 if (!submit_op1( emit
, inst_token( SVGA3DOP_FRC
),
2675 writemask( floor_log2
, TGSI_WRITEMASK_X
),
2676 scalar( src( log2_abs
), TGSI_SWIZZLE_Z
) ) )
2679 if (!submit_op2( emit
, inst_token( SVGA3DOP_ADD
),
2680 writemask( floor_log2
, TGSI_WRITEMASK_X
),
2681 scalar( src( log2_abs
), TGSI_SWIZZLE_Z
),
2682 negate( src( floor_log2
) ) ) )
2685 /* If y is being written, fill it with
2686 * abs ( src0 ) / ( 2 ^ floor( log2( abs( src0 ) ) ) ).
2688 if (dst
.mask
& TGSI_WRITEMASK_Y
) {
2689 if (!submit_op1( emit
, inst_token( SVGA3DOP_EXP
),
2690 writemask( dst
, TGSI_WRITEMASK_Y
),
2691 negate( scalar( src( floor_log2
),
2692 TGSI_SWIZZLE_X
) ) ) )
2695 if (!submit_op2( emit
, inst_token( SVGA3DOP_MUL
),
2696 writemask( dst
, TGSI_WRITEMASK_Y
),
2702 if (!(dst
.mask
& TGSI_WRITEMASK_X
))
2703 release_temp( emit
, floor_log2
);
2705 if (!(dst
.mask
& TGSI_WRITEMASK_Z
))
2706 release_temp( emit
, log2_abs
);
2709 if (dst
.mask
& TGSI_WRITEMASK_XYZ
&& src0
.base
.srcMod
&&
2710 src0
.base
.srcMod
!= SVGA3DSRCMOD_ABS
)
2711 release_temp( emit
, abs_tmp
);
2713 /* If w is being written, fill it with one.
2715 if (dst
.mask
& TGSI_WRITEMASK_W
) {
2716 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
2717 writemask(dst
, TGSI_WRITEMASK_W
),
2718 get_one_immediate(emit
)))
2727 * Translate TGSI TRUNC or ROUND instruction.
2728 * We need to truncate toward zero. Ex: trunc(-1.9) = -1
2729 * Different approaches are needed for VS versus PS.
2732 emit_trunc_round(struct svga_shader_emitter
*emit
,
2733 const struct tgsi_full_instruction
*insn
,
2736 SVGA3dShaderDestToken dst
= translate_dst_register(emit
, insn
, 0);
2737 const struct src_register src0
=
2738 translate_src_register(emit
, &insn
->Src
[0] );
2739 SVGA3dShaderDestToken t1
= get_temp(emit
);
2742 SVGA3dShaderDestToken t0
= get_temp(emit
);
2743 struct src_register half
= get_half_immediate(emit
);
2745 /* t0 = abs(src0) + 0.5 */
2746 if (!submit_op2(emit
, inst_token(SVGA3DOP_ADD
), t0
,
2747 absolute(src0
), half
))
2750 /* t1 = fract(t0) */
2751 if (!submit_op1(emit
, inst_token(SVGA3DOP_FRC
), t1
, src(t0
)))
2755 if (!submit_op2(emit
, inst_token(SVGA3DOP_ADD
), t1
, src(t0
),
2762 /* t1 = fract(abs(src0)) */
2763 if (!submit_op1(emit
, inst_token(SVGA3DOP_FRC
), t1
, absolute(src0
)))
2766 /* t1 = abs(src0) - t1 */
2767 if (!submit_op2(emit
, inst_token(SVGA3DOP_ADD
), t1
, absolute(src0
),
2773 * Now we need to multiply t1 by the sign of the original value.
2775 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
2776 /* For VS: use SGN instruction */
2777 /* Need two extra/dummy registers: */
2778 SVGA3dShaderDestToken t2
= get_temp(emit
), t3
= get_temp(emit
),
2779 t4
= get_temp(emit
);
2781 /* t2 = sign(src0) */
2782 if (!submit_op3(emit
, inst_token(SVGA3DOP_SGN
), t2
, src0
,
2787 if (!submit_op2(emit
, inst_token(SVGA3DOP_MUL
), dst
, src(t1
), src(t2
)))
2791 /* For FS: Use CMP instruction */
2792 return submit_op3(emit
, inst_token( SVGA3DOP_CMP
), dst
,
2793 src0
, src(t1
), negate(src(t1
)));
2801 * Translate/emit "begin subroutine" instruction/marker/label.
2804 emit_bgnsub(struct svga_shader_emitter
*emit
,
2806 const struct tgsi_full_instruction
*insn
)
2810 /* Note that we've finished the main function and are now emitting
2811 * subroutines. This affects how we terminate the generated
2814 emit
->in_main_func
= FALSE
;
2816 for (i
= 0; i
< emit
->nr_labels
; i
++) {
2817 if (emit
->label
[i
] == position
) {
2818 return (emit_instruction( emit
, inst_token( SVGA3DOP_RET
) ) &&
2819 emit_instruction( emit
, inst_token( SVGA3DOP_LABEL
) ) &&
2820 emit_src( emit
, src_register( SVGA3DREG_LABEL
, i
)));
2830 * Translate/emit subroutine call instruction.
2833 emit_call(struct svga_shader_emitter
*emit
,
2834 const struct tgsi_full_instruction
*insn
)
2836 unsigned position
= insn
->Label
.Label
;
2839 for (i
= 0; i
< emit
->nr_labels
; i
++) {
2840 if (emit
->label
[i
] == position
)
2844 if (emit
->nr_labels
== Elements(emit
->label
))
2847 if (i
== emit
->nr_labels
) {
2848 emit
->label
[i
] = position
;
2852 return (emit_instruction( emit
, inst_token( SVGA3DOP_CALL
) ) &&
2853 emit_src( emit
, src_register( SVGA3DREG_LABEL
, i
)));
2858 * Called at the end of the shader. Actually, emit special "fix-up"
2859 * code for the vertex/fragment shader.
2862 emit_end(struct svga_shader_emitter
*emit
)
2864 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
2865 return emit_vs_postamble( emit
);
2868 return emit_ps_postamble( emit
);
2874 * Translate any TGSI instruction to SVGA.
2877 svga_emit_instruction(struct svga_shader_emitter
*emit
,
2879 const struct tgsi_full_instruction
*insn
)
2881 switch (insn
->Instruction
.Opcode
) {
2883 case TGSI_OPCODE_ARL
:
2884 return emit_arl( emit
, insn
);
2886 case TGSI_OPCODE_TEX
:
2887 case TGSI_OPCODE_TXB
:
2888 case TGSI_OPCODE_TXP
:
2889 case TGSI_OPCODE_TXL
:
2890 case TGSI_OPCODE_TXD
:
2891 return emit_tex( emit
, insn
);
2893 case TGSI_OPCODE_DDX
:
2894 case TGSI_OPCODE_DDY
:
2895 return emit_deriv( emit
, insn
);
2897 case TGSI_OPCODE_BGNSUB
:
2898 return emit_bgnsub( emit
, position
, insn
);
2900 case TGSI_OPCODE_ENDSUB
:
2903 case TGSI_OPCODE_CAL
:
2904 return emit_call( emit
, insn
);
2906 case TGSI_OPCODE_FLR
:
2907 return emit_floor( emit
, insn
);
2909 case TGSI_OPCODE_TRUNC
:
2910 return emit_trunc_round( emit
, insn
, FALSE
);
2912 case TGSI_OPCODE_ROUND
:
2913 return emit_trunc_round( emit
, insn
, TRUE
);
2915 case TGSI_OPCODE_CEIL
:
2916 return emit_ceil( emit
, insn
);
2918 case TGSI_OPCODE_CMP
:
2919 return emit_cmp( emit
, insn
);
2921 case TGSI_OPCODE_DIV
:
2922 return emit_div( emit
, insn
);
2924 case TGSI_OPCODE_DP2
:
2925 return emit_dp2( emit
, insn
);
2927 case TGSI_OPCODE_DPH
:
2928 return emit_dph( emit
, insn
);
2930 case TGSI_OPCODE_COS
:
2931 return emit_cos( emit
, insn
);
2933 case TGSI_OPCODE_SIN
:
2934 return emit_sin( emit
, insn
);
2936 case TGSI_OPCODE_SCS
:
2937 return emit_sincos( emit
, insn
);
2939 case TGSI_OPCODE_END
:
2940 /* TGSI always finishes the main func with an END */
2941 return emit_end( emit
);
2943 case TGSI_OPCODE_KILL_IF
:
2944 return emit_kill_if( emit
, insn
);
2946 /* Selection opcodes. The underlying language is fairly
2947 * non-orthogonal about these.
2949 case TGSI_OPCODE_SEQ
:
2950 return emit_select_op( emit
, PIPE_FUNC_EQUAL
, insn
);
2952 case TGSI_OPCODE_SNE
:
2953 return emit_select_op( emit
, PIPE_FUNC_NOTEQUAL
, insn
);
2955 case TGSI_OPCODE_SGT
:
2956 return emit_select_op( emit
, PIPE_FUNC_GREATER
, insn
);
2958 case TGSI_OPCODE_SGE
:
2959 return emit_select_op( emit
, PIPE_FUNC_GEQUAL
, insn
);
2961 case TGSI_OPCODE_SLT
:
2962 return emit_select_op( emit
, PIPE_FUNC_LESS
, insn
);
2964 case TGSI_OPCODE_SLE
:
2965 return emit_select_op( emit
, PIPE_FUNC_LEQUAL
, insn
);
2967 case TGSI_OPCODE_SUB
:
2968 return emit_sub( emit
, insn
);
2970 case TGSI_OPCODE_POW
:
2971 return emit_pow( emit
, insn
);
2973 case TGSI_OPCODE_EX2
:
2974 return emit_ex2( emit
, insn
);
2976 case TGSI_OPCODE_EXP
:
2977 return emit_exp( emit
, insn
);
2979 case TGSI_OPCODE_LOG
:
2980 return emit_log( emit
, insn
);
2982 case TGSI_OPCODE_LG2
:
2983 return emit_scalar_op1( emit
, SVGA3DOP_LOG
, insn
);
2985 case TGSI_OPCODE_RSQ
:
2986 return emit_scalar_op1( emit
, SVGA3DOP_RSQ
, insn
);
2988 case TGSI_OPCODE_RCP
:
2989 return emit_scalar_op1( emit
, SVGA3DOP_RCP
, insn
);
2991 case TGSI_OPCODE_CONT
:
2992 /* not expected (we return PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED = 0) */
2995 case TGSI_OPCODE_RET
:
2996 /* This is a noop -- we tell mesa that we can't support RET
2997 * within a function (early return), so this will always be
2998 * followed by an ENDSUB.
3002 /* These aren't actually used by any of the frontends we care
3005 case TGSI_OPCODE_CLAMP
:
3006 case TGSI_OPCODE_AND
:
3007 case TGSI_OPCODE_OR
:
3008 case TGSI_OPCODE_I2F
:
3009 case TGSI_OPCODE_NOT
:
3010 case TGSI_OPCODE_SHL
:
3011 case TGSI_OPCODE_ISHR
:
3012 case TGSI_OPCODE_XOR
:
3015 case TGSI_OPCODE_IF
:
3016 return emit_if( emit
, insn
);
3017 case TGSI_OPCODE_ELSE
:
3018 return emit_else( emit
, insn
);
3019 case TGSI_OPCODE_ENDIF
:
3020 return emit_endif( emit
, insn
);
3022 case TGSI_OPCODE_BGNLOOP
:
3023 return emit_bgnloop( emit
, insn
);
3024 case TGSI_OPCODE_ENDLOOP
:
3025 return emit_endloop( emit
, insn
);
3026 case TGSI_OPCODE_BRK
:
3027 return emit_brk( emit
, insn
);
3029 case TGSI_OPCODE_XPD
:
3030 return emit_xpd( emit
, insn
);
3032 case TGSI_OPCODE_KILL
:
3033 return emit_kill( emit
, insn
);
3035 case TGSI_OPCODE_DST
:
3036 return emit_dst_insn( emit
, insn
);
3038 case TGSI_OPCODE_LIT
:
3039 return emit_lit( emit
, insn
);
3041 case TGSI_OPCODE_LRP
:
3042 return emit_lrp( emit
, insn
);
3044 case TGSI_OPCODE_SSG
:
3045 return emit_ssg( emit
, insn
);
3049 unsigned opcode
= translate_opcode(insn
->Instruction
.Opcode
);
3051 if (opcode
== SVGA3DOP_LAST_INST
)
3054 if (!emit_simple_instruction( emit
, opcode
, insn
))
3064 * Translate/emit a TGSI IMMEDIATE declaration.
3065 * An immediate vector is a constant that's hard-coded into the shader.
3068 svga_emit_immediate(struct svga_shader_emitter
*emit
,
3069 const struct tgsi_full_immediate
*imm
)
3071 static const float id
[4] = {0,0,0,1};
3075 assert(1 <= imm
->Immediate
.NrTokens
&& imm
->Immediate
.NrTokens
<= 5);
3076 for (i
= 0; i
< imm
->Immediate
.NrTokens
- 1; i
++) {
3077 float f
= imm
->u
[i
].Float
;
3078 value
[i
] = util_is_inf_or_nan(f
) ? 0.0f
: f
;
3081 /* If the immediate has less than four values, fill in the remaining
3082 * positions from id={0,0,0,1}.
3084 for ( ; i
< 4; i
++ )
3087 return emit_def_const( emit
, SVGA3D_CONST_TYPE_FLOAT
,
3088 emit
->imm_start
+ emit
->internal_imm_count
++,
3089 value
[0], value
[1], value
[2], value
[3]);
3094 make_immediate(struct svga_shader_emitter
*emit
,
3095 float a
, float b
, float c
, float d
,
3096 struct src_register
*out
)
3098 unsigned idx
= emit
->nr_hw_float_const
++;
3100 if (!emit_def_const( emit
, SVGA3D_CONST_TYPE_FLOAT
,
3104 *out
= src_register( SVGA3DREG_CONST
, idx
);
3111 * Emit special VS instructions at top of shader.
3114 emit_vs_preamble(struct svga_shader_emitter
*emit
)
3116 if (!emit
->key
.vkey
.need_prescale
) {
3117 if (!make_immediate( emit
, 0, 0, .5, .5,
3127 * Emit special PS instructions at top of shader.
3130 emit_ps_preamble(struct svga_shader_emitter
*emit
)
3132 if (emit
->ps_reads_pos
&& emit
->info
.reads_z
) {
3134 * Assemble the position from various bits of inputs. Depth and W are
3135 * passed in a texcoord this is due to D3D's vPos not hold Z or W.
3136 * Also fixup the perspective interpolation.
3138 * temp_pos.xy = vPos.xy
3139 * temp_pos.w = rcp(texcoord1.w);
3140 * temp_pos.z = texcoord1.z * temp_pos.w;
3142 if (!submit_op1( emit
,
3143 inst_token(SVGA3DOP_MOV
),
3144 writemask( emit
->ps_temp_pos
, TGSI_WRITEMASK_XY
),
3145 emit
->ps_true_pos
))
3148 if (!submit_op1( emit
,
3149 inst_token(SVGA3DOP_RCP
),
3150 writemask( emit
->ps_temp_pos
, TGSI_WRITEMASK_W
),
3151 scalar( emit
->ps_depth_pos
, TGSI_SWIZZLE_W
) ))
3154 if (!submit_op2( emit
,
3155 inst_token(SVGA3DOP_MUL
),
3156 writemask( emit
->ps_temp_pos
, TGSI_WRITEMASK_Z
),
3157 scalar( emit
->ps_depth_pos
, TGSI_SWIZZLE_Z
),
3158 scalar( src(emit
->ps_temp_pos
), TGSI_SWIZZLE_W
) ))
3167 * Emit special PS instructions at end of shader.
3170 emit_ps_postamble(struct svga_shader_emitter
*emit
)
3174 /* PS oDepth is incredibly fragile and it's very hard to catch the
3175 * types of usage that break it during shader emit. Easier just to
3176 * redirect the main program to a temporary and then only touch
3177 * oDepth with a hand-crafted MOV below.
3179 if (SVGA3dShaderGetRegType(emit
->true_pos
.value
) != 0) {
3180 if (!submit_op1( emit
,
3181 inst_token(SVGA3DOP_MOV
),
3183 scalar(src(emit
->temp_pos
), TGSI_SWIZZLE_Z
) ))
3187 for (i
= 0; i
< PIPE_MAX_COLOR_BUFS
; i
++) {
3188 if (SVGA3dShaderGetRegType(emit
->true_color_output
[i
].value
) != 0) {
3189 /* Potentially override output colors with white for XOR
3190 * logicop workaround.
3192 if (emit
->unit
== PIPE_SHADER_FRAGMENT
&&
3193 emit
->key
.fkey
.white_fragments
) {
3194 struct src_register one
= get_one_immediate(emit
);
3196 if (!submit_op1( emit
,
3197 inst_token(SVGA3DOP_MOV
),
3198 emit
->true_color_output
[i
],
3202 else if (emit
->unit
== PIPE_SHADER_FRAGMENT
&&
3203 i
< emit
->key
.fkey
.write_color0_to_n_cbufs
) {
3204 /* Write temp color output [0] to true output [i] */
3205 if (!submit_op1(emit
, inst_token(SVGA3DOP_MOV
),
3206 emit
->true_color_output
[i
],
3207 src(emit
->temp_color_output
[0]))) {
3212 if (!submit_op1( emit
,
3213 inst_token(SVGA3DOP_MOV
),
3214 emit
->true_color_output
[i
],
3215 src(emit
->temp_color_output
[i
]) ))
3226 * Emit special VS instructions at end of shader.
3229 emit_vs_postamble(struct svga_shader_emitter
*emit
)
3231 /* PSIZ output is incredibly fragile and it's very hard to catch
3232 * the types of usage that break it during shader emit. Easier
3233 * just to redirect the main program to a temporary and then only
3234 * touch PSIZ with a hand-crafted MOV below.
3236 if (SVGA3dShaderGetRegType(emit
->true_psiz
.value
) != 0) {
3237 if (!submit_op1( emit
,
3238 inst_token(SVGA3DOP_MOV
),
3240 scalar(src(emit
->temp_psiz
), TGSI_SWIZZLE_X
) ))
3244 /* Need to perform various manipulations on vertex position to cope
3245 * with the different GL and D3D clip spaces.
3247 if (emit
->key
.vkey
.need_prescale
) {
3248 SVGA3dShaderDestToken temp_pos
= emit
->temp_pos
;
3249 SVGA3dShaderDestToken depth
= emit
->depth_pos
;
3250 SVGA3dShaderDestToken pos
= emit
->true_pos
;
3251 unsigned offset
= emit
->info
.file_max
[TGSI_FILE_CONSTANT
] + 1;
3252 struct src_register prescale_scale
= src_register( SVGA3DREG_CONST
,
3254 struct src_register prescale_trans
= src_register( SVGA3DREG_CONST
,
3257 if (!submit_op1( emit
,
3258 inst_token(SVGA3DOP_MOV
),
3259 writemask(depth
, TGSI_WRITEMASK_W
),
3260 scalar(src(temp_pos
), TGSI_SWIZZLE_W
) ))
3263 /* MUL temp_pos.xyz, temp_pos, prescale.scale
3264 * MAD result.position, temp_pos.wwww, prescale.trans, temp_pos
3265 * --> Note that prescale.trans.w == 0
3267 if (!submit_op2( emit
,
3268 inst_token(SVGA3DOP_MUL
),
3269 writemask(temp_pos
, TGSI_WRITEMASK_XYZ
),
3274 if (!submit_op3( emit
,
3275 inst_token(SVGA3DOP_MAD
),
3277 swizzle(src(temp_pos
), 3, 3, 3, 3),
3282 /* Also write to depth value */
3283 if (!submit_op3( emit
,
3284 inst_token(SVGA3DOP_MAD
),
3285 writemask(depth
, TGSI_WRITEMASK_Z
),
3286 swizzle(src(temp_pos
), 3, 3, 3, 3),
3292 SVGA3dShaderDestToken temp_pos
= emit
->temp_pos
;
3293 SVGA3dShaderDestToken depth
= emit
->depth_pos
;
3294 SVGA3dShaderDestToken pos
= emit
->true_pos
;
3295 struct src_register imm_0055
= emit
->imm_0055
;
3297 /* Adjust GL clipping coordinate space to hardware (D3D-style):
3299 * DP4 temp_pos.z, {0,0,.5,.5}, temp_pos
3300 * MOV result.position, temp_pos
3302 if (!submit_op2( emit
,
3303 inst_token(SVGA3DOP_DP4
),
3304 writemask(temp_pos
, TGSI_WRITEMASK_Z
),
3309 if (!submit_op1( emit
,
3310 inst_token(SVGA3DOP_MOV
),
3315 /* Move the manipulated depth into the extra texcoord reg */
3316 if (!submit_op1( emit
,
3317 inst_token(SVGA3DOP_MOV
),
3318 writemask(depth
, TGSI_WRITEMASK_ZW
),
3328 * For the pixel shader: emit the code which chooses the front
3329 * or back face color depending on triangle orientation.
3330 * This happens at the top of the fragment shader.
3333 * 1: COLOR = FrontColor;
3335 * 3: COLOR = BackColor;
3339 emit_light_twoside(struct svga_shader_emitter
*emit
)
3341 struct src_register vface
, zero
;
3342 struct src_register front
[2];
3343 struct src_register back
[2];
3344 SVGA3dShaderDestToken color
[2];
3345 int count
= emit
->internal_color_count
;
3347 SVGA3dShaderInstToken if_token
;
3352 vface
= get_vface( emit
);
3353 zero
= get_zero_immediate(emit
);
3355 /* Can't use get_temp() to allocate the color reg as such
3356 * temporaries will be reclaimed after each instruction by the call
3357 * to reset_temp_regs().
3359 for (i
= 0; i
< count
; i
++) {
3360 color
[i
] = dst_register( SVGA3DREG_TEMP
, emit
->nr_hw_temp
++ );
3361 front
[i
] = emit
->input_map
[emit
->internal_color_idx
[i
]];
3363 /* Back is always the next input:
3366 back
[i
].base
.num
= front
[i
].base
.num
+ 1;
3368 /* Reassign the input_map to the actual front-face color:
3370 emit
->input_map
[emit
->internal_color_idx
[i
]] = src(color
[i
]);
3373 if_token
= inst_token( SVGA3DOP_IFC
);
3375 if (emit
->key
.fkey
.front_ccw
)
3376 if_token
.control
= SVGA3DOPCOMP_LT
;
3378 if_token
.control
= SVGA3DOPCOMP_GT
;
3380 if (!(emit_instruction( emit
, if_token
) &&
3381 emit_src( emit
, vface
) &&
3382 emit_src( emit
, zero
) ))
3385 for (i
= 0; i
< count
; i
++) {
3386 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), color
[i
], front
[i
] ))
3390 if (!(emit_instruction( emit
, inst_token( SVGA3DOP_ELSE
))))
3393 for (i
= 0; i
< count
; i
++) {
3394 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), color
[i
], back
[i
] ))
3398 if (!emit_instruction( emit
, inst_token( SVGA3DOP_ENDIF
) ))
3406 * Emit special setup code for the front/back face register in the FS.
3407 * 0: SETP_GT TEMP, VFACE, 0
3408 * where TEMP is a fake frontface register
3411 emit_frontface(struct svga_shader_emitter
*emit
)
3413 struct src_register vface
;
3414 SVGA3dShaderDestToken temp
;
3415 struct src_register pass
, fail
;
3417 vface
= get_vface( emit
);
3419 /* Can't use get_temp() to allocate the fake frontface reg as such
3420 * temporaries will be reclaimed after each instruction by the call
3421 * to reset_temp_regs().
3423 temp
= dst_register( SVGA3DREG_TEMP
,
3424 emit
->nr_hw_temp
++ );
3426 if (emit
->key
.fkey
.front_ccw
) {
3427 pass
= get_zero_immediate(emit
);
3428 fail
= get_one_immediate(emit
);
3430 pass
= get_one_immediate(emit
);
3431 fail
= get_zero_immediate(emit
);
3434 if (!emit_conditional(emit
, PIPE_FUNC_GREATER
,
3435 temp
, vface
, get_zero_immediate(emit
),
3439 /* Reassign the input_map to the actual front-face color:
3441 emit
->input_map
[emit
->internal_frontface_idx
] = src(temp
);
3448 * Emit code to invert the T component of the incoming texture coordinate.
3449 * This is used for drawing point sprites when
3450 * pipe_rasterizer_state::sprite_coord_mode == PIPE_SPRITE_COORD_LOWER_LEFT.
3453 emit_inverted_texcoords(struct svga_shader_emitter
*emit
)
3455 unsigned inverted_texcoords
= emit
->inverted_texcoords
;
3457 while (inverted_texcoords
) {
3458 const unsigned unit
= ffs(inverted_texcoords
) - 1;
3460 assert(emit
->inverted_texcoords
& (1 << unit
));
3462 assert(unit
< Elements(emit
->ps_true_texcoord
));
3464 assert(unit
< Elements(emit
->ps_inverted_texcoord_input
));
3466 assert(emit
->ps_inverted_texcoord_input
[unit
]
3467 < Elements(emit
->input_map
));
3469 /* inverted = coord * (1, -1, 1, 1) + (0, 1, 0, 0) */
3470 if (!submit_op3(emit
,
3471 inst_token(SVGA3DOP_MAD
),
3472 dst(emit
->ps_inverted_texcoord
[unit
]),
3473 emit
->ps_true_texcoord
[unit
],
3474 get_immediate(emit
, 1.0f
, -1.0f
, 1.0f
, 1.0f
),
3475 get_immediate(emit
, 0.0f
, 1.0f
, 0.0f
, 0.0f
)))
3478 /* Reassign the input_map entry to the new texcoord register */
3479 emit
->input_map
[emit
->ps_inverted_texcoord_input
[unit
]] =
3480 emit
->ps_inverted_texcoord
[unit
];
3482 inverted_texcoords
&= ~(1 << unit
);
3490 * Emit code to adjust vertex shader inputs/attributes:
3491 * - Change range from [0,1] to [-1,1] (for normalized byte/short attribs).
3492 * - Set attrib W component = 1.
3495 emit_adjusted_vertex_attribs(struct svga_shader_emitter
*emit
)
3497 unsigned adjust_mask
= (emit
->key
.vkey
.adjust_attrib_range
|
3498 emit
->key
.vkey
.adjust_attrib_w_1
);
3500 while (adjust_mask
) {
3501 /* Adjust vertex attrib range and/or set W component = 1 */
3502 const unsigned index
= u_bit_scan(&adjust_mask
);
3503 struct src_register tmp
;
3505 /* allocate a temp reg */
3506 tmp
= src_register(SVGA3DREG_TEMP
, emit
->nr_hw_temp
);
3509 if (emit
->key
.vkey
.adjust_attrib_range
& (1 << index
)) {
3510 /* The vertex input/attribute is supposed to be a signed value in
3511 * the range [-1,1] but we actually fetched/converted it to the
3512 * range [0,1]. This most likely happens when the app specifies a
3513 * signed byte attribute but we interpreted it as unsigned bytes.
3514 * See also svga_translate_vertex_format().
3516 * Here, we emit some extra instructions to adjust
3517 * the attribute values from [0,1] to [-1,1].
3519 * The adjustment we implement is:
3520 * new_attrib = attrib * 2.0;
3521 * if (attrib >= 0.5)
3522 * new_attrib = new_attrib - 2.0;
3523 * This isn't exactly right (it's off by a bit or so) but close enough.
3525 SVGA3dShaderDestToken pred_reg
= dst_register(SVGA3DREG_PREDICATE
, 0);
3527 /* tmp = attrib * 2.0 */
3528 if (!submit_op2(emit
,
3529 inst_token(SVGA3DOP_MUL
),
3531 emit
->input_map
[index
],
3532 get_two_immediate(emit
)))
3535 /* pred = (attrib >= 0.5) */
3536 if (!submit_op2(emit
,
3537 inst_token_setp(SVGA3DOPCOMP_GE
),
3539 emit
->input_map
[index
], /* vert attrib */
3540 get_half_immediate(emit
))) /* 0.5 */
3543 /* sub(pred) tmp, tmp, 2.0 */
3544 if (!submit_op3(emit
,
3545 inst_token_predicated(SVGA3DOP_SUB
),
3549 get_two_immediate(emit
)))
3553 /* just copy the vertex input attrib to the temp register */
3554 if (!submit_op1(emit
,
3555 inst_token(SVGA3DOP_MOV
),
3557 emit
->input_map
[index
]))
3561 if (emit
->key
.vkey
.adjust_attrib_w_1
& (1 << index
)) {
3562 /* move 1 into W position of tmp */
3563 if (!submit_op1(emit
,
3564 inst_token(SVGA3DOP_MOV
),
3565 writemask(dst(tmp
), TGSI_WRITEMASK_W
),
3566 get_one_immediate(emit
)))
3570 /* Reassign the input_map entry to the new tmp register */
3571 emit
->input_map
[index
] = tmp
;
3579 * Determine if we need to create the "common" immediate value which is
3580 * used for generating useful vector constants such as {0,0,0,0} and
3582 * We could just do this all the time except that we want to conserve
3583 * registers whenever possible.
3586 needs_to_create_common_immediate(const struct svga_shader_emitter
*emit
)
3590 if (emit
->unit
== PIPE_SHADER_FRAGMENT
) {
3591 if (emit
->key
.fkey
.light_twoside
)
3594 if (emit
->key
.fkey
.white_fragments
)
3597 if (emit
->emit_frontface
)
3600 if (emit
->info
.opcode_count
[TGSI_OPCODE_DST
] >= 1 ||
3601 emit
->info
.opcode_count
[TGSI_OPCODE_SSG
] >= 1 ||
3602 emit
->info
.opcode_count
[TGSI_OPCODE_LIT
] >= 1)
3605 if (emit
->inverted_texcoords
)
3608 /* look for any PIPE_SWIZZLE_ZERO/ONE terms */
3609 for (i
= 0; i
< emit
->key
.fkey
.num_textures
; i
++) {
3610 if (emit
->key
.fkey
.tex
[i
].swizzle_r
> PIPE_SWIZZLE_ALPHA
||
3611 emit
->key
.fkey
.tex
[i
].swizzle_g
> PIPE_SWIZZLE_ALPHA
||
3612 emit
->key
.fkey
.tex
[i
].swizzle_b
> PIPE_SWIZZLE_ALPHA
||
3613 emit
->key
.fkey
.tex
[i
].swizzle_a
> PIPE_SWIZZLE_ALPHA
)
3617 for (i
= 0; i
< emit
->key
.fkey
.num_textures
; i
++) {
3618 if (emit
->key
.fkey
.tex
[i
].compare_mode
3619 == PIPE_TEX_COMPARE_R_TO_TEXTURE
)
3623 else if (emit
->unit
== PIPE_SHADER_VERTEX
) {
3624 if (emit
->info
.opcode_count
[TGSI_OPCODE_CMP
] >= 1)
3626 if (emit
->key
.vkey
.adjust_attrib_range
||
3627 emit
->key
.vkey
.adjust_attrib_w_1
)
3631 if (emit
->info
.opcode_count
[TGSI_OPCODE_IF
] >= 1 ||
3632 emit
->info
.opcode_count
[TGSI_OPCODE_BGNLOOP
] >= 1 ||
3633 emit
->info
.opcode_count
[TGSI_OPCODE_DDX
] >= 1 ||
3634 emit
->info
.opcode_count
[TGSI_OPCODE_DDY
] >= 1 ||
3635 emit
->info
.opcode_count
[TGSI_OPCODE_ROUND
] >= 1 ||
3636 emit
->info
.opcode_count
[TGSI_OPCODE_SGE
] >= 1 ||
3637 emit
->info
.opcode_count
[TGSI_OPCODE_SGT
] >= 1 ||
3638 emit
->info
.opcode_count
[TGSI_OPCODE_SLE
] >= 1 ||
3639 emit
->info
.opcode_count
[TGSI_OPCODE_SLT
] >= 1 ||
3640 emit
->info
.opcode_count
[TGSI_OPCODE_SNE
] >= 1 ||
3641 emit
->info
.opcode_count
[TGSI_OPCODE_SEQ
] >= 1 ||
3642 emit
->info
.opcode_count
[TGSI_OPCODE_EXP
] >= 1 ||
3643 emit
->info
.opcode_count
[TGSI_OPCODE_LOG
] >= 1 ||
3644 emit
->info
.opcode_count
[TGSI_OPCODE_XPD
] >= 1 ||
3645 emit
->info
.opcode_count
[TGSI_OPCODE_KILL
] >= 1)
3653 * Do we need to create a looping constant?
3656 needs_to_create_loop_const(const struct svga_shader_emitter
*emit
)
3658 return (emit
->info
.opcode_count
[TGSI_OPCODE_BGNLOOP
] >= 1);
3663 needs_to_create_arl_consts(const struct svga_shader_emitter
*emit
)
3665 return (emit
->num_arl_consts
> 0);
3670 pre_parse_add_indirect( struct svga_shader_emitter
*emit
,
3671 int num
, int current_arl
)
3676 for (i
= 0; i
< emit
->num_arl_consts
; ++i
) {
3677 if (emit
->arl_consts
[i
].arl_num
== current_arl
)
3681 if (emit
->num_arl_consts
== i
) {
3682 ++emit
->num_arl_consts
;
3684 emit
->arl_consts
[i
].number
= (emit
->arl_consts
[i
].number
> num
) ?
3686 emit
->arl_consts
[i
].number
;
3687 emit
->arl_consts
[i
].arl_num
= current_arl
;
3693 pre_parse_instruction( struct svga_shader_emitter
*emit
,
3694 const struct tgsi_full_instruction
*insn
,
3697 if (insn
->Src
[0].Register
.Indirect
&&
3698 insn
->Src
[0].Indirect
.File
== TGSI_FILE_ADDRESS
) {
3699 const struct tgsi_full_src_register
*reg
= &insn
->Src
[0];
3700 if (reg
->Register
.Index
< 0) {
3701 pre_parse_add_indirect(emit
, reg
->Register
.Index
, current_arl
);
3705 if (insn
->Src
[1].Register
.Indirect
&&
3706 insn
->Src
[1].Indirect
.File
== TGSI_FILE_ADDRESS
) {
3707 const struct tgsi_full_src_register
*reg
= &insn
->Src
[1];
3708 if (reg
->Register
.Index
< 0) {
3709 pre_parse_add_indirect(emit
, reg
->Register
.Index
, current_arl
);
3713 if (insn
->Src
[2].Register
.Indirect
&&
3714 insn
->Src
[2].Indirect
.File
== TGSI_FILE_ADDRESS
) {
3715 const struct tgsi_full_src_register
*reg
= &insn
->Src
[2];
3716 if (reg
->Register
.Index
< 0) {
3717 pre_parse_add_indirect(emit
, reg
->Register
.Index
, current_arl
);
3726 pre_parse_tokens( struct svga_shader_emitter
*emit
,
3727 const struct tgsi_token
*tokens
)
3729 struct tgsi_parse_context parse
;
3730 int current_arl
= 0;
3732 tgsi_parse_init( &parse
, tokens
);
3734 while (!tgsi_parse_end_of_tokens( &parse
)) {
3735 tgsi_parse_token( &parse
);
3736 switch (parse
.FullToken
.Token
.Type
) {
3737 case TGSI_TOKEN_TYPE_IMMEDIATE
:
3738 case TGSI_TOKEN_TYPE_DECLARATION
:
3740 case TGSI_TOKEN_TYPE_INSTRUCTION
:
3741 if (parse
.FullToken
.FullInstruction
.Instruction
.Opcode
==
3745 if (!pre_parse_instruction( emit
, &parse
.FullToken
.FullInstruction
,
3759 svga_shader_emit_helpers(struct svga_shader_emitter
*emit
)
3761 if (needs_to_create_common_immediate( emit
)) {
3762 create_common_immediate( emit
);
3764 if (needs_to_create_loop_const( emit
)) {
3765 create_loop_const( emit
);
3767 if (needs_to_create_arl_consts( emit
)) {
3768 create_arl_consts( emit
);
3771 if (emit
->unit
== PIPE_SHADER_FRAGMENT
) {
3772 if (!emit_ps_preamble( emit
))
3775 if (emit
->key
.fkey
.light_twoside
) {
3776 if (!emit_light_twoside( emit
))
3779 if (emit
->emit_frontface
) {
3780 if (!emit_frontface( emit
))
3783 if (emit
->inverted_texcoords
) {
3784 if (!emit_inverted_texcoords( emit
))
3789 assert(emit
->unit
== PIPE_SHADER_VERTEX
);
3790 if (emit
->key
.vkey
.adjust_attrib_range
||
3791 emit
->key
.vkey
.adjust_attrib_w_1
) {
3792 if (!emit_adjusted_vertex_attribs(emit
))
3803 * This is the main entrypoint into the TGSI instruction translater.
3804 * Translate TGSI shader tokens into an SVGA shader.
3807 svga_shader_emit_instructions(struct svga_shader_emitter
*emit
,
3808 const struct tgsi_token
*tokens
)
3810 struct tgsi_parse_context parse
;
3812 boolean helpers_emitted
= FALSE
;
3813 unsigned line_nr
= 0;
3815 tgsi_parse_init( &parse
, tokens
);
3816 emit
->internal_imm_count
= 0;
3818 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
3819 ret
= emit_vs_preamble( emit
);
3824 pre_parse_tokens(emit
, tokens
);
3826 while (!tgsi_parse_end_of_tokens( &parse
)) {
3827 tgsi_parse_token( &parse
);
3829 switch (parse
.FullToken
.Token
.Type
) {
3830 case TGSI_TOKEN_TYPE_IMMEDIATE
:
3831 ret
= svga_emit_immediate( emit
, &parse
.FullToken
.FullImmediate
);
3836 case TGSI_TOKEN_TYPE_DECLARATION
:
3837 ret
= svga_translate_decl_sm30( emit
, &parse
.FullToken
.FullDeclaration
);
3842 case TGSI_TOKEN_TYPE_INSTRUCTION
:
3843 if (!helpers_emitted
) {
3844 if (!svga_shader_emit_helpers( emit
))
3846 helpers_emitted
= TRUE
;
3848 ret
= svga_emit_instruction( emit
,
3850 &parse
.FullToken
.FullInstruction
);
3858 reset_temp_regs( emit
);
3861 /* Need to terminate the current subroutine. Note that the
3862 * hardware doesn't tolerate shaders without sub-routines
3863 * terminating with RET+END.
3865 if (!emit
->in_main_func
) {
3866 ret
= emit_instruction( emit
, inst_token( SVGA3DOP_RET
) );
3871 assert(emit
->dynamic_branching_level
== 0);
3873 /* Need to terminate the whole shader:
3875 ret
= emit_instruction( emit
, inst_token( SVGA3DOP_END
) );
3880 tgsi_parse_free( &parse
);