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svga: remove support for shader model 2.0
[mesa.git] / src / gallium / drivers / svga / svga_tgsi_insn.c
1 /**********************************************************
2 * Copyright 2008-2009 VMware, Inc. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 **********************************************************/
25
26
27 #include "pipe/p_shader_tokens.h"
28 #include "tgsi/tgsi_dump.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/u_memory.h"
31 #include "util/u_math.h"
32
33 #include "svga_tgsi_emit.h"
34 #include "svga_context.h"
35
36
37 static boolean emit_vs_postamble( struct svga_shader_emitter *emit );
38 static boolean emit_ps_postamble( struct svga_shader_emitter *emit );
39
40
41
42
43 static unsigned
44 translate_opcode(
45 uint opcode )
46 {
47 switch (opcode) {
48 case TGSI_OPCODE_ABS: return SVGA3DOP_ABS;
49 case TGSI_OPCODE_ADD: return SVGA3DOP_ADD;
50 case TGSI_OPCODE_BREAKC: return SVGA3DOP_BREAKC;
51 case TGSI_OPCODE_DP2A: return SVGA3DOP_DP2ADD;
52 case TGSI_OPCODE_DP3: return SVGA3DOP_DP3;
53 case TGSI_OPCODE_DP4: return SVGA3DOP_DP4;
54 case TGSI_OPCODE_FRC: return SVGA3DOP_FRC;
55 case TGSI_OPCODE_MAD: return SVGA3DOP_MAD;
56 case TGSI_OPCODE_MAX: return SVGA3DOP_MAX;
57 case TGSI_OPCODE_MIN: return SVGA3DOP_MIN;
58 case TGSI_OPCODE_MOV: return SVGA3DOP_MOV;
59 case TGSI_OPCODE_MUL: return SVGA3DOP_MUL;
60 case TGSI_OPCODE_NOP: return SVGA3DOP_NOP;
61 case TGSI_OPCODE_NRM4: return SVGA3DOP_NRM;
62 default:
63 debug_printf("Unkown opcode %u\n", opcode);
64 assert( 0 );
65 return SVGA3DOP_LAST_INST;
66 }
67 }
68
69
70 static unsigned translate_file( unsigned file )
71 {
72 switch (file) {
73 case TGSI_FILE_TEMPORARY: return SVGA3DREG_TEMP;
74 case TGSI_FILE_INPUT: return SVGA3DREG_INPUT;
75 case TGSI_FILE_OUTPUT: return SVGA3DREG_OUTPUT; /* VS3.0+ only */
76 case TGSI_FILE_IMMEDIATE: return SVGA3DREG_CONST;
77 case TGSI_FILE_CONSTANT: return SVGA3DREG_CONST;
78 case TGSI_FILE_SAMPLER: return SVGA3DREG_SAMPLER;
79 case TGSI_FILE_ADDRESS: return SVGA3DREG_ADDR;
80 default:
81 assert( 0 );
82 return SVGA3DREG_TEMP;
83 }
84 }
85
86
87
88
89
90
91 static SVGA3dShaderDestToken
92 translate_dst_register( struct svga_shader_emitter *emit,
93 const struct tgsi_full_instruction *insn,
94 unsigned idx )
95 {
96 const struct tgsi_full_dst_register *reg = &insn->Dst[idx];
97 SVGA3dShaderDestToken dest;
98
99 switch (reg->Register.File) {
100 case TGSI_FILE_OUTPUT:
101 /* Output registers encode semantic information in their name.
102 * Need to lookup a table built at decl time:
103 */
104 dest = emit->output_map[reg->Register.Index];
105 break;
106
107 default:
108 dest = dst_register( translate_file( reg->Register.File ),
109 reg->Register.Index );
110 break;
111 }
112
113 dest.mask = reg->Register.WriteMask;
114 assert(dest.mask);
115
116 if (insn->Instruction.Saturate)
117 dest.dstMod = SVGA3DDSTMOD_SATURATE;
118
119 return dest;
120 }
121
122
123 static struct src_register
124 swizzle( struct src_register src,
125 int x,
126 int y,
127 int z,
128 int w )
129 {
130 x = (src.base.swizzle >> (x * 2)) & 0x3;
131 y = (src.base.swizzle >> (y * 2)) & 0x3;
132 z = (src.base.swizzle >> (z * 2)) & 0x3;
133 w = (src.base.swizzle >> (w * 2)) & 0x3;
134
135 src.base.swizzle = TRANSLATE_SWIZZLE(x,y,z,w);
136
137 return src;
138 }
139
140 static struct src_register
141 scalar( struct src_register src,
142 int comp )
143 {
144 return swizzle( src, comp, comp, comp, comp );
145 }
146
147 static INLINE boolean
148 svga_arl_needs_adjustment( const struct svga_shader_emitter *emit )
149 {
150 int i;
151
152 for (i = 0; i < emit->num_arl_consts; ++i) {
153 if (emit->arl_consts[i].arl_num == emit->current_arl)
154 return TRUE;
155 }
156 return FALSE;
157 }
158
159 static INLINE int
160 svga_arl_adjustment( const struct svga_shader_emitter *emit )
161 {
162 int i;
163
164 for (i = 0; i < emit->num_arl_consts; ++i) {
165 if (emit->arl_consts[i].arl_num == emit->current_arl)
166 return emit->arl_consts[i].number;
167 }
168 return 0;
169 }
170
171 static struct src_register
172 translate_src_register( const struct svga_shader_emitter *emit,
173 const struct tgsi_full_src_register *reg )
174 {
175 struct src_register src;
176
177 switch (reg->Register.File) {
178 case TGSI_FILE_INPUT:
179 /* Input registers are referred to by their semantic name rather
180 * than by index. Use the mapping build up from the decls:
181 */
182 src = emit->input_map[reg->Register.Index];
183 break;
184
185 case TGSI_FILE_IMMEDIATE:
186 /* Immediates are appended after TGSI constants in the D3D
187 * constant buffer.
188 */
189 src = src_register( translate_file( reg->Register.File ),
190 reg->Register.Index +
191 emit->imm_start );
192 break;
193
194 default:
195 src = src_register( translate_file( reg->Register.File ),
196 reg->Register.Index );
197
198 break;
199 }
200
201 /* Indirect addressing.
202 */
203 if (reg->Register.Indirect) {
204 if (emit->unit == PIPE_SHADER_FRAGMENT) {
205 /* Pixel shaders have only loop registers for relative
206 * addressing into inputs. Ignore the redundant address
207 * register, the contents of aL should be in sync with it.
208 */
209 if (reg->Register.File == TGSI_FILE_INPUT) {
210 src.base.relAddr = 1;
211 src.indirect = src_token(SVGA3DREG_LOOP, 0);
212 }
213 }
214 else {
215 /* Constant buffers only.
216 */
217 if (reg->Register.File == TGSI_FILE_CONSTANT) {
218 /* we shift the offset towards the minimum */
219 if (svga_arl_needs_adjustment( emit )) {
220 src.base.num -= svga_arl_adjustment( emit );
221 }
222 src.base.relAddr = 1;
223
224 /* Not really sure what should go in the second token:
225 */
226 src.indirect = src_token( SVGA3DREG_ADDR,
227 reg->Indirect.Index );
228
229 src.indirect.swizzle = SWIZZLE_XXXX;
230 }
231 }
232 }
233
234 src = swizzle( src,
235 reg->Register.SwizzleX,
236 reg->Register.SwizzleY,
237 reg->Register.SwizzleZ,
238 reg->Register.SwizzleW );
239
240 /* src.mod isn't a bitfield, unfortunately:
241 * See tgsi_util_get_full_src_register_sign_mode for implementation details.
242 */
243 if (reg->Register.Absolute) {
244 if (reg->Register.Negate)
245 src.base.srcMod = SVGA3DSRCMOD_ABSNEG;
246 else
247 src.base.srcMod = SVGA3DSRCMOD_ABS;
248 }
249 else {
250 if (reg->Register.Negate)
251 src.base.srcMod = SVGA3DSRCMOD_NEG;
252 else
253 src.base.srcMod = SVGA3DSRCMOD_NONE;
254 }
255
256 return src;
257 }
258
259
260 /*
261 * Get a temporary register, return -1 if none available
262 */
263 static INLINE SVGA3dShaderDestToken
264 get_temp( struct svga_shader_emitter *emit )
265 {
266 int i = emit->nr_hw_temp + emit->internal_temp_count++;
267
268 return dst_register( SVGA3DREG_TEMP, i );
269 }
270
271 /* Release a single temp. Currently only effective if it was the last
272 * allocated temp, otherwise release will be delayed until the next
273 * call to reset_temp_regs().
274 */
275 static INLINE void
276 release_temp( struct svga_shader_emitter *emit,
277 SVGA3dShaderDestToken temp )
278 {
279 if (temp.num == emit->internal_temp_count - 1)
280 emit->internal_temp_count--;
281 }
282
283 static void reset_temp_regs( struct svga_shader_emitter *emit )
284 {
285 emit->internal_temp_count = 0;
286 }
287
288
289 /* Replace the src with the temporary specified in the dst, but copying
290 * only the necessary channels, and preserving the original swizzle (which is
291 * important given that several opcodes have constraints in the allowed
292 * swizzles).
293 */
294 static boolean emit_repl( struct svga_shader_emitter *emit,
295 SVGA3dShaderDestToken dst,
296 struct src_register *src0)
297 {
298 unsigned src0_swizzle;
299 unsigned chan;
300
301 assert(SVGA3dShaderGetRegType(dst.value) == SVGA3DREG_TEMP);
302
303 src0_swizzle = src0->base.swizzle;
304
305 dst.mask = 0;
306 for (chan = 0; chan < 4; ++chan) {
307 unsigned swizzle = (src0_swizzle >> (chan *2)) & 0x3;
308 dst.mask |= 1 << swizzle;
309 }
310 assert(dst.mask);
311
312 src0->base.swizzle = SVGA3DSWIZZLE_NONE;
313
314 if (!emit_op1( emit, inst_token( SVGA3DOP_MOV ), dst, *src0 ))
315 return FALSE;
316
317 *src0 = src( dst );
318 src0->base.swizzle = src0_swizzle;
319
320 return TRUE;
321 }
322
323
324 static boolean submit_op0( struct svga_shader_emitter *emit,
325 SVGA3dShaderInstToken inst,
326 SVGA3dShaderDestToken dest )
327 {
328 return (emit_instruction( emit, inst ) &&
329 emit_dst( emit, dest ));
330 }
331
332 static boolean submit_op1( struct svga_shader_emitter *emit,
333 SVGA3dShaderInstToken inst,
334 SVGA3dShaderDestToken dest,
335 struct src_register src0 )
336 {
337 return emit_op1( emit, inst, dest, src0 );
338 }
339
340
341 /* SVGA shaders may not refer to >1 constant register in a single
342 * instruction. This function checks for that usage and inserts a
343 * move to temporary if detected.
344 *
345 * The same applies to input registers -- at most a single input
346 * register may be read by any instruction.
347 */
348 static boolean submit_op2( struct svga_shader_emitter *emit,
349 SVGA3dShaderInstToken inst,
350 SVGA3dShaderDestToken dest,
351 struct src_register src0,
352 struct src_register src1 )
353 {
354 SVGA3dShaderDestToken temp;
355 SVGA3dShaderRegType type0, type1;
356 boolean need_temp = FALSE;
357
358 temp.value = 0;
359 type0 = SVGA3dShaderGetRegType( src0.base.value );
360 type1 = SVGA3dShaderGetRegType( src1.base.value );
361
362 if (type0 == SVGA3DREG_CONST &&
363 type1 == SVGA3DREG_CONST &&
364 src0.base.num != src1.base.num)
365 need_temp = TRUE;
366
367 if (type0 == SVGA3DREG_INPUT &&
368 type1 == SVGA3DREG_INPUT &&
369 src0.base.num != src1.base.num)
370 need_temp = TRUE;
371
372 if (need_temp) {
373 temp = get_temp( emit );
374
375 if (!emit_repl( emit, temp, &src0 ))
376 return FALSE;
377 }
378
379 if (!emit_op2( emit, inst, dest, src0, src1 ))
380 return FALSE;
381
382 if (need_temp)
383 release_temp( emit, temp );
384
385 return TRUE;
386 }
387
388
389 /* SVGA shaders may not refer to >1 constant register in a single
390 * instruction. This function checks for that usage and inserts a
391 * move to temporary if detected.
392 */
393 static boolean submit_op3( struct svga_shader_emitter *emit,
394 SVGA3dShaderInstToken inst,
395 SVGA3dShaderDestToken dest,
396 struct src_register src0,
397 struct src_register src1,
398 struct src_register src2 )
399 {
400 SVGA3dShaderDestToken temp0;
401 SVGA3dShaderDestToken temp1;
402 boolean need_temp0 = FALSE;
403 boolean need_temp1 = FALSE;
404 SVGA3dShaderRegType type0, type1, type2;
405
406 temp0.value = 0;
407 temp1.value = 0;
408 type0 = SVGA3dShaderGetRegType( src0.base.value );
409 type1 = SVGA3dShaderGetRegType( src1.base.value );
410 type2 = SVGA3dShaderGetRegType( src2.base.value );
411
412 if (inst.op != SVGA3DOP_SINCOS) {
413 if (type0 == SVGA3DREG_CONST &&
414 ((type1 == SVGA3DREG_CONST && src0.base.num != src1.base.num) ||
415 (type2 == SVGA3DREG_CONST && src0.base.num != src2.base.num)))
416 need_temp0 = TRUE;
417
418 if (type1 == SVGA3DREG_CONST &&
419 (type2 == SVGA3DREG_CONST && src1.base.num != src2.base.num))
420 need_temp1 = TRUE;
421 }
422
423 if (type0 == SVGA3DREG_INPUT &&
424 ((type1 == SVGA3DREG_INPUT && src0.base.num != src1.base.num) ||
425 (type2 == SVGA3DREG_INPUT && src0.base.num != src2.base.num)))
426 need_temp0 = TRUE;
427
428 if (type1 == SVGA3DREG_INPUT &&
429 (type2 == SVGA3DREG_INPUT && src1.base.num != src2.base.num))
430 need_temp1 = TRUE;
431
432 if (need_temp0) {
433 temp0 = get_temp( emit );
434
435 if (!emit_repl( emit, temp0, &src0 ))
436 return FALSE;
437 }
438
439 if (need_temp1) {
440 temp1 = get_temp( emit );
441
442 if (!emit_repl( emit, temp1, &src1 ))
443 return FALSE;
444 }
445
446 if (!emit_op3( emit, inst, dest, src0, src1, src2 ))
447 return FALSE;
448
449 if (need_temp1)
450 release_temp( emit, temp1 );
451 if (need_temp0)
452 release_temp( emit, temp0 );
453 return TRUE;
454 }
455
456
457
458
459 /* SVGA shaders may not refer to >1 constant register in a single
460 * instruction. This function checks for that usage and inserts a
461 * move to temporary if detected.
462 */
463 static boolean submit_op4( struct svga_shader_emitter *emit,
464 SVGA3dShaderInstToken inst,
465 SVGA3dShaderDestToken dest,
466 struct src_register src0,
467 struct src_register src1,
468 struct src_register src2,
469 struct src_register src3)
470 {
471 SVGA3dShaderDestToken temp0;
472 SVGA3dShaderDestToken temp3;
473 boolean need_temp0 = FALSE;
474 boolean need_temp3 = FALSE;
475 SVGA3dShaderRegType type0, type1, type2, type3;
476
477 temp0.value = 0;
478 temp3.value = 0;
479 type0 = SVGA3dShaderGetRegType( src0.base.value );
480 type1 = SVGA3dShaderGetRegType( src1.base.value );
481 type2 = SVGA3dShaderGetRegType( src2.base.value );
482 type3 = SVGA3dShaderGetRegType( src2.base.value );
483
484 /* Make life a little easier - this is only used by the TXD
485 * instruction which is guaranteed not to have a constant/input reg
486 * in one slot at least:
487 */
488 assert(type1 == SVGA3DREG_SAMPLER);
489
490 if (type0 == SVGA3DREG_CONST &&
491 ((type3 == SVGA3DREG_CONST && src0.base.num != src3.base.num) ||
492 (type2 == SVGA3DREG_CONST && src0.base.num != src2.base.num)))
493 need_temp0 = TRUE;
494
495 if (type3 == SVGA3DREG_CONST &&
496 (type2 == SVGA3DREG_CONST && src3.base.num != src2.base.num))
497 need_temp3 = TRUE;
498
499 if (type0 == SVGA3DREG_INPUT &&
500 ((type3 == SVGA3DREG_INPUT && src0.base.num != src3.base.num) ||
501 (type2 == SVGA3DREG_INPUT && src0.base.num != src2.base.num)))
502 need_temp0 = TRUE;
503
504 if (type3 == SVGA3DREG_INPUT &&
505 (type2 == SVGA3DREG_INPUT && src3.base.num != src2.base.num))
506 need_temp3 = TRUE;
507
508 if (need_temp0) {
509 temp0 = get_temp( emit );
510
511 if (!emit_repl( emit, temp0, &src0 ))
512 return FALSE;
513 }
514
515 if (need_temp3) {
516 temp3 = get_temp( emit );
517
518 if (!emit_repl( emit, temp3, &src3 ))
519 return FALSE;
520 }
521
522 if (!emit_op4( emit, inst, dest, src0, src1, src2, src3 ))
523 return FALSE;
524
525 if (need_temp3)
526 release_temp( emit, temp3 );
527 if (need_temp0)
528 release_temp( emit, temp0 );
529 return TRUE;
530 }
531
532
533 static boolean alias_src_dst( struct src_register src,
534 SVGA3dShaderDestToken dst )
535 {
536 if (src.base.num != dst.num)
537 return FALSE;
538
539 if (SVGA3dShaderGetRegType(dst.value) !=
540 SVGA3dShaderGetRegType(src.base.value))
541 return FALSE;
542
543 return TRUE;
544 }
545
546
547 static boolean submit_lrp(struct svga_shader_emitter *emit,
548 SVGA3dShaderDestToken dst,
549 struct src_register src0,
550 struct src_register src1,
551 struct src_register src2)
552 {
553 SVGA3dShaderDestToken tmp;
554 boolean need_dst_tmp = FALSE;
555
556 /* The dst reg must be a temporary, and not be the same as src0 or src2 */
557 if (SVGA3dShaderGetRegType(dst.value) != SVGA3DREG_TEMP ||
558 alias_src_dst(src0, dst) ||
559 alias_src_dst(src2, dst))
560 need_dst_tmp = TRUE;
561
562 if (need_dst_tmp) {
563 tmp = get_temp( emit );
564 tmp.mask = dst.mask;
565 }
566 else {
567 tmp = dst;
568 }
569
570 if (!submit_op3(emit, inst_token( SVGA3DOP_LRP ), tmp, src0, src1, src2))
571 return FALSE;
572
573 if (need_dst_tmp) {
574 if (!submit_op1(emit, inst_token( SVGA3DOP_MOV ), dst, src( tmp )))
575 return FALSE;
576 }
577
578 return TRUE;
579 }
580
581
582 static boolean emit_def_const( struct svga_shader_emitter *emit,
583 SVGA3dShaderConstType type,
584 unsigned idx,
585 float a,
586 float b,
587 float c,
588 float d )
589 {
590 SVGA3DOpDefArgs def;
591 SVGA3dShaderInstToken opcode;
592
593 switch (type) {
594 case SVGA3D_CONST_TYPE_FLOAT:
595 opcode = inst_token( SVGA3DOP_DEF );
596 def.dst = dst_register( SVGA3DREG_CONST, idx );
597 def.constValues[0] = a;
598 def.constValues[1] = b;
599 def.constValues[2] = c;
600 def.constValues[3] = d;
601 break;
602 case SVGA3D_CONST_TYPE_INT:
603 opcode = inst_token( SVGA3DOP_DEFI );
604 def.dst = dst_register( SVGA3DREG_CONSTINT, idx );
605 def.constIValues[0] = (int)a;
606 def.constIValues[1] = (int)b;
607 def.constIValues[2] = (int)c;
608 def.constIValues[3] = (int)d;
609 break;
610 default:
611 assert(0);
612 opcode = inst_token( SVGA3DOP_NOP );
613 break;
614 }
615
616 if (!emit_instruction(emit, opcode) ||
617 !svga_shader_emit_dwords( emit, def.values, Elements(def.values)))
618 return FALSE;
619
620 return TRUE;
621 }
622
623 static INLINE boolean
624 create_zero_immediate( struct svga_shader_emitter *emit )
625 {
626 unsigned idx = emit->nr_hw_float_const++;
627
628 /* Emit the constant (0, 0, -1, 1) and use swizzling to generate
629 * other useful vectors.
630 */
631 if (!emit_def_const( emit, SVGA3D_CONST_TYPE_FLOAT,
632 idx, 0, 0, -1, 1 ))
633 return FALSE;
634
635 emit->zero_immediate_idx = idx;
636 emit->created_zero_immediate = TRUE;
637
638 return TRUE;
639 }
640
641 static INLINE boolean
642 create_loop_const( struct svga_shader_emitter *emit )
643 {
644 unsigned idx = emit->nr_hw_int_const++;
645
646 if (!emit_def_const( emit, SVGA3D_CONST_TYPE_INT, idx,
647 255, /* iteration count */
648 0, /* initial value */
649 1, /* step size */
650 0 /* not used, must be 0 */))
651 return FALSE;
652
653 emit->loop_const_idx = idx;
654 emit->created_loop_const = TRUE;
655
656 return TRUE;
657 }
658
659 static INLINE boolean
660 create_sincos_consts( struct svga_shader_emitter *emit )
661 {
662 unsigned idx = emit->nr_hw_float_const++;
663
664 if (!emit_def_const( emit, SVGA3D_CONST_TYPE_FLOAT, idx,
665 -1.5500992e-006f,
666 -2.1701389e-005f,
667 0.0026041667f,
668 0.00026041668f ))
669 return FALSE;
670
671 emit->sincos_consts_idx = idx;
672 idx = emit->nr_hw_float_const++;
673
674 if (!emit_def_const( emit, SVGA3D_CONST_TYPE_FLOAT, idx,
675 -0.020833334f,
676 -0.12500000f,
677 1.0f,
678 0.50000000f ))
679 return FALSE;
680
681 emit->created_sincos_consts = TRUE;
682
683 return TRUE;
684 }
685
686 static INLINE boolean
687 create_arl_consts( struct svga_shader_emitter *emit )
688 {
689 int i;
690
691 for (i = 0; i < emit->num_arl_consts; i += 4) {
692 int j;
693 unsigned idx = emit->nr_hw_float_const++;
694 float vals[4];
695 for (j = 0; j < 4 && (j + i) < emit->num_arl_consts; ++j) {
696 vals[j] = emit->arl_consts[i + j].number;
697 emit->arl_consts[i + j].idx = idx;
698 switch (j) {
699 case 0:
700 emit->arl_consts[i + 0].swizzle = TGSI_SWIZZLE_X;
701 break;
702 case 1:
703 emit->arl_consts[i + 0].swizzle = TGSI_SWIZZLE_Y;
704 break;
705 case 2:
706 emit->arl_consts[i + 0].swizzle = TGSI_SWIZZLE_Z;
707 break;
708 case 3:
709 emit->arl_consts[i + 0].swizzle = TGSI_SWIZZLE_W;
710 break;
711 }
712 }
713 while (j < 4)
714 vals[j++] = 0;
715
716 if (!emit_def_const( emit, SVGA3D_CONST_TYPE_FLOAT, idx,
717 vals[0], vals[1],
718 vals[2], vals[3]))
719 return FALSE;
720 }
721
722 return TRUE;
723 }
724
725 static INLINE struct src_register
726 get_vface( struct svga_shader_emitter *emit )
727 {
728 assert(emit->emitted_vface);
729 return src_register(SVGA3DREG_MISCTYPE,
730 SVGA3DMISCREG_FACE);
731 }
732
733 /* returns {0, 0, 0, 1} immediate */
734 static INLINE struct src_register
735 get_zero_immediate( struct svga_shader_emitter *emit )
736 {
737 assert(emit->created_zero_immediate);
738 assert(emit->zero_immediate_idx >= 0);
739 return swizzle(src_register( SVGA3DREG_CONST,
740 emit->zero_immediate_idx),
741 0, 0, 0, 3);
742 }
743
744 /* returns {1, 1, 1, -1} immediate */
745 static INLINE struct src_register
746 get_pos_neg_one_immediate( struct svga_shader_emitter *emit )
747 {
748 assert(emit->created_zero_immediate);
749 assert(emit->zero_immediate_idx >= 0);
750 return swizzle(src_register( SVGA3DREG_CONST,
751 emit->zero_immediate_idx),
752 3, 3, 3, 2);
753 }
754
755 /* returns the loop const */
756 static INLINE struct src_register
757 get_loop_const( struct svga_shader_emitter *emit )
758 {
759 assert(emit->created_loop_const);
760 assert(emit->loop_const_idx >= 0);
761 return src_register( SVGA3DREG_CONSTINT,
762 emit->loop_const_idx );
763 }
764
765 /* returns a sincos const */
766 static INLINE struct src_register
767 get_sincos_const( struct svga_shader_emitter *emit,
768 unsigned index )
769 {
770 assert(emit->created_sincos_consts);
771 assert(emit->sincos_consts_idx >= 0);
772 assert(index == 0 || index == 1);
773 return src_register( SVGA3DREG_CONST,
774 emit->sincos_consts_idx + index );
775 }
776
777 static INLINE struct src_register
778 get_fake_arl_const( struct svga_shader_emitter *emit )
779 {
780 struct src_register reg;
781 int idx = 0, swizzle = 0, i;
782
783 for (i = 0; i < emit->num_arl_consts; ++ i) {
784 if (emit->arl_consts[i].arl_num == emit->current_arl) {
785 idx = emit->arl_consts[i].idx;
786 swizzle = emit->arl_consts[i].swizzle;
787 }
788 }
789
790 reg = src_register( SVGA3DREG_CONST, idx );
791 return scalar(reg, swizzle);
792 }
793
794 static INLINE struct src_register
795 get_tex_dimensions( struct svga_shader_emitter *emit, int sampler_num )
796 {
797 int idx;
798 struct src_register reg;
799
800 /* the width/height indexes start right after constants */
801 idx = emit->key.fkey.tex[sampler_num].width_height_idx +
802 emit->info.file_max[TGSI_FILE_CONSTANT] + 1;
803
804 reg = src_register( SVGA3DREG_CONST, idx );
805 return reg;
806 }
807
808 static boolean emit_fake_arl(struct svga_shader_emitter *emit,
809 const struct tgsi_full_instruction *insn)
810 {
811 const struct src_register src0 = translate_src_register(
812 emit, &insn->Src[0] );
813 struct src_register src1 = get_fake_arl_const( emit );
814 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
815 SVGA3dShaderDestToken tmp = get_temp( emit );
816
817 if (!submit_op1(emit, inst_token( SVGA3DOP_MOV ), tmp, src0))
818 return FALSE;
819
820 if (!submit_op2( emit, inst_token( SVGA3DOP_ADD ), tmp, src( tmp ),
821 src1))
822 return FALSE;
823
824 /* replicate the original swizzle */
825 src1 = src(tmp);
826 src1.base.swizzle = src0.base.swizzle;
827
828 return submit_op1( emit, inst_token( SVGA3DOP_MOVA ),
829 dst, src1 );
830 }
831
832 static boolean emit_if(struct svga_shader_emitter *emit,
833 const struct tgsi_full_instruction *insn)
834 {
835 struct src_register src0 = translate_src_register(
836 emit, &insn->Src[0] );
837 struct src_register zero = get_zero_immediate( emit );
838 SVGA3dShaderInstToken if_token = inst_token( SVGA3DOP_IFC );
839
840 if_token.control = SVGA3DOPCOMPC_NE;
841 zero = scalar(zero, TGSI_SWIZZLE_X);
842
843 if (SVGA3dShaderGetRegType(src0.base.value) == SVGA3DREG_CONST) {
844 /*
845 * Max different constant registers readable per IFC instruction is 1.
846 */
847
848 SVGA3dShaderDestToken tmp = get_temp( emit );
849
850 if (!submit_op1(emit, inst_token( SVGA3DOP_MOV ), tmp, src0))
851 return FALSE;
852
853 src0 = scalar(src( tmp ), TGSI_SWIZZLE_X);
854 }
855
856 emit->dynamic_branching_level++;
857
858 return (emit_instruction( emit, if_token ) &&
859 emit_src( emit, src0 ) &&
860 emit_src( emit, zero ) );
861 }
862
863 static boolean emit_endif(struct svga_shader_emitter *emit,
864 const struct tgsi_full_instruction *insn)
865 {
866 emit->dynamic_branching_level--;
867
868 return (emit_instruction( emit,
869 inst_token( SVGA3DOP_ENDIF )));
870 }
871
872 static boolean emit_else(struct svga_shader_emitter *emit,
873 const struct tgsi_full_instruction *insn)
874 {
875 return (emit_instruction( emit,
876 inst_token( SVGA3DOP_ELSE )));
877 }
878
879 /* Translate the following TGSI FLR instruction.
880 * FLR DST, SRC
881 * To the following SVGA3D instruction sequence.
882 * FRC TMP, SRC
883 * SUB DST, SRC, TMP
884 */
885 static boolean emit_floor(struct svga_shader_emitter *emit,
886 const struct tgsi_full_instruction *insn )
887 {
888 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
889 const struct src_register src0 = translate_src_register(
890 emit, &insn->Src[0] );
891 SVGA3dShaderDestToken temp = get_temp( emit );
892
893 /* FRC TMP, SRC */
894 if (!submit_op1( emit, inst_token( SVGA3DOP_FRC ), temp, src0 ))
895 return FALSE;
896
897 /* SUB DST, SRC, TMP */
898 if (!submit_op2( emit, inst_token( SVGA3DOP_ADD ), dst, src0,
899 negate( src( temp ) ) ))
900 return FALSE;
901
902 return TRUE;
903 }
904
905
906 /* Translate the following TGSI CMP instruction.
907 * CMP DST, SRC0, SRC1, SRC2
908 * To the following SVGA3D instruction sequence.
909 * CMP DST, SRC0, SRC2, SRC1
910 */
911 static boolean emit_cmp(struct svga_shader_emitter *emit,
912 const struct tgsi_full_instruction *insn )
913 {
914 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
915 const struct src_register src0 = translate_src_register(
916 emit, &insn->Src[0] );
917 const struct src_register src1 = translate_src_register(
918 emit, &insn->Src[1] );
919 const struct src_register src2 = translate_src_register(
920 emit, &insn->Src[2] );
921
922 if (emit->unit == PIPE_SHADER_VERTEX) {
923 SVGA3dShaderDestToken temp = get_temp(emit);
924 struct src_register zero = scalar(get_zero_immediate(emit), TGSI_SWIZZLE_X);
925
926 /* Since vertex shaders don't support the CMP instruction,
927 * simulate it with SLT and LRP instructions.
928 * SLT TMP, SRC0, 0.0
929 * LRP DST, TMP, SRC1, SRC2
930 */
931 if (!submit_op2(emit, inst_token(SVGA3DOP_SLT), temp, src0, zero))
932 return FALSE;
933 return submit_lrp(emit, dst, src(temp), src1, src2);
934 }
935
936 /* CMP DST, SRC0, SRC2, SRC1 */
937 return submit_op3( emit, inst_token( SVGA3DOP_CMP ), dst, src0, src2, src1);
938 }
939
940
941
942 /* Translate the following TGSI DIV instruction.
943 * DIV DST.xy, SRC0, SRC1
944 * To the following SVGA3D instruction sequence.
945 * RCP TMP.x, SRC1.xxxx
946 * RCP TMP.y, SRC1.yyyy
947 * MUL DST.xy, SRC0, TMP
948 */
949 static boolean emit_div(struct svga_shader_emitter *emit,
950 const struct tgsi_full_instruction *insn )
951 {
952 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
953 const struct src_register src0 = translate_src_register(
954 emit, &insn->Src[0] );
955 const struct src_register src1 = translate_src_register(
956 emit, &insn->Src[1] );
957 SVGA3dShaderDestToken temp = get_temp( emit );
958 int i;
959
960 /* For each enabled element, perform a RCP instruction. Note that
961 * RCP is scalar in SVGA3D:
962 */
963 for (i = 0; i < 4; i++) {
964 unsigned channel = 1 << i;
965 if (dst.mask & channel) {
966 /* RCP TMP.?, SRC1.???? */
967 if (!submit_op1( emit, inst_token( SVGA3DOP_RCP ),
968 writemask(temp, channel),
969 scalar(src1, i) ))
970 return FALSE;
971 }
972 }
973
974 /* Then multiply them out with a single mul:
975 *
976 * MUL DST, SRC0, TMP
977 */
978 if (!submit_op2( emit, inst_token( SVGA3DOP_MUL ), dst, src0,
979 src( temp ) ))
980 return FALSE;
981
982 return TRUE;
983 }
984
985 /* Translate the following TGSI DP2 instruction.
986 * DP2 DST, SRC1, SRC2
987 * To the following SVGA3D instruction sequence.
988 * MUL TMP, SRC1, SRC2
989 * ADD DST, TMP.xxxx, TMP.yyyy
990 */
991 static boolean emit_dp2(struct svga_shader_emitter *emit,
992 const struct tgsi_full_instruction *insn )
993 {
994 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
995 const struct src_register src0 = translate_src_register(
996 emit, &insn->Src[0] );
997 const struct src_register src1 = translate_src_register(
998 emit, &insn->Src[1] );
999 SVGA3dShaderDestToken temp = get_temp( emit );
1000 struct src_register temp_src0, temp_src1;
1001
1002 /* MUL TMP, SRC1, SRC2 */
1003 if (!submit_op2( emit, inst_token( SVGA3DOP_MUL ), temp, src0, src1 ))
1004 return FALSE;
1005
1006 temp_src0 = scalar(src( temp ), TGSI_SWIZZLE_X);
1007 temp_src1 = scalar(src( temp ), TGSI_SWIZZLE_Y);
1008
1009 /* ADD DST, TMP.xxxx, TMP.yyyy */
1010 if (!submit_op2( emit, inst_token( SVGA3DOP_ADD ), dst,
1011 temp_src0, temp_src1 ))
1012 return FALSE;
1013
1014 return TRUE;
1015 }
1016
1017
1018 /* Translate the following TGSI DPH instruction.
1019 * DPH DST, SRC1, SRC2
1020 * To the following SVGA3D instruction sequence.
1021 * DP3 TMP, SRC1, SRC2
1022 * ADD DST, TMP, SRC2.wwww
1023 */
1024 static boolean emit_dph(struct svga_shader_emitter *emit,
1025 const struct tgsi_full_instruction *insn )
1026 {
1027 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
1028 const struct src_register src0 = translate_src_register(
1029 emit, &insn->Src[0] );
1030 struct src_register src1 = translate_src_register(
1031 emit, &insn->Src[1] );
1032 SVGA3dShaderDestToken temp = get_temp( emit );
1033
1034 /* DP3 TMP, SRC1, SRC2 */
1035 if (!submit_op2( emit, inst_token( SVGA3DOP_DP3 ), temp, src0, src1 ))
1036 return FALSE;
1037
1038 src1 = scalar(src1, TGSI_SWIZZLE_W);
1039
1040 /* ADD DST, TMP, SRC2.wwww */
1041 if (!submit_op2( emit, inst_token( SVGA3DOP_ADD ), dst,
1042 src( temp ), src1 ))
1043 return FALSE;
1044
1045 return TRUE;
1046 }
1047
1048 /* Translate the following TGSI DST instruction.
1049 * NRM DST, SRC
1050 * To the following SVGA3D instruction sequence.
1051 * DP3 TMP, SRC, SRC
1052 * RSQ TMP, TMP
1053 * MUL DST, SRC, TMP
1054 */
1055 static boolean emit_nrm(struct svga_shader_emitter *emit,
1056 const struct tgsi_full_instruction *insn )
1057 {
1058 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
1059 const struct src_register src0 = translate_src_register(
1060 emit, &insn->Src[0] );
1061 SVGA3dShaderDestToken temp = get_temp( emit );
1062
1063 /* DP3 TMP, SRC, SRC */
1064 if (!submit_op2( emit, inst_token( SVGA3DOP_DP3 ), temp, src0, src0 ))
1065 return FALSE;
1066
1067 /* RSQ TMP, TMP */
1068 if (!submit_op1( emit, inst_token( SVGA3DOP_RSQ ), temp, src( temp )))
1069 return FALSE;
1070
1071 /* MUL DST, SRC, TMP */
1072 if (!submit_op2( emit, inst_token( SVGA3DOP_MUL ), dst,
1073 src0, src( temp )))
1074 return FALSE;
1075
1076 return TRUE;
1077
1078 }
1079
1080 static boolean do_emit_sincos(struct svga_shader_emitter *emit,
1081 SVGA3dShaderDestToken dst,
1082 struct src_register src0)
1083 {
1084 src0 = scalar(src0, TGSI_SWIZZLE_X);
1085
1086 return submit_op1( emit, inst_token( SVGA3DOP_SINCOS ),
1087 dst, src0 );
1088 }
1089
1090 static boolean emit_sincos(struct svga_shader_emitter *emit,
1091 const struct tgsi_full_instruction *insn)
1092 {
1093 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
1094 struct src_register src0 = translate_src_register(
1095 emit, &insn->Src[0] );
1096 SVGA3dShaderDestToken temp = get_temp( emit );
1097
1098 /* SCS TMP SRC */
1099 if (!do_emit_sincos(emit, writemask(temp, TGSI_WRITEMASK_XY), src0 ))
1100 return FALSE;
1101
1102 /* MOV DST TMP */
1103 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ), dst, src( temp ) ))
1104 return FALSE;
1105
1106 return TRUE;
1107 }
1108
1109 /*
1110 * SCS TMP SRC
1111 * MOV DST TMP.yyyy
1112 */
1113 static boolean emit_sin(struct svga_shader_emitter *emit,
1114 const struct tgsi_full_instruction *insn )
1115 {
1116 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
1117 struct src_register src0 = translate_src_register(
1118 emit, &insn->Src[0] );
1119 SVGA3dShaderDestToken temp = get_temp( emit );
1120
1121 /* SCS TMP SRC */
1122 if (!do_emit_sincos(emit, writemask(temp, TGSI_WRITEMASK_Y), src0))
1123 return FALSE;
1124
1125 src0 = scalar(src( temp ), TGSI_SWIZZLE_Y);
1126
1127 /* MOV DST TMP.yyyy */
1128 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ), dst, src0 ))
1129 return FALSE;
1130
1131 return TRUE;
1132 }
1133
1134 /*
1135 * SCS TMP SRC
1136 * MOV DST TMP.xxxx
1137 */
1138 static boolean emit_cos(struct svga_shader_emitter *emit,
1139 const struct tgsi_full_instruction *insn )
1140 {
1141 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
1142 struct src_register src0 = translate_src_register(
1143 emit, &insn->Src[0] );
1144 SVGA3dShaderDestToken temp = get_temp( emit );
1145
1146 /* SCS TMP SRC */
1147 if (!do_emit_sincos( emit, writemask(temp, TGSI_WRITEMASK_X), src0 ))
1148 return FALSE;
1149
1150 src0 = scalar(src( temp ), TGSI_SWIZZLE_X);
1151
1152 /* MOV DST TMP.xxxx */
1153 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ), dst, src0 ))
1154 return FALSE;
1155
1156 return TRUE;
1157 }
1158
1159 static boolean emit_ssg(struct svga_shader_emitter *emit,
1160 const struct tgsi_full_instruction *insn )
1161 {
1162 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
1163 struct src_register src0 = translate_src_register(
1164 emit, &insn->Src[0] );
1165 SVGA3dShaderDestToken temp0 = get_temp( emit );
1166 SVGA3dShaderDestToken temp1 = get_temp( emit );
1167 struct src_register zero, one;
1168
1169 if (emit->unit == PIPE_SHADER_VERTEX) {
1170 /* SGN DST, SRC0, TMP0, TMP1 */
1171 return submit_op3( emit, inst_token( SVGA3DOP_SGN ), dst, src0,
1172 src( temp0 ), src( temp1 ) );
1173 }
1174
1175 zero = get_zero_immediate( emit );
1176 one = scalar( zero, TGSI_SWIZZLE_W );
1177 zero = scalar( zero, TGSI_SWIZZLE_X );
1178
1179 /* CMP TMP0, SRC0, one, zero */
1180 if (!submit_op3( emit, inst_token( SVGA3DOP_CMP ),
1181 writemask( temp0, dst.mask ), src0, one, zero ))
1182 return FALSE;
1183
1184 /* CMP TMP1, negate(SRC0), negate(one), zero */
1185 if (!submit_op3( emit, inst_token( SVGA3DOP_CMP ),
1186 writemask( temp1, dst.mask ), negate( src0 ), negate( one ),
1187 zero ))
1188 return FALSE;
1189
1190 /* ADD DST, TMP0, TMP1 */
1191 return submit_op2( emit, inst_token( SVGA3DOP_ADD ), dst, src( temp0 ),
1192 src( temp1 ) );
1193 }
1194
1195 /*
1196 * ADD DST SRC0, negate(SRC0)
1197 */
1198 static boolean emit_sub(struct svga_shader_emitter *emit,
1199 const struct tgsi_full_instruction *insn)
1200 {
1201 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
1202 struct src_register src0 = translate_src_register(
1203 emit, &insn->Src[0] );
1204 struct src_register src1 = translate_src_register(
1205 emit, &insn->Src[1] );
1206
1207 src1 = negate(src1);
1208
1209 if (!submit_op2( emit, inst_token( SVGA3DOP_ADD ), dst,
1210 src0, src1 ))
1211 return FALSE;
1212
1213 return TRUE;
1214 }
1215
1216
1217 static boolean emit_kil(struct svga_shader_emitter *emit,
1218 const struct tgsi_full_instruction *insn )
1219 {
1220 const struct tgsi_full_src_register *reg = &insn->Src[0];
1221 struct src_register src0, srcIn;
1222 /* is the W component tested in another position? */
1223 const boolean w_tested = (reg->Register.SwizzleW == reg->Register.SwizzleX ||
1224 reg->Register.SwizzleW == reg->Register.SwizzleY ||
1225 reg->Register.SwizzleW == reg->Register.SwizzleZ);
1226 const boolean special = (reg->Register.Absolute ||
1227 reg->Register.Negate ||
1228 reg->Register.Indirect ||
1229 reg->Register.SwizzleX != 0 ||
1230 reg->Register.SwizzleY != 1 ||
1231 reg->Register.SwizzleZ != 2 ||
1232 reg->Register.File != TGSI_FILE_TEMPORARY);
1233 SVGA3dShaderDestToken temp;
1234
1235 src0 = srcIn = translate_src_register( emit, reg );
1236
1237 if (special || !w_tested) {
1238 /* need a temp reg */
1239 temp = get_temp( emit );
1240 }
1241
1242 if (special) {
1243 /* move the source into a temp register */
1244 submit_op1( emit, inst_token( SVGA3DOP_MOV ),
1245 writemask( temp, TGSI_WRITEMASK_XYZ ),
1246 src0 );
1247
1248 src0 = src( temp );
1249 }
1250
1251 /* do the texkill (on the xyz components) */
1252 if (!submit_op0( emit, inst_token( SVGA3DOP_TEXKILL ), dst(src0) ))
1253 return FALSE;
1254
1255 if (!w_tested) {
1256 /* need to emit a second texkill to test the W component */
1257 /* put src.wwww into temp register */
1258 if (!submit_op1(emit,
1259 inst_token( SVGA3DOP_MOV ),
1260 writemask( temp, TGSI_WRITEMASK_XYZ ),
1261 scalar(srcIn, TGSI_SWIZZLE_W)))
1262 return FALSE;
1263
1264 /* second texkill */
1265 if (!submit_op0( emit, inst_token( SVGA3DOP_TEXKILL ), temp ))
1266 return FALSE;
1267 }
1268
1269 return TRUE;
1270 }
1271
1272
1273 /* mesa state tracker always emits kilp as an unconditional
1274 * kil */
1275 static boolean emit_kilp(struct svga_shader_emitter *emit,
1276 const struct tgsi_full_instruction *insn )
1277 {
1278 SVGA3dShaderInstToken inst;
1279 SVGA3dShaderDestToken temp;
1280 struct src_register one = scalar( get_zero_immediate( emit ),
1281 TGSI_SWIZZLE_W );
1282
1283 inst = inst_token( SVGA3DOP_TEXKILL );
1284
1285 /* texkill doesn't allow negation on the operand so lets move
1286 * negation of {1} to a temp register */
1287 temp = get_temp( emit );
1288 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ), temp,
1289 negate( one ) ))
1290 return FALSE;
1291
1292 return submit_op0( emit, inst, temp );
1293 }
1294
1295 /* Implement conditionals by initializing destination reg to 'fail',
1296 * then set predicate reg with UFOP_SETP, then move 'pass' to dest
1297 * based on predicate reg.
1298 *
1299 * SETP src0, cmp, src1 -- do this first to avoid aliasing problems.
1300 * MOV dst, fail
1301 * MOV dst, pass, p0
1302 */
1303 static boolean
1304 emit_conditional(struct svga_shader_emitter *emit,
1305 unsigned compare_func,
1306 SVGA3dShaderDestToken dst,
1307 struct src_register src0,
1308 struct src_register src1,
1309 struct src_register pass,
1310 struct src_register fail)
1311 {
1312 SVGA3dShaderDestToken pred_reg = dst_register( SVGA3DREG_PREDICATE, 0 );
1313 SVGA3dShaderInstToken setp_token, mov_token;
1314 setp_token = inst_token( SVGA3DOP_SETP );
1315
1316 switch (compare_func) {
1317 case PIPE_FUNC_NEVER:
1318 return submit_op1( emit, inst_token( SVGA3DOP_MOV ),
1319 dst, fail );
1320 break;
1321 case PIPE_FUNC_LESS:
1322 setp_token.control = SVGA3DOPCOMP_LT;
1323 break;
1324 case PIPE_FUNC_EQUAL:
1325 setp_token.control = SVGA3DOPCOMP_EQ;
1326 break;
1327 case PIPE_FUNC_LEQUAL:
1328 setp_token.control = SVGA3DOPCOMP_LE;
1329 break;
1330 case PIPE_FUNC_GREATER:
1331 setp_token.control = SVGA3DOPCOMP_GT;
1332 break;
1333 case PIPE_FUNC_NOTEQUAL:
1334 setp_token.control = SVGA3DOPCOMPC_NE;
1335 break;
1336 case PIPE_FUNC_GEQUAL:
1337 setp_token.control = SVGA3DOPCOMP_GE;
1338 break;
1339 case PIPE_FUNC_ALWAYS:
1340 return submit_op1( emit, inst_token( SVGA3DOP_MOV ),
1341 dst, pass );
1342 break;
1343 }
1344
1345 /* SETP src0, COMPOP, src1 */
1346 if (!submit_op2( emit, setp_token, pred_reg,
1347 src0, src1 ))
1348 return FALSE;
1349
1350 mov_token = inst_token( SVGA3DOP_MOV );
1351
1352 /* MOV dst, fail */
1353 if (!submit_op1( emit, mov_token, dst,
1354 fail ))
1355 return FALSE;
1356
1357 /* MOV dst, pass (predicated)
1358 *
1359 * Note that the predicate reg (and possible modifiers) is passed
1360 * as the first source argument.
1361 */
1362 mov_token.predicated = 1;
1363 if (!submit_op2( emit, mov_token, dst,
1364 src( pred_reg ), pass ))
1365 return FALSE;
1366
1367 return TRUE;
1368 }
1369
1370
1371 static boolean
1372 emit_select(struct svga_shader_emitter *emit,
1373 unsigned compare_func,
1374 SVGA3dShaderDestToken dst,
1375 struct src_register src0,
1376 struct src_register src1 )
1377 {
1378 /* There are some SVGA instructions which implement some selects
1379 * directly, but they are only available in the vertex shader.
1380 */
1381 if (emit->unit == PIPE_SHADER_VERTEX) {
1382 switch (compare_func) {
1383 case PIPE_FUNC_GEQUAL:
1384 return submit_op2( emit, inst_token( SVGA3DOP_SGE ), dst, src0, src1 );
1385 case PIPE_FUNC_LEQUAL:
1386 return submit_op2( emit, inst_token( SVGA3DOP_SGE ), dst, src1, src0 );
1387 case PIPE_FUNC_GREATER:
1388 return submit_op2( emit, inst_token( SVGA3DOP_SLT ), dst, src1, src0 );
1389 case PIPE_FUNC_LESS:
1390 return submit_op2( emit, inst_token( SVGA3DOP_SLT ), dst, src0, src1 );
1391 default:
1392 break;
1393 }
1394 }
1395
1396
1397 /* Otherwise, need to use the setp approach:
1398 */
1399 {
1400 struct src_register one, zero;
1401 /* zero immediate is 0,0,0,1 */
1402 zero = get_zero_immediate( emit );
1403 one = scalar( zero, TGSI_SWIZZLE_W );
1404 zero = scalar( zero, TGSI_SWIZZLE_X );
1405
1406 return emit_conditional(
1407 emit,
1408 compare_func,
1409 dst,
1410 src0,
1411 src1,
1412 one, zero);
1413 }
1414 }
1415
1416
1417 static boolean emit_select_op(struct svga_shader_emitter *emit,
1418 unsigned compare,
1419 const struct tgsi_full_instruction *insn)
1420 {
1421 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
1422 struct src_register src0 = translate_src_register(
1423 emit, &insn->Src[0] );
1424 struct src_register src1 = translate_src_register(
1425 emit, &insn->Src[1] );
1426
1427 return emit_select( emit, compare, dst, src0, src1 );
1428 }
1429
1430
1431 /* Translate texture instructions to SVGA3D representation.
1432 */
1433 static boolean emit_tex2(struct svga_shader_emitter *emit,
1434 const struct tgsi_full_instruction *insn,
1435 SVGA3dShaderDestToken dst )
1436 {
1437 SVGA3dShaderInstToken inst;
1438 struct src_register texcoord;
1439 struct src_register sampler;
1440 SVGA3dShaderDestToken tmp;
1441
1442 inst.value = 0;
1443
1444 switch (insn->Instruction.Opcode) {
1445 case TGSI_OPCODE_TEX:
1446 inst.op = SVGA3DOP_TEX;
1447 break;
1448 case TGSI_OPCODE_TXP:
1449 inst.op = SVGA3DOP_TEX;
1450 inst.control = SVGA3DOPCONT_PROJECT;
1451 break;
1452 case TGSI_OPCODE_TXB:
1453 inst.op = SVGA3DOP_TEX;
1454 inst.control = SVGA3DOPCONT_BIAS;
1455 break;
1456 case TGSI_OPCODE_TXL:
1457 inst.op = SVGA3DOP_TEXLDL;
1458 break;
1459 default:
1460 assert(0);
1461 return FALSE;
1462 }
1463
1464 texcoord = translate_src_register( emit, &insn->Src[0] );
1465 sampler = translate_src_register( emit, &insn->Src[1] );
1466
1467 if (emit->key.fkey.tex[sampler.base.num].unnormalized ||
1468 emit->dynamic_branching_level > 0)
1469 tmp = get_temp( emit );
1470
1471 /* Can't do mipmapping inside dynamic branch constructs. Force LOD
1472 * zero in that case.
1473 */
1474 if (emit->dynamic_branching_level > 0 &&
1475 inst.op == SVGA3DOP_TEX &&
1476 SVGA3dShaderGetRegType(texcoord.base.value) == SVGA3DREG_TEMP) {
1477 struct src_register zero = get_zero_immediate( emit );
1478
1479 /* MOV tmp, texcoord */
1480 if (!submit_op1( emit,
1481 inst_token( SVGA3DOP_MOV ),
1482 tmp,
1483 texcoord ))
1484 return FALSE;
1485
1486 /* MOV tmp.w, zero */
1487 if (!submit_op1( emit,
1488 inst_token( SVGA3DOP_MOV ),
1489 writemask( tmp, TGSI_WRITEMASK_W ),
1490 scalar( zero, TGSI_SWIZZLE_X )))
1491 return FALSE;
1492
1493 texcoord = src( tmp );
1494 inst.op = SVGA3DOP_TEXLDL;
1495 }
1496
1497 /* Explicit normalization of texcoords:
1498 */
1499 if (emit->key.fkey.tex[sampler.base.num].unnormalized) {
1500 struct src_register wh = get_tex_dimensions( emit, sampler.base.num );
1501
1502 /* MUL tmp, SRC0, WH */
1503 if (!submit_op2( emit, inst_token( SVGA3DOP_MUL ),
1504 tmp, texcoord, wh ))
1505 return FALSE;
1506
1507 texcoord = src( tmp );
1508 }
1509
1510 return submit_op2( emit, inst, dst, texcoord, sampler );
1511 }
1512
1513
1514
1515
1516 /* Translate texture instructions to SVGA3D representation.
1517 */
1518 static boolean emit_tex4(struct svga_shader_emitter *emit,
1519 const struct tgsi_full_instruction *insn,
1520 SVGA3dShaderDestToken dst )
1521 {
1522 SVGA3dShaderInstToken inst;
1523 struct src_register texcoord;
1524 struct src_register ddx;
1525 struct src_register ddy;
1526 struct src_register sampler;
1527
1528 texcoord = translate_src_register( emit, &insn->Src[0] );
1529 ddx = translate_src_register( emit, &insn->Src[1] );
1530 ddy = translate_src_register( emit, &insn->Src[2] );
1531 sampler = translate_src_register( emit, &insn->Src[3] );
1532
1533 inst.value = 0;
1534
1535 switch (insn->Instruction.Opcode) {
1536 case TGSI_OPCODE_TXD:
1537 inst.op = SVGA3DOP_TEXLDD; /* 4 args! */
1538 break;
1539 default:
1540 assert(0);
1541 return FALSE;
1542 }
1543
1544 return submit_op4( emit, inst, dst, texcoord, sampler, ddx, ddy );
1545 }
1546
1547
1548 /**
1549 * Emit texture swizzle code.
1550 */
1551 static boolean emit_tex_swizzle( struct svga_shader_emitter *emit,
1552 SVGA3dShaderDestToken dst,
1553 struct src_register src,
1554 unsigned swizzle_x,
1555 unsigned swizzle_y,
1556 unsigned swizzle_z,
1557 unsigned swizzle_w)
1558 {
1559 const unsigned swizzleIn[4] = {swizzle_x, swizzle_y, swizzle_z, swizzle_w};
1560 unsigned srcSwizzle[4];
1561 unsigned srcWritemask = 0x0, zeroWritemask = 0x0, oneWritemask = 0x0;
1562 int i;
1563
1564 /* build writemasks and srcSwizzle terms */
1565 for (i = 0; i < 4; i++) {
1566 if (swizzleIn[i] == PIPE_SWIZZLE_ZERO) {
1567 srcSwizzle[i] = TGSI_SWIZZLE_X + i;
1568 zeroWritemask |= (1 << i);
1569 }
1570 else if (swizzleIn[i] == PIPE_SWIZZLE_ONE) {
1571 srcSwizzle[i] = TGSI_SWIZZLE_X + i;
1572 oneWritemask |= (1 << i);
1573 }
1574 else {
1575 srcSwizzle[i] = swizzleIn[i];
1576 srcWritemask |= (1 << i);
1577 }
1578 }
1579
1580 /* write x/y/z/w comps */
1581 if (dst.mask & srcWritemask) {
1582 if (!submit_op1(emit,
1583 inst_token(SVGA3DOP_MOV),
1584 writemask(dst, srcWritemask),
1585 swizzle(src,
1586 srcSwizzle[0],
1587 srcSwizzle[1],
1588 srcSwizzle[2],
1589 srcSwizzle[3])))
1590 return FALSE;
1591 }
1592
1593 /* write 0 comps */
1594 if (dst.mask & zeroWritemask) {
1595 if (!submit_op1(emit,
1596 inst_token(SVGA3DOP_MOV),
1597 writemask(dst, zeroWritemask),
1598 scalar(get_zero_immediate(emit), TGSI_SWIZZLE_X)))
1599 return FALSE;
1600 }
1601
1602 /* write 1 comps */
1603 if (dst.mask & oneWritemask) {
1604 if (!submit_op1(emit,
1605 inst_token(SVGA3DOP_MOV),
1606 writemask(dst, oneWritemask),
1607 scalar(get_zero_immediate(emit), TGSI_SWIZZLE_W)))
1608 return FALSE;
1609 }
1610
1611 return TRUE;
1612 }
1613
1614
1615 static boolean emit_tex(struct svga_shader_emitter *emit,
1616 const struct tgsi_full_instruction *insn )
1617 {
1618 SVGA3dShaderDestToken dst =
1619 translate_dst_register( emit, insn, 0 );
1620 struct src_register src0 =
1621 translate_src_register( emit, &insn->Src[0] );
1622 struct src_register src1 =
1623 translate_src_register( emit, &insn->Src[1] );
1624
1625 SVGA3dShaderDestToken tex_result;
1626 const unsigned unit = src1.base.num;
1627
1628 /* check for shadow samplers */
1629 boolean compare = (emit->key.fkey.tex[unit].compare_mode ==
1630 PIPE_TEX_COMPARE_R_TO_TEXTURE);
1631
1632 /* texture swizzle */
1633 boolean swizzle = (emit->key.fkey.tex[unit].swizzle_r != PIPE_SWIZZLE_RED ||
1634 emit->key.fkey.tex[unit].swizzle_g != PIPE_SWIZZLE_GREEN ||
1635 emit->key.fkey.tex[unit].swizzle_b != PIPE_SWIZZLE_BLUE ||
1636 emit->key.fkey.tex[unit].swizzle_a != PIPE_SWIZZLE_ALPHA);
1637
1638 /* If doing compare processing or tex swizzle, need to put fetched color into
1639 * a temporary so it can be used as a source later on.
1640 */
1641 if (compare || swizzle) {
1642 tex_result = get_temp( emit );
1643 }
1644 else {
1645 tex_result = dst;
1646 }
1647
1648 switch(insn->Instruction.Opcode) {
1649 case TGSI_OPCODE_TEX:
1650 case TGSI_OPCODE_TXB:
1651 case TGSI_OPCODE_TXP:
1652 case TGSI_OPCODE_TXL:
1653 if (!emit_tex2( emit, insn, tex_result ))
1654 return FALSE;
1655 break;
1656 case TGSI_OPCODE_TXD:
1657 if (!emit_tex4( emit, insn, tex_result ))
1658 return FALSE;
1659 break;
1660 default:
1661 assert(0);
1662 }
1663
1664
1665 if (compare) {
1666 SVGA3dShaderDestToken dst2;
1667
1668 if (swizzle)
1669 dst2 = tex_result;
1670 else
1671 dst2 = dst;
1672
1673 if (dst.mask & TGSI_WRITEMASK_XYZ) {
1674 SVGA3dShaderDestToken src0_zdivw = get_temp( emit );
1675 /* When sampling a depth texture, the result of the comparison is in
1676 * the Y component.
1677 */
1678 struct src_register tex_src_x = scalar(src(tex_result), TGSI_SWIZZLE_Y);
1679 struct src_register r_coord;
1680
1681 if (insn->Instruction.Opcode == TGSI_OPCODE_TXP) {
1682 /* Divide texcoord R by Q */
1683 if (!submit_op1( emit, inst_token( SVGA3DOP_RCP ),
1684 writemask(src0_zdivw, TGSI_WRITEMASK_X),
1685 scalar(src0, TGSI_SWIZZLE_W) ))
1686 return FALSE;
1687
1688 if (!submit_op2( emit, inst_token( SVGA3DOP_MUL ),
1689 writemask(src0_zdivw, TGSI_WRITEMASK_X),
1690 scalar(src0, TGSI_SWIZZLE_Z),
1691 scalar(src(src0_zdivw), TGSI_SWIZZLE_X) ))
1692 return FALSE;
1693
1694 r_coord = scalar(src(src0_zdivw), TGSI_SWIZZLE_X);
1695 }
1696 else {
1697 r_coord = scalar(src0, TGSI_SWIZZLE_Z);
1698 }
1699
1700 /* Compare texture sample value against R component of texcoord */
1701 if (!emit_select(emit,
1702 emit->key.fkey.tex[unit].compare_func,
1703 writemask( dst2, TGSI_WRITEMASK_XYZ ),
1704 r_coord,
1705 tex_src_x))
1706 return FALSE;
1707 }
1708
1709 if (dst.mask & TGSI_WRITEMASK_W) {
1710 struct src_register one =
1711 scalar( get_zero_immediate( emit ), TGSI_SWIZZLE_W );
1712
1713 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ),
1714 writemask( dst2, TGSI_WRITEMASK_W ),
1715 one ))
1716 return FALSE;
1717 }
1718 }
1719
1720 if (swizzle) {
1721 /* swizzle from tex_result to dst */
1722 emit_tex_swizzle(emit,
1723 dst, src(tex_result),
1724 emit->key.fkey.tex[unit].swizzle_r,
1725 emit->key.fkey.tex[unit].swizzle_g,
1726 emit->key.fkey.tex[unit].swizzle_b,
1727 emit->key.fkey.tex[unit].swizzle_a);
1728 }
1729
1730 return TRUE;
1731 }
1732
1733 static boolean emit_bgnloop2( struct svga_shader_emitter *emit,
1734 const struct tgsi_full_instruction *insn )
1735 {
1736 SVGA3dShaderInstToken inst = inst_token( SVGA3DOP_LOOP );
1737 struct src_register loop_reg = src_register( SVGA3DREG_LOOP, 0 );
1738 struct src_register const_int = get_loop_const( emit );
1739
1740 emit->dynamic_branching_level++;
1741
1742 return (emit_instruction( emit, inst ) &&
1743 emit_src( emit, loop_reg ) &&
1744 emit_src( emit, const_int ) );
1745 }
1746
1747 static boolean emit_endloop2( struct svga_shader_emitter *emit,
1748 const struct tgsi_full_instruction *insn )
1749 {
1750 SVGA3dShaderInstToken inst = inst_token( SVGA3DOP_ENDLOOP );
1751
1752 emit->dynamic_branching_level--;
1753
1754 return emit_instruction( emit, inst );
1755 }
1756
1757 static boolean emit_brk( struct svga_shader_emitter *emit,
1758 const struct tgsi_full_instruction *insn )
1759 {
1760 SVGA3dShaderInstToken inst = inst_token( SVGA3DOP_BREAK );
1761 return emit_instruction( emit, inst );
1762 }
1763
1764 static boolean emit_scalar_op1( struct svga_shader_emitter *emit,
1765 unsigned opcode,
1766 const struct tgsi_full_instruction *insn )
1767 {
1768 SVGA3dShaderInstToken inst;
1769 SVGA3dShaderDestToken dst;
1770 struct src_register src;
1771
1772 inst = inst_token( opcode );
1773 dst = translate_dst_register( emit, insn, 0 );
1774 src = translate_src_register( emit, &insn->Src[0] );
1775 src = scalar( src, TGSI_SWIZZLE_X );
1776
1777 return submit_op1( emit, inst, dst, src );
1778 }
1779
1780
1781 static boolean emit_simple_instruction(struct svga_shader_emitter *emit,
1782 unsigned opcode,
1783 const struct tgsi_full_instruction *insn )
1784 {
1785 const struct tgsi_full_src_register *src = insn->Src;
1786 SVGA3dShaderInstToken inst;
1787 SVGA3dShaderDestToken dst;
1788
1789 inst = inst_token( opcode );
1790 dst = translate_dst_register( emit, insn, 0 );
1791
1792 switch (insn->Instruction.NumSrcRegs) {
1793 case 0:
1794 return submit_op0( emit, inst, dst );
1795 case 1:
1796 return submit_op1( emit, inst, dst,
1797 translate_src_register( emit, &src[0] ));
1798 case 2:
1799 return submit_op2( emit, inst, dst,
1800 translate_src_register( emit, &src[0] ),
1801 translate_src_register( emit, &src[1] ) );
1802 case 3:
1803 return submit_op3( emit, inst, dst,
1804 translate_src_register( emit, &src[0] ),
1805 translate_src_register( emit, &src[1] ),
1806 translate_src_register( emit, &src[2] ) );
1807 default:
1808 assert(0);
1809 return FALSE;
1810 }
1811 }
1812
1813
1814 static boolean emit_deriv(struct svga_shader_emitter *emit,
1815 const struct tgsi_full_instruction *insn )
1816 {
1817 if (emit->dynamic_branching_level > 0 &&
1818 insn->Src[0].Register.File == TGSI_FILE_TEMPORARY)
1819 {
1820 struct src_register zero = get_zero_immediate( emit );
1821 SVGA3dShaderDestToken dst =
1822 translate_dst_register( emit, insn, 0 );
1823
1824 /* Deriv opcodes not valid inside dynamic branching, workaround
1825 * by zeroing out the destination.
1826 */
1827 if (!submit_op1(emit,
1828 inst_token( SVGA3DOP_MOV ),
1829 dst,
1830 scalar(zero, TGSI_SWIZZLE_X)))
1831 return FALSE;
1832
1833 return TRUE;
1834 }
1835 else {
1836 unsigned opcode;
1837 const struct tgsi_full_src_register *reg = &insn->Src[0];
1838 SVGA3dShaderInstToken inst;
1839 SVGA3dShaderDestToken dst;
1840 struct src_register src0;
1841
1842 switch (insn->Instruction.Opcode) {
1843 case TGSI_OPCODE_DDX:
1844 opcode = SVGA3DOP_DSX;
1845 break;
1846 case TGSI_OPCODE_DDY:
1847 opcode = SVGA3DOP_DSY;
1848 break;
1849 default:
1850 return FALSE;
1851 }
1852
1853 inst = inst_token( opcode );
1854 dst = translate_dst_register( emit, insn, 0 );
1855 src0 = translate_src_register( emit, reg );
1856
1857 /* We cannot use negate or abs on source to dsx/dsy instruction.
1858 */
1859 if (reg->Register.Absolute ||
1860 reg->Register.Negate) {
1861 SVGA3dShaderDestToken temp = get_temp( emit );
1862
1863 if (!emit_repl( emit, temp, &src0 ))
1864 return FALSE;
1865 }
1866
1867 return submit_op1( emit, inst, dst, src0 );
1868 }
1869 }
1870
1871 static boolean emit_arl(struct svga_shader_emitter *emit,
1872 const struct tgsi_full_instruction *insn)
1873 {
1874 ++emit->current_arl;
1875 if (emit->unit == PIPE_SHADER_FRAGMENT) {
1876 /* MOVA not present in pixel shader instruction set.
1877 * Ignore this instruction altogether since it is
1878 * only used for loop counters -- and for that
1879 * we reference aL directly.
1880 */
1881 return TRUE;
1882 }
1883 if (svga_arl_needs_adjustment( emit )) {
1884 return emit_fake_arl( emit, insn );
1885 } else {
1886 /* no need to adjust, just emit straight arl */
1887 return emit_simple_instruction(emit, SVGA3DOP_MOVA, insn);
1888 }
1889 }
1890
1891 static boolean emit_pow(struct svga_shader_emitter *emit,
1892 const struct tgsi_full_instruction *insn)
1893 {
1894 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
1895 struct src_register src0 = translate_src_register(
1896 emit, &insn->Src[0] );
1897 struct src_register src1 = translate_src_register(
1898 emit, &insn->Src[1] );
1899 boolean need_tmp = FALSE;
1900
1901 /* POW can only output to a temporary */
1902 if (insn->Dst[0].Register.File != TGSI_FILE_TEMPORARY)
1903 need_tmp = TRUE;
1904
1905 /* POW src1 must not be the same register as dst */
1906 if (alias_src_dst( src1, dst ))
1907 need_tmp = TRUE;
1908
1909 /* it's a scalar op */
1910 src0 = scalar( src0, TGSI_SWIZZLE_X );
1911 src1 = scalar( src1, TGSI_SWIZZLE_X );
1912
1913 if (need_tmp) {
1914 SVGA3dShaderDestToken tmp = writemask(get_temp( emit ), TGSI_WRITEMASK_X );
1915
1916 if (!submit_op2(emit, inst_token( SVGA3DOP_POW ), tmp, src0, src1))
1917 return FALSE;
1918
1919 return submit_op1(emit, inst_token( SVGA3DOP_MOV ), dst, scalar(src(tmp), 0) );
1920 }
1921 else {
1922 return submit_op2(emit, inst_token( SVGA3DOP_POW ), dst, src0, src1);
1923 }
1924 }
1925
1926 static boolean emit_xpd(struct svga_shader_emitter *emit,
1927 const struct tgsi_full_instruction *insn)
1928 {
1929 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
1930 const struct src_register src0 = translate_src_register(
1931 emit, &insn->Src[0] );
1932 const struct src_register src1 = translate_src_register(
1933 emit, &insn->Src[1] );
1934 boolean need_dst_tmp = FALSE;
1935
1936 /* XPD can only output to a temporary */
1937 if (SVGA3dShaderGetRegType(dst.value) != SVGA3DREG_TEMP)
1938 need_dst_tmp = TRUE;
1939
1940 /* The dst reg must not be the same as src0 or src1*/
1941 if (alias_src_dst(src0, dst) ||
1942 alias_src_dst(src1, dst))
1943 need_dst_tmp = TRUE;
1944
1945 if (need_dst_tmp) {
1946 SVGA3dShaderDestToken tmp = get_temp( emit );
1947
1948 /* Obey DX9 restrictions on mask:
1949 */
1950 tmp.mask = dst.mask & TGSI_WRITEMASK_XYZ;
1951
1952 if (!submit_op2(emit, inst_token( SVGA3DOP_CRS ), tmp, src0, src1))
1953 return FALSE;
1954
1955 if (!submit_op1(emit, inst_token( SVGA3DOP_MOV ), dst, src( tmp )))
1956 return FALSE;
1957 }
1958 else {
1959 if (!submit_op2(emit, inst_token( SVGA3DOP_CRS ), dst, src0, src1))
1960 return FALSE;
1961 }
1962
1963 /* Need to emit 1.0 to dst.w?
1964 */
1965 if (dst.mask & TGSI_WRITEMASK_W) {
1966 struct src_register zero = get_zero_immediate( emit );
1967
1968 if (!submit_op1(emit,
1969 inst_token( SVGA3DOP_MOV ),
1970 writemask(dst, TGSI_WRITEMASK_W),
1971 zero))
1972 return FALSE;
1973 }
1974
1975 return TRUE;
1976 }
1977
1978
1979 static boolean emit_lrp(struct svga_shader_emitter *emit,
1980 const struct tgsi_full_instruction *insn)
1981 {
1982 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
1983 const struct src_register src0 = translate_src_register(
1984 emit, &insn->Src[0] );
1985 const struct src_register src1 = translate_src_register(
1986 emit, &insn->Src[1] );
1987 const struct src_register src2 = translate_src_register(
1988 emit, &insn->Src[2] );
1989
1990 return submit_lrp(emit, dst, src0, src1, src2);
1991 }
1992
1993
1994 static boolean emit_dst_insn(struct svga_shader_emitter *emit,
1995 const struct tgsi_full_instruction *insn )
1996 {
1997 if (emit->unit == PIPE_SHADER_VERTEX) {
1998 /* SVGA/DX9 has a DST instruction, but only for vertex shaders:
1999 */
2000 return emit_simple_instruction(emit, SVGA3DOP_DST, insn);
2001 }
2002 else {
2003
2004 /* result[0] = 1 * 1;
2005 * result[1] = a[1] * b[1];
2006 * result[2] = a[2] * 1;
2007 * result[3] = 1 * b[3];
2008 */
2009
2010 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
2011 SVGA3dShaderDestToken tmp;
2012 const struct src_register src0 = translate_src_register(
2013 emit, &insn->Src[0] );
2014 const struct src_register src1 = translate_src_register(
2015 emit, &insn->Src[1] );
2016 struct src_register zero = get_zero_immediate( emit );
2017 boolean need_tmp = FALSE;
2018
2019 if (SVGA3dShaderGetRegType(dst.value) != SVGA3DREG_TEMP ||
2020 alias_src_dst(src0, dst) ||
2021 alias_src_dst(src1, dst))
2022 need_tmp = TRUE;
2023
2024 if (need_tmp) {
2025 tmp = get_temp( emit );
2026 }
2027 else {
2028 tmp = dst;
2029 }
2030
2031 /* tmp.xw = 1.0
2032 */
2033 if (tmp.mask & TGSI_WRITEMASK_XW) {
2034 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ),
2035 writemask(tmp, TGSI_WRITEMASK_XW ),
2036 scalar( zero, 3 )))
2037 return FALSE;
2038 }
2039
2040 /* tmp.yz = src0
2041 */
2042 if (tmp.mask & TGSI_WRITEMASK_YZ) {
2043 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ),
2044 writemask(tmp, TGSI_WRITEMASK_YZ ),
2045 src0))
2046 return FALSE;
2047 }
2048
2049 /* tmp.yw = tmp * src1
2050 */
2051 if (tmp.mask & TGSI_WRITEMASK_YW) {
2052 if (!submit_op2( emit, inst_token( SVGA3DOP_MUL ),
2053 writemask(tmp, TGSI_WRITEMASK_YW ),
2054 src(tmp),
2055 src1))
2056 return FALSE;
2057 }
2058
2059 /* dst = tmp
2060 */
2061 if (need_tmp) {
2062 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ),
2063 dst,
2064 src(tmp)))
2065 return FALSE;
2066 }
2067 }
2068
2069 return TRUE;
2070 }
2071
2072
2073 static boolean emit_exp(struct svga_shader_emitter *emit,
2074 const struct tgsi_full_instruction *insn)
2075 {
2076 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
2077 struct src_register src0 =
2078 translate_src_register( emit, &insn->Src[0] );
2079 struct src_register zero = get_zero_immediate( emit );
2080 SVGA3dShaderDestToken fraction;
2081
2082 if (dst.mask & TGSI_WRITEMASK_Y)
2083 fraction = dst;
2084 else if (dst.mask & TGSI_WRITEMASK_X)
2085 fraction = get_temp( emit );
2086 else
2087 fraction.value = 0;
2088
2089 /* If y is being written, fill it with src0 - floor(src0).
2090 */
2091 if (dst.mask & TGSI_WRITEMASK_XY) {
2092 if (!submit_op1( emit, inst_token( SVGA3DOP_FRC ),
2093 writemask( fraction, TGSI_WRITEMASK_Y ),
2094 src0 ))
2095 return FALSE;
2096 }
2097
2098 /* If x is being written, fill it with 2 ^ floor(src0).
2099 */
2100 if (dst.mask & TGSI_WRITEMASK_X) {
2101 if (!submit_op2( emit, inst_token( SVGA3DOP_ADD ),
2102 writemask( dst, TGSI_WRITEMASK_X ),
2103 src0,
2104 scalar( negate( src( fraction ) ), TGSI_SWIZZLE_Y ) ) )
2105 return FALSE;
2106
2107 if (!submit_op1( emit, inst_token( SVGA3DOP_EXP ),
2108 writemask( dst, TGSI_WRITEMASK_X ),
2109 scalar( src( dst ), TGSI_SWIZZLE_X ) ) )
2110 return FALSE;
2111
2112 if (!(dst.mask & TGSI_WRITEMASK_Y))
2113 release_temp( emit, fraction );
2114 }
2115
2116 /* If z is being written, fill it with 2 ^ src0 (partial precision).
2117 */
2118 if (dst.mask & TGSI_WRITEMASK_Z) {
2119 if (!submit_op1( emit, inst_token( SVGA3DOP_EXPP ),
2120 writemask( dst, TGSI_WRITEMASK_Z ),
2121 src0 ) )
2122 return FALSE;
2123 }
2124
2125 /* If w is being written, fill it with one.
2126 */
2127 if (dst.mask & TGSI_WRITEMASK_W) {
2128 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ),
2129 writemask(dst, TGSI_WRITEMASK_W),
2130 scalar( zero, TGSI_SWIZZLE_W ) ))
2131 return FALSE;
2132 }
2133
2134 return TRUE;
2135 }
2136
2137 static boolean emit_lit(struct svga_shader_emitter *emit,
2138 const struct tgsi_full_instruction *insn )
2139 {
2140 if (emit->unit == PIPE_SHADER_VERTEX) {
2141 /* SVGA/DX9 has a LIT instruction, but only for vertex shaders:
2142 */
2143 return emit_simple_instruction(emit, SVGA3DOP_LIT, insn);
2144 }
2145 else {
2146
2147 /* D3D vs. GL semantics can be fairly easily accomodated by
2148 * variations on this sequence.
2149 *
2150 * GL:
2151 * tmp.y = src.x
2152 * tmp.z = pow(src.y,src.w)
2153 * p0 = src0.xxxx > 0
2154 * result = zero.wxxw
2155 * (p0) result.yz = tmp
2156 *
2157 * D3D:
2158 * tmp.y = src.x
2159 * tmp.z = pow(src.y,src.w)
2160 * p0 = src0.xxyy > 0
2161 * result = zero.wxxw
2162 * (p0) result.yz = tmp
2163 *
2164 * Will implement the GL version for now.
2165 */
2166
2167 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
2168 SVGA3dShaderDestToken tmp = get_temp( emit );
2169 const struct src_register src0 = translate_src_register(
2170 emit, &insn->Src[0] );
2171 struct src_register zero = get_zero_immediate( emit );
2172
2173 /* tmp = pow(src.y, src.w)
2174 */
2175 if (dst.mask & TGSI_WRITEMASK_Z) {
2176 if (!submit_op2(emit, inst_token( SVGA3DOP_POW ),
2177 tmp,
2178 scalar(src0, 1),
2179 scalar(src0, 3)))
2180 return FALSE;
2181 }
2182
2183 /* tmp.y = src.x
2184 */
2185 if (dst.mask & TGSI_WRITEMASK_Y) {
2186 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ),
2187 writemask(tmp, TGSI_WRITEMASK_Y ),
2188 scalar(src0, 0)))
2189 return FALSE;
2190 }
2191
2192 /* Can't quite do this with emit conditional due to the extra
2193 * writemask on the predicated mov:
2194 */
2195 {
2196 SVGA3dShaderDestToken pred_reg = dst_register( SVGA3DREG_PREDICATE, 0 );
2197 SVGA3dShaderInstToken setp_token, mov_token;
2198 struct src_register predsrc;
2199
2200 setp_token = inst_token( SVGA3DOP_SETP );
2201 mov_token = inst_token( SVGA3DOP_MOV );
2202
2203 setp_token.control = SVGA3DOPCOMP_GT;
2204
2205 /* D3D vs GL semantics:
2206 */
2207 if (0)
2208 predsrc = swizzle(src0, 0, 0, 1, 1); /* D3D */
2209 else
2210 predsrc = swizzle(src0, 0, 0, 0, 0); /* GL */
2211
2212 /* SETP src0.xxyy, GT, {0}.x */
2213 if (!submit_op2( emit, setp_token, pred_reg,
2214 predsrc,
2215 swizzle(zero, 0, 0, 0, 0) ))
2216 return FALSE;
2217
2218 /* MOV dst, fail */
2219 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ), dst,
2220 swizzle(zero, 3, 0, 0, 3 )))
2221 return FALSE;
2222
2223 /* MOV dst.yz, tmp (predicated)
2224 *
2225 * Note that the predicate reg (and possible modifiers) is passed
2226 * as the first source argument.
2227 */
2228 if (dst.mask & TGSI_WRITEMASK_YZ) {
2229 mov_token.predicated = 1;
2230 if (!submit_op2( emit, mov_token,
2231 writemask(dst, TGSI_WRITEMASK_YZ),
2232 src( pred_reg ), src( tmp ) ))
2233 return FALSE;
2234 }
2235 }
2236 }
2237
2238 return TRUE;
2239 }
2240
2241
2242
2243
2244 static boolean emit_ex2( struct svga_shader_emitter *emit,
2245 const struct tgsi_full_instruction *insn )
2246 {
2247 SVGA3dShaderInstToken inst;
2248 SVGA3dShaderDestToken dst;
2249 struct src_register src0;
2250
2251 inst = inst_token( SVGA3DOP_EXP );
2252 dst = translate_dst_register( emit, insn, 0 );
2253 src0 = translate_src_register( emit, &insn->Src[0] );
2254 src0 = scalar( src0, TGSI_SWIZZLE_X );
2255
2256 if (dst.mask != TGSI_WRITEMASK_XYZW) {
2257 SVGA3dShaderDestToken tmp = get_temp( emit );
2258
2259 if (!submit_op1( emit, inst, tmp, src0 ))
2260 return FALSE;
2261
2262 return submit_op1( emit, inst_token( SVGA3DOP_MOV ),
2263 dst,
2264 scalar( src( tmp ), TGSI_SWIZZLE_X ) );
2265 }
2266
2267 return submit_op1( emit, inst, dst, src0 );
2268 }
2269
2270
2271 static boolean emit_log(struct svga_shader_emitter *emit,
2272 const struct tgsi_full_instruction *insn)
2273 {
2274 SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
2275 struct src_register src0 =
2276 translate_src_register( emit, &insn->Src[0] );
2277 struct src_register zero = get_zero_immediate( emit );
2278 SVGA3dShaderDestToken abs_tmp;
2279 struct src_register abs_src0;
2280 SVGA3dShaderDestToken log2_abs;
2281
2282 abs_tmp.value = 0;
2283
2284 if (dst.mask & TGSI_WRITEMASK_Z)
2285 log2_abs = dst;
2286 else if (dst.mask & TGSI_WRITEMASK_XY)
2287 log2_abs = get_temp( emit );
2288 else
2289 log2_abs.value = 0;
2290
2291 /* If z is being written, fill it with log2( abs( src0 ) ).
2292 */
2293 if (dst.mask & TGSI_WRITEMASK_XYZ) {
2294 if (!src0.base.srcMod || src0.base.srcMod == SVGA3DSRCMOD_ABS)
2295 abs_src0 = src0;
2296 else {
2297 abs_tmp = get_temp( emit );
2298
2299 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ),
2300 abs_tmp,
2301 src0 ) )
2302 return FALSE;
2303
2304 abs_src0 = src( abs_tmp );
2305 }
2306
2307 abs_src0 = absolute( scalar( abs_src0, TGSI_SWIZZLE_X ) );
2308
2309 if (!submit_op1( emit, inst_token( SVGA3DOP_LOG ),
2310 writemask( log2_abs, TGSI_WRITEMASK_Z ),
2311 abs_src0 ) )
2312 return FALSE;
2313 }
2314
2315 if (dst.mask & TGSI_WRITEMASK_XY) {
2316 SVGA3dShaderDestToken floor_log2;
2317
2318 if (dst.mask & TGSI_WRITEMASK_X)
2319 floor_log2 = dst;
2320 else
2321 floor_log2 = get_temp( emit );
2322
2323 /* If x is being written, fill it with floor( log2( abs( src0 ) ) ).
2324 */
2325 if (!submit_op1( emit, inst_token( SVGA3DOP_FRC ),
2326 writemask( floor_log2, TGSI_WRITEMASK_X ),
2327 scalar( src( log2_abs ), TGSI_SWIZZLE_Z ) ) )
2328 return FALSE;
2329
2330 if (!submit_op2( emit, inst_token( SVGA3DOP_ADD ),
2331 writemask( floor_log2, TGSI_WRITEMASK_X ),
2332 scalar( src( log2_abs ), TGSI_SWIZZLE_Z ),
2333 negate( src( floor_log2 ) ) ) )
2334 return FALSE;
2335
2336 /* If y is being written, fill it with
2337 * abs ( src0 ) / ( 2 ^ floor( log2( abs( src0 ) ) ) ).
2338 */
2339 if (dst.mask & TGSI_WRITEMASK_Y) {
2340 if (!submit_op1( emit, inst_token( SVGA3DOP_EXP ),
2341 writemask( dst, TGSI_WRITEMASK_Y ),
2342 negate( scalar( src( floor_log2 ),
2343 TGSI_SWIZZLE_X ) ) ) )
2344 return FALSE;
2345
2346 if (!submit_op2( emit, inst_token( SVGA3DOP_MUL ),
2347 writemask( dst, TGSI_WRITEMASK_Y ),
2348 src( dst ),
2349 abs_src0 ) )
2350 return FALSE;
2351 }
2352
2353 if (!(dst.mask & TGSI_WRITEMASK_X))
2354 release_temp( emit, floor_log2 );
2355
2356 if (!(dst.mask & TGSI_WRITEMASK_Z))
2357 release_temp( emit, log2_abs );
2358 }
2359
2360 if (dst.mask & TGSI_WRITEMASK_XYZ && src0.base.srcMod &&
2361 src0.base.srcMod != SVGA3DSRCMOD_ABS)
2362 release_temp( emit, abs_tmp );
2363
2364 /* If w is being written, fill it with one.
2365 */
2366 if (dst.mask & TGSI_WRITEMASK_W) {
2367 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ),
2368 writemask(dst, TGSI_WRITEMASK_W),
2369 scalar( zero, TGSI_SWIZZLE_W ) ))
2370 return FALSE;
2371 }
2372
2373 return TRUE;
2374 }
2375
2376
2377 static boolean emit_bgnsub( struct svga_shader_emitter *emit,
2378 unsigned position,
2379 const struct tgsi_full_instruction *insn )
2380 {
2381 unsigned i;
2382
2383 /* Note that we've finished the main function and are now emitting
2384 * subroutines. This affects how we terminate the generated
2385 * shader.
2386 */
2387 emit->in_main_func = FALSE;
2388
2389 for (i = 0; i < emit->nr_labels; i++) {
2390 if (emit->label[i] == position) {
2391 return (emit_instruction( emit, inst_token( SVGA3DOP_RET ) ) &&
2392 emit_instruction( emit, inst_token( SVGA3DOP_LABEL ) ) &&
2393 emit_src( emit, src_register( SVGA3DREG_LABEL, i )));
2394 }
2395 }
2396
2397 assert(0);
2398 return TRUE;
2399 }
2400
2401 static boolean emit_call( struct svga_shader_emitter *emit,
2402 const struct tgsi_full_instruction *insn )
2403 {
2404 unsigned position = insn->Label.Label;
2405 unsigned i;
2406
2407 for (i = 0; i < emit->nr_labels; i++) {
2408 if (emit->label[i] == position)
2409 break;
2410 }
2411
2412 if (emit->nr_labels == Elements(emit->label))
2413 return FALSE;
2414
2415 if (i == emit->nr_labels) {
2416 emit->label[i] = position;
2417 emit->nr_labels++;
2418 }
2419
2420 return (emit_instruction( emit, inst_token( SVGA3DOP_CALL ) ) &&
2421 emit_src( emit, src_register( SVGA3DREG_LABEL, i )));
2422 }
2423
2424
2425 static boolean emit_end( struct svga_shader_emitter *emit )
2426 {
2427 if (emit->unit == PIPE_SHADER_VERTEX) {
2428 return emit_vs_postamble( emit );
2429 }
2430 else {
2431 return emit_ps_postamble( emit );
2432 }
2433 }
2434
2435
2436
2437 static boolean svga_emit_instruction( struct svga_shader_emitter *emit,
2438 unsigned position,
2439 const struct tgsi_full_instruction *insn )
2440 {
2441 switch (insn->Instruction.Opcode) {
2442
2443 case TGSI_OPCODE_ARL:
2444 return emit_arl( emit, insn );
2445
2446 case TGSI_OPCODE_TEX:
2447 case TGSI_OPCODE_TXB:
2448 case TGSI_OPCODE_TXP:
2449 case TGSI_OPCODE_TXL:
2450 case TGSI_OPCODE_TXD:
2451 return emit_tex( emit, insn );
2452
2453 case TGSI_OPCODE_DDX:
2454 case TGSI_OPCODE_DDY:
2455 return emit_deriv( emit, insn );
2456
2457 case TGSI_OPCODE_BGNSUB:
2458 return emit_bgnsub( emit, position, insn );
2459
2460 case TGSI_OPCODE_ENDSUB:
2461 return TRUE;
2462
2463 case TGSI_OPCODE_CAL:
2464 return emit_call( emit, insn );
2465
2466 case TGSI_OPCODE_FLR:
2467 case TGSI_OPCODE_TRUNC: /* should be TRUNC, not FLR */
2468 return emit_floor( emit, insn );
2469
2470 case TGSI_OPCODE_CMP:
2471 return emit_cmp( emit, insn );
2472
2473 case TGSI_OPCODE_DIV:
2474 return emit_div( emit, insn );
2475
2476 case TGSI_OPCODE_DP2:
2477 return emit_dp2( emit, insn );
2478
2479 case TGSI_OPCODE_DPH:
2480 return emit_dph( emit, insn );
2481
2482 case TGSI_OPCODE_NRM:
2483 return emit_nrm( emit, insn );
2484
2485 case TGSI_OPCODE_COS:
2486 return emit_cos( emit, insn );
2487
2488 case TGSI_OPCODE_SIN:
2489 return emit_sin( emit, insn );
2490
2491 case TGSI_OPCODE_SCS:
2492 return emit_sincos( emit, insn );
2493
2494 case TGSI_OPCODE_END:
2495 /* TGSI always finishes the main func with an END */
2496 return emit_end( emit );
2497
2498 case TGSI_OPCODE_KIL:
2499 return emit_kil( emit, insn );
2500
2501 /* Selection opcodes. The underlying language is fairly
2502 * non-orthogonal about these.
2503 */
2504 case TGSI_OPCODE_SEQ:
2505 return emit_select_op( emit, PIPE_FUNC_EQUAL, insn );
2506
2507 case TGSI_OPCODE_SNE:
2508 return emit_select_op( emit, PIPE_FUNC_NOTEQUAL, insn );
2509
2510 case TGSI_OPCODE_SGT:
2511 return emit_select_op( emit, PIPE_FUNC_GREATER, insn );
2512
2513 case TGSI_OPCODE_SGE:
2514 return emit_select_op( emit, PIPE_FUNC_GEQUAL, insn );
2515
2516 case TGSI_OPCODE_SLT:
2517 return emit_select_op( emit, PIPE_FUNC_LESS, insn );
2518
2519 case TGSI_OPCODE_SLE:
2520 return emit_select_op( emit, PIPE_FUNC_LEQUAL, insn );
2521
2522 case TGSI_OPCODE_SUB:
2523 return emit_sub( emit, insn );
2524
2525 case TGSI_OPCODE_POW:
2526 return emit_pow( emit, insn );
2527
2528 case TGSI_OPCODE_EX2:
2529 return emit_ex2( emit, insn );
2530
2531 case TGSI_OPCODE_EXP:
2532 return emit_exp( emit, insn );
2533
2534 case TGSI_OPCODE_LOG:
2535 return emit_log( emit, insn );
2536
2537 case TGSI_OPCODE_LG2:
2538 return emit_scalar_op1( emit, SVGA3DOP_LOG, insn );
2539
2540 case TGSI_OPCODE_RSQ:
2541 return emit_scalar_op1( emit, SVGA3DOP_RSQ, insn );
2542
2543 case TGSI_OPCODE_RCP:
2544 return emit_scalar_op1( emit, SVGA3DOP_RCP, insn );
2545
2546 case TGSI_OPCODE_CONT:
2547 case TGSI_OPCODE_RET:
2548 /* This is a noop -- we tell mesa that we can't support RET
2549 * within a function (early return), so this will always be
2550 * followed by an ENDSUB.
2551 */
2552 return TRUE;
2553
2554 /* These aren't actually used by any of the frontends we care
2555 * about:
2556 */
2557 case TGSI_OPCODE_CLAMP:
2558 case TGSI_OPCODE_ROUND:
2559 case TGSI_OPCODE_AND:
2560 case TGSI_OPCODE_OR:
2561 case TGSI_OPCODE_I2F:
2562 case TGSI_OPCODE_NOT:
2563 case TGSI_OPCODE_SHL:
2564 case TGSI_OPCODE_ISHR:
2565 case TGSI_OPCODE_XOR:
2566 return FALSE;
2567
2568 case TGSI_OPCODE_IF:
2569 return emit_if( emit, insn );
2570 case TGSI_OPCODE_ELSE:
2571 return emit_else( emit, insn );
2572 case TGSI_OPCODE_ENDIF:
2573 return emit_endif( emit, insn );
2574
2575 case TGSI_OPCODE_BGNLOOP:
2576 return emit_bgnloop2( emit, insn );
2577 case TGSI_OPCODE_ENDLOOP:
2578 return emit_endloop2( emit, insn );
2579 case TGSI_OPCODE_BRK:
2580 return emit_brk( emit, insn );
2581
2582 case TGSI_OPCODE_XPD:
2583 return emit_xpd( emit, insn );
2584
2585 case TGSI_OPCODE_KILP:
2586 return emit_kilp( emit, insn );
2587
2588 case TGSI_OPCODE_DST:
2589 return emit_dst_insn( emit, insn );
2590
2591 case TGSI_OPCODE_LIT:
2592 return emit_lit( emit, insn );
2593
2594 case TGSI_OPCODE_LRP:
2595 return emit_lrp( emit, insn );
2596
2597 case TGSI_OPCODE_SSG:
2598 return emit_ssg( emit, insn );
2599
2600 default: {
2601 unsigned opcode = translate_opcode(insn->Instruction.Opcode);
2602
2603 if (opcode == SVGA3DOP_LAST_INST)
2604 return FALSE;
2605
2606 if (!emit_simple_instruction( emit, opcode, insn ))
2607 return FALSE;
2608 }
2609 }
2610
2611 return TRUE;
2612 }
2613
2614
2615 static boolean svga_emit_immediate( struct svga_shader_emitter *emit,
2616 struct tgsi_full_immediate *imm)
2617 {
2618 static const float id[4] = {0,0,0,1};
2619 float value[4];
2620 unsigned i;
2621
2622 assert(1 <= imm->Immediate.NrTokens && imm->Immediate.NrTokens <= 5);
2623 for (i = 0; i < imm->Immediate.NrTokens - 1; i++)
2624 value[i] = imm->u[i].Float;
2625
2626 for ( ; i < 4; i++ )
2627 value[i] = id[i];
2628
2629 return emit_def_const( emit, SVGA3D_CONST_TYPE_FLOAT,
2630 emit->imm_start + emit->internal_imm_count++,
2631 value[0], value[1], value[2], value[3]);
2632 }
2633
2634 static boolean make_immediate( struct svga_shader_emitter *emit,
2635 float a,
2636 float b,
2637 float c,
2638 float d,
2639 struct src_register *out )
2640 {
2641 unsigned idx = emit->nr_hw_float_const++;
2642
2643 if (!emit_def_const( emit, SVGA3D_CONST_TYPE_FLOAT,
2644 idx, a, b, c, d ))
2645 return FALSE;
2646
2647 *out = src_register( SVGA3DREG_CONST, idx );
2648
2649 return TRUE;
2650 }
2651
2652 static boolean emit_vs_preamble( struct svga_shader_emitter *emit )
2653 {
2654 if (!emit->key.vkey.need_prescale) {
2655 if (!make_immediate( emit, 0, 0, .5, .5,
2656 &emit->imm_0055))
2657 return FALSE;
2658 }
2659
2660 return TRUE;
2661 }
2662
2663 static boolean emit_ps_preamble( struct svga_shader_emitter *emit )
2664 {
2665 if (emit->ps_reads_pos && emit->info.reads_z) {
2666 /*
2667 * Assemble the position from various bits of inputs. Depth and W are
2668 * passed in a texcoord this is due to D3D's vPos not hold Z or W.
2669 * Also fixup the perspective interpolation.
2670 *
2671 * temp_pos.xy = vPos.xy
2672 * temp_pos.w = rcp(texcoord1.w);
2673 * temp_pos.z = texcoord1.z * temp_pos.w;
2674 */
2675 if (!submit_op1( emit,
2676 inst_token(SVGA3DOP_MOV),
2677 writemask( emit->ps_temp_pos, TGSI_WRITEMASK_XY ),
2678 emit->ps_true_pos ))
2679 return FALSE;
2680
2681 if (!submit_op1( emit,
2682 inst_token(SVGA3DOP_RCP),
2683 writemask( emit->ps_temp_pos, TGSI_WRITEMASK_W ),
2684 scalar( emit->ps_depth_pos, TGSI_SWIZZLE_W ) ))
2685 return FALSE;
2686
2687 if (!submit_op2( emit,
2688 inst_token(SVGA3DOP_MUL),
2689 writemask( emit->ps_temp_pos, TGSI_WRITEMASK_Z ),
2690 scalar( emit->ps_depth_pos, TGSI_SWIZZLE_Z ),
2691 scalar( src(emit->ps_temp_pos), TGSI_SWIZZLE_W ) ))
2692 return FALSE;
2693 }
2694
2695 return TRUE;
2696 }
2697
2698 static boolean emit_ps_postamble( struct svga_shader_emitter *emit )
2699 {
2700 unsigned i;
2701
2702 /* PS oDepth is incredibly fragile and it's very hard to catch the
2703 * types of usage that break it during shader emit. Easier just to
2704 * redirect the main program to a temporary and then only touch
2705 * oDepth with a hand-crafted MOV below.
2706 */
2707 if (SVGA3dShaderGetRegType(emit->true_pos.value) != 0) {
2708
2709 if (!submit_op1( emit,
2710 inst_token(SVGA3DOP_MOV),
2711 emit->true_pos,
2712 scalar(src(emit->temp_pos), TGSI_SWIZZLE_Z) ))
2713 return FALSE;
2714 }
2715
2716 for (i = 0; i < PIPE_MAX_COLOR_BUFS; i++) {
2717 if (SVGA3dShaderGetRegType(emit->true_col[i].value) != 0) {
2718
2719 /* Potentially override output colors with white for XOR
2720 * logicop workaround.
2721 */
2722 if (emit->unit == PIPE_SHADER_FRAGMENT &&
2723 emit->key.fkey.white_fragments) {
2724
2725 struct src_register one = scalar( get_zero_immediate( emit ),
2726 TGSI_SWIZZLE_W );
2727
2728 if (!submit_op1( emit,
2729 inst_token(SVGA3DOP_MOV),
2730 emit->true_col[i],
2731 one ))
2732 return FALSE;
2733 }
2734 else {
2735 if (!submit_op1( emit,
2736 inst_token(SVGA3DOP_MOV),
2737 emit->true_col[i],
2738 src(emit->temp_col[i]) ))
2739 return FALSE;
2740 }
2741 }
2742 }
2743
2744 return TRUE;
2745 }
2746
2747 static boolean emit_vs_postamble( struct svga_shader_emitter *emit )
2748 {
2749 /* PSIZ output is incredibly fragile and it's very hard to catch
2750 * the types of usage that break it during shader emit. Easier
2751 * just to redirect the main program to a temporary and then only
2752 * touch PSIZ with a hand-crafted MOV below.
2753 */
2754 if (SVGA3dShaderGetRegType(emit->true_psiz.value) != 0) {
2755
2756 if (!submit_op1( emit,
2757 inst_token(SVGA3DOP_MOV),
2758 emit->true_psiz,
2759 scalar(src(emit->temp_psiz), TGSI_SWIZZLE_X) ))
2760 return FALSE;
2761 }
2762
2763 /* Need to perform various manipulations on vertex position to cope
2764 * with the different GL and D3D clip spaces.
2765 */
2766 if (emit->key.vkey.need_prescale) {
2767 SVGA3dShaderDestToken temp_pos = emit->temp_pos;
2768 SVGA3dShaderDestToken depth = emit->depth_pos;
2769 SVGA3dShaderDestToken pos = emit->true_pos;
2770 unsigned offset = emit->info.file_max[TGSI_FILE_CONSTANT] + 1;
2771 struct src_register prescale_scale = src_register( SVGA3DREG_CONST,
2772 offset + 0 );
2773 struct src_register prescale_trans = src_register( SVGA3DREG_CONST,
2774 offset + 1 );
2775
2776 if (!submit_op1( emit,
2777 inst_token(SVGA3DOP_MOV),
2778 writemask(depth, TGSI_WRITEMASK_W),
2779 scalar(src(temp_pos), TGSI_SWIZZLE_W) ))
2780 return FALSE;
2781
2782 /* MUL temp_pos.xyz, temp_pos, prescale.scale
2783 * MAD result.position, temp_pos.wwww, prescale.trans, temp_pos
2784 * --> Note that prescale.trans.w == 0
2785 */
2786 if (!submit_op2( emit,
2787 inst_token(SVGA3DOP_MUL),
2788 writemask(temp_pos, TGSI_WRITEMASK_XYZ),
2789 src(temp_pos),
2790 prescale_scale ))
2791 return FALSE;
2792
2793 if (!submit_op3( emit,
2794 inst_token(SVGA3DOP_MAD),
2795 pos,
2796 swizzle(src(temp_pos), 3, 3, 3, 3),
2797 prescale_trans,
2798 src(temp_pos)))
2799 return FALSE;
2800
2801 /* Also write to depth value */
2802 if (!submit_op3( emit,
2803 inst_token(SVGA3DOP_MAD),
2804 writemask(depth, TGSI_WRITEMASK_Z),
2805 swizzle(src(temp_pos), 3, 3, 3, 3),
2806 prescale_trans,
2807 src(temp_pos) ))
2808 return FALSE;
2809 }
2810 else {
2811 SVGA3dShaderDestToken temp_pos = emit->temp_pos;
2812 SVGA3dShaderDestToken depth = emit->depth_pos;
2813 SVGA3dShaderDestToken pos = emit->true_pos;
2814 struct src_register imm_0055 = emit->imm_0055;
2815
2816 /* Adjust GL clipping coordinate space to hardware (D3D-style):
2817 *
2818 * DP4 temp_pos.z, {0,0,.5,.5}, temp_pos
2819 * MOV result.position, temp_pos
2820 */
2821 if (!submit_op2( emit,
2822 inst_token(SVGA3DOP_DP4),
2823 writemask(temp_pos, TGSI_WRITEMASK_Z),
2824 imm_0055,
2825 src(temp_pos) ))
2826 return FALSE;
2827
2828 if (!submit_op1( emit,
2829 inst_token(SVGA3DOP_MOV),
2830 pos,
2831 src(temp_pos) ))
2832 return FALSE;
2833
2834 /* Move the manipulated depth into the extra texcoord reg */
2835 if (!submit_op1( emit,
2836 inst_token(SVGA3DOP_MOV),
2837 writemask(depth, TGSI_WRITEMASK_ZW),
2838 src(temp_pos) ))
2839 return FALSE;
2840 }
2841
2842 return TRUE;
2843 }
2844
2845 /*
2846 0: IF VFACE :4
2847 1: COLOR = FrontColor;
2848 2: ELSE
2849 3: COLOR = BackColor;
2850 4: ENDIF
2851 */
2852 static boolean emit_light_twoside( struct svga_shader_emitter *emit )
2853 {
2854 struct src_register vface, zero;
2855 struct src_register front[2];
2856 struct src_register back[2];
2857 SVGA3dShaderDestToken color[2];
2858 int count = emit->internal_color_count;
2859 int i;
2860 SVGA3dShaderInstToken if_token;
2861
2862 if (count == 0)
2863 return TRUE;
2864
2865 vface = get_vface( emit );
2866 zero = get_zero_immediate( emit );
2867
2868 /* Can't use get_temp() to allocate the color reg as such
2869 * temporaries will be reclaimed after each instruction by the call
2870 * to reset_temp_regs().
2871 */
2872 for (i = 0; i < count; i++) {
2873 color[i] = dst_register( SVGA3DREG_TEMP,
2874 emit->nr_hw_temp++ );
2875
2876 front[i] = emit->input_map[emit->internal_color_idx[i]];
2877
2878 /* Back is always the next input:
2879 */
2880 back[i] = front[i];
2881 back[i].base.num = front[i].base.num + 1;
2882
2883 /* Reassign the input_map to the actual front-face color:
2884 */
2885 emit->input_map[emit->internal_color_idx[i]] = src(color[i]);
2886 }
2887
2888 if_token = inst_token( SVGA3DOP_IFC );
2889
2890 if (emit->key.fkey.front_ccw)
2891 if_token.control = SVGA3DOPCOMP_LT;
2892 else
2893 if_token.control = SVGA3DOPCOMP_GT;
2894
2895 zero = scalar(zero, TGSI_SWIZZLE_X);
2896
2897 if (!(emit_instruction( emit, if_token ) &&
2898 emit_src( emit, vface ) &&
2899 emit_src( emit, zero ) ))
2900 return FALSE;
2901
2902 for (i = 0; i < count; i++) {
2903 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ), color[i], front[i] ))
2904 return FALSE;
2905 }
2906
2907 if (!(emit_instruction( emit, inst_token( SVGA3DOP_ELSE))))
2908 return FALSE;
2909
2910 for (i = 0; i < count; i++) {
2911 if (!submit_op1( emit, inst_token( SVGA3DOP_MOV ), color[i], back[i] ))
2912 return FALSE;
2913 }
2914
2915 if (!emit_instruction( emit, inst_token( SVGA3DOP_ENDIF ) ))
2916 return FALSE;
2917
2918 return TRUE;
2919 }
2920
2921 /*
2922 0: SETP_GT TEMP, VFACE, 0
2923 where TEMP is a fake frontface register
2924 */
2925 static boolean emit_frontface( struct svga_shader_emitter *emit )
2926 {
2927 struct src_register vface, zero;
2928 SVGA3dShaderDestToken temp;
2929 struct src_register pass, fail;
2930
2931 vface = get_vface( emit );
2932 zero = get_zero_immediate( emit );
2933
2934 /* Can't use get_temp() to allocate the fake frontface reg as such
2935 * temporaries will be reclaimed after each instruction by the call
2936 * to reset_temp_regs().
2937 */
2938 temp = dst_register( SVGA3DREG_TEMP,
2939 emit->nr_hw_temp++ );
2940
2941 if (emit->key.fkey.front_ccw) {
2942 pass = scalar( zero, TGSI_SWIZZLE_X );
2943 fail = scalar( zero, TGSI_SWIZZLE_W );
2944 } else {
2945 pass = scalar( zero, TGSI_SWIZZLE_W );
2946 fail = scalar( zero, TGSI_SWIZZLE_X );
2947 }
2948
2949 if (!emit_conditional(emit, PIPE_FUNC_GREATER,
2950 temp, vface, scalar( zero, TGSI_SWIZZLE_X ),
2951 pass, fail))
2952 return FALSE;
2953
2954 /* Reassign the input_map to the actual front-face color:
2955 */
2956 emit->input_map[emit->internal_frontface_idx] = src(temp);
2957
2958 return TRUE;
2959 }
2960
2961
2962 /**
2963 * Emit code to invert the T component of the incoming texture coordinate.
2964 * This is used for drawing point sprites when
2965 * pipe_rasterizer_state::sprite_coord_mode == PIPE_SPRITE_COORD_LOWER_LEFT.
2966 */
2967 static boolean emit_inverted_texcoords( struct svga_shader_emitter *emit )
2968 {
2969 struct src_register zero = get_zero_immediate(emit);
2970 struct src_register pos_neg_one = get_pos_neg_one_immediate( emit );
2971 unsigned inverted_texcoords = emit->inverted_texcoords;
2972
2973 while (inverted_texcoords) {
2974 const unsigned unit = ffs(inverted_texcoords) - 1;
2975
2976 assert(emit->inverted_texcoords & (1 << unit));
2977
2978 assert(unit < Elements(emit->ps_true_texcoord));
2979
2980 assert(unit < Elements(emit->ps_inverted_texcoord_input));
2981
2982 assert(emit->ps_inverted_texcoord_input[unit]
2983 < Elements(emit->input_map));
2984
2985 /* inverted = coord * (1, -1, 1, 1) + (0, 1, 0, 0) */
2986 if (!submit_op3(emit,
2987 inst_token(SVGA3DOP_MAD),
2988 dst(emit->ps_inverted_texcoord[unit]),
2989 emit->ps_true_texcoord[unit],
2990 swizzle(pos_neg_one, 0, 3, 0, 0), /* (1, -1, 1, 1) */
2991 swizzle(zero, 0, 3, 0, 0))) /* (0, 1, 0, 0) */
2992 return FALSE;
2993
2994 /* Reassign the input_map entry to the new texcoord register */
2995 emit->input_map[emit->ps_inverted_texcoord_input[unit]] =
2996 emit->ps_inverted_texcoord[unit];
2997
2998 inverted_texcoords &= ~(1 << unit);
2999 }
3000
3001 return TRUE;
3002 }
3003
3004
3005 static INLINE boolean
3006 needs_to_create_zero( struct svga_shader_emitter *emit )
3007 {
3008 int i;
3009
3010 if (emit->unit == PIPE_SHADER_FRAGMENT) {
3011 if (emit->key.fkey.light_twoside)
3012 return TRUE;
3013
3014 if (emit->key.fkey.white_fragments)
3015 return TRUE;
3016
3017 if (emit->emit_frontface)
3018 return TRUE;
3019
3020 if (emit->info.opcode_count[TGSI_OPCODE_DST] >= 1 ||
3021 emit->info.opcode_count[TGSI_OPCODE_SSG] >= 1 ||
3022 emit->info.opcode_count[TGSI_OPCODE_LIT] >= 1)
3023 return TRUE;
3024
3025 if (emit->inverted_texcoords)
3026 return TRUE;
3027
3028 /* look for any PIPE_SWIZZLE_ZERO/ONE terms */
3029 for (i = 0; i < emit->key.fkey.num_textures; i++) {
3030 if (emit->key.fkey.tex[i].swizzle_r > PIPE_SWIZZLE_ALPHA ||
3031 emit->key.fkey.tex[i].swizzle_g > PIPE_SWIZZLE_ALPHA ||
3032 emit->key.fkey.tex[i].swizzle_b > PIPE_SWIZZLE_ALPHA ||
3033 emit->key.fkey.tex[i].swizzle_a > PIPE_SWIZZLE_ALPHA)
3034 return TRUE;
3035 }
3036 }
3037
3038 if (emit->unit == PIPE_SHADER_VERTEX) {
3039 if (emit->info.opcode_count[TGSI_OPCODE_CMP] >= 1)
3040 return TRUE;
3041 }
3042
3043 if (emit->info.opcode_count[TGSI_OPCODE_IF] >= 1 ||
3044 emit->info.opcode_count[TGSI_OPCODE_BGNLOOP] >= 1 ||
3045 emit->info.opcode_count[TGSI_OPCODE_DDX] >= 1 ||
3046 emit->info.opcode_count[TGSI_OPCODE_DDY] >= 1 ||
3047 emit->info.opcode_count[TGSI_OPCODE_SGE] >= 1 ||
3048 emit->info.opcode_count[TGSI_OPCODE_SGT] >= 1 ||
3049 emit->info.opcode_count[TGSI_OPCODE_SLE] >= 1 ||
3050 emit->info.opcode_count[TGSI_OPCODE_SLT] >= 1 ||
3051 emit->info.opcode_count[TGSI_OPCODE_SNE] >= 1 ||
3052 emit->info.opcode_count[TGSI_OPCODE_SEQ] >= 1 ||
3053 emit->info.opcode_count[TGSI_OPCODE_EXP] >= 1 ||
3054 emit->info.opcode_count[TGSI_OPCODE_LOG] >= 1 ||
3055 emit->info.opcode_count[TGSI_OPCODE_XPD] >= 1 ||
3056 emit->info.opcode_count[TGSI_OPCODE_KILP] >= 1)
3057 return TRUE;
3058
3059 for (i = 0; i < emit->key.fkey.num_textures; i++) {
3060 if (emit->key.fkey.tex[i].compare_mode == PIPE_TEX_COMPARE_R_TO_TEXTURE)
3061 return TRUE;
3062 }
3063
3064 return FALSE;
3065 }
3066
3067 static INLINE boolean
3068 needs_to_create_loop_const( struct svga_shader_emitter *emit )
3069 {
3070 return (emit->info.opcode_count[TGSI_OPCODE_BGNLOOP] >= 1);
3071 }
3072
3073 static INLINE boolean
3074 needs_to_create_sincos_consts( struct svga_shader_emitter *emit )
3075 {
3076 return FALSE;
3077 }
3078
3079 static INLINE boolean
3080 needs_to_create_arl_consts( struct svga_shader_emitter *emit )
3081 {
3082 return (emit->num_arl_consts > 0);
3083 }
3084
3085 static INLINE boolean
3086 pre_parse_add_indirect( struct svga_shader_emitter *emit,
3087 int num, int current_arl)
3088 {
3089 int i;
3090 assert(num < 0);
3091
3092 for (i = 0; i < emit->num_arl_consts; ++i) {
3093 if (emit->arl_consts[i].arl_num == current_arl)
3094 break;
3095 }
3096 /* new entry */
3097 if (emit->num_arl_consts == i) {
3098 ++emit->num_arl_consts;
3099 }
3100 emit->arl_consts[i].number = (emit->arl_consts[i].number > num) ?
3101 num :
3102 emit->arl_consts[i].number;
3103 emit->arl_consts[i].arl_num = current_arl;
3104 return TRUE;
3105 }
3106
3107 static boolean
3108 pre_parse_instruction( struct svga_shader_emitter *emit,
3109 const struct tgsi_full_instruction *insn,
3110 int current_arl)
3111 {
3112 if (insn->Src[0].Register.Indirect &&
3113 insn->Src[0].Indirect.File == TGSI_FILE_ADDRESS) {
3114 const struct tgsi_full_src_register *reg = &insn->Src[0];
3115 if (reg->Register.Index < 0) {
3116 pre_parse_add_indirect(emit, reg->Register.Index, current_arl);
3117 }
3118 }
3119
3120 if (insn->Src[1].Register.Indirect &&
3121 insn->Src[1].Indirect.File == TGSI_FILE_ADDRESS) {
3122 const struct tgsi_full_src_register *reg = &insn->Src[1];
3123 if (reg->Register.Index < 0) {
3124 pre_parse_add_indirect(emit, reg->Register.Index, current_arl);
3125 }
3126 }
3127
3128 if (insn->Src[2].Register.Indirect &&
3129 insn->Src[2].Indirect.File == TGSI_FILE_ADDRESS) {
3130 const struct tgsi_full_src_register *reg = &insn->Src[2];
3131 if (reg->Register.Index < 0) {
3132 pre_parse_add_indirect(emit, reg->Register.Index, current_arl);
3133 }
3134 }
3135
3136 return TRUE;
3137 }
3138
3139 static boolean
3140 pre_parse_tokens( struct svga_shader_emitter *emit,
3141 const struct tgsi_token *tokens )
3142 {
3143 struct tgsi_parse_context parse;
3144 int current_arl = 0;
3145
3146 tgsi_parse_init( &parse, tokens );
3147
3148 while (!tgsi_parse_end_of_tokens( &parse )) {
3149 tgsi_parse_token( &parse );
3150 switch (parse.FullToken.Token.Type) {
3151 case TGSI_TOKEN_TYPE_IMMEDIATE:
3152 case TGSI_TOKEN_TYPE_DECLARATION:
3153 break;
3154 case TGSI_TOKEN_TYPE_INSTRUCTION:
3155 if (parse.FullToken.FullInstruction.Instruction.Opcode ==
3156 TGSI_OPCODE_ARL) {
3157 ++current_arl;
3158 }
3159 if (!pre_parse_instruction( emit, &parse.FullToken.FullInstruction,
3160 current_arl ))
3161 return FALSE;
3162 break;
3163 default:
3164 break;
3165 }
3166
3167 }
3168 return TRUE;
3169 }
3170
3171 static boolean svga_shader_emit_helpers( struct svga_shader_emitter *emit )
3172
3173 {
3174 if (needs_to_create_zero( emit )) {
3175 create_zero_immediate( emit );
3176 }
3177 if (needs_to_create_loop_const( emit )) {
3178 create_loop_const( emit );
3179 }
3180 if (needs_to_create_sincos_consts( emit )) {
3181 create_sincos_consts( emit );
3182 }
3183 if (needs_to_create_arl_consts( emit )) {
3184 create_arl_consts( emit );
3185 }
3186
3187 if (emit->unit == PIPE_SHADER_FRAGMENT) {
3188 if (!emit_ps_preamble( emit ))
3189 return FALSE;
3190
3191 if (emit->key.fkey.light_twoside) {
3192 if (!emit_light_twoside( emit ))
3193 return FALSE;
3194 }
3195 if (emit->emit_frontface) {
3196 if (!emit_frontface( emit ))
3197 return FALSE;
3198 }
3199 if (emit->inverted_texcoords) {
3200 if (!emit_inverted_texcoords( emit ))
3201 return FALSE;
3202 }
3203 }
3204
3205 return TRUE;
3206 }
3207
3208 boolean svga_shader_emit_instructions( struct svga_shader_emitter *emit,
3209 const struct tgsi_token *tokens )
3210 {
3211 struct tgsi_parse_context parse;
3212 boolean ret = TRUE;
3213 boolean helpers_emitted = FALSE;
3214 unsigned line_nr = 0;
3215
3216 tgsi_parse_init( &parse, tokens );
3217 emit->internal_imm_count = 0;
3218
3219 if (emit->unit == PIPE_SHADER_VERTEX) {
3220 ret = emit_vs_preamble( emit );
3221 if (!ret)
3222 goto done;
3223 }
3224
3225 pre_parse_tokens(emit, tokens);
3226
3227 while (!tgsi_parse_end_of_tokens( &parse )) {
3228 tgsi_parse_token( &parse );
3229
3230 switch (parse.FullToken.Token.Type) {
3231 case TGSI_TOKEN_TYPE_IMMEDIATE:
3232 ret = svga_emit_immediate( emit, &parse.FullToken.FullImmediate );
3233 if (!ret)
3234 goto done;
3235 break;
3236
3237 case TGSI_TOKEN_TYPE_DECLARATION:
3238 ret = svga_translate_decl_sm30( emit, &parse.FullToken.FullDeclaration );
3239 if (!ret)
3240 goto done;
3241 break;
3242
3243 case TGSI_TOKEN_TYPE_INSTRUCTION:
3244 if (!helpers_emitted) {
3245 if (!svga_shader_emit_helpers( emit ))
3246 goto done;
3247 helpers_emitted = TRUE;
3248 }
3249 ret = svga_emit_instruction( emit,
3250 line_nr++,
3251 &parse.FullToken.FullInstruction );
3252 if (!ret)
3253 goto done;
3254 break;
3255 default:
3256 break;
3257 }
3258
3259 reset_temp_regs( emit );
3260 }
3261
3262 /* Need to terminate the current subroutine. Note that the
3263 * hardware doesn't tolerate shaders without sub-routines
3264 * terminating with RET+END.
3265 */
3266 if (!emit->in_main_func) {
3267 ret = emit_instruction( emit, inst_token( SVGA3DOP_RET ) );
3268 if (!ret)
3269 goto done;
3270 }
3271
3272 assert(emit->dynamic_branching_level == 0);
3273
3274 /* Need to terminate the whole shader:
3275 */
3276 ret = emit_instruction( emit, inst_token( SVGA3DOP_END ) );
3277 if (!ret)
3278 goto done;
3279
3280 done:
3281 tgsi_parse_free( &parse );
3282 return ret;
3283 }
3284