1 /**********************************************************
2 * Copyright 2008-2009 VMware, Inc. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 **********************************************************/
27 #include "pipe/p_shader_tokens.h"
28 #include "tgsi/tgsi_dump.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/u_memory.h"
31 #include "util/u_math.h"
33 #include "svga_tgsi_emit.h"
34 #include "svga_context.h"
37 static boolean
emit_vs_postamble( struct svga_shader_emitter
*emit
);
38 static boolean
emit_ps_postamble( struct svga_shader_emitter
*emit
);
48 case TGSI_OPCODE_ABS
: return SVGA3DOP_ABS
;
49 case TGSI_OPCODE_ADD
: return SVGA3DOP_ADD
;
50 case TGSI_OPCODE_BREAKC
: return SVGA3DOP_BREAKC
;
51 case TGSI_OPCODE_DP2A
: return SVGA3DOP_DP2ADD
;
52 case TGSI_OPCODE_DP3
: return SVGA3DOP_DP3
;
53 case TGSI_OPCODE_DP4
: return SVGA3DOP_DP4
;
54 case TGSI_OPCODE_FRC
: return SVGA3DOP_FRC
;
55 case TGSI_OPCODE_MAD
: return SVGA3DOP_MAD
;
56 case TGSI_OPCODE_MAX
: return SVGA3DOP_MAX
;
57 case TGSI_OPCODE_MIN
: return SVGA3DOP_MIN
;
58 case TGSI_OPCODE_MOV
: return SVGA3DOP_MOV
;
59 case TGSI_OPCODE_MUL
: return SVGA3DOP_MUL
;
60 case TGSI_OPCODE_NOP
: return SVGA3DOP_NOP
;
61 case TGSI_OPCODE_NRM4
: return SVGA3DOP_NRM
;
63 debug_printf("Unkown opcode %u\n", opcode
);
65 return SVGA3DOP_LAST_INST
;
70 static unsigned translate_file( unsigned file
)
73 case TGSI_FILE_TEMPORARY
: return SVGA3DREG_TEMP
;
74 case TGSI_FILE_INPUT
: return SVGA3DREG_INPUT
;
75 case TGSI_FILE_OUTPUT
: return SVGA3DREG_OUTPUT
; /* VS3.0+ only */
76 case TGSI_FILE_IMMEDIATE
: return SVGA3DREG_CONST
;
77 case TGSI_FILE_CONSTANT
: return SVGA3DREG_CONST
;
78 case TGSI_FILE_SAMPLER
: return SVGA3DREG_SAMPLER
;
79 case TGSI_FILE_ADDRESS
: return SVGA3DREG_ADDR
;
82 return SVGA3DREG_TEMP
;
91 static SVGA3dShaderDestToken
92 translate_dst_register( struct svga_shader_emitter
*emit
,
93 const struct tgsi_full_instruction
*insn
,
96 const struct tgsi_full_dst_register
*reg
= &insn
->Dst
[idx
];
97 SVGA3dShaderDestToken dest
;
99 switch (reg
->Register
.File
) {
100 case TGSI_FILE_OUTPUT
:
101 /* Output registers encode semantic information in their name.
102 * Need to lookup a table built at decl time:
104 dest
= emit
->output_map
[reg
->Register
.Index
];
108 dest
= dst_register( translate_file( reg
->Register
.File
),
109 reg
->Register
.Index
);
113 dest
.mask
= reg
->Register
.WriteMask
;
116 if (insn
->Instruction
.Saturate
)
117 dest
.dstMod
= SVGA3DDSTMOD_SATURATE
;
123 static struct src_register
124 swizzle( struct src_register src
,
130 x
= (src
.base
.swizzle
>> (x
* 2)) & 0x3;
131 y
= (src
.base
.swizzle
>> (y
* 2)) & 0x3;
132 z
= (src
.base
.swizzle
>> (z
* 2)) & 0x3;
133 w
= (src
.base
.swizzle
>> (w
* 2)) & 0x3;
135 src
.base
.swizzle
= TRANSLATE_SWIZZLE(x
,y
,z
,w
);
140 static struct src_register
141 scalar( struct src_register src
,
144 return swizzle( src
, comp
, comp
, comp
, comp
);
147 static INLINE boolean
148 svga_arl_needs_adjustment( const struct svga_shader_emitter
*emit
)
152 for (i
= 0; i
< emit
->num_arl_consts
; ++i
) {
153 if (emit
->arl_consts
[i
].arl_num
== emit
->current_arl
)
160 svga_arl_adjustment( const struct svga_shader_emitter
*emit
)
164 for (i
= 0; i
< emit
->num_arl_consts
; ++i
) {
165 if (emit
->arl_consts
[i
].arl_num
== emit
->current_arl
)
166 return emit
->arl_consts
[i
].number
;
171 static struct src_register
172 translate_src_register( const struct svga_shader_emitter
*emit
,
173 const struct tgsi_full_src_register
*reg
)
175 struct src_register src
;
177 switch (reg
->Register
.File
) {
178 case TGSI_FILE_INPUT
:
179 /* Input registers are referred to by their semantic name rather
180 * than by index. Use the mapping build up from the decls:
182 src
= emit
->input_map
[reg
->Register
.Index
];
185 case TGSI_FILE_IMMEDIATE
:
186 /* Immediates are appended after TGSI constants in the D3D
189 src
= src_register( translate_file( reg
->Register
.File
),
190 reg
->Register
.Index
+
195 src
= src_register( translate_file( reg
->Register
.File
),
196 reg
->Register
.Index
);
201 /* Indirect addressing.
203 if (reg
->Register
.Indirect
) {
204 if (emit
->unit
== PIPE_SHADER_FRAGMENT
) {
205 /* Pixel shaders have only loop registers for relative
206 * addressing into inputs. Ignore the redundant address
207 * register, the contents of aL should be in sync with it.
209 if (reg
->Register
.File
== TGSI_FILE_INPUT
) {
210 src
.base
.relAddr
= 1;
211 src
.indirect
= src_token(SVGA3DREG_LOOP
, 0);
215 /* Constant buffers only.
217 if (reg
->Register
.File
== TGSI_FILE_CONSTANT
) {
218 /* we shift the offset towards the minimum */
219 if (svga_arl_needs_adjustment( emit
)) {
220 src
.base
.num
-= svga_arl_adjustment( emit
);
222 src
.base
.relAddr
= 1;
224 /* Not really sure what should go in the second token:
226 src
.indirect
= src_token( SVGA3DREG_ADDR
,
227 reg
->Indirect
.Index
);
229 src
.indirect
.swizzle
= SWIZZLE_XXXX
;
235 reg
->Register
.SwizzleX
,
236 reg
->Register
.SwizzleY
,
237 reg
->Register
.SwizzleZ
,
238 reg
->Register
.SwizzleW
);
240 /* src.mod isn't a bitfield, unfortunately:
241 * See tgsi_util_get_full_src_register_sign_mode for implementation details.
243 if (reg
->Register
.Absolute
) {
244 if (reg
->Register
.Negate
)
245 src
.base
.srcMod
= SVGA3DSRCMOD_ABSNEG
;
247 src
.base
.srcMod
= SVGA3DSRCMOD_ABS
;
250 if (reg
->Register
.Negate
)
251 src
.base
.srcMod
= SVGA3DSRCMOD_NEG
;
253 src
.base
.srcMod
= SVGA3DSRCMOD_NONE
;
261 * Get a temporary register, return -1 if none available
263 static INLINE SVGA3dShaderDestToken
264 get_temp( struct svga_shader_emitter
*emit
)
266 int i
= emit
->nr_hw_temp
+ emit
->internal_temp_count
++;
268 return dst_register( SVGA3DREG_TEMP
, i
);
271 /* Release a single temp. Currently only effective if it was the last
272 * allocated temp, otherwise release will be delayed until the next
273 * call to reset_temp_regs().
276 release_temp( struct svga_shader_emitter
*emit
,
277 SVGA3dShaderDestToken temp
)
279 if (temp
.num
== emit
->internal_temp_count
- 1)
280 emit
->internal_temp_count
--;
283 static void reset_temp_regs( struct svga_shader_emitter
*emit
)
285 emit
->internal_temp_count
= 0;
289 /* Replace the src with the temporary specified in the dst, but copying
290 * only the necessary channels, and preserving the original swizzle (which is
291 * important given that several opcodes have constraints in the allowed
294 static boolean
emit_repl( struct svga_shader_emitter
*emit
,
295 SVGA3dShaderDestToken dst
,
296 struct src_register
*src0
)
298 unsigned src0_swizzle
;
301 assert(SVGA3dShaderGetRegType(dst
.value
) == SVGA3DREG_TEMP
);
303 src0_swizzle
= src0
->base
.swizzle
;
306 for (chan
= 0; chan
< 4; ++chan
) {
307 unsigned swizzle
= (src0_swizzle
>> (chan
*2)) & 0x3;
308 dst
.mask
|= 1 << swizzle
;
312 src0
->base
.swizzle
= SVGA3DSWIZZLE_NONE
;
314 if (!emit_op1( emit
, inst_token( SVGA3DOP_MOV
), dst
, *src0
))
318 src0
->base
.swizzle
= src0_swizzle
;
324 static boolean
submit_op0( struct svga_shader_emitter
*emit
,
325 SVGA3dShaderInstToken inst
,
326 SVGA3dShaderDestToken dest
)
328 return (emit_instruction( emit
, inst
) &&
329 emit_dst( emit
, dest
));
332 static boolean
submit_op1( struct svga_shader_emitter
*emit
,
333 SVGA3dShaderInstToken inst
,
334 SVGA3dShaderDestToken dest
,
335 struct src_register src0
)
337 return emit_op1( emit
, inst
, dest
, src0
);
341 /* SVGA shaders may not refer to >1 constant register in a single
342 * instruction. This function checks for that usage and inserts a
343 * move to temporary if detected.
345 * The same applies to input registers -- at most a single input
346 * register may be read by any instruction.
348 static boolean
submit_op2( struct svga_shader_emitter
*emit
,
349 SVGA3dShaderInstToken inst
,
350 SVGA3dShaderDestToken dest
,
351 struct src_register src0
,
352 struct src_register src1
)
354 SVGA3dShaderDestToken temp
;
355 SVGA3dShaderRegType type0
, type1
;
356 boolean need_temp
= FALSE
;
359 type0
= SVGA3dShaderGetRegType( src0
.base
.value
);
360 type1
= SVGA3dShaderGetRegType( src1
.base
.value
);
362 if (type0
== SVGA3DREG_CONST
&&
363 type1
== SVGA3DREG_CONST
&&
364 src0
.base
.num
!= src1
.base
.num
)
367 if (type0
== SVGA3DREG_INPUT
&&
368 type1
== SVGA3DREG_INPUT
&&
369 src0
.base
.num
!= src1
.base
.num
)
373 temp
= get_temp( emit
);
375 if (!emit_repl( emit
, temp
, &src0
))
379 if (!emit_op2( emit
, inst
, dest
, src0
, src1
))
383 release_temp( emit
, temp
);
389 /* SVGA shaders may not refer to >1 constant register in a single
390 * instruction. This function checks for that usage and inserts a
391 * move to temporary if detected.
393 static boolean
submit_op3( struct svga_shader_emitter
*emit
,
394 SVGA3dShaderInstToken inst
,
395 SVGA3dShaderDestToken dest
,
396 struct src_register src0
,
397 struct src_register src1
,
398 struct src_register src2
)
400 SVGA3dShaderDestToken temp0
;
401 SVGA3dShaderDestToken temp1
;
402 boolean need_temp0
= FALSE
;
403 boolean need_temp1
= FALSE
;
404 SVGA3dShaderRegType type0
, type1
, type2
;
408 type0
= SVGA3dShaderGetRegType( src0
.base
.value
);
409 type1
= SVGA3dShaderGetRegType( src1
.base
.value
);
410 type2
= SVGA3dShaderGetRegType( src2
.base
.value
);
412 if (inst
.op
!= SVGA3DOP_SINCOS
) {
413 if (type0
== SVGA3DREG_CONST
&&
414 ((type1
== SVGA3DREG_CONST
&& src0
.base
.num
!= src1
.base
.num
) ||
415 (type2
== SVGA3DREG_CONST
&& src0
.base
.num
!= src2
.base
.num
)))
418 if (type1
== SVGA3DREG_CONST
&&
419 (type2
== SVGA3DREG_CONST
&& src1
.base
.num
!= src2
.base
.num
))
423 if (type0
== SVGA3DREG_INPUT
&&
424 ((type1
== SVGA3DREG_INPUT
&& src0
.base
.num
!= src1
.base
.num
) ||
425 (type2
== SVGA3DREG_INPUT
&& src0
.base
.num
!= src2
.base
.num
)))
428 if (type1
== SVGA3DREG_INPUT
&&
429 (type2
== SVGA3DREG_INPUT
&& src1
.base
.num
!= src2
.base
.num
))
433 temp0
= get_temp( emit
);
435 if (!emit_repl( emit
, temp0
, &src0
))
440 temp1
= get_temp( emit
);
442 if (!emit_repl( emit
, temp1
, &src1
))
446 if (!emit_op3( emit
, inst
, dest
, src0
, src1
, src2
))
450 release_temp( emit
, temp1
);
452 release_temp( emit
, temp0
);
459 /* SVGA shaders may not refer to >1 constant register in a single
460 * instruction. This function checks for that usage and inserts a
461 * move to temporary if detected.
463 static boolean
submit_op4( struct svga_shader_emitter
*emit
,
464 SVGA3dShaderInstToken inst
,
465 SVGA3dShaderDestToken dest
,
466 struct src_register src0
,
467 struct src_register src1
,
468 struct src_register src2
,
469 struct src_register src3
)
471 SVGA3dShaderDestToken temp0
;
472 SVGA3dShaderDestToken temp3
;
473 boolean need_temp0
= FALSE
;
474 boolean need_temp3
= FALSE
;
475 SVGA3dShaderRegType type0
, type1
, type2
, type3
;
479 type0
= SVGA3dShaderGetRegType( src0
.base
.value
);
480 type1
= SVGA3dShaderGetRegType( src1
.base
.value
);
481 type2
= SVGA3dShaderGetRegType( src2
.base
.value
);
482 type3
= SVGA3dShaderGetRegType( src2
.base
.value
);
484 /* Make life a little easier - this is only used by the TXD
485 * instruction which is guaranteed not to have a constant/input reg
486 * in one slot at least:
488 assert(type1
== SVGA3DREG_SAMPLER
);
490 if (type0
== SVGA3DREG_CONST
&&
491 ((type3
== SVGA3DREG_CONST
&& src0
.base
.num
!= src3
.base
.num
) ||
492 (type2
== SVGA3DREG_CONST
&& src0
.base
.num
!= src2
.base
.num
)))
495 if (type3
== SVGA3DREG_CONST
&&
496 (type2
== SVGA3DREG_CONST
&& src3
.base
.num
!= src2
.base
.num
))
499 if (type0
== SVGA3DREG_INPUT
&&
500 ((type3
== SVGA3DREG_INPUT
&& src0
.base
.num
!= src3
.base
.num
) ||
501 (type2
== SVGA3DREG_INPUT
&& src0
.base
.num
!= src2
.base
.num
)))
504 if (type3
== SVGA3DREG_INPUT
&&
505 (type2
== SVGA3DREG_INPUT
&& src3
.base
.num
!= src2
.base
.num
))
509 temp0
= get_temp( emit
);
511 if (!emit_repl( emit
, temp0
, &src0
))
516 temp3
= get_temp( emit
);
518 if (!emit_repl( emit
, temp3
, &src3
))
522 if (!emit_op4( emit
, inst
, dest
, src0
, src1
, src2
, src3
))
526 release_temp( emit
, temp3
);
528 release_temp( emit
, temp0
);
533 static boolean
alias_src_dst( struct src_register src
,
534 SVGA3dShaderDestToken dst
)
536 if (src
.base
.num
!= dst
.num
)
539 if (SVGA3dShaderGetRegType(dst
.value
) !=
540 SVGA3dShaderGetRegType(src
.base
.value
))
547 static boolean
submit_lrp(struct svga_shader_emitter
*emit
,
548 SVGA3dShaderDestToken dst
,
549 struct src_register src0
,
550 struct src_register src1
,
551 struct src_register src2
)
553 SVGA3dShaderDestToken tmp
;
554 boolean need_dst_tmp
= FALSE
;
556 /* The dst reg must be a temporary, and not be the same as src0 or src2 */
557 if (SVGA3dShaderGetRegType(dst
.value
) != SVGA3DREG_TEMP
||
558 alias_src_dst(src0
, dst
) ||
559 alias_src_dst(src2
, dst
))
563 tmp
= get_temp( emit
);
570 if (!submit_op3(emit
, inst_token( SVGA3DOP_LRP
), tmp
, src0
, src1
, src2
))
574 if (!submit_op1(emit
, inst_token( SVGA3DOP_MOV
), dst
, src( tmp
)))
582 static boolean
emit_def_const( struct svga_shader_emitter
*emit
,
583 SVGA3dShaderConstType type
,
591 SVGA3dShaderInstToken opcode
;
594 case SVGA3D_CONST_TYPE_FLOAT
:
595 opcode
= inst_token( SVGA3DOP_DEF
);
596 def
.dst
= dst_register( SVGA3DREG_CONST
, idx
);
597 def
.constValues
[0] = a
;
598 def
.constValues
[1] = b
;
599 def
.constValues
[2] = c
;
600 def
.constValues
[3] = d
;
602 case SVGA3D_CONST_TYPE_INT
:
603 opcode
= inst_token( SVGA3DOP_DEFI
);
604 def
.dst
= dst_register( SVGA3DREG_CONSTINT
, idx
);
605 def
.constIValues
[0] = (int)a
;
606 def
.constIValues
[1] = (int)b
;
607 def
.constIValues
[2] = (int)c
;
608 def
.constIValues
[3] = (int)d
;
612 opcode
= inst_token( SVGA3DOP_NOP
);
616 if (!emit_instruction(emit
, opcode
) ||
617 !svga_shader_emit_dwords( emit
, def
.values
, Elements(def
.values
)))
623 static INLINE boolean
624 create_zero_immediate( struct svga_shader_emitter
*emit
)
626 unsigned idx
= emit
->nr_hw_float_const
++;
628 /* Emit the constant (0, 0, -1, 1) and use swizzling to generate
629 * other useful vectors.
631 if (!emit_def_const( emit
, SVGA3D_CONST_TYPE_FLOAT
,
635 emit
->zero_immediate_idx
= idx
;
636 emit
->created_zero_immediate
= TRUE
;
641 static INLINE boolean
642 create_loop_const( struct svga_shader_emitter
*emit
)
644 unsigned idx
= emit
->nr_hw_int_const
++;
646 if (!emit_def_const( emit
, SVGA3D_CONST_TYPE_INT
, idx
,
647 255, /* iteration count */
648 0, /* initial value */
650 0 /* not used, must be 0 */))
653 emit
->loop_const_idx
= idx
;
654 emit
->created_loop_const
= TRUE
;
659 static INLINE boolean
660 create_sincos_consts( struct svga_shader_emitter
*emit
)
662 unsigned idx
= emit
->nr_hw_float_const
++;
664 if (!emit_def_const( emit
, SVGA3D_CONST_TYPE_FLOAT
, idx
,
671 emit
->sincos_consts_idx
= idx
;
672 idx
= emit
->nr_hw_float_const
++;
674 if (!emit_def_const( emit
, SVGA3D_CONST_TYPE_FLOAT
, idx
,
681 emit
->created_sincos_consts
= TRUE
;
686 static INLINE boolean
687 create_arl_consts( struct svga_shader_emitter
*emit
)
691 for (i
= 0; i
< emit
->num_arl_consts
; i
+= 4) {
693 unsigned idx
= emit
->nr_hw_float_const
++;
695 for (j
= 0; j
< 4 && (j
+ i
) < emit
->num_arl_consts
; ++j
) {
696 vals
[j
] = emit
->arl_consts
[i
+ j
].number
;
697 emit
->arl_consts
[i
+ j
].idx
= idx
;
700 emit
->arl_consts
[i
+ 0].swizzle
= TGSI_SWIZZLE_X
;
703 emit
->arl_consts
[i
+ 0].swizzle
= TGSI_SWIZZLE_Y
;
706 emit
->arl_consts
[i
+ 0].swizzle
= TGSI_SWIZZLE_Z
;
709 emit
->arl_consts
[i
+ 0].swizzle
= TGSI_SWIZZLE_W
;
716 if (!emit_def_const( emit
, SVGA3D_CONST_TYPE_FLOAT
, idx
,
725 static INLINE
struct src_register
726 get_vface( struct svga_shader_emitter
*emit
)
728 assert(emit
->emitted_vface
);
729 return src_register(SVGA3DREG_MISCTYPE
,
733 /* returns {0, 0, 0, 1} immediate */
734 static INLINE
struct src_register
735 get_zero_immediate( struct svga_shader_emitter
*emit
)
737 assert(emit
->created_zero_immediate
);
738 assert(emit
->zero_immediate_idx
>= 0);
739 return swizzle(src_register( SVGA3DREG_CONST
,
740 emit
->zero_immediate_idx
),
744 /* returns {1, 1, 1, -1} immediate */
745 static INLINE
struct src_register
746 get_pos_neg_one_immediate( struct svga_shader_emitter
*emit
)
748 assert(emit
->created_zero_immediate
);
749 assert(emit
->zero_immediate_idx
>= 0);
750 return swizzle(src_register( SVGA3DREG_CONST
,
751 emit
->zero_immediate_idx
),
755 /* returns the loop const */
756 static INLINE
struct src_register
757 get_loop_const( struct svga_shader_emitter
*emit
)
759 assert(emit
->created_loop_const
);
760 assert(emit
->loop_const_idx
>= 0);
761 return src_register( SVGA3DREG_CONSTINT
,
762 emit
->loop_const_idx
);
765 /* returns a sincos const */
766 static INLINE
struct src_register
767 get_sincos_const( struct svga_shader_emitter
*emit
,
770 assert(emit
->created_sincos_consts
);
771 assert(emit
->sincos_consts_idx
>= 0);
772 assert(index
== 0 || index
== 1);
773 return src_register( SVGA3DREG_CONST
,
774 emit
->sincos_consts_idx
+ index
);
777 static INLINE
struct src_register
778 get_fake_arl_const( struct svga_shader_emitter
*emit
)
780 struct src_register reg
;
781 int idx
= 0, swizzle
= 0, i
;
783 for (i
= 0; i
< emit
->num_arl_consts
; ++ i
) {
784 if (emit
->arl_consts
[i
].arl_num
== emit
->current_arl
) {
785 idx
= emit
->arl_consts
[i
].idx
;
786 swizzle
= emit
->arl_consts
[i
].swizzle
;
790 reg
= src_register( SVGA3DREG_CONST
, idx
);
791 return scalar(reg
, swizzle
);
794 static INLINE
struct src_register
795 get_tex_dimensions( struct svga_shader_emitter
*emit
, int sampler_num
)
798 struct src_register reg
;
800 /* the width/height indexes start right after constants */
801 idx
= emit
->key
.fkey
.tex
[sampler_num
].width_height_idx
+
802 emit
->info
.file_max
[TGSI_FILE_CONSTANT
] + 1;
804 reg
= src_register( SVGA3DREG_CONST
, idx
);
808 static boolean
emit_fake_arl(struct svga_shader_emitter
*emit
,
809 const struct tgsi_full_instruction
*insn
)
811 const struct src_register src0
= translate_src_register(
812 emit
, &insn
->Src
[0] );
813 struct src_register src1
= get_fake_arl_const( emit
);
814 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
815 SVGA3dShaderDestToken tmp
= get_temp( emit
);
817 if (!submit_op1(emit
, inst_token( SVGA3DOP_MOV
), tmp
, src0
))
820 if (!submit_op2( emit
, inst_token( SVGA3DOP_ADD
), tmp
, src( tmp
),
824 /* replicate the original swizzle */
826 src1
.base
.swizzle
= src0
.base
.swizzle
;
828 return submit_op1( emit
, inst_token( SVGA3DOP_MOVA
),
832 static boolean
emit_if(struct svga_shader_emitter
*emit
,
833 const struct tgsi_full_instruction
*insn
)
835 struct src_register src0
= translate_src_register(
836 emit
, &insn
->Src
[0] );
837 struct src_register zero
= get_zero_immediate( emit
);
838 SVGA3dShaderInstToken if_token
= inst_token( SVGA3DOP_IFC
);
840 if_token
.control
= SVGA3DOPCOMPC_NE
;
841 zero
= scalar(zero
, TGSI_SWIZZLE_X
);
843 if (SVGA3dShaderGetRegType(src0
.base
.value
) == SVGA3DREG_CONST
) {
845 * Max different constant registers readable per IFC instruction is 1.
848 SVGA3dShaderDestToken tmp
= get_temp( emit
);
850 if (!submit_op1(emit
, inst_token( SVGA3DOP_MOV
), tmp
, src0
))
853 src0
= scalar(src( tmp
), TGSI_SWIZZLE_X
);
856 emit
->dynamic_branching_level
++;
858 return (emit_instruction( emit
, if_token
) &&
859 emit_src( emit
, src0
) &&
860 emit_src( emit
, zero
) );
863 static boolean
emit_endif(struct svga_shader_emitter
*emit
,
864 const struct tgsi_full_instruction
*insn
)
866 emit
->dynamic_branching_level
--;
868 return (emit_instruction( emit
,
869 inst_token( SVGA3DOP_ENDIF
)));
872 static boolean
emit_else(struct svga_shader_emitter
*emit
,
873 const struct tgsi_full_instruction
*insn
)
875 return (emit_instruction( emit
,
876 inst_token( SVGA3DOP_ELSE
)));
879 /* Translate the following TGSI FLR instruction.
881 * To the following SVGA3D instruction sequence.
885 static boolean
emit_floor(struct svga_shader_emitter
*emit
,
886 const struct tgsi_full_instruction
*insn
)
888 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
889 const struct src_register src0
= translate_src_register(
890 emit
, &insn
->Src
[0] );
891 SVGA3dShaderDestToken temp
= get_temp( emit
);
894 if (!submit_op1( emit
, inst_token( SVGA3DOP_FRC
), temp
, src0
))
897 /* SUB DST, SRC, TMP */
898 if (!submit_op2( emit
, inst_token( SVGA3DOP_ADD
), dst
, src0
,
899 negate( src( temp
) ) ))
906 /* Translate the following TGSI CMP instruction.
907 * CMP DST, SRC0, SRC1, SRC2
908 * To the following SVGA3D instruction sequence.
909 * CMP DST, SRC0, SRC2, SRC1
911 static boolean
emit_cmp(struct svga_shader_emitter
*emit
,
912 const struct tgsi_full_instruction
*insn
)
914 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
915 const struct src_register src0
= translate_src_register(
916 emit
, &insn
->Src
[0] );
917 const struct src_register src1
= translate_src_register(
918 emit
, &insn
->Src
[1] );
919 const struct src_register src2
= translate_src_register(
920 emit
, &insn
->Src
[2] );
922 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
923 SVGA3dShaderDestToken temp
= get_temp(emit
);
924 struct src_register zero
= scalar(get_zero_immediate(emit
), TGSI_SWIZZLE_X
);
926 /* Since vertex shaders don't support the CMP instruction,
927 * simulate it with SLT and LRP instructions.
929 * LRP DST, TMP, SRC1, SRC2
931 if (!submit_op2(emit
, inst_token(SVGA3DOP_SLT
), temp
, src0
, zero
))
933 return submit_lrp(emit
, dst
, src(temp
), src1
, src2
);
936 /* CMP DST, SRC0, SRC2, SRC1 */
937 return submit_op3( emit
, inst_token( SVGA3DOP_CMP
), dst
, src0
, src2
, src1
);
942 /* Translate the following TGSI DIV instruction.
943 * DIV DST.xy, SRC0, SRC1
944 * To the following SVGA3D instruction sequence.
945 * RCP TMP.x, SRC1.xxxx
946 * RCP TMP.y, SRC1.yyyy
947 * MUL DST.xy, SRC0, TMP
949 static boolean
emit_div(struct svga_shader_emitter
*emit
,
950 const struct tgsi_full_instruction
*insn
)
952 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
953 const struct src_register src0
= translate_src_register(
954 emit
, &insn
->Src
[0] );
955 const struct src_register src1
= translate_src_register(
956 emit
, &insn
->Src
[1] );
957 SVGA3dShaderDestToken temp
= get_temp( emit
);
960 /* For each enabled element, perform a RCP instruction. Note that
961 * RCP is scalar in SVGA3D:
963 for (i
= 0; i
< 4; i
++) {
964 unsigned channel
= 1 << i
;
965 if (dst
.mask
& channel
) {
966 /* RCP TMP.?, SRC1.???? */
967 if (!submit_op1( emit
, inst_token( SVGA3DOP_RCP
),
968 writemask(temp
, channel
),
974 /* Then multiply them out with a single mul:
978 if (!submit_op2( emit
, inst_token( SVGA3DOP_MUL
), dst
, src0
,
985 /* Translate the following TGSI DP2 instruction.
986 * DP2 DST, SRC1, SRC2
987 * To the following SVGA3D instruction sequence.
988 * MUL TMP, SRC1, SRC2
989 * ADD DST, TMP.xxxx, TMP.yyyy
991 static boolean
emit_dp2(struct svga_shader_emitter
*emit
,
992 const struct tgsi_full_instruction
*insn
)
994 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
995 const struct src_register src0
= translate_src_register(
996 emit
, &insn
->Src
[0] );
997 const struct src_register src1
= translate_src_register(
998 emit
, &insn
->Src
[1] );
999 SVGA3dShaderDestToken temp
= get_temp( emit
);
1000 struct src_register temp_src0
, temp_src1
;
1002 /* MUL TMP, SRC1, SRC2 */
1003 if (!submit_op2( emit
, inst_token( SVGA3DOP_MUL
), temp
, src0
, src1
))
1006 temp_src0
= scalar(src( temp
), TGSI_SWIZZLE_X
);
1007 temp_src1
= scalar(src( temp
), TGSI_SWIZZLE_Y
);
1009 /* ADD DST, TMP.xxxx, TMP.yyyy */
1010 if (!submit_op2( emit
, inst_token( SVGA3DOP_ADD
), dst
,
1011 temp_src0
, temp_src1
))
1018 /* Translate the following TGSI DPH instruction.
1019 * DPH DST, SRC1, SRC2
1020 * To the following SVGA3D instruction sequence.
1021 * DP3 TMP, SRC1, SRC2
1022 * ADD DST, TMP, SRC2.wwww
1024 static boolean
emit_dph(struct svga_shader_emitter
*emit
,
1025 const struct tgsi_full_instruction
*insn
)
1027 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1028 const struct src_register src0
= translate_src_register(
1029 emit
, &insn
->Src
[0] );
1030 struct src_register src1
= translate_src_register(
1031 emit
, &insn
->Src
[1] );
1032 SVGA3dShaderDestToken temp
= get_temp( emit
);
1034 /* DP3 TMP, SRC1, SRC2 */
1035 if (!submit_op2( emit
, inst_token( SVGA3DOP_DP3
), temp
, src0
, src1
))
1038 src1
= scalar(src1
, TGSI_SWIZZLE_W
);
1040 /* ADD DST, TMP, SRC2.wwww */
1041 if (!submit_op2( emit
, inst_token( SVGA3DOP_ADD
), dst
,
1042 src( temp
), src1
))
1048 /* Translate the following TGSI DST instruction.
1050 * To the following SVGA3D instruction sequence.
1055 static boolean
emit_nrm(struct svga_shader_emitter
*emit
,
1056 const struct tgsi_full_instruction
*insn
)
1058 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1059 const struct src_register src0
= translate_src_register(
1060 emit
, &insn
->Src
[0] );
1061 SVGA3dShaderDestToken temp
= get_temp( emit
);
1063 /* DP3 TMP, SRC, SRC */
1064 if (!submit_op2( emit
, inst_token( SVGA3DOP_DP3
), temp
, src0
, src0
))
1068 if (!submit_op1( emit
, inst_token( SVGA3DOP_RSQ
), temp
, src( temp
)))
1071 /* MUL DST, SRC, TMP */
1072 if (!submit_op2( emit
, inst_token( SVGA3DOP_MUL
), dst
,
1080 static boolean
do_emit_sincos(struct svga_shader_emitter
*emit
,
1081 SVGA3dShaderDestToken dst
,
1082 struct src_register src0
)
1084 src0
= scalar(src0
, TGSI_SWIZZLE_X
);
1086 if (emit
->use_sm30
) {
1087 return submit_op1( emit
, inst_token( SVGA3DOP_SINCOS
),
1090 struct src_register const1
= get_sincos_const( emit
, 0 );
1091 struct src_register const2
= get_sincos_const( emit
, 1 );
1093 return submit_op3( emit
, inst_token( SVGA3DOP_SINCOS
),
1094 dst
, src0
, const1
, const2
);
1098 static boolean
emit_sincos(struct svga_shader_emitter
*emit
,
1099 const struct tgsi_full_instruction
*insn
)
1101 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1102 struct src_register src0
= translate_src_register(
1103 emit
, &insn
->Src
[0] );
1104 SVGA3dShaderDestToken temp
= get_temp( emit
);
1107 if (!do_emit_sincos(emit
, writemask(temp
, TGSI_WRITEMASK_XY
), src0
))
1111 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), dst
, src( temp
) ))
1121 static boolean
emit_sin(struct svga_shader_emitter
*emit
,
1122 const struct tgsi_full_instruction
*insn
)
1124 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1125 struct src_register src0
= translate_src_register(
1126 emit
, &insn
->Src
[0] );
1127 SVGA3dShaderDestToken temp
= get_temp( emit
);
1130 if (!do_emit_sincos(emit
, writemask(temp
, TGSI_WRITEMASK_Y
), src0
))
1133 src0
= scalar(src( temp
), TGSI_SWIZZLE_Y
);
1135 /* MOV DST TMP.yyyy */
1136 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), dst
, src0
))
1146 static boolean
emit_cos(struct svga_shader_emitter
*emit
,
1147 const struct tgsi_full_instruction
*insn
)
1149 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1150 struct src_register src0
= translate_src_register(
1151 emit
, &insn
->Src
[0] );
1152 SVGA3dShaderDestToken temp
= get_temp( emit
);
1155 if (!do_emit_sincos( emit
, writemask(temp
, TGSI_WRITEMASK_X
), src0
))
1158 src0
= scalar(src( temp
), TGSI_SWIZZLE_X
);
1160 /* MOV DST TMP.xxxx */
1161 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), dst
, src0
))
1167 static boolean
emit_ssg(struct svga_shader_emitter
*emit
,
1168 const struct tgsi_full_instruction
*insn
)
1170 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1171 struct src_register src0
= translate_src_register(
1172 emit
, &insn
->Src
[0] );
1173 SVGA3dShaderDestToken temp0
= get_temp( emit
);
1174 SVGA3dShaderDestToken temp1
= get_temp( emit
);
1175 struct src_register zero
, one
;
1177 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
1178 /* SGN DST, SRC0, TMP0, TMP1 */
1179 return submit_op3( emit
, inst_token( SVGA3DOP_SGN
), dst
, src0
,
1180 src( temp0
), src( temp1
) );
1183 zero
= get_zero_immediate( emit
);
1184 one
= scalar( zero
, TGSI_SWIZZLE_W
);
1185 zero
= scalar( zero
, TGSI_SWIZZLE_X
);
1187 /* CMP TMP0, SRC0, one, zero */
1188 if (!submit_op3( emit
, inst_token( SVGA3DOP_CMP
),
1189 writemask( temp0
, dst
.mask
), src0
, one
, zero
))
1192 /* CMP TMP1, negate(SRC0), negate(one), zero */
1193 if (!submit_op3( emit
, inst_token( SVGA3DOP_CMP
),
1194 writemask( temp1
, dst
.mask
), negate( src0
), negate( one
),
1198 /* ADD DST, TMP0, TMP1 */
1199 return submit_op2( emit
, inst_token( SVGA3DOP_ADD
), dst
, src( temp0
),
1204 * ADD DST SRC0, negate(SRC0)
1206 static boolean
emit_sub(struct svga_shader_emitter
*emit
,
1207 const struct tgsi_full_instruction
*insn
)
1209 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1210 struct src_register src0
= translate_src_register(
1211 emit
, &insn
->Src
[0] );
1212 struct src_register src1
= translate_src_register(
1213 emit
, &insn
->Src
[1] );
1215 src1
= negate(src1
);
1217 if (!submit_op2( emit
, inst_token( SVGA3DOP_ADD
), dst
,
1225 static boolean
emit_kil(struct svga_shader_emitter
*emit
,
1226 const struct tgsi_full_instruction
*insn
)
1228 SVGA3dShaderInstToken inst
;
1229 const struct tgsi_full_src_register
*reg
= &insn
->Src
[0];
1230 struct src_register src0
;
1232 inst
= inst_token( SVGA3DOP_TEXKILL
);
1233 src0
= translate_src_register( emit
, reg
);
1235 if (reg
->Register
.Absolute
||
1236 reg
->Register
.Negate
||
1237 reg
->Register
.Indirect
||
1238 reg
->Register
.SwizzleX
!= 0 ||
1239 reg
->Register
.SwizzleY
!= 1 ||
1240 reg
->Register
.SwizzleZ
!= 2 ||
1241 reg
->Register
.File
!= TGSI_FILE_TEMPORARY
)
1243 SVGA3dShaderDestToken temp
= get_temp( emit
);
1245 submit_op1( emit
, inst_token( SVGA3DOP_MOV
), temp
, src0
);
1249 return submit_op0( emit
, inst
, dst(src0
) );
1253 /* mesa state tracker always emits kilp as an unconditional
1255 static boolean
emit_kilp(struct svga_shader_emitter
*emit
,
1256 const struct tgsi_full_instruction
*insn
)
1258 SVGA3dShaderInstToken inst
;
1259 SVGA3dShaderDestToken temp
;
1260 struct src_register one
= scalar( get_zero_immediate( emit
),
1263 inst
= inst_token( SVGA3DOP_TEXKILL
);
1265 /* texkill doesn't allow negation on the operand so lets move
1266 * negation of {1} to a temp register */
1267 temp
= get_temp( emit
);
1268 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), temp
,
1272 return submit_op0( emit
, inst
, temp
);
1275 /* Implement conditionals by initializing destination reg to 'fail',
1276 * then set predicate reg with UFOP_SETP, then move 'pass' to dest
1277 * based on predicate reg.
1279 * SETP src0, cmp, src1 -- do this first to avoid aliasing problems.
1284 emit_conditional(struct svga_shader_emitter
*emit
,
1285 unsigned compare_func
,
1286 SVGA3dShaderDestToken dst
,
1287 struct src_register src0
,
1288 struct src_register src1
,
1289 struct src_register pass
,
1290 struct src_register fail
)
1292 SVGA3dShaderDestToken pred_reg
= dst_register( SVGA3DREG_PREDICATE
, 0 );
1293 SVGA3dShaderInstToken setp_token
, mov_token
;
1294 setp_token
= inst_token( SVGA3DOP_SETP
);
1296 switch (compare_func
) {
1297 case PIPE_FUNC_NEVER
:
1298 return submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
1301 case PIPE_FUNC_LESS
:
1302 setp_token
.control
= SVGA3DOPCOMP_LT
;
1304 case PIPE_FUNC_EQUAL
:
1305 setp_token
.control
= SVGA3DOPCOMP_EQ
;
1307 case PIPE_FUNC_LEQUAL
:
1308 setp_token
.control
= SVGA3DOPCOMP_LE
;
1310 case PIPE_FUNC_GREATER
:
1311 setp_token
.control
= SVGA3DOPCOMP_GT
;
1313 case PIPE_FUNC_NOTEQUAL
:
1314 setp_token
.control
= SVGA3DOPCOMPC_NE
;
1316 case PIPE_FUNC_GEQUAL
:
1317 setp_token
.control
= SVGA3DOPCOMP_GE
;
1319 case PIPE_FUNC_ALWAYS
:
1320 return submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
1325 /* SETP src0, COMPOP, src1 */
1326 if (!submit_op2( emit
, setp_token
, pred_reg
,
1330 mov_token
= inst_token( SVGA3DOP_MOV
);
1333 if (!submit_op1( emit
, mov_token
, dst
,
1337 /* MOV dst, pass (predicated)
1339 * Note that the predicate reg (and possible modifiers) is passed
1340 * as the first source argument.
1342 mov_token
.predicated
= 1;
1343 if (!submit_op2( emit
, mov_token
, dst
,
1344 src( pred_reg
), pass
))
1352 emit_select(struct svga_shader_emitter
*emit
,
1353 unsigned compare_func
,
1354 SVGA3dShaderDestToken dst
,
1355 struct src_register src0
,
1356 struct src_register src1
)
1358 /* There are some SVGA instructions which implement some selects
1359 * directly, but they are only available in the vertex shader.
1361 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
1362 switch (compare_func
) {
1363 case PIPE_FUNC_GEQUAL
:
1364 return submit_op2( emit
, inst_token( SVGA3DOP_SGE
), dst
, src0
, src1
);
1365 case PIPE_FUNC_LEQUAL
:
1366 return submit_op2( emit
, inst_token( SVGA3DOP_SGE
), dst
, src1
, src0
);
1367 case PIPE_FUNC_GREATER
:
1368 return submit_op2( emit
, inst_token( SVGA3DOP_SLT
), dst
, src1
, src0
);
1369 case PIPE_FUNC_LESS
:
1370 return submit_op2( emit
, inst_token( SVGA3DOP_SLT
), dst
, src0
, src1
);
1377 /* Otherwise, need to use the setp approach:
1380 struct src_register one
, zero
;
1381 /* zero immediate is 0,0,0,1 */
1382 zero
= get_zero_immediate( emit
);
1383 one
= scalar( zero
, TGSI_SWIZZLE_W
);
1384 zero
= scalar( zero
, TGSI_SWIZZLE_X
);
1386 return emit_conditional(
1397 static boolean
emit_select_op(struct svga_shader_emitter
*emit
,
1399 const struct tgsi_full_instruction
*insn
)
1401 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1402 struct src_register src0
= translate_src_register(
1403 emit
, &insn
->Src
[0] );
1404 struct src_register src1
= translate_src_register(
1405 emit
, &insn
->Src
[1] );
1407 return emit_select( emit
, compare
, dst
, src0
, src1
);
1411 /* Translate texture instructions to SVGA3D representation.
1413 static boolean
emit_tex2(struct svga_shader_emitter
*emit
,
1414 const struct tgsi_full_instruction
*insn
,
1415 SVGA3dShaderDestToken dst
)
1417 SVGA3dShaderInstToken inst
;
1418 struct src_register texcoord
;
1419 struct src_register sampler
;
1420 SVGA3dShaderDestToken tmp
;
1424 switch (insn
->Instruction
.Opcode
) {
1425 case TGSI_OPCODE_TEX
:
1426 inst
.op
= SVGA3DOP_TEX
;
1428 case TGSI_OPCODE_TXP
:
1429 inst
.op
= SVGA3DOP_TEX
;
1430 inst
.control
= SVGA3DOPCONT_PROJECT
;
1432 case TGSI_OPCODE_TXB
:
1433 inst
.op
= SVGA3DOP_TEX
;
1434 inst
.control
= SVGA3DOPCONT_BIAS
;
1436 case TGSI_OPCODE_TXL
:
1437 inst
.op
= SVGA3DOP_TEXLDL
;
1444 texcoord
= translate_src_register( emit
, &insn
->Src
[0] );
1445 sampler
= translate_src_register( emit
, &insn
->Src
[1] );
1447 if (emit
->key
.fkey
.tex
[sampler
.base
.num
].unnormalized
||
1448 emit
->dynamic_branching_level
> 0)
1449 tmp
= get_temp( emit
);
1451 /* Can't do mipmapping inside dynamic branch constructs. Force LOD
1452 * zero in that case.
1454 if (emit
->dynamic_branching_level
> 0 &&
1455 inst
.op
== SVGA3DOP_TEX
&&
1456 SVGA3dShaderGetRegType(texcoord
.base
.value
) == SVGA3DREG_TEMP
) {
1457 struct src_register zero
= get_zero_immediate( emit
);
1459 /* MOV tmp, texcoord */
1460 if (!submit_op1( emit
,
1461 inst_token( SVGA3DOP_MOV
),
1466 /* MOV tmp.w, zero */
1467 if (!submit_op1( emit
,
1468 inst_token( SVGA3DOP_MOV
),
1469 writemask( tmp
, TGSI_WRITEMASK_W
),
1470 scalar( zero
, TGSI_SWIZZLE_X
)))
1473 texcoord
= src( tmp
);
1474 inst
.op
= SVGA3DOP_TEXLDL
;
1477 /* Explicit normalization of texcoords:
1479 if (emit
->key
.fkey
.tex
[sampler
.base
.num
].unnormalized
) {
1480 struct src_register wh
= get_tex_dimensions( emit
, sampler
.base
.num
);
1482 /* MUL tmp, SRC0, WH */
1483 if (!submit_op2( emit
, inst_token( SVGA3DOP_MUL
),
1484 tmp
, texcoord
, wh
))
1487 texcoord
= src( tmp
);
1490 return submit_op2( emit
, inst
, dst
, texcoord
, sampler
);
1496 /* Translate texture instructions to SVGA3D representation.
1498 static boolean
emit_tex4(struct svga_shader_emitter
*emit
,
1499 const struct tgsi_full_instruction
*insn
,
1500 SVGA3dShaderDestToken dst
)
1502 SVGA3dShaderInstToken inst
;
1503 struct src_register texcoord
;
1504 struct src_register ddx
;
1505 struct src_register ddy
;
1506 struct src_register sampler
;
1508 texcoord
= translate_src_register( emit
, &insn
->Src
[0] );
1509 ddx
= translate_src_register( emit
, &insn
->Src
[1] );
1510 ddy
= translate_src_register( emit
, &insn
->Src
[2] );
1511 sampler
= translate_src_register( emit
, &insn
->Src
[3] );
1515 switch (insn
->Instruction
.Opcode
) {
1516 case TGSI_OPCODE_TXD
:
1517 inst
.op
= SVGA3DOP_TEXLDD
; /* 4 args! */
1524 return submit_op4( emit
, inst
, dst
, texcoord
, sampler
, ddx
, ddy
);
1529 * Emit texture swizzle code.
1531 static boolean
emit_tex_swizzle( struct svga_shader_emitter
*emit
,
1532 SVGA3dShaderDestToken dst
,
1533 struct src_register src
,
1539 const unsigned swizzleIn
[4] = {swizzle_x
, swizzle_y
, swizzle_z
, swizzle_w
};
1540 unsigned srcSwizzle
[4];
1541 unsigned srcWritemask
= 0x0, zeroWritemask
= 0x0, oneWritemask
= 0x0;
1544 /* build writemasks and srcSwizzle terms */
1545 for (i
= 0; i
< 4; i
++) {
1546 if (swizzleIn
[i
] == PIPE_SWIZZLE_ZERO
) {
1547 srcSwizzle
[i
] = TGSI_SWIZZLE_X
+ i
;
1548 zeroWritemask
|= (1 << i
);
1550 else if (swizzleIn
[i
] == PIPE_SWIZZLE_ONE
) {
1551 srcSwizzle
[i
] = TGSI_SWIZZLE_X
+ i
;
1552 oneWritemask
|= (1 << i
);
1555 srcSwizzle
[i
] = swizzleIn
[i
];
1556 srcWritemask
|= (1 << i
);
1560 /* write x/y/z/w comps */
1561 if (dst
.mask
& srcWritemask
) {
1562 if (!submit_op1(emit
,
1563 inst_token(SVGA3DOP_MOV
),
1564 writemask(dst
, srcWritemask
),
1574 if (dst
.mask
& zeroWritemask
) {
1575 if (!submit_op1(emit
,
1576 inst_token(SVGA3DOP_MOV
),
1577 writemask(dst
, zeroWritemask
),
1578 scalar(get_zero_immediate(emit
), TGSI_SWIZZLE_X
)))
1583 if (dst
.mask
& oneWritemask
) {
1584 if (!submit_op1(emit
,
1585 inst_token(SVGA3DOP_MOV
),
1586 writemask(dst
, oneWritemask
),
1587 scalar(get_zero_immediate(emit
), TGSI_SWIZZLE_W
)))
1595 static boolean
emit_tex(struct svga_shader_emitter
*emit
,
1596 const struct tgsi_full_instruction
*insn
)
1598 SVGA3dShaderDestToken dst
=
1599 translate_dst_register( emit
, insn
, 0 );
1600 struct src_register src0
=
1601 translate_src_register( emit
, &insn
->Src
[0] );
1602 struct src_register src1
=
1603 translate_src_register( emit
, &insn
->Src
[1] );
1605 SVGA3dShaderDestToken tex_result
;
1606 const unsigned unit
= src1
.base
.num
;
1608 /* check for shadow samplers */
1609 boolean compare
= (emit
->key
.fkey
.tex
[unit
].compare_mode
==
1610 PIPE_TEX_COMPARE_R_TO_TEXTURE
);
1612 /* texture swizzle */
1613 boolean swizzle
= (emit
->key
.fkey
.tex
[unit
].swizzle_r
!= PIPE_SWIZZLE_RED
||
1614 emit
->key
.fkey
.tex
[unit
].swizzle_g
!= PIPE_SWIZZLE_GREEN
||
1615 emit
->key
.fkey
.tex
[unit
].swizzle_b
!= PIPE_SWIZZLE_BLUE
||
1616 emit
->key
.fkey
.tex
[unit
].swizzle_a
!= PIPE_SWIZZLE_ALPHA
);
1618 /* If doing compare processing or tex swizzle, need to put fetched color into
1619 * a temporary so it can be used as a source later on.
1623 (!emit
->use_sm30
&& dst
.mask
!= TGSI_WRITEMASK_XYZW
) ) {
1624 tex_result
= get_temp( emit
);
1630 switch(insn
->Instruction
.Opcode
) {
1631 case TGSI_OPCODE_TEX
:
1632 case TGSI_OPCODE_TXB
:
1633 case TGSI_OPCODE_TXP
:
1634 case TGSI_OPCODE_TXL
:
1635 if (!emit_tex2( emit
, insn
, tex_result
))
1638 case TGSI_OPCODE_TXD
:
1639 if (!emit_tex4( emit
, insn
, tex_result
))
1648 SVGA3dShaderDestToken dst2
;
1655 if (dst
.mask
& TGSI_WRITEMASK_XYZ
) {
1656 SVGA3dShaderDestToken src0_zdivw
= get_temp( emit
);
1657 /* When sampling a depth texture, the result of the comparison is in
1660 struct src_register tex_src_x
= scalar(src(tex_result
), TGSI_SWIZZLE_Y
);
1662 /* Divide texcoord R by Q */
1663 if (!submit_op1( emit
, inst_token( SVGA3DOP_RCP
),
1664 writemask(src0_zdivw
, TGSI_WRITEMASK_X
),
1665 scalar(src0
, TGSI_SWIZZLE_W
) ))
1668 if (!submit_op2( emit
, inst_token( SVGA3DOP_MUL
),
1669 writemask(src0_zdivw
, TGSI_WRITEMASK_X
),
1670 scalar(src0
, TGSI_SWIZZLE_Z
),
1671 scalar(src(src0_zdivw
), TGSI_SWIZZLE_X
) ))
1676 emit
->key
.fkey
.tex
[unit
].compare_func
,
1677 writemask( dst2
, TGSI_WRITEMASK_XYZ
),
1678 scalar(src(src0_zdivw
), TGSI_SWIZZLE_X
),
1683 if (dst
.mask
& TGSI_WRITEMASK_W
) {
1684 struct src_register one
=
1685 scalar( get_zero_immediate( emit
), TGSI_SWIZZLE_W
);
1687 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
1688 writemask( dst2
, TGSI_WRITEMASK_W
),
1695 /* swizzle from tex_result to dst */
1696 emit_tex_swizzle(emit
,
1697 dst
, src(tex_result
),
1698 emit
->key
.fkey
.tex
[unit
].swizzle_r
,
1699 emit
->key
.fkey
.tex
[unit
].swizzle_g
,
1700 emit
->key
.fkey
.tex
[unit
].swizzle_b
,
1701 emit
->key
.fkey
.tex
[unit
].swizzle_a
);
1704 if (!emit
->use_sm30
&&
1705 dst
.mask
!= TGSI_WRITEMASK_XYZW
&&
1708 /* pre SM3.0 a TEX instruction can't have a writemask. Do it as a
1709 * separate step here.
1711 if (!emit_op1( emit
, inst_token( SVGA3DOP_MOV
), dst
, src(tex_result
) ))
1718 static boolean
emit_bgnloop2( struct svga_shader_emitter
*emit
,
1719 const struct tgsi_full_instruction
*insn
)
1721 SVGA3dShaderInstToken inst
= inst_token( SVGA3DOP_LOOP
);
1722 struct src_register loop_reg
= src_register( SVGA3DREG_LOOP
, 0 );
1723 struct src_register const_int
= get_loop_const( emit
);
1725 emit
->dynamic_branching_level
++;
1727 return (emit_instruction( emit
, inst
) &&
1728 emit_src( emit
, loop_reg
) &&
1729 emit_src( emit
, const_int
) );
1732 static boolean
emit_endloop2( struct svga_shader_emitter
*emit
,
1733 const struct tgsi_full_instruction
*insn
)
1735 SVGA3dShaderInstToken inst
= inst_token( SVGA3DOP_ENDLOOP
);
1737 emit
->dynamic_branching_level
--;
1739 return emit_instruction( emit
, inst
);
1742 static boolean
emit_brk( struct svga_shader_emitter
*emit
,
1743 const struct tgsi_full_instruction
*insn
)
1745 SVGA3dShaderInstToken inst
= inst_token( SVGA3DOP_BREAK
);
1746 return emit_instruction( emit
, inst
);
1749 static boolean
emit_scalar_op1( struct svga_shader_emitter
*emit
,
1751 const struct tgsi_full_instruction
*insn
)
1753 SVGA3dShaderInstToken inst
;
1754 SVGA3dShaderDestToken dst
;
1755 struct src_register src
;
1757 inst
= inst_token( opcode
);
1758 dst
= translate_dst_register( emit
, insn
, 0 );
1759 src
= translate_src_register( emit
, &insn
->Src
[0] );
1760 src
= scalar( src
, TGSI_SWIZZLE_X
);
1762 return submit_op1( emit
, inst
, dst
, src
);
1766 static boolean
emit_simple_instruction(struct svga_shader_emitter
*emit
,
1768 const struct tgsi_full_instruction
*insn
)
1770 const struct tgsi_full_src_register
*src
= insn
->Src
;
1771 SVGA3dShaderInstToken inst
;
1772 SVGA3dShaderDestToken dst
;
1774 inst
= inst_token( opcode
);
1775 dst
= translate_dst_register( emit
, insn
, 0 );
1777 switch (insn
->Instruction
.NumSrcRegs
) {
1779 return submit_op0( emit
, inst
, dst
);
1781 return submit_op1( emit
, inst
, dst
,
1782 translate_src_register( emit
, &src
[0] ));
1784 return submit_op2( emit
, inst
, dst
,
1785 translate_src_register( emit
, &src
[0] ),
1786 translate_src_register( emit
, &src
[1] ) );
1788 return submit_op3( emit
, inst
, dst
,
1789 translate_src_register( emit
, &src
[0] ),
1790 translate_src_register( emit
, &src
[1] ),
1791 translate_src_register( emit
, &src
[2] ) );
1799 static boolean
emit_deriv(struct svga_shader_emitter
*emit
,
1800 const struct tgsi_full_instruction
*insn
)
1802 if (emit
->dynamic_branching_level
> 0 &&
1803 insn
->Src
[0].Register
.File
== TGSI_FILE_TEMPORARY
)
1805 struct src_register zero
= get_zero_immediate( emit
);
1806 SVGA3dShaderDestToken dst
=
1807 translate_dst_register( emit
, insn
, 0 );
1809 /* Deriv opcodes not valid inside dynamic branching, workaround
1810 * by zeroing out the destination.
1812 if (!submit_op1(emit
,
1813 inst_token( SVGA3DOP_MOV
),
1815 scalar(zero
, TGSI_SWIZZLE_X
)))
1822 const struct tgsi_full_src_register
*reg
= &insn
->Src
[0];
1823 SVGA3dShaderInstToken inst
;
1824 SVGA3dShaderDestToken dst
;
1825 struct src_register src0
;
1827 switch (insn
->Instruction
.Opcode
) {
1828 case TGSI_OPCODE_DDX
:
1829 opcode
= SVGA3DOP_DSX
;
1831 case TGSI_OPCODE_DDY
:
1832 opcode
= SVGA3DOP_DSY
;
1838 inst
= inst_token( opcode
);
1839 dst
= translate_dst_register( emit
, insn
, 0 );
1840 src0
= translate_src_register( emit
, reg
);
1842 /* We cannot use negate or abs on source to dsx/dsy instruction.
1844 if (reg
->Register
.Absolute
||
1845 reg
->Register
.Negate
) {
1846 SVGA3dShaderDestToken temp
= get_temp( emit
);
1848 if (!emit_repl( emit
, temp
, &src0
))
1852 return submit_op1( emit
, inst
, dst
, src0
);
1856 static boolean
emit_arl(struct svga_shader_emitter
*emit
,
1857 const struct tgsi_full_instruction
*insn
)
1859 ++emit
->current_arl
;
1860 if (emit
->unit
== PIPE_SHADER_FRAGMENT
) {
1861 /* MOVA not present in pixel shader instruction set.
1862 * Ignore this instruction altogether since it is
1863 * only used for loop counters -- and for that
1864 * we reference aL directly.
1868 if (svga_arl_needs_adjustment( emit
)) {
1869 return emit_fake_arl( emit
, insn
);
1871 /* no need to adjust, just emit straight arl */
1872 return emit_simple_instruction(emit
, SVGA3DOP_MOVA
, insn
);
1876 static boolean
emit_pow(struct svga_shader_emitter
*emit
,
1877 const struct tgsi_full_instruction
*insn
)
1879 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1880 struct src_register src0
= translate_src_register(
1881 emit
, &insn
->Src
[0] );
1882 struct src_register src1
= translate_src_register(
1883 emit
, &insn
->Src
[1] );
1884 boolean need_tmp
= FALSE
;
1886 /* POW can only output to a temporary */
1887 if (insn
->Dst
[0].Register
.File
!= TGSI_FILE_TEMPORARY
)
1890 /* POW src1 must not be the same register as dst */
1891 if (alias_src_dst( src1
, dst
))
1894 /* it's a scalar op */
1895 src0
= scalar( src0
, TGSI_SWIZZLE_X
);
1896 src1
= scalar( src1
, TGSI_SWIZZLE_X
);
1899 SVGA3dShaderDestToken tmp
= writemask(get_temp( emit
), TGSI_WRITEMASK_X
);
1901 if (!submit_op2(emit
, inst_token( SVGA3DOP_POW
), tmp
, src0
, src1
))
1904 return submit_op1(emit
, inst_token( SVGA3DOP_MOV
), dst
, scalar(src(tmp
), 0) );
1907 return submit_op2(emit
, inst_token( SVGA3DOP_POW
), dst
, src0
, src1
);
1911 static boolean
emit_xpd(struct svga_shader_emitter
*emit
,
1912 const struct tgsi_full_instruction
*insn
)
1914 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1915 const struct src_register src0
= translate_src_register(
1916 emit
, &insn
->Src
[0] );
1917 const struct src_register src1
= translate_src_register(
1918 emit
, &insn
->Src
[1] );
1919 boolean need_dst_tmp
= FALSE
;
1921 /* XPD can only output to a temporary */
1922 if (SVGA3dShaderGetRegType(dst
.value
) != SVGA3DREG_TEMP
)
1923 need_dst_tmp
= TRUE
;
1925 /* The dst reg must not be the same as src0 or src1*/
1926 if (alias_src_dst(src0
, dst
) ||
1927 alias_src_dst(src1
, dst
))
1928 need_dst_tmp
= TRUE
;
1931 SVGA3dShaderDestToken tmp
= get_temp( emit
);
1933 /* Obey DX9 restrictions on mask:
1935 tmp
.mask
= dst
.mask
& TGSI_WRITEMASK_XYZ
;
1937 if (!submit_op2(emit
, inst_token( SVGA3DOP_CRS
), tmp
, src0
, src1
))
1940 if (!submit_op1(emit
, inst_token( SVGA3DOP_MOV
), dst
, src( tmp
)))
1944 if (!submit_op2(emit
, inst_token( SVGA3DOP_CRS
), dst
, src0
, src1
))
1948 /* Need to emit 1.0 to dst.w?
1950 if (dst
.mask
& TGSI_WRITEMASK_W
) {
1951 struct src_register zero
= get_zero_immediate( emit
);
1953 if (!submit_op1(emit
,
1954 inst_token( SVGA3DOP_MOV
),
1955 writemask(dst
, TGSI_WRITEMASK_W
),
1964 static boolean
emit_lrp(struct svga_shader_emitter
*emit
,
1965 const struct tgsi_full_instruction
*insn
)
1967 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1968 const struct src_register src0
= translate_src_register(
1969 emit
, &insn
->Src
[0] );
1970 const struct src_register src1
= translate_src_register(
1971 emit
, &insn
->Src
[1] );
1972 const struct src_register src2
= translate_src_register(
1973 emit
, &insn
->Src
[2] );
1975 return submit_lrp(emit
, dst
, src0
, src1
, src2
);
1979 static boolean
emit_dst_insn(struct svga_shader_emitter
*emit
,
1980 const struct tgsi_full_instruction
*insn
)
1982 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
1983 /* SVGA/DX9 has a DST instruction, but only for vertex shaders:
1985 return emit_simple_instruction(emit
, SVGA3DOP_DST
, insn
);
1989 /* result[0] = 1 * 1;
1990 * result[1] = a[1] * b[1];
1991 * result[2] = a[2] * 1;
1992 * result[3] = 1 * b[3];
1995 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1996 SVGA3dShaderDestToken tmp
;
1997 const struct src_register src0
= translate_src_register(
1998 emit
, &insn
->Src
[0] );
1999 const struct src_register src1
= translate_src_register(
2000 emit
, &insn
->Src
[1] );
2001 struct src_register zero
= get_zero_immediate( emit
);
2002 boolean need_tmp
= FALSE
;
2004 if (SVGA3dShaderGetRegType(dst
.value
) != SVGA3DREG_TEMP
||
2005 alias_src_dst(src0
, dst
) ||
2006 alias_src_dst(src1
, dst
))
2010 tmp
= get_temp( emit
);
2018 if (tmp
.mask
& TGSI_WRITEMASK_XW
) {
2019 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
2020 writemask(tmp
, TGSI_WRITEMASK_XW
),
2027 if (tmp
.mask
& TGSI_WRITEMASK_YZ
) {
2028 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
2029 writemask(tmp
, TGSI_WRITEMASK_YZ
),
2034 /* tmp.yw = tmp * src1
2036 if (tmp
.mask
& TGSI_WRITEMASK_YW
) {
2037 if (!submit_op2( emit
, inst_token( SVGA3DOP_MUL
),
2038 writemask(tmp
, TGSI_WRITEMASK_YW
),
2047 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
2058 static boolean
emit_exp(struct svga_shader_emitter
*emit
,
2059 const struct tgsi_full_instruction
*insn
)
2061 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
2062 struct src_register src0
=
2063 translate_src_register( emit
, &insn
->Src
[0] );
2064 struct src_register zero
= get_zero_immediate( emit
);
2065 SVGA3dShaderDestToken fraction
;
2067 if (dst
.mask
& TGSI_WRITEMASK_Y
)
2069 else if (dst
.mask
& TGSI_WRITEMASK_X
)
2070 fraction
= get_temp( emit
);
2074 /* If y is being written, fill it with src0 - floor(src0).
2076 if (dst
.mask
& TGSI_WRITEMASK_XY
) {
2077 if (!submit_op1( emit
, inst_token( SVGA3DOP_FRC
),
2078 writemask( fraction
, TGSI_WRITEMASK_Y
),
2083 /* If x is being written, fill it with 2 ^ floor(src0).
2085 if (dst
.mask
& TGSI_WRITEMASK_X
) {
2086 if (!submit_op2( emit
, inst_token( SVGA3DOP_ADD
),
2087 writemask( dst
, TGSI_WRITEMASK_X
),
2089 scalar( negate( src( fraction
) ), TGSI_SWIZZLE_Y
) ) )
2092 if (!submit_op1( emit
, inst_token( SVGA3DOP_EXP
),
2093 writemask( dst
, TGSI_WRITEMASK_X
),
2094 scalar( src( dst
), TGSI_SWIZZLE_X
) ) )
2097 if (!(dst
.mask
& TGSI_WRITEMASK_Y
))
2098 release_temp( emit
, fraction
);
2101 /* If z is being written, fill it with 2 ^ src0 (partial precision).
2103 if (dst
.mask
& TGSI_WRITEMASK_Z
) {
2104 if (!submit_op1( emit
, inst_token( SVGA3DOP_EXPP
),
2105 writemask( dst
, TGSI_WRITEMASK_Z
),
2110 /* If w is being written, fill it with one.
2112 if (dst
.mask
& TGSI_WRITEMASK_W
) {
2113 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
2114 writemask(dst
, TGSI_WRITEMASK_W
),
2115 scalar( zero
, TGSI_SWIZZLE_W
) ))
2122 static boolean
emit_lit(struct svga_shader_emitter
*emit
,
2123 const struct tgsi_full_instruction
*insn
)
2125 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
2126 /* SVGA/DX9 has a LIT instruction, but only for vertex shaders:
2128 return emit_simple_instruction(emit
, SVGA3DOP_LIT
, insn
);
2132 /* D3D vs. GL semantics can be fairly easily accomodated by
2133 * variations on this sequence.
2137 * tmp.z = pow(src.y,src.w)
2138 * p0 = src0.xxxx > 0
2139 * result = zero.wxxw
2140 * (p0) result.yz = tmp
2144 * tmp.z = pow(src.y,src.w)
2145 * p0 = src0.xxyy > 0
2146 * result = zero.wxxw
2147 * (p0) result.yz = tmp
2149 * Will implement the GL version for now.
2152 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
2153 SVGA3dShaderDestToken tmp
= get_temp( emit
);
2154 const struct src_register src0
= translate_src_register(
2155 emit
, &insn
->Src
[0] );
2156 struct src_register zero
= get_zero_immediate( emit
);
2158 /* tmp = pow(src.y, src.w)
2160 if (dst
.mask
& TGSI_WRITEMASK_Z
) {
2161 if (!submit_op2(emit
, inst_token( SVGA3DOP_POW
),
2170 if (dst
.mask
& TGSI_WRITEMASK_Y
) {
2171 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
2172 writemask(tmp
, TGSI_WRITEMASK_Y
),
2177 /* Can't quite do this with emit conditional due to the extra
2178 * writemask on the predicated mov:
2181 SVGA3dShaderDestToken pred_reg
= dst_register( SVGA3DREG_PREDICATE
, 0 );
2182 SVGA3dShaderInstToken setp_token
, mov_token
;
2183 struct src_register predsrc
;
2185 setp_token
= inst_token( SVGA3DOP_SETP
);
2186 mov_token
= inst_token( SVGA3DOP_MOV
);
2188 setp_token
.control
= SVGA3DOPCOMP_GT
;
2190 /* D3D vs GL semantics:
2193 predsrc
= swizzle(src0
, 0, 0, 1, 1); /* D3D */
2195 predsrc
= swizzle(src0
, 0, 0, 0, 0); /* GL */
2197 /* SETP src0.xxyy, GT, {0}.x */
2198 if (!submit_op2( emit
, setp_token
, pred_reg
,
2200 swizzle(zero
, 0, 0, 0, 0) ))
2204 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), dst
,
2205 swizzle(zero
, 3, 0, 0, 3 )))
2208 /* MOV dst.yz, tmp (predicated)
2210 * Note that the predicate reg (and possible modifiers) is passed
2211 * as the first source argument.
2213 if (dst
.mask
& TGSI_WRITEMASK_YZ
) {
2214 mov_token
.predicated
= 1;
2215 if (!submit_op2( emit
, mov_token
,
2216 writemask(dst
, TGSI_WRITEMASK_YZ
),
2217 src( pred_reg
), src( tmp
) ))
2229 static boolean
emit_ex2( struct svga_shader_emitter
*emit
,
2230 const struct tgsi_full_instruction
*insn
)
2232 SVGA3dShaderInstToken inst
;
2233 SVGA3dShaderDestToken dst
;
2234 struct src_register src0
;
2236 inst
= inst_token( SVGA3DOP_EXP
);
2237 dst
= translate_dst_register( emit
, insn
, 0 );
2238 src0
= translate_src_register( emit
, &insn
->Src
[0] );
2239 src0
= scalar( src0
, TGSI_SWIZZLE_X
);
2241 if (dst
.mask
!= TGSI_WRITEMASK_XYZW
) {
2242 SVGA3dShaderDestToken tmp
= get_temp( emit
);
2244 if (!submit_op1( emit
, inst
, tmp
, src0
))
2247 return submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
2249 scalar( src( tmp
), TGSI_SWIZZLE_X
) );
2252 return submit_op1( emit
, inst
, dst
, src0
);
2256 static boolean
emit_log(struct svga_shader_emitter
*emit
,
2257 const struct tgsi_full_instruction
*insn
)
2259 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
2260 struct src_register src0
=
2261 translate_src_register( emit
, &insn
->Src
[0] );
2262 struct src_register zero
= get_zero_immediate( emit
);
2263 SVGA3dShaderDestToken abs_tmp
;
2264 struct src_register abs_src0
;
2265 SVGA3dShaderDestToken log2_abs
;
2269 if (dst
.mask
& TGSI_WRITEMASK_Z
)
2271 else if (dst
.mask
& TGSI_WRITEMASK_XY
)
2272 log2_abs
= get_temp( emit
);
2276 /* If z is being written, fill it with log2( abs( src0 ) ).
2278 if (dst
.mask
& TGSI_WRITEMASK_XYZ
) {
2279 if (!src0
.base
.srcMod
|| src0
.base
.srcMod
== SVGA3DSRCMOD_ABS
)
2282 abs_tmp
= get_temp( emit
);
2284 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
2289 abs_src0
= src( abs_tmp
);
2292 abs_src0
= absolute( scalar( abs_src0
, TGSI_SWIZZLE_X
) );
2294 if (!submit_op1( emit
, inst_token( SVGA3DOP_LOG
),
2295 writemask( log2_abs
, TGSI_WRITEMASK_Z
),
2300 if (dst
.mask
& TGSI_WRITEMASK_XY
) {
2301 SVGA3dShaderDestToken floor_log2
;
2303 if (dst
.mask
& TGSI_WRITEMASK_X
)
2306 floor_log2
= get_temp( emit
);
2308 /* If x is being written, fill it with floor( log2( abs( src0 ) ) ).
2310 if (!submit_op1( emit
, inst_token( SVGA3DOP_FRC
),
2311 writemask( floor_log2
, TGSI_WRITEMASK_X
),
2312 scalar( src( log2_abs
), TGSI_SWIZZLE_Z
) ) )
2315 if (!submit_op2( emit
, inst_token( SVGA3DOP_ADD
),
2316 writemask( floor_log2
, TGSI_WRITEMASK_X
),
2317 scalar( src( log2_abs
), TGSI_SWIZZLE_Z
),
2318 negate( src( floor_log2
) ) ) )
2321 /* If y is being written, fill it with
2322 * abs ( src0 ) / ( 2 ^ floor( log2( abs( src0 ) ) ) ).
2324 if (dst
.mask
& TGSI_WRITEMASK_Y
) {
2325 if (!submit_op1( emit
, inst_token( SVGA3DOP_EXP
),
2326 writemask( dst
, TGSI_WRITEMASK_Y
),
2327 negate( scalar( src( floor_log2
),
2328 TGSI_SWIZZLE_X
) ) ) )
2331 if (!submit_op2( emit
, inst_token( SVGA3DOP_MUL
),
2332 writemask( dst
, TGSI_WRITEMASK_Y
),
2338 if (!(dst
.mask
& TGSI_WRITEMASK_X
))
2339 release_temp( emit
, floor_log2
);
2341 if (!(dst
.mask
& TGSI_WRITEMASK_Z
))
2342 release_temp( emit
, log2_abs
);
2345 if (dst
.mask
& TGSI_WRITEMASK_XYZ
&& src0
.base
.srcMod
&&
2346 src0
.base
.srcMod
!= SVGA3DSRCMOD_ABS
)
2347 release_temp( emit
, abs_tmp
);
2349 /* If w is being written, fill it with one.
2351 if (dst
.mask
& TGSI_WRITEMASK_W
) {
2352 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
2353 writemask(dst
, TGSI_WRITEMASK_W
),
2354 scalar( zero
, TGSI_SWIZZLE_W
) ))
2362 static boolean
emit_bgnsub( struct svga_shader_emitter
*emit
,
2364 const struct tgsi_full_instruction
*insn
)
2368 /* Note that we've finished the main function and are now emitting
2369 * subroutines. This affects how we terminate the generated
2372 emit
->in_main_func
= FALSE
;
2374 for (i
= 0; i
< emit
->nr_labels
; i
++) {
2375 if (emit
->label
[i
] == position
) {
2376 return (emit_instruction( emit
, inst_token( SVGA3DOP_RET
) ) &&
2377 emit_instruction( emit
, inst_token( SVGA3DOP_LABEL
) ) &&
2378 emit_src( emit
, src_register( SVGA3DREG_LABEL
, i
)));
2386 static boolean
emit_call( struct svga_shader_emitter
*emit
,
2387 const struct tgsi_full_instruction
*insn
)
2389 unsigned position
= insn
->Label
.Label
;
2392 for (i
= 0; i
< emit
->nr_labels
; i
++) {
2393 if (emit
->label
[i
] == position
)
2397 if (emit
->nr_labels
== Elements(emit
->label
))
2400 if (i
== emit
->nr_labels
) {
2401 emit
->label
[i
] = position
;
2405 return (emit_instruction( emit
, inst_token( SVGA3DOP_CALL
) ) &&
2406 emit_src( emit
, src_register( SVGA3DREG_LABEL
, i
)));
2410 static boolean
emit_end( struct svga_shader_emitter
*emit
)
2412 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
2413 return emit_vs_postamble( emit
);
2416 return emit_ps_postamble( emit
);
2422 static boolean
svga_emit_instruction( struct svga_shader_emitter
*emit
,
2424 const struct tgsi_full_instruction
*insn
)
2426 switch (insn
->Instruction
.Opcode
) {
2428 case TGSI_OPCODE_ARL
:
2429 return emit_arl( emit
, insn
);
2431 case TGSI_OPCODE_TEX
:
2432 case TGSI_OPCODE_TXB
:
2433 case TGSI_OPCODE_TXP
:
2434 case TGSI_OPCODE_TXL
:
2435 case TGSI_OPCODE_TXD
:
2436 return emit_tex( emit
, insn
);
2438 case TGSI_OPCODE_DDX
:
2439 case TGSI_OPCODE_DDY
:
2440 return emit_deriv( emit
, insn
);
2442 case TGSI_OPCODE_BGNSUB
:
2443 return emit_bgnsub( emit
, position
, insn
);
2445 case TGSI_OPCODE_ENDSUB
:
2448 case TGSI_OPCODE_CAL
:
2449 return emit_call( emit
, insn
);
2451 case TGSI_OPCODE_FLR
:
2452 case TGSI_OPCODE_TRUNC
: /* should be TRUNC, not FLR */
2453 return emit_floor( emit
, insn
);
2455 case TGSI_OPCODE_CMP
:
2456 return emit_cmp( emit
, insn
);
2458 case TGSI_OPCODE_DIV
:
2459 return emit_div( emit
, insn
);
2461 case TGSI_OPCODE_DP2
:
2462 return emit_dp2( emit
, insn
);
2464 case TGSI_OPCODE_DPH
:
2465 return emit_dph( emit
, insn
);
2467 case TGSI_OPCODE_NRM
:
2468 return emit_nrm( emit
, insn
);
2470 case TGSI_OPCODE_COS
:
2471 return emit_cos( emit
, insn
);
2473 case TGSI_OPCODE_SIN
:
2474 return emit_sin( emit
, insn
);
2476 case TGSI_OPCODE_SCS
:
2477 return emit_sincos( emit
, insn
);
2479 case TGSI_OPCODE_END
:
2480 /* TGSI always finishes the main func with an END */
2481 return emit_end( emit
);
2483 case TGSI_OPCODE_KIL
:
2484 return emit_kil( emit
, insn
);
2486 /* Selection opcodes. The underlying language is fairly
2487 * non-orthogonal about these.
2489 case TGSI_OPCODE_SEQ
:
2490 return emit_select_op( emit
, PIPE_FUNC_EQUAL
, insn
);
2492 case TGSI_OPCODE_SNE
:
2493 return emit_select_op( emit
, PIPE_FUNC_NOTEQUAL
, insn
);
2495 case TGSI_OPCODE_SGT
:
2496 return emit_select_op( emit
, PIPE_FUNC_GREATER
, insn
);
2498 case TGSI_OPCODE_SGE
:
2499 return emit_select_op( emit
, PIPE_FUNC_GEQUAL
, insn
);
2501 case TGSI_OPCODE_SLT
:
2502 return emit_select_op( emit
, PIPE_FUNC_LESS
, insn
);
2504 case TGSI_OPCODE_SLE
:
2505 return emit_select_op( emit
, PIPE_FUNC_LEQUAL
, insn
);
2507 case TGSI_OPCODE_SUB
:
2508 return emit_sub( emit
, insn
);
2510 case TGSI_OPCODE_POW
:
2511 return emit_pow( emit
, insn
);
2513 case TGSI_OPCODE_EX2
:
2514 return emit_ex2( emit
, insn
);
2516 case TGSI_OPCODE_EXP
:
2517 return emit_exp( emit
, insn
);
2519 case TGSI_OPCODE_LOG
:
2520 return emit_log( emit
, insn
);
2522 case TGSI_OPCODE_LG2
:
2523 return emit_scalar_op1( emit
, SVGA3DOP_LOG
, insn
);
2525 case TGSI_OPCODE_RSQ
:
2526 return emit_scalar_op1( emit
, SVGA3DOP_RSQ
, insn
);
2528 case TGSI_OPCODE_RCP
:
2529 return emit_scalar_op1( emit
, SVGA3DOP_RCP
, insn
);
2531 case TGSI_OPCODE_CONT
:
2532 case TGSI_OPCODE_RET
:
2533 /* This is a noop -- we tell mesa that we can't support RET
2534 * within a function (early return), so this will always be
2535 * followed by an ENDSUB.
2539 /* These aren't actually used by any of the frontends we care
2542 case TGSI_OPCODE_CLAMP
:
2543 case TGSI_OPCODE_ROUND
:
2544 case TGSI_OPCODE_AND
:
2545 case TGSI_OPCODE_OR
:
2546 case TGSI_OPCODE_I2F
:
2547 case TGSI_OPCODE_NOT
:
2548 case TGSI_OPCODE_SHL
:
2549 case TGSI_OPCODE_ISHR
:
2550 case TGSI_OPCODE_XOR
:
2553 case TGSI_OPCODE_IF
:
2554 return emit_if( emit
, insn
);
2555 case TGSI_OPCODE_ELSE
:
2556 return emit_else( emit
, insn
);
2557 case TGSI_OPCODE_ENDIF
:
2558 return emit_endif( emit
, insn
);
2560 case TGSI_OPCODE_BGNLOOP
:
2561 return emit_bgnloop2( emit
, insn
);
2562 case TGSI_OPCODE_ENDLOOP
:
2563 return emit_endloop2( emit
, insn
);
2564 case TGSI_OPCODE_BRK
:
2565 return emit_brk( emit
, insn
);
2567 case TGSI_OPCODE_XPD
:
2568 return emit_xpd( emit
, insn
);
2570 case TGSI_OPCODE_KILP
:
2571 return emit_kilp( emit
, insn
);
2573 case TGSI_OPCODE_DST
:
2574 return emit_dst_insn( emit
, insn
);
2576 case TGSI_OPCODE_LIT
:
2577 return emit_lit( emit
, insn
);
2579 case TGSI_OPCODE_LRP
:
2580 return emit_lrp( emit
, insn
);
2582 case TGSI_OPCODE_SSG
:
2583 return emit_ssg( emit
, insn
);
2586 unsigned opcode
= translate_opcode(insn
->Instruction
.Opcode
);
2588 if (opcode
== SVGA3DOP_LAST_INST
)
2591 if (!emit_simple_instruction( emit
, opcode
, insn
))
2600 static boolean
svga_emit_immediate( struct svga_shader_emitter
*emit
,
2601 struct tgsi_full_immediate
*imm
)
2603 static const float id
[4] = {0,0,0,1};
2607 assert(1 <= imm
->Immediate
.NrTokens
&& imm
->Immediate
.NrTokens
<= 5);
2608 for (i
= 0; i
< imm
->Immediate
.NrTokens
- 1; i
++)
2609 value
[i
] = imm
->u
[i
].Float
;
2611 for ( ; i
< 4; i
++ )
2614 return emit_def_const( emit
, SVGA3D_CONST_TYPE_FLOAT
,
2615 emit
->imm_start
+ emit
->internal_imm_count
++,
2616 value
[0], value
[1], value
[2], value
[3]);
2619 static boolean
make_immediate( struct svga_shader_emitter
*emit
,
2624 struct src_register
*out
)
2626 unsigned idx
= emit
->nr_hw_float_const
++;
2628 if (!emit_def_const( emit
, SVGA3D_CONST_TYPE_FLOAT
,
2632 *out
= src_register( SVGA3DREG_CONST
, idx
);
2637 static boolean
emit_vs_preamble( struct svga_shader_emitter
*emit
)
2639 if (!emit
->key
.vkey
.need_prescale
) {
2640 if (!make_immediate( emit
, 0, 0, .5, .5,
2648 static boolean
emit_ps_preamble( struct svga_shader_emitter
*emit
)
2652 /* For SM20, need to initialize the temporaries we're using to hold
2653 * color outputs to some value. Shaders which don't set all of
2654 * these values are likely to be rejected by the DX9 runtime.
2656 if (!emit
->use_sm30
) {
2657 struct src_register zero
= get_zero_immediate( emit
);
2658 for (i
= 0; i
< PIPE_MAX_COLOR_BUFS
; i
++) {
2659 if (SVGA3dShaderGetRegType(emit
->true_col
[i
].value
) != 0) {
2661 if (!submit_op1( emit
,
2662 inst_token(SVGA3DOP_MOV
),
2668 } else if (emit
->ps_reads_pos
&& emit
->info
.reads_z
) {
2670 * Assemble the position from various bits of inputs. Depth and W are
2671 * passed in a texcoord this is due to D3D's vPos not hold Z or W.
2672 * Also fixup the perspective interpolation.
2674 * temp_pos.xy = vPos.xy
2675 * temp_pos.w = rcp(texcoord1.w);
2676 * temp_pos.z = texcoord1.z * temp_pos.w;
2678 if (!submit_op1( emit
,
2679 inst_token(SVGA3DOP_MOV
),
2680 writemask( emit
->ps_temp_pos
, TGSI_WRITEMASK_XY
),
2681 emit
->ps_true_pos
))
2684 if (!submit_op1( emit
,
2685 inst_token(SVGA3DOP_RCP
),
2686 writemask( emit
->ps_temp_pos
, TGSI_WRITEMASK_W
),
2687 scalar( emit
->ps_depth_pos
, TGSI_SWIZZLE_W
) ))
2690 if (!submit_op2( emit
,
2691 inst_token(SVGA3DOP_MUL
),
2692 writemask( emit
->ps_temp_pos
, TGSI_WRITEMASK_Z
),
2693 scalar( emit
->ps_depth_pos
, TGSI_SWIZZLE_Z
),
2694 scalar( src(emit
->ps_temp_pos
), TGSI_SWIZZLE_W
) ))
2701 static boolean
emit_ps_postamble( struct svga_shader_emitter
*emit
)
2705 /* PS oDepth is incredibly fragile and it's very hard to catch the
2706 * types of usage that break it during shader emit. Easier just to
2707 * redirect the main program to a temporary and then only touch
2708 * oDepth with a hand-crafted MOV below.
2710 if (SVGA3dShaderGetRegType(emit
->true_pos
.value
) != 0) {
2712 if (!submit_op1( emit
,
2713 inst_token(SVGA3DOP_MOV
),
2715 scalar(src(emit
->temp_pos
), TGSI_SWIZZLE_Z
) ))
2719 /* Similarly for SM20 color outputs... Luckily SM30 isn't so
2722 for (i
= 0; i
< PIPE_MAX_COLOR_BUFS
; i
++) {
2723 if (SVGA3dShaderGetRegType(emit
->true_col
[i
].value
) != 0) {
2725 /* Potentially override output colors with white for XOR
2726 * logicop workaround.
2728 if (emit
->unit
== PIPE_SHADER_FRAGMENT
&&
2729 emit
->key
.fkey
.white_fragments
) {
2731 struct src_register one
= scalar( get_zero_immediate( emit
),
2734 if (!submit_op1( emit
,
2735 inst_token(SVGA3DOP_MOV
),
2741 if (!submit_op1( emit
,
2742 inst_token(SVGA3DOP_MOV
),
2744 src(emit
->temp_col
[i
]) ))
2753 static boolean
emit_vs_postamble( struct svga_shader_emitter
*emit
)
2755 /* PSIZ output is incredibly fragile and it's very hard to catch
2756 * the types of usage that break it during shader emit. Easier
2757 * just to redirect the main program to a temporary and then only
2758 * touch PSIZ with a hand-crafted MOV below.
2760 if (SVGA3dShaderGetRegType(emit
->true_psiz
.value
) != 0) {
2762 if (!submit_op1( emit
,
2763 inst_token(SVGA3DOP_MOV
),
2765 scalar(src(emit
->temp_psiz
), TGSI_SWIZZLE_X
) ))
2769 /* Need to perform various manipulations on vertex position to cope
2770 * with the different GL and D3D clip spaces.
2772 if (emit
->key
.vkey
.need_prescale
) {
2773 SVGA3dShaderDestToken temp_pos
= emit
->temp_pos
;
2774 SVGA3dShaderDestToken depth
= emit
->depth_pos
;
2775 SVGA3dShaderDestToken pos
= emit
->true_pos
;
2776 unsigned offset
= emit
->info
.file_max
[TGSI_FILE_CONSTANT
] + 1;
2777 struct src_register prescale_scale
= src_register( SVGA3DREG_CONST
,
2779 struct src_register prescale_trans
= src_register( SVGA3DREG_CONST
,
2782 if (!submit_op1( emit
,
2783 inst_token(SVGA3DOP_MOV
),
2784 writemask(depth
, TGSI_WRITEMASK_W
),
2785 scalar(src(temp_pos
), TGSI_SWIZZLE_W
) ))
2788 /* MUL temp_pos.xyz, temp_pos, prescale.scale
2789 * MAD result.position, temp_pos.wwww, prescale.trans, temp_pos
2790 * --> Note that prescale.trans.w == 0
2792 if (!submit_op2( emit
,
2793 inst_token(SVGA3DOP_MUL
),
2794 writemask(temp_pos
, TGSI_WRITEMASK_XYZ
),
2799 if (!submit_op3( emit
,
2800 inst_token(SVGA3DOP_MAD
),
2802 swizzle(src(temp_pos
), 3, 3, 3, 3),
2807 /* Also write to depth value */
2808 if (!submit_op3( emit
,
2809 inst_token(SVGA3DOP_MAD
),
2810 writemask(depth
, TGSI_WRITEMASK_Z
),
2811 swizzle(src(temp_pos
), 3, 3, 3, 3),
2817 SVGA3dShaderDestToken temp_pos
= emit
->temp_pos
;
2818 SVGA3dShaderDestToken depth
= emit
->depth_pos
;
2819 SVGA3dShaderDestToken pos
= emit
->true_pos
;
2820 struct src_register imm_0055
= emit
->imm_0055
;
2822 /* Adjust GL clipping coordinate space to hardware (D3D-style):
2824 * DP4 temp_pos.z, {0,0,.5,.5}, temp_pos
2825 * MOV result.position, temp_pos
2827 if (!submit_op2( emit
,
2828 inst_token(SVGA3DOP_DP4
),
2829 writemask(temp_pos
, TGSI_WRITEMASK_Z
),
2834 if (!submit_op1( emit
,
2835 inst_token(SVGA3DOP_MOV
),
2840 /* Move the manipulated depth into the extra texcoord reg */
2841 if (!submit_op1( emit
,
2842 inst_token(SVGA3DOP_MOV
),
2843 writemask(depth
, TGSI_WRITEMASK_ZW
),
2853 1: COLOR = FrontColor;
2855 3: COLOR = BackColor;
2858 static boolean
emit_light_twoside( struct svga_shader_emitter
*emit
)
2860 struct src_register vface
, zero
;
2861 struct src_register front
[2];
2862 struct src_register back
[2];
2863 SVGA3dShaderDestToken color
[2];
2864 int count
= emit
->internal_color_count
;
2866 SVGA3dShaderInstToken if_token
;
2871 vface
= get_vface( emit
);
2872 zero
= get_zero_immediate( emit
);
2874 /* Can't use get_temp() to allocate the color reg as such
2875 * temporaries will be reclaimed after each instruction by the call
2876 * to reset_temp_regs().
2878 for (i
= 0; i
< count
; i
++) {
2879 color
[i
] = dst_register( SVGA3DREG_TEMP
,
2880 emit
->nr_hw_temp
++ );
2882 front
[i
] = emit
->input_map
[emit
->internal_color_idx
[i
]];
2884 /* Back is always the next input:
2887 back
[i
].base
.num
= front
[i
].base
.num
+ 1;
2889 /* Reassign the input_map to the actual front-face color:
2891 emit
->input_map
[emit
->internal_color_idx
[i
]] = src(color
[i
]);
2894 if_token
= inst_token( SVGA3DOP_IFC
);
2896 if (emit
->key
.fkey
.front_ccw
)
2897 if_token
.control
= SVGA3DOPCOMP_LT
;
2899 if_token
.control
= SVGA3DOPCOMP_GT
;
2901 zero
= scalar(zero
, TGSI_SWIZZLE_X
);
2903 if (!(emit_instruction( emit
, if_token
) &&
2904 emit_src( emit
, vface
) &&
2905 emit_src( emit
, zero
) ))
2908 for (i
= 0; i
< count
; i
++) {
2909 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), color
[i
], front
[i
] ))
2913 if (!(emit_instruction( emit
, inst_token( SVGA3DOP_ELSE
))))
2916 for (i
= 0; i
< count
; i
++) {
2917 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), color
[i
], back
[i
] ))
2921 if (!emit_instruction( emit
, inst_token( SVGA3DOP_ENDIF
) ))
2928 0: SETP_GT TEMP, VFACE, 0
2929 where TEMP is a fake frontface register
2931 static boolean
emit_frontface( struct svga_shader_emitter
*emit
)
2933 struct src_register vface
, zero
;
2934 SVGA3dShaderDestToken temp
;
2935 struct src_register pass
, fail
;
2937 vface
= get_vface( emit
);
2938 zero
= get_zero_immediate( emit
);
2940 /* Can't use get_temp() to allocate the fake frontface reg as such
2941 * temporaries will be reclaimed after each instruction by the call
2942 * to reset_temp_regs().
2944 temp
= dst_register( SVGA3DREG_TEMP
,
2945 emit
->nr_hw_temp
++ );
2947 if (emit
->key
.fkey
.front_ccw
) {
2948 pass
= scalar( zero
, TGSI_SWIZZLE_X
);
2949 fail
= scalar( zero
, TGSI_SWIZZLE_W
);
2951 pass
= scalar( zero
, TGSI_SWIZZLE_W
);
2952 fail
= scalar( zero
, TGSI_SWIZZLE_X
);
2955 if (!emit_conditional(emit
, PIPE_FUNC_GREATER
,
2956 temp
, vface
, scalar( zero
, TGSI_SWIZZLE_X
),
2960 /* Reassign the input_map to the actual front-face color:
2962 emit
->input_map
[emit
->internal_frontface_idx
] = src(temp
);
2969 * Emit code to invert the T component of the incoming texture coordinate.
2970 * This is used for drawing point sprites when
2971 * pipe_rasterizer_state::sprite_coord_mode == PIPE_SPRITE_COORD_LOWER_LEFT.
2973 static boolean
emit_inverted_texcoords( struct svga_shader_emitter
*emit
)
2975 struct src_register zero
= get_zero_immediate(emit
);
2976 struct src_register pos_neg_one
= get_pos_neg_one_immediate( emit
);
2977 unsigned inverted_texcoords
= emit
->inverted_texcoords
;
2979 while (inverted_texcoords
) {
2980 const unsigned unit
= ffs(inverted_texcoords
) - 1;
2982 assert(emit
->inverted_texcoords
& (1 << unit
));
2984 assert(unit
< Elements(emit
->ps_true_texcoord
));
2986 assert(unit
< Elements(emit
->ps_inverted_texcoord_input
));
2988 assert(emit
->ps_inverted_texcoord_input
[unit
]
2989 < Elements(emit
->input_map
));
2991 /* inverted = coord * (1, -1, 1, 1) + (0, 1, 0, 0) */
2992 if (!submit_op3(emit
,
2993 inst_token(SVGA3DOP_MAD
),
2994 dst(emit
->ps_inverted_texcoord
[unit
]),
2995 emit
->ps_true_texcoord
[unit
],
2996 swizzle(pos_neg_one
, 0, 3, 0, 0), /* (1, -1, 1, 1) */
2997 swizzle(zero
, 0, 3, 0, 0))) /* (0, 1, 0, 0) */
3000 /* Reassign the input_map entry to the new texcoord register */
3001 emit
->input_map
[emit
->ps_inverted_texcoord_input
[unit
]] =
3002 emit
->ps_inverted_texcoord
[unit
];
3004 inverted_texcoords
&= ~(1 << unit
);
3011 static INLINE boolean
3012 needs_to_create_zero( struct svga_shader_emitter
*emit
)
3016 if (emit
->unit
== PIPE_SHADER_FRAGMENT
) {
3017 if (!emit
->use_sm30
)
3020 if (emit
->key
.fkey
.light_twoside
)
3023 if (emit
->key
.fkey
.white_fragments
)
3026 if (emit
->emit_frontface
)
3029 if (emit
->info
.opcode_count
[TGSI_OPCODE_DST
] >= 1 ||
3030 emit
->info
.opcode_count
[TGSI_OPCODE_SSG
] >= 1 ||
3031 emit
->info
.opcode_count
[TGSI_OPCODE_LIT
] >= 1)
3034 if (emit
->inverted_texcoords
)
3037 /* look for any PIPE_SWIZZLE_ZERO/ONE terms */
3038 for (i
= 0; i
< emit
->key
.fkey
.num_textures
; i
++) {
3039 if (emit
->key
.fkey
.tex
[i
].swizzle_r
> PIPE_SWIZZLE_ALPHA
||
3040 emit
->key
.fkey
.tex
[i
].swizzle_g
> PIPE_SWIZZLE_ALPHA
||
3041 emit
->key
.fkey
.tex
[i
].swizzle_b
> PIPE_SWIZZLE_ALPHA
||
3042 emit
->key
.fkey
.tex
[i
].swizzle_a
> PIPE_SWIZZLE_ALPHA
)
3047 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
3048 if (emit
->info
.opcode_count
[TGSI_OPCODE_CMP
] >= 1)
3052 if (emit
->info
.opcode_count
[TGSI_OPCODE_IF
] >= 1 ||
3053 emit
->info
.opcode_count
[TGSI_OPCODE_BGNLOOP
] >= 1 ||
3054 emit
->info
.opcode_count
[TGSI_OPCODE_DDX
] >= 1 ||
3055 emit
->info
.opcode_count
[TGSI_OPCODE_DDY
] >= 1 ||
3056 emit
->info
.opcode_count
[TGSI_OPCODE_SGE
] >= 1 ||
3057 emit
->info
.opcode_count
[TGSI_OPCODE_SGT
] >= 1 ||
3058 emit
->info
.opcode_count
[TGSI_OPCODE_SLE
] >= 1 ||
3059 emit
->info
.opcode_count
[TGSI_OPCODE_SLT
] >= 1 ||
3060 emit
->info
.opcode_count
[TGSI_OPCODE_SNE
] >= 1 ||
3061 emit
->info
.opcode_count
[TGSI_OPCODE_SEQ
] >= 1 ||
3062 emit
->info
.opcode_count
[TGSI_OPCODE_EXP
] >= 1 ||
3063 emit
->info
.opcode_count
[TGSI_OPCODE_LOG
] >= 1 ||
3064 emit
->info
.opcode_count
[TGSI_OPCODE_XPD
] >= 1 ||
3065 emit
->info
.opcode_count
[TGSI_OPCODE_KILP
] >= 1)
3068 for (i
= 0; i
< emit
->key
.fkey
.num_textures
; i
++) {
3069 if (emit
->key
.fkey
.tex
[i
].compare_mode
== PIPE_TEX_COMPARE_R_TO_TEXTURE
)
3076 static INLINE boolean
3077 needs_to_create_loop_const( struct svga_shader_emitter
*emit
)
3079 return (emit
->info
.opcode_count
[TGSI_OPCODE_BGNLOOP
] >= 1);
3082 static INLINE boolean
3083 needs_to_create_sincos_consts( struct svga_shader_emitter
*emit
)
3085 return !emit
->use_sm30
&& (emit
->info
.opcode_count
[TGSI_OPCODE_SIN
] >= 1 ||
3086 emit
->info
.opcode_count
[TGSI_OPCODE_COS
] >= 1 ||
3087 emit
->info
.opcode_count
[TGSI_OPCODE_SCS
] >= 1);
3090 static INLINE boolean
3091 needs_to_create_arl_consts( struct svga_shader_emitter
*emit
)
3093 return (emit
->num_arl_consts
> 0);
3096 static INLINE boolean
3097 pre_parse_add_indirect( struct svga_shader_emitter
*emit
,
3098 int num
, int current_arl
)
3103 for (i
= 0; i
< emit
->num_arl_consts
; ++i
) {
3104 if (emit
->arl_consts
[i
].arl_num
== current_arl
)
3108 if (emit
->num_arl_consts
== i
) {
3109 ++emit
->num_arl_consts
;
3111 emit
->arl_consts
[i
].number
= (emit
->arl_consts
[i
].number
> num
) ?
3113 emit
->arl_consts
[i
].number
;
3114 emit
->arl_consts
[i
].arl_num
= current_arl
;
3119 pre_parse_instruction( struct svga_shader_emitter
*emit
,
3120 const struct tgsi_full_instruction
*insn
,
3123 if (insn
->Src
[0].Register
.Indirect
&&
3124 insn
->Src
[0].Indirect
.File
== TGSI_FILE_ADDRESS
) {
3125 const struct tgsi_full_src_register
*reg
= &insn
->Src
[0];
3126 if (reg
->Register
.Index
< 0) {
3127 pre_parse_add_indirect(emit
, reg
->Register
.Index
, current_arl
);
3131 if (insn
->Src
[1].Register
.Indirect
&&
3132 insn
->Src
[1].Indirect
.File
== TGSI_FILE_ADDRESS
) {
3133 const struct tgsi_full_src_register
*reg
= &insn
->Src
[1];
3134 if (reg
->Register
.Index
< 0) {
3135 pre_parse_add_indirect(emit
, reg
->Register
.Index
, current_arl
);
3139 if (insn
->Src
[2].Register
.Indirect
&&
3140 insn
->Src
[2].Indirect
.File
== TGSI_FILE_ADDRESS
) {
3141 const struct tgsi_full_src_register
*reg
= &insn
->Src
[2];
3142 if (reg
->Register
.Index
< 0) {
3143 pre_parse_add_indirect(emit
, reg
->Register
.Index
, current_arl
);
3151 pre_parse_tokens( struct svga_shader_emitter
*emit
,
3152 const struct tgsi_token
*tokens
)
3154 struct tgsi_parse_context parse
;
3155 int current_arl
= 0;
3157 tgsi_parse_init( &parse
, tokens
);
3159 while (!tgsi_parse_end_of_tokens( &parse
)) {
3160 tgsi_parse_token( &parse
);
3161 switch (parse
.FullToken
.Token
.Type
) {
3162 case TGSI_TOKEN_TYPE_IMMEDIATE
:
3163 case TGSI_TOKEN_TYPE_DECLARATION
:
3165 case TGSI_TOKEN_TYPE_INSTRUCTION
:
3166 if (parse
.FullToken
.FullInstruction
.Instruction
.Opcode
==
3170 if (!pre_parse_instruction( emit
, &parse
.FullToken
.FullInstruction
,
3182 static boolean
svga_shader_emit_helpers( struct svga_shader_emitter
*emit
)
3185 if (needs_to_create_zero( emit
)) {
3186 create_zero_immediate( emit
);
3188 if (needs_to_create_loop_const( emit
)) {
3189 create_loop_const( emit
);
3191 if (needs_to_create_sincos_consts( emit
)) {
3192 create_sincos_consts( emit
);
3194 if (needs_to_create_arl_consts( emit
)) {
3195 create_arl_consts( emit
);
3198 if (emit
->unit
== PIPE_SHADER_FRAGMENT
) {
3199 if (!emit_ps_preamble( emit
))
3202 if (emit
->key
.fkey
.light_twoside
) {
3203 if (!emit_light_twoside( emit
))
3206 if (emit
->emit_frontface
) {
3207 if (!emit_frontface( emit
))
3210 if (emit
->inverted_texcoords
) {
3211 if (!emit_inverted_texcoords( emit
))
3219 boolean
svga_shader_emit_instructions( struct svga_shader_emitter
*emit
,
3220 const struct tgsi_token
*tokens
)
3222 struct tgsi_parse_context parse
;
3224 boolean helpers_emitted
= FALSE
;
3225 unsigned line_nr
= 0;
3227 tgsi_parse_init( &parse
, tokens
);
3228 emit
->internal_imm_count
= 0;
3230 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
3231 ret
= emit_vs_preamble( emit
);
3236 pre_parse_tokens(emit
, tokens
);
3238 while (!tgsi_parse_end_of_tokens( &parse
)) {
3239 tgsi_parse_token( &parse
);
3241 switch (parse
.FullToken
.Token
.Type
) {
3242 case TGSI_TOKEN_TYPE_IMMEDIATE
:
3243 ret
= svga_emit_immediate( emit
, &parse
.FullToken
.FullImmediate
);
3248 case TGSI_TOKEN_TYPE_DECLARATION
:
3250 ret
= svga_translate_decl_sm30( emit
, &parse
.FullToken
.FullDeclaration
);
3252 ret
= svga_translate_decl_sm20( emit
, &parse
.FullToken
.FullDeclaration
);
3257 case TGSI_TOKEN_TYPE_INSTRUCTION
:
3258 if (!helpers_emitted
) {
3259 if (!svga_shader_emit_helpers( emit
))
3261 helpers_emitted
= TRUE
;
3263 ret
= svga_emit_instruction( emit
,
3265 &parse
.FullToken
.FullInstruction
);
3273 reset_temp_regs( emit
);
3276 /* Need to terminate the current subroutine. Note that the
3277 * hardware doesn't tolerate shaders without sub-routines
3278 * terminating with RET+END.
3280 if (!emit
->in_main_func
) {
3281 ret
= emit_instruction( emit
, inst_token( SVGA3DOP_RET
) );
3286 assert(emit
->dynamic_branching_level
== 0);
3288 /* Need to terminate the whole shader:
3290 ret
= emit_instruction( emit
, inst_token( SVGA3DOP_END
) );
3295 tgsi_parse_free( &parse
);