1 /**********************************************************
2 * Copyright 2008-2009 VMware, Inc. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 **********************************************************/
27 #include "pipe/p_shader_tokens.h"
28 #include "tgsi/tgsi_parse.h"
29 #include "util/u_memory.h"
31 #include "svga_tgsi_emit.h"
32 #include "svga_context.h"
35 static boolean
emit_vs_postamble( struct svga_shader_emitter
*emit
);
36 static boolean
emit_ps_postamble( struct svga_shader_emitter
*emit
);
46 case TGSI_OPCODE_ABS
: return SVGA3DOP_ABS
;
47 case TGSI_OPCODE_ADD
: return SVGA3DOP_ADD
;
48 case TGSI_OPCODE_BREAKC
: return SVGA3DOP_BREAKC
;
49 case TGSI_OPCODE_DP2A
: return SVGA3DOP_DP2ADD
;
50 case TGSI_OPCODE_DP3
: return SVGA3DOP_DP3
;
51 case TGSI_OPCODE_DP4
: return SVGA3DOP_DP4
;
52 case TGSI_OPCODE_FRC
: return SVGA3DOP_FRC
;
53 case TGSI_OPCODE_MAD
: return SVGA3DOP_MAD
;
54 case TGSI_OPCODE_MAX
: return SVGA3DOP_MAX
;
55 case TGSI_OPCODE_MIN
: return SVGA3DOP_MIN
;
56 case TGSI_OPCODE_MOV
: return SVGA3DOP_MOV
;
57 case TGSI_OPCODE_MUL
: return SVGA3DOP_MUL
;
58 case TGSI_OPCODE_NOP
: return SVGA3DOP_NOP
;
59 case TGSI_OPCODE_NRM4
: return SVGA3DOP_NRM
;
61 debug_printf("Unkown opcode %u\n", opcode
);
63 return SVGA3DOP_LAST_INST
;
68 static unsigned translate_file( unsigned file
)
71 case TGSI_FILE_TEMPORARY
: return SVGA3DREG_TEMP
;
72 case TGSI_FILE_INPUT
: return SVGA3DREG_INPUT
;
73 case TGSI_FILE_OUTPUT
: return SVGA3DREG_OUTPUT
; /* VS3.0+ only */
74 case TGSI_FILE_IMMEDIATE
: return SVGA3DREG_CONST
;
75 case TGSI_FILE_CONSTANT
: return SVGA3DREG_CONST
;
76 case TGSI_FILE_SAMPLER
: return SVGA3DREG_SAMPLER
;
77 case TGSI_FILE_ADDRESS
: return SVGA3DREG_ADDR
;
80 return SVGA3DREG_TEMP
;
89 static SVGA3dShaderDestToken
90 translate_dst_register( struct svga_shader_emitter
*emit
,
91 const struct tgsi_full_instruction
*insn
,
94 const struct tgsi_full_dst_register
*reg
= &insn
->Dst
[idx
];
95 SVGA3dShaderDestToken dest
;
97 switch (reg
->Register
.File
) {
98 case TGSI_FILE_OUTPUT
:
99 /* Output registers encode semantic information in their name.
100 * Need to lookup a table built at decl time:
102 dest
= emit
->output_map
[reg
->Register
.Index
];
106 dest
= dst_register( translate_file( reg
->Register
.File
),
107 reg
->Register
.Index
);
111 dest
.mask
= reg
->Register
.WriteMask
;
114 if (insn
->Instruction
.Saturate
)
115 dest
.dstMod
= SVGA3DDSTMOD_SATURATE
;
121 static struct src_register
122 swizzle( struct src_register src
,
128 x
= (src
.base
.swizzle
>> (x
* 2)) & 0x3;
129 y
= (src
.base
.swizzle
>> (y
* 2)) & 0x3;
130 z
= (src
.base
.swizzle
>> (z
* 2)) & 0x3;
131 w
= (src
.base
.swizzle
>> (w
* 2)) & 0x3;
133 src
.base
.swizzle
= TRANSLATE_SWIZZLE(x
,y
,z
,w
);
138 static struct src_register
139 scalar( struct src_register src
,
142 return swizzle( src
, comp
, comp
, comp
, comp
);
145 static INLINE boolean
146 svga_arl_needs_adjustment( const struct svga_shader_emitter
*emit
)
150 for (i
= 0; i
< emit
->num_arl_consts
; ++i
) {
151 if (emit
->arl_consts
[i
].arl_num
== emit
->current_arl
)
158 svga_arl_adjustment( const struct svga_shader_emitter
*emit
)
162 for (i
= 0; i
< emit
->num_arl_consts
; ++i
) {
163 if (emit
->arl_consts
[i
].arl_num
== emit
->current_arl
)
164 return emit
->arl_consts
[i
].number
;
169 static struct src_register
170 translate_src_register( const struct svga_shader_emitter
*emit
,
171 const struct tgsi_full_src_register
*reg
)
173 struct src_register src
;
175 switch (reg
->Register
.File
) {
176 case TGSI_FILE_INPUT
:
177 /* Input registers are referred to by their semantic name rather
178 * than by index. Use the mapping build up from the decls:
180 src
= emit
->input_map
[reg
->Register
.Index
];
183 case TGSI_FILE_IMMEDIATE
:
184 /* Immediates are appended after TGSI constants in the D3D
187 src
= src_register( translate_file( reg
->Register
.File
),
188 reg
->Register
.Index
+
193 src
= src_register( translate_file( reg
->Register
.File
),
194 reg
->Register
.Index
);
199 /* Indirect addressing.
201 if (reg
->Register
.Indirect
) {
202 if (emit
->unit
== PIPE_SHADER_FRAGMENT
) {
203 /* Pixel shaders have only loop registers for relative
204 * addressing into inputs. Ignore the redundant address
205 * register, the contents of aL should be in sync with it.
207 if (reg
->Register
.File
== TGSI_FILE_INPUT
) {
208 src
.base
.relAddr
= 1;
209 src
.indirect
= src_token(SVGA3DREG_LOOP
, 0);
213 /* Constant buffers only.
215 if (reg
->Register
.File
== TGSI_FILE_CONSTANT
) {
216 /* we shift the offset towards the minimum */
217 if (svga_arl_needs_adjustment( emit
)) {
218 src
.base
.num
-= svga_arl_adjustment( emit
);
220 src
.base
.relAddr
= 1;
222 /* Not really sure what should go in the second token:
224 src
.indirect
= src_token( SVGA3DREG_ADDR
,
225 reg
->Indirect
.Index
);
227 src
.indirect
.swizzle
= SWIZZLE_XXXX
;
233 reg
->Register
.SwizzleX
,
234 reg
->Register
.SwizzleY
,
235 reg
->Register
.SwizzleZ
,
236 reg
->Register
.SwizzleW
);
238 /* src.mod isn't a bitfield, unfortunately:
239 * See tgsi_util_get_full_src_register_sign_mode for implementation details.
241 if (reg
->Register
.Absolute
) {
242 if (reg
->Register
.Negate
)
243 src
.base
.srcMod
= SVGA3DSRCMOD_ABSNEG
;
245 src
.base
.srcMod
= SVGA3DSRCMOD_ABS
;
248 if (reg
->Register
.Negate
)
249 src
.base
.srcMod
= SVGA3DSRCMOD_NEG
;
251 src
.base
.srcMod
= SVGA3DSRCMOD_NONE
;
259 * Get a temporary register, return -1 if none available
261 static INLINE SVGA3dShaderDestToken
262 get_temp( struct svga_shader_emitter
*emit
)
264 int i
= emit
->nr_hw_temp
+ emit
->internal_temp_count
++;
266 return dst_register( SVGA3DREG_TEMP
, i
);
269 /* Release a single temp. Currently only effective if it was the last
270 * allocated temp, otherwise release will be delayed until the next
271 * call to reset_temp_regs().
274 release_temp( struct svga_shader_emitter
*emit
,
275 SVGA3dShaderDestToken temp
)
277 if (temp
.num
== emit
->internal_temp_count
- 1)
278 emit
->internal_temp_count
--;
281 static void reset_temp_regs( struct svga_shader_emitter
*emit
)
283 emit
->internal_temp_count
= 0;
287 /* Replace the src with the temporary specified in the dst, but copying
288 * only the necessary channels, and preserving the original swizzle (which is
289 * important given that several opcodes have constraints in the allowed
292 static boolean
emit_repl( struct svga_shader_emitter
*emit
,
293 SVGA3dShaderDestToken dst
,
294 struct src_register
*src0
)
296 unsigned src0_swizzle
;
299 assert(SVGA3dShaderGetRegType(dst
.value
) == SVGA3DREG_TEMP
);
301 src0_swizzle
= src0
->base
.swizzle
;
304 for (chan
= 0; chan
< 4; ++chan
) {
305 unsigned swizzle
= (src0_swizzle
>> (chan
*2)) & 0x3;
306 dst
.mask
|= 1 << swizzle
;
310 src0
->base
.swizzle
= SVGA3DSWIZZLE_NONE
;
312 if (!emit_op1( emit
, inst_token( SVGA3DOP_MOV
), dst
, *src0
))
316 src0
->base
.swizzle
= src0_swizzle
;
322 static boolean
submit_op0( struct svga_shader_emitter
*emit
,
323 SVGA3dShaderInstToken inst
,
324 SVGA3dShaderDestToken dest
)
326 return (emit_instruction( emit
, inst
) &&
327 emit_dst( emit
, dest
));
330 static boolean
submit_op1( struct svga_shader_emitter
*emit
,
331 SVGA3dShaderInstToken inst
,
332 SVGA3dShaderDestToken dest
,
333 struct src_register src0
)
335 return emit_op1( emit
, inst
, dest
, src0
);
339 /* SVGA shaders may not refer to >1 constant register in a single
340 * instruction. This function checks for that usage and inserts a
341 * move to temporary if detected.
343 * The same applies to input registers -- at most a single input
344 * register may be read by any instruction.
346 static boolean
submit_op2( struct svga_shader_emitter
*emit
,
347 SVGA3dShaderInstToken inst
,
348 SVGA3dShaderDestToken dest
,
349 struct src_register src0
,
350 struct src_register src1
)
352 SVGA3dShaderDestToken temp
;
353 SVGA3dShaderRegType type0
, type1
;
354 boolean need_temp
= FALSE
;
357 type0
= SVGA3dShaderGetRegType( src0
.base
.value
);
358 type1
= SVGA3dShaderGetRegType( src1
.base
.value
);
360 if (type0
== SVGA3DREG_CONST
&&
361 type1
== SVGA3DREG_CONST
&&
362 src0
.base
.num
!= src1
.base
.num
)
365 if (type0
== SVGA3DREG_INPUT
&&
366 type1
== SVGA3DREG_INPUT
&&
367 src0
.base
.num
!= src1
.base
.num
)
371 temp
= get_temp( emit
);
373 if (!emit_repl( emit
, temp
, &src0
))
377 if (!emit_op2( emit
, inst
, dest
, src0
, src1
))
381 release_temp( emit
, temp
);
387 /* SVGA shaders may not refer to >1 constant register in a single
388 * instruction. This function checks for that usage and inserts a
389 * move to temporary if detected.
391 static boolean
submit_op3( struct svga_shader_emitter
*emit
,
392 SVGA3dShaderInstToken inst
,
393 SVGA3dShaderDestToken dest
,
394 struct src_register src0
,
395 struct src_register src1
,
396 struct src_register src2
)
398 SVGA3dShaderDestToken temp0
;
399 SVGA3dShaderDestToken temp1
;
400 boolean need_temp0
= FALSE
;
401 boolean need_temp1
= FALSE
;
402 SVGA3dShaderRegType type0
, type1
, type2
;
406 type0
= SVGA3dShaderGetRegType( src0
.base
.value
);
407 type1
= SVGA3dShaderGetRegType( src1
.base
.value
);
408 type2
= SVGA3dShaderGetRegType( src2
.base
.value
);
410 if (inst
.op
!= SVGA3DOP_SINCOS
) {
411 if (type0
== SVGA3DREG_CONST
&&
412 ((type1
== SVGA3DREG_CONST
&& src0
.base
.num
!= src1
.base
.num
) ||
413 (type2
== SVGA3DREG_CONST
&& src0
.base
.num
!= src2
.base
.num
)))
416 if (type1
== SVGA3DREG_CONST
&&
417 (type2
== SVGA3DREG_CONST
&& src1
.base
.num
!= src2
.base
.num
))
421 if (type0
== SVGA3DREG_INPUT
&&
422 ((type1
== SVGA3DREG_INPUT
&& src0
.base
.num
!= src1
.base
.num
) ||
423 (type2
== SVGA3DREG_INPUT
&& src0
.base
.num
!= src2
.base
.num
)))
426 if (type1
== SVGA3DREG_INPUT
&&
427 (type2
== SVGA3DREG_INPUT
&& src1
.base
.num
!= src2
.base
.num
))
431 temp0
= get_temp( emit
);
433 if (!emit_repl( emit
, temp0
, &src0
))
438 temp1
= get_temp( emit
);
440 if (!emit_repl( emit
, temp1
, &src1
))
444 if (!emit_op3( emit
, inst
, dest
, src0
, src1
, src2
))
448 release_temp( emit
, temp1
);
450 release_temp( emit
, temp0
);
457 /* SVGA shaders may not refer to >1 constant register in a single
458 * instruction. This function checks for that usage and inserts a
459 * move to temporary if detected.
461 static boolean
submit_op4( struct svga_shader_emitter
*emit
,
462 SVGA3dShaderInstToken inst
,
463 SVGA3dShaderDestToken dest
,
464 struct src_register src0
,
465 struct src_register src1
,
466 struct src_register src2
,
467 struct src_register src3
)
469 SVGA3dShaderDestToken temp0
;
470 SVGA3dShaderDestToken temp3
;
471 boolean need_temp0
= FALSE
;
472 boolean need_temp3
= FALSE
;
473 SVGA3dShaderRegType type0
, type1
, type2
, type3
;
477 type0
= SVGA3dShaderGetRegType( src0
.base
.value
);
478 type1
= SVGA3dShaderGetRegType( src1
.base
.value
);
479 type2
= SVGA3dShaderGetRegType( src2
.base
.value
);
480 type3
= SVGA3dShaderGetRegType( src2
.base
.value
);
482 /* Make life a little easier - this is only used by the TXD
483 * instruction which is guaranteed not to have a constant/input reg
484 * in one slot at least:
486 assert(type1
== SVGA3DREG_SAMPLER
);
488 if (type0
== SVGA3DREG_CONST
&&
489 ((type3
== SVGA3DREG_CONST
&& src0
.base
.num
!= src3
.base
.num
) ||
490 (type2
== SVGA3DREG_CONST
&& src0
.base
.num
!= src2
.base
.num
)))
493 if (type3
== SVGA3DREG_CONST
&&
494 (type2
== SVGA3DREG_CONST
&& src3
.base
.num
!= src2
.base
.num
))
497 if (type0
== SVGA3DREG_INPUT
&&
498 ((type3
== SVGA3DREG_INPUT
&& src0
.base
.num
!= src3
.base
.num
) ||
499 (type2
== SVGA3DREG_INPUT
&& src0
.base
.num
!= src2
.base
.num
)))
502 if (type3
== SVGA3DREG_INPUT
&&
503 (type2
== SVGA3DREG_INPUT
&& src3
.base
.num
!= src2
.base
.num
))
507 temp0
= get_temp( emit
);
509 if (!emit_repl( emit
, temp0
, &src0
))
514 temp3
= get_temp( emit
);
516 if (!emit_repl( emit
, temp3
, &src3
))
520 if (!emit_op4( emit
, inst
, dest
, src0
, src1
, src2
, src3
))
524 release_temp( emit
, temp3
);
526 release_temp( emit
, temp0
);
531 static boolean
alias_src_dst( struct src_register src
,
532 SVGA3dShaderDestToken dst
)
534 if (src
.base
.num
!= dst
.num
)
537 if (SVGA3dShaderGetRegType(dst
.value
) !=
538 SVGA3dShaderGetRegType(src
.base
.value
))
545 static boolean
submit_lrp(struct svga_shader_emitter
*emit
,
546 SVGA3dShaderDestToken dst
,
547 struct src_register src0
,
548 struct src_register src1
,
549 struct src_register src2
)
551 SVGA3dShaderDestToken tmp
;
552 boolean need_dst_tmp
= FALSE
;
554 /* The dst reg must be a temporary, and not be the same as src0 or src2 */
555 if (SVGA3dShaderGetRegType(dst
.value
) != SVGA3DREG_TEMP
||
556 alias_src_dst(src0
, dst
) ||
557 alias_src_dst(src2
, dst
))
561 tmp
= get_temp( emit
);
568 if (!submit_op3(emit
, inst_token( SVGA3DOP_LRP
), tmp
, src0
, src1
, src2
))
572 if (!submit_op1(emit
, inst_token( SVGA3DOP_MOV
), dst
, src( tmp
)))
580 static boolean
emit_def_const( struct svga_shader_emitter
*emit
,
581 SVGA3dShaderConstType type
,
589 SVGA3dShaderInstToken opcode
;
592 case SVGA3D_CONST_TYPE_FLOAT
:
593 opcode
= inst_token( SVGA3DOP_DEF
);
594 def
.dst
= dst_register( SVGA3DREG_CONST
, idx
);
595 def
.constValues
[0] = a
;
596 def
.constValues
[1] = b
;
597 def
.constValues
[2] = c
;
598 def
.constValues
[3] = d
;
600 case SVGA3D_CONST_TYPE_INT
:
601 opcode
= inst_token( SVGA3DOP_DEFI
);
602 def
.dst
= dst_register( SVGA3DREG_CONSTINT
, idx
);
603 def
.constIValues
[0] = (int)a
;
604 def
.constIValues
[1] = (int)b
;
605 def
.constIValues
[2] = (int)c
;
606 def
.constIValues
[3] = (int)d
;
610 opcode
= inst_token( SVGA3DOP_NOP
);
614 if (!emit_instruction(emit
, opcode
) ||
615 !svga_shader_emit_dwords( emit
, def
.values
, Elements(def
.values
)))
621 static INLINE boolean
622 create_zero_immediate( struct svga_shader_emitter
*emit
)
624 unsigned idx
= emit
->nr_hw_float_const
++;
626 if (!emit_def_const( emit
, SVGA3D_CONST_TYPE_FLOAT
,
630 emit
->zero_immediate_idx
= idx
;
631 emit
->created_zero_immediate
= TRUE
;
636 static INLINE boolean
637 create_loop_const( struct svga_shader_emitter
*emit
)
639 unsigned idx
= emit
->nr_hw_int_const
++;
641 if (!emit_def_const( emit
, SVGA3D_CONST_TYPE_INT
, idx
,
642 255, /* iteration count */
643 0, /* initial value */
645 0 /* not used, must be 0 */))
648 emit
->loop_const_idx
= idx
;
649 emit
->created_loop_const
= TRUE
;
654 static INLINE boolean
655 create_sincos_consts( struct svga_shader_emitter
*emit
)
657 unsigned idx
= emit
->nr_hw_float_const
++;
659 if (!emit_def_const( emit
, SVGA3D_CONST_TYPE_FLOAT
, idx
,
666 emit
->sincos_consts_idx
= idx
;
667 idx
= emit
->nr_hw_float_const
++;
669 if (!emit_def_const( emit
, SVGA3D_CONST_TYPE_FLOAT
, idx
,
676 emit
->created_sincos_consts
= TRUE
;
681 static INLINE boolean
682 create_arl_consts( struct svga_shader_emitter
*emit
)
686 for (i
= 0; i
< emit
->num_arl_consts
; i
+= 4) {
688 unsigned idx
= emit
->nr_hw_float_const
++;
690 for (j
= 0; j
< 4 && (j
+ i
) < emit
->num_arl_consts
; ++j
) {
691 vals
[j
] = emit
->arl_consts
[i
+ j
].number
;
692 emit
->arl_consts
[i
+ j
].idx
= idx
;
695 emit
->arl_consts
[i
+ 0].swizzle
= TGSI_SWIZZLE_X
;
698 emit
->arl_consts
[i
+ 0].swizzle
= TGSI_SWIZZLE_Y
;
701 emit
->arl_consts
[i
+ 0].swizzle
= TGSI_SWIZZLE_Z
;
704 emit
->arl_consts
[i
+ 0].swizzle
= TGSI_SWIZZLE_W
;
711 if (!emit_def_const( emit
, SVGA3D_CONST_TYPE_FLOAT
, idx
,
720 static INLINE
struct src_register
721 get_vface( struct svga_shader_emitter
*emit
)
723 assert(emit
->emitted_vface
);
724 return src_register(SVGA3DREG_MISCTYPE
,
728 /* returns {0, 0, 0, 1} immediate */
729 static INLINE
struct src_register
730 get_zero_immediate( struct svga_shader_emitter
*emit
)
732 assert(emit
->created_zero_immediate
);
733 assert(emit
->zero_immediate_idx
>= 0);
734 return src_register( SVGA3DREG_CONST
,
735 emit
->zero_immediate_idx
);
738 /* returns the loop const */
739 static INLINE
struct src_register
740 get_loop_const( struct svga_shader_emitter
*emit
)
742 assert(emit
->created_loop_const
);
743 assert(emit
->loop_const_idx
>= 0);
744 return src_register( SVGA3DREG_CONSTINT
,
745 emit
->loop_const_idx
);
748 /* returns a sincos const */
749 static INLINE
struct src_register
750 get_sincos_const( struct svga_shader_emitter
*emit
,
753 assert(emit
->created_sincos_consts
);
754 assert(emit
->sincos_consts_idx
>= 0);
755 assert(index
== 0 || index
== 1);
756 return src_register( SVGA3DREG_CONST
,
757 emit
->sincos_consts_idx
+ index
);
760 static INLINE
struct src_register
761 get_fake_arl_const( struct svga_shader_emitter
*emit
)
763 struct src_register reg
;
764 int idx
= 0, swizzle
= 0, i
;
766 for (i
= 0; i
< emit
->num_arl_consts
; ++ i
) {
767 if (emit
->arl_consts
[i
].arl_num
== emit
->current_arl
) {
768 idx
= emit
->arl_consts
[i
].idx
;
769 swizzle
= emit
->arl_consts
[i
].swizzle
;
773 reg
= src_register( SVGA3DREG_CONST
, idx
);
774 return scalar(reg
, swizzle
);
777 static INLINE
struct src_register
778 get_tex_dimensions( struct svga_shader_emitter
*emit
, int sampler_num
)
781 struct src_register reg
;
783 /* the width/height indexes start right after constants */
784 idx
= emit
->key
.fkey
.tex
[sampler_num
].width_height_idx
+
785 emit
->info
.file_max
[TGSI_FILE_CONSTANT
] + 1;
787 reg
= src_register( SVGA3DREG_CONST
, idx
);
791 static boolean
emit_fake_arl(struct svga_shader_emitter
*emit
,
792 const struct tgsi_full_instruction
*insn
)
794 const struct src_register src0
= translate_src_register(
795 emit
, &insn
->Src
[0] );
796 struct src_register src1
= get_fake_arl_const( emit
);
797 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
798 SVGA3dShaderDestToken tmp
= get_temp( emit
);
800 if (!submit_op1(emit
, inst_token( SVGA3DOP_MOV
), tmp
, src0
))
803 if (!submit_op2( emit
, inst_token( SVGA3DOP_ADD
), tmp
, src( tmp
),
807 /* replicate the original swizzle */
809 src1
.base
.swizzle
= src0
.base
.swizzle
;
811 return submit_op1( emit
, inst_token( SVGA3DOP_MOVA
),
815 static boolean
emit_if(struct svga_shader_emitter
*emit
,
816 const struct tgsi_full_instruction
*insn
)
818 struct src_register src0
= translate_src_register(
819 emit
, &insn
->Src
[0] );
820 struct src_register zero
= get_zero_immediate( emit
);
821 SVGA3dShaderInstToken if_token
= inst_token( SVGA3DOP_IFC
);
823 if_token
.control
= SVGA3DOPCOMPC_NE
;
824 zero
= scalar(zero
, TGSI_SWIZZLE_X
);
826 if (SVGA3dShaderGetRegType(src0
.base
.value
) == SVGA3DREG_CONST
) {
828 * Max different constant registers readable per IFC instruction is 1.
831 SVGA3dShaderDestToken tmp
= get_temp( emit
);
833 if (!submit_op1(emit
, inst_token( SVGA3DOP_MOV
), tmp
, src0
))
836 src0
= scalar(src( tmp
), TGSI_SWIZZLE_X
);
839 emit
->dynamic_branching_level
++;
841 return (emit_instruction( emit
, if_token
) &&
842 emit_src( emit
, src0
) &&
843 emit_src( emit
, zero
) );
846 static boolean
emit_endif(struct svga_shader_emitter
*emit
,
847 const struct tgsi_full_instruction
*insn
)
849 emit
->dynamic_branching_level
--;
851 return (emit_instruction( emit
,
852 inst_token( SVGA3DOP_ENDIF
)));
855 static boolean
emit_else(struct svga_shader_emitter
*emit
,
856 const struct tgsi_full_instruction
*insn
)
858 return (emit_instruction( emit
,
859 inst_token( SVGA3DOP_ELSE
)));
862 /* Translate the following TGSI FLR instruction.
864 * To the following SVGA3D instruction sequence.
868 static boolean
emit_floor(struct svga_shader_emitter
*emit
,
869 const struct tgsi_full_instruction
*insn
)
871 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
872 const struct src_register src0
= translate_src_register(
873 emit
, &insn
->Src
[0] );
874 SVGA3dShaderDestToken temp
= get_temp( emit
);
877 if (!submit_op1( emit
, inst_token( SVGA3DOP_FRC
), temp
, src0
))
880 /* SUB DST, SRC, TMP */
881 if (!submit_op2( emit
, inst_token( SVGA3DOP_ADD
), dst
, src0
,
882 negate( src( temp
) ) ))
889 /* Translate the following TGSI CMP instruction.
890 * CMP DST, SRC0, SRC1, SRC2
891 * To the following SVGA3D instruction sequence.
892 * CMP DST, SRC0, SRC2, SRC1
894 static boolean
emit_cmp(struct svga_shader_emitter
*emit
,
895 const struct tgsi_full_instruction
*insn
)
897 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
898 const struct src_register src0
= translate_src_register(
899 emit
, &insn
->Src
[0] );
900 const struct src_register src1
= translate_src_register(
901 emit
, &insn
->Src
[1] );
902 const struct src_register src2
= translate_src_register(
903 emit
, &insn
->Src
[2] );
905 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
906 SVGA3dShaderDestToken temp
= get_temp(emit
);
907 struct src_register zero
= scalar(get_zero_immediate(emit
), TGSI_SWIZZLE_X
);
909 /* Since vertex shaders don't support the CMP instruction,
910 * simulate it with SLT and LRP instructions.
912 * LRP DST, TMP, SRC1, SRC2
914 if (!submit_op2(emit
, inst_token(SVGA3DOP_SLT
), temp
, src0
, zero
))
916 return submit_lrp(emit
, dst
, src(temp
), src1
, src2
);
919 /* CMP DST, SRC0, SRC2, SRC1 */
920 return submit_op3( emit
, inst_token( SVGA3DOP_CMP
), dst
, src0
, src2
, src1
);
925 /* Translate the following TGSI DIV instruction.
926 * DIV DST.xy, SRC0, SRC1
927 * To the following SVGA3D instruction sequence.
928 * RCP TMP.x, SRC1.xxxx
929 * RCP TMP.y, SRC1.yyyy
930 * MUL DST.xy, SRC0, TMP
932 static boolean
emit_div(struct svga_shader_emitter
*emit
,
933 const struct tgsi_full_instruction
*insn
)
935 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
936 const struct src_register src0
= translate_src_register(
937 emit
, &insn
->Src
[0] );
938 const struct src_register src1
= translate_src_register(
939 emit
, &insn
->Src
[1] );
940 SVGA3dShaderDestToken temp
= get_temp( emit
);
943 /* For each enabled element, perform a RCP instruction. Note that
944 * RCP is scalar in SVGA3D:
946 for (i
= 0; i
< 4; i
++) {
947 unsigned channel
= 1 << i
;
948 if (dst
.mask
& channel
) {
949 /* RCP TMP.?, SRC1.???? */
950 if (!submit_op1( emit
, inst_token( SVGA3DOP_RCP
),
951 writemask(temp
, channel
),
957 /* Then multiply them out with a single mul:
961 if (!submit_op2( emit
, inst_token( SVGA3DOP_MUL
), dst
, src0
,
968 /* Translate the following TGSI DP2 instruction.
969 * DP2 DST, SRC1, SRC2
970 * To the following SVGA3D instruction sequence.
971 * MUL TMP, SRC1, SRC2
972 * ADD DST, TMP.xxxx, TMP.yyyy
974 static boolean
emit_dp2(struct svga_shader_emitter
*emit
,
975 const struct tgsi_full_instruction
*insn
)
977 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
978 const struct src_register src0
= translate_src_register(
979 emit
, &insn
->Src
[0] );
980 const struct src_register src1
= translate_src_register(
981 emit
, &insn
->Src
[1] );
982 SVGA3dShaderDestToken temp
= get_temp( emit
);
983 struct src_register temp_src0
, temp_src1
;
985 /* MUL TMP, SRC1, SRC2 */
986 if (!submit_op2( emit
, inst_token( SVGA3DOP_MUL
), temp
, src0
, src1
))
989 temp_src0
= scalar(src( temp
), TGSI_SWIZZLE_X
);
990 temp_src1
= scalar(src( temp
), TGSI_SWIZZLE_Y
);
992 /* ADD DST, TMP.xxxx, TMP.yyyy */
993 if (!submit_op2( emit
, inst_token( SVGA3DOP_ADD
), dst
,
994 temp_src0
, temp_src1
))
1001 /* Translate the following TGSI DPH instruction.
1002 * DPH DST, SRC1, SRC2
1003 * To the following SVGA3D instruction sequence.
1004 * DP3 TMP, SRC1, SRC2
1005 * ADD DST, TMP, SRC2.wwww
1007 static boolean
emit_dph(struct svga_shader_emitter
*emit
,
1008 const struct tgsi_full_instruction
*insn
)
1010 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1011 const struct src_register src0
= translate_src_register(
1012 emit
, &insn
->Src
[0] );
1013 struct src_register src1
= translate_src_register(
1014 emit
, &insn
->Src
[1] );
1015 SVGA3dShaderDestToken temp
= get_temp( emit
);
1017 /* DP3 TMP, SRC1, SRC2 */
1018 if (!submit_op2( emit
, inst_token( SVGA3DOP_DP3
), temp
, src0
, src1
))
1021 src1
= scalar(src1
, TGSI_SWIZZLE_W
);
1023 /* ADD DST, TMP, SRC2.wwww */
1024 if (!submit_op2( emit
, inst_token( SVGA3DOP_ADD
), dst
,
1025 src( temp
), src1
))
1031 /* Translate the following TGSI DST instruction.
1033 * To the following SVGA3D instruction sequence.
1038 static boolean
emit_nrm(struct svga_shader_emitter
*emit
,
1039 const struct tgsi_full_instruction
*insn
)
1041 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1042 const struct src_register src0
= translate_src_register(
1043 emit
, &insn
->Src
[0] );
1044 SVGA3dShaderDestToken temp
= get_temp( emit
);
1046 /* DP3 TMP, SRC, SRC */
1047 if (!submit_op2( emit
, inst_token( SVGA3DOP_DP3
), temp
, src0
, src0
))
1051 if (!submit_op1( emit
, inst_token( SVGA3DOP_RSQ
), temp
, src( temp
)))
1054 /* MUL DST, SRC, TMP */
1055 if (!submit_op2( emit
, inst_token( SVGA3DOP_MUL
), dst
,
1063 static boolean
do_emit_sincos(struct svga_shader_emitter
*emit
,
1064 SVGA3dShaderDestToken dst
,
1065 struct src_register src0
)
1067 src0
= scalar(src0
, TGSI_SWIZZLE_X
);
1069 if (emit
->use_sm30
) {
1070 return submit_op1( emit
, inst_token( SVGA3DOP_SINCOS
),
1073 struct src_register const1
= get_sincos_const( emit
, 0 );
1074 struct src_register const2
= get_sincos_const( emit
, 1 );
1076 return submit_op3( emit
, inst_token( SVGA3DOP_SINCOS
),
1077 dst
, src0
, const1
, const2
);
1081 static boolean
emit_sincos(struct svga_shader_emitter
*emit
,
1082 const struct tgsi_full_instruction
*insn
)
1084 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1085 struct src_register src0
= translate_src_register(
1086 emit
, &insn
->Src
[0] );
1087 SVGA3dShaderDestToken temp
= get_temp( emit
);
1090 if (!do_emit_sincos(emit
, writemask(temp
, TGSI_WRITEMASK_XY
), src0
))
1094 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), dst
, src( temp
) ))
1104 static boolean
emit_sin(struct svga_shader_emitter
*emit
,
1105 const struct tgsi_full_instruction
*insn
)
1107 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1108 struct src_register src0
= translate_src_register(
1109 emit
, &insn
->Src
[0] );
1110 SVGA3dShaderDestToken temp
= get_temp( emit
);
1113 if (!do_emit_sincos(emit
, writemask(temp
, TGSI_WRITEMASK_Y
), src0
))
1116 src0
= scalar(src( temp
), TGSI_SWIZZLE_Y
);
1118 /* MOV DST TMP.yyyy */
1119 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), dst
, src0
))
1129 static boolean
emit_cos(struct svga_shader_emitter
*emit
,
1130 const struct tgsi_full_instruction
*insn
)
1132 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1133 struct src_register src0
= translate_src_register(
1134 emit
, &insn
->Src
[0] );
1135 SVGA3dShaderDestToken temp
= get_temp( emit
);
1138 if (!do_emit_sincos( emit
, writemask(temp
, TGSI_WRITEMASK_X
), src0
))
1141 src0
= scalar(src( temp
), TGSI_SWIZZLE_X
);
1143 /* MOV DST TMP.xxxx */
1144 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), dst
, src0
))
1150 static boolean
emit_ssg(struct svga_shader_emitter
*emit
,
1151 const struct tgsi_full_instruction
*insn
)
1153 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1154 struct src_register src0
= translate_src_register(
1155 emit
, &insn
->Src
[0] );
1156 SVGA3dShaderDestToken temp0
= get_temp( emit
);
1157 SVGA3dShaderDestToken temp1
= get_temp( emit
);
1158 struct src_register zero
, one
;
1160 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
1161 /* SGN DST, SRC0, TMP0, TMP1 */
1162 return submit_op3( emit
, inst_token( SVGA3DOP_SGN
), dst
, src0
,
1163 src( temp0
), src( temp1
) );
1166 zero
= get_zero_immediate( emit
);
1167 one
= scalar( zero
, TGSI_SWIZZLE_W
);
1168 zero
= scalar( zero
, TGSI_SWIZZLE_X
);
1170 /* CMP TMP0, SRC0, one, zero */
1171 if (!submit_op3( emit
, inst_token( SVGA3DOP_CMP
),
1172 writemask( temp0
, dst
.mask
), src0
, one
, zero
))
1175 /* CMP TMP1, negate(SRC0), negate(one), zero */
1176 if (!submit_op3( emit
, inst_token( SVGA3DOP_CMP
),
1177 writemask( temp1
, dst
.mask
), negate( src0
), negate( one
),
1181 /* ADD DST, TMP0, TMP1 */
1182 return submit_op2( emit
, inst_token( SVGA3DOP_ADD
), dst
, src( temp0
),
1187 * ADD DST SRC0, negate(SRC0)
1189 static boolean
emit_sub(struct svga_shader_emitter
*emit
,
1190 const struct tgsi_full_instruction
*insn
)
1192 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1193 struct src_register src0
= translate_src_register(
1194 emit
, &insn
->Src
[0] );
1195 struct src_register src1
= translate_src_register(
1196 emit
, &insn
->Src
[1] );
1198 src1
= negate(src1
);
1200 if (!submit_op2( emit
, inst_token( SVGA3DOP_ADD
), dst
,
1208 static boolean
emit_kil(struct svga_shader_emitter
*emit
,
1209 const struct tgsi_full_instruction
*insn
)
1211 SVGA3dShaderInstToken inst
;
1212 const struct tgsi_full_src_register
*reg
= &insn
->Src
[0];
1213 struct src_register src0
;
1215 inst
= inst_token( SVGA3DOP_TEXKILL
);
1216 src0
= translate_src_register( emit
, reg
);
1218 if (reg
->Register
.Absolute
||
1219 reg
->Register
.Negate
||
1220 reg
->Register
.Indirect
||
1221 reg
->Register
.SwizzleX
!= 0 ||
1222 reg
->Register
.SwizzleY
!= 1 ||
1223 reg
->Register
.SwizzleZ
!= 2 ||
1224 reg
->Register
.File
!= TGSI_FILE_TEMPORARY
)
1226 SVGA3dShaderDestToken temp
= get_temp( emit
);
1228 submit_op1( emit
, inst_token( SVGA3DOP_MOV
), temp
, src0
);
1232 return submit_op0( emit
, inst
, dst(src0
) );
1236 /* mesa state tracker always emits kilp as an unconditional
1238 static boolean
emit_kilp(struct svga_shader_emitter
*emit
,
1239 const struct tgsi_full_instruction
*insn
)
1241 SVGA3dShaderInstToken inst
;
1242 SVGA3dShaderDestToken temp
;
1243 struct src_register one
= scalar( get_zero_immediate( emit
),
1246 inst
= inst_token( SVGA3DOP_TEXKILL
);
1248 /* texkill doesn't allow negation on the operand so lets move
1249 * negation of {1} to a temp register */
1250 temp
= get_temp( emit
);
1251 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), temp
,
1255 return submit_op0( emit
, inst
, temp
);
1258 /* Implement conditionals by initializing destination reg to 'fail',
1259 * then set predicate reg with UFOP_SETP, then move 'pass' to dest
1260 * based on predicate reg.
1262 * SETP src0, cmp, src1 -- do this first to avoid aliasing problems.
1267 emit_conditional(struct svga_shader_emitter
*emit
,
1268 unsigned compare_func
,
1269 SVGA3dShaderDestToken dst
,
1270 struct src_register src0
,
1271 struct src_register src1
,
1272 struct src_register pass
,
1273 struct src_register fail
)
1275 SVGA3dShaderDestToken pred_reg
= dst_register( SVGA3DREG_PREDICATE
, 0 );
1276 SVGA3dShaderInstToken setp_token
, mov_token
;
1277 setp_token
= inst_token( SVGA3DOP_SETP
);
1279 switch (compare_func
) {
1280 case PIPE_FUNC_NEVER
:
1281 return submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
1284 case PIPE_FUNC_LESS
:
1285 setp_token
.control
= SVGA3DOPCOMP_LT
;
1287 case PIPE_FUNC_EQUAL
:
1288 setp_token
.control
= SVGA3DOPCOMP_EQ
;
1290 case PIPE_FUNC_LEQUAL
:
1291 setp_token
.control
= SVGA3DOPCOMP_LE
;
1293 case PIPE_FUNC_GREATER
:
1294 setp_token
.control
= SVGA3DOPCOMP_GT
;
1296 case PIPE_FUNC_NOTEQUAL
:
1297 setp_token
.control
= SVGA3DOPCOMPC_NE
;
1299 case PIPE_FUNC_GEQUAL
:
1300 setp_token
.control
= SVGA3DOPCOMP_GE
;
1302 case PIPE_FUNC_ALWAYS
:
1303 return submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
1308 /* SETP src0, COMPOP, src1 */
1309 if (!submit_op2( emit
, setp_token
, pred_reg
,
1313 mov_token
= inst_token( SVGA3DOP_MOV
);
1316 if (!submit_op1( emit
, mov_token
, dst
,
1320 /* MOV dst, pass (predicated)
1322 * Note that the predicate reg (and possible modifiers) is passed
1323 * as the first source argument.
1325 mov_token
.predicated
= 1;
1326 if (!submit_op2( emit
, mov_token
, dst
,
1327 src( pred_reg
), pass
))
1335 emit_select(struct svga_shader_emitter
*emit
,
1336 unsigned compare_func
,
1337 SVGA3dShaderDestToken dst
,
1338 struct src_register src0
,
1339 struct src_register src1
)
1341 /* There are some SVGA instructions which implement some selects
1342 * directly, but they are only available in the vertex shader.
1344 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
1345 switch (compare_func
) {
1346 case PIPE_FUNC_GEQUAL
:
1347 return submit_op2( emit
, inst_token( SVGA3DOP_SGE
), dst
, src0
, src1
);
1348 case PIPE_FUNC_LEQUAL
:
1349 return submit_op2( emit
, inst_token( SVGA3DOP_SGE
), dst
, src1
, src0
);
1350 case PIPE_FUNC_GREATER
:
1351 return submit_op2( emit
, inst_token( SVGA3DOP_SLT
), dst
, src1
, src0
);
1352 case PIPE_FUNC_LESS
:
1353 return submit_op2( emit
, inst_token( SVGA3DOP_SLT
), dst
, src0
, src1
);
1360 /* Otherwise, need to use the setp approach:
1363 struct src_register one
, zero
;
1364 /* zero immediate is 0,0,0,1 */
1365 zero
= get_zero_immediate( emit
);
1366 one
= scalar( zero
, TGSI_SWIZZLE_W
);
1367 zero
= scalar( zero
, TGSI_SWIZZLE_X
);
1369 return emit_conditional(
1380 static boolean
emit_select_op(struct svga_shader_emitter
*emit
,
1382 const struct tgsi_full_instruction
*insn
)
1384 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1385 struct src_register src0
= translate_src_register(
1386 emit
, &insn
->Src
[0] );
1387 struct src_register src1
= translate_src_register(
1388 emit
, &insn
->Src
[1] );
1390 return emit_select( emit
, compare
, dst
, src0
, src1
);
1394 /* Translate texture instructions to SVGA3D representation.
1396 static boolean
emit_tex2(struct svga_shader_emitter
*emit
,
1397 const struct tgsi_full_instruction
*insn
,
1398 SVGA3dShaderDestToken dst
)
1400 SVGA3dShaderInstToken inst
;
1401 struct src_register texcoord
;
1402 struct src_register sampler
;
1403 SVGA3dShaderDestToken tmp
;
1407 switch (insn
->Instruction
.Opcode
) {
1408 case TGSI_OPCODE_TEX
:
1409 inst
.op
= SVGA3DOP_TEX
;
1411 case TGSI_OPCODE_TXP
:
1412 inst
.op
= SVGA3DOP_TEX
;
1413 inst
.control
= SVGA3DOPCONT_PROJECT
;
1415 case TGSI_OPCODE_TXB
:
1416 inst
.op
= SVGA3DOP_TEX
;
1417 inst
.control
= SVGA3DOPCONT_BIAS
;
1419 case TGSI_OPCODE_TXL
:
1420 inst
.op
= SVGA3DOP_TEXLDL
;
1427 texcoord
= translate_src_register( emit
, &insn
->Src
[0] );
1428 sampler
= translate_src_register( emit
, &insn
->Src
[1] );
1430 if (emit
->key
.fkey
.tex
[sampler
.base
.num
].unnormalized
||
1431 emit
->dynamic_branching_level
> 0)
1432 tmp
= get_temp( emit
);
1434 /* Can't do mipmapping inside dynamic branch constructs. Force LOD
1435 * zero in that case.
1437 if (emit
->dynamic_branching_level
> 0 &&
1438 inst
.op
== SVGA3DOP_TEX
&&
1439 SVGA3dShaderGetRegType(texcoord
.base
.value
) == SVGA3DREG_TEMP
) {
1440 struct src_register zero
= get_zero_immediate( emit
);
1442 /* MOV tmp, texcoord */
1443 if (!submit_op1( emit
,
1444 inst_token( SVGA3DOP_MOV
),
1449 /* MOV tmp.w, zero */
1450 if (!submit_op1( emit
,
1451 inst_token( SVGA3DOP_MOV
),
1452 writemask( tmp
, TGSI_WRITEMASK_W
),
1453 scalar( zero
, TGSI_SWIZZLE_X
)))
1456 texcoord
= src( tmp
);
1457 inst
.op
= SVGA3DOP_TEXLDL
;
1460 /* Explicit normalization of texcoords:
1462 if (emit
->key
.fkey
.tex
[sampler
.base
.num
].unnormalized
) {
1463 struct src_register wh
= get_tex_dimensions( emit
, sampler
.base
.num
);
1465 /* MUL tmp, SRC0, WH */
1466 if (!submit_op2( emit
, inst_token( SVGA3DOP_MUL
),
1467 tmp
, texcoord
, wh
))
1470 texcoord
= src( tmp
);
1473 return submit_op2( emit
, inst
, dst
, texcoord
, sampler
);
1479 /* Translate texture instructions to SVGA3D representation.
1481 static boolean
emit_tex4(struct svga_shader_emitter
*emit
,
1482 const struct tgsi_full_instruction
*insn
,
1483 SVGA3dShaderDestToken dst
)
1485 SVGA3dShaderInstToken inst
;
1486 struct src_register texcoord
;
1487 struct src_register ddx
;
1488 struct src_register ddy
;
1489 struct src_register sampler
;
1491 texcoord
= translate_src_register( emit
, &insn
->Src
[0] );
1492 ddx
= translate_src_register( emit
, &insn
->Src
[1] );
1493 ddy
= translate_src_register( emit
, &insn
->Src
[2] );
1494 sampler
= translate_src_register( emit
, &insn
->Src
[3] );
1498 switch (insn
->Instruction
.Opcode
) {
1499 case TGSI_OPCODE_TXD
:
1500 inst
.op
= SVGA3DOP_TEXLDD
; /* 4 args! */
1507 return submit_op4( emit
, inst
, dst
, texcoord
, sampler
, ddx
, ddy
);
1511 static boolean
emit_tex(struct svga_shader_emitter
*emit
,
1512 const struct tgsi_full_instruction
*insn
)
1514 SVGA3dShaderDestToken dst
=
1515 translate_dst_register( emit
, insn
, 0 );
1516 struct src_register src0
=
1517 translate_src_register( emit
, &insn
->Src
[0] );
1518 struct src_register src1
=
1519 translate_src_register( emit
, &insn
->Src
[1] );
1521 SVGA3dShaderDestToken tex_result
;
1523 /* check for shadow samplers */
1524 boolean compare
= (emit
->key
.fkey
.tex
[src1
.base
.num
].compare_mode
==
1525 PIPE_TEX_COMPARE_R_TO_TEXTURE
);
1528 /* If doing compare processing, need to put this value into a
1529 * temporary so it can be used as a source later on.
1532 (!emit
->use_sm30
&& dst
.mask
!= TGSI_WRITEMASK_XYZW
) ) {
1533 tex_result
= get_temp( emit
);
1539 switch(insn
->Instruction
.Opcode
) {
1540 case TGSI_OPCODE_TEX
:
1541 case TGSI_OPCODE_TXB
:
1542 case TGSI_OPCODE_TXP
:
1543 case TGSI_OPCODE_TXL
:
1544 if (!emit_tex2( emit
, insn
, tex_result
))
1547 case TGSI_OPCODE_TXD
:
1548 if (!emit_tex4( emit
, insn
, tex_result
))
1557 if (dst
.mask
& TGSI_WRITEMASK_XYZ
) {
1558 SVGA3dShaderDestToken src0_zdivw
= get_temp( emit
);
1559 struct src_register tex_src_x
= scalar(src(tex_result
), TGSI_SWIZZLE_Y
);
1561 /* Divide texcoord R by Q */
1562 if (!submit_op1( emit
, inst_token( SVGA3DOP_RCP
),
1563 writemask(src0_zdivw
, TGSI_WRITEMASK_X
),
1564 scalar(src0
, TGSI_SWIZZLE_W
) ))
1567 if (!submit_op2( emit
, inst_token( SVGA3DOP_MUL
),
1568 writemask(src0_zdivw
, TGSI_WRITEMASK_X
),
1569 scalar(src0
, TGSI_SWIZZLE_Z
),
1570 scalar(src(src0_zdivw
), TGSI_SWIZZLE_X
) ))
1575 emit
->key
.fkey
.tex
[src1
.base
.num
].compare_func
,
1576 writemask( dst
, TGSI_WRITEMASK_XYZ
),
1577 scalar(src(src0_zdivw
), TGSI_SWIZZLE_X
),
1582 if (dst
.mask
& TGSI_WRITEMASK_W
) {
1583 struct src_register one
=
1584 scalar( get_zero_immediate( emit
), TGSI_SWIZZLE_W
);
1586 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
1587 writemask( dst
, TGSI_WRITEMASK_W
),
1594 else if (!emit
->use_sm30
&& dst
.mask
!= TGSI_WRITEMASK_XYZW
)
1596 if (!emit_op1( emit
, inst_token( SVGA3DOP_MOV
), dst
, src(tex_result
) ))
1603 static boolean
emit_bgnloop2( struct svga_shader_emitter
*emit
,
1604 const struct tgsi_full_instruction
*insn
)
1606 SVGA3dShaderInstToken inst
= inst_token( SVGA3DOP_LOOP
);
1607 struct src_register loop_reg
= src_register( SVGA3DREG_LOOP
, 0 );
1608 struct src_register const_int
= get_loop_const( emit
);
1610 emit
->dynamic_branching_level
++;
1612 return (emit_instruction( emit
, inst
) &&
1613 emit_src( emit
, loop_reg
) &&
1614 emit_src( emit
, const_int
) );
1617 static boolean
emit_endloop2( struct svga_shader_emitter
*emit
,
1618 const struct tgsi_full_instruction
*insn
)
1620 SVGA3dShaderInstToken inst
= inst_token( SVGA3DOP_ENDLOOP
);
1622 emit
->dynamic_branching_level
--;
1624 return emit_instruction( emit
, inst
);
1627 static boolean
emit_brk( struct svga_shader_emitter
*emit
,
1628 const struct tgsi_full_instruction
*insn
)
1630 SVGA3dShaderInstToken inst
= inst_token( SVGA3DOP_BREAK
);
1631 return emit_instruction( emit
, inst
);
1634 static boolean
emit_scalar_op1( struct svga_shader_emitter
*emit
,
1636 const struct tgsi_full_instruction
*insn
)
1638 SVGA3dShaderInstToken inst
;
1639 SVGA3dShaderDestToken dst
;
1640 struct src_register src
;
1642 inst
= inst_token( opcode
);
1643 dst
= translate_dst_register( emit
, insn
, 0 );
1644 src
= translate_src_register( emit
, &insn
->Src
[0] );
1645 src
= scalar( src
, TGSI_SWIZZLE_X
);
1647 return submit_op1( emit
, inst
, dst
, src
);
1651 static boolean
emit_simple_instruction(struct svga_shader_emitter
*emit
,
1653 const struct tgsi_full_instruction
*insn
)
1655 const struct tgsi_full_src_register
*src
= insn
->Src
;
1656 SVGA3dShaderInstToken inst
;
1657 SVGA3dShaderDestToken dst
;
1659 inst
= inst_token( opcode
);
1660 dst
= translate_dst_register( emit
, insn
, 0 );
1662 switch (insn
->Instruction
.NumSrcRegs
) {
1664 return submit_op0( emit
, inst
, dst
);
1666 return submit_op1( emit
, inst
, dst
,
1667 translate_src_register( emit
, &src
[0] ));
1669 return submit_op2( emit
, inst
, dst
,
1670 translate_src_register( emit
, &src
[0] ),
1671 translate_src_register( emit
, &src
[1] ) );
1673 return submit_op3( emit
, inst
, dst
,
1674 translate_src_register( emit
, &src
[0] ),
1675 translate_src_register( emit
, &src
[1] ),
1676 translate_src_register( emit
, &src
[2] ) );
1684 static boolean
emit_deriv(struct svga_shader_emitter
*emit
,
1685 const struct tgsi_full_instruction
*insn
)
1687 if (emit
->dynamic_branching_level
> 0 &&
1688 insn
->Src
[0].Register
.File
== TGSI_FILE_TEMPORARY
)
1690 struct src_register zero
= get_zero_immediate( emit
);
1691 SVGA3dShaderDestToken dst
=
1692 translate_dst_register( emit
, insn
, 0 );
1694 /* Deriv opcodes not valid inside dynamic branching, workaround
1695 * by zeroing out the destination.
1697 if (!submit_op1(emit
,
1698 inst_token( SVGA3DOP_MOV
),
1700 scalar(zero
, TGSI_SWIZZLE_X
)))
1707 const struct tgsi_full_src_register
*reg
= &insn
->Src
[0];
1708 SVGA3dShaderInstToken inst
;
1709 SVGA3dShaderDestToken dst
;
1710 struct src_register src0
;
1712 switch (insn
->Instruction
.Opcode
) {
1713 case TGSI_OPCODE_DDX
:
1714 opcode
= SVGA3DOP_DSX
;
1716 case TGSI_OPCODE_DDY
:
1717 opcode
= SVGA3DOP_DSY
;
1723 inst
= inst_token( opcode
);
1724 dst
= translate_dst_register( emit
, insn
, 0 );
1725 src0
= translate_src_register( emit
, reg
);
1727 /* We cannot use negate or abs on source to dsx/dsy instruction.
1729 if (reg
->Register
.Absolute
||
1730 reg
->Register
.Negate
) {
1731 SVGA3dShaderDestToken temp
= get_temp( emit
);
1733 if (!emit_repl( emit
, temp
, &src0
))
1737 return submit_op1( emit
, inst
, dst
, src0
);
1741 static boolean
emit_arl(struct svga_shader_emitter
*emit
,
1742 const struct tgsi_full_instruction
*insn
)
1744 ++emit
->current_arl
;
1745 if (emit
->unit
== PIPE_SHADER_FRAGMENT
) {
1746 /* MOVA not present in pixel shader instruction set.
1747 * Ignore this instruction altogether since it is
1748 * only used for loop counters -- and for that
1749 * we reference aL directly.
1753 if (svga_arl_needs_adjustment( emit
)) {
1754 return emit_fake_arl( emit
, insn
);
1756 /* no need to adjust, just emit straight arl */
1757 return emit_simple_instruction(emit
, SVGA3DOP_MOVA
, insn
);
1761 static boolean
emit_pow(struct svga_shader_emitter
*emit
,
1762 const struct tgsi_full_instruction
*insn
)
1764 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1765 struct src_register src0
= translate_src_register(
1766 emit
, &insn
->Src
[0] );
1767 struct src_register src1
= translate_src_register(
1768 emit
, &insn
->Src
[1] );
1769 boolean need_tmp
= FALSE
;
1771 /* POW can only output to a temporary */
1772 if (insn
->Dst
[0].Register
.File
!= TGSI_FILE_TEMPORARY
)
1775 /* POW src1 must not be the same register as dst */
1776 if (alias_src_dst( src1
, dst
))
1779 /* it's a scalar op */
1780 src0
= scalar( src0
, TGSI_SWIZZLE_X
);
1781 src1
= scalar( src1
, TGSI_SWIZZLE_X
);
1784 SVGA3dShaderDestToken tmp
= writemask(get_temp( emit
), TGSI_WRITEMASK_X
);
1786 if (!submit_op2(emit
, inst_token( SVGA3DOP_POW
), tmp
, src0
, src1
))
1789 return submit_op1(emit
, inst_token( SVGA3DOP_MOV
), dst
, scalar(src(tmp
), 0) );
1792 return submit_op2(emit
, inst_token( SVGA3DOP_POW
), dst
, src0
, src1
);
1796 static boolean
emit_xpd(struct svga_shader_emitter
*emit
,
1797 const struct tgsi_full_instruction
*insn
)
1799 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1800 const struct src_register src0
= translate_src_register(
1801 emit
, &insn
->Src
[0] );
1802 const struct src_register src1
= translate_src_register(
1803 emit
, &insn
->Src
[1] );
1804 boolean need_dst_tmp
= FALSE
;
1806 /* XPD can only output to a temporary */
1807 if (SVGA3dShaderGetRegType(dst
.value
) != SVGA3DREG_TEMP
)
1808 need_dst_tmp
= TRUE
;
1810 /* The dst reg must not be the same as src0 or src1*/
1811 if (alias_src_dst(src0
, dst
) ||
1812 alias_src_dst(src1
, dst
))
1813 need_dst_tmp
= TRUE
;
1816 SVGA3dShaderDestToken tmp
= get_temp( emit
);
1818 /* Obey DX9 restrictions on mask:
1820 tmp
.mask
= dst
.mask
& TGSI_WRITEMASK_XYZ
;
1822 if (!submit_op2(emit
, inst_token( SVGA3DOP_CRS
), tmp
, src0
, src1
))
1825 if (!submit_op1(emit
, inst_token( SVGA3DOP_MOV
), dst
, src( tmp
)))
1829 if (!submit_op2(emit
, inst_token( SVGA3DOP_CRS
), dst
, src0
, src1
))
1833 /* Need to emit 1.0 to dst.w?
1835 if (dst
.mask
& TGSI_WRITEMASK_W
) {
1836 struct src_register zero
= get_zero_immediate( emit
);
1838 if (!submit_op1(emit
,
1839 inst_token( SVGA3DOP_MOV
),
1840 writemask(dst
, TGSI_WRITEMASK_W
),
1849 static boolean
emit_lrp(struct svga_shader_emitter
*emit
,
1850 const struct tgsi_full_instruction
*insn
)
1852 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1853 const struct src_register src0
= translate_src_register(
1854 emit
, &insn
->Src
[0] );
1855 const struct src_register src1
= translate_src_register(
1856 emit
, &insn
->Src
[1] );
1857 const struct src_register src2
= translate_src_register(
1858 emit
, &insn
->Src
[2] );
1860 return submit_lrp(emit
, dst
, src0
, src1
, src2
);
1864 static boolean
emit_dst_insn(struct svga_shader_emitter
*emit
,
1865 const struct tgsi_full_instruction
*insn
)
1867 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
1868 /* SVGA/DX9 has a DST instruction, but only for vertex shaders:
1870 return emit_simple_instruction(emit
, SVGA3DOP_DST
, insn
);
1874 /* result[0] = 1 * 1;
1875 * result[1] = a[1] * b[1];
1876 * result[2] = a[2] * 1;
1877 * result[3] = 1 * b[3];
1880 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1881 SVGA3dShaderDestToken tmp
;
1882 const struct src_register src0
= translate_src_register(
1883 emit
, &insn
->Src
[0] );
1884 const struct src_register src1
= translate_src_register(
1885 emit
, &insn
->Src
[1] );
1886 struct src_register zero
= get_zero_immediate( emit
);
1887 boolean need_tmp
= FALSE
;
1889 if (SVGA3dShaderGetRegType(dst
.value
) != SVGA3DREG_TEMP
||
1890 alias_src_dst(src0
, dst
) ||
1891 alias_src_dst(src1
, dst
))
1895 tmp
= get_temp( emit
);
1903 if (tmp
.mask
& TGSI_WRITEMASK_XW
) {
1904 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
1905 writemask(tmp
, TGSI_WRITEMASK_XW
),
1912 if (tmp
.mask
& TGSI_WRITEMASK_YZ
) {
1913 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
1914 writemask(tmp
, TGSI_WRITEMASK_YZ
),
1919 /* tmp.yw = tmp * src1
1921 if (tmp
.mask
& TGSI_WRITEMASK_YW
) {
1922 if (!submit_op2( emit
, inst_token( SVGA3DOP_MUL
),
1923 writemask(tmp
, TGSI_WRITEMASK_YW
),
1932 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
1943 static boolean
emit_exp(struct svga_shader_emitter
*emit
,
1944 const struct tgsi_full_instruction
*insn
)
1946 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
1947 struct src_register src0
=
1948 translate_src_register( emit
, &insn
->Src
[0] );
1949 struct src_register zero
= get_zero_immediate( emit
);
1950 SVGA3dShaderDestToken fraction
;
1952 if (dst
.mask
& TGSI_WRITEMASK_Y
)
1954 else if (dst
.mask
& TGSI_WRITEMASK_X
)
1955 fraction
= get_temp( emit
);
1959 /* If y is being written, fill it with src0 - floor(src0).
1961 if (dst
.mask
& TGSI_WRITEMASK_XY
) {
1962 if (!submit_op1( emit
, inst_token( SVGA3DOP_FRC
),
1963 writemask( fraction
, TGSI_WRITEMASK_Y
),
1968 /* If x is being written, fill it with 2 ^ floor(src0).
1970 if (dst
.mask
& TGSI_WRITEMASK_X
) {
1971 if (!submit_op2( emit
, inst_token( SVGA3DOP_ADD
),
1972 writemask( dst
, TGSI_WRITEMASK_X
),
1974 scalar( negate( src( fraction
) ), TGSI_SWIZZLE_Y
) ) )
1977 if (!submit_op1( emit
, inst_token( SVGA3DOP_EXP
),
1978 writemask( dst
, TGSI_WRITEMASK_X
),
1979 scalar( src( dst
), TGSI_SWIZZLE_X
) ) )
1982 if (!(dst
.mask
& TGSI_WRITEMASK_Y
))
1983 release_temp( emit
, fraction
);
1986 /* If z is being written, fill it with 2 ^ src0 (partial precision).
1988 if (dst
.mask
& TGSI_WRITEMASK_Z
) {
1989 if (!submit_op1( emit
, inst_token( SVGA3DOP_EXPP
),
1990 writemask( dst
, TGSI_WRITEMASK_Z
),
1995 /* If w is being written, fill it with one.
1997 if (dst
.mask
& TGSI_WRITEMASK_W
) {
1998 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
1999 writemask(dst
, TGSI_WRITEMASK_W
),
2000 scalar( zero
, TGSI_SWIZZLE_W
) ))
2007 static boolean
emit_lit(struct svga_shader_emitter
*emit
,
2008 const struct tgsi_full_instruction
*insn
)
2010 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
2011 /* SVGA/DX9 has a LIT instruction, but only for vertex shaders:
2013 return emit_simple_instruction(emit
, SVGA3DOP_LIT
, insn
);
2017 /* D3D vs. GL semantics can be fairly easily accomodated by
2018 * variations on this sequence.
2022 * tmp.z = pow(src.y,src.w)
2023 * p0 = src0.xxxx > 0
2024 * result = zero.wxxw
2025 * (p0) result.yz = tmp
2029 * tmp.z = pow(src.y,src.w)
2030 * p0 = src0.xxyy > 0
2031 * result = zero.wxxw
2032 * (p0) result.yz = tmp
2034 * Will implement the GL version for now.
2037 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
2038 SVGA3dShaderDestToken tmp
= get_temp( emit
);
2039 const struct src_register src0
= translate_src_register(
2040 emit
, &insn
->Src
[0] );
2041 struct src_register zero
= get_zero_immediate( emit
);
2043 /* tmp = pow(src.y, src.w)
2045 if (dst
.mask
& TGSI_WRITEMASK_Z
) {
2046 if (!submit_op2(emit
, inst_token( SVGA3DOP_POW
),
2055 if (dst
.mask
& TGSI_WRITEMASK_Y
) {
2056 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
2057 writemask(tmp
, TGSI_WRITEMASK_Y
),
2062 /* Can't quite do this with emit conditional due to the extra
2063 * writemask on the predicated mov:
2066 SVGA3dShaderDestToken pred_reg
= dst_register( SVGA3DREG_PREDICATE
, 0 );
2067 SVGA3dShaderInstToken setp_token
, mov_token
;
2068 struct src_register predsrc
;
2070 setp_token
= inst_token( SVGA3DOP_SETP
);
2071 mov_token
= inst_token( SVGA3DOP_MOV
);
2073 setp_token
.control
= SVGA3DOPCOMP_GT
;
2075 /* D3D vs GL semantics:
2078 predsrc
= swizzle(src0
, 0, 0, 1, 1); /* D3D */
2080 predsrc
= swizzle(src0
, 0, 0, 0, 0); /* GL */
2082 /* SETP src0.xxyy, GT, {0}.x */
2083 if (!submit_op2( emit
, setp_token
, pred_reg
,
2085 swizzle(zero
, 0, 0, 0, 0) ))
2089 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), dst
,
2090 swizzle(zero
, 3, 0, 0, 3 )))
2093 /* MOV dst.yz, tmp (predicated)
2095 * Note that the predicate reg (and possible modifiers) is passed
2096 * as the first source argument.
2098 if (dst
.mask
& TGSI_WRITEMASK_YZ
) {
2099 mov_token
.predicated
= 1;
2100 if (!submit_op2( emit
, mov_token
,
2101 writemask(dst
, TGSI_WRITEMASK_YZ
),
2102 src( pred_reg
), src( tmp
) ))
2114 static boolean
emit_ex2( struct svga_shader_emitter
*emit
,
2115 const struct tgsi_full_instruction
*insn
)
2117 SVGA3dShaderInstToken inst
;
2118 SVGA3dShaderDestToken dst
;
2119 struct src_register src0
;
2121 inst
= inst_token( SVGA3DOP_EXP
);
2122 dst
= translate_dst_register( emit
, insn
, 0 );
2123 src0
= translate_src_register( emit
, &insn
->Src
[0] );
2124 src0
= scalar( src0
, TGSI_SWIZZLE_X
);
2126 if (dst
.mask
!= TGSI_WRITEMASK_XYZW
) {
2127 SVGA3dShaderDestToken tmp
= get_temp( emit
);
2129 if (!submit_op1( emit
, inst
, tmp
, src0
))
2132 return submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
2134 scalar( src( tmp
), TGSI_SWIZZLE_X
) );
2137 return submit_op1( emit
, inst
, dst
, src0
);
2141 static boolean
emit_log(struct svga_shader_emitter
*emit
,
2142 const struct tgsi_full_instruction
*insn
)
2144 SVGA3dShaderDestToken dst
= translate_dst_register( emit
, insn
, 0 );
2145 struct src_register src0
=
2146 translate_src_register( emit
, &insn
->Src
[0] );
2147 struct src_register zero
= get_zero_immediate( emit
);
2148 SVGA3dShaderDestToken abs_tmp
;
2149 struct src_register abs_src0
;
2150 SVGA3dShaderDestToken log2_abs
;
2154 if (dst
.mask
& TGSI_WRITEMASK_Z
)
2156 else if (dst
.mask
& TGSI_WRITEMASK_XY
)
2157 log2_abs
= get_temp( emit
);
2161 /* If z is being written, fill it with log2( abs( src0 ) ).
2163 if (dst
.mask
& TGSI_WRITEMASK_XYZ
) {
2164 if (!src0
.base
.srcMod
|| src0
.base
.srcMod
== SVGA3DSRCMOD_ABS
)
2167 abs_tmp
= get_temp( emit
);
2169 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
2174 abs_src0
= src( abs_tmp
);
2177 abs_src0
= absolute( scalar( abs_src0
, TGSI_SWIZZLE_X
) );
2179 if (!submit_op1( emit
, inst_token( SVGA3DOP_LOG
),
2180 writemask( log2_abs
, TGSI_WRITEMASK_Z
),
2185 if (dst
.mask
& TGSI_WRITEMASK_XY
) {
2186 SVGA3dShaderDestToken floor_log2
;
2188 if (dst
.mask
& TGSI_WRITEMASK_X
)
2191 floor_log2
= get_temp( emit
);
2193 /* If x is being written, fill it with floor( log2( abs( src0 ) ) ).
2195 if (!submit_op1( emit
, inst_token( SVGA3DOP_FRC
),
2196 writemask( floor_log2
, TGSI_WRITEMASK_X
),
2197 scalar( src( log2_abs
), TGSI_SWIZZLE_Z
) ) )
2200 if (!submit_op2( emit
, inst_token( SVGA3DOP_ADD
),
2201 writemask( floor_log2
, TGSI_WRITEMASK_X
),
2202 scalar( src( log2_abs
), TGSI_SWIZZLE_Z
),
2203 negate( src( floor_log2
) ) ) )
2206 /* If y is being written, fill it with
2207 * abs ( src0 ) / ( 2 ^ floor( log2( abs( src0 ) ) ) ).
2209 if (dst
.mask
& TGSI_WRITEMASK_Y
) {
2210 if (!submit_op1( emit
, inst_token( SVGA3DOP_EXP
),
2211 writemask( dst
, TGSI_WRITEMASK_Y
),
2212 negate( scalar( src( floor_log2
),
2213 TGSI_SWIZZLE_X
) ) ) )
2216 if (!submit_op2( emit
, inst_token( SVGA3DOP_MUL
),
2217 writemask( dst
, TGSI_WRITEMASK_Y
),
2223 if (!(dst
.mask
& TGSI_WRITEMASK_X
))
2224 release_temp( emit
, floor_log2
);
2226 if (!(dst
.mask
& TGSI_WRITEMASK_Z
))
2227 release_temp( emit
, log2_abs
);
2230 if (dst
.mask
& TGSI_WRITEMASK_XYZ
&& src0
.base
.srcMod
&&
2231 src0
.base
.srcMod
!= SVGA3DSRCMOD_ABS
)
2232 release_temp( emit
, abs_tmp
);
2234 /* If w is being written, fill it with one.
2236 if (dst
.mask
& TGSI_WRITEMASK_W
) {
2237 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
),
2238 writemask(dst
, TGSI_WRITEMASK_W
),
2239 scalar( zero
, TGSI_SWIZZLE_W
) ))
2247 static boolean
emit_bgnsub( struct svga_shader_emitter
*emit
,
2249 const struct tgsi_full_instruction
*insn
)
2253 /* Note that we've finished the main function and are now emitting
2254 * subroutines. This affects how we terminate the generated
2257 emit
->in_main_func
= FALSE
;
2259 for (i
= 0; i
< emit
->nr_labels
; i
++) {
2260 if (emit
->label
[i
] == position
) {
2261 return (emit_instruction( emit
, inst_token( SVGA3DOP_RET
) ) &&
2262 emit_instruction( emit
, inst_token( SVGA3DOP_LABEL
) ) &&
2263 emit_src( emit
, src_register( SVGA3DREG_LABEL
, i
)));
2271 static boolean
emit_call( struct svga_shader_emitter
*emit
,
2272 const struct tgsi_full_instruction
*insn
)
2274 unsigned position
= insn
->Label
.Label
;
2277 for (i
= 0; i
< emit
->nr_labels
; i
++) {
2278 if (emit
->label
[i
] == position
)
2282 if (emit
->nr_labels
== Elements(emit
->label
))
2285 if (i
== emit
->nr_labels
) {
2286 emit
->label
[i
] = position
;
2290 return (emit_instruction( emit
, inst_token( SVGA3DOP_CALL
) ) &&
2291 emit_src( emit
, src_register( SVGA3DREG_LABEL
, i
)));
2295 static boolean
emit_end( struct svga_shader_emitter
*emit
)
2297 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
2298 return emit_vs_postamble( emit
);
2301 return emit_ps_postamble( emit
);
2307 static boolean
svga_emit_instruction( struct svga_shader_emitter
*emit
,
2309 const struct tgsi_full_instruction
*insn
)
2311 switch (insn
->Instruction
.Opcode
) {
2313 case TGSI_OPCODE_ARL
:
2314 return emit_arl( emit
, insn
);
2316 case TGSI_OPCODE_TEX
:
2317 case TGSI_OPCODE_TXB
:
2318 case TGSI_OPCODE_TXP
:
2319 case TGSI_OPCODE_TXL
:
2320 case TGSI_OPCODE_TXD
:
2321 return emit_tex( emit
, insn
);
2323 case TGSI_OPCODE_DDX
:
2324 case TGSI_OPCODE_DDY
:
2325 return emit_deriv( emit
, insn
);
2327 case TGSI_OPCODE_BGNSUB
:
2328 return emit_bgnsub( emit
, position
, insn
);
2330 case TGSI_OPCODE_ENDSUB
:
2333 case TGSI_OPCODE_CAL
:
2334 return emit_call( emit
, insn
);
2336 case TGSI_OPCODE_FLR
:
2337 case TGSI_OPCODE_TRUNC
: /* should be TRUNC, not FLR */
2338 return emit_floor( emit
, insn
);
2340 case TGSI_OPCODE_CMP
:
2341 return emit_cmp( emit
, insn
);
2343 case TGSI_OPCODE_DIV
:
2344 return emit_div( emit
, insn
);
2346 case TGSI_OPCODE_DP2
:
2347 return emit_dp2( emit
, insn
);
2349 case TGSI_OPCODE_DPH
:
2350 return emit_dph( emit
, insn
);
2352 case TGSI_OPCODE_NRM
:
2353 return emit_nrm( emit
, insn
);
2355 case TGSI_OPCODE_COS
:
2356 return emit_cos( emit
, insn
);
2358 case TGSI_OPCODE_SIN
:
2359 return emit_sin( emit
, insn
);
2361 case TGSI_OPCODE_SCS
:
2362 return emit_sincos( emit
, insn
);
2364 case TGSI_OPCODE_END
:
2365 /* TGSI always finishes the main func with an END */
2366 return emit_end( emit
);
2368 case TGSI_OPCODE_KIL
:
2369 return emit_kil( emit
, insn
);
2371 /* Selection opcodes. The underlying language is fairly
2372 * non-orthogonal about these.
2374 case TGSI_OPCODE_SEQ
:
2375 return emit_select_op( emit
, PIPE_FUNC_EQUAL
, insn
);
2377 case TGSI_OPCODE_SNE
:
2378 return emit_select_op( emit
, PIPE_FUNC_NOTEQUAL
, insn
);
2380 case TGSI_OPCODE_SGT
:
2381 return emit_select_op( emit
, PIPE_FUNC_GREATER
, insn
);
2383 case TGSI_OPCODE_SGE
:
2384 return emit_select_op( emit
, PIPE_FUNC_GEQUAL
, insn
);
2386 case TGSI_OPCODE_SLT
:
2387 return emit_select_op( emit
, PIPE_FUNC_LESS
, insn
);
2389 case TGSI_OPCODE_SLE
:
2390 return emit_select_op( emit
, PIPE_FUNC_LEQUAL
, insn
);
2392 case TGSI_OPCODE_SUB
:
2393 return emit_sub( emit
, insn
);
2395 case TGSI_OPCODE_POW
:
2396 return emit_pow( emit
, insn
);
2398 case TGSI_OPCODE_EX2
:
2399 return emit_ex2( emit
, insn
);
2401 case TGSI_OPCODE_EXP
:
2402 return emit_exp( emit
, insn
);
2404 case TGSI_OPCODE_LOG
:
2405 return emit_log( emit
, insn
);
2407 case TGSI_OPCODE_LG2
:
2408 return emit_scalar_op1( emit
, SVGA3DOP_LOG
, insn
);
2410 case TGSI_OPCODE_RSQ
:
2411 return emit_scalar_op1( emit
, SVGA3DOP_RSQ
, insn
);
2413 case TGSI_OPCODE_RCP
:
2414 return emit_scalar_op1( emit
, SVGA3DOP_RCP
, insn
);
2416 case TGSI_OPCODE_CONT
:
2417 case TGSI_OPCODE_RET
:
2418 /* This is a noop -- we tell mesa that we can't support RET
2419 * within a function (early return), so this will always be
2420 * followed by an ENDSUB.
2424 /* These aren't actually used by any of the frontends we care
2427 case TGSI_OPCODE_CLAMP
:
2428 case TGSI_OPCODE_ROUND
:
2429 case TGSI_OPCODE_AND
:
2430 case TGSI_OPCODE_OR
:
2431 case TGSI_OPCODE_I2F
:
2432 case TGSI_OPCODE_NOT
:
2433 case TGSI_OPCODE_SHL
:
2434 case TGSI_OPCODE_ISHR
:
2435 case TGSI_OPCODE_XOR
:
2438 case TGSI_OPCODE_IF
:
2439 return emit_if( emit
, insn
);
2440 case TGSI_OPCODE_ELSE
:
2441 return emit_else( emit
, insn
);
2442 case TGSI_OPCODE_ENDIF
:
2443 return emit_endif( emit
, insn
);
2445 case TGSI_OPCODE_BGNLOOP
:
2446 return emit_bgnloop2( emit
, insn
);
2447 case TGSI_OPCODE_ENDLOOP
:
2448 return emit_endloop2( emit
, insn
);
2449 case TGSI_OPCODE_BRK
:
2450 return emit_brk( emit
, insn
);
2452 case TGSI_OPCODE_XPD
:
2453 return emit_xpd( emit
, insn
);
2455 case TGSI_OPCODE_KILP
:
2456 return emit_kilp( emit
, insn
);
2458 case TGSI_OPCODE_DST
:
2459 return emit_dst_insn( emit
, insn
);
2461 case TGSI_OPCODE_LIT
:
2462 return emit_lit( emit
, insn
);
2464 case TGSI_OPCODE_LRP
:
2465 return emit_lrp( emit
, insn
);
2467 case TGSI_OPCODE_SSG
:
2468 return emit_ssg( emit
, insn
);
2471 unsigned opcode
= translate_opcode(insn
->Instruction
.Opcode
);
2473 if (opcode
== SVGA3DOP_LAST_INST
)
2476 if (!emit_simple_instruction( emit
, opcode
, insn
))
2485 static boolean
svga_emit_immediate( struct svga_shader_emitter
*emit
,
2486 struct tgsi_full_immediate
*imm
)
2488 static const float id
[4] = {0,0,0,1};
2492 assert(1 <= imm
->Immediate
.NrTokens
&& imm
->Immediate
.NrTokens
<= 5);
2493 for (i
= 0; i
< imm
->Immediate
.NrTokens
- 1; i
++)
2494 value
[i
] = imm
->u
[i
].Float
;
2496 for ( ; i
< 4; i
++ )
2499 return emit_def_const( emit
, SVGA3D_CONST_TYPE_FLOAT
,
2500 emit
->imm_start
+ emit
->internal_imm_count
++,
2501 value
[0], value
[1], value
[2], value
[3]);
2504 static boolean
make_immediate( struct svga_shader_emitter
*emit
,
2509 struct src_register
*out
)
2511 unsigned idx
= emit
->nr_hw_float_const
++;
2513 if (!emit_def_const( emit
, SVGA3D_CONST_TYPE_FLOAT
,
2517 *out
= src_register( SVGA3DREG_CONST
, idx
);
2522 static boolean
emit_vs_preamble( struct svga_shader_emitter
*emit
)
2524 if (!emit
->key
.vkey
.need_prescale
) {
2525 if (!make_immediate( emit
, 0, 0, .5, .5,
2533 static boolean
emit_ps_preamble( struct svga_shader_emitter
*emit
)
2537 /* For SM20, need to initialize the temporaries we're using to hold
2538 * color outputs to some value. Shaders which don't set all of
2539 * these values are likely to be rejected by the DX9 runtime.
2541 if (!emit
->use_sm30
) {
2542 struct src_register zero
= get_zero_immediate( emit
);
2543 for (i
= 0; i
< PIPE_MAX_COLOR_BUFS
; i
++) {
2544 if (SVGA3dShaderGetRegType(emit
->true_col
[i
].value
) != 0) {
2546 if (!submit_op1( emit
,
2547 inst_token(SVGA3DOP_MOV
),
2558 static boolean
emit_ps_postamble( struct svga_shader_emitter
*emit
)
2562 /* PS oDepth is incredibly fragile and it's very hard to catch the
2563 * types of usage that break it during shader emit. Easier just to
2564 * redirect the main program to a temporary and then only touch
2565 * oDepth with a hand-crafted MOV below.
2567 if (SVGA3dShaderGetRegType(emit
->true_pos
.value
) != 0) {
2569 if (!submit_op1( emit
,
2570 inst_token(SVGA3DOP_MOV
),
2572 scalar(src(emit
->temp_pos
), TGSI_SWIZZLE_Z
) ))
2576 /* Similarly for SM20 color outputs... Luckily SM30 isn't so
2579 for (i
= 0; i
< PIPE_MAX_COLOR_BUFS
; i
++) {
2580 if (SVGA3dShaderGetRegType(emit
->true_col
[i
].value
) != 0) {
2582 /* Potentially override output colors with white for XOR
2583 * logicop workaround.
2585 if (emit
->unit
== PIPE_SHADER_FRAGMENT
&&
2586 emit
->key
.fkey
.white_fragments
) {
2588 struct src_register one
= scalar( get_zero_immediate( emit
),
2591 if (!submit_op1( emit
,
2592 inst_token(SVGA3DOP_MOV
),
2598 if (!submit_op1( emit
,
2599 inst_token(SVGA3DOP_MOV
),
2601 src(emit
->temp_col
[i
]) ))
2610 static boolean
emit_vs_postamble( struct svga_shader_emitter
*emit
)
2612 /* PSIZ output is incredibly fragile and it's very hard to catch
2613 * the types of usage that break it during shader emit. Easier
2614 * just to redirect the main program to a temporary and then only
2615 * touch PSIZ with a hand-crafted MOV below.
2617 if (SVGA3dShaderGetRegType(emit
->true_psiz
.value
) != 0) {
2619 if (!submit_op1( emit
,
2620 inst_token(SVGA3DOP_MOV
),
2622 scalar(src(emit
->temp_psiz
), TGSI_SWIZZLE_X
) ))
2626 /* Need to perform various manipulations on vertex position to cope
2627 * with the different GL and D3D clip spaces.
2629 if (emit
->key
.vkey
.need_prescale
) {
2630 SVGA3dShaderDestToken temp_pos
= emit
->temp_pos
;
2631 SVGA3dShaderDestToken pos
= emit
->true_pos
;
2632 unsigned offset
= emit
->info
.file_max
[TGSI_FILE_CONSTANT
] + 1;
2633 struct src_register prescale_scale
= src_register( SVGA3DREG_CONST
,
2635 struct src_register prescale_trans
= src_register( SVGA3DREG_CONST
,
2638 /* MUL temp_pos.xyz, temp_pos, prescale.scale
2639 * MAD result.position, temp_pos.wwww, prescale.trans, temp_pos
2640 * --> Note that prescale.trans.w == 0
2642 if (!submit_op2( emit
,
2643 inst_token(SVGA3DOP_MUL
),
2644 writemask(temp_pos
, TGSI_WRITEMASK_XYZ
),
2649 if (!submit_op3( emit
,
2650 inst_token(SVGA3DOP_MAD
),
2652 swizzle(src(temp_pos
), 3, 3, 3, 3),
2658 SVGA3dShaderDestToken temp_pos
= emit
->temp_pos
;
2659 SVGA3dShaderDestToken pos
= emit
->true_pos
;
2660 struct src_register imm_0055
= emit
->imm_0055
;
2662 /* Adjust GL clipping coordinate space to hardware (D3D-style):
2664 * DP4 temp_pos.z, {0,0,.5,.5}, temp_pos
2665 * MOV result.position, temp_pos
2667 if (!submit_op2( emit
,
2668 inst_token(SVGA3DOP_DP4
),
2669 writemask(temp_pos
, TGSI_WRITEMASK_Z
),
2674 if (!submit_op1( emit
,
2675 inst_token(SVGA3DOP_MOV
),
2686 1: COLOR = FrontColor;
2688 3: COLOR = BackColor;
2691 static boolean
emit_light_twoside( struct svga_shader_emitter
*emit
)
2693 struct src_register vface
, zero
;
2694 struct src_register front
[2];
2695 struct src_register back
[2];
2696 SVGA3dShaderDestToken color
[2];
2697 int count
= emit
->internal_color_count
;
2699 SVGA3dShaderInstToken if_token
;
2704 vface
= get_vface( emit
);
2705 zero
= get_zero_immediate( emit
);
2707 /* Can't use get_temp() to allocate the color reg as such
2708 * temporaries will be reclaimed after each instruction by the call
2709 * to reset_temp_regs().
2711 for (i
= 0; i
< count
; i
++) {
2712 color
[i
] = dst_register( SVGA3DREG_TEMP
,
2713 emit
->nr_hw_temp
++ );
2715 front
[i
] = emit
->input_map
[emit
->internal_color_idx
[i
]];
2717 /* Back is always the next input:
2720 back
[i
].base
.num
= front
[i
].base
.num
+ 1;
2722 /* Reassign the input_map to the actual front-face color:
2724 emit
->input_map
[emit
->internal_color_idx
[i
]] = src(color
[i
]);
2727 if_token
= inst_token( SVGA3DOP_IFC
);
2729 if (emit
->key
.fkey
.front_ccw
)
2730 if_token
.control
= SVGA3DOPCOMP_LT
;
2732 if_token
.control
= SVGA3DOPCOMP_GT
;
2734 zero
= scalar(zero
, TGSI_SWIZZLE_X
);
2736 if (!(emit_instruction( emit
, if_token
) &&
2737 emit_src( emit
, vface
) &&
2738 emit_src( emit
, zero
) ))
2741 for (i
= 0; i
< count
; i
++) {
2742 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), color
[i
], front
[i
] ))
2746 if (!(emit_instruction( emit
, inst_token( SVGA3DOP_ELSE
))))
2749 for (i
= 0; i
< count
; i
++) {
2750 if (!submit_op1( emit
, inst_token( SVGA3DOP_MOV
), color
[i
], back
[i
] ))
2754 if (!emit_instruction( emit
, inst_token( SVGA3DOP_ENDIF
) ))
2761 0: SETP_GT TEMP, VFACE, 0
2762 where TEMP is a fake frontface register
2764 static boolean
emit_frontface( struct svga_shader_emitter
*emit
)
2766 struct src_register vface
, zero
;
2767 SVGA3dShaderDestToken temp
;
2768 struct src_register pass
, fail
;
2770 vface
= get_vface( emit
);
2771 zero
= get_zero_immediate( emit
);
2773 /* Can't use get_temp() to allocate the fake frontface reg as such
2774 * temporaries will be reclaimed after each instruction by the call
2775 * to reset_temp_regs().
2777 temp
= dst_register( SVGA3DREG_TEMP
,
2778 emit
->nr_hw_temp
++ );
2780 if (emit
->key
.fkey
.front_ccw
) {
2781 pass
= scalar( zero
, TGSI_SWIZZLE_X
);
2782 fail
= scalar( zero
, TGSI_SWIZZLE_W
);
2784 pass
= scalar( zero
, TGSI_SWIZZLE_W
);
2785 fail
= scalar( zero
, TGSI_SWIZZLE_X
);
2788 if (!emit_conditional(emit
, PIPE_FUNC_GREATER
,
2789 temp
, vface
, scalar( zero
, TGSI_SWIZZLE_X
),
2793 /* Reassign the input_map to the actual front-face color:
2795 emit
->input_map
[emit
->internal_frontface_idx
] = src(temp
);
2800 static INLINE boolean
2801 needs_to_create_zero( struct svga_shader_emitter
*emit
)
2805 if (emit
->unit
== PIPE_SHADER_FRAGMENT
) {
2806 if (!emit
->use_sm30
)
2809 if (emit
->key
.fkey
.light_twoside
)
2812 if (emit
->key
.fkey
.white_fragments
)
2815 if (emit
->emit_frontface
)
2818 if (emit
->info
.opcode_count
[TGSI_OPCODE_DST
] >= 1 ||
2819 emit
->info
.opcode_count
[TGSI_OPCODE_SSG
] >= 1 ||
2820 emit
->info
.opcode_count
[TGSI_OPCODE_LIT
] >= 1)
2824 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
2825 if (emit
->info
.opcode_count
[TGSI_OPCODE_CMP
] >= 1)
2829 if (emit
->info
.opcode_count
[TGSI_OPCODE_IF
] >= 1 ||
2830 emit
->info
.opcode_count
[TGSI_OPCODE_BGNLOOP
] >= 1 ||
2831 emit
->info
.opcode_count
[TGSI_OPCODE_DDX
] >= 1 ||
2832 emit
->info
.opcode_count
[TGSI_OPCODE_DDY
] >= 1 ||
2833 emit
->info
.opcode_count
[TGSI_OPCODE_SGE
] >= 1 ||
2834 emit
->info
.opcode_count
[TGSI_OPCODE_SGT
] >= 1 ||
2835 emit
->info
.opcode_count
[TGSI_OPCODE_SLE
] >= 1 ||
2836 emit
->info
.opcode_count
[TGSI_OPCODE_SLT
] >= 1 ||
2837 emit
->info
.opcode_count
[TGSI_OPCODE_SNE
] >= 1 ||
2838 emit
->info
.opcode_count
[TGSI_OPCODE_SEQ
] >= 1 ||
2839 emit
->info
.opcode_count
[TGSI_OPCODE_EXP
] >= 1 ||
2840 emit
->info
.opcode_count
[TGSI_OPCODE_LOG
] >= 1 ||
2841 emit
->info
.opcode_count
[TGSI_OPCODE_XPD
] >= 1 ||
2842 emit
->info
.opcode_count
[TGSI_OPCODE_KILP
] >= 1)
2845 for (i
= 0; i
< emit
->key
.fkey
.num_textures
; i
++) {
2846 if (emit
->key
.fkey
.tex
[i
].compare_mode
== PIPE_TEX_COMPARE_R_TO_TEXTURE
)
2853 static INLINE boolean
2854 needs_to_create_loop_const( struct svga_shader_emitter
*emit
)
2856 return (emit
->info
.opcode_count
[TGSI_OPCODE_BGNLOOP
] >= 1);
2859 static INLINE boolean
2860 needs_to_create_sincos_consts( struct svga_shader_emitter
*emit
)
2862 return !emit
->use_sm30
&& (emit
->info
.opcode_count
[TGSI_OPCODE_SIN
] >= 1 ||
2863 emit
->info
.opcode_count
[TGSI_OPCODE_COS
] >= 1 ||
2864 emit
->info
.opcode_count
[TGSI_OPCODE_SCS
] >= 1);
2867 static INLINE boolean
2868 needs_to_create_arl_consts( struct svga_shader_emitter
*emit
)
2870 return (emit
->num_arl_consts
> 0);
2873 static INLINE boolean
2874 pre_parse_add_indirect( struct svga_shader_emitter
*emit
,
2875 int num
, int current_arl
)
2880 for (i
= 0; i
< emit
->num_arl_consts
; ++i
) {
2881 if (emit
->arl_consts
[i
].arl_num
== current_arl
)
2885 if (emit
->num_arl_consts
== i
) {
2886 ++emit
->num_arl_consts
;
2888 emit
->arl_consts
[i
].number
= (emit
->arl_consts
[i
].number
> num
) ?
2890 emit
->arl_consts
[i
].number
;
2891 emit
->arl_consts
[i
].arl_num
= current_arl
;
2896 pre_parse_instruction( struct svga_shader_emitter
*emit
,
2897 const struct tgsi_full_instruction
*insn
,
2900 if (insn
->Src
[0].Register
.Indirect
&&
2901 insn
->Src
[0].Indirect
.File
== TGSI_FILE_ADDRESS
) {
2902 const struct tgsi_full_src_register
*reg
= &insn
->Src
[0];
2903 if (reg
->Register
.Index
< 0) {
2904 pre_parse_add_indirect(emit
, reg
->Register
.Index
, current_arl
);
2908 if (insn
->Src
[1].Register
.Indirect
&&
2909 insn
->Src
[1].Indirect
.File
== TGSI_FILE_ADDRESS
) {
2910 const struct tgsi_full_src_register
*reg
= &insn
->Src
[1];
2911 if (reg
->Register
.Index
< 0) {
2912 pre_parse_add_indirect(emit
, reg
->Register
.Index
, current_arl
);
2916 if (insn
->Src
[2].Register
.Indirect
&&
2917 insn
->Src
[2].Indirect
.File
== TGSI_FILE_ADDRESS
) {
2918 const struct tgsi_full_src_register
*reg
= &insn
->Src
[2];
2919 if (reg
->Register
.Index
< 0) {
2920 pre_parse_add_indirect(emit
, reg
->Register
.Index
, current_arl
);
2928 pre_parse_tokens( struct svga_shader_emitter
*emit
,
2929 const struct tgsi_token
*tokens
)
2931 struct tgsi_parse_context parse
;
2932 int current_arl
= 0;
2934 tgsi_parse_init( &parse
, tokens
);
2936 while (!tgsi_parse_end_of_tokens( &parse
)) {
2937 tgsi_parse_token( &parse
);
2938 switch (parse
.FullToken
.Token
.Type
) {
2939 case TGSI_TOKEN_TYPE_IMMEDIATE
:
2940 case TGSI_TOKEN_TYPE_DECLARATION
:
2942 case TGSI_TOKEN_TYPE_INSTRUCTION
:
2943 if (parse
.FullToken
.FullInstruction
.Instruction
.Opcode
==
2947 if (!pre_parse_instruction( emit
, &parse
.FullToken
.FullInstruction
,
2959 static boolean
svga_shader_emit_helpers( struct svga_shader_emitter
*emit
)
2962 if (needs_to_create_zero( emit
)) {
2963 create_zero_immediate( emit
);
2965 if (needs_to_create_loop_const( emit
)) {
2966 create_loop_const( emit
);
2968 if (needs_to_create_sincos_consts( emit
)) {
2969 create_sincos_consts( emit
);
2971 if (needs_to_create_arl_consts( emit
)) {
2972 create_arl_consts( emit
);
2975 if (emit
->unit
== PIPE_SHADER_FRAGMENT
) {
2976 if (!emit_ps_preamble( emit
))
2979 if (emit
->key
.fkey
.light_twoside
) {
2980 if (!emit_light_twoside( emit
))
2983 if (emit
->emit_frontface
) {
2984 if (!emit_frontface( emit
))
2992 boolean
svga_shader_emit_instructions( struct svga_shader_emitter
*emit
,
2993 const struct tgsi_token
*tokens
)
2995 struct tgsi_parse_context parse
;
2997 boolean helpers_emitted
= FALSE
;
2998 unsigned line_nr
= 0;
3000 tgsi_parse_init( &parse
, tokens
);
3001 emit
->internal_imm_count
= 0;
3003 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
3004 ret
= emit_vs_preamble( emit
);
3009 pre_parse_tokens(emit
, tokens
);
3011 while (!tgsi_parse_end_of_tokens( &parse
)) {
3012 tgsi_parse_token( &parse
);
3014 switch (parse
.FullToken
.Token
.Type
) {
3015 case TGSI_TOKEN_TYPE_IMMEDIATE
:
3016 ret
= svga_emit_immediate( emit
, &parse
.FullToken
.FullImmediate
);
3021 case TGSI_TOKEN_TYPE_DECLARATION
:
3023 ret
= svga_translate_decl_sm30( emit
, &parse
.FullToken
.FullDeclaration
);
3025 ret
= svga_translate_decl_sm20( emit
, &parse
.FullToken
.FullDeclaration
);
3030 case TGSI_TOKEN_TYPE_INSTRUCTION
:
3031 if (!helpers_emitted
) {
3032 if (!svga_shader_emit_helpers( emit
))
3034 helpers_emitted
= TRUE
;
3036 ret
= svga_emit_instruction( emit
,
3038 &parse
.FullToken
.FullInstruction
);
3046 reset_temp_regs( emit
);
3049 /* Need to terminate the current subroutine. Note that the
3050 * hardware doesn't tolerate shaders without sub-routines
3051 * terminating with RET+END.
3053 if (!emit
->in_main_func
) {
3054 ret
= emit_instruction( emit
, inst_token( SVGA3DOP_RET
) );
3059 assert(emit
->dynamic_branching_level
== 0);
3061 /* Need to terminate the whole shader:
3063 ret
= emit_instruction( emit
, inst_token( SVGA3DOP_END
) );
3069 tgsi_parse_free( &parse
);