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[mesa.git] / src / gallium / drivers / svga / svga_tgsi_vgpu10.c
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2 * Copyright 1998-2013 VMware, Inc. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
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25
26 /**
27 * @file svga_tgsi_vgpu10.c
28 *
29 * TGSI -> VGPU10 shader translation.
30 *
31 * \author Mingcheng Chen
32 * \author Brian Paul
33 */
34
35 #include "pipe/p_compiler.h"
36 #include "pipe/p_shader_tokens.h"
37 #include "pipe/p_defines.h"
38 #include "tgsi/tgsi_build.h"
39 #include "tgsi/tgsi_dump.h"
40 #include "tgsi/tgsi_info.h"
41 #include "tgsi/tgsi_parse.h"
42 #include "tgsi/tgsi_scan.h"
43 #include "tgsi/tgsi_two_side.h"
44 #include "tgsi/tgsi_aa_point.h"
45 #include "tgsi/tgsi_util.h"
46 #include "util/u_math.h"
47 #include "util/u_memory.h"
48 #include "util/u_bitmask.h"
49 #include "util/u_debug.h"
50 #include "util/u_pstipple.h"
51
52 #include "svga_context.h"
53 #include "svga_debug.h"
54 #include "svga_link.h"
55 #include "svga_shader.h"
56 #include "svga_tgsi.h"
57
58 #include "VGPU10ShaderTokens.h"
59
60
61 #define INVALID_INDEX 99999
62 #define MAX_INTERNAL_TEMPS 3
63 #define MAX_SYSTEM_VALUES 4
64 #define MAX_IMMEDIATE_COUNT \
65 (VGPU10_MAX_IMMEDIATE_CONSTANT_BUFFER_ELEMENT_COUNT/4)
66 #define MAX_TEMP_ARRAYS 64 /* Enough? */
67
68
69 /**
70 * Clipping is complicated. There's four different cases which we
71 * handle during VS/GS shader translation:
72 */
73 enum clipping_mode
74 {
75 CLIP_NONE, /**< No clipping enabled */
76 CLIP_LEGACY, /**< The shader has no clipping declarations or code but
77 * one or more user-defined clip planes are enabled. We
78 * generate extra code to emit clip distances.
79 */
80 CLIP_DISTANCE, /**< The shader already declares clip distance output
81 * registers and has code to write to them.
82 */
83 CLIP_VERTEX /**< The shader declares a clip vertex output register and
84 * has code that writes to the register. We convert the
85 * clipvertex position into one or more clip distances.
86 */
87 };
88
89
90 struct svga_shader_emitter_v10
91 {
92 /* The token output buffer */
93 unsigned size;
94 char *buf;
95 char *ptr;
96
97 /* Information about the shader and state (does not change) */
98 struct svga_compile_key key;
99 struct tgsi_shader_info info;
100 unsigned unit;
101
102 unsigned inst_start_token;
103 boolean discard_instruction; /**< throw away current instruction? */
104
105 union tgsi_immediate_data immediates[MAX_IMMEDIATE_COUNT][4];
106 unsigned num_immediates; /**< Number of immediates emitted */
107 unsigned common_immediate_pos[8]; /**< literals for common immediates */
108 unsigned num_common_immediates;
109 boolean immediates_emitted;
110
111 unsigned num_outputs; /**< include any extra outputs */
112 /** The first extra output is reserved for
113 * non-adjusted vertex position for
114 * stream output purpose
115 */
116
117 /* Temporary Registers */
118 unsigned num_shader_temps; /**< num of temps used by original shader */
119 unsigned internal_temp_count; /**< currently allocated internal temps */
120 struct {
121 unsigned start, size;
122 } temp_arrays[MAX_TEMP_ARRAYS];
123 unsigned num_temp_arrays;
124
125 /** Map TGSI temp registers to VGPU10 temp array IDs and indexes */
126 struct {
127 unsigned arrayId, index;
128 } temp_map[VGPU10_MAX_TEMPS]; /**< arrayId, element */
129
130 /** Number of constants used by original shader for each constant buffer.
131 * The size should probably always match with that of svga_state.constbufs.
132 */
133 unsigned num_shader_consts[SVGA_MAX_CONST_BUFS];
134
135 /* Samplers */
136 unsigned num_samplers;
137 ubyte sampler_target[PIPE_MAX_SAMPLERS]; /**< TGSI_TEXTURE_x */
138 ubyte sampler_return_type[PIPE_MAX_SAMPLERS]; /**< TGSI_RETURN_TYPE_x */
139
140 /* Address regs (really implemented with temps) */
141 unsigned num_address_regs;
142 unsigned address_reg_index[MAX_VGPU10_ADDR_REGS];
143
144 /* Output register usage masks */
145 ubyte output_usage_mask[PIPE_MAX_SHADER_OUTPUTS];
146
147 /* To map TGSI system value index to VGPU shader input indexes */
148 ubyte system_value_indexes[MAX_SYSTEM_VALUES];
149
150 struct {
151 /* vertex position scale/translation */
152 unsigned out_index; /**< the real position output reg */
153 unsigned tmp_index; /**< the fake/temp position output reg */
154 unsigned so_index; /**< the non-adjusted position output reg */
155 unsigned prescale_scale_index, prescale_trans_index;
156 boolean need_prescale;
157 } vposition;
158
159 /* For vertex shaders only */
160 struct {
161 /* viewport constant */
162 unsigned viewport_index;
163
164 /* temp index of adjusted vertex attributes */
165 unsigned adjusted_input[PIPE_MAX_SHADER_INPUTS];
166 } vs;
167
168 /* For fragment shaders only */
169 struct {
170 /* apha test */
171 unsigned color_out_index[PIPE_MAX_COLOR_BUFS]; /**< the real color output regs */
172 unsigned color_tmp_index; /**< fake/temp color output reg */
173 unsigned alpha_ref_index; /**< immediate constant for alpha ref */
174
175 /* front-face */
176 unsigned face_input_index; /**< real fragment shader face reg (bool) */
177 unsigned face_tmp_index; /**< temp face reg converted to -1 / +1 */
178
179 unsigned pstipple_sampler_unit;
180
181 unsigned fragcoord_input_index; /**< real fragment position input reg */
182 unsigned fragcoord_tmp_index; /**< 1/w modified position temp reg */
183 } fs;
184
185 /* For geometry shaders only */
186 struct {
187 VGPU10_PRIMITIVE prim_type;/**< VGPU10 primitive type */
188 VGPU10_PRIMITIVE_TOPOLOGY prim_topology; /**< VGPU10 primitive topology */
189 unsigned input_size; /**< size of input arrays */
190 unsigned prim_id_index; /**< primitive id register index */
191 unsigned max_out_vertices; /**< maximum number of output vertices */
192 } gs;
193
194 /* For vertex or geometry shaders */
195 enum clipping_mode clip_mode;
196 unsigned clip_dist_out_index; /**< clip distance output register index */
197 unsigned clip_dist_tmp_index; /**< clip distance temporary register */
198 unsigned clip_dist_so_index; /**< clip distance shadow copy */
199
200 /** Index of temporary holding the clipvertex coordinate */
201 unsigned clip_vertex_out_index; /**< clip vertex output register index */
202 unsigned clip_vertex_tmp_index; /**< clip vertex temporary index */
203
204 /* user clip plane constant slot indexes */
205 unsigned clip_plane_const[PIPE_MAX_CLIP_PLANES];
206
207 unsigned num_output_writes;
208 boolean constant_color_output;
209
210 boolean uses_flat_interp;
211
212 /* For all shaders: const reg index for RECT coord scaling */
213 unsigned texcoord_scale_index[PIPE_MAX_SAMPLERS];
214
215 /* For all shaders: const reg index for texture buffer size */
216 unsigned texture_buffer_size_index[PIPE_MAX_SAMPLERS];
217
218 /* VS/GS/FS Linkage info */
219 struct shader_linkage linkage;
220
221 bool register_overflow; /**< Set if we exceed a VGPU10 register limit */
222 };
223
224
225 static boolean
226 emit_post_helpers(struct svga_shader_emitter_v10 *emit);
227
228 static boolean
229 emit_vertex(struct svga_shader_emitter_v10 *emit,
230 const struct tgsi_full_instruction *inst);
231
232 static char err_buf[128];
233
234 static boolean
235 expand(struct svga_shader_emitter_v10 *emit)
236 {
237 char *new_buf;
238 unsigned newsize = emit->size * 2;
239
240 if (emit->buf != err_buf)
241 new_buf = REALLOC(emit->buf, emit->size, newsize);
242 else
243 new_buf = NULL;
244
245 if (!new_buf) {
246 emit->ptr = err_buf;
247 emit->buf = err_buf;
248 emit->size = sizeof(err_buf);
249 return FALSE;
250 }
251
252 emit->size = newsize;
253 emit->ptr = new_buf + (emit->ptr - emit->buf);
254 emit->buf = new_buf;
255 return TRUE;
256 }
257
258 /**
259 * Create and initialize a new svga_shader_emitter_v10 object.
260 */
261 static struct svga_shader_emitter_v10 *
262 alloc_emitter(void)
263 {
264 struct svga_shader_emitter_v10 *emit = CALLOC(1, sizeof(*emit));
265
266 if (!emit)
267 return NULL;
268
269 /* to initialize the output buffer */
270 emit->size = 512;
271 if (!expand(emit)) {
272 FREE(emit);
273 return NULL;
274 }
275 return emit;
276 }
277
278 /**
279 * Free an svga_shader_emitter_v10 object.
280 */
281 static void
282 free_emitter(struct svga_shader_emitter_v10 *emit)
283 {
284 assert(emit);
285 FREE(emit->buf); /* will be NULL if translation succeeded */
286 FREE(emit);
287 }
288
289 static inline boolean
290 reserve(struct svga_shader_emitter_v10 *emit,
291 unsigned nr_dwords)
292 {
293 while (emit->ptr - emit->buf + nr_dwords * sizeof(uint32) >= emit->size) {
294 if (!expand(emit))
295 return FALSE;
296 }
297
298 return TRUE;
299 }
300
301 static boolean
302 emit_dword(struct svga_shader_emitter_v10 *emit, uint32 dword)
303 {
304 if (!reserve(emit, 1))
305 return FALSE;
306
307 *(uint32 *)emit->ptr = dword;
308 emit->ptr += sizeof dword;
309 return TRUE;
310 }
311
312 static boolean
313 emit_dwords(struct svga_shader_emitter_v10 *emit,
314 const uint32 *dwords,
315 unsigned nr)
316 {
317 if (!reserve(emit, nr))
318 return FALSE;
319
320 memcpy(emit->ptr, dwords, nr * sizeof *dwords);
321 emit->ptr += nr * sizeof *dwords;
322 return TRUE;
323 }
324
325 /** Return the number of tokens in the emitter's buffer */
326 static unsigned
327 emit_get_num_tokens(const struct svga_shader_emitter_v10 *emit)
328 {
329 return (emit->ptr - emit->buf) / sizeof(unsigned);
330 }
331
332
333 /**
334 * Check for register overflow. If we overflow we'll set an
335 * error flag. This function can be called for register declarations
336 * or use as src/dst instruction operands.
337 * \param type register type. One of VGPU10_OPERAND_TYPE_x
338 or VGPU10_OPCODE_DCL_x
339 * \param index the register index
340 */
341 static void
342 check_register_index(struct svga_shader_emitter_v10 *emit,
343 unsigned operandType, unsigned index)
344 {
345 bool overflow_before = emit->register_overflow;
346
347 switch (operandType) {
348 case VGPU10_OPERAND_TYPE_TEMP:
349 case VGPU10_OPERAND_TYPE_INDEXABLE_TEMP:
350 case VGPU10_OPCODE_DCL_TEMPS:
351 if (index >= VGPU10_MAX_TEMPS) {
352 emit->register_overflow = TRUE;
353 }
354 break;
355 case VGPU10_OPERAND_TYPE_CONSTANT_BUFFER:
356 case VGPU10_OPCODE_DCL_CONSTANT_BUFFER:
357 if (index >= VGPU10_MAX_CONSTANT_BUFFER_ELEMENT_COUNT) {
358 emit->register_overflow = TRUE;
359 }
360 break;
361 case VGPU10_OPERAND_TYPE_INPUT:
362 case VGPU10_OPERAND_TYPE_INPUT_PRIMITIVEID:
363 case VGPU10_OPCODE_DCL_INPUT:
364 case VGPU10_OPCODE_DCL_INPUT_SGV:
365 case VGPU10_OPCODE_DCL_INPUT_SIV:
366 case VGPU10_OPCODE_DCL_INPUT_PS:
367 case VGPU10_OPCODE_DCL_INPUT_PS_SGV:
368 case VGPU10_OPCODE_DCL_INPUT_PS_SIV:
369 if ((emit->unit == PIPE_SHADER_VERTEX &&
370 index >= VGPU10_MAX_VS_INPUTS) ||
371 (emit->unit == PIPE_SHADER_GEOMETRY &&
372 index >= VGPU10_MAX_GS_INPUTS) ||
373 (emit->unit == PIPE_SHADER_FRAGMENT &&
374 index >= VGPU10_MAX_FS_INPUTS)) {
375 emit->register_overflow = TRUE;
376 }
377 break;
378 case VGPU10_OPERAND_TYPE_OUTPUT:
379 case VGPU10_OPCODE_DCL_OUTPUT:
380 case VGPU10_OPCODE_DCL_OUTPUT_SGV:
381 case VGPU10_OPCODE_DCL_OUTPUT_SIV:
382 if ((emit->unit == PIPE_SHADER_VERTEX &&
383 index >= VGPU10_MAX_VS_OUTPUTS) ||
384 (emit->unit == PIPE_SHADER_GEOMETRY &&
385 index >= VGPU10_MAX_GS_OUTPUTS) ||
386 (emit->unit == PIPE_SHADER_FRAGMENT &&
387 index >= VGPU10_MAX_FS_OUTPUTS)) {
388 emit->register_overflow = TRUE;
389 }
390 break;
391 case VGPU10_OPERAND_TYPE_SAMPLER:
392 case VGPU10_OPCODE_DCL_SAMPLER:
393 if (index >= VGPU10_MAX_SAMPLERS) {
394 emit->register_overflow = TRUE;
395 }
396 break;
397 case VGPU10_OPERAND_TYPE_RESOURCE:
398 case VGPU10_OPCODE_DCL_RESOURCE:
399 if (index >= VGPU10_MAX_RESOURCES) {
400 emit->register_overflow = TRUE;
401 }
402 break;
403 case VGPU10_OPERAND_TYPE_IMMEDIATE_CONSTANT_BUFFER:
404 if (index >= MAX_IMMEDIATE_COUNT) {
405 emit->register_overflow = TRUE;
406 }
407 break;
408 default:
409 assert(0);
410 ; /* nothing */
411 }
412
413 if (emit->register_overflow && !overflow_before) {
414 debug_printf("svga: vgpu10 register overflow (reg %u, index %u)\n",
415 operandType, index);
416 }
417 }
418
419
420 /**
421 * Examine misc state to determine the clipping mode.
422 */
423 static void
424 determine_clipping_mode(struct svga_shader_emitter_v10 *emit)
425 {
426 if (emit->info.num_written_clipdistance > 0) {
427 emit->clip_mode = CLIP_DISTANCE;
428 }
429 else if (emit->info.writes_clipvertex) {
430 emit->clip_mode = CLIP_VERTEX;
431 }
432 else if (emit->key.clip_plane_enable) {
433 emit->clip_mode = CLIP_LEGACY;
434 }
435 else {
436 emit->clip_mode = CLIP_NONE;
437 }
438 }
439
440
441 /**
442 * For clip distance register declarations and clip distance register
443 * writes we need to mask the declaration usage or instruction writemask
444 * (respectively) against the set of the really-enabled clipping planes.
445 *
446 * The piglit test spec/glsl-1.30/execution/clipping/vs-clip-distance-enables
447 * has a VS that writes to all 8 clip distance registers, but the plane enable
448 * flags are a subset of that.
449 *
450 * This function is used to apply the plane enable flags to the register
451 * declaration or instruction writemask.
452 *
453 * \param writemask the declaration usage mask or instruction writemask
454 * \param clip_reg_index which clip plane register is being declared/written.
455 * The legal values are 0 and 1 (two clip planes per
456 * register, for a total of 8 clip planes)
457 */
458 static unsigned
459 apply_clip_plane_mask(struct svga_shader_emitter_v10 *emit,
460 unsigned writemask, unsigned clip_reg_index)
461 {
462 unsigned shift;
463
464 assert(clip_reg_index < 2);
465
466 /* four clip planes per clip register: */
467 shift = clip_reg_index * 4;
468 writemask &= ((emit->key.clip_plane_enable >> shift) & 0xf);
469
470 return writemask;
471 }
472
473
474 /**
475 * Translate gallium shader type into VGPU10 type.
476 */
477 static VGPU10_PROGRAM_TYPE
478 translate_shader_type(unsigned type)
479 {
480 switch (type) {
481 case PIPE_SHADER_VERTEX:
482 return VGPU10_VERTEX_SHADER;
483 case PIPE_SHADER_GEOMETRY:
484 return VGPU10_GEOMETRY_SHADER;
485 case PIPE_SHADER_FRAGMENT:
486 return VGPU10_PIXEL_SHADER;
487 default:
488 assert(!"Unexpected shader type");
489 return VGPU10_VERTEX_SHADER;
490 }
491 }
492
493
494 /**
495 * Translate a TGSI_OPCODE_x into a VGPU10_OPCODE_x
496 * Note: we only need to translate the opcodes for "simple" instructions,
497 * as seen below. All other opcodes are handled/translated specially.
498 */
499 static VGPU10_OPCODE_TYPE
500 translate_opcode(unsigned opcode)
501 {
502 switch (opcode) {
503 case TGSI_OPCODE_MOV:
504 return VGPU10_OPCODE_MOV;
505 case TGSI_OPCODE_MUL:
506 return VGPU10_OPCODE_MUL;
507 case TGSI_OPCODE_ADD:
508 return VGPU10_OPCODE_ADD;
509 case TGSI_OPCODE_DP3:
510 return VGPU10_OPCODE_DP3;
511 case TGSI_OPCODE_DP4:
512 return VGPU10_OPCODE_DP4;
513 case TGSI_OPCODE_MIN:
514 return VGPU10_OPCODE_MIN;
515 case TGSI_OPCODE_MAX:
516 return VGPU10_OPCODE_MAX;
517 case TGSI_OPCODE_MAD:
518 return VGPU10_OPCODE_MAD;
519 case TGSI_OPCODE_SQRT:
520 return VGPU10_OPCODE_SQRT;
521 case TGSI_OPCODE_FRC:
522 return VGPU10_OPCODE_FRC;
523 case TGSI_OPCODE_FLR:
524 return VGPU10_OPCODE_ROUND_NI;
525 case TGSI_OPCODE_FSEQ:
526 return VGPU10_OPCODE_EQ;
527 case TGSI_OPCODE_FSGE:
528 return VGPU10_OPCODE_GE;
529 case TGSI_OPCODE_FSNE:
530 return VGPU10_OPCODE_NE;
531 case TGSI_OPCODE_DDX:
532 return VGPU10_OPCODE_DERIV_RTX;
533 case TGSI_OPCODE_DDY:
534 return VGPU10_OPCODE_DERIV_RTY;
535 case TGSI_OPCODE_RET:
536 return VGPU10_OPCODE_RET;
537 case TGSI_OPCODE_DIV:
538 return VGPU10_OPCODE_DIV;
539 case TGSI_OPCODE_IDIV:
540 return VGPU10_OPCODE_IDIV;
541 case TGSI_OPCODE_DP2:
542 return VGPU10_OPCODE_DP2;
543 case TGSI_OPCODE_BRK:
544 return VGPU10_OPCODE_BREAK;
545 case TGSI_OPCODE_IF:
546 return VGPU10_OPCODE_IF;
547 case TGSI_OPCODE_ELSE:
548 return VGPU10_OPCODE_ELSE;
549 case TGSI_OPCODE_ENDIF:
550 return VGPU10_OPCODE_ENDIF;
551 case TGSI_OPCODE_CEIL:
552 return VGPU10_OPCODE_ROUND_PI;
553 case TGSI_OPCODE_I2F:
554 return VGPU10_OPCODE_ITOF;
555 case TGSI_OPCODE_NOT:
556 return VGPU10_OPCODE_NOT;
557 case TGSI_OPCODE_TRUNC:
558 return VGPU10_OPCODE_ROUND_Z;
559 case TGSI_OPCODE_SHL:
560 return VGPU10_OPCODE_ISHL;
561 case TGSI_OPCODE_AND:
562 return VGPU10_OPCODE_AND;
563 case TGSI_OPCODE_OR:
564 return VGPU10_OPCODE_OR;
565 case TGSI_OPCODE_XOR:
566 return VGPU10_OPCODE_XOR;
567 case TGSI_OPCODE_CONT:
568 return VGPU10_OPCODE_CONTINUE;
569 case TGSI_OPCODE_EMIT:
570 return VGPU10_OPCODE_EMIT;
571 case TGSI_OPCODE_ENDPRIM:
572 return VGPU10_OPCODE_CUT;
573 case TGSI_OPCODE_BGNLOOP:
574 return VGPU10_OPCODE_LOOP;
575 case TGSI_OPCODE_ENDLOOP:
576 return VGPU10_OPCODE_ENDLOOP;
577 case TGSI_OPCODE_ENDSUB:
578 return VGPU10_OPCODE_RET;
579 case TGSI_OPCODE_NOP:
580 return VGPU10_OPCODE_NOP;
581 case TGSI_OPCODE_BREAKC:
582 return VGPU10_OPCODE_BREAKC;
583 case TGSI_OPCODE_END:
584 return VGPU10_OPCODE_RET;
585 case TGSI_OPCODE_F2I:
586 return VGPU10_OPCODE_FTOI;
587 case TGSI_OPCODE_IMAX:
588 return VGPU10_OPCODE_IMAX;
589 case TGSI_OPCODE_IMIN:
590 return VGPU10_OPCODE_IMIN;
591 case TGSI_OPCODE_UDIV:
592 case TGSI_OPCODE_UMOD:
593 case TGSI_OPCODE_MOD:
594 return VGPU10_OPCODE_UDIV;
595 case TGSI_OPCODE_IMUL_HI:
596 return VGPU10_OPCODE_IMUL;
597 case TGSI_OPCODE_INEG:
598 return VGPU10_OPCODE_INEG;
599 case TGSI_OPCODE_ISHR:
600 return VGPU10_OPCODE_ISHR;
601 case TGSI_OPCODE_ISGE:
602 return VGPU10_OPCODE_IGE;
603 case TGSI_OPCODE_ISLT:
604 return VGPU10_OPCODE_ILT;
605 case TGSI_OPCODE_F2U:
606 return VGPU10_OPCODE_FTOU;
607 case TGSI_OPCODE_UADD:
608 return VGPU10_OPCODE_IADD;
609 case TGSI_OPCODE_U2F:
610 return VGPU10_OPCODE_UTOF;
611 case TGSI_OPCODE_UCMP:
612 return VGPU10_OPCODE_MOVC;
613 case TGSI_OPCODE_UMAD:
614 return VGPU10_OPCODE_UMAD;
615 case TGSI_OPCODE_UMAX:
616 return VGPU10_OPCODE_UMAX;
617 case TGSI_OPCODE_UMIN:
618 return VGPU10_OPCODE_UMIN;
619 case TGSI_OPCODE_UMUL:
620 case TGSI_OPCODE_UMUL_HI:
621 return VGPU10_OPCODE_UMUL;
622 case TGSI_OPCODE_USEQ:
623 return VGPU10_OPCODE_IEQ;
624 case TGSI_OPCODE_USGE:
625 return VGPU10_OPCODE_UGE;
626 case TGSI_OPCODE_USHR:
627 return VGPU10_OPCODE_USHR;
628 case TGSI_OPCODE_USLT:
629 return VGPU10_OPCODE_ULT;
630 case TGSI_OPCODE_USNE:
631 return VGPU10_OPCODE_INE;
632 case TGSI_OPCODE_SWITCH:
633 return VGPU10_OPCODE_SWITCH;
634 case TGSI_OPCODE_CASE:
635 return VGPU10_OPCODE_CASE;
636 case TGSI_OPCODE_DEFAULT:
637 return VGPU10_OPCODE_DEFAULT;
638 case TGSI_OPCODE_ENDSWITCH:
639 return VGPU10_OPCODE_ENDSWITCH;
640 case TGSI_OPCODE_FSLT:
641 return VGPU10_OPCODE_LT;
642 case TGSI_OPCODE_ROUND:
643 return VGPU10_OPCODE_ROUND_NE;
644 default:
645 assert(!"Unexpected TGSI opcode in translate_opcode()");
646 return VGPU10_OPCODE_NOP;
647 }
648 }
649
650
651 /**
652 * Translate a TGSI register file type into a VGPU10 operand type.
653 * \param array is the TGSI_FILE_TEMPORARY register an array?
654 */
655 static VGPU10_OPERAND_TYPE
656 translate_register_file(enum tgsi_file_type file, boolean array)
657 {
658 switch (file) {
659 case TGSI_FILE_CONSTANT:
660 return VGPU10_OPERAND_TYPE_CONSTANT_BUFFER;
661 case TGSI_FILE_INPUT:
662 return VGPU10_OPERAND_TYPE_INPUT;
663 case TGSI_FILE_OUTPUT:
664 return VGPU10_OPERAND_TYPE_OUTPUT;
665 case TGSI_FILE_TEMPORARY:
666 return array ? VGPU10_OPERAND_TYPE_INDEXABLE_TEMP
667 : VGPU10_OPERAND_TYPE_TEMP;
668 case TGSI_FILE_IMMEDIATE:
669 /* all immediates are 32-bit values at this time so
670 * VGPU10_OPERAND_TYPE_IMMEDIATE64 is not possible at this time.
671 */
672 return VGPU10_OPERAND_TYPE_IMMEDIATE_CONSTANT_BUFFER;
673 case TGSI_FILE_SAMPLER:
674 return VGPU10_OPERAND_TYPE_SAMPLER;
675 case TGSI_FILE_SYSTEM_VALUE:
676 return VGPU10_OPERAND_TYPE_INPUT;
677
678 /* XXX TODO more cases to finish */
679
680 default:
681 assert(!"Bad tgsi register file!");
682 return VGPU10_OPERAND_TYPE_NULL;
683 }
684 }
685
686
687 /**
688 * Emit a null dst register
689 */
690 static void
691 emit_null_dst_register(struct svga_shader_emitter_v10 *emit)
692 {
693 VGPU10OperandToken0 operand;
694
695 operand.value = 0;
696 operand.operandType = VGPU10_OPERAND_TYPE_NULL;
697 operand.numComponents = VGPU10_OPERAND_0_COMPONENT;
698
699 emit_dword(emit, operand.value);
700 }
701
702
703 /**
704 * If the given register is a temporary, return the array ID.
705 * Else return zero.
706 */
707 static unsigned
708 get_temp_array_id(const struct svga_shader_emitter_v10 *emit,
709 unsigned file, unsigned index)
710 {
711 if (file == TGSI_FILE_TEMPORARY) {
712 return emit->temp_map[index].arrayId;
713 }
714 else {
715 return 0;
716 }
717 }
718
719
720 /**
721 * If the given register is a temporary, convert the index from a TGSI
722 * TEMPORARY index to a VGPU10 temp index.
723 */
724 static unsigned
725 remap_temp_index(const struct svga_shader_emitter_v10 *emit,
726 unsigned file, unsigned index)
727 {
728 if (file == TGSI_FILE_TEMPORARY) {
729 return emit->temp_map[index].index;
730 }
731 else {
732 return index;
733 }
734 }
735
736
737 /**
738 * Setup the operand0 fields related to indexing (1D, 2D, relative, etc).
739 * Note: the operandType field must already be initialized.
740 */
741 static VGPU10OperandToken0
742 setup_operand0_indexing(struct svga_shader_emitter_v10 *emit,
743 VGPU10OperandToken0 operand0,
744 unsigned file,
745 boolean indirect, boolean index2D,
746 unsigned tempArrayID)
747 {
748 unsigned indexDim, index0Rep, index1Rep = VGPU10_OPERAND_INDEX_IMMEDIATE32;
749
750 /*
751 * Compute index dimensions
752 */
753 if (operand0.operandType == VGPU10_OPERAND_TYPE_IMMEDIATE32 ||
754 operand0.operandType == VGPU10_OPERAND_TYPE_INPUT_PRIMITIVEID) {
755 /* there's no swizzle for in-line immediates */
756 indexDim = VGPU10_OPERAND_INDEX_0D;
757 assert(operand0.selectionMode == 0);
758 }
759 else {
760 if (index2D ||
761 tempArrayID > 0 ||
762 operand0.operandType == VGPU10_OPERAND_TYPE_CONSTANT_BUFFER) {
763 indexDim = VGPU10_OPERAND_INDEX_2D;
764 }
765 else {
766 indexDim = VGPU10_OPERAND_INDEX_1D;
767 }
768 }
769
770 /*
771 * Compute index representations (immediate, relative, etc).
772 */
773 if (tempArrayID > 0) {
774 assert(file == TGSI_FILE_TEMPORARY);
775 /* First index is the array ID, second index is the array element */
776 index0Rep = VGPU10_OPERAND_INDEX_IMMEDIATE32;
777 if (indirect) {
778 index1Rep = VGPU10_OPERAND_INDEX_IMMEDIATE32_PLUS_RELATIVE;
779 }
780 else {
781 index1Rep = VGPU10_OPERAND_INDEX_IMMEDIATE32;
782 }
783 }
784 else if (indirect) {
785 if (file == TGSI_FILE_CONSTANT) {
786 /* index[0] indicates which constant buffer while index[1] indicates
787 * the position in the constant buffer.
788 */
789 index0Rep = VGPU10_OPERAND_INDEX_IMMEDIATE32;
790 index1Rep = VGPU10_OPERAND_INDEX_IMMEDIATE32_PLUS_RELATIVE;
791 }
792 else {
793 /* All other register files are 1-dimensional */
794 index0Rep = VGPU10_OPERAND_INDEX_IMMEDIATE32_PLUS_RELATIVE;
795 }
796 }
797 else {
798 index0Rep = VGPU10_OPERAND_INDEX_IMMEDIATE32;
799 index1Rep = VGPU10_OPERAND_INDEX_IMMEDIATE32;
800 }
801
802 operand0.indexDimension = indexDim;
803 operand0.index0Representation = index0Rep;
804 operand0.index1Representation = index1Rep;
805
806 return operand0;
807 }
808
809
810 /**
811 * Emit the operand for expressing an address register for indirect indexing.
812 * Note that the address register is really just a temp register.
813 * \param addr_reg_index which address register to use
814 */
815 static void
816 emit_indirect_register(struct svga_shader_emitter_v10 *emit,
817 unsigned addr_reg_index)
818 {
819 unsigned tmp_reg_index;
820 VGPU10OperandToken0 operand0;
821
822 assert(addr_reg_index < MAX_VGPU10_ADDR_REGS);
823
824 tmp_reg_index = emit->address_reg_index[addr_reg_index];
825
826 /* operand0 is a simple temporary register, selecting one component */
827 operand0.value = 0;
828 operand0.operandType = VGPU10_OPERAND_TYPE_TEMP;
829 operand0.numComponents = VGPU10_OPERAND_4_COMPONENT;
830 operand0.indexDimension = VGPU10_OPERAND_INDEX_1D;
831 operand0.index0Representation = VGPU10_OPERAND_INDEX_IMMEDIATE32;
832 operand0.selectionMode = VGPU10_OPERAND_4_COMPONENT_SELECT_1_MODE;
833 operand0.swizzleX = 0;
834 operand0.swizzleY = 1;
835 operand0.swizzleZ = 2;
836 operand0.swizzleW = 3;
837
838 emit_dword(emit, operand0.value);
839 emit_dword(emit, remap_temp_index(emit, TGSI_FILE_TEMPORARY, tmp_reg_index));
840 }
841
842
843 /**
844 * Translate the dst register of a TGSI instruction and emit VGPU10 tokens.
845 * \param emit the emitter context
846 * \param reg the TGSI dst register to translate
847 */
848 static void
849 emit_dst_register(struct svga_shader_emitter_v10 *emit,
850 const struct tgsi_full_dst_register *reg)
851 {
852 unsigned file = reg->Register.File;
853 unsigned index = reg->Register.Index;
854 const unsigned sem_name = emit->info.output_semantic_name[index];
855 const unsigned sem_index = emit->info.output_semantic_index[index];
856 unsigned writemask = reg->Register.WriteMask;
857 const unsigned indirect = reg->Register.Indirect;
858 const unsigned tempArrayId = get_temp_array_id(emit, file, index);
859 const unsigned index2d = reg->Register.Dimension;
860 VGPU10OperandToken0 operand0;
861
862 if (file == TGSI_FILE_OUTPUT) {
863 if (emit->unit == PIPE_SHADER_VERTEX ||
864 emit->unit == PIPE_SHADER_GEOMETRY) {
865 if (index == emit->vposition.out_index &&
866 emit->vposition.tmp_index != INVALID_INDEX) {
867 /* replace OUTPUT[POS] with TEMP[POS]. We need to store the
868 * vertex position result in a temporary so that we can modify
869 * it in the post_helper() code.
870 */
871 file = TGSI_FILE_TEMPORARY;
872 index = emit->vposition.tmp_index;
873 }
874 else if (sem_name == TGSI_SEMANTIC_CLIPDIST &&
875 emit->clip_dist_tmp_index != INVALID_INDEX) {
876 /* replace OUTPUT[CLIPDIST] with TEMP[CLIPDIST].
877 * We store the clip distance in a temporary first, then
878 * we'll copy it to the shadow copy and to CLIPDIST with the
879 * enabled planes mask in emit_clip_distance_instructions().
880 */
881 file = TGSI_FILE_TEMPORARY;
882 index = emit->clip_dist_tmp_index + sem_index;
883 }
884 else if (sem_name == TGSI_SEMANTIC_CLIPVERTEX &&
885 emit->clip_vertex_tmp_index != INVALID_INDEX) {
886 /* replace the CLIPVERTEX output register with a temporary */
887 assert(emit->clip_mode == CLIP_VERTEX);
888 assert(sem_index == 0);
889 file = TGSI_FILE_TEMPORARY;
890 index = emit->clip_vertex_tmp_index;
891 }
892 }
893 else if (emit->unit == PIPE_SHADER_FRAGMENT) {
894 if (sem_name == TGSI_SEMANTIC_POSITION) {
895 /* Fragment depth output register */
896 operand0.value = 0;
897 operand0.operandType = VGPU10_OPERAND_TYPE_OUTPUT_DEPTH;
898 operand0.indexDimension = VGPU10_OPERAND_INDEX_0D;
899 operand0.numComponents = VGPU10_OPERAND_1_COMPONENT;
900 emit_dword(emit, operand0.value);
901 return;
902 }
903 else if (index == emit->fs.color_out_index[0] &&
904 emit->fs.color_tmp_index != INVALID_INDEX) {
905 /* replace OUTPUT[COLOR] with TEMP[COLOR]. We need to store the
906 * fragment color result in a temporary so that we can read it
907 * it in the post_helper() code.
908 */
909 file = TGSI_FILE_TEMPORARY;
910 index = emit->fs.color_tmp_index;
911 }
912 else {
913 /* Typically, for fragment shaders, the output register index
914 * matches the color semantic index. But not when we write to
915 * the fragment depth register. In that case, OUT[0] will be
916 * fragdepth and OUT[1] will be the 0th color output. We need
917 * to use the semantic index for color outputs.
918 */
919 assert(sem_name == TGSI_SEMANTIC_COLOR);
920 index = emit->info.output_semantic_index[index];
921
922 emit->num_output_writes++;
923 }
924 }
925 }
926
927 /* init operand tokens to all zero */
928 operand0.value = 0;
929
930 operand0.numComponents = VGPU10_OPERAND_4_COMPONENT;
931
932 /* the operand has a writemask */
933 operand0.selectionMode = VGPU10_OPERAND_4_COMPONENT_MASK_MODE;
934
935 /* Which of the four dest components to write to. Note that we can use a
936 * simple assignment here since TGSI writemasks match VGPU10 writemasks.
937 */
938 STATIC_ASSERT(TGSI_WRITEMASK_X == VGPU10_OPERAND_4_COMPONENT_MASK_X);
939 operand0.mask = writemask;
940
941 /* translate TGSI register file type to VGPU10 operand type */
942 operand0.operandType = translate_register_file(file, tempArrayId > 0);
943
944 check_register_index(emit, operand0.operandType, index);
945
946 operand0 = setup_operand0_indexing(emit, operand0, file, indirect,
947 index2d, tempArrayId);
948
949 /* Emit tokens */
950 emit_dword(emit, operand0.value);
951 if (tempArrayId > 0) {
952 emit_dword(emit, tempArrayId);
953 }
954
955 emit_dword(emit, remap_temp_index(emit, file, index));
956
957 if (indirect) {
958 emit_indirect_register(emit, reg->Indirect.Index);
959 }
960 }
961
962
963 /**
964 * Translate a src register of a TGSI instruction and emit VGPU10 tokens.
965 */
966 static void
967 emit_src_register(struct svga_shader_emitter_v10 *emit,
968 const struct tgsi_full_src_register *reg)
969 {
970 unsigned file = reg->Register.File;
971 unsigned index = reg->Register.Index;
972 const unsigned indirect = reg->Register.Indirect;
973 const unsigned tempArrayId = get_temp_array_id(emit, file, index);
974 const unsigned index2d = reg->Register.Dimension;
975 const unsigned swizzleX = reg->Register.SwizzleX;
976 const unsigned swizzleY = reg->Register.SwizzleY;
977 const unsigned swizzleZ = reg->Register.SwizzleZ;
978 const unsigned swizzleW = reg->Register.SwizzleW;
979 const unsigned absolute = reg->Register.Absolute;
980 const unsigned negate = reg->Register.Negate;
981 bool is_prim_id = FALSE;
982
983 VGPU10OperandToken0 operand0;
984 VGPU10OperandToken1 operand1;
985
986 if (emit->unit == PIPE_SHADER_FRAGMENT &&
987 file == TGSI_FILE_INPUT) {
988 if (index == emit->fs.face_input_index) {
989 /* Replace INPUT[FACE] with TEMP[FACE] */
990 file = TGSI_FILE_TEMPORARY;
991 index = emit->fs.face_tmp_index;
992 }
993 else if (index == emit->fs.fragcoord_input_index) {
994 /* Replace INPUT[POSITION] with TEMP[POSITION] */
995 file = TGSI_FILE_TEMPORARY;
996 index = emit->fs.fragcoord_tmp_index;
997 }
998 else {
999 /* We remap fragment shader inputs to that FS input indexes
1000 * match up with VS/GS output indexes.
1001 */
1002 index = emit->linkage.input_map[index];
1003 }
1004 }
1005 else if (emit->unit == PIPE_SHADER_GEOMETRY &&
1006 file == TGSI_FILE_INPUT) {
1007 is_prim_id = (index == emit->gs.prim_id_index);
1008 index = emit->linkage.input_map[index];
1009 }
1010 else if (emit->unit == PIPE_SHADER_VERTEX) {
1011 if (file == TGSI_FILE_INPUT) {
1012 /* if input is adjusted... */
1013 if ((emit->key.vs.adjust_attrib_w_1 |
1014 emit->key.vs.adjust_attrib_itof |
1015 emit->key.vs.adjust_attrib_utof |
1016 emit->key.vs.attrib_is_bgra |
1017 emit->key.vs.attrib_puint_to_snorm |
1018 emit->key.vs.attrib_puint_to_uscaled |
1019 emit->key.vs.attrib_puint_to_sscaled) & (1 << index)) {
1020 file = TGSI_FILE_TEMPORARY;
1021 index = emit->vs.adjusted_input[index];
1022 }
1023 }
1024 else if (file == TGSI_FILE_SYSTEM_VALUE) {
1025 assert(index < ARRAY_SIZE(emit->system_value_indexes));
1026 index = emit->system_value_indexes[index];
1027 }
1028 }
1029
1030 operand0.value = operand1.value = 0;
1031
1032 if (is_prim_id) {
1033 /* NOTE: we should be using VGPU10_OPERAND_1_COMPONENT here, but
1034 * our virtual GPU accepts this as-is.
1035 */
1036 operand0.numComponents = VGPU10_OPERAND_0_COMPONENT;
1037 operand0.operandType = VGPU10_OPERAND_TYPE_INPUT_PRIMITIVEID;
1038 }
1039 else {
1040 operand0.numComponents = VGPU10_OPERAND_4_COMPONENT;
1041 operand0.operandType = translate_register_file(file, tempArrayId > 0);
1042 }
1043
1044 operand0 = setup_operand0_indexing(emit, operand0, file, indirect,
1045 index2d, tempArrayId);
1046
1047 if (operand0.operandType != VGPU10_OPERAND_TYPE_IMMEDIATE32 &&
1048 operand0.operandType != VGPU10_OPERAND_TYPE_INPUT_PRIMITIVEID) {
1049 /* there's no swizzle for in-line immediates */
1050 if (swizzleX == swizzleY &&
1051 swizzleX == swizzleZ &&
1052 swizzleX == swizzleW) {
1053 operand0.selectionMode = VGPU10_OPERAND_4_COMPONENT_SELECT_1_MODE;
1054 }
1055 else {
1056 operand0.selectionMode = VGPU10_OPERAND_4_COMPONENT_SWIZZLE_MODE;
1057 }
1058
1059 operand0.swizzleX = swizzleX;
1060 operand0.swizzleY = swizzleY;
1061 operand0.swizzleZ = swizzleZ;
1062 operand0.swizzleW = swizzleW;
1063
1064 if (absolute || negate) {
1065 operand0.extended = 1;
1066 operand1.extendedOperandType = VGPU10_EXTENDED_OPERAND_MODIFIER;
1067 if (absolute && !negate)
1068 operand1.operandModifier = VGPU10_OPERAND_MODIFIER_ABS;
1069 if (!absolute && negate)
1070 operand1.operandModifier = VGPU10_OPERAND_MODIFIER_NEG;
1071 if (absolute && negate)
1072 operand1.operandModifier = VGPU10_OPERAND_MODIFIER_ABSNEG;
1073 }
1074 }
1075
1076 /* Emit the operand tokens */
1077 emit_dword(emit, operand0.value);
1078 if (operand0.extended)
1079 emit_dword(emit, operand1.value);
1080
1081 if (operand0.operandType == VGPU10_OPERAND_TYPE_IMMEDIATE32) {
1082 /* Emit the four float/int in-line immediate values */
1083 unsigned *c;
1084 assert(index < ARRAY_SIZE(emit->immediates));
1085 assert(file == TGSI_FILE_IMMEDIATE);
1086 assert(swizzleX < 4);
1087 assert(swizzleY < 4);
1088 assert(swizzleZ < 4);
1089 assert(swizzleW < 4);
1090 c = (unsigned *) emit->immediates[index];
1091 emit_dword(emit, c[swizzleX]);
1092 emit_dword(emit, c[swizzleY]);
1093 emit_dword(emit, c[swizzleZ]);
1094 emit_dword(emit, c[swizzleW]);
1095 }
1096 else if (operand0.indexDimension >= VGPU10_OPERAND_INDEX_1D) {
1097 /* Emit the register index(es) */
1098 if (index2d ||
1099 operand0.operandType == VGPU10_OPERAND_TYPE_CONSTANT_BUFFER) {
1100 emit_dword(emit, reg->Dimension.Index);
1101 }
1102
1103 if (tempArrayId > 0) {
1104 emit_dword(emit, tempArrayId);
1105 }
1106
1107 emit_dword(emit, remap_temp_index(emit, file, index));
1108
1109 if (indirect) {
1110 emit_indirect_register(emit, reg->Indirect.Index);
1111 }
1112 }
1113 }
1114
1115
1116 /**
1117 * Emit a resource operand (for use with a SAMPLE instruction).
1118 */
1119 static void
1120 emit_resource_register(struct svga_shader_emitter_v10 *emit,
1121 unsigned resource_number)
1122 {
1123 VGPU10OperandToken0 operand0;
1124
1125 check_register_index(emit, VGPU10_OPERAND_TYPE_RESOURCE, resource_number);
1126
1127 /* init */
1128 operand0.value = 0;
1129
1130 operand0.operandType = VGPU10_OPERAND_TYPE_RESOURCE;
1131 operand0.indexDimension = VGPU10_OPERAND_INDEX_1D;
1132 operand0.numComponents = VGPU10_OPERAND_4_COMPONENT;
1133 operand0.selectionMode = VGPU10_OPERAND_4_COMPONENT_SWIZZLE_MODE;
1134 operand0.swizzleX = VGPU10_COMPONENT_X;
1135 operand0.swizzleY = VGPU10_COMPONENT_Y;
1136 operand0.swizzleZ = VGPU10_COMPONENT_Z;
1137 operand0.swizzleW = VGPU10_COMPONENT_W;
1138
1139 emit_dword(emit, operand0.value);
1140 emit_dword(emit, resource_number);
1141 }
1142
1143
1144 /**
1145 * Emit a sampler operand (for use with a SAMPLE instruction).
1146 */
1147 static void
1148 emit_sampler_register(struct svga_shader_emitter_v10 *emit,
1149 unsigned sampler_number)
1150 {
1151 VGPU10OperandToken0 operand0;
1152
1153 check_register_index(emit, VGPU10_OPERAND_TYPE_SAMPLER, sampler_number);
1154
1155 /* init */
1156 operand0.value = 0;
1157
1158 operand0.operandType = VGPU10_OPERAND_TYPE_SAMPLER;
1159 operand0.indexDimension = VGPU10_OPERAND_INDEX_1D;
1160
1161 emit_dword(emit, operand0.value);
1162 emit_dword(emit, sampler_number);
1163 }
1164
1165
1166 /**
1167 * Emit an operand which reads the IS_FRONT_FACING register.
1168 */
1169 static void
1170 emit_face_register(struct svga_shader_emitter_v10 *emit)
1171 {
1172 VGPU10OperandToken0 operand0;
1173 unsigned index = emit->linkage.input_map[emit->fs.face_input_index];
1174
1175 /* init */
1176 operand0.value = 0;
1177
1178 operand0.operandType = VGPU10_OPERAND_TYPE_INPUT;
1179 operand0.indexDimension = VGPU10_OPERAND_INDEX_1D;
1180 operand0.selectionMode = VGPU10_OPERAND_4_COMPONENT_SELECT_1_MODE;
1181 operand0.numComponents = VGPU10_OPERAND_4_COMPONENT;
1182
1183 operand0.swizzleX = VGPU10_COMPONENT_X;
1184 operand0.swizzleY = VGPU10_COMPONENT_X;
1185 operand0.swizzleZ = VGPU10_COMPONENT_X;
1186 operand0.swizzleW = VGPU10_COMPONENT_X;
1187
1188 emit_dword(emit, operand0.value);
1189 emit_dword(emit, index);
1190 }
1191
1192
1193 /**
1194 * Emit the token for a VGPU10 opcode.
1195 * \param saturate clamp result to [0,1]?
1196 */
1197 static void
1198 emit_opcode(struct svga_shader_emitter_v10 *emit,
1199 unsigned vgpu10_opcode, boolean saturate)
1200 {
1201 VGPU10OpcodeToken0 token0;
1202
1203 token0.value = 0; /* init all fields to zero */
1204 token0.opcodeType = vgpu10_opcode;
1205 token0.instructionLength = 0; /* Filled in by end_emit_instruction() */
1206 token0.saturate = saturate;
1207
1208 emit_dword(emit, token0.value);
1209 }
1210
1211
1212 /**
1213 * Emit the token for a VGPU10 resinfo instruction.
1214 * \param modifier return type modifier, _uint or _rcpFloat.
1215 * TODO: We may want to remove this parameter if it will
1216 * only ever be used as _uint.
1217 */
1218 static void
1219 emit_opcode_resinfo(struct svga_shader_emitter_v10 *emit,
1220 VGPU10_RESINFO_RETURN_TYPE modifier)
1221 {
1222 VGPU10OpcodeToken0 token0;
1223
1224 token0.value = 0; /* init all fields to zero */
1225 token0.opcodeType = VGPU10_OPCODE_RESINFO;
1226 token0.instructionLength = 0; /* Filled in by end_emit_instruction() */
1227 token0.resinfoReturnType = modifier;
1228
1229 emit_dword(emit, token0.value);
1230 }
1231
1232
1233 /**
1234 * Emit opcode tokens for a texture sample instruction. Texture instructions
1235 * can be rather complicated (texel offsets, etc) so we have this specialized
1236 * function.
1237 */
1238 static void
1239 emit_sample_opcode(struct svga_shader_emitter_v10 *emit,
1240 unsigned vgpu10_opcode, boolean saturate,
1241 const int offsets[3])
1242 {
1243 VGPU10OpcodeToken0 token0;
1244 VGPU10OpcodeToken1 token1;
1245
1246 token0.value = 0; /* init all fields to zero */
1247 token0.opcodeType = vgpu10_opcode;
1248 token0.instructionLength = 0; /* Filled in by end_emit_instruction() */
1249 token0.saturate = saturate;
1250
1251 if (offsets[0] || offsets[1] || offsets[2]) {
1252 assert(offsets[0] >= VGPU10_MIN_TEXEL_FETCH_OFFSET);
1253 assert(offsets[1] >= VGPU10_MIN_TEXEL_FETCH_OFFSET);
1254 assert(offsets[2] >= VGPU10_MIN_TEXEL_FETCH_OFFSET);
1255 assert(offsets[0] <= VGPU10_MAX_TEXEL_FETCH_OFFSET);
1256 assert(offsets[1] <= VGPU10_MAX_TEXEL_FETCH_OFFSET);
1257 assert(offsets[2] <= VGPU10_MAX_TEXEL_FETCH_OFFSET);
1258
1259 token0.extended = 1;
1260 token1.value = 0;
1261 token1.opcodeType = VGPU10_EXTENDED_OPCODE_SAMPLE_CONTROLS;
1262 token1.offsetU = offsets[0];
1263 token1.offsetV = offsets[1];
1264 token1.offsetW = offsets[2];
1265 }
1266
1267 emit_dword(emit, token0.value);
1268 if (token0.extended) {
1269 emit_dword(emit, token1.value);
1270 }
1271 }
1272
1273
1274 /**
1275 * Emit a DISCARD opcode token.
1276 * If nonzero is set, we'll discard the fragment if the X component is not 0.
1277 * Otherwise, we'll discard the fragment if the X component is 0.
1278 */
1279 static void
1280 emit_discard_opcode(struct svga_shader_emitter_v10 *emit, boolean nonzero)
1281 {
1282 VGPU10OpcodeToken0 opcode0;
1283
1284 opcode0.value = 0;
1285 opcode0.opcodeType = VGPU10_OPCODE_DISCARD;
1286 if (nonzero)
1287 opcode0.testBoolean = VGPU10_INSTRUCTION_TEST_NONZERO;
1288
1289 emit_dword(emit, opcode0.value);
1290 }
1291
1292
1293 /**
1294 * We need to call this before we begin emitting a VGPU10 instruction.
1295 */
1296 static void
1297 begin_emit_instruction(struct svga_shader_emitter_v10 *emit)
1298 {
1299 assert(emit->inst_start_token == 0);
1300 /* Save location of the instruction's VGPU10OpcodeToken0 token.
1301 * Note, we can't save a pointer because it would become invalid if
1302 * we have to realloc the output buffer.
1303 */
1304 emit->inst_start_token = emit_get_num_tokens(emit);
1305 }
1306
1307
1308 /**
1309 * We need to call this after we emit the last token of a VGPU10 instruction.
1310 * This function patches in the opcode token's instructionLength field.
1311 */
1312 static void
1313 end_emit_instruction(struct svga_shader_emitter_v10 *emit)
1314 {
1315 VGPU10OpcodeToken0 *tokens = (VGPU10OpcodeToken0 *) emit->buf;
1316 unsigned inst_length;
1317
1318 assert(emit->inst_start_token > 0);
1319
1320 if (emit->discard_instruction) {
1321 /* Back up the emit->ptr to where this instruction started so
1322 * that we discard the current instruction.
1323 */
1324 emit->ptr = (char *) (tokens + emit->inst_start_token);
1325 }
1326 else {
1327 /* Compute instruction length and patch that into the start of
1328 * the instruction.
1329 */
1330 inst_length = emit_get_num_tokens(emit) - emit->inst_start_token;
1331
1332 assert(inst_length > 0);
1333
1334 tokens[emit->inst_start_token].instructionLength = inst_length;
1335 }
1336
1337 emit->inst_start_token = 0; /* reset to zero for error checking */
1338 emit->discard_instruction = FALSE;
1339 }
1340
1341
1342 /**
1343 * Return index for a free temporary register.
1344 */
1345 static unsigned
1346 get_temp_index(struct svga_shader_emitter_v10 *emit)
1347 {
1348 assert(emit->internal_temp_count < MAX_INTERNAL_TEMPS);
1349 return emit->num_shader_temps + emit->internal_temp_count++;
1350 }
1351
1352
1353 /**
1354 * Release the temporaries which were generated by get_temp_index().
1355 */
1356 static void
1357 free_temp_indexes(struct svga_shader_emitter_v10 *emit)
1358 {
1359 emit->internal_temp_count = 0;
1360 }
1361
1362
1363 /**
1364 * Create a tgsi_full_src_register.
1365 */
1366 static struct tgsi_full_src_register
1367 make_src_reg(unsigned file, unsigned index)
1368 {
1369 struct tgsi_full_src_register reg;
1370
1371 memset(&reg, 0, sizeof(reg));
1372 reg.Register.File = file;
1373 reg.Register.Index = index;
1374 reg.Register.SwizzleX = TGSI_SWIZZLE_X;
1375 reg.Register.SwizzleY = TGSI_SWIZZLE_Y;
1376 reg.Register.SwizzleZ = TGSI_SWIZZLE_Z;
1377 reg.Register.SwizzleW = TGSI_SWIZZLE_W;
1378 return reg;
1379 }
1380
1381
1382 /**
1383 * Create a tgsi_full_src_register for a temporary.
1384 */
1385 static struct tgsi_full_src_register
1386 make_src_temp_reg(unsigned index)
1387 {
1388 return make_src_reg(TGSI_FILE_TEMPORARY, index);
1389 }
1390
1391
1392 /**
1393 * Create a tgsi_full_src_register for a constant.
1394 */
1395 static struct tgsi_full_src_register
1396 make_src_const_reg(unsigned index)
1397 {
1398 return make_src_reg(TGSI_FILE_CONSTANT, index);
1399 }
1400
1401
1402 /**
1403 * Create a tgsi_full_src_register for an immediate constant.
1404 */
1405 static struct tgsi_full_src_register
1406 make_src_immediate_reg(unsigned index)
1407 {
1408 return make_src_reg(TGSI_FILE_IMMEDIATE, index);
1409 }
1410
1411
1412 /**
1413 * Create a tgsi_full_dst_register.
1414 */
1415 static struct tgsi_full_dst_register
1416 make_dst_reg(unsigned file, unsigned index)
1417 {
1418 struct tgsi_full_dst_register reg;
1419
1420 memset(&reg, 0, sizeof(reg));
1421 reg.Register.File = file;
1422 reg.Register.Index = index;
1423 reg.Register.WriteMask = TGSI_WRITEMASK_XYZW;
1424 return reg;
1425 }
1426
1427
1428 /**
1429 * Create a tgsi_full_dst_register for a temporary.
1430 */
1431 static struct tgsi_full_dst_register
1432 make_dst_temp_reg(unsigned index)
1433 {
1434 return make_dst_reg(TGSI_FILE_TEMPORARY, index);
1435 }
1436
1437
1438 /**
1439 * Create a tgsi_full_dst_register for an output.
1440 */
1441 static struct tgsi_full_dst_register
1442 make_dst_output_reg(unsigned index)
1443 {
1444 return make_dst_reg(TGSI_FILE_OUTPUT, index);
1445 }
1446
1447
1448 /**
1449 * Create negated tgsi_full_src_register.
1450 */
1451 static struct tgsi_full_src_register
1452 negate_src(const struct tgsi_full_src_register *reg)
1453 {
1454 struct tgsi_full_src_register neg = *reg;
1455 neg.Register.Negate = !reg->Register.Negate;
1456 return neg;
1457 }
1458
1459 /**
1460 * Create absolute value of a tgsi_full_src_register.
1461 */
1462 static struct tgsi_full_src_register
1463 absolute_src(const struct tgsi_full_src_register *reg)
1464 {
1465 struct tgsi_full_src_register absolute = *reg;
1466 absolute.Register.Absolute = 1;
1467 return absolute;
1468 }
1469
1470
1471 /** Return the named swizzle term from the src register */
1472 static inline unsigned
1473 get_swizzle(const struct tgsi_full_src_register *reg, unsigned term)
1474 {
1475 switch (term) {
1476 case TGSI_SWIZZLE_X:
1477 return reg->Register.SwizzleX;
1478 case TGSI_SWIZZLE_Y:
1479 return reg->Register.SwizzleY;
1480 case TGSI_SWIZZLE_Z:
1481 return reg->Register.SwizzleZ;
1482 case TGSI_SWIZZLE_W:
1483 return reg->Register.SwizzleW;
1484 default:
1485 assert(!"Bad swizzle");
1486 return TGSI_SWIZZLE_X;
1487 }
1488 }
1489
1490
1491 /**
1492 * Create swizzled tgsi_full_src_register.
1493 */
1494 static struct tgsi_full_src_register
1495 swizzle_src(const struct tgsi_full_src_register *reg,
1496 unsigned swizzleX, unsigned swizzleY,
1497 unsigned swizzleZ, unsigned swizzleW)
1498 {
1499 struct tgsi_full_src_register swizzled = *reg;
1500 /* Note: we swizzle the current swizzle */
1501 swizzled.Register.SwizzleX = get_swizzle(reg, swizzleX);
1502 swizzled.Register.SwizzleY = get_swizzle(reg, swizzleY);
1503 swizzled.Register.SwizzleZ = get_swizzle(reg, swizzleZ);
1504 swizzled.Register.SwizzleW = get_swizzle(reg, swizzleW);
1505 return swizzled;
1506 }
1507
1508
1509 /**
1510 * Create swizzled tgsi_full_src_register where all the swizzle
1511 * terms are the same.
1512 */
1513 static struct tgsi_full_src_register
1514 scalar_src(const struct tgsi_full_src_register *reg, unsigned swizzle)
1515 {
1516 struct tgsi_full_src_register swizzled = *reg;
1517 /* Note: we swizzle the current swizzle */
1518 swizzled.Register.SwizzleX =
1519 swizzled.Register.SwizzleY =
1520 swizzled.Register.SwizzleZ =
1521 swizzled.Register.SwizzleW = get_swizzle(reg, swizzle);
1522 return swizzled;
1523 }
1524
1525
1526 /**
1527 * Create new tgsi_full_dst_register with writemask.
1528 * \param mask bitmask of TGSI_WRITEMASK_[XYZW]
1529 */
1530 static struct tgsi_full_dst_register
1531 writemask_dst(const struct tgsi_full_dst_register *reg, unsigned mask)
1532 {
1533 struct tgsi_full_dst_register masked = *reg;
1534 masked.Register.WriteMask = mask;
1535 return masked;
1536 }
1537
1538
1539 /**
1540 * Check if the register's swizzle is XXXX, YYYY, ZZZZ, or WWWW.
1541 */
1542 static boolean
1543 same_swizzle_terms(const struct tgsi_full_src_register *reg)
1544 {
1545 return (reg->Register.SwizzleX == reg->Register.SwizzleY &&
1546 reg->Register.SwizzleY == reg->Register.SwizzleZ &&
1547 reg->Register.SwizzleZ == reg->Register.SwizzleW);
1548 }
1549
1550
1551 /**
1552 * Search the vector for the value 'x' and return its position.
1553 */
1554 static int
1555 find_imm_in_vec4(const union tgsi_immediate_data vec[4],
1556 union tgsi_immediate_data x)
1557 {
1558 unsigned i;
1559 for (i = 0; i < 4; i++) {
1560 if (vec[i].Int == x.Int)
1561 return i;
1562 }
1563 return -1;
1564 }
1565
1566
1567 /**
1568 * Helper used by make_immediate_reg(), make_immediate_reg_4().
1569 */
1570 static int
1571 find_immediate(struct svga_shader_emitter_v10 *emit,
1572 union tgsi_immediate_data x, unsigned startIndex)
1573 {
1574 const unsigned endIndex = emit->num_immediates;
1575 unsigned i;
1576
1577 assert(emit->immediates_emitted);
1578
1579 /* Search immediates for x, y, z, w */
1580 for (i = startIndex; i < endIndex; i++) {
1581 if (x.Int == emit->immediates[i][0].Int ||
1582 x.Int == emit->immediates[i][1].Int ||
1583 x.Int == emit->immediates[i][2].Int ||
1584 x.Int == emit->immediates[i][3].Int) {
1585 return i;
1586 }
1587 }
1588 /* Should never try to use an immediate value that wasn't pre-declared */
1589 assert(!"find_immediate() failed!");
1590 return -1;
1591 }
1592
1593
1594 /**
1595 * Return a tgsi_full_src_register for an immediate/literal
1596 * union tgsi_immediate_data[4] value.
1597 * Note: the values must have been previously declared/allocated in
1598 * emit_pre_helpers(). And, all of x,y,z,w must be located in the same
1599 * vec4 immediate.
1600 */
1601 static struct tgsi_full_src_register
1602 make_immediate_reg_4(struct svga_shader_emitter_v10 *emit,
1603 const union tgsi_immediate_data imm[4])
1604 {
1605 struct tgsi_full_src_register reg;
1606 unsigned i;
1607
1608 for (i = 0; i < emit->num_common_immediates; i++) {
1609 /* search for first component value */
1610 int immpos = find_immediate(emit, imm[0], i);
1611 int x, y, z, w;
1612
1613 assert(immpos >= 0);
1614
1615 /* find remaining components within the immediate vector */
1616 x = find_imm_in_vec4(emit->immediates[immpos], imm[0]);
1617 y = find_imm_in_vec4(emit->immediates[immpos], imm[1]);
1618 z = find_imm_in_vec4(emit->immediates[immpos], imm[2]);
1619 w = find_imm_in_vec4(emit->immediates[immpos], imm[3]);
1620
1621 if (x >=0 && y >= 0 && z >= 0 && w >= 0) {
1622 /* found them all */
1623 memset(&reg, 0, sizeof(reg));
1624 reg.Register.File = TGSI_FILE_IMMEDIATE;
1625 reg.Register.Index = immpos;
1626 reg.Register.SwizzleX = x;
1627 reg.Register.SwizzleY = y;
1628 reg.Register.SwizzleZ = z;
1629 reg.Register.SwizzleW = w;
1630 return reg;
1631 }
1632 /* else, keep searching */
1633 }
1634
1635 assert(!"Failed to find immediate register!");
1636
1637 /* Just return IMM[0].xxxx */
1638 memset(&reg, 0, sizeof(reg));
1639 reg.Register.File = TGSI_FILE_IMMEDIATE;
1640 return reg;
1641 }
1642
1643
1644 /**
1645 * Return a tgsi_full_src_register for an immediate/literal
1646 * union tgsi_immediate_data value of the form {value, value, value, value}.
1647 * \sa make_immediate_reg_4() regarding allowed values.
1648 */
1649 static struct tgsi_full_src_register
1650 make_immediate_reg(struct svga_shader_emitter_v10 *emit,
1651 union tgsi_immediate_data value)
1652 {
1653 struct tgsi_full_src_register reg;
1654 int immpos = find_immediate(emit, value, 0);
1655
1656 assert(immpos >= 0);
1657
1658 memset(&reg, 0, sizeof(reg));
1659 reg.Register.File = TGSI_FILE_IMMEDIATE;
1660 reg.Register.Index = immpos;
1661 reg.Register.SwizzleX =
1662 reg.Register.SwizzleY =
1663 reg.Register.SwizzleZ =
1664 reg.Register.SwizzleW = find_imm_in_vec4(emit->immediates[immpos], value);
1665
1666 return reg;
1667 }
1668
1669
1670 /**
1671 * Return a tgsi_full_src_register for an immediate/literal float[4] value.
1672 * \sa make_immediate_reg_4() regarding allowed values.
1673 */
1674 static struct tgsi_full_src_register
1675 make_immediate_reg_float4(struct svga_shader_emitter_v10 *emit,
1676 float x, float y, float z, float w)
1677 {
1678 union tgsi_immediate_data imm[4];
1679 imm[0].Float = x;
1680 imm[1].Float = y;
1681 imm[2].Float = z;
1682 imm[3].Float = w;
1683 return make_immediate_reg_4(emit, imm);
1684 }
1685
1686
1687 /**
1688 * Return a tgsi_full_src_register for an immediate/literal float value
1689 * of the form {value, value, value, value}.
1690 * \sa make_immediate_reg_4() regarding allowed values.
1691 */
1692 static struct tgsi_full_src_register
1693 make_immediate_reg_float(struct svga_shader_emitter_v10 *emit, float value)
1694 {
1695 union tgsi_immediate_data imm;
1696 imm.Float = value;
1697 return make_immediate_reg(emit, imm);
1698 }
1699
1700
1701 /**
1702 * Return a tgsi_full_src_register for an immediate/literal int[4] vector.
1703 */
1704 static struct tgsi_full_src_register
1705 make_immediate_reg_int4(struct svga_shader_emitter_v10 *emit,
1706 int x, int y, int z, int w)
1707 {
1708 union tgsi_immediate_data imm[4];
1709 imm[0].Int = x;
1710 imm[1].Int = y;
1711 imm[2].Int = z;
1712 imm[3].Int = w;
1713 return make_immediate_reg_4(emit, imm);
1714 }
1715
1716
1717 /**
1718 * Return a tgsi_full_src_register for an immediate/literal int value
1719 * of the form {value, value, value, value}.
1720 * \sa make_immediate_reg_4() regarding allowed values.
1721 */
1722 static struct tgsi_full_src_register
1723 make_immediate_reg_int(struct svga_shader_emitter_v10 *emit, int value)
1724 {
1725 union tgsi_immediate_data imm;
1726 imm.Int = value;
1727 return make_immediate_reg(emit, imm);
1728 }
1729
1730
1731 /**
1732 * Allocate space for a union tgsi_immediate_data[4] immediate.
1733 * \return the index/position of the immediate.
1734 */
1735 static unsigned
1736 alloc_immediate_4(struct svga_shader_emitter_v10 *emit,
1737 const union tgsi_immediate_data imm[4])
1738 {
1739 unsigned n = emit->num_immediates++;
1740 assert(!emit->immediates_emitted);
1741 assert(n < ARRAY_SIZE(emit->immediates));
1742 emit->immediates[n][0] = imm[0];
1743 emit->immediates[n][1] = imm[1];
1744 emit->immediates[n][2] = imm[2];
1745 emit->immediates[n][3] = imm[3];
1746 return n;
1747 }
1748
1749
1750 /**
1751 * Allocate space for a float[4] immediate.
1752 * \return the index/position of the immediate.
1753 */
1754 static unsigned
1755 alloc_immediate_float4(struct svga_shader_emitter_v10 *emit,
1756 float x, float y, float z, float w)
1757 {
1758 union tgsi_immediate_data imm[4];
1759 imm[0].Float = x;
1760 imm[1].Float = y;
1761 imm[2].Float = z;
1762 imm[3].Float = w;
1763 return alloc_immediate_4(emit, imm);
1764 }
1765
1766
1767 /**
1768 * Allocate space for an int[4] immediate.
1769 * \return the index/position of the immediate.
1770 */
1771 static unsigned
1772 alloc_immediate_int4(struct svga_shader_emitter_v10 *emit,
1773 int x, int y, int z, int w)
1774 {
1775 union tgsi_immediate_data imm[4];
1776 imm[0].Int = x;
1777 imm[1].Int = y;
1778 imm[2].Int = z;
1779 imm[3].Int = w;
1780 return alloc_immediate_4(emit, imm);
1781 }
1782
1783
1784 /**
1785 * Allocate a shader input to store a system value.
1786 */
1787 static unsigned
1788 alloc_system_value_index(struct svga_shader_emitter_v10 *emit, unsigned index)
1789 {
1790 const unsigned n = emit->info.file_max[TGSI_FILE_INPUT] + 1 + index;
1791 assert(index < ARRAY_SIZE(emit->system_value_indexes));
1792 emit->system_value_indexes[index] = n;
1793 return n;
1794 }
1795
1796
1797 /**
1798 * Translate a TGSI immediate value (union tgsi_immediate_data[4]) to VGPU10.
1799 */
1800 static boolean
1801 emit_vgpu10_immediate(struct svga_shader_emitter_v10 *emit,
1802 const struct tgsi_full_immediate *imm)
1803 {
1804 /* We don't actually emit any code here. We just save the
1805 * immediate values and emit them later.
1806 */
1807 alloc_immediate_4(emit, imm->u);
1808 return TRUE;
1809 }
1810
1811
1812 /**
1813 * Emit a VGPU10_CUSTOMDATA_DCL_IMMEDIATE_CONSTANT_BUFFER block
1814 * containing all the immediate values previously allocated
1815 * with alloc_immediate_4().
1816 */
1817 static boolean
1818 emit_vgpu10_immediates_block(struct svga_shader_emitter_v10 *emit)
1819 {
1820 VGPU10OpcodeToken0 token;
1821
1822 assert(!emit->immediates_emitted);
1823
1824 token.value = 0;
1825 token.opcodeType = VGPU10_OPCODE_CUSTOMDATA;
1826 token.customDataClass = VGPU10_CUSTOMDATA_DCL_IMMEDIATE_CONSTANT_BUFFER;
1827
1828 /* Note: no begin/end_emit_instruction() calls */
1829 emit_dword(emit, token.value);
1830 emit_dword(emit, 2 + 4 * emit->num_immediates);
1831 emit_dwords(emit, (unsigned *) emit->immediates, 4 * emit->num_immediates);
1832
1833 emit->immediates_emitted = TRUE;
1834
1835 return TRUE;
1836 }
1837
1838
1839 /**
1840 * Translate a fragment shader's TGSI_INTERPOLATE_x mode to a vgpu10
1841 * interpolation mode.
1842 * \return a VGPU10_INTERPOLATION_x value
1843 */
1844 static unsigned
1845 translate_interpolation(const struct svga_shader_emitter_v10 *emit,
1846 unsigned interp, unsigned interpolate_loc)
1847 {
1848 if (interp == TGSI_INTERPOLATE_COLOR) {
1849 interp = emit->key.fs.flatshade ?
1850 TGSI_INTERPOLATE_CONSTANT : TGSI_INTERPOLATE_PERSPECTIVE;
1851 }
1852
1853 switch (interp) {
1854 case TGSI_INTERPOLATE_CONSTANT:
1855 return VGPU10_INTERPOLATION_CONSTANT;
1856 case TGSI_INTERPOLATE_LINEAR:
1857 return interpolate_loc == TGSI_INTERPOLATE_LOC_CENTROID ?
1858 VGPU10_INTERPOLATION_LINEAR_NOPERSPECTIVE_CENTROID :
1859 VGPU10_INTERPOLATION_LINEAR_NOPERSPECTIVE;
1860 case TGSI_INTERPOLATE_PERSPECTIVE:
1861 return interpolate_loc == TGSI_INTERPOLATE_LOC_CENTROID ?
1862 VGPU10_INTERPOLATION_LINEAR_CENTROID :
1863 VGPU10_INTERPOLATION_LINEAR;
1864 default:
1865 assert(!"Unexpected interpolation mode");
1866 return VGPU10_INTERPOLATION_CONSTANT;
1867 }
1868 }
1869
1870
1871 /**
1872 * Translate a TGSI property to VGPU10.
1873 * Don't emit any instructions yet, only need to gather the primitive property information.
1874 * The output primitive topology might be changed later. The final property instructions
1875 * will be emitted as part of the pre-helper code.
1876 */
1877 static boolean
1878 emit_vgpu10_property(struct svga_shader_emitter_v10 *emit,
1879 const struct tgsi_full_property *prop)
1880 {
1881 static const VGPU10_PRIMITIVE primType[] = {
1882 VGPU10_PRIMITIVE_POINT, /* PIPE_PRIM_POINTS */
1883 VGPU10_PRIMITIVE_LINE, /* PIPE_PRIM_LINES */
1884 VGPU10_PRIMITIVE_LINE, /* PIPE_PRIM_LINE_LOOP */
1885 VGPU10_PRIMITIVE_LINE, /* PIPE_PRIM_LINE_STRIP */
1886 VGPU10_PRIMITIVE_TRIANGLE, /* PIPE_PRIM_TRIANGLES */
1887 VGPU10_PRIMITIVE_TRIANGLE, /* PIPE_PRIM_TRIANGLE_STRIP */
1888 VGPU10_PRIMITIVE_TRIANGLE, /* PIPE_PRIM_TRIANGLE_FAN */
1889 VGPU10_PRIMITIVE_UNDEFINED, /* PIPE_PRIM_QUADS */
1890 VGPU10_PRIMITIVE_UNDEFINED, /* PIPE_PRIM_QUAD_STRIP */
1891 VGPU10_PRIMITIVE_UNDEFINED, /* PIPE_PRIM_POLYGON */
1892 VGPU10_PRIMITIVE_LINE_ADJ, /* PIPE_PRIM_LINES_ADJACENCY */
1893 VGPU10_PRIMITIVE_LINE_ADJ, /* PIPE_PRIM_LINE_STRIP_ADJACENCY */
1894 VGPU10_PRIMITIVE_TRIANGLE_ADJ, /* PIPE_PRIM_TRIANGLES_ADJACENCY */
1895 VGPU10_PRIMITIVE_TRIANGLE_ADJ /* PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY */
1896 };
1897
1898 static const VGPU10_PRIMITIVE_TOPOLOGY primTopology[] = {
1899 VGPU10_PRIMITIVE_TOPOLOGY_POINTLIST, /* PIPE_PRIM_POINTS */
1900 VGPU10_PRIMITIVE_TOPOLOGY_LINELIST, /* PIPE_PRIM_LINES */
1901 VGPU10_PRIMITIVE_TOPOLOGY_LINELIST, /* PIPE_PRIM_LINE_LOOP */
1902 VGPU10_PRIMITIVE_TOPOLOGY_LINESTRIP, /* PIPE_PRIM_LINE_STRIP */
1903 VGPU10_PRIMITIVE_TOPOLOGY_TRIANGLELIST, /* PIPE_PRIM_TRIANGLES */
1904 VGPU10_PRIMITIVE_TOPOLOGY_TRIANGLESTRIP, /* PIPE_PRIM_TRIANGLE_STRIP */
1905 VGPU10_PRIMITIVE_TOPOLOGY_TRIANGLESTRIP, /* PIPE_PRIM_TRIANGLE_FAN */
1906 VGPU10_PRIMITIVE_TOPOLOGY_UNDEFINED, /* PIPE_PRIM_QUADS */
1907 VGPU10_PRIMITIVE_TOPOLOGY_UNDEFINED, /* PIPE_PRIM_QUAD_STRIP */
1908 VGPU10_PRIMITIVE_TOPOLOGY_UNDEFINED, /* PIPE_PRIM_POLYGON */
1909 VGPU10_PRIMITIVE_TOPOLOGY_LINELIST_ADJ, /* PIPE_PRIM_LINES_ADJACENCY */
1910 VGPU10_PRIMITIVE_TOPOLOGY_LINELIST_ADJ, /* PIPE_PRIM_LINE_STRIP_ADJACENCY */
1911 VGPU10_PRIMITIVE_TOPOLOGY_TRIANGLELIST_ADJ, /* PIPE_PRIM_TRIANGLES_ADJACENCY */
1912 VGPU10_PRIMITIVE_TOPOLOGY_TRIANGLESTRIP_ADJ /* PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY */
1913 };
1914
1915 static const unsigned inputArraySize[] = {
1916 0, /* VGPU10_PRIMITIVE_UNDEFINED */
1917 1, /* VGPU10_PRIMITIVE_POINT */
1918 2, /* VGPU10_PRIMITIVE_LINE */
1919 3, /* VGPU10_PRIMITIVE_TRIANGLE */
1920 0,
1921 0,
1922 4, /* VGPU10_PRIMITIVE_LINE_ADJ */
1923 6 /* VGPU10_PRIMITIVE_TRIANGLE_ADJ */
1924 };
1925
1926 switch (prop->Property.PropertyName) {
1927 case TGSI_PROPERTY_GS_INPUT_PRIM:
1928 assert(prop->u[0].Data < ARRAY_SIZE(primType));
1929 emit->gs.prim_type = primType[prop->u[0].Data];
1930 assert(emit->gs.prim_type != VGPU10_PRIMITIVE_UNDEFINED);
1931 emit->gs.input_size = inputArraySize[emit->gs.prim_type];
1932 break;
1933
1934 case TGSI_PROPERTY_GS_OUTPUT_PRIM:
1935 assert(prop->u[0].Data < ARRAY_SIZE(primTopology));
1936 emit->gs.prim_topology = primTopology[prop->u[0].Data];
1937 assert(emit->gs.prim_topology != VGPU10_PRIMITIVE_TOPOLOGY_UNDEFINED);
1938 break;
1939
1940 case TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES:
1941 emit->gs.max_out_vertices = prop->u[0].Data;
1942 break;
1943
1944 default:
1945 break;
1946 }
1947
1948 return TRUE;
1949 }
1950
1951
1952 static void
1953 emit_property_instruction(struct svga_shader_emitter_v10 *emit,
1954 VGPU10OpcodeToken0 opcode0, unsigned nData,
1955 unsigned data)
1956 {
1957 begin_emit_instruction(emit);
1958 emit_dword(emit, opcode0.value);
1959 if (nData)
1960 emit_dword(emit, data);
1961 end_emit_instruction(emit);
1962 }
1963
1964
1965 /**
1966 * Emit property instructions
1967 */
1968 static void
1969 emit_property_instructions(struct svga_shader_emitter_v10 *emit)
1970 {
1971 VGPU10OpcodeToken0 opcode0;
1972
1973 assert(emit->unit == PIPE_SHADER_GEOMETRY);
1974
1975 /* emit input primitive type declaration */
1976 opcode0.value = 0;
1977 opcode0.opcodeType = VGPU10_OPCODE_DCL_GS_INPUT_PRIMITIVE;
1978 opcode0.primitive = emit->gs.prim_type;
1979 emit_property_instruction(emit, opcode0, 0, 0);
1980
1981 /* emit output primitive topology declaration */
1982 opcode0.value = 0;
1983 opcode0.opcodeType = VGPU10_OPCODE_DCL_GS_OUTPUT_PRIMITIVE_TOPOLOGY;
1984 opcode0.primitiveTopology = emit->gs.prim_topology;
1985 emit_property_instruction(emit, opcode0, 0, 0);
1986
1987 /* emit max output vertices */
1988 opcode0.value = 0;
1989 opcode0.opcodeType = VGPU10_OPCODE_DCL_MAX_OUTPUT_VERTEX_COUNT;
1990 emit_property_instruction(emit, opcode0, 1, emit->gs.max_out_vertices);
1991 }
1992
1993
1994 /**
1995 * Emit a vgpu10 declaration "instruction".
1996 * \param index the register index
1997 * \param size array size of the operand. In most cases, it is 1,
1998 * but for inputs to geometry shader, the array size varies
1999 * depending on the primitive type.
2000 */
2001 static void
2002 emit_decl_instruction(struct svga_shader_emitter_v10 *emit,
2003 VGPU10OpcodeToken0 opcode0,
2004 VGPU10OperandToken0 operand0,
2005 VGPU10NameToken name_token,
2006 unsigned index, unsigned size)
2007 {
2008 assert(opcode0.opcodeType);
2009 assert(operand0.mask);
2010
2011 begin_emit_instruction(emit);
2012 emit_dword(emit, opcode0.value);
2013
2014 emit_dword(emit, operand0.value);
2015
2016 if (operand0.indexDimension == VGPU10_OPERAND_INDEX_1D) {
2017 /* Next token is the index of the register to declare */
2018 emit_dword(emit, index);
2019 }
2020 else if (operand0.indexDimension >= VGPU10_OPERAND_INDEX_2D) {
2021 /* Next token is the size of the register */
2022 emit_dword(emit, size);
2023
2024 /* Followed by the index of the register */
2025 emit_dword(emit, index);
2026 }
2027
2028 if (name_token.value) {
2029 emit_dword(emit, name_token.value);
2030 }
2031
2032 end_emit_instruction(emit);
2033 }
2034
2035
2036 /**
2037 * Emit the declaration for a shader input.
2038 * \param opcodeType opcode type, one of VGPU10_OPCODE_DCL_INPUTx
2039 * \param operandType operand type, one of VGPU10_OPERAND_TYPE_INPUT_x
2040 * \param dim index dimension
2041 * \param index the input register index
2042 * \param size array size of the operand. In most cases, it is 1,
2043 * but for inputs to geometry shader, the array size varies
2044 * depending on the primitive type.
2045 * \param name one of VGPU10_NAME_x
2046 * \parma numComp number of components
2047 * \param selMode component selection mode
2048 * \param usageMask bitfield of VGPU10_OPERAND_4_COMPONENT_MASK_x values
2049 * \param interpMode interpolation mode
2050 */
2051 static void
2052 emit_input_declaration(struct svga_shader_emitter_v10 *emit,
2053 unsigned opcodeType, unsigned operandType,
2054 unsigned dim, unsigned index, unsigned size,
2055 unsigned name, unsigned numComp,
2056 unsigned selMode, unsigned usageMask,
2057 unsigned interpMode)
2058 {
2059 VGPU10OpcodeToken0 opcode0;
2060 VGPU10OperandToken0 operand0;
2061 VGPU10NameToken name_token;
2062
2063 assert(usageMask <= VGPU10_OPERAND_4_COMPONENT_MASK_ALL);
2064 assert(opcodeType == VGPU10_OPCODE_DCL_INPUT ||
2065 opcodeType == VGPU10_OPCODE_DCL_INPUT_SIV ||
2066 opcodeType == VGPU10_OPCODE_DCL_INPUT_PS ||
2067 opcodeType == VGPU10_OPCODE_DCL_INPUT_PS_SGV);
2068 assert(operandType == VGPU10_OPERAND_TYPE_INPUT ||
2069 operandType == VGPU10_OPERAND_TYPE_INPUT_PRIMITIVEID);
2070 assert(numComp <= VGPU10_OPERAND_4_COMPONENT);
2071 assert(selMode <= VGPU10_OPERAND_4_COMPONENT_MASK_MODE);
2072 assert(dim <= VGPU10_OPERAND_INDEX_3D);
2073 assert(name == VGPU10_NAME_UNDEFINED ||
2074 name == VGPU10_NAME_POSITION ||
2075 name == VGPU10_NAME_INSTANCE_ID ||
2076 name == VGPU10_NAME_VERTEX_ID ||
2077 name == VGPU10_NAME_PRIMITIVE_ID ||
2078 name == VGPU10_NAME_IS_FRONT_FACE);
2079 assert(interpMode == VGPU10_INTERPOLATION_UNDEFINED ||
2080 interpMode == VGPU10_INTERPOLATION_CONSTANT ||
2081 interpMode == VGPU10_INTERPOLATION_LINEAR ||
2082 interpMode == VGPU10_INTERPOLATION_LINEAR_CENTROID ||
2083 interpMode == VGPU10_INTERPOLATION_LINEAR_NOPERSPECTIVE ||
2084 interpMode == VGPU10_INTERPOLATION_LINEAR_NOPERSPECTIVE_CENTROID);
2085
2086 check_register_index(emit, opcodeType, index);
2087
2088 opcode0.value = operand0.value = name_token.value = 0;
2089
2090 opcode0.opcodeType = opcodeType;
2091 opcode0.interpolationMode = interpMode;
2092
2093 operand0.operandType = operandType;
2094 operand0.numComponents = numComp;
2095 operand0.selectionMode = selMode;
2096 operand0.mask = usageMask;
2097 operand0.indexDimension = dim;
2098 operand0.index0Representation = VGPU10_OPERAND_INDEX_IMMEDIATE32;
2099 if (dim == VGPU10_OPERAND_INDEX_2D)
2100 operand0.index1Representation = VGPU10_OPERAND_INDEX_IMMEDIATE32;
2101
2102 name_token.name = name;
2103
2104 emit_decl_instruction(emit, opcode0, operand0, name_token, index, size);
2105 }
2106
2107
2108 /**
2109 * Emit the declaration for a shader output.
2110 * \param type one of VGPU10_OPCODE_DCL_OUTPUTx
2111 * \param index the output register index
2112 * \param name one of VGPU10_NAME_x
2113 * \param usageMask bitfield of VGPU10_OPERAND_4_COMPONENT_MASK_x values
2114 */
2115 static void
2116 emit_output_declaration(struct svga_shader_emitter_v10 *emit,
2117 unsigned type, unsigned index,
2118 unsigned name, unsigned usageMask)
2119 {
2120 VGPU10OpcodeToken0 opcode0;
2121 VGPU10OperandToken0 operand0;
2122 VGPU10NameToken name_token;
2123
2124 assert(usageMask <= VGPU10_OPERAND_4_COMPONENT_MASK_ALL);
2125 assert(type == VGPU10_OPCODE_DCL_OUTPUT ||
2126 type == VGPU10_OPCODE_DCL_OUTPUT_SGV ||
2127 type == VGPU10_OPCODE_DCL_OUTPUT_SIV);
2128 assert(name == VGPU10_NAME_UNDEFINED ||
2129 name == VGPU10_NAME_POSITION ||
2130 name == VGPU10_NAME_PRIMITIVE_ID ||
2131 name == VGPU10_NAME_RENDER_TARGET_ARRAY_INDEX ||
2132 name == VGPU10_NAME_CLIP_DISTANCE);
2133
2134 check_register_index(emit, type, index);
2135
2136 opcode0.value = operand0.value = name_token.value = 0;
2137
2138 opcode0.opcodeType = type;
2139 operand0.operandType = VGPU10_OPERAND_TYPE_OUTPUT;
2140 operand0.numComponents = VGPU10_OPERAND_4_COMPONENT;
2141 operand0.selectionMode = VGPU10_OPERAND_4_COMPONENT_MASK_MODE;
2142 operand0.mask = usageMask;
2143 operand0.indexDimension = VGPU10_OPERAND_INDEX_1D;
2144 operand0.index0Representation = VGPU10_OPERAND_INDEX_IMMEDIATE32;
2145
2146 name_token.name = name;
2147
2148 emit_decl_instruction(emit, opcode0, operand0, name_token, index, 1);
2149 }
2150
2151
2152 /**
2153 * Emit the declaration for the fragment depth output.
2154 */
2155 static void
2156 emit_fragdepth_output_declaration(struct svga_shader_emitter_v10 *emit)
2157 {
2158 VGPU10OpcodeToken0 opcode0;
2159 VGPU10OperandToken0 operand0;
2160 VGPU10NameToken name_token;
2161
2162 assert(emit->unit == PIPE_SHADER_FRAGMENT);
2163
2164 opcode0.value = operand0.value = name_token.value = 0;
2165
2166 opcode0.opcodeType = VGPU10_OPCODE_DCL_OUTPUT;
2167 operand0.operandType = VGPU10_OPERAND_TYPE_OUTPUT_DEPTH;
2168 operand0.numComponents = VGPU10_OPERAND_1_COMPONENT;
2169 operand0.indexDimension = VGPU10_OPERAND_INDEX_0D;
2170 operand0.mask = VGPU10_OPERAND_4_COMPONENT_MASK_ALL;
2171
2172 emit_decl_instruction(emit, opcode0, operand0, name_token, 0, 1);
2173 }
2174
2175
2176 /**
2177 * Emit the declaration for a system value input/output.
2178 */
2179 static void
2180 emit_system_value_declaration(struct svga_shader_emitter_v10 *emit,
2181 unsigned semantic_name, unsigned index)
2182 {
2183 switch (semantic_name) {
2184 case TGSI_SEMANTIC_INSTANCEID:
2185 index = alloc_system_value_index(emit, index);
2186 emit_input_declaration(emit, VGPU10_OPCODE_DCL_INPUT_SIV,
2187 VGPU10_OPERAND_TYPE_INPUT,
2188 VGPU10_OPERAND_INDEX_1D,
2189 index, 1,
2190 VGPU10_NAME_INSTANCE_ID,
2191 VGPU10_OPERAND_4_COMPONENT,
2192 VGPU10_OPERAND_4_COMPONENT_MASK_MODE,
2193 VGPU10_OPERAND_4_COMPONENT_MASK_X,
2194 VGPU10_INTERPOLATION_UNDEFINED);
2195 break;
2196 case TGSI_SEMANTIC_VERTEXID:
2197 index = alloc_system_value_index(emit, index);
2198 emit_input_declaration(emit, VGPU10_OPCODE_DCL_INPUT_SIV,
2199 VGPU10_OPERAND_TYPE_INPUT,
2200 VGPU10_OPERAND_INDEX_1D,
2201 index, 1,
2202 VGPU10_NAME_VERTEX_ID,
2203 VGPU10_OPERAND_4_COMPONENT,
2204 VGPU10_OPERAND_4_COMPONENT_MASK_MODE,
2205 VGPU10_OPERAND_4_COMPONENT_MASK_X,
2206 VGPU10_INTERPOLATION_UNDEFINED);
2207 break;
2208 default:
2209 ; /* XXX */
2210 }
2211 }
2212
2213 /**
2214 * Translate a TGSI declaration to VGPU10.
2215 */
2216 static boolean
2217 emit_vgpu10_declaration(struct svga_shader_emitter_v10 *emit,
2218 const struct tgsi_full_declaration *decl)
2219 {
2220 switch (decl->Declaration.File) {
2221 case TGSI_FILE_INPUT:
2222 /* do nothing - see emit_input_declarations() */
2223 return TRUE;
2224
2225 case TGSI_FILE_OUTPUT:
2226 assert(decl->Range.First == decl->Range.Last);
2227 emit->output_usage_mask[decl->Range.First] = decl->Declaration.UsageMask;
2228 return TRUE;
2229
2230 case TGSI_FILE_TEMPORARY:
2231 /* Don't declare the temps here. Just keep track of how many
2232 * and emit the declaration later.
2233 */
2234 if (decl->Declaration.Array) {
2235 /* Indexed temporary array. Save the start index of the array
2236 * and the size of the array.
2237 */
2238 const unsigned arrayID = MIN2(decl->Array.ArrayID, MAX_TEMP_ARRAYS);
2239 unsigned i;
2240
2241 assert(arrayID < ARRAY_SIZE(emit->temp_arrays));
2242
2243 /* Save this array so we can emit the declaration for it later */
2244 emit->temp_arrays[arrayID].start = decl->Range.First;
2245 emit->temp_arrays[arrayID].size =
2246 decl->Range.Last - decl->Range.First + 1;
2247
2248 emit->num_temp_arrays = MAX2(emit->num_temp_arrays, arrayID + 1);
2249 assert(emit->num_temp_arrays <= MAX_TEMP_ARRAYS);
2250 emit->num_temp_arrays = MIN2(emit->num_temp_arrays, MAX_TEMP_ARRAYS);
2251
2252 /* Fill in the temp_map entries for this array */
2253 for (i = decl->Range.First; i <= decl->Range.Last; i++) {
2254 emit->temp_map[i].arrayId = arrayID;
2255 emit->temp_map[i].index = i - decl->Range.First;
2256 }
2257 }
2258
2259 /* for all temps, indexed or not, keep track of highest index */
2260 emit->num_shader_temps = MAX2(emit->num_shader_temps,
2261 decl->Range.Last + 1);
2262 return TRUE;
2263
2264 case TGSI_FILE_CONSTANT:
2265 /* Don't declare constants here. Just keep track and emit later. */
2266 {
2267 unsigned constbuf = 0, num_consts;
2268 if (decl->Declaration.Dimension) {
2269 constbuf = decl->Dim.Index2D;
2270 }
2271 /* We throw an assertion here when, in fact, the shader should never
2272 * have linked due to constbuf index out of bounds, so we shouldn't
2273 * have reached here.
2274 */
2275 assert(constbuf < ARRAY_SIZE(emit->num_shader_consts));
2276
2277 num_consts = MAX2(emit->num_shader_consts[constbuf],
2278 decl->Range.Last + 1);
2279
2280 if (num_consts > VGPU10_MAX_CONSTANT_BUFFER_ELEMENT_COUNT) {
2281 debug_printf("Warning: constant buffer is declared to size [%u]"
2282 " but [%u] is the limit.\n",
2283 num_consts,
2284 VGPU10_MAX_CONSTANT_BUFFER_ELEMENT_COUNT);
2285 }
2286 /* The linker doesn't enforce the max UBO size so we clamp here */
2287 emit->num_shader_consts[constbuf] =
2288 MIN2(num_consts, VGPU10_MAX_CONSTANT_BUFFER_ELEMENT_COUNT);
2289 }
2290 return TRUE;
2291
2292 case TGSI_FILE_IMMEDIATE:
2293 assert(!"TGSI_FILE_IMMEDIATE not handled yet!");
2294 return FALSE;
2295
2296 case TGSI_FILE_SYSTEM_VALUE:
2297 emit_system_value_declaration(emit, decl->Semantic.Name,
2298 decl->Range.First);
2299 return TRUE;
2300
2301 case TGSI_FILE_SAMPLER:
2302 /* Don't declare samplers here. Just keep track and emit later. */
2303 emit->num_samplers = MAX2(emit->num_samplers, decl->Range.Last + 1);
2304 return TRUE;
2305
2306 #if 0
2307 case TGSI_FILE_RESOURCE:
2308 /*opcode0.opcodeType = VGPU10_OPCODE_DCL_RESOURCE;*/
2309 /* XXX more, VGPU10_RETURN_TYPE_FLOAT */
2310 assert(!"TGSI_FILE_RESOURCE not handled yet");
2311 return FALSE;
2312 #endif
2313
2314 case TGSI_FILE_ADDRESS:
2315 emit->num_address_regs = MAX2(emit->num_address_regs,
2316 decl->Range.Last + 1);
2317 return TRUE;
2318
2319 case TGSI_FILE_SAMPLER_VIEW:
2320 {
2321 unsigned unit = decl->Range.First;
2322 assert(decl->Range.First == decl->Range.Last);
2323 emit->sampler_target[unit] = decl->SamplerView.Resource;
2324 /* Note: we can ignore YZW return types for now */
2325 emit->sampler_return_type[unit] = decl->SamplerView.ReturnTypeX;
2326 }
2327 return TRUE;
2328
2329 default:
2330 assert(!"Unexpected type of declaration");
2331 return FALSE;
2332 }
2333 }
2334
2335
2336
2337 /**
2338 * Emit all input declarations.
2339 */
2340 static boolean
2341 emit_input_declarations(struct svga_shader_emitter_v10 *emit)
2342 {
2343 unsigned i;
2344
2345 if (emit->unit == PIPE_SHADER_FRAGMENT) {
2346
2347 for (i = 0; i < emit->linkage.num_inputs; i++) {
2348 unsigned semantic_name = emit->info.input_semantic_name[i];
2349 unsigned usage_mask = emit->info.input_usage_mask[i];
2350 unsigned index = emit->linkage.input_map[i];
2351 unsigned type, interpolationMode, name;
2352
2353 if (usage_mask == 0)
2354 continue; /* register is not actually used */
2355
2356 if (semantic_name == TGSI_SEMANTIC_POSITION) {
2357 /* fragment position input */
2358 type = VGPU10_OPCODE_DCL_INPUT_PS_SGV;
2359 interpolationMode = VGPU10_INTERPOLATION_LINEAR;
2360 name = VGPU10_NAME_POSITION;
2361 if (usage_mask & TGSI_WRITEMASK_W) {
2362 /* we need to replace use of 'w' with '1/w' */
2363 emit->fs.fragcoord_input_index = i;
2364 }
2365 }
2366 else if (semantic_name == TGSI_SEMANTIC_FACE) {
2367 /* fragment front-facing input */
2368 type = VGPU10_OPCODE_DCL_INPUT_PS_SGV;
2369 interpolationMode = VGPU10_INTERPOLATION_CONSTANT;
2370 name = VGPU10_NAME_IS_FRONT_FACE;
2371 emit->fs.face_input_index = i;
2372 }
2373 else if (semantic_name == TGSI_SEMANTIC_PRIMID) {
2374 /* primitive ID */
2375 type = VGPU10_OPCODE_DCL_INPUT_PS_SGV;
2376 interpolationMode = VGPU10_INTERPOLATION_CONSTANT;
2377 name = VGPU10_NAME_PRIMITIVE_ID;
2378 }
2379 else {
2380 /* general fragment input */
2381 type = VGPU10_OPCODE_DCL_INPUT_PS;
2382 interpolationMode =
2383 translate_interpolation(emit,
2384 emit->info.input_interpolate[i],
2385 emit->info.input_interpolate_loc[i]);
2386
2387 /* keeps track if flat interpolation mode is being used */
2388 emit->uses_flat_interp = emit->uses_flat_interp ||
2389 (interpolationMode == VGPU10_INTERPOLATION_CONSTANT);
2390
2391 name = VGPU10_NAME_UNDEFINED;
2392 }
2393
2394 emit_input_declaration(emit, type,
2395 VGPU10_OPERAND_TYPE_INPUT,
2396 VGPU10_OPERAND_INDEX_1D, index, 1,
2397 name,
2398 VGPU10_OPERAND_4_COMPONENT,
2399 VGPU10_OPERAND_4_COMPONENT_MASK_MODE,
2400 VGPU10_OPERAND_4_COMPONENT_MASK_ALL,
2401 interpolationMode);
2402 }
2403 }
2404 else if (emit->unit == PIPE_SHADER_GEOMETRY) {
2405
2406 for (i = 0; i < emit->info.num_inputs; i++) {
2407 unsigned semantic_name = emit->info.input_semantic_name[i];
2408 unsigned usage_mask = emit->info.input_usage_mask[i];
2409 unsigned index = emit->linkage.input_map[i];
2410 unsigned opcodeType, operandType;
2411 unsigned numComp, selMode;
2412 unsigned name;
2413 unsigned dim;
2414
2415 if (usage_mask == 0)
2416 continue; /* register is not actually used */
2417
2418 opcodeType = VGPU10_OPCODE_DCL_INPUT;
2419 operandType = VGPU10_OPERAND_TYPE_INPUT;
2420 numComp = VGPU10_OPERAND_4_COMPONENT;
2421 selMode = VGPU10_OPERAND_4_COMPONENT_MASK_MODE;
2422 name = VGPU10_NAME_UNDEFINED;
2423
2424 /* all geometry shader inputs are two dimensional except gl_PrimitiveID */
2425 dim = VGPU10_OPERAND_INDEX_2D;
2426
2427 if (semantic_name == TGSI_SEMANTIC_PRIMID) {
2428 /* Primitive ID */
2429 operandType = VGPU10_OPERAND_TYPE_INPUT_PRIMITIVEID;
2430 dim = VGPU10_OPERAND_INDEX_0D;
2431 numComp = VGPU10_OPERAND_0_COMPONENT;
2432 selMode = 0;
2433
2434 /* also save the register index so we can check for
2435 * primitive id when emit src register. We need to modify the
2436 * operand type, index dimension when emit primitive id src reg.
2437 */
2438 emit->gs.prim_id_index = i;
2439 }
2440 else if (semantic_name == TGSI_SEMANTIC_POSITION) {
2441 /* vertex position input */
2442 opcodeType = VGPU10_OPCODE_DCL_INPUT_SIV;
2443 name = VGPU10_NAME_POSITION;
2444 }
2445
2446 emit_input_declaration(emit, opcodeType, operandType,
2447 dim, index,
2448 emit->gs.input_size,
2449 name,
2450 numComp, selMode,
2451 VGPU10_OPERAND_4_COMPONENT_MASK_ALL,
2452 VGPU10_INTERPOLATION_UNDEFINED);
2453 }
2454 }
2455 else {
2456 assert(emit->unit == PIPE_SHADER_VERTEX);
2457
2458 for (i = 0; i < emit->info.file_max[TGSI_FILE_INPUT] + 1; i++) {
2459 unsigned usage_mask = emit->info.input_usage_mask[i];
2460 unsigned index = i;
2461
2462 if (usage_mask == 0)
2463 continue; /* register is not actually used */
2464
2465 emit_input_declaration(emit, VGPU10_OPCODE_DCL_INPUT,
2466 VGPU10_OPERAND_TYPE_INPUT,
2467 VGPU10_OPERAND_INDEX_1D, index, 1,
2468 VGPU10_NAME_UNDEFINED,
2469 VGPU10_OPERAND_4_COMPONENT,
2470 VGPU10_OPERAND_4_COMPONENT_MASK_MODE,
2471 VGPU10_OPERAND_4_COMPONENT_MASK_ALL,
2472 VGPU10_INTERPOLATION_UNDEFINED);
2473 }
2474 }
2475
2476 return TRUE;
2477 }
2478
2479
2480 /**
2481 * Emit all output declarations.
2482 */
2483 static boolean
2484 emit_output_declarations(struct svga_shader_emitter_v10 *emit)
2485 {
2486 unsigned i;
2487
2488 for (i = 0; i < emit->info.num_outputs; i++) {
2489 /*const unsigned usage_mask = emit->info.output_usage_mask[i];*/
2490 const unsigned semantic_name = emit->info.output_semantic_name[i];
2491 const unsigned semantic_index = emit->info.output_semantic_index[i];
2492 unsigned index = i;
2493
2494 if (emit->unit == PIPE_SHADER_FRAGMENT) {
2495 if (semantic_name == TGSI_SEMANTIC_COLOR) {
2496 assert(semantic_index < ARRAY_SIZE(emit->fs.color_out_index));
2497
2498 emit->fs.color_out_index[semantic_index] = index;
2499
2500 /* The semantic index is the shader's color output/buffer index */
2501 emit_output_declaration(emit,
2502 VGPU10_OPCODE_DCL_OUTPUT, semantic_index,
2503 VGPU10_NAME_UNDEFINED,
2504 VGPU10_OPERAND_4_COMPONENT_MASK_ALL);
2505
2506 if (semantic_index == 0) {
2507 if (emit->key.fs.write_color0_to_n_cbufs > 1) {
2508 /* Emit declarations for the additional color outputs
2509 * for broadcasting.
2510 */
2511 unsigned j;
2512 for (j = 1; j < emit->key.fs.write_color0_to_n_cbufs; j++) {
2513 /* Allocate a new output index */
2514 unsigned idx = emit->info.num_outputs + j - 1;
2515 emit->fs.color_out_index[j] = idx;
2516 emit_output_declaration(emit,
2517 VGPU10_OPCODE_DCL_OUTPUT, idx,
2518 VGPU10_NAME_UNDEFINED,
2519 VGPU10_OPERAND_4_COMPONENT_MASK_ALL);
2520 emit->info.output_semantic_index[idx] = j;
2521 }
2522 }
2523 }
2524 else {
2525 assert(!emit->key.fs.write_color0_to_n_cbufs);
2526 }
2527 }
2528 else if (semantic_name == TGSI_SEMANTIC_POSITION) {
2529 /* Fragment depth output */
2530 emit_fragdepth_output_declaration(emit);
2531 }
2532 else {
2533 assert(!"Bad output semantic name");
2534 }
2535 }
2536 else {
2537 /* VS or GS */
2538 unsigned name, type;
2539 unsigned writemask = VGPU10_OPERAND_4_COMPONENT_MASK_ALL;
2540
2541 switch (semantic_name) {
2542 case TGSI_SEMANTIC_POSITION:
2543 assert(emit->unit != PIPE_SHADER_FRAGMENT);
2544 type = VGPU10_OPCODE_DCL_OUTPUT_SIV;
2545 name = VGPU10_NAME_POSITION;
2546 /* Save the index of the vertex position output register */
2547 emit->vposition.out_index = index;
2548 break;
2549 case TGSI_SEMANTIC_CLIPDIST:
2550 type = VGPU10_OPCODE_DCL_OUTPUT_SIV;
2551 name = VGPU10_NAME_CLIP_DISTANCE;
2552 /* save the starting index of the clip distance output register */
2553 if (semantic_index == 0)
2554 emit->clip_dist_out_index = index;
2555 writemask = emit->output_usage_mask[index];
2556 writemask = apply_clip_plane_mask(emit, writemask, semantic_index);
2557 if (writemask == 0x0) {
2558 continue; /* discard this do-nothing declaration */
2559 }
2560 break;
2561 case TGSI_SEMANTIC_PRIMID:
2562 assert(emit->unit == PIPE_SHADER_GEOMETRY);
2563 type = VGPU10_OPCODE_DCL_OUTPUT_SGV;
2564 name = VGPU10_NAME_PRIMITIVE_ID;
2565 break;
2566 case TGSI_SEMANTIC_LAYER:
2567 assert(emit->unit == PIPE_SHADER_GEOMETRY);
2568 type = VGPU10_OPCODE_DCL_OUTPUT_SGV;
2569 name = VGPU10_NAME_RENDER_TARGET_ARRAY_INDEX;
2570 break;
2571 case TGSI_SEMANTIC_CLIPVERTEX:
2572 type = VGPU10_OPCODE_DCL_OUTPUT;
2573 name = VGPU10_NAME_UNDEFINED;
2574 emit->clip_vertex_out_index = index;
2575 break;
2576 default:
2577 /* generic output */
2578 type = VGPU10_OPCODE_DCL_OUTPUT;
2579 name = VGPU10_NAME_UNDEFINED;
2580 }
2581
2582 emit_output_declaration(emit, type, index, name, writemask);
2583 }
2584 }
2585
2586 if (emit->vposition.so_index != INVALID_INDEX &&
2587 emit->vposition.out_index != INVALID_INDEX) {
2588
2589 assert(emit->unit != PIPE_SHADER_FRAGMENT);
2590
2591 /* Emit the declaration for the non-adjusted vertex position
2592 * for stream output purpose
2593 */
2594 emit_output_declaration(emit, VGPU10_OPCODE_DCL_OUTPUT,
2595 emit->vposition.so_index,
2596 VGPU10_NAME_UNDEFINED,
2597 VGPU10_OPERAND_4_COMPONENT_MASK_ALL);
2598 }
2599
2600 if (emit->clip_dist_so_index != INVALID_INDEX &&
2601 emit->clip_dist_out_index != INVALID_INDEX) {
2602
2603 assert(emit->unit != PIPE_SHADER_FRAGMENT);
2604
2605 /* Emit the declaration for the clip distance shadow copy which
2606 * will be used for stream output purpose and for clip distance
2607 * varying variable
2608 */
2609 emit_output_declaration(emit, VGPU10_OPCODE_DCL_OUTPUT,
2610 emit->clip_dist_so_index,
2611 VGPU10_NAME_UNDEFINED,
2612 emit->output_usage_mask[emit->clip_dist_out_index]);
2613
2614 if (emit->info.num_written_clipdistance > 4) {
2615 /* for the second clip distance register, each handles 4 planes */
2616 emit_output_declaration(emit, VGPU10_OPCODE_DCL_OUTPUT,
2617 emit->clip_dist_so_index + 1,
2618 VGPU10_NAME_UNDEFINED,
2619 emit->output_usage_mask[emit->clip_dist_out_index+1]);
2620 }
2621 }
2622
2623 return TRUE;
2624 }
2625
2626
2627 /**
2628 * Emit the declaration for the temporary registers.
2629 */
2630 static boolean
2631 emit_temporaries_declaration(struct svga_shader_emitter_v10 *emit)
2632 {
2633 unsigned total_temps, reg, i;
2634
2635 total_temps = emit->num_shader_temps;
2636
2637 /* If there is indirect access to non-indexable temps in the shader,
2638 * convert those temps to indexable temps. This works around a bug
2639 * in the GLSL->TGSI translator exposed in piglit test
2640 * glsl-1.20/execution/fs-const-array-of-struct-of-array.shader_test.
2641 * Internal temps added by the driver remain as non-indexable temps.
2642 */
2643 if ((emit->info.indirect_files & (1 << TGSI_FILE_TEMPORARY)) &&
2644 emit->num_temp_arrays == 0) {
2645 unsigned arrayID;
2646
2647 arrayID = 1;
2648 emit->num_temp_arrays = arrayID + 1;
2649 emit->temp_arrays[arrayID].start = 0;
2650 emit->temp_arrays[arrayID].size = total_temps;
2651
2652 /* Fill in the temp_map entries for this temp array */
2653 for (i = 0; i < total_temps; i++) {
2654 emit->temp_map[i].arrayId = arrayID;
2655 emit->temp_map[i].index = i;
2656 }
2657 }
2658
2659 /* Allocate extra temps for specially-implemented instructions,
2660 * such as LIT.
2661 */
2662 total_temps += MAX_INTERNAL_TEMPS;
2663
2664 if (emit->unit == PIPE_SHADER_VERTEX || emit->unit == PIPE_SHADER_GEOMETRY) {
2665 if (emit->vposition.need_prescale || emit->key.vs.undo_viewport ||
2666 emit->key.clip_plane_enable ||
2667 emit->vposition.so_index != INVALID_INDEX) {
2668 emit->vposition.tmp_index = total_temps;
2669 total_temps += 1;
2670 }
2671
2672 if (emit->unit == PIPE_SHADER_VERTEX) {
2673 unsigned attrib_mask = (emit->key.vs.adjust_attrib_w_1 |
2674 emit->key.vs.adjust_attrib_itof |
2675 emit->key.vs.adjust_attrib_utof |
2676 emit->key.vs.attrib_is_bgra |
2677 emit->key.vs.attrib_puint_to_snorm |
2678 emit->key.vs.attrib_puint_to_uscaled |
2679 emit->key.vs.attrib_puint_to_sscaled);
2680 while (attrib_mask) {
2681 unsigned index = u_bit_scan(&attrib_mask);
2682 emit->vs.adjusted_input[index] = total_temps++;
2683 }
2684 }
2685
2686 if (emit->clip_mode == CLIP_DISTANCE) {
2687 /* We need to write the clip distance to a temporary register
2688 * first. Then it will be copied to the shadow copy for
2689 * the clip distance varying variable and stream output purpose.
2690 * It will also be copied to the actual CLIPDIST register
2691 * according to the enabled clip planes
2692 */
2693 emit->clip_dist_tmp_index = total_temps++;
2694 if (emit->info.num_written_clipdistance > 4)
2695 total_temps++; /* second clip register */
2696 }
2697 else if (emit->clip_mode == CLIP_VERTEX) {
2698 /* We need to convert the TGSI CLIPVERTEX output to one or more
2699 * clip distances. Allocate a temp reg for the clipvertex here.
2700 */
2701 assert(emit->info.writes_clipvertex > 0);
2702 emit->clip_vertex_tmp_index = total_temps;
2703 total_temps++;
2704 }
2705 }
2706 else if (emit->unit == PIPE_SHADER_FRAGMENT) {
2707 if (emit->key.fs.alpha_func != SVGA3D_CMP_ALWAYS ||
2708 emit->key.fs.white_fragments ||
2709 emit->key.fs.write_color0_to_n_cbufs > 1) {
2710 /* Allocate a temp to hold the output color */
2711 emit->fs.color_tmp_index = total_temps;
2712 total_temps += 1;
2713 }
2714
2715 if (emit->fs.face_input_index != INVALID_INDEX) {
2716 /* Allocate a temp for the +/-1 face register */
2717 emit->fs.face_tmp_index = total_temps;
2718 total_temps += 1;
2719 }
2720
2721 if (emit->fs.fragcoord_input_index != INVALID_INDEX) {
2722 /* Allocate a temp for modified fragment position register */
2723 emit->fs.fragcoord_tmp_index = total_temps;
2724 total_temps += 1;
2725 }
2726 }
2727
2728 for (i = 0; i < emit->num_address_regs; i++) {
2729 emit->address_reg_index[i] = total_temps++;
2730 }
2731
2732 /* Initialize the temp_map array which maps TGSI temp indexes to VGPU10
2733 * temp indexes. Basically, we compact all the non-array temp register
2734 * indexes into a consecutive series.
2735 *
2736 * Before, we may have some TGSI declarations like:
2737 * DCL TEMP[0..1], LOCAL
2738 * DCL TEMP[2..4], ARRAY(1), LOCAL
2739 * DCL TEMP[5..7], ARRAY(2), LOCAL
2740 * plus, some extra temps, like TEMP[8], TEMP[9] for misc things
2741 *
2742 * After, we'll have a map like this:
2743 * temp_map[0] = { array 0, index 0 }
2744 * temp_map[1] = { array 0, index 1 }
2745 * temp_map[2] = { array 1, index 0 }
2746 * temp_map[3] = { array 1, index 1 }
2747 * temp_map[4] = { array 1, index 2 }
2748 * temp_map[5] = { array 2, index 0 }
2749 * temp_map[6] = { array 2, index 1 }
2750 * temp_map[7] = { array 2, index 2 }
2751 * temp_map[8] = { array 0, index 2 }
2752 * temp_map[9] = { array 0, index 3 }
2753 *
2754 * We'll declare two arrays of 3 elements, plus a set of four non-indexed
2755 * temps numbered 0..3
2756 *
2757 * Any time we emit a temporary register index, we'll have to use the
2758 * temp_map[] table to convert the TGSI index to the VGPU10 index.
2759 *
2760 * Finally, we recompute the total_temps value here.
2761 */
2762 reg = 0;
2763 for (i = 0; i < total_temps; i++) {
2764 if (emit->temp_map[i].arrayId == 0) {
2765 emit->temp_map[i].index = reg++;
2766 }
2767 }
2768
2769 if (0) {
2770 debug_printf("total_temps %u\n", total_temps);
2771 for (i = 0; i < total_temps; i++) {
2772 debug_printf("temp %u -> array %u index %u\n",
2773 i, emit->temp_map[i].arrayId, emit->temp_map[i].index);
2774 }
2775 }
2776
2777 total_temps = reg;
2778
2779 /* Emit declaration of ordinary temp registers */
2780 if (total_temps > 0) {
2781 VGPU10OpcodeToken0 opcode0;
2782
2783 opcode0.value = 0;
2784 opcode0.opcodeType = VGPU10_OPCODE_DCL_TEMPS;
2785
2786 begin_emit_instruction(emit);
2787 emit_dword(emit, opcode0.value);
2788 emit_dword(emit, total_temps);
2789 end_emit_instruction(emit);
2790 }
2791
2792 /* Emit declarations for indexable temp arrays. Skip 0th entry since
2793 * it's unused.
2794 */
2795 for (i = 1; i < emit->num_temp_arrays; i++) {
2796 unsigned num_temps = emit->temp_arrays[i].size;
2797
2798 if (num_temps > 0) {
2799 VGPU10OpcodeToken0 opcode0;
2800
2801 opcode0.value = 0;
2802 opcode0.opcodeType = VGPU10_OPCODE_DCL_INDEXABLE_TEMP;
2803
2804 begin_emit_instruction(emit);
2805 emit_dword(emit, opcode0.value);
2806 emit_dword(emit, i); /* which array */
2807 emit_dword(emit, num_temps);
2808 emit_dword(emit, 4); /* num components */
2809 end_emit_instruction(emit);
2810
2811 total_temps += num_temps;
2812 }
2813 }
2814
2815 /* Check that the grand total of all regular and indexed temps is
2816 * under the limit.
2817 */
2818 check_register_index(emit, VGPU10_OPCODE_DCL_TEMPS, total_temps - 1);
2819
2820 return TRUE;
2821 }
2822
2823
2824 static boolean
2825 emit_constant_declaration(struct svga_shader_emitter_v10 *emit)
2826 {
2827 VGPU10OpcodeToken0 opcode0;
2828 VGPU10OperandToken0 operand0;
2829 unsigned total_consts, i;
2830
2831 opcode0.value = 0;
2832 opcode0.opcodeType = VGPU10_OPCODE_DCL_CONSTANT_BUFFER;
2833 opcode0.accessPattern = VGPU10_CB_IMMEDIATE_INDEXED;
2834 /* XXX or, access pattern = VGPU10_CB_DYNAMIC_INDEXED */
2835
2836 operand0.value = 0;
2837 operand0.numComponents = VGPU10_OPERAND_4_COMPONENT;
2838 operand0.indexDimension = VGPU10_OPERAND_INDEX_2D;
2839 operand0.index0Representation = VGPU10_OPERAND_INDEX_IMMEDIATE32;
2840 operand0.index1Representation = VGPU10_OPERAND_INDEX_IMMEDIATE32;
2841 operand0.operandType = VGPU10_OPERAND_TYPE_CONSTANT_BUFFER;
2842 operand0.selectionMode = VGPU10_OPERAND_4_COMPONENT_SWIZZLE_MODE;
2843 operand0.swizzleX = 0;
2844 operand0.swizzleY = 1;
2845 operand0.swizzleZ = 2;
2846 operand0.swizzleW = 3;
2847
2848 /**
2849 * Emit declaration for constant buffer [0]. We also allocate
2850 * room for the extra constants here.
2851 */
2852 total_consts = emit->num_shader_consts[0];
2853
2854 /* Now, allocate constant slots for the "extra" constants */
2855
2856 /* Vertex position scale/translation */
2857 if (emit->vposition.need_prescale) {
2858 emit->vposition.prescale_scale_index = total_consts++;
2859 emit->vposition.prescale_trans_index = total_consts++;
2860 }
2861
2862 if (emit->unit == PIPE_SHADER_VERTEX) {
2863 if (emit->key.vs.undo_viewport) {
2864 emit->vs.viewport_index = total_consts++;
2865 }
2866 }
2867
2868 /* user-defined clip planes */
2869 if (emit->key.clip_plane_enable) {
2870 unsigned n = util_bitcount(emit->key.clip_plane_enable);
2871 assert(emit->unit == PIPE_SHADER_VERTEX ||
2872 emit->unit == PIPE_SHADER_GEOMETRY);
2873 for (i = 0; i < n; i++) {
2874 emit->clip_plane_const[i] = total_consts++;
2875 }
2876 }
2877
2878 /* Texcoord scale factors for RECT textures */
2879 {
2880 for (i = 0; i < emit->num_samplers; i++) {
2881 if (emit->key.tex[i].unnormalized) {
2882 emit->texcoord_scale_index[i] = total_consts++;
2883 }
2884 }
2885 }
2886
2887 /* Texture buffer sizes */
2888 for (i = 0; i < emit->num_samplers; i++) {
2889 if (emit->sampler_target[i] == TGSI_TEXTURE_BUFFER) {
2890 emit->texture_buffer_size_index[i] = total_consts++;
2891 }
2892 }
2893
2894 if (total_consts > 0) {
2895 begin_emit_instruction(emit);
2896 emit_dword(emit, opcode0.value);
2897 emit_dword(emit, operand0.value);
2898 emit_dword(emit, 0); /* which const buffer slot */
2899 emit_dword(emit, total_consts);
2900 end_emit_instruction(emit);
2901 }
2902
2903 /* Declare remaining constant buffers (UBOs) */
2904 for (i = 1; i < ARRAY_SIZE(emit->num_shader_consts); i++) {
2905 if (emit->num_shader_consts[i] > 0) {
2906 begin_emit_instruction(emit);
2907 emit_dword(emit, opcode0.value);
2908 emit_dword(emit, operand0.value);
2909 emit_dword(emit, i); /* which const buffer slot */
2910 emit_dword(emit, emit->num_shader_consts[i]);
2911 end_emit_instruction(emit);
2912 }
2913 }
2914
2915 return TRUE;
2916 }
2917
2918
2919 /**
2920 * Emit declarations for samplers.
2921 */
2922 static boolean
2923 emit_sampler_declarations(struct svga_shader_emitter_v10 *emit)
2924 {
2925 unsigned i;
2926
2927 for (i = 0; i < emit->num_samplers; i++) {
2928 VGPU10OpcodeToken0 opcode0;
2929 VGPU10OperandToken0 operand0;
2930
2931 opcode0.value = 0;
2932 opcode0.opcodeType = VGPU10_OPCODE_DCL_SAMPLER;
2933 opcode0.samplerMode = VGPU10_SAMPLER_MODE_DEFAULT;
2934
2935 operand0.value = 0;
2936 operand0.numComponents = VGPU10_OPERAND_0_COMPONENT;
2937 operand0.operandType = VGPU10_OPERAND_TYPE_SAMPLER;
2938 operand0.indexDimension = VGPU10_OPERAND_INDEX_1D;
2939 operand0.index0Representation = VGPU10_OPERAND_INDEX_IMMEDIATE32;
2940
2941 begin_emit_instruction(emit);
2942 emit_dword(emit, opcode0.value);
2943 emit_dword(emit, operand0.value);
2944 emit_dword(emit, i);
2945 end_emit_instruction(emit);
2946 }
2947
2948 return TRUE;
2949 }
2950
2951
2952 /**
2953 * Translate TGSI_TEXTURE_x to VGAPU10_RESOURCE_DIMENSION_x.
2954 */
2955 static unsigned
2956 tgsi_texture_to_resource_dimension(unsigned target, boolean is_array)
2957 {
2958 switch (target) {
2959 case TGSI_TEXTURE_BUFFER:
2960 return VGPU10_RESOURCE_DIMENSION_BUFFER;
2961 case TGSI_TEXTURE_1D:
2962 return VGPU10_RESOURCE_DIMENSION_TEXTURE1D;
2963 case TGSI_TEXTURE_2D:
2964 case TGSI_TEXTURE_RECT:
2965 return VGPU10_RESOURCE_DIMENSION_TEXTURE2D;
2966 case TGSI_TEXTURE_3D:
2967 return VGPU10_RESOURCE_DIMENSION_TEXTURE3D;
2968 case TGSI_TEXTURE_CUBE:
2969 return VGPU10_RESOURCE_DIMENSION_TEXTURECUBE;
2970 case TGSI_TEXTURE_SHADOW1D:
2971 return VGPU10_RESOURCE_DIMENSION_TEXTURE1D;
2972 case TGSI_TEXTURE_SHADOW2D:
2973 case TGSI_TEXTURE_SHADOWRECT:
2974 return VGPU10_RESOURCE_DIMENSION_TEXTURE2D;
2975 case TGSI_TEXTURE_1D_ARRAY:
2976 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2977 return is_array ? VGPU10_RESOURCE_DIMENSION_TEXTURE1DARRAY
2978 : VGPU10_RESOURCE_DIMENSION_TEXTURE1D;
2979 case TGSI_TEXTURE_2D_ARRAY:
2980 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2981 return is_array ? VGPU10_RESOURCE_DIMENSION_TEXTURE2DARRAY
2982 : VGPU10_RESOURCE_DIMENSION_TEXTURE2D;
2983 case TGSI_TEXTURE_SHADOWCUBE:
2984 return VGPU10_RESOURCE_DIMENSION_TEXTURECUBE;
2985 case TGSI_TEXTURE_2D_MSAA:
2986 return VGPU10_RESOURCE_DIMENSION_TEXTURE2DMS;
2987 case TGSI_TEXTURE_2D_ARRAY_MSAA:
2988 return is_array ? VGPU10_RESOURCE_DIMENSION_TEXTURE2DMSARRAY
2989 : VGPU10_RESOURCE_DIMENSION_TEXTURE2DMS;
2990 case TGSI_TEXTURE_CUBE_ARRAY:
2991 return VGPU10_RESOURCE_DIMENSION_TEXTURECUBEARRAY;
2992 default:
2993 assert(!"Unexpected resource type");
2994 return VGPU10_RESOURCE_DIMENSION_TEXTURE2D;
2995 }
2996 }
2997
2998
2999 /**
3000 * Given a tgsi_return_type, return true iff it is an integer type.
3001 */
3002 static boolean
3003 is_integer_type(enum tgsi_return_type type)
3004 {
3005 switch (type) {
3006 case TGSI_RETURN_TYPE_SINT:
3007 case TGSI_RETURN_TYPE_UINT:
3008 return TRUE;
3009 case TGSI_RETURN_TYPE_FLOAT:
3010 case TGSI_RETURN_TYPE_UNORM:
3011 case TGSI_RETURN_TYPE_SNORM:
3012 return FALSE;
3013 case TGSI_RETURN_TYPE_COUNT:
3014 default:
3015 assert(!"is_integer_type: Unknown tgsi_return_type");
3016 return FALSE;
3017 }
3018 }
3019
3020
3021 /**
3022 * Emit declarations for resources.
3023 * XXX When we're sure that all TGSI shaders will be generated with
3024 * sampler view declarations (Ex: DCL SVIEW[n], 2D, UINT) we may
3025 * rework this code.
3026 */
3027 static boolean
3028 emit_resource_declarations(struct svga_shader_emitter_v10 *emit)
3029 {
3030 unsigned i;
3031
3032 /* Emit resource decl for each sampler */
3033 for (i = 0; i < emit->num_samplers; i++) {
3034 VGPU10OpcodeToken0 opcode0;
3035 VGPU10OperandToken0 operand0;
3036 VGPU10ResourceReturnTypeToken return_type;
3037 VGPU10_RESOURCE_RETURN_TYPE rt;
3038
3039 opcode0.value = 0;
3040 opcode0.opcodeType = VGPU10_OPCODE_DCL_RESOURCE;
3041 opcode0.resourceDimension =
3042 tgsi_texture_to_resource_dimension(emit->sampler_target[i],
3043 emit->key.tex[i].is_array);
3044 operand0.value = 0;
3045 operand0.numComponents = VGPU10_OPERAND_0_COMPONENT;
3046 operand0.operandType = VGPU10_OPERAND_TYPE_RESOURCE;
3047 operand0.indexDimension = VGPU10_OPERAND_INDEX_1D;
3048 operand0.index0Representation = VGPU10_OPERAND_INDEX_IMMEDIATE32;
3049
3050 #if 1
3051 /* convert TGSI_RETURN_TYPE_x to VGPU10_RETURN_TYPE_x */
3052 STATIC_ASSERT(VGPU10_RETURN_TYPE_UNORM == TGSI_RETURN_TYPE_UNORM + 1);
3053 STATIC_ASSERT(VGPU10_RETURN_TYPE_SNORM == TGSI_RETURN_TYPE_SNORM + 1);
3054 STATIC_ASSERT(VGPU10_RETURN_TYPE_SINT == TGSI_RETURN_TYPE_SINT + 1);
3055 STATIC_ASSERT(VGPU10_RETURN_TYPE_UINT == TGSI_RETURN_TYPE_UINT + 1);
3056 STATIC_ASSERT(VGPU10_RETURN_TYPE_FLOAT == TGSI_RETURN_TYPE_FLOAT + 1);
3057 assert(emit->sampler_return_type[i] <= TGSI_RETURN_TYPE_FLOAT);
3058 rt = emit->sampler_return_type[i] + 1;
3059 #else
3060 switch (emit->sampler_return_type[i]) {
3061 case TGSI_RETURN_TYPE_UNORM: rt = VGPU10_RETURN_TYPE_UNORM; break;
3062 case TGSI_RETURN_TYPE_SNORM: rt = VGPU10_RETURN_TYPE_SNORM; break;
3063 case TGSI_RETURN_TYPE_SINT: rt = VGPU10_RETURN_TYPE_SINT; break;
3064 case TGSI_RETURN_TYPE_UINT: rt = VGPU10_RETURN_TYPE_UINT; break;
3065 case TGSI_RETURN_TYPE_FLOAT: rt = VGPU10_RETURN_TYPE_FLOAT; break;
3066 case TGSI_RETURN_TYPE_COUNT:
3067 default:
3068 rt = VGPU10_RETURN_TYPE_FLOAT;
3069 assert(!"emit_resource_declarations: Unknown tgsi_return_type");
3070 }
3071 #endif
3072
3073 return_type.value = 0;
3074 return_type.component0 = rt;
3075 return_type.component1 = rt;
3076 return_type.component2 = rt;
3077 return_type.component3 = rt;
3078
3079 begin_emit_instruction(emit);
3080 emit_dword(emit, opcode0.value);
3081 emit_dword(emit, operand0.value);
3082 emit_dword(emit, i);
3083 emit_dword(emit, return_type.value);
3084 end_emit_instruction(emit);
3085 }
3086
3087 return TRUE;
3088 }
3089
3090 static void
3091 emit_instruction_op1(struct svga_shader_emitter_v10 *emit,
3092 unsigned opcode,
3093 const struct tgsi_full_dst_register *dst,
3094 const struct tgsi_full_src_register *src,
3095 boolean saturate)
3096 {
3097 begin_emit_instruction(emit);
3098 emit_opcode(emit, opcode, saturate);
3099 emit_dst_register(emit, dst);
3100 emit_src_register(emit, src);
3101 end_emit_instruction(emit);
3102 }
3103
3104 static void
3105 emit_instruction_op2(struct svga_shader_emitter_v10 *emit,
3106 unsigned opcode,
3107 const struct tgsi_full_dst_register *dst,
3108 const struct tgsi_full_src_register *src1,
3109 const struct tgsi_full_src_register *src2,
3110 boolean saturate)
3111 {
3112 begin_emit_instruction(emit);
3113 emit_opcode(emit, opcode, saturate);
3114 emit_dst_register(emit, dst);
3115 emit_src_register(emit, src1);
3116 emit_src_register(emit, src2);
3117 end_emit_instruction(emit);
3118 }
3119
3120 static void
3121 emit_instruction_op3(struct svga_shader_emitter_v10 *emit,
3122 unsigned opcode,
3123 const struct tgsi_full_dst_register *dst,
3124 const struct tgsi_full_src_register *src1,
3125 const struct tgsi_full_src_register *src2,
3126 const struct tgsi_full_src_register *src3,
3127 boolean saturate)
3128 {
3129 begin_emit_instruction(emit);
3130 emit_opcode(emit, opcode, saturate);
3131 emit_dst_register(emit, dst);
3132 emit_src_register(emit, src1);
3133 emit_src_register(emit, src2);
3134 emit_src_register(emit, src3);
3135 end_emit_instruction(emit);
3136 }
3137
3138 /**
3139 * Emit the actual clip distance instructions to be used for clipping
3140 * by copying the clip distance from the temporary registers to the
3141 * CLIPDIST registers written with the enabled planes mask.
3142 * Also copy the clip distance from the temporary to the clip distance
3143 * shadow copy register which will be referenced by the input shader
3144 */
3145 static void
3146 emit_clip_distance_instructions(struct svga_shader_emitter_v10 *emit)
3147 {
3148 struct tgsi_full_src_register tmp_clip_dist_src;
3149 struct tgsi_full_dst_register clip_dist_dst;
3150
3151 unsigned i;
3152 unsigned clip_plane_enable = emit->key.clip_plane_enable;
3153 unsigned clip_dist_tmp_index = emit->clip_dist_tmp_index;
3154 int num_written_clipdist = emit->info.num_written_clipdistance;
3155
3156 assert(emit->clip_dist_out_index != INVALID_INDEX);
3157 assert(emit->clip_dist_tmp_index != INVALID_INDEX);
3158
3159 /**
3160 * Temporary reset the temporary clip dist register index so
3161 * that the copy to the real clip dist register will not
3162 * attempt to copy to the temporary register again
3163 */
3164 emit->clip_dist_tmp_index = INVALID_INDEX;
3165
3166 for (i = 0; i < 2 && num_written_clipdist > 0; i++, num_written_clipdist-=4) {
3167
3168 tmp_clip_dist_src = make_src_temp_reg(clip_dist_tmp_index + i);
3169
3170 /**
3171 * copy to the shadow copy for use by varying variable and
3172 * stream output. All clip distances
3173 * will be written regardless of the enabled clipping planes.
3174 */
3175 clip_dist_dst = make_dst_reg(TGSI_FILE_OUTPUT,
3176 emit->clip_dist_so_index + i);
3177
3178 /* MOV clip_dist_so, tmp_clip_dist */
3179 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &clip_dist_dst,
3180 &tmp_clip_dist_src, FALSE);
3181
3182 /**
3183 * copy those clip distances to enabled clipping planes
3184 * to CLIPDIST registers for clipping
3185 */
3186 if (clip_plane_enable & 0xf) {
3187 clip_dist_dst = make_dst_reg(TGSI_FILE_OUTPUT,
3188 emit->clip_dist_out_index + i);
3189 clip_dist_dst = writemask_dst(&clip_dist_dst, clip_plane_enable & 0xf);
3190
3191 /* MOV CLIPDIST, tmp_clip_dist */
3192 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &clip_dist_dst,
3193 &tmp_clip_dist_src, FALSE);
3194 }
3195 /* four clip planes per clip register */
3196 clip_plane_enable >>= 4;
3197 }
3198 /**
3199 * set the temporary clip dist register index back to the
3200 * temporary index for the next vertex
3201 */
3202 emit->clip_dist_tmp_index = clip_dist_tmp_index;
3203 }
3204
3205 /* Declare clip distance output registers for user-defined clip planes
3206 * or the TGSI_CLIPVERTEX output.
3207 */
3208 static void
3209 emit_clip_distance_declarations(struct svga_shader_emitter_v10 *emit)
3210 {
3211 unsigned num_clip_planes = util_bitcount(emit->key.clip_plane_enable);
3212 unsigned index = emit->num_outputs;
3213 unsigned plane_mask;
3214
3215 assert(emit->unit == PIPE_SHADER_VERTEX ||
3216 emit->unit == PIPE_SHADER_GEOMETRY);
3217 assert(num_clip_planes <= 8);
3218
3219 if (emit->clip_mode != CLIP_LEGACY &&
3220 emit->clip_mode != CLIP_VERTEX) {
3221 return;
3222 }
3223
3224 if (num_clip_planes == 0)
3225 return;
3226
3227 /* Declare one or two clip output registers. The number of components
3228 * in the mask reflects the number of clip planes. For example, if 5
3229 * clip planes are needed, we'll declare outputs similar to:
3230 * dcl_output_siv o2.xyzw, clip_distance
3231 * dcl_output_siv o3.x, clip_distance
3232 */
3233 emit->clip_dist_out_index = index; /* save the starting clip dist reg index */
3234
3235 plane_mask = (1 << num_clip_planes) - 1;
3236 if (plane_mask & 0xf) {
3237 unsigned cmask = plane_mask & VGPU10_OPERAND_4_COMPONENT_MASK_ALL;
3238 emit_output_declaration(emit, VGPU10_OPCODE_DCL_OUTPUT_SIV, index,
3239 VGPU10_NAME_CLIP_DISTANCE, cmask);
3240 emit->num_outputs++;
3241 }
3242 if (plane_mask & 0xf0) {
3243 unsigned cmask = (plane_mask >> 4) & VGPU10_OPERAND_4_COMPONENT_MASK_ALL;
3244 emit_output_declaration(emit, VGPU10_OPCODE_DCL_OUTPUT_SIV, index + 1,
3245 VGPU10_NAME_CLIP_DISTANCE, cmask);
3246 emit->num_outputs++;
3247 }
3248 }
3249
3250
3251 /**
3252 * Emit the instructions for writing to the clip distance registers
3253 * to handle legacy/automatic clip planes.
3254 * For each clip plane, the distance is the dot product of the vertex
3255 * position (found in TEMP[vpos_tmp_index]) and the clip plane coefficients.
3256 * This is not used when the shader has an explicit CLIPVERTEX or CLIPDISTANCE
3257 * output registers already declared.
3258 */
3259 static void
3260 emit_clip_distance_from_vpos(struct svga_shader_emitter_v10 *emit,
3261 unsigned vpos_tmp_index)
3262 {
3263 unsigned i, num_clip_planes = util_bitcount(emit->key.clip_plane_enable);
3264
3265 assert(emit->clip_mode == CLIP_LEGACY);
3266 assert(num_clip_planes <= 8);
3267
3268 assert(emit->unit == PIPE_SHADER_VERTEX ||
3269 emit->unit == PIPE_SHADER_GEOMETRY);
3270
3271 for (i = 0; i < num_clip_planes; i++) {
3272 struct tgsi_full_dst_register dst;
3273 struct tgsi_full_src_register plane_src, vpos_src;
3274 unsigned reg_index = emit->clip_dist_out_index + i / 4;
3275 unsigned comp = i % 4;
3276 unsigned writemask = VGPU10_OPERAND_4_COMPONENT_MASK_X << comp;
3277
3278 /* create dst, src regs */
3279 dst = make_dst_reg(TGSI_FILE_OUTPUT, reg_index);
3280 dst = writemask_dst(&dst, writemask);
3281
3282 plane_src = make_src_const_reg(emit->clip_plane_const[i]);
3283 vpos_src = make_src_temp_reg(vpos_tmp_index);
3284
3285 /* DP4 clip_dist, plane, vpos */
3286 emit_instruction_op2(emit, VGPU10_OPCODE_DP4, &dst,
3287 &plane_src, &vpos_src, FALSE);
3288 }
3289 }
3290
3291
3292 /**
3293 * Emit the instructions for computing the clip distance results from
3294 * the clip vertex temporary.
3295 * For each clip plane, the distance is the dot product of the clip vertex
3296 * position (found in a temp reg) and the clip plane coefficients.
3297 */
3298 static void
3299 emit_clip_vertex_instructions(struct svga_shader_emitter_v10 *emit)
3300 {
3301 const unsigned num_clip = util_bitcount(emit->key.clip_plane_enable);
3302 unsigned i;
3303 struct tgsi_full_dst_register dst;
3304 struct tgsi_full_src_register clipvert_src;
3305 const unsigned clip_vertex_tmp = emit->clip_vertex_tmp_index;
3306
3307 assert(emit->unit == PIPE_SHADER_VERTEX ||
3308 emit->unit == PIPE_SHADER_GEOMETRY);
3309
3310 assert(emit->clip_mode == CLIP_VERTEX);
3311
3312 clipvert_src = make_src_temp_reg(clip_vertex_tmp);
3313
3314 for (i = 0; i < num_clip; i++) {
3315 struct tgsi_full_src_register plane_src;
3316 unsigned reg_index = emit->clip_dist_out_index + i / 4;
3317 unsigned comp = i % 4;
3318 unsigned writemask = VGPU10_OPERAND_4_COMPONENT_MASK_X << comp;
3319
3320 /* create dst, src regs */
3321 dst = make_dst_reg(TGSI_FILE_OUTPUT, reg_index);
3322 dst = writemask_dst(&dst, writemask);
3323
3324 plane_src = make_src_const_reg(emit->clip_plane_const[i]);
3325
3326 /* DP4 clip_dist, plane, vpos */
3327 emit_instruction_op2(emit, VGPU10_OPCODE_DP4, &dst,
3328 &plane_src, &clipvert_src, FALSE);
3329 }
3330
3331 /* copy temporary clip vertex register to the clip vertex register */
3332
3333 assert(emit->clip_vertex_out_index != INVALID_INDEX);
3334
3335 /**
3336 * temporary reset the temporary clip vertex register index so
3337 * that copy to the clip vertex register will not attempt
3338 * to copy to the temporary register again
3339 */
3340 emit->clip_vertex_tmp_index = INVALID_INDEX;
3341
3342 /* MOV clip_vertex, clip_vertex_tmp */
3343 dst = make_dst_reg(TGSI_FILE_OUTPUT, emit->clip_vertex_out_index);
3344 emit_instruction_op1(emit, VGPU10_OPCODE_MOV,
3345 &dst, &clipvert_src, FALSE);
3346
3347 /**
3348 * set the temporary clip vertex register index back to the
3349 * temporary index for the next vertex
3350 */
3351 emit->clip_vertex_tmp_index = clip_vertex_tmp;
3352 }
3353
3354 /**
3355 * Emit code to convert RGBA to BGRA
3356 */
3357 static void
3358 emit_swap_r_b(struct svga_shader_emitter_v10 *emit,
3359 const struct tgsi_full_dst_register *dst,
3360 const struct tgsi_full_src_register *src)
3361 {
3362 struct tgsi_full_src_register bgra_src =
3363 swizzle_src(src, TGSI_SWIZZLE_Z, TGSI_SWIZZLE_Y, TGSI_SWIZZLE_X, TGSI_SWIZZLE_W);
3364
3365 begin_emit_instruction(emit);
3366 emit_opcode(emit, VGPU10_OPCODE_MOV, FALSE);
3367 emit_dst_register(emit, dst);
3368 emit_src_register(emit, &bgra_src);
3369 end_emit_instruction(emit);
3370 }
3371
3372
3373 /** Convert from 10_10_10_2 normalized to 10_10_10_2_snorm */
3374 static void
3375 emit_puint_to_snorm(struct svga_shader_emitter_v10 *emit,
3376 const struct tgsi_full_dst_register *dst,
3377 const struct tgsi_full_src_register *src)
3378 {
3379 struct tgsi_full_src_register half = make_immediate_reg_float(emit, 0.5f);
3380 struct tgsi_full_src_register two =
3381 make_immediate_reg_float4(emit, 2.0f, 2.0f, 2.0f, 3.0f);
3382 struct tgsi_full_src_register neg_two =
3383 make_immediate_reg_float4(emit, -2.0f, -2.0f, -2.0f, -1.66666f);
3384
3385 unsigned val_tmp = get_temp_index(emit);
3386 struct tgsi_full_dst_register val_dst = make_dst_temp_reg(val_tmp);
3387 struct tgsi_full_src_register val_src = make_src_temp_reg(val_tmp);
3388
3389 unsigned bias_tmp = get_temp_index(emit);
3390 struct tgsi_full_dst_register bias_dst = make_dst_temp_reg(bias_tmp);
3391 struct tgsi_full_src_register bias_src = make_src_temp_reg(bias_tmp);
3392
3393 /* val = src * 2.0 */
3394 emit_instruction_op2(emit, VGPU10_OPCODE_MUL, &val_dst,
3395 src, &two, FALSE);
3396
3397 /* bias = src > 0.5 */
3398 emit_instruction_op2(emit, VGPU10_OPCODE_GE, &bias_dst,
3399 src, &half, FALSE);
3400
3401 /* bias = bias & -2.0 */
3402 emit_instruction_op2(emit, VGPU10_OPCODE_AND, &bias_dst,
3403 &bias_src, &neg_two, FALSE);
3404
3405 /* dst = val + bias */
3406 emit_instruction_op2(emit, VGPU10_OPCODE_ADD, dst,
3407 &val_src, &bias_src, FALSE);
3408
3409 free_temp_indexes(emit);
3410 }
3411
3412
3413 /** Convert from 10_10_10_2_unorm to 10_10_10_2_uscaled */
3414 static void
3415 emit_puint_to_uscaled(struct svga_shader_emitter_v10 *emit,
3416 const struct tgsi_full_dst_register *dst,
3417 const struct tgsi_full_src_register *src)
3418 {
3419 struct tgsi_full_src_register scale =
3420 make_immediate_reg_float4(emit, 1023.0f, 1023.0f, 1023.0f, 3.0f);
3421
3422 /* dst = src * scale */
3423 emit_instruction_op2(emit, VGPU10_OPCODE_MUL, dst, src, &scale, FALSE);
3424 }
3425
3426
3427 /** Convert from R32_UINT to 10_10_10_2_sscaled */
3428 static void
3429 emit_puint_to_sscaled(struct svga_shader_emitter_v10 *emit,
3430 const struct tgsi_full_dst_register *dst,
3431 const struct tgsi_full_src_register *src)
3432 {
3433 struct tgsi_full_src_register lshift =
3434 make_immediate_reg_int4(emit, 22, 12, 2, 0);
3435 struct tgsi_full_src_register rshift =
3436 make_immediate_reg_int4(emit, 22, 22, 22, 30);
3437
3438 struct tgsi_full_src_register src_xxxx = scalar_src(src, TGSI_SWIZZLE_X);
3439
3440 unsigned tmp = get_temp_index(emit);
3441 struct tgsi_full_dst_register tmp_dst = make_dst_temp_reg(tmp);
3442 struct tgsi_full_src_register tmp_src = make_src_temp_reg(tmp);
3443
3444 /*
3445 * r = (pixel << 22) >> 22; # signed int in [511, -512]
3446 * g = (pixel << 12) >> 22; # signed int in [511, -512]
3447 * b = (pixel << 2) >> 22; # signed int in [511, -512]
3448 * a = (pixel << 0) >> 30; # signed int in [1, -2]
3449 * dst = i_to_f(r,g,b,a); # convert to float
3450 */
3451 emit_instruction_op2(emit, VGPU10_OPCODE_ISHL, &tmp_dst,
3452 &src_xxxx, &lshift, FALSE);
3453 emit_instruction_op2(emit, VGPU10_OPCODE_ISHR, &tmp_dst,
3454 &tmp_src, &rshift, FALSE);
3455 emit_instruction_op1(emit, VGPU10_OPCODE_ITOF, dst, &tmp_src, FALSE);
3456
3457 free_temp_indexes(emit);
3458 }
3459
3460
3461 /**
3462 * Emit code for TGSI_OPCODE_ARL or TGSI_OPCODE_UARL instruction.
3463 */
3464 static boolean
3465 emit_arl_uarl(struct svga_shader_emitter_v10 *emit,
3466 const struct tgsi_full_instruction *inst)
3467 {
3468 unsigned index = inst->Dst[0].Register.Index;
3469 struct tgsi_full_dst_register dst;
3470 unsigned opcode;
3471
3472 assert(index < MAX_VGPU10_ADDR_REGS);
3473 dst = make_dst_temp_reg(emit->address_reg_index[index]);
3474
3475 /* ARL dst, s0
3476 * Translates into:
3477 * FTOI address_tmp, s0
3478 *
3479 * UARL dst, s0
3480 * Translates into:
3481 * MOV address_tmp, s0
3482 */
3483 if (inst->Instruction.Opcode == TGSI_OPCODE_ARL)
3484 opcode = VGPU10_OPCODE_FTOI;
3485 else
3486 opcode = VGPU10_OPCODE_MOV;
3487
3488 emit_instruction_op1(emit, opcode, &dst, &inst->Src[0], FALSE);
3489
3490 return TRUE;
3491 }
3492
3493
3494 /**
3495 * Emit code for TGSI_OPCODE_CAL instruction.
3496 */
3497 static boolean
3498 emit_cal(struct svga_shader_emitter_v10 *emit,
3499 const struct tgsi_full_instruction *inst)
3500 {
3501 unsigned label = inst->Label.Label;
3502 VGPU10OperandToken0 operand;
3503 operand.value = 0;
3504 operand.operandType = VGPU10_OPERAND_TYPE_LABEL;
3505
3506 begin_emit_instruction(emit);
3507 emit_dword(emit, operand.value);
3508 emit_dword(emit, label);
3509 end_emit_instruction(emit);
3510
3511 return TRUE;
3512 }
3513
3514
3515 /**
3516 * Emit code for TGSI_OPCODE_IABS instruction.
3517 */
3518 static boolean
3519 emit_iabs(struct svga_shader_emitter_v10 *emit,
3520 const struct tgsi_full_instruction *inst)
3521 {
3522 /* dst.x = (src0.x < 0) ? -src0.x : src0.x
3523 * dst.y = (src0.y < 0) ? -src0.y : src0.y
3524 * dst.z = (src0.z < 0) ? -src0.z : src0.z
3525 * dst.w = (src0.w < 0) ? -src0.w : src0.w
3526 *
3527 * Translates into
3528 * IMAX dst, src, neg(src)
3529 */
3530 struct tgsi_full_src_register neg_src = negate_src(&inst->Src[0]);
3531 emit_instruction_op2(emit, VGPU10_OPCODE_IMAX, &inst->Dst[0],
3532 &inst->Src[0], &neg_src, FALSE);
3533
3534 return TRUE;
3535 }
3536
3537
3538 /**
3539 * Emit code for TGSI_OPCODE_CMP instruction.
3540 */
3541 static boolean
3542 emit_cmp(struct svga_shader_emitter_v10 *emit,
3543 const struct tgsi_full_instruction *inst)
3544 {
3545 /* dst.x = (src0.x < 0) ? src1.x : src2.x
3546 * dst.y = (src0.y < 0) ? src1.y : src2.y
3547 * dst.z = (src0.z < 0) ? src1.z : src2.z
3548 * dst.w = (src0.w < 0) ? src1.w : src2.w
3549 *
3550 * Translates into
3551 * LT tmp, src0, 0.0
3552 * MOVC dst, tmp, src1, src2
3553 */
3554 struct tgsi_full_src_register zero = make_immediate_reg_float(emit, 0.0f);
3555 unsigned tmp = get_temp_index(emit);
3556 struct tgsi_full_src_register tmp_src = make_src_temp_reg(tmp);
3557 struct tgsi_full_dst_register tmp_dst = make_dst_temp_reg(tmp);
3558
3559 emit_instruction_op2(emit, VGPU10_OPCODE_LT, &tmp_dst,
3560 &inst->Src[0], &zero, FALSE);
3561 emit_instruction_op3(emit, VGPU10_OPCODE_MOVC, &inst->Dst[0],
3562 &tmp_src, &inst->Src[1], &inst->Src[2],
3563 inst->Instruction.Saturate);
3564
3565 free_temp_indexes(emit);
3566
3567 return TRUE;
3568 }
3569
3570
3571 /**
3572 * Emit code for TGSI_OPCODE_DP2A instruction.
3573 */
3574 static boolean
3575 emit_dp2a(struct svga_shader_emitter_v10 *emit,
3576 const struct tgsi_full_instruction *inst)
3577 {
3578 /* dst.x = src0.x * src1.x + src0.y * src1.y + src2.x
3579 * dst.y = src0.x * src1.x + src0.y * src1.y + src2.x
3580 * dst.z = src0.x * src1.x + src0.y * src1.y + src2.x
3581 * dst.w = src0.x * src1.x + src0.y * src1.y + src2.x
3582 * Translate into
3583 * MAD tmp.x, s0.y, s1.y, s2.x
3584 * MAD tmp.x, s0.x, s1.x, tmp.x
3585 * MOV dst.xyzw, tmp.xxxx
3586 */
3587 unsigned tmp = get_temp_index(emit);
3588 struct tgsi_full_src_register tmp_src = make_src_temp_reg(tmp);
3589 struct tgsi_full_dst_register tmp_dst = make_dst_temp_reg(tmp);
3590
3591 struct tgsi_full_src_register tmp_src_xxxx =
3592 scalar_src(&tmp_src, TGSI_SWIZZLE_X);
3593 struct tgsi_full_dst_register tmp_dst_x =
3594 writemask_dst(&tmp_dst, TGSI_WRITEMASK_X);
3595
3596 struct tgsi_full_src_register src0_xxxx =
3597 scalar_src(&inst->Src[0], TGSI_SWIZZLE_X);
3598 struct tgsi_full_src_register src0_yyyy =
3599 scalar_src(&inst->Src[0], TGSI_SWIZZLE_Y);
3600 struct tgsi_full_src_register src1_xxxx =
3601 scalar_src(&inst->Src[1], TGSI_SWIZZLE_X);
3602 struct tgsi_full_src_register src1_yyyy =
3603 scalar_src(&inst->Src[1], TGSI_SWIZZLE_Y);
3604 struct tgsi_full_src_register src2_xxxx =
3605 scalar_src(&inst->Src[2], TGSI_SWIZZLE_X);
3606
3607 emit_instruction_op3(emit, VGPU10_OPCODE_MAD, &tmp_dst_x, &src0_yyyy,
3608 &src1_yyyy, &src2_xxxx, FALSE);
3609 emit_instruction_op3(emit, VGPU10_OPCODE_MAD, &tmp_dst_x, &src0_xxxx,
3610 &src1_xxxx, &tmp_src_xxxx, FALSE);
3611 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &inst->Dst[0],
3612 &tmp_src_xxxx, inst->Instruction.Saturate);
3613
3614 free_temp_indexes(emit);
3615
3616 return TRUE;
3617 }
3618
3619
3620 /**
3621 * Emit code for TGSI_OPCODE_DPH instruction.
3622 */
3623 static boolean
3624 emit_dph(struct svga_shader_emitter_v10 *emit,
3625 const struct tgsi_full_instruction *inst)
3626 {
3627 /*
3628 * DP3 tmp, s0, s1
3629 * ADD dst, tmp, s1.wwww
3630 */
3631
3632 struct tgsi_full_src_register s1_wwww =
3633 swizzle_src(&inst->Src[1], TGSI_SWIZZLE_W, TGSI_SWIZZLE_W,
3634 TGSI_SWIZZLE_W, TGSI_SWIZZLE_W);
3635
3636 unsigned tmp = get_temp_index(emit);
3637 struct tgsi_full_src_register tmp_src = make_src_temp_reg(tmp);
3638 struct tgsi_full_dst_register tmp_dst = make_dst_temp_reg(tmp);
3639
3640 /* DP3 tmp, s0, s1 */
3641 emit_instruction_op2(emit, VGPU10_OPCODE_DP3, &tmp_dst, &inst->Src[0],
3642 &inst->Src[1], FALSE);
3643
3644 /* ADD dst, tmp, s1.wwww */
3645 emit_instruction_op2(emit, VGPU10_OPCODE_ADD, &inst->Dst[0], &tmp_src,
3646 &s1_wwww, inst->Instruction.Saturate);
3647
3648 free_temp_indexes(emit);
3649
3650 return TRUE;
3651 }
3652
3653
3654 /**
3655 * Emit code for TGSI_OPCODE_DST instruction.
3656 */
3657 static boolean
3658 emit_dst(struct svga_shader_emitter_v10 *emit,
3659 const struct tgsi_full_instruction *inst)
3660 {
3661 /*
3662 * dst.x = 1
3663 * dst.y = src0.y * src1.y
3664 * dst.z = src0.z
3665 * dst.w = src1.w
3666 */
3667
3668 struct tgsi_full_src_register s0_yyyy =
3669 scalar_src(&inst->Src[0], TGSI_SWIZZLE_Y);
3670 struct tgsi_full_src_register s0_zzzz =
3671 scalar_src(&inst->Src[0], TGSI_SWIZZLE_Z);
3672 struct tgsi_full_src_register s1_yyyy =
3673 scalar_src(&inst->Src[1], TGSI_SWIZZLE_Y);
3674 struct tgsi_full_src_register s1_wwww =
3675 scalar_src(&inst->Src[1], TGSI_SWIZZLE_W);
3676
3677 /*
3678 * If dst and either src0 and src1 are the same we need
3679 * to create a temporary for it and insert a extra move.
3680 */
3681 unsigned tmp_move = get_temp_index(emit);
3682 struct tgsi_full_src_register move_src = make_src_temp_reg(tmp_move);
3683 struct tgsi_full_dst_register move_dst = make_dst_temp_reg(tmp_move);
3684
3685 /* MOV dst.x, 1.0 */
3686 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3687 struct tgsi_full_dst_register dst_x =
3688 writemask_dst(&move_dst, TGSI_WRITEMASK_X);
3689 struct tgsi_full_src_register one = make_immediate_reg_float(emit, 1.0f);
3690
3691 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &dst_x, &one, FALSE);
3692 }
3693
3694 /* MUL dst.y, s0.y, s1.y */
3695 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3696 struct tgsi_full_dst_register dst_y =
3697 writemask_dst(&move_dst, TGSI_WRITEMASK_Y);
3698
3699 emit_instruction_op2(emit, VGPU10_OPCODE_MUL, &dst_y, &s0_yyyy,
3700 &s1_yyyy, inst->Instruction.Saturate);
3701 }
3702
3703 /* MOV dst.z, s0.z */
3704 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3705 struct tgsi_full_dst_register dst_z =
3706 writemask_dst(&move_dst, TGSI_WRITEMASK_Z);
3707
3708 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &dst_z, &s0_zzzz,
3709 inst->Instruction.Saturate);
3710 }
3711
3712 /* MOV dst.w, s1.w */
3713 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3714 struct tgsi_full_dst_register dst_w =
3715 writemask_dst(&move_dst, TGSI_WRITEMASK_W);
3716
3717 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &dst_w, &s1_wwww,
3718 inst->Instruction.Saturate);
3719 }
3720
3721 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &inst->Dst[0], &move_src,
3722 FALSE);
3723 free_temp_indexes(emit);
3724
3725 return TRUE;
3726 }
3727
3728
3729
3730 /**
3731 * Emit code for TGSI_OPCODE_ENDPRIM (GS only)
3732 */
3733 static boolean
3734 emit_endprim(struct svga_shader_emitter_v10 *emit,
3735 const struct tgsi_full_instruction *inst)
3736 {
3737 assert(emit->unit == PIPE_SHADER_GEOMETRY);
3738
3739 /* We can't use emit_simple() because the TGSI instruction has one
3740 * operand (vertex stream number) which we must ignore for VGPU10.
3741 */
3742 begin_emit_instruction(emit);
3743 emit_opcode(emit, VGPU10_OPCODE_CUT, FALSE);
3744 end_emit_instruction(emit);
3745 return TRUE;
3746 }
3747
3748
3749 /**
3750 * Emit code for TGSI_OPCODE_EX2 (2^x) instruction.
3751 */
3752 static boolean
3753 emit_ex2(struct svga_shader_emitter_v10 *emit,
3754 const struct tgsi_full_instruction *inst)
3755 {
3756 /* Note that TGSI_OPCODE_EX2 computes only one value from src.x
3757 * while VGPU10 computes four values.
3758 *
3759 * dst = EX2(src):
3760 * dst.xyzw = 2.0 ^ src.x
3761 */
3762
3763 struct tgsi_full_src_register src_xxxx =
3764 swizzle_src(&inst->Src[0], TGSI_SWIZZLE_X, TGSI_SWIZZLE_X,
3765 TGSI_SWIZZLE_X, TGSI_SWIZZLE_X);
3766
3767 /* EXP tmp, s0.xxxx */
3768 emit_instruction_op1(emit, VGPU10_OPCODE_EXP, &inst->Dst[0], &src_xxxx,
3769 inst->Instruction.Saturate);
3770
3771 return TRUE;
3772 }
3773
3774
3775 /**
3776 * Emit code for TGSI_OPCODE_EXP instruction.
3777 */
3778 static boolean
3779 emit_exp(struct svga_shader_emitter_v10 *emit,
3780 const struct tgsi_full_instruction *inst)
3781 {
3782 /*
3783 * dst.x = 2 ^ floor(s0.x)
3784 * dst.y = s0.x - floor(s0.x)
3785 * dst.z = 2 ^ s0.x
3786 * dst.w = 1.0
3787 */
3788
3789 struct tgsi_full_src_register src_xxxx =
3790 scalar_src(&inst->Src[0], TGSI_SWIZZLE_X);
3791 unsigned tmp = get_temp_index(emit);
3792 struct tgsi_full_src_register tmp_src = make_src_temp_reg(tmp);
3793 struct tgsi_full_dst_register tmp_dst = make_dst_temp_reg(tmp);
3794
3795 /*
3796 * If dst and src are the same we need to create
3797 * a temporary for it and insert a extra move.
3798 */
3799 unsigned tmp_move = get_temp_index(emit);
3800 struct tgsi_full_src_register move_src = make_src_temp_reg(tmp_move);
3801 struct tgsi_full_dst_register move_dst = make_dst_temp_reg(tmp_move);
3802
3803 /* only use X component of temp reg */
3804 tmp_dst = writemask_dst(&tmp_dst, TGSI_WRITEMASK_X);
3805 tmp_src = scalar_src(&tmp_src, TGSI_SWIZZLE_X);
3806
3807 /* ROUND_NI tmp.x, s0.x */
3808 emit_instruction_op1(emit, VGPU10_OPCODE_ROUND_NI, &tmp_dst,
3809 &src_xxxx, FALSE); /* round to -infinity */
3810
3811 /* EXP dst.x, tmp.x */
3812 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3813 struct tgsi_full_dst_register dst_x =
3814 writemask_dst(&move_dst, TGSI_WRITEMASK_X);
3815
3816 emit_instruction_op1(emit, VGPU10_OPCODE_EXP, &dst_x, &tmp_src,
3817 inst->Instruction.Saturate);
3818 }
3819
3820 /* ADD dst.y, s0.x, -tmp */
3821 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3822 struct tgsi_full_dst_register dst_y =
3823 writemask_dst(&move_dst, TGSI_WRITEMASK_Y);
3824 struct tgsi_full_src_register neg_tmp_src = negate_src(&tmp_src);
3825
3826 emit_instruction_op2(emit, VGPU10_OPCODE_ADD, &dst_y, &src_xxxx,
3827 &neg_tmp_src, inst->Instruction.Saturate);
3828 }
3829
3830 /* EXP dst.z, s0.x */
3831 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3832 struct tgsi_full_dst_register dst_z =
3833 writemask_dst(&move_dst, TGSI_WRITEMASK_Z);
3834
3835 emit_instruction_op1(emit, VGPU10_OPCODE_EXP, &dst_z, &src_xxxx,
3836 inst->Instruction.Saturate);
3837 }
3838
3839 /* MOV dst.w, 1.0 */
3840 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3841 struct tgsi_full_dst_register dst_w =
3842 writemask_dst(&move_dst, TGSI_WRITEMASK_W);
3843 struct tgsi_full_src_register one = make_immediate_reg_float(emit, 1.0f);
3844
3845 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &dst_w, &one,
3846 FALSE);
3847 }
3848
3849 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &inst->Dst[0], &move_src,
3850 FALSE);
3851
3852 free_temp_indexes(emit);
3853
3854 return TRUE;
3855 }
3856
3857
3858 /**
3859 * Emit code for TGSI_OPCODE_IF instruction.
3860 */
3861 static boolean
3862 emit_if(struct svga_shader_emitter_v10 *emit,
3863 const struct tgsi_full_instruction *inst)
3864 {
3865 VGPU10OpcodeToken0 opcode0;
3866
3867 /* The src register should be a scalar */
3868 assert(inst->Src[0].Register.SwizzleX == inst->Src[0].Register.SwizzleY &&
3869 inst->Src[0].Register.SwizzleX == inst->Src[0].Register.SwizzleZ &&
3870 inst->Src[0].Register.SwizzleX == inst->Src[0].Register.SwizzleW);
3871
3872 /* The only special thing here is that we need to set the
3873 * VGPU10_INSTRUCTION_TEST_NONZERO flag since we want to test if
3874 * src.x is non-zero.
3875 */
3876 opcode0.value = 0;
3877 opcode0.opcodeType = VGPU10_OPCODE_IF;
3878 opcode0.testBoolean = VGPU10_INSTRUCTION_TEST_NONZERO;
3879
3880 begin_emit_instruction(emit);
3881 emit_dword(emit, opcode0.value);
3882 emit_src_register(emit, &inst->Src[0]);
3883 end_emit_instruction(emit);
3884
3885 return TRUE;
3886 }
3887
3888
3889 /**
3890 * Emit code for TGSI_OPCODE_KILL_IF instruction (kill fragment if any of
3891 * the register components are negative).
3892 */
3893 static boolean
3894 emit_kill_if(struct svga_shader_emitter_v10 *emit,
3895 const struct tgsi_full_instruction *inst)
3896 {
3897 unsigned tmp = get_temp_index(emit);
3898 struct tgsi_full_src_register tmp_src = make_src_temp_reg(tmp);
3899 struct tgsi_full_dst_register tmp_dst = make_dst_temp_reg(tmp);
3900
3901 struct tgsi_full_src_register zero = make_immediate_reg_float(emit, 0.0f);
3902
3903 struct tgsi_full_dst_register tmp_dst_x =
3904 writemask_dst(&tmp_dst, TGSI_WRITEMASK_X);
3905 struct tgsi_full_src_register tmp_src_xxxx =
3906 scalar_src(&tmp_src, TGSI_SWIZZLE_X);
3907
3908 /* tmp = src[0] < 0.0 */
3909 emit_instruction_op2(emit, VGPU10_OPCODE_LT, &tmp_dst, &inst->Src[0],
3910 &zero, FALSE);
3911
3912 if (!same_swizzle_terms(&inst->Src[0])) {
3913 /* If the swizzle is not XXXX, YYYY, ZZZZ or WWWW we need to
3914 * logically OR the swizzle terms. Most uses of KILL_IF only
3915 * test one channel so it's good to avoid these extra steps.
3916 */
3917 struct tgsi_full_src_register tmp_src_yyyy =
3918 scalar_src(&tmp_src, TGSI_SWIZZLE_Y);
3919 struct tgsi_full_src_register tmp_src_zzzz =
3920 scalar_src(&tmp_src, TGSI_SWIZZLE_Z);
3921 struct tgsi_full_src_register tmp_src_wwww =
3922 scalar_src(&tmp_src, TGSI_SWIZZLE_W);
3923
3924 emit_instruction_op2(emit, VGPU10_OPCODE_OR, &tmp_dst_x, &tmp_src_xxxx,
3925 &tmp_src_yyyy, FALSE);
3926 emit_instruction_op2(emit, VGPU10_OPCODE_OR, &tmp_dst_x, &tmp_src_xxxx,
3927 &tmp_src_zzzz, FALSE);
3928 emit_instruction_op2(emit, VGPU10_OPCODE_OR, &tmp_dst_x, &tmp_src_xxxx,
3929 &tmp_src_wwww, FALSE);
3930 }
3931
3932 begin_emit_instruction(emit);
3933 emit_discard_opcode(emit, TRUE); /* discard if src0.x is non-zero */
3934 emit_src_register(emit, &tmp_src_xxxx);
3935 end_emit_instruction(emit);
3936
3937 free_temp_indexes(emit);
3938
3939 return TRUE;
3940 }
3941
3942
3943 /**
3944 * Emit code for TGSI_OPCODE_KILL instruction (unconditional discard).
3945 */
3946 static boolean
3947 emit_kill(struct svga_shader_emitter_v10 *emit,
3948 const struct tgsi_full_instruction *inst)
3949 {
3950 struct tgsi_full_src_register zero = make_immediate_reg_float(emit, 0.0f);
3951
3952 /* DISCARD if 0.0 is zero */
3953 begin_emit_instruction(emit);
3954 emit_discard_opcode(emit, FALSE);
3955 emit_src_register(emit, &zero);
3956 end_emit_instruction(emit);
3957
3958 return TRUE;
3959 }
3960
3961
3962 /**
3963 * Emit code for TGSI_OPCODE_LG2 instruction.
3964 */
3965 static boolean
3966 emit_lg2(struct svga_shader_emitter_v10 *emit,
3967 const struct tgsi_full_instruction *inst)
3968 {
3969 /* Note that TGSI_OPCODE_LG2 computes only one value from src.x
3970 * while VGPU10 computes four values.
3971 *
3972 * dst = LG2(src):
3973 * dst.xyzw = log2(src.x)
3974 */
3975
3976 struct tgsi_full_src_register src_xxxx =
3977 swizzle_src(&inst->Src[0], TGSI_SWIZZLE_X, TGSI_SWIZZLE_X,
3978 TGSI_SWIZZLE_X, TGSI_SWIZZLE_X);
3979
3980 /* LOG tmp, s0.xxxx */
3981 emit_instruction_op1(emit, VGPU10_OPCODE_LOG, &inst->Dst[0], &src_xxxx,
3982 inst->Instruction.Saturate);
3983
3984 return TRUE;
3985 }
3986
3987
3988 /**
3989 * Emit code for TGSI_OPCODE_LIT instruction.
3990 */
3991 static boolean
3992 emit_lit(struct svga_shader_emitter_v10 *emit,
3993 const struct tgsi_full_instruction *inst)
3994 {
3995 struct tgsi_full_src_register one = make_immediate_reg_float(emit, 1.0f);
3996
3997 /*
3998 * If dst and src are the same we need to create
3999 * a temporary for it and insert a extra move.
4000 */
4001 unsigned tmp_move = get_temp_index(emit);
4002 struct tgsi_full_src_register move_src = make_src_temp_reg(tmp_move);
4003 struct tgsi_full_dst_register move_dst = make_dst_temp_reg(tmp_move);
4004
4005 /*
4006 * dst.x = 1
4007 * dst.y = max(src.x, 0)
4008 * dst.z = (src.x > 0) ? max(src.y, 0)^{clamp(src.w, -128, 128))} : 0
4009 * dst.w = 1
4010 */
4011
4012 /* MOV dst.x, 1.0 */
4013 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
4014 struct tgsi_full_dst_register dst_x =
4015 writemask_dst(&move_dst, TGSI_WRITEMASK_X);
4016 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &dst_x, &one, FALSE);
4017 }
4018
4019 /* MOV dst.w, 1.0 */
4020 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
4021 struct tgsi_full_dst_register dst_w =
4022 writemask_dst(&move_dst, TGSI_WRITEMASK_W);
4023 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &dst_w, &one, FALSE);
4024 }
4025
4026 /* MAX dst.y, src.x, 0.0 */
4027 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
4028 struct tgsi_full_dst_register dst_y =
4029 writemask_dst(&move_dst, TGSI_WRITEMASK_Y);
4030 struct tgsi_full_src_register zero =
4031 make_immediate_reg_float(emit, 0.0f);
4032 struct tgsi_full_src_register src_xxxx =
4033 swizzle_src(&inst->Src[0], TGSI_SWIZZLE_X, TGSI_SWIZZLE_X,
4034 TGSI_SWIZZLE_X, TGSI_SWIZZLE_X);
4035
4036 emit_instruction_op2(emit, VGPU10_OPCODE_MAX, &dst_y, &src_xxxx,
4037 &zero, inst->Instruction.Saturate);
4038 }
4039
4040 /*
4041 * tmp1 = clamp(src.w, -128, 128);
4042 * MAX tmp1, src.w, -128
4043 * MIN tmp1, tmp1, 128
4044 *
4045 * tmp2 = max(tmp2, 0);
4046 * MAX tmp2, src.y, 0
4047 *
4048 * tmp1 = pow(tmp2, tmp1);
4049 * LOG tmp2, tmp2
4050 * MUL tmp1, tmp2, tmp1
4051 * EXP tmp1, tmp1
4052 *
4053 * tmp1 = (src.w == 0) ? 1 : tmp1;
4054 * EQ tmp2, 0, src.w
4055 * MOVC tmp1, tmp2, 1.0, tmp1
4056 *
4057 * dst.z = (0 < src.x) ? tmp1 : 0;
4058 * LT tmp2, 0, src.x
4059 * MOVC dst.z, tmp2, tmp1, 0.0
4060 */
4061 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
4062 struct tgsi_full_dst_register dst_z =
4063 writemask_dst(&move_dst, TGSI_WRITEMASK_Z);
4064
4065 unsigned tmp1 = get_temp_index(emit);
4066 struct tgsi_full_src_register tmp1_src = make_src_temp_reg(tmp1);
4067 struct tgsi_full_dst_register tmp1_dst = make_dst_temp_reg(tmp1);
4068 unsigned tmp2 = get_temp_index(emit);
4069 struct tgsi_full_src_register tmp2_src = make_src_temp_reg(tmp2);
4070 struct tgsi_full_dst_register tmp2_dst = make_dst_temp_reg(tmp2);
4071
4072 struct tgsi_full_src_register src_xxxx =
4073 scalar_src(&inst->Src[0], TGSI_SWIZZLE_X);
4074 struct tgsi_full_src_register src_yyyy =
4075 scalar_src(&inst->Src[0], TGSI_SWIZZLE_Y);
4076 struct tgsi_full_src_register src_wwww =
4077 scalar_src(&inst->Src[0], TGSI_SWIZZLE_W);
4078
4079 struct tgsi_full_src_register zero =
4080 make_immediate_reg_float(emit, 0.0f);
4081 struct tgsi_full_src_register lowerbound =
4082 make_immediate_reg_float(emit, -128.0f);
4083 struct tgsi_full_src_register upperbound =
4084 make_immediate_reg_float(emit, 128.0f);
4085
4086 emit_instruction_op2(emit, VGPU10_OPCODE_MAX, &tmp1_dst, &src_wwww,
4087 &lowerbound, FALSE);
4088 emit_instruction_op2(emit, VGPU10_OPCODE_MIN, &tmp1_dst, &tmp1_src,
4089 &upperbound, FALSE);
4090 emit_instruction_op2(emit, VGPU10_OPCODE_MAX, &tmp2_dst, &src_yyyy,
4091 &zero, FALSE);
4092
4093 /* POW tmp1, tmp2, tmp1 */
4094 /* LOG tmp2, tmp2 */
4095 emit_instruction_op1(emit, VGPU10_OPCODE_LOG, &tmp2_dst, &tmp2_src,
4096 FALSE);
4097
4098 /* MUL tmp1, tmp2, tmp1 */
4099 emit_instruction_op2(emit, VGPU10_OPCODE_MUL, &tmp1_dst, &tmp2_src,
4100 &tmp1_src, FALSE);
4101
4102 /* EXP tmp1, tmp1 */
4103 emit_instruction_op1(emit, VGPU10_OPCODE_EXP, &tmp1_dst, &tmp1_src,
4104 FALSE);
4105
4106 /* EQ tmp2, 0, src.w */
4107 emit_instruction_op2(emit, VGPU10_OPCODE_EQ, &tmp2_dst, &zero,
4108 &src_wwww, FALSE);
4109 /* MOVC tmp1.z, tmp2, tmp1, 1.0 */
4110 emit_instruction_op3(emit, VGPU10_OPCODE_MOVC, &tmp1_dst,
4111 &tmp2_src, &one, &tmp1_src, FALSE);
4112
4113 /* LT tmp2, 0, src.x */
4114 emit_instruction_op2(emit, VGPU10_OPCODE_LT, &tmp2_dst, &zero,
4115 &src_xxxx, FALSE);
4116 /* MOVC dst.z, tmp2, tmp1, 0.0 */
4117 emit_instruction_op3(emit, VGPU10_OPCODE_MOVC, &dst_z,
4118 &tmp2_src, &tmp1_src, &zero, FALSE);
4119 }
4120
4121 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &inst->Dst[0], &move_src,
4122 FALSE);
4123 free_temp_indexes(emit);
4124
4125 return TRUE;
4126 }
4127
4128
4129 /**
4130 * Emit code for TGSI_OPCODE_LOG instruction.
4131 */
4132 static boolean
4133 emit_log(struct svga_shader_emitter_v10 *emit,
4134 const struct tgsi_full_instruction *inst)
4135 {
4136 /*
4137 * dst.x = floor(lg2(abs(s0.x)))
4138 * dst.y = abs(s0.x) / (2 ^ floor(lg2(abs(s0.x))))
4139 * dst.z = lg2(abs(s0.x))
4140 * dst.w = 1.0
4141 */
4142
4143 struct tgsi_full_src_register src_xxxx =
4144 scalar_src(&inst->Src[0], TGSI_SWIZZLE_X);
4145 unsigned tmp = get_temp_index(emit);
4146 struct tgsi_full_src_register tmp_src = make_src_temp_reg(tmp);
4147 struct tgsi_full_dst_register tmp_dst = make_dst_temp_reg(tmp);
4148 struct tgsi_full_src_register abs_src_xxxx = absolute_src(&src_xxxx);
4149
4150 /* only use X component of temp reg */
4151 tmp_dst = writemask_dst(&tmp_dst, TGSI_WRITEMASK_X);
4152 tmp_src = scalar_src(&tmp_src, TGSI_SWIZZLE_X);
4153
4154 /* LOG tmp.x, abs(s0.x) */
4155 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XYZ) {
4156 emit_instruction_op1(emit, VGPU10_OPCODE_LOG, &tmp_dst,
4157 &abs_src_xxxx, FALSE);
4158 }
4159
4160 /* MOV dst.z, tmp.x */
4161 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
4162 struct tgsi_full_dst_register dst_z =
4163 writemask_dst(&inst->Dst[0], TGSI_WRITEMASK_Z);
4164
4165 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &dst_z,
4166 &tmp_src, inst->Instruction.Saturate);
4167 }
4168
4169 /* FLR tmp.x, tmp.x */
4170 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) {
4171 emit_instruction_op1(emit, VGPU10_OPCODE_ROUND_NI, &tmp_dst,
4172 &tmp_src, FALSE);
4173 }
4174
4175 /* MOV dst.x, tmp.x */
4176 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
4177 struct tgsi_full_dst_register dst_x =
4178 writemask_dst(&inst->Dst[0], TGSI_WRITEMASK_X);
4179
4180 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &dst_x, &tmp_src,
4181 inst->Instruction.Saturate);
4182 }
4183
4184 /* EXP tmp.x, tmp.x */
4185 /* DIV dst.y, abs(s0.x), tmp.x */
4186 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
4187 struct tgsi_full_dst_register dst_y =
4188 writemask_dst(&inst->Dst[0], TGSI_WRITEMASK_Y);
4189
4190 emit_instruction_op1(emit, VGPU10_OPCODE_EXP, &tmp_dst, &tmp_src,
4191 FALSE);
4192 emit_instruction_op2(emit, VGPU10_OPCODE_DIV, &dst_y, &abs_src_xxxx,
4193 &tmp_src, inst->Instruction.Saturate);
4194 }
4195
4196 /* MOV dst.w, 1.0 */
4197 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
4198 struct tgsi_full_dst_register dst_w =
4199 writemask_dst(&inst->Dst[0], TGSI_WRITEMASK_W);
4200 struct tgsi_full_src_register one =
4201 make_immediate_reg_float(emit, 1.0f);
4202
4203 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &dst_w, &one, FALSE);
4204 }
4205
4206 free_temp_indexes(emit);
4207
4208 return TRUE;
4209 }
4210
4211
4212 /**
4213 * Emit code for TGSI_OPCODE_LRP instruction.
4214 */
4215 static boolean
4216 emit_lrp(struct svga_shader_emitter_v10 *emit,
4217 const struct tgsi_full_instruction *inst)
4218 {
4219 /* dst = LRP(s0, s1, s2):
4220 * dst = s0 * (s1 - s2) + s2
4221 * Translates into:
4222 * SUB tmp, s1, s2; tmp = s1 - s2
4223 * MAD dst, s0, tmp, s2; dst = s0 * t1 + s2
4224 */
4225 unsigned tmp = get_temp_index(emit);
4226 struct tgsi_full_src_register src_tmp = make_src_temp_reg(tmp);
4227 struct tgsi_full_dst_register dst_tmp = make_dst_temp_reg(tmp);
4228 struct tgsi_full_src_register neg_src2 = negate_src(&inst->Src[2]);
4229
4230 /* ADD tmp, s1, -s2 */
4231 emit_instruction_op2(emit, VGPU10_OPCODE_ADD, &dst_tmp,
4232 &inst->Src[1], &neg_src2, FALSE);
4233
4234 /* MAD dst, s1, tmp, s3 */
4235 emit_instruction_op3(emit, VGPU10_OPCODE_MAD, &inst->Dst[0],
4236 &inst->Src[0], &src_tmp, &inst->Src[2],
4237 inst->Instruction.Saturate);
4238
4239 free_temp_indexes(emit);
4240
4241 return TRUE;
4242 }
4243
4244
4245 /**
4246 * Emit code for TGSI_OPCODE_POW instruction.
4247 */
4248 static boolean
4249 emit_pow(struct svga_shader_emitter_v10 *emit,
4250 const struct tgsi_full_instruction *inst)
4251 {
4252 /* Note that TGSI_OPCODE_POW computes only one value from src0.x and
4253 * src1.x while VGPU10 computes four values.
4254 *
4255 * dst = POW(src0, src1):
4256 * dst.xyzw = src0.x ^ src1.x
4257 */
4258 unsigned tmp = get_temp_index(emit);
4259 struct tgsi_full_src_register tmp_src = make_src_temp_reg(tmp);
4260 struct tgsi_full_dst_register tmp_dst = make_dst_temp_reg(tmp);
4261 struct tgsi_full_src_register src0_xxxx =
4262 swizzle_src(&inst->Src[0], TGSI_SWIZZLE_X, TGSI_SWIZZLE_X,
4263 TGSI_SWIZZLE_X, TGSI_SWIZZLE_X);
4264 struct tgsi_full_src_register src1_xxxx =
4265 swizzle_src(&inst->Src[1], TGSI_SWIZZLE_X, TGSI_SWIZZLE_X,
4266 TGSI_SWIZZLE_X, TGSI_SWIZZLE_X);
4267
4268 /* LOG tmp, s0.xxxx */
4269 emit_instruction_op1(emit, VGPU10_OPCODE_LOG, &tmp_dst, &src0_xxxx,
4270 FALSE);
4271
4272 /* MUL tmp, tmp, s1.xxxx */
4273 emit_instruction_op2(emit, VGPU10_OPCODE_MUL, &tmp_dst, &tmp_src,
4274 &src1_xxxx, FALSE);
4275
4276 /* EXP tmp, s0.xxxx */
4277 emit_instruction_op1(emit, VGPU10_OPCODE_EXP, &inst->Dst[0],
4278 &tmp_src, inst->Instruction.Saturate);
4279
4280 /* free tmp */
4281 free_temp_indexes(emit);
4282
4283 return TRUE;
4284 }
4285
4286
4287 /**
4288 * Emit code for TGSI_OPCODE_RCP (reciprocal) instruction.
4289 */
4290 static boolean
4291 emit_rcp(struct svga_shader_emitter_v10 *emit,
4292 const struct tgsi_full_instruction *inst)
4293 {
4294 struct tgsi_full_src_register one = make_immediate_reg_float(emit, 1.0f);
4295
4296 unsigned tmp = get_temp_index(emit);
4297 struct tgsi_full_src_register tmp_src = make_src_temp_reg(tmp);
4298 struct tgsi_full_dst_register tmp_dst = make_dst_temp_reg(tmp);
4299
4300 struct tgsi_full_dst_register tmp_dst_x =
4301 writemask_dst(&tmp_dst, TGSI_WRITEMASK_X);
4302 struct tgsi_full_src_register tmp_src_xxxx =
4303 scalar_src(&tmp_src, TGSI_SWIZZLE_X);
4304
4305 /* DIV tmp.x, 1.0, s0 */
4306 emit_instruction_op2(emit, VGPU10_OPCODE_DIV, &tmp_dst_x, &one,
4307 &inst->Src[0], FALSE);
4308
4309 /* MOV dst, tmp.xxxx */
4310 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &inst->Dst[0],
4311 &tmp_src_xxxx, inst->Instruction.Saturate);
4312
4313 free_temp_indexes(emit);
4314
4315 return TRUE;
4316 }
4317
4318
4319 /**
4320 * Emit code for TGSI_OPCODE_RSQ instruction.
4321 */
4322 static boolean
4323 emit_rsq(struct svga_shader_emitter_v10 *emit,
4324 const struct tgsi_full_instruction *inst)
4325 {
4326 /* dst = RSQ(src):
4327 * dst.xyzw = 1 / sqrt(src.x)
4328 * Translates into:
4329 * RSQ tmp, src.x
4330 * MOV dst, tmp.xxxx
4331 */
4332
4333 unsigned tmp = get_temp_index(emit);
4334 struct tgsi_full_src_register tmp_src = make_src_temp_reg(tmp);
4335 struct tgsi_full_dst_register tmp_dst = make_dst_temp_reg(tmp);
4336
4337 struct tgsi_full_dst_register tmp_dst_x =
4338 writemask_dst(&tmp_dst, TGSI_WRITEMASK_X);
4339 struct tgsi_full_src_register tmp_src_xxxx =
4340 scalar_src(&tmp_src, TGSI_SWIZZLE_X);
4341
4342 /* RSQ tmp, src.x */
4343 emit_instruction_op1(emit, VGPU10_OPCODE_RSQ, &tmp_dst_x,
4344 &inst->Src[0], FALSE);
4345
4346 /* MOV dst, tmp.xxxx */
4347 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &inst->Dst[0],
4348 &tmp_src_xxxx, inst->Instruction.Saturate);
4349
4350 /* free tmp */
4351 free_temp_indexes(emit);
4352
4353 return TRUE;
4354 }
4355
4356
4357 /**
4358 * Emit code for TGSI_OPCODE_SCS instruction.
4359 */
4360 static boolean
4361 emit_scs(struct svga_shader_emitter_v10 *emit,
4362 const struct tgsi_full_instruction *inst)
4363 {
4364 /* dst.x = cos(src.x)
4365 * dst.y = sin(src.x)
4366 * dst.z = 0.0
4367 * dst.w = 1.0
4368 */
4369 struct tgsi_full_dst_register dst_x =
4370 writemask_dst(&inst->Dst[0], TGSI_WRITEMASK_X);
4371 struct tgsi_full_dst_register dst_y =
4372 writemask_dst(&inst->Dst[0], TGSI_WRITEMASK_Y);
4373 struct tgsi_full_dst_register dst_zw =
4374 writemask_dst(&inst->Dst[0], TGSI_WRITEMASK_ZW);
4375
4376 struct tgsi_full_src_register zero_one =
4377 make_immediate_reg_float4(emit, 0.0f, 0.0f, 0.0f, 1.0f);
4378
4379 begin_emit_instruction(emit);
4380 emit_opcode(emit, VGPU10_OPCODE_SINCOS, inst->Instruction.Saturate);
4381 emit_dst_register(emit, &dst_y);
4382 emit_dst_register(emit, &dst_x);
4383 emit_src_register(emit, &inst->Src[0]);
4384 end_emit_instruction(emit);
4385
4386 emit_instruction_op1(emit, VGPU10_OPCODE_MOV,
4387 &dst_zw, &zero_one, inst->Instruction.Saturate);
4388
4389 return TRUE;
4390 }
4391
4392
4393 /**
4394 * Emit code for TGSI_OPCODE_SEQ (Set Equal) instruction.
4395 */
4396 static boolean
4397 emit_seq(struct svga_shader_emitter_v10 *emit,
4398 const struct tgsi_full_instruction *inst)
4399 {
4400 /* dst = SEQ(s0, s1):
4401 * dst = s0 == s1 ? 1.0 : 0.0 (per component)
4402 * Translates into:
4403 * EQ tmp, s0, s1; tmp = s0 == s1 : 0xffffffff : 0 (per comp)
4404 * MOVC dst, tmp, 1.0, 0.0; dst = tmp ? 1.0 : 0.0 (per component)
4405 */
4406 unsigned tmp = get_temp_index(emit);
4407 struct tgsi_full_src_register tmp_src = make_src_temp_reg(tmp);
4408 struct tgsi_full_dst_register tmp_dst = make_dst_temp_reg(tmp);
4409 struct tgsi_full_src_register zero = make_immediate_reg_float(emit, 0.0f);
4410 struct tgsi_full_src_register one = make_immediate_reg_float(emit, 1.0f);
4411
4412 /* EQ tmp, s0, s1 */
4413 emit_instruction_op2(emit, VGPU10_OPCODE_EQ, &tmp_dst, &inst->Src[0],
4414 &inst->Src[1], FALSE);
4415
4416 /* MOVC dst, tmp, one, zero */
4417 emit_instruction_op3(emit, VGPU10_OPCODE_MOVC, &inst->Dst[0], &tmp_src,
4418 &one, &zero, FALSE);
4419
4420 free_temp_indexes(emit);
4421
4422 return TRUE;
4423 }
4424
4425
4426 /**
4427 * Emit code for TGSI_OPCODE_SGE (Set Greater than or Equal) instruction.
4428 */
4429 static boolean
4430 emit_sge(struct svga_shader_emitter_v10 *emit,
4431 const struct tgsi_full_instruction *inst)
4432 {
4433 /* dst = SGE(s0, s1):
4434 * dst = s0 >= s1 ? 1.0 : 0.0 (per component)
4435 * Translates into:
4436 * GE tmp, s0, s1; tmp = s0 >= s1 : 0xffffffff : 0 (per comp)
4437 * MOVC dst, tmp, 1.0, 0.0; dst = tmp ? 1.0 : 0.0 (per component)
4438 */
4439 unsigned tmp = get_temp_index(emit);
4440 struct tgsi_full_src_register tmp_src = make_src_temp_reg(tmp);
4441 struct tgsi_full_dst_register tmp_dst = make_dst_temp_reg(tmp);
4442 struct tgsi_full_src_register zero = make_immediate_reg_float(emit, 0.0f);
4443 struct tgsi_full_src_register one = make_immediate_reg_float(emit, 1.0f);
4444
4445 /* GE tmp, s0, s1 */
4446 emit_instruction_op2(emit, VGPU10_OPCODE_GE, &tmp_dst, &inst->Src[0],
4447 &inst->Src[1], FALSE);
4448
4449 /* MOVC dst, tmp, one, zero */
4450 emit_instruction_op3(emit, VGPU10_OPCODE_MOVC, &inst->Dst[0], &tmp_src,
4451 &one, &zero, FALSE);
4452
4453 free_temp_indexes(emit);
4454
4455 return TRUE;
4456 }
4457
4458
4459 /**
4460 * Emit code for TGSI_OPCODE_SGT (Set Greater than) instruction.
4461 */
4462 static boolean
4463 emit_sgt(struct svga_shader_emitter_v10 *emit,
4464 const struct tgsi_full_instruction *inst)
4465 {
4466 /* dst = SGT(s0, s1):
4467 * dst = s0 > s1 ? 1.0 : 0.0 (per component)
4468 * Translates into:
4469 * LT tmp, s1, s0; tmp = s1 < s0 ? 0xffffffff : 0 (per comp)
4470 * MOVC dst, tmp, 1.0, 0.0; dst = tmp ? 1.0 : 0.0 (per component)
4471 */
4472 unsigned tmp = get_temp_index(emit);
4473 struct tgsi_full_src_register tmp_src = make_src_temp_reg(tmp);
4474 struct tgsi_full_dst_register tmp_dst = make_dst_temp_reg(tmp);
4475 struct tgsi_full_src_register zero = make_immediate_reg_float(emit, 0.0f);
4476 struct tgsi_full_src_register one = make_immediate_reg_float(emit, 1.0f);
4477
4478 /* LT tmp, s1, s0 */
4479 emit_instruction_op2(emit, VGPU10_OPCODE_LT, &tmp_dst, &inst->Src[1],
4480 &inst->Src[0], FALSE);
4481
4482 /* MOVC dst, tmp, one, zero */
4483 emit_instruction_op3(emit, VGPU10_OPCODE_MOVC, &inst->Dst[0], &tmp_src,
4484 &one, &zero, FALSE);
4485
4486 free_temp_indexes(emit);
4487
4488 return TRUE;
4489 }
4490
4491
4492 /**
4493 * Emit code for TGSI_OPCODE_SIN and TGSI_OPCODE_COS instructions.
4494 */
4495 static boolean
4496 emit_sincos(struct svga_shader_emitter_v10 *emit,
4497 const struct tgsi_full_instruction *inst)
4498 {
4499 unsigned tmp = get_temp_index(emit);
4500 struct tgsi_full_src_register tmp_src = make_src_temp_reg(tmp);
4501 struct tgsi_full_dst_register tmp_dst = make_dst_temp_reg(tmp);
4502
4503 struct tgsi_full_src_register tmp_src_xxxx =
4504 scalar_src(&tmp_src, TGSI_SWIZZLE_X);
4505 struct tgsi_full_dst_register tmp_dst_x =
4506 writemask_dst(&tmp_dst, TGSI_WRITEMASK_X);
4507
4508 begin_emit_instruction(emit);
4509 emit_opcode(emit, VGPU10_OPCODE_SINCOS, FALSE);
4510
4511 if(inst->Instruction.Opcode == TGSI_OPCODE_SIN)
4512 {
4513 emit_dst_register(emit, &tmp_dst_x); /* first destination register */
4514 emit_null_dst_register(emit); /* second destination register */
4515 }
4516 else {
4517 emit_null_dst_register(emit);
4518 emit_dst_register(emit, &tmp_dst_x);
4519 }
4520
4521 emit_src_register(emit, &inst->Src[0]);
4522 end_emit_instruction(emit);
4523
4524 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &inst->Dst[0],
4525 &tmp_src_xxxx, inst->Instruction.Saturate);
4526
4527 free_temp_indexes(emit);
4528
4529 return TRUE;
4530 }
4531
4532
4533 /**
4534 * Emit code for TGSI_OPCODE_SLE (Set Less than or Equal) instruction.
4535 */
4536 static boolean
4537 emit_sle(struct svga_shader_emitter_v10 *emit,
4538 const struct tgsi_full_instruction *inst)
4539 {
4540 /* dst = SLE(s0, s1):
4541 * dst = s0 <= s1 ? 1.0 : 0.0 (per component)
4542 * Translates into:
4543 * GE tmp, s1, s0; tmp = s1 >= s0 : 0xffffffff : 0 (per comp)
4544 * MOVC dst, tmp, 1.0, 0.0; dst = tmp ? 1.0 : 0.0 (per component)
4545 */
4546 unsigned tmp = get_temp_index(emit);
4547 struct tgsi_full_src_register tmp_src = make_src_temp_reg(tmp);
4548 struct tgsi_full_dst_register tmp_dst = make_dst_temp_reg(tmp);
4549 struct tgsi_full_src_register zero = make_immediate_reg_float(emit, 0.0f);
4550 struct tgsi_full_src_register one = make_immediate_reg_float(emit, 1.0f);
4551
4552 /* GE tmp, s1, s0 */
4553 emit_instruction_op2(emit, VGPU10_OPCODE_GE, &tmp_dst, &inst->Src[1],
4554 &inst->Src[0], FALSE);
4555
4556 /* MOVC dst, tmp, one, zero */
4557 emit_instruction_op3(emit, VGPU10_OPCODE_MOVC, &inst->Dst[0], &tmp_src,
4558 &one, &zero, FALSE);
4559
4560 free_temp_indexes(emit);
4561
4562 return TRUE;
4563 }
4564
4565
4566 /**
4567 * Emit code for TGSI_OPCODE_SLT (Set Less than) instruction.
4568 */
4569 static boolean
4570 emit_slt(struct svga_shader_emitter_v10 *emit,
4571 const struct tgsi_full_instruction *inst)
4572 {
4573 /* dst = SLT(s0, s1):
4574 * dst = s0 < s1 ? 1.0 : 0.0 (per component)
4575 * Translates into:
4576 * LT tmp, s0, s1; tmp = s0 < s1 ? 0xffffffff : 0 (per comp)
4577 * MOVC dst, tmp, 1.0, 0.0; dst = tmp ? 1.0 : 0.0 (per component)
4578 */
4579 unsigned tmp = get_temp_index(emit);
4580 struct tgsi_full_src_register tmp_src = make_src_temp_reg(tmp);
4581 struct tgsi_full_dst_register tmp_dst = make_dst_temp_reg(tmp);
4582 struct tgsi_full_src_register zero = make_immediate_reg_float(emit, 0.0f);
4583 struct tgsi_full_src_register one = make_immediate_reg_float(emit, 1.0f);
4584
4585 /* LT tmp, s0, s1 */
4586 emit_instruction_op2(emit, VGPU10_OPCODE_LT, &tmp_dst, &inst->Src[0],
4587 &inst->Src[1], FALSE);
4588
4589 /* MOVC dst, tmp, one, zero */
4590 emit_instruction_op3(emit, VGPU10_OPCODE_MOVC, &inst->Dst[0], &tmp_src,
4591 &one, &zero, FALSE);
4592
4593 free_temp_indexes(emit);
4594
4595 return TRUE;
4596 }
4597
4598
4599 /**
4600 * Emit code for TGSI_OPCODE_SNE (Set Not Equal) instruction.
4601 */
4602 static boolean
4603 emit_sne(struct svga_shader_emitter_v10 *emit,
4604 const struct tgsi_full_instruction *inst)
4605 {
4606 /* dst = SNE(s0, s1):
4607 * dst = s0 != s1 ? 1.0 : 0.0 (per component)
4608 * Translates into:
4609 * EQ tmp, s0, s1; tmp = s0 == s1 : 0xffffffff : 0 (per comp)
4610 * MOVC dst, tmp, 1.0, 0.0; dst = tmp ? 1.0 : 0.0 (per component)
4611 */
4612 unsigned tmp = get_temp_index(emit);
4613 struct tgsi_full_src_register tmp_src = make_src_temp_reg(tmp);
4614 struct tgsi_full_dst_register tmp_dst = make_dst_temp_reg(tmp);
4615 struct tgsi_full_src_register zero = make_immediate_reg_float(emit, 0.0f);
4616 struct tgsi_full_src_register one = make_immediate_reg_float(emit, 1.0f);
4617
4618 /* NE tmp, s0, s1 */
4619 emit_instruction_op2(emit, VGPU10_OPCODE_NE, &tmp_dst, &inst->Src[0],
4620 &inst->Src[1], FALSE);
4621
4622 /* MOVC dst, tmp, one, zero */
4623 emit_instruction_op3(emit, VGPU10_OPCODE_MOVC, &inst->Dst[0], &tmp_src,
4624 &one, &zero, FALSE);
4625
4626 free_temp_indexes(emit);
4627
4628 return TRUE;
4629 }
4630
4631
4632 /**
4633 * Emit code for TGSI_OPCODE_SSG (Set Sign) instruction.
4634 */
4635 static boolean
4636 emit_ssg(struct svga_shader_emitter_v10 *emit,
4637 const struct tgsi_full_instruction *inst)
4638 {
4639 /* dst.x = (src.x > 0.0) ? 1.0 : (src.x < 0.0) ? -1.0 : 0.0
4640 * dst.y = (src.y > 0.0) ? 1.0 : (src.y < 0.0) ? -1.0 : 0.0
4641 * dst.z = (src.z > 0.0) ? 1.0 : (src.z < 0.0) ? -1.0 : 0.0
4642 * dst.w = (src.w > 0.0) ? 1.0 : (src.w < 0.0) ? -1.0 : 0.0
4643 * Translates into:
4644 * LT tmp1, src, zero; tmp1 = src < zero ? 0xffffffff : 0 (per comp)
4645 * MOVC tmp2, tmp1, -1.0, 0.0; tmp2 = tmp1 ? -1.0 : 0.0 (per component)
4646 * LT tmp1, zero, src; tmp1 = zero < src ? 0xffffffff : 0 (per comp)
4647 * MOVC dst, tmp1, 1.0, tmp2; dst = tmp1 ? 1.0 : tmp2 (per component)
4648 */
4649 struct tgsi_full_src_register zero =
4650 make_immediate_reg_float(emit, 0.0f);
4651 struct tgsi_full_src_register one =
4652 make_immediate_reg_float(emit, 1.0f);
4653 struct tgsi_full_src_register neg_one =
4654 make_immediate_reg_float(emit, -1.0f);
4655
4656 unsigned tmp1 = get_temp_index(emit);
4657 struct tgsi_full_src_register tmp1_src = make_src_temp_reg(tmp1);
4658 struct tgsi_full_dst_register tmp1_dst = make_dst_temp_reg(tmp1);
4659
4660 unsigned tmp2 = get_temp_index(emit);
4661 struct tgsi_full_src_register tmp2_src = make_src_temp_reg(tmp2);
4662 struct tgsi_full_dst_register tmp2_dst = make_dst_temp_reg(tmp2);
4663
4664 emit_instruction_op2(emit, VGPU10_OPCODE_LT, &tmp1_dst, &inst->Src[0],
4665 &zero, FALSE);
4666 emit_instruction_op3(emit, VGPU10_OPCODE_MOVC, &tmp2_dst, &tmp1_src,
4667 &neg_one, &zero, FALSE);
4668 emit_instruction_op2(emit, VGPU10_OPCODE_LT, &tmp1_dst, &zero,
4669 &inst->Src[0], FALSE);
4670 emit_instruction_op3(emit, VGPU10_OPCODE_MOVC, &inst->Dst[0], &tmp1_src,
4671 &one, &tmp2_src, FALSE);
4672
4673 free_temp_indexes(emit);
4674
4675 return TRUE;
4676 }
4677
4678
4679 /**
4680 * Emit code for TGSI_OPCODE_ISSG (Integer Set Sign) instruction.
4681 */
4682 static boolean
4683 emit_issg(struct svga_shader_emitter_v10 *emit,
4684 const struct tgsi_full_instruction *inst)
4685 {
4686 /* dst.x = (src.x > 0) ? 1 : (src.x < 0) ? -1 : 0
4687 * dst.y = (src.y > 0) ? 1 : (src.y < 0) ? -1 : 0
4688 * dst.z = (src.z > 0) ? 1 : (src.z < 0) ? -1 : 0
4689 * dst.w = (src.w > 0) ? 1 : (src.w < 0) ? -1 : 0
4690 * Translates into:
4691 * ILT tmp1, src, 0 tmp1 = src < 0 ? -1 : 0 (per component)
4692 * ILT tmp2, 0, src tmp2 = 0 < src ? -1 : 0 (per component)
4693 * IADD dst, tmp1, neg(tmp2) dst = tmp1 - tmp2 (per component)
4694 */
4695 struct tgsi_full_src_register zero = make_immediate_reg_float(emit, 0.0f);
4696
4697 unsigned tmp1 = get_temp_index(emit);
4698 struct tgsi_full_src_register tmp1_src = make_src_temp_reg(tmp1);
4699 struct tgsi_full_dst_register tmp1_dst = make_dst_temp_reg(tmp1);
4700
4701 unsigned tmp2 = get_temp_index(emit);
4702 struct tgsi_full_src_register tmp2_src = make_src_temp_reg(tmp2);
4703 struct tgsi_full_dst_register tmp2_dst = make_dst_temp_reg(tmp2);
4704
4705 struct tgsi_full_src_register neg_tmp2 = negate_src(&tmp2_src);
4706
4707 emit_instruction_op2(emit, VGPU10_OPCODE_ILT, &tmp1_dst,
4708 &inst->Src[0], &zero, FALSE);
4709 emit_instruction_op2(emit, VGPU10_OPCODE_ILT, &tmp2_dst,
4710 &zero, &inst->Src[0], FALSE);
4711 emit_instruction_op2(emit, VGPU10_OPCODE_IADD, &inst->Dst[0],
4712 &tmp1_src, &neg_tmp2, FALSE);
4713
4714 free_temp_indexes(emit);
4715
4716 return TRUE;
4717 }
4718
4719
4720 /**
4721 * Emit a comparison instruction. The dest register will get
4722 * 0 or ~0 values depending on the outcome of comparing src0 to src1.
4723 */
4724 static void
4725 emit_comparison(struct svga_shader_emitter_v10 *emit,
4726 SVGA3dCmpFunc func,
4727 const struct tgsi_full_dst_register *dst,
4728 const struct tgsi_full_src_register *src0,
4729 const struct tgsi_full_src_register *src1)
4730 {
4731 struct tgsi_full_src_register immediate;
4732 VGPU10OpcodeToken0 opcode0;
4733 boolean swapSrc = FALSE;
4734
4735 /* Sanity checks for svga vs. gallium enums */
4736 STATIC_ASSERT(SVGA3D_CMP_LESS == (PIPE_FUNC_LESS + 1));
4737 STATIC_ASSERT(SVGA3D_CMP_GREATEREQUAL == (PIPE_FUNC_GEQUAL + 1));
4738
4739 opcode0.value = 0;
4740
4741 switch (func) {
4742 case SVGA3D_CMP_NEVER:
4743 immediate = make_immediate_reg_int(emit, 0);
4744 /* MOV dst, {0} */
4745 begin_emit_instruction(emit);
4746 emit_dword(emit, VGPU10_OPCODE_MOV);
4747 emit_dst_register(emit, dst);
4748 emit_src_register(emit, &immediate);
4749 end_emit_instruction(emit);
4750 return;
4751 case SVGA3D_CMP_ALWAYS:
4752 immediate = make_immediate_reg_int(emit, -1);
4753 /* MOV dst, {-1} */
4754 begin_emit_instruction(emit);
4755 emit_dword(emit, VGPU10_OPCODE_MOV);
4756 emit_dst_register(emit, dst);
4757 emit_src_register(emit, &immediate);
4758 end_emit_instruction(emit);
4759 return;
4760 case SVGA3D_CMP_LESS:
4761 opcode0.opcodeType = VGPU10_OPCODE_LT;
4762 break;
4763 case SVGA3D_CMP_EQUAL:
4764 opcode0.opcodeType = VGPU10_OPCODE_EQ;
4765 break;
4766 case SVGA3D_CMP_LESSEQUAL:
4767 opcode0.opcodeType = VGPU10_OPCODE_GE;
4768 swapSrc = TRUE;
4769 break;
4770 case SVGA3D_CMP_GREATER:
4771 opcode0.opcodeType = VGPU10_OPCODE_LT;
4772 swapSrc = TRUE;
4773 break;
4774 case SVGA3D_CMP_NOTEQUAL:
4775 opcode0.opcodeType = VGPU10_OPCODE_NE;
4776 break;
4777 case SVGA3D_CMP_GREATEREQUAL:
4778 opcode0.opcodeType = VGPU10_OPCODE_GE;
4779 break;
4780 default:
4781 assert(!"Unexpected comparison mode");
4782 opcode0.opcodeType = VGPU10_OPCODE_EQ;
4783 }
4784
4785 begin_emit_instruction(emit);
4786 emit_dword(emit, opcode0.value);
4787 emit_dst_register(emit, dst);
4788 if (swapSrc) {
4789 emit_src_register(emit, src1);
4790 emit_src_register(emit, src0);
4791 }
4792 else {
4793 emit_src_register(emit, src0);
4794 emit_src_register(emit, src1);
4795 }
4796 end_emit_instruction(emit);
4797 }
4798
4799
4800 /**
4801 * Get texel/address offsets for a texture instruction.
4802 */
4803 static void
4804 get_texel_offsets(const struct svga_shader_emitter_v10 *emit,
4805 const struct tgsi_full_instruction *inst, int offsets[3])
4806 {
4807 if (inst->Texture.NumOffsets == 1) {
4808 /* According to OpenGL Shader Language spec the offsets are only
4809 * fetched from a previously-declared immediate/literal.
4810 */
4811 const struct tgsi_texture_offset *off = inst->TexOffsets;
4812 const unsigned index = off[0].Index;
4813 const unsigned swizzleX = off[0].SwizzleX;
4814 const unsigned swizzleY = off[0].SwizzleY;
4815 const unsigned swizzleZ = off[0].SwizzleZ;
4816 const union tgsi_immediate_data *imm = emit->immediates[index];
4817
4818 assert(inst->TexOffsets[0].File == TGSI_FILE_IMMEDIATE);
4819
4820 offsets[0] = imm[swizzleX].Int;
4821 offsets[1] = imm[swizzleY].Int;
4822 offsets[2] = imm[swizzleZ].Int;
4823 }
4824 else {
4825 offsets[0] = offsets[1] = offsets[2] = 0;
4826 }
4827 }
4828
4829
4830 /**
4831 * Set up the coordinate register for texture sampling.
4832 * When we're sampling from a RECT texture we have to scale the
4833 * unnormalized coordinate to a normalized coordinate.
4834 * We do that by multiplying the coordinate by an "extra" constant.
4835 * An alternative would be to use the RESINFO instruction to query the
4836 * texture's size.
4837 */
4838 static struct tgsi_full_src_register
4839 setup_texcoord(struct svga_shader_emitter_v10 *emit,
4840 unsigned unit,
4841 const struct tgsi_full_src_register *coord)
4842 {
4843 if (emit->key.tex[unit].unnormalized) {
4844 unsigned scale_index = emit->texcoord_scale_index[unit];
4845 unsigned tmp = get_temp_index(emit);
4846 struct tgsi_full_src_register tmp_src = make_src_temp_reg(tmp);
4847 struct tgsi_full_dst_register tmp_dst = make_dst_temp_reg(tmp);
4848 struct tgsi_full_src_register scale_src = make_src_const_reg(scale_index);
4849
4850 /* MUL tmp, coord, const[] */
4851 emit_instruction_op2(emit, VGPU10_OPCODE_MUL, &tmp_dst,
4852 coord, &scale_src, FALSE);
4853 return tmp_src;
4854 }
4855 else {
4856 /* use texcoord as-is */
4857 return *coord;
4858 }
4859 }
4860
4861
4862 /**
4863 * For SAMPLE_C instructions, emit the extra src register which indicates
4864 * the reference/comparision value.
4865 */
4866 static void
4867 emit_tex_compare_refcoord(struct svga_shader_emitter_v10 *emit,
4868 unsigned target,
4869 const struct tgsi_full_src_register *coord)
4870 {
4871 struct tgsi_full_src_register coord_src_ref;
4872 unsigned component;
4873
4874 assert(tgsi_is_shadow_target(target));
4875
4876 assert(target != TGSI_TEXTURE_SHADOWCUBE_ARRAY); /* XXX not implemented */
4877 if (target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
4878 target == TGSI_TEXTURE_SHADOWCUBE)
4879 component = TGSI_SWIZZLE_W;
4880 else
4881 component = TGSI_SWIZZLE_Z;
4882
4883 coord_src_ref = scalar_src(coord, component);
4884
4885 emit_src_register(emit, &coord_src_ref);
4886 }
4887
4888
4889 /**
4890 * Info for implementing texture swizzles.
4891 * The begin_tex_swizzle(), get_tex_swizzle_dst() and end_tex_swizzle()
4892 * functions use this to encapsulate the extra steps needed to perform
4893 * a texture swizzle, or shadow/depth comparisons.
4894 * The shadow/depth comparison is only done here if for the cases where
4895 * there's no VGPU10 opcode (like texture bias lookup w/ shadow compare).
4896 */
4897 struct tex_swizzle_info
4898 {
4899 boolean swizzled;
4900 boolean shadow_compare;
4901 unsigned unit;
4902 unsigned texture_target; /**< TGSI_TEXTURE_x */
4903 struct tgsi_full_src_register tmp_src;
4904 struct tgsi_full_dst_register tmp_dst;
4905 const struct tgsi_full_dst_register *inst_dst;
4906 const struct tgsi_full_src_register *coord_src;
4907 };
4908
4909
4910 /**
4911 * Do setup for handling texture swizzles or shadow compares.
4912 * \param unit the texture unit
4913 * \param inst the TGSI texture instruction
4914 * \param shadow_compare do shadow/depth comparison?
4915 * \param swz returns the swizzle info
4916 */
4917 static void
4918 begin_tex_swizzle(struct svga_shader_emitter_v10 *emit,
4919 unsigned unit,
4920 const struct tgsi_full_instruction *inst,
4921 boolean shadow_compare,
4922 struct tex_swizzle_info *swz)
4923 {
4924 swz->swizzled = (emit->key.tex[unit].swizzle_r != TGSI_SWIZZLE_X ||
4925 emit->key.tex[unit].swizzle_g != TGSI_SWIZZLE_Y ||
4926 emit->key.tex[unit].swizzle_b != TGSI_SWIZZLE_Z ||
4927 emit->key.tex[unit].swizzle_a != TGSI_SWIZZLE_W);
4928
4929 swz->shadow_compare = shadow_compare;
4930 swz->texture_target = inst->Texture.Texture;
4931
4932 if (swz->swizzled || shadow_compare) {
4933 /* Allocate temp register for the result of the SAMPLE instruction
4934 * and the source of the MOV/compare/swizzle instructions.
4935 */
4936 unsigned tmp = get_temp_index(emit);
4937 swz->tmp_src = make_src_temp_reg(tmp);
4938 swz->tmp_dst = make_dst_temp_reg(tmp);
4939
4940 swz->unit = unit;
4941 }
4942 swz->inst_dst = &inst->Dst[0];
4943 swz->coord_src = &inst->Src[0];
4944 }
4945
4946
4947 /**
4948 * Returns the register to put the SAMPLE instruction results into.
4949 * This will either be the original instruction dst reg (if no swizzle
4950 * and no shadow comparison) or a temporary reg if there is a swizzle.
4951 */
4952 static const struct tgsi_full_dst_register *
4953 get_tex_swizzle_dst(const struct tex_swizzle_info *swz)
4954 {
4955 return (swz->swizzled || swz->shadow_compare)
4956 ? &swz->tmp_dst : swz->inst_dst;
4957 }
4958
4959
4960 /**
4961 * This emits the MOV instruction that actually implements a texture swizzle
4962 * and/or shadow comparison.
4963 */
4964 static void
4965 end_tex_swizzle(struct svga_shader_emitter_v10 *emit,
4966 const struct tex_swizzle_info *swz)
4967 {
4968 if (swz->shadow_compare) {
4969 /* Emit extra instructions to compare the fetched texel value against
4970 * a texture coordinate component. The result of the comparison
4971 * is 0.0 or 1.0.
4972 */
4973 struct tgsi_full_src_register coord_src;
4974 struct tgsi_full_src_register texel_src =
4975 scalar_src(&swz->tmp_src, TGSI_SWIZZLE_X);
4976 struct tgsi_full_src_register one =
4977 make_immediate_reg_float(emit, 1.0f);
4978 /* convert gallium comparison func to SVGA comparison func */
4979 SVGA3dCmpFunc compare_func = emit->key.tex[swz->unit].compare_func + 1;
4980
4981 assert(emit->unit == PIPE_SHADER_FRAGMENT);
4982
4983 switch (swz->texture_target) {
4984 case TGSI_TEXTURE_SHADOW2D:
4985 case TGSI_TEXTURE_SHADOWRECT:
4986 case TGSI_TEXTURE_SHADOW1D_ARRAY:
4987 coord_src = scalar_src(swz->coord_src, TGSI_SWIZZLE_Z);
4988 break;
4989 case TGSI_TEXTURE_SHADOW1D:
4990 coord_src = scalar_src(swz->coord_src, TGSI_SWIZZLE_Y);
4991 break;
4992 case TGSI_TEXTURE_SHADOWCUBE:
4993 case TGSI_TEXTURE_SHADOW2D_ARRAY:
4994 coord_src = scalar_src(swz->coord_src, TGSI_SWIZZLE_W);
4995 break;
4996 default:
4997 assert(!"Unexpected texture target in end_tex_swizzle()");
4998 coord_src = scalar_src(swz->coord_src, TGSI_SWIZZLE_Z);
4999 }
5000
5001 /* COMPARE tmp, coord, texel */
5002 /* XXX it would seem that the texel and coord arguments should
5003 * be transposed here, but piglit tests indicate otherwise.
5004 */
5005 emit_comparison(emit, compare_func,
5006 &swz->tmp_dst, &texel_src, &coord_src);
5007
5008 /* AND dest, tmp, {1.0} */
5009 begin_emit_instruction(emit);
5010 emit_opcode(emit, VGPU10_OPCODE_AND, FALSE);
5011 if (swz->swizzled) {
5012 emit_dst_register(emit, &swz->tmp_dst);
5013 }
5014 else {
5015 emit_dst_register(emit, swz->inst_dst);
5016 }
5017 emit_src_register(emit, &swz->tmp_src);
5018 emit_src_register(emit, &one);
5019 end_emit_instruction(emit);
5020 }
5021
5022 if (swz->swizzled) {
5023 unsigned swz_r = emit->key.tex[swz->unit].swizzle_r;
5024 unsigned swz_g = emit->key.tex[swz->unit].swizzle_g;
5025 unsigned swz_b = emit->key.tex[swz->unit].swizzle_b;
5026 unsigned swz_a = emit->key.tex[swz->unit].swizzle_a;
5027 unsigned writemask_0 = 0, writemask_1 = 0;
5028 boolean int_tex = is_integer_type(emit->sampler_return_type[swz->unit]);
5029
5030 /* Swizzle w/out zero/one terms */
5031 struct tgsi_full_src_register src_swizzled =
5032 swizzle_src(&swz->tmp_src,
5033 swz_r < PIPE_SWIZZLE_0 ? swz_r : PIPE_SWIZZLE_X,
5034 swz_g < PIPE_SWIZZLE_0 ? swz_g : PIPE_SWIZZLE_Y,
5035 swz_b < PIPE_SWIZZLE_0 ? swz_b : PIPE_SWIZZLE_Z,
5036 swz_a < PIPE_SWIZZLE_0 ? swz_a : PIPE_SWIZZLE_W);
5037
5038 /* MOV dst, color(tmp).<swizzle> */
5039 emit_instruction_op1(emit, VGPU10_OPCODE_MOV,
5040 swz->inst_dst, &src_swizzled, FALSE);
5041
5042 /* handle swizzle zero terms */
5043 writemask_0 = (((swz_r == PIPE_SWIZZLE_0) << 0) |
5044 ((swz_g == PIPE_SWIZZLE_0) << 1) |
5045 ((swz_b == PIPE_SWIZZLE_0) << 2) |
5046 ((swz_a == PIPE_SWIZZLE_0) << 3));
5047
5048 if (writemask_0) {
5049 struct tgsi_full_src_register zero = int_tex ?
5050 make_immediate_reg_int(emit, 0) :
5051 make_immediate_reg_float(emit, 0.0f);
5052 struct tgsi_full_dst_register dst =
5053 writemask_dst(swz->inst_dst, writemask_0);
5054
5055 /* MOV dst.writemask_0, {0,0,0,0} */
5056 emit_instruction_op1(emit, VGPU10_OPCODE_MOV,
5057 &dst, &zero, FALSE);
5058 }
5059
5060 /* handle swizzle one terms */
5061 writemask_1 = (((swz_r == PIPE_SWIZZLE_1) << 0) |
5062 ((swz_g == PIPE_SWIZZLE_1) << 1) |
5063 ((swz_b == PIPE_SWIZZLE_1) << 2) |
5064 ((swz_a == PIPE_SWIZZLE_1) << 3));
5065
5066 if (writemask_1) {
5067 struct tgsi_full_src_register one = int_tex ?
5068 make_immediate_reg_int(emit, 1) :
5069 make_immediate_reg_float(emit, 1.0f);
5070 struct tgsi_full_dst_register dst =
5071 writemask_dst(swz->inst_dst, writemask_1);
5072
5073 /* MOV dst.writemask_1, {1,1,1,1} */
5074 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &dst, &one, FALSE);
5075 }
5076 }
5077 }
5078
5079
5080 /**
5081 * Emit code for TGSI_OPCODE_SAMPLE instruction.
5082 */
5083 static boolean
5084 emit_sample(struct svga_shader_emitter_v10 *emit,
5085 const struct tgsi_full_instruction *inst)
5086 {
5087 const unsigned resource_unit = inst->Src[1].Register.Index;
5088 const unsigned sampler_unit = inst->Src[2].Register.Index;
5089 struct tgsi_full_src_register coord;
5090 int offsets[3];
5091 struct tex_swizzle_info swz_info;
5092
5093 begin_tex_swizzle(emit, sampler_unit, inst, FALSE, &swz_info);
5094
5095 get_texel_offsets(emit, inst, offsets);
5096
5097 coord = setup_texcoord(emit, resource_unit, &inst->Src[0]);
5098
5099 /* SAMPLE dst, coord(s0), resource, sampler */
5100 begin_emit_instruction(emit);
5101
5102 /* NOTE: for non-fragment shaders, we should use VGPU10_OPCODE_SAMPLE_L
5103 * with LOD=0. But our virtual GPU accepts this as-is.
5104 */
5105 emit_sample_opcode(emit, VGPU10_OPCODE_SAMPLE,
5106 inst->Instruction.Saturate, offsets);
5107 emit_dst_register(emit, get_tex_swizzle_dst(&swz_info));
5108 emit_src_register(emit, &coord);
5109 emit_resource_register(emit, resource_unit);
5110 emit_sampler_register(emit, sampler_unit);
5111 end_emit_instruction(emit);
5112
5113 end_tex_swizzle(emit, &swz_info);
5114
5115 free_temp_indexes(emit);
5116
5117 return TRUE;
5118 }
5119
5120
5121 /**
5122 * Check if a texture instruction is valid.
5123 * An example of an invalid texture instruction is doing shadow comparison
5124 * with an integer-valued texture.
5125 * If we detect an invalid texture instruction, we replace it with:
5126 * MOV dst, {1,1,1,1};
5127 * \return TRUE if valid, FALSE if invalid.
5128 */
5129 static boolean
5130 is_valid_tex_instruction(struct svga_shader_emitter_v10 *emit,
5131 const struct tgsi_full_instruction *inst)
5132 {
5133 const unsigned unit = inst->Src[1].Register.Index;
5134 const unsigned target = inst->Texture.Texture;
5135 boolean valid = TRUE;
5136
5137 if (tgsi_is_shadow_target(target) &&
5138 is_integer_type(emit->sampler_return_type[unit])) {
5139 debug_printf("Invalid SAMPLE_C with an integer texture!\n");
5140 valid = FALSE;
5141 }
5142 /* XXX might check for other conditions in the future here */
5143
5144 if (!valid) {
5145 /* emit a MOV dst, {1,1,1,1} instruction. */
5146 struct tgsi_full_src_register one = make_immediate_reg_float(emit, 1.0f);
5147 begin_emit_instruction(emit);
5148 emit_opcode(emit, VGPU10_OPCODE_MOV, FALSE);
5149 emit_dst_register(emit, &inst->Dst[0]);
5150 emit_src_register(emit, &one);
5151 end_emit_instruction(emit);
5152 }
5153
5154 return valid;
5155 }
5156
5157
5158 /**
5159 * Emit code for TGSI_OPCODE_TEX (simple texture lookup)
5160 */
5161 static boolean
5162 emit_tex(struct svga_shader_emitter_v10 *emit,
5163 const struct tgsi_full_instruction *inst)
5164 {
5165 const uint unit = inst->Src[1].Register.Index;
5166 unsigned target = inst->Texture.Texture;
5167 unsigned opcode;
5168 struct tgsi_full_src_register coord;
5169 int offsets[3];
5170 struct tex_swizzle_info swz_info;
5171
5172 /* check that the sampler returns a float */
5173 if (!is_valid_tex_instruction(emit, inst))
5174 return TRUE;
5175
5176 begin_tex_swizzle(emit, unit, inst, FALSE, &swz_info);
5177
5178 get_texel_offsets(emit, inst, offsets);
5179
5180 coord = setup_texcoord(emit, unit, &inst->Src[0]);
5181
5182 /* SAMPLE dst, coord(s0), resource, sampler */
5183 begin_emit_instruction(emit);
5184
5185 if (tgsi_is_shadow_target(target))
5186 opcode = VGPU10_OPCODE_SAMPLE_C;
5187 else
5188 opcode = VGPU10_OPCODE_SAMPLE;
5189
5190 emit_sample_opcode(emit, opcode, inst->Instruction.Saturate, offsets);
5191 emit_dst_register(emit, get_tex_swizzle_dst(&swz_info));
5192 emit_src_register(emit, &coord);
5193 emit_resource_register(emit, unit);
5194 emit_sampler_register(emit, unit);
5195 if (opcode == VGPU10_OPCODE_SAMPLE_C) {
5196 emit_tex_compare_refcoord(emit, target, &coord);
5197 }
5198 end_emit_instruction(emit);
5199
5200 end_tex_swizzle(emit, &swz_info);
5201
5202 free_temp_indexes(emit);
5203
5204 return TRUE;
5205 }
5206
5207
5208 /**
5209 * Emit code for TGSI_OPCODE_TXP (projective texture)
5210 */
5211 static boolean
5212 emit_txp(struct svga_shader_emitter_v10 *emit,
5213 const struct tgsi_full_instruction *inst)
5214 {
5215 const uint unit = inst->Src[1].Register.Index;
5216 unsigned target = inst->Texture.Texture;
5217 unsigned opcode;
5218 int offsets[3];
5219 unsigned tmp = get_temp_index(emit);
5220 struct tgsi_full_src_register tmp_src = make_src_temp_reg(tmp);
5221 struct tgsi_full_dst_register tmp_dst = make_dst_temp_reg(tmp);
5222 struct tgsi_full_src_register src0_wwww =
5223 scalar_src(&inst->Src[0], TGSI_SWIZZLE_W);
5224 struct tgsi_full_src_register coord;
5225 struct tex_swizzle_info swz_info;
5226
5227 /* check that the sampler returns a float */
5228 if (!is_valid_tex_instruction(emit, inst))
5229 return TRUE;
5230
5231 begin_tex_swizzle(emit, unit, inst, FALSE, &swz_info);
5232
5233 get_texel_offsets(emit, inst, offsets);
5234
5235 coord = setup_texcoord(emit, unit, &inst->Src[0]);
5236
5237 /* DIV tmp, coord, coord.wwww */
5238 emit_instruction_op2(emit, VGPU10_OPCODE_DIV, &tmp_dst,
5239 &coord, &src0_wwww, FALSE);
5240
5241 /* SAMPLE dst, coord(tmp), resource, sampler */
5242 begin_emit_instruction(emit);
5243
5244 if (tgsi_is_shadow_target(target))
5245 /* NOTE: for non-fragment shaders, we should use
5246 * VGPU10_OPCODE_SAMPLE_C_LZ, but our virtual GPU accepts this as-is.
5247 */
5248 opcode = VGPU10_OPCODE_SAMPLE_C;
5249 else
5250 opcode = VGPU10_OPCODE_SAMPLE;
5251
5252 emit_sample_opcode(emit, opcode, inst->Instruction.Saturate, offsets);
5253 emit_dst_register(emit, get_tex_swizzle_dst(&swz_info));
5254 emit_src_register(emit, &tmp_src); /* projected coord */
5255 emit_resource_register(emit, unit);
5256 emit_sampler_register(emit, unit);
5257 if (opcode == VGPU10_OPCODE_SAMPLE_C) {
5258 emit_tex_compare_refcoord(emit, target, &tmp_src);
5259 }
5260 end_emit_instruction(emit);
5261
5262 end_tex_swizzle(emit, &swz_info);
5263
5264 free_temp_indexes(emit);
5265
5266 return TRUE;
5267 }
5268
5269
5270 /*
5271 * Emit code for TGSI_OPCODE_XPD instruction.
5272 */
5273 static boolean
5274 emit_xpd(struct svga_shader_emitter_v10 *emit,
5275 const struct tgsi_full_instruction *inst)
5276 {
5277 /* dst.x = src0.y * src1.z - src1.y * src0.z
5278 * dst.y = src0.z * src1.x - src1.z * src0.x
5279 * dst.z = src0.x * src1.y - src1.x * src0.y
5280 * dst.w = 1
5281 */
5282 struct tgsi_full_src_register s0_xxxx =
5283 scalar_src(&inst->Src[0], TGSI_SWIZZLE_X);
5284 struct tgsi_full_src_register s0_yyyy =
5285 scalar_src(&inst->Src[0], TGSI_SWIZZLE_Y);
5286 struct tgsi_full_src_register s0_zzzz =
5287 scalar_src(&inst->Src[0], TGSI_SWIZZLE_Z);
5288
5289 struct tgsi_full_src_register s1_xxxx =
5290 scalar_src(&inst->Src[1], TGSI_SWIZZLE_X);
5291 struct tgsi_full_src_register s1_yyyy =
5292 scalar_src(&inst->Src[1], TGSI_SWIZZLE_Y);
5293 struct tgsi_full_src_register s1_zzzz =
5294 scalar_src(&inst->Src[1], TGSI_SWIZZLE_Z);
5295
5296 unsigned tmp1 = get_temp_index(emit);
5297 struct tgsi_full_src_register tmp1_src = make_src_temp_reg(tmp1);
5298 struct tgsi_full_dst_register tmp1_dst = make_dst_temp_reg(tmp1);
5299
5300 unsigned tmp2 = get_temp_index(emit);
5301 struct tgsi_full_src_register tmp2_src = make_src_temp_reg(tmp2);
5302 struct tgsi_full_dst_register tmp2_dst = make_dst_temp_reg(tmp2);
5303 struct tgsi_full_src_register neg_tmp2_src = negate_src(&tmp2_src);
5304
5305 unsigned tmp3 = get_temp_index(emit);
5306 struct tgsi_full_src_register tmp3_src = make_src_temp_reg(tmp3);
5307 struct tgsi_full_dst_register tmp3_dst = make_dst_temp_reg(tmp3);
5308 struct tgsi_full_dst_register tmp3_dst_x =
5309 writemask_dst(&tmp3_dst, TGSI_WRITEMASK_X);
5310 struct tgsi_full_dst_register tmp3_dst_y =
5311 writemask_dst(&tmp3_dst, TGSI_WRITEMASK_Y);
5312 struct tgsi_full_dst_register tmp3_dst_z =
5313 writemask_dst(&tmp3_dst, TGSI_WRITEMASK_Z);
5314 struct tgsi_full_dst_register tmp3_dst_w =
5315 writemask_dst(&tmp3_dst, TGSI_WRITEMASK_W);
5316
5317 /* Note: we put all the intermediate computations into tmp3 in case
5318 * the XPD dest register is that same as one of the src regs (in which
5319 * case we could clobber a src reg before we're done with it) .
5320 *
5321 * Note: we could get by with just one temp register instead of three
5322 * since we're doing scalar operations and there's enough room in one
5323 * temp for everything.
5324 */
5325
5326 /* MUL tmp1, src0.y, src1.z */
5327 /* MUL tmp2, src1.y, src0.z */
5328 /* ADD tmp3.x, tmp1, -tmp2 */
5329 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
5330 emit_instruction_op2(emit, VGPU10_OPCODE_MUL, &tmp1_dst,
5331 &s0_yyyy, &s1_zzzz, FALSE);
5332 emit_instruction_op2(emit, VGPU10_OPCODE_MUL, &tmp2_dst,
5333 &s1_yyyy, &s0_zzzz, FALSE);
5334 emit_instruction_op2(emit, VGPU10_OPCODE_ADD, &tmp3_dst_x,
5335 &tmp1_src, &neg_tmp2_src, FALSE);
5336 }
5337
5338 /* MUL tmp1, src0.z, src1.x */
5339 /* MUL tmp2, src1.z, src0.x */
5340 /* ADD tmp3.y, tmp1, -tmp2 */
5341 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
5342 emit_instruction_op2(emit, VGPU10_OPCODE_MUL, &tmp1_dst, &s0_zzzz,
5343 &s1_xxxx, FALSE);
5344 emit_instruction_op2(emit, VGPU10_OPCODE_MUL, &tmp2_dst, &s1_zzzz,
5345 &s0_xxxx, FALSE);
5346 emit_instruction_op2(emit, VGPU10_OPCODE_ADD, &tmp3_dst_y,
5347 &tmp1_src, &neg_tmp2_src, FALSE);
5348 }
5349
5350 /* MUL tmp1, src0.x, src1.y */
5351 /* MUL tmp2, src1.x, src0.y */
5352 /* ADD tmp3.z, tmp1, -tmp2 */
5353 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
5354 emit_instruction_op2(emit, VGPU10_OPCODE_MUL, &tmp1_dst, &s0_xxxx,
5355 &s1_yyyy, FALSE);
5356 emit_instruction_op2(emit, VGPU10_OPCODE_MUL, &tmp2_dst, &s1_xxxx,
5357 &s0_yyyy, FALSE);
5358 emit_instruction_op2(emit, VGPU10_OPCODE_ADD, &tmp3_dst_z,
5359 &tmp1_src, &neg_tmp2_src, FALSE);
5360 }
5361
5362 /* MOV tmp3.w, 1.0 */
5363 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
5364 struct tgsi_full_src_register one =
5365 make_immediate_reg_float(emit, 1.0f);
5366
5367 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &tmp3_dst_w, &one, FALSE);
5368 }
5369
5370 /* MOV dst, tmp3 */
5371 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &inst->Dst[0], &tmp3_src,
5372 inst->Instruction.Saturate);
5373
5374
5375 free_temp_indexes(emit);
5376
5377 return TRUE;
5378 }
5379
5380
5381 /**
5382 * Emit code for TGSI_OPCODE_TXD (explicit derivatives)
5383 */
5384 static boolean
5385 emit_txd(struct svga_shader_emitter_v10 *emit,
5386 const struct tgsi_full_instruction *inst)
5387 {
5388 const uint unit = inst->Src[3].Register.Index;
5389 unsigned target = inst->Texture.Texture;
5390 int offsets[3];
5391 struct tgsi_full_src_register coord;
5392 struct tex_swizzle_info swz_info;
5393
5394 begin_tex_swizzle(emit, unit, inst, tgsi_is_shadow_target(target),
5395 &swz_info);
5396
5397 get_texel_offsets(emit, inst, offsets);
5398
5399 coord = setup_texcoord(emit, unit, &inst->Src[0]);
5400
5401 /* SAMPLE_D dst, coord(s0), resource, sampler, Xderiv(s1), Yderiv(s2) */
5402 begin_emit_instruction(emit);
5403 emit_sample_opcode(emit, VGPU10_OPCODE_SAMPLE_D,
5404 inst->Instruction.Saturate, offsets);
5405 emit_dst_register(emit, get_tex_swizzle_dst(&swz_info));
5406 emit_src_register(emit, &coord);
5407 emit_resource_register(emit, unit);
5408 emit_sampler_register(emit, unit);
5409 emit_src_register(emit, &inst->Src[1]); /* Xderiv */
5410 emit_src_register(emit, &inst->Src[2]); /* Yderiv */
5411 end_emit_instruction(emit);
5412
5413 end_tex_swizzle(emit, &swz_info);
5414
5415 free_temp_indexes(emit);
5416
5417 return TRUE;
5418 }
5419
5420
5421 /**
5422 * Emit code for TGSI_OPCODE_TXF (texel fetch)
5423 */
5424 static boolean
5425 emit_txf(struct svga_shader_emitter_v10 *emit,
5426 const struct tgsi_full_instruction *inst)
5427 {
5428 const uint unit = inst->Src[1].Register.Index;
5429 const boolean msaa = tgsi_is_msaa_target(inst->Texture.Texture);
5430 int offsets[3];
5431 struct tex_swizzle_info swz_info;
5432
5433 begin_tex_swizzle(emit, unit, inst, FALSE, &swz_info);
5434
5435 get_texel_offsets(emit, inst, offsets);
5436
5437 if (msaa) {
5438 /* Fetch one sample from an MSAA texture */
5439 struct tgsi_full_src_register sampleIndex =
5440 scalar_src(&inst->Src[0], TGSI_SWIZZLE_W);
5441 /* LD_MS dst, coord(s0), resource, sampleIndex */
5442 begin_emit_instruction(emit);
5443 emit_sample_opcode(emit, VGPU10_OPCODE_LD_MS,
5444 inst->Instruction.Saturate, offsets);
5445 emit_dst_register(emit, get_tex_swizzle_dst(&swz_info));
5446 emit_src_register(emit, &inst->Src[0]);
5447 emit_resource_register(emit, unit);
5448 emit_src_register(emit, &sampleIndex);
5449 end_emit_instruction(emit);
5450 }
5451 else {
5452 /* Fetch one texel specified by integer coordinate */
5453 /* LD dst, coord(s0), resource */
5454 begin_emit_instruction(emit);
5455 emit_sample_opcode(emit, VGPU10_OPCODE_LD,
5456 inst->Instruction.Saturate, offsets);
5457 emit_dst_register(emit, get_tex_swizzle_dst(&swz_info));
5458 emit_src_register(emit, &inst->Src[0]);
5459 emit_resource_register(emit, unit);
5460 end_emit_instruction(emit);
5461 }
5462
5463 end_tex_swizzle(emit, &swz_info);
5464
5465 free_temp_indexes(emit);
5466
5467 return TRUE;
5468 }
5469
5470
5471 /**
5472 * Emit code for TGSI_OPCODE_TXL (explicit LOD) or TGSI_OPCODE_TXB (LOD bias)
5473 * or TGSI_OPCODE_TXB2 (for cube shadow maps).
5474 */
5475 static boolean
5476 emit_txl_txb(struct svga_shader_emitter_v10 *emit,
5477 const struct tgsi_full_instruction *inst)
5478 {
5479 unsigned target = inst->Texture.Texture;
5480 unsigned opcode, unit;
5481 int offsets[3];
5482 struct tgsi_full_src_register coord, lod_bias;
5483 struct tex_swizzle_info swz_info;
5484
5485 assert(inst->Instruction.Opcode == TGSI_OPCODE_TXL ||
5486 inst->Instruction.Opcode == TGSI_OPCODE_TXB ||
5487 inst->Instruction.Opcode == TGSI_OPCODE_TXB2);
5488
5489 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB2) {
5490 lod_bias = scalar_src(&inst->Src[1], TGSI_SWIZZLE_X);
5491 unit = inst->Src[2].Register.Index;
5492 }
5493 else {
5494 lod_bias = scalar_src(&inst->Src[0], TGSI_SWIZZLE_W);
5495 unit = inst->Src[1].Register.Index;
5496 }
5497
5498 begin_tex_swizzle(emit, unit, inst, tgsi_is_shadow_target(target),
5499 &swz_info);
5500
5501 get_texel_offsets(emit, inst, offsets);
5502
5503 coord = setup_texcoord(emit, unit, &inst->Src[0]);
5504
5505 /* SAMPLE_L/B dst, coord(s0), resource, sampler, lod(s3) */
5506 begin_emit_instruction(emit);
5507 if (inst->Instruction.Opcode == TGSI_OPCODE_TXL) {
5508 opcode = VGPU10_OPCODE_SAMPLE_L;
5509 }
5510 else {
5511 opcode = VGPU10_OPCODE_SAMPLE_B;
5512 }
5513 emit_sample_opcode(emit, opcode, inst->Instruction.Saturate, offsets);
5514 emit_dst_register(emit, get_tex_swizzle_dst(&swz_info));
5515 emit_src_register(emit, &coord);
5516 emit_resource_register(emit, unit);
5517 emit_sampler_register(emit, unit);
5518 emit_src_register(emit, &lod_bias);
5519 end_emit_instruction(emit);
5520
5521 end_tex_swizzle(emit, &swz_info);
5522
5523 free_temp_indexes(emit);
5524
5525 return TRUE;
5526 }
5527
5528
5529 /**
5530 * Emit code for TGSI_OPCODE_TXQ (texture query) instruction.
5531 */
5532 static boolean
5533 emit_txq(struct svga_shader_emitter_v10 *emit,
5534 const struct tgsi_full_instruction *inst)
5535 {
5536 const uint unit = inst->Src[1].Register.Index;
5537
5538 if (emit->sampler_target[unit] == TGSI_TEXTURE_BUFFER) {
5539 /* RESINFO does not support querying texture buffers, so we instead
5540 * store texture buffer sizes in shader constants, then copy them to
5541 * implement TXQ instead of emitting RESINFO.
5542 * MOV dst, const[texture_buffer_size_index[unit]]
5543 */
5544 struct tgsi_full_src_register size_src =
5545 make_src_const_reg(emit->texture_buffer_size_index[unit]);
5546 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &inst->Dst[0], &size_src,
5547 FALSE);
5548 } else {
5549 /* RESINFO dst, srcMipLevel, resource */
5550 begin_emit_instruction(emit);
5551 emit_opcode_resinfo(emit, VGPU10_RESINFO_RETURN_UINT);
5552 emit_dst_register(emit, &inst->Dst[0]);
5553 emit_src_register(emit, &inst->Src[0]);
5554 emit_resource_register(emit, unit);
5555 end_emit_instruction(emit);
5556 }
5557
5558 free_temp_indexes(emit);
5559
5560 return TRUE;
5561 }
5562
5563
5564 /**
5565 * Emit a simple instruction (like ADD, MUL, MIN, etc).
5566 */
5567 static boolean
5568 emit_simple(struct svga_shader_emitter_v10 *emit,
5569 const struct tgsi_full_instruction *inst)
5570 {
5571 const unsigned opcode = inst->Instruction.Opcode;
5572 const struct tgsi_opcode_info *op = tgsi_get_opcode_info(opcode);
5573 unsigned i;
5574
5575 begin_emit_instruction(emit);
5576 emit_opcode(emit, translate_opcode(inst->Instruction.Opcode),
5577 inst->Instruction.Saturate);
5578 for (i = 0; i < op->num_dst; i++) {
5579 emit_dst_register(emit, &inst->Dst[i]);
5580 }
5581 for (i = 0; i < op->num_src; i++) {
5582 emit_src_register(emit, &inst->Src[i]);
5583 }
5584 end_emit_instruction(emit);
5585
5586 return TRUE;
5587 }
5588
5589
5590 /**
5591 * We only special case the MOV instruction to try to detect constant
5592 * color writes in the fragment shader.
5593 */
5594 static boolean
5595 emit_mov(struct svga_shader_emitter_v10 *emit,
5596 const struct tgsi_full_instruction *inst)
5597 {
5598 const struct tgsi_full_src_register *src = &inst->Src[0];
5599 const struct tgsi_full_dst_register *dst = &inst->Dst[0];
5600
5601 if (emit->unit == PIPE_SHADER_FRAGMENT &&
5602 dst->Register.File == TGSI_FILE_OUTPUT &&
5603 dst->Register.Index == 0 &&
5604 src->Register.File == TGSI_FILE_CONSTANT &&
5605 !src->Register.Indirect) {
5606 emit->constant_color_output = TRUE;
5607 }
5608
5609 return emit_simple(emit, inst);
5610 }
5611
5612
5613 /**
5614 * Emit a simple VGPU10 instruction which writes to multiple dest registers,
5615 * where TGSI only uses one dest register.
5616 */
5617 static boolean
5618 emit_simple_1dst(struct svga_shader_emitter_v10 *emit,
5619 const struct tgsi_full_instruction *inst,
5620 unsigned dst_count,
5621 unsigned dst_index)
5622 {
5623 const unsigned opcode = inst->Instruction.Opcode;
5624 const struct tgsi_opcode_info *op = tgsi_get_opcode_info(opcode);
5625 unsigned i;
5626
5627 begin_emit_instruction(emit);
5628 emit_opcode(emit, translate_opcode(inst->Instruction.Opcode),
5629 inst->Instruction.Saturate);
5630
5631 for (i = 0; i < dst_count; i++) {
5632 if (i == dst_index) {
5633 emit_dst_register(emit, &inst->Dst[0]);
5634 } else {
5635 emit_null_dst_register(emit);
5636 }
5637 }
5638
5639 for (i = 0; i < op->num_src; i++) {
5640 emit_src_register(emit, &inst->Src[i]);
5641 }
5642 end_emit_instruction(emit);
5643
5644 return TRUE;
5645 }
5646
5647
5648 /**
5649 * Translate a single TGSI instruction to VGPU10.
5650 */
5651 static boolean
5652 emit_vgpu10_instruction(struct svga_shader_emitter_v10 *emit,
5653 unsigned inst_number,
5654 const struct tgsi_full_instruction *inst)
5655 {
5656 const unsigned opcode = inst->Instruction.Opcode;
5657
5658 switch (opcode) {
5659 case TGSI_OPCODE_ADD:
5660 case TGSI_OPCODE_AND:
5661 case TGSI_OPCODE_BGNLOOP:
5662 case TGSI_OPCODE_BRK:
5663 case TGSI_OPCODE_CEIL:
5664 case TGSI_OPCODE_CONT:
5665 case TGSI_OPCODE_DDX:
5666 case TGSI_OPCODE_DDY:
5667 case TGSI_OPCODE_DIV:
5668 case TGSI_OPCODE_DP2:
5669 case TGSI_OPCODE_DP3:
5670 case TGSI_OPCODE_DP4:
5671 case TGSI_OPCODE_ELSE:
5672 case TGSI_OPCODE_ENDIF:
5673 case TGSI_OPCODE_ENDLOOP:
5674 case TGSI_OPCODE_ENDSUB:
5675 case TGSI_OPCODE_F2I:
5676 case TGSI_OPCODE_F2U:
5677 case TGSI_OPCODE_FLR:
5678 case TGSI_OPCODE_FRC:
5679 case TGSI_OPCODE_FSEQ:
5680 case TGSI_OPCODE_FSGE:
5681 case TGSI_OPCODE_FSLT:
5682 case TGSI_OPCODE_FSNE:
5683 case TGSI_OPCODE_I2F:
5684 case TGSI_OPCODE_IMAX:
5685 case TGSI_OPCODE_IMIN:
5686 case TGSI_OPCODE_INEG:
5687 case TGSI_OPCODE_ISGE:
5688 case TGSI_OPCODE_ISHR:
5689 case TGSI_OPCODE_ISLT:
5690 case TGSI_OPCODE_MAD:
5691 case TGSI_OPCODE_MAX:
5692 case TGSI_OPCODE_MIN:
5693 case TGSI_OPCODE_MUL:
5694 case TGSI_OPCODE_NOP:
5695 case TGSI_OPCODE_NOT:
5696 case TGSI_OPCODE_OR:
5697 case TGSI_OPCODE_RET:
5698 case TGSI_OPCODE_UADD:
5699 case TGSI_OPCODE_USEQ:
5700 case TGSI_OPCODE_USGE:
5701 case TGSI_OPCODE_USLT:
5702 case TGSI_OPCODE_UMIN:
5703 case TGSI_OPCODE_UMAD:
5704 case TGSI_OPCODE_UMAX:
5705 case TGSI_OPCODE_ROUND:
5706 case TGSI_OPCODE_SQRT:
5707 case TGSI_OPCODE_SHL:
5708 case TGSI_OPCODE_TRUNC:
5709 case TGSI_OPCODE_U2F:
5710 case TGSI_OPCODE_UCMP:
5711 case TGSI_OPCODE_USHR:
5712 case TGSI_OPCODE_USNE:
5713 case TGSI_OPCODE_XOR:
5714 /* simple instructions */
5715 return emit_simple(emit, inst);
5716
5717 case TGSI_OPCODE_MOV:
5718 return emit_mov(emit, inst);
5719 case TGSI_OPCODE_EMIT:
5720 return emit_vertex(emit, inst);
5721 case TGSI_OPCODE_ENDPRIM:
5722 return emit_endprim(emit, inst);
5723 case TGSI_OPCODE_IABS:
5724 return emit_iabs(emit, inst);
5725 case TGSI_OPCODE_ARL:
5726 /* fall-through */
5727 case TGSI_OPCODE_UARL:
5728 return emit_arl_uarl(emit, inst);
5729 case TGSI_OPCODE_BGNSUB:
5730 /* no-op */
5731 return TRUE;
5732 case TGSI_OPCODE_CAL:
5733 return emit_cal(emit, inst);
5734 case TGSI_OPCODE_CMP:
5735 return emit_cmp(emit, inst);
5736 case TGSI_OPCODE_COS:
5737 return emit_sincos(emit, inst);
5738 case TGSI_OPCODE_DP2A:
5739 return emit_dp2a(emit, inst);
5740 case TGSI_OPCODE_DPH:
5741 return emit_dph(emit, inst);
5742 case TGSI_OPCODE_DST:
5743 return emit_dst(emit, inst);
5744 case TGSI_OPCODE_EX2:
5745 return emit_ex2(emit, inst);
5746 case TGSI_OPCODE_EXP:
5747 return emit_exp(emit, inst);
5748 case TGSI_OPCODE_IF:
5749 return emit_if(emit, inst);
5750 case TGSI_OPCODE_KILL:
5751 return emit_kill(emit, inst);
5752 case TGSI_OPCODE_KILL_IF:
5753 return emit_kill_if(emit, inst);
5754 case TGSI_OPCODE_LG2:
5755 return emit_lg2(emit, inst);
5756 case TGSI_OPCODE_LIT:
5757 return emit_lit(emit, inst);
5758 case TGSI_OPCODE_LOG:
5759 return emit_log(emit, inst);
5760 case TGSI_OPCODE_LRP:
5761 return emit_lrp(emit, inst);
5762 case TGSI_OPCODE_POW:
5763 return emit_pow(emit, inst);
5764 case TGSI_OPCODE_RCP:
5765 return emit_rcp(emit, inst);
5766 case TGSI_OPCODE_RSQ:
5767 return emit_rsq(emit, inst);
5768 case TGSI_OPCODE_SAMPLE:
5769 return emit_sample(emit, inst);
5770 case TGSI_OPCODE_SCS:
5771 return emit_scs(emit, inst);
5772 case TGSI_OPCODE_SEQ:
5773 return emit_seq(emit, inst);
5774 case TGSI_OPCODE_SGE:
5775 return emit_sge(emit, inst);
5776 case TGSI_OPCODE_SGT:
5777 return emit_sgt(emit, inst);
5778 case TGSI_OPCODE_SIN:
5779 return emit_sincos(emit, inst);
5780 case TGSI_OPCODE_SLE:
5781 return emit_sle(emit, inst);
5782 case TGSI_OPCODE_SLT:
5783 return emit_slt(emit, inst);
5784 case TGSI_OPCODE_SNE:
5785 return emit_sne(emit, inst);
5786 case TGSI_OPCODE_SSG:
5787 return emit_ssg(emit, inst);
5788 case TGSI_OPCODE_ISSG:
5789 return emit_issg(emit, inst);
5790 case TGSI_OPCODE_TEX:
5791 return emit_tex(emit, inst);
5792 case TGSI_OPCODE_TXP:
5793 return emit_txp(emit, inst);
5794 case TGSI_OPCODE_TXB:
5795 case TGSI_OPCODE_TXB2:
5796 case TGSI_OPCODE_TXL:
5797 return emit_txl_txb(emit, inst);
5798 case TGSI_OPCODE_TXD:
5799 return emit_txd(emit, inst);
5800 case TGSI_OPCODE_TXF:
5801 return emit_txf(emit, inst);
5802 case TGSI_OPCODE_TXQ:
5803 return emit_txq(emit, inst);
5804 case TGSI_OPCODE_UIF:
5805 return emit_if(emit, inst);
5806 case TGSI_OPCODE_XPD:
5807 return emit_xpd(emit, inst);
5808 case TGSI_OPCODE_UMUL_HI:
5809 case TGSI_OPCODE_IMUL_HI:
5810 case TGSI_OPCODE_UDIV:
5811 case TGSI_OPCODE_IDIV:
5812 /* These cases use only the FIRST of two destination registers */
5813 return emit_simple_1dst(emit, inst, 2, 0);
5814 case TGSI_OPCODE_UMUL:
5815 case TGSI_OPCODE_UMOD:
5816 case TGSI_OPCODE_MOD:
5817 /* These cases use only the SECOND of two destination registers */
5818 return emit_simple_1dst(emit, inst, 2, 1);
5819 case TGSI_OPCODE_END:
5820 if (!emit_post_helpers(emit))
5821 return FALSE;
5822 return emit_simple(emit, inst);
5823
5824 default:
5825 debug_printf("Unimplemented tgsi instruction %s\n",
5826 tgsi_get_opcode_name(opcode));
5827 return FALSE;
5828 }
5829
5830 return TRUE;
5831 }
5832
5833
5834 /**
5835 * Emit the extra instructions to adjust the vertex position.
5836 * There are two possible adjustments:
5837 * 1. Converting from Gallium to VGPU10 coordinate space by applying the
5838 * "prescale" and "pretranslate" values.
5839 * 2. Undoing the viewport transformation when we use the swtnl/draw path.
5840 * \param vs_pos_tmp_index which temporary register contains the vertex pos.
5841 */
5842 static void
5843 emit_vpos_instructions(struct svga_shader_emitter_v10 *emit,
5844 unsigned vs_pos_tmp_index)
5845 {
5846 struct tgsi_full_src_register tmp_pos_src;
5847 struct tgsi_full_dst_register pos_dst;
5848
5849 /* Don't bother to emit any extra vertex instructions if vertex position is
5850 * not written out
5851 */
5852 if (emit->vposition.out_index == INVALID_INDEX)
5853 return;
5854
5855 tmp_pos_src = make_src_temp_reg(vs_pos_tmp_index);
5856 pos_dst = make_dst_output_reg(emit->vposition.out_index);
5857
5858 /* If non-adjusted vertex position register index
5859 * is valid, copy the vertex position from the temporary
5860 * vertex position register before it is modified by the
5861 * prescale computation.
5862 */
5863 if (emit->vposition.so_index != INVALID_INDEX) {
5864 struct tgsi_full_dst_register pos_so_dst =
5865 make_dst_output_reg(emit->vposition.so_index);
5866
5867 /* MOV pos_so, tmp_pos */
5868 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &pos_so_dst,
5869 &tmp_pos_src, FALSE);
5870 }
5871
5872 if (emit->vposition.need_prescale) {
5873 /* This code adjusts the vertex position to match the VGPU10 convention.
5874 * If p is the position computed by the shader (usually by applying the
5875 * modelview and projection matrices), the new position q is computed by:
5876 *
5877 * q.x = p.w * trans.x + p.x * scale.x
5878 * q.y = p.w * trans.y + p.y * scale.y
5879 * q.z = p.w * trans.z + p.z * scale.z;
5880 * q.w = p.w * trans.w + p.w;
5881 */
5882 struct tgsi_full_src_register tmp_pos_src_w =
5883 scalar_src(&tmp_pos_src, TGSI_SWIZZLE_W);
5884 struct tgsi_full_dst_register tmp_pos_dst =
5885 make_dst_temp_reg(vs_pos_tmp_index);
5886 struct tgsi_full_dst_register tmp_pos_dst_xyz =
5887 writemask_dst(&tmp_pos_dst, TGSI_WRITEMASK_XYZ);
5888
5889 struct tgsi_full_src_register prescale_scale =
5890 make_src_const_reg(emit->vposition.prescale_scale_index);
5891 struct tgsi_full_src_register prescale_trans =
5892 make_src_const_reg(emit->vposition.prescale_trans_index);
5893
5894 /* MUL tmp_pos.xyz, tmp_pos, prescale.scale */
5895 emit_instruction_op2(emit, VGPU10_OPCODE_MUL, &tmp_pos_dst_xyz,
5896 &tmp_pos_src, &prescale_scale, FALSE);
5897
5898 /* MAD pos, tmp_pos.wwww, prescale.trans, tmp_pos */
5899 emit_instruction_op3(emit, VGPU10_OPCODE_MAD, &pos_dst, &tmp_pos_src_w,
5900 &prescale_trans, &tmp_pos_src, FALSE);
5901 }
5902 else if (emit->key.vs.undo_viewport) {
5903 /* This code computes the final vertex position from the temporary
5904 * vertex position by undoing the viewport transformation and the
5905 * divide-by-W operation (we convert window coords back to clip coords).
5906 * This is needed when we use the 'draw' module for fallbacks.
5907 * If p is the temp pos in window coords, then the NDC coord q is:
5908 * q.x = (p.x - vp.x_trans) / vp.x_scale * p.w
5909 * q.y = (p.y - vp.y_trans) / vp.y_scale * p.w
5910 * q.z = p.z * p.w
5911 * q.w = p.w
5912 * CONST[vs_viewport_index] contains:
5913 * { 1/vp.x_scale, 1/vp.y_scale, -vp.x_trans, -vp.y_trans }
5914 */
5915 struct tgsi_full_dst_register tmp_pos_dst =
5916 make_dst_temp_reg(vs_pos_tmp_index);
5917 struct tgsi_full_dst_register tmp_pos_dst_xy =
5918 writemask_dst(&tmp_pos_dst, TGSI_WRITEMASK_XY);
5919 struct tgsi_full_src_register tmp_pos_src_wwww =
5920 scalar_src(&tmp_pos_src, TGSI_SWIZZLE_W);
5921
5922 struct tgsi_full_dst_register pos_dst_xyz =
5923 writemask_dst(&pos_dst, TGSI_WRITEMASK_XYZ);
5924 struct tgsi_full_dst_register pos_dst_w =
5925 writemask_dst(&pos_dst, TGSI_WRITEMASK_W);
5926
5927 struct tgsi_full_src_register vp_xyzw =
5928 make_src_const_reg(emit->vs.viewport_index);
5929 struct tgsi_full_src_register vp_zwww =
5930 swizzle_src(&vp_xyzw, TGSI_SWIZZLE_Z, TGSI_SWIZZLE_W,
5931 TGSI_SWIZZLE_W, TGSI_SWIZZLE_W);
5932
5933 /* ADD tmp_pos.xy, tmp_pos.xy, viewport.zwww */
5934 emit_instruction_op2(emit, VGPU10_OPCODE_ADD, &tmp_pos_dst_xy,
5935 &tmp_pos_src, &vp_zwww, FALSE);
5936
5937 /* MUL tmp_pos.xy, tmp_pos.xyzw, viewport.xyzy */
5938 emit_instruction_op2(emit, VGPU10_OPCODE_MUL, &tmp_pos_dst_xy,
5939 &tmp_pos_src, &vp_xyzw, FALSE);
5940
5941 /* MUL pos.xyz, tmp_pos.xyz, tmp_pos.www */
5942 emit_instruction_op2(emit, VGPU10_OPCODE_MUL, &pos_dst_xyz,
5943 &tmp_pos_src, &tmp_pos_src_wwww, FALSE);
5944
5945 /* MOV pos.w, tmp_pos.w */
5946 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &pos_dst_w,
5947 &tmp_pos_src, FALSE);
5948 }
5949 else if (vs_pos_tmp_index != INVALID_INDEX) {
5950 /* This code is to handle the case where the temporary vertex
5951 * position register is created when the vertex shader has stream
5952 * output and prescale is disabled because rasterization is to be
5953 * discarded.
5954 */
5955 struct tgsi_full_dst_register pos_dst =
5956 make_dst_output_reg(emit->vposition.out_index);
5957
5958 /* MOV pos, tmp_pos */
5959 begin_emit_instruction(emit);
5960 emit_opcode(emit, VGPU10_OPCODE_MOV, FALSE);
5961 emit_dst_register(emit, &pos_dst);
5962 emit_src_register(emit, &tmp_pos_src);
5963 end_emit_instruction(emit);
5964 }
5965 }
5966
5967 static void
5968 emit_clipping_instructions(struct svga_shader_emitter_v10 *emit)
5969 {
5970 if (emit->clip_mode == CLIP_DISTANCE) {
5971 /* Copy from copy distance temporary to CLIPDIST & the shadow copy */
5972 emit_clip_distance_instructions(emit);
5973
5974 } else if (emit->clip_mode == CLIP_VERTEX) {
5975 /* Convert TGSI CLIPVERTEX to CLIPDIST */
5976 emit_clip_vertex_instructions(emit);
5977 }
5978
5979 /**
5980 * Emit vertex position and take care of legacy user planes only if
5981 * there is a valid vertex position register index.
5982 * This is to take care of the case
5983 * where the shader doesn't output vertex position. Then in
5984 * this case, don't bother to emit more vertex instructions.
5985 */
5986 if (emit->vposition.out_index == INVALID_INDEX)
5987 return;
5988
5989 /**
5990 * Emit per-vertex clipping instructions for legacy user defined clip planes.
5991 * NOTE: we must emit the clip distance instructions before the
5992 * emit_vpos_instructions() call since the later function will change
5993 * the TEMP[vs_pos_tmp_index] value.
5994 */
5995 if (emit->clip_mode == CLIP_LEGACY) {
5996 /* Emit CLIPDIST for legacy user defined clip planes */
5997 emit_clip_distance_from_vpos(emit, emit->vposition.tmp_index);
5998 }
5999 }
6000
6001
6002 /**
6003 * Emit extra per-vertex instructions. This includes clip-coordinate
6004 * space conversion and computing clip distances. This is called for
6005 * each GS emit-vertex instruction and at the end of VS translation.
6006 */
6007 static void
6008 emit_vertex_instructions(struct svga_shader_emitter_v10 *emit)
6009 {
6010 const unsigned vs_pos_tmp_index = emit->vposition.tmp_index;
6011
6012 /* Emit clipping instructions based on clipping mode */
6013 emit_clipping_instructions(emit);
6014
6015 /**
6016 * Reset the temporary vertex position register index
6017 * so that emit_dst_register() will use the real vertex position output
6018 */
6019 emit->vposition.tmp_index = INVALID_INDEX;
6020
6021 /* Emit vertex position instructions */
6022 emit_vpos_instructions(emit, vs_pos_tmp_index);
6023
6024 /* Restore original vposition.tmp_index value for the next GS vertex.
6025 * It doesn't matter for VS.
6026 */
6027 emit->vposition.tmp_index = vs_pos_tmp_index;
6028 }
6029
6030 /**
6031 * Translate the TGSI_OPCODE_EMIT GS instruction.
6032 */
6033 static boolean
6034 emit_vertex(struct svga_shader_emitter_v10 *emit,
6035 const struct tgsi_full_instruction *inst)
6036 {
6037 unsigned ret = TRUE;
6038
6039 assert(emit->unit == PIPE_SHADER_GEOMETRY);
6040
6041 emit_vertex_instructions(emit);
6042
6043 /* We can't use emit_simple() because the TGSI instruction has one
6044 * operand (vertex stream number) which we must ignore for VGPU10.
6045 */
6046 begin_emit_instruction(emit);
6047 emit_opcode(emit, VGPU10_OPCODE_EMIT, FALSE);
6048 end_emit_instruction(emit);
6049
6050 return ret;
6051 }
6052
6053
6054 /**
6055 * Emit the extra code to convert from VGPU10's boolean front-face
6056 * register to TGSI's signed front-face register.
6057 *
6058 * TODO: Make temporary front-face register a scalar.
6059 */
6060 static void
6061 emit_frontface_instructions(struct svga_shader_emitter_v10 *emit)
6062 {
6063 assert(emit->unit == PIPE_SHADER_FRAGMENT);
6064
6065 if (emit->fs.face_input_index != INVALID_INDEX) {
6066 /* convert vgpu10 boolean face register to gallium +/-1 value */
6067 struct tgsi_full_dst_register tmp_dst =
6068 make_dst_temp_reg(emit->fs.face_tmp_index);
6069 struct tgsi_full_src_register one =
6070 make_immediate_reg_float(emit, 1.0f);
6071 struct tgsi_full_src_register neg_one =
6072 make_immediate_reg_float(emit, -1.0f);
6073
6074 /* MOVC face_tmp, IS_FRONT_FACE.x, 1.0, -1.0 */
6075 begin_emit_instruction(emit);
6076 emit_opcode(emit, VGPU10_OPCODE_MOVC, FALSE);
6077 emit_dst_register(emit, &tmp_dst);
6078 emit_face_register(emit);
6079 emit_src_register(emit, &one);
6080 emit_src_register(emit, &neg_one);
6081 end_emit_instruction(emit);
6082 }
6083 }
6084
6085
6086 /**
6087 * Emit the extra code to convert from VGPU10's fragcoord.w value to 1/w.
6088 */
6089 static void
6090 emit_fragcoord_instructions(struct svga_shader_emitter_v10 *emit)
6091 {
6092 assert(emit->unit == PIPE_SHADER_FRAGMENT);
6093
6094 if (emit->fs.fragcoord_input_index != INVALID_INDEX) {
6095 struct tgsi_full_dst_register tmp_dst =
6096 make_dst_temp_reg(emit->fs.fragcoord_tmp_index);
6097 struct tgsi_full_dst_register tmp_dst_xyz =
6098 writemask_dst(&tmp_dst, TGSI_WRITEMASK_XYZ);
6099 struct tgsi_full_dst_register tmp_dst_w =
6100 writemask_dst(&tmp_dst, TGSI_WRITEMASK_W);
6101 struct tgsi_full_src_register one =
6102 make_immediate_reg_float(emit, 1.0f);
6103 struct tgsi_full_src_register fragcoord =
6104 make_src_reg(TGSI_FILE_INPUT, emit->fs.fragcoord_input_index);
6105
6106 /* save the input index */
6107 unsigned fragcoord_input_index = emit->fs.fragcoord_input_index;
6108 /* set to invalid to prevent substitution in emit_src_register() */
6109 emit->fs.fragcoord_input_index = INVALID_INDEX;
6110
6111 /* MOV fragcoord_tmp.xyz, fragcoord.xyz */
6112 begin_emit_instruction(emit);
6113 emit_opcode(emit, VGPU10_OPCODE_MOV, FALSE);
6114 emit_dst_register(emit, &tmp_dst_xyz);
6115 emit_src_register(emit, &fragcoord);
6116 end_emit_instruction(emit);
6117
6118 /* DIV fragcoord_tmp.w, 1.0, fragcoord.w */
6119 begin_emit_instruction(emit);
6120 emit_opcode(emit, VGPU10_OPCODE_DIV, FALSE);
6121 emit_dst_register(emit, &tmp_dst_w);
6122 emit_src_register(emit, &one);
6123 emit_src_register(emit, &fragcoord);
6124 end_emit_instruction(emit);
6125
6126 /* restore saved value */
6127 emit->fs.fragcoord_input_index = fragcoord_input_index;
6128 }
6129 }
6130
6131
6132 /**
6133 * Emit extra instructions to adjust VS inputs/attributes. This can
6134 * mean casting a vertex attribute from int to float or setting the
6135 * W component to 1, or both.
6136 */
6137 static void
6138 emit_vertex_attrib_instructions(struct svga_shader_emitter_v10 *emit)
6139 {
6140 const unsigned save_w_1_mask = emit->key.vs.adjust_attrib_w_1;
6141 const unsigned save_itof_mask = emit->key.vs.adjust_attrib_itof;
6142 const unsigned save_utof_mask = emit->key.vs.adjust_attrib_utof;
6143 const unsigned save_is_bgra_mask = emit->key.vs.attrib_is_bgra;
6144 const unsigned save_puint_to_snorm_mask = emit->key.vs.attrib_puint_to_snorm;
6145 const unsigned save_puint_to_uscaled_mask = emit->key.vs.attrib_puint_to_uscaled;
6146 const unsigned save_puint_to_sscaled_mask = emit->key.vs.attrib_puint_to_sscaled;
6147
6148 unsigned adjust_mask = (save_w_1_mask |
6149 save_itof_mask |
6150 save_utof_mask |
6151 save_is_bgra_mask |
6152 save_puint_to_snorm_mask |
6153 save_puint_to_uscaled_mask |
6154 save_puint_to_sscaled_mask);
6155
6156 assert(emit->unit == PIPE_SHADER_VERTEX);
6157
6158 if (adjust_mask) {
6159 struct tgsi_full_src_register one =
6160 make_immediate_reg_float(emit, 1.0f);
6161
6162 struct tgsi_full_src_register one_int =
6163 make_immediate_reg_int(emit, 1);
6164
6165 /* We need to turn off these bitmasks while emitting the
6166 * instructions below, then restore them afterward.
6167 */
6168 emit->key.vs.adjust_attrib_w_1 = 0;
6169 emit->key.vs.adjust_attrib_itof = 0;
6170 emit->key.vs.adjust_attrib_utof = 0;
6171 emit->key.vs.attrib_is_bgra = 0;
6172 emit->key.vs.attrib_puint_to_snorm = 0;
6173 emit->key.vs.attrib_puint_to_uscaled = 0;
6174 emit->key.vs.attrib_puint_to_sscaled = 0;
6175
6176 while (adjust_mask) {
6177 unsigned index = u_bit_scan(&adjust_mask);
6178
6179 /* skip the instruction if this vertex attribute is not being used */
6180 if (emit->info.input_usage_mask[index] == 0)
6181 continue;
6182
6183 unsigned tmp = emit->vs.adjusted_input[index];
6184 struct tgsi_full_src_register input_src =
6185 make_src_reg(TGSI_FILE_INPUT, index);
6186
6187 struct tgsi_full_dst_register tmp_dst = make_dst_temp_reg(tmp);
6188 struct tgsi_full_src_register tmp_src = make_src_temp_reg(tmp);
6189 struct tgsi_full_dst_register tmp_dst_w =
6190 writemask_dst(&tmp_dst, TGSI_WRITEMASK_W);
6191
6192 /* ITOF/UTOF/MOV tmp, input[index] */
6193 if (save_itof_mask & (1 << index)) {
6194 emit_instruction_op1(emit, VGPU10_OPCODE_ITOF,
6195 &tmp_dst, &input_src, FALSE);
6196 }
6197 else if (save_utof_mask & (1 << index)) {
6198 emit_instruction_op1(emit, VGPU10_OPCODE_UTOF,
6199 &tmp_dst, &input_src, FALSE);
6200 }
6201 else if (save_puint_to_snorm_mask & (1 << index)) {
6202 emit_puint_to_snorm(emit, &tmp_dst, &input_src);
6203 }
6204 else if (save_puint_to_uscaled_mask & (1 << index)) {
6205 emit_puint_to_uscaled(emit, &tmp_dst, &input_src);
6206 }
6207 else if (save_puint_to_sscaled_mask & (1 << index)) {
6208 emit_puint_to_sscaled(emit, &tmp_dst, &input_src);
6209 }
6210 else {
6211 assert((save_w_1_mask | save_is_bgra_mask) & (1 << index));
6212 emit_instruction_op1(emit, VGPU10_OPCODE_MOV,
6213 &tmp_dst, &input_src, FALSE);
6214 }
6215
6216 if (save_is_bgra_mask & (1 << index)) {
6217 emit_swap_r_b(emit, &tmp_dst, &tmp_src);
6218 }
6219
6220 if (save_w_1_mask & (1 << index)) {
6221 /* MOV tmp.w, 1.0 */
6222 if (emit->key.vs.attrib_is_pure_int & (1 << index)) {
6223 emit_instruction_op1(emit, VGPU10_OPCODE_MOV,
6224 &tmp_dst_w, &one_int, FALSE);
6225 }
6226 else {
6227 emit_instruction_op1(emit, VGPU10_OPCODE_MOV,
6228 &tmp_dst_w, &one, FALSE);
6229 }
6230 }
6231 }
6232
6233 emit->key.vs.adjust_attrib_w_1 = save_w_1_mask;
6234 emit->key.vs.adjust_attrib_itof = save_itof_mask;
6235 emit->key.vs.adjust_attrib_utof = save_utof_mask;
6236 emit->key.vs.attrib_is_bgra = save_is_bgra_mask;
6237 emit->key.vs.attrib_puint_to_snorm = save_puint_to_snorm_mask;
6238 emit->key.vs.attrib_puint_to_uscaled = save_puint_to_uscaled_mask;
6239 emit->key.vs.attrib_puint_to_sscaled = save_puint_to_sscaled_mask;
6240 }
6241 }
6242
6243
6244 /**
6245 * Some common values like 0.0, 1.0, 0.5, etc. are frequently needed
6246 * to implement some instructions. We pre-allocate those values here
6247 * in the immediate constant buffer.
6248 */
6249 static void
6250 alloc_common_immediates(struct svga_shader_emitter_v10 *emit)
6251 {
6252 unsigned n = 0;
6253
6254 emit->common_immediate_pos[n++] =
6255 alloc_immediate_float4(emit, 0.0f, 1.0f, 0.5f, -1.0f);
6256
6257 emit->common_immediate_pos[n++] =
6258 alloc_immediate_float4(emit, 128.0f, -128.0f, 2.0f, 3.0f);
6259
6260 emit->common_immediate_pos[n++] =
6261 alloc_immediate_int4(emit, 0, 1, 0, -1);
6262
6263 if (emit->key.vs.attrib_puint_to_snorm) {
6264 emit->common_immediate_pos[n++] =
6265 alloc_immediate_float4(emit, -2.0f, -2.0f, -2.0f, -1.66666f);
6266 }
6267
6268 if (emit->key.vs.attrib_puint_to_uscaled) {
6269 emit->common_immediate_pos[n++] =
6270 alloc_immediate_float4(emit, 1023.0f, 3.0f, 0.0f, 0.0f);
6271 }
6272
6273 if (emit->key.vs.attrib_puint_to_sscaled) {
6274 emit->common_immediate_pos[n++] =
6275 alloc_immediate_int4(emit, 22, 12, 2, 0);
6276
6277 emit->common_immediate_pos[n++] =
6278 alloc_immediate_int4(emit, 22, 30, 0, 0);
6279 }
6280
6281 assert(n <= ARRAY_SIZE(emit->common_immediate_pos));
6282 emit->num_common_immediates = n;
6283 }
6284
6285
6286 /**
6287 * Emit any extra/helper declarations/code that we might need between
6288 * the declaration section and code section.
6289 */
6290 static boolean
6291 emit_pre_helpers(struct svga_shader_emitter_v10 *emit)
6292 {
6293 /* Properties */
6294 if (emit->unit == PIPE_SHADER_GEOMETRY)
6295 emit_property_instructions(emit);
6296
6297 /* Declare inputs */
6298 if (!emit_input_declarations(emit))
6299 return FALSE;
6300
6301 /* Declare outputs */
6302 if (!emit_output_declarations(emit))
6303 return FALSE;
6304
6305 /* Declare temporary registers */
6306 emit_temporaries_declaration(emit);
6307
6308 /* Declare constant registers */
6309 emit_constant_declaration(emit);
6310
6311 /* Declare samplers and resources */
6312 emit_sampler_declarations(emit);
6313 emit_resource_declarations(emit);
6314
6315 /* Declare clip distance output registers */
6316 if (emit->unit == PIPE_SHADER_VERTEX ||
6317 emit->unit == PIPE_SHADER_GEOMETRY) {
6318 emit_clip_distance_declarations(emit);
6319 }
6320
6321 alloc_common_immediates(emit);
6322
6323 if (emit->unit == PIPE_SHADER_FRAGMENT &&
6324 emit->key.fs.alpha_func != SVGA3D_CMP_ALWAYS) {
6325 float alpha = emit->key.fs.alpha_ref;
6326 emit->fs.alpha_ref_index =
6327 alloc_immediate_float4(emit, alpha, alpha, alpha, alpha);
6328 }
6329
6330 /* Now, emit the constant block containing all the immediates
6331 * declared by shader, as well as the extra ones seen above.
6332 */
6333 emit_vgpu10_immediates_block(emit);
6334
6335 if (emit->unit == PIPE_SHADER_FRAGMENT) {
6336 emit_frontface_instructions(emit);
6337 emit_fragcoord_instructions(emit);
6338 }
6339 else if (emit->unit == PIPE_SHADER_VERTEX) {
6340 emit_vertex_attrib_instructions(emit);
6341 }
6342
6343 return TRUE;
6344 }
6345
6346
6347 /**
6348 * Emit alpha test code. This compares TEMP[fs_color_tmp_index].w
6349 * against the alpha reference value and discards the fragment if the
6350 * comparison fails.
6351 */
6352 static void
6353 emit_alpha_test_instructions(struct svga_shader_emitter_v10 *emit,
6354 unsigned fs_color_tmp_index)
6355 {
6356 /* compare output color's alpha to alpha ref and kill */
6357 unsigned tmp = get_temp_index(emit);
6358 struct tgsi_full_src_register tmp_src = make_src_temp_reg(tmp);
6359 struct tgsi_full_src_register tmp_src_x =
6360 scalar_src(&tmp_src, TGSI_SWIZZLE_X);
6361 struct tgsi_full_dst_register tmp_dst = make_dst_temp_reg(tmp);
6362 struct tgsi_full_src_register color_src =
6363 make_src_temp_reg(fs_color_tmp_index);
6364 struct tgsi_full_src_register color_src_w =
6365 scalar_src(&color_src, TGSI_SWIZZLE_W);
6366 struct tgsi_full_src_register ref_src =
6367 make_src_immediate_reg(emit->fs.alpha_ref_index);
6368 struct tgsi_full_dst_register color_dst =
6369 make_dst_output_reg(emit->fs.color_out_index[0]);
6370
6371 assert(emit->unit == PIPE_SHADER_FRAGMENT);
6372
6373 /* dst = src0 'alpha_func' src1 */
6374 emit_comparison(emit, emit->key.fs.alpha_func, &tmp_dst,
6375 &color_src_w, &ref_src);
6376
6377 /* DISCARD if dst.x == 0 */
6378 begin_emit_instruction(emit);
6379 emit_discard_opcode(emit, FALSE); /* discard if src0.x is zero */
6380 emit_src_register(emit, &tmp_src_x);
6381 end_emit_instruction(emit);
6382
6383 /* If we don't need to broadcast the color below or set fragments to
6384 * white, emit final color here.
6385 */
6386 if (emit->key.fs.write_color0_to_n_cbufs <= 1 &&
6387 !emit->key.fs.white_fragments) {
6388 /* MOV output.color, tempcolor */
6389 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &color_dst,
6390 &color_src, FALSE); /* XXX saturate? */
6391 }
6392
6393 free_temp_indexes(emit);
6394 }
6395
6396
6397 /**
6398 * When we need to emit white for all fragments (for emulating XOR logicop
6399 * mode), this function copies white into the temporary color output register.
6400 */
6401 static void
6402 emit_set_color_white(struct svga_shader_emitter_v10 *emit,
6403 unsigned fs_color_tmp_index)
6404 {
6405 struct tgsi_full_dst_register color_dst =
6406 make_dst_temp_reg(fs_color_tmp_index);
6407 struct tgsi_full_src_register white =
6408 make_immediate_reg_float(emit, 1.0f);
6409
6410 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &color_dst, &white, FALSE);
6411 }
6412
6413
6414 /**
6415 * Emit instructions for writing a single color output to multiple
6416 * color buffers.
6417 * This is used when the TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS (or
6418 * when key.fs.white_fragments is true).
6419 * property is set and the number of render targets is greater than one.
6420 * \param fs_color_tmp_index index of the temp register that holds the
6421 * color to broadcast.
6422 */
6423 static void
6424 emit_broadcast_color_instructions(struct svga_shader_emitter_v10 *emit,
6425 unsigned fs_color_tmp_index)
6426 {
6427 const unsigned n = emit->key.fs.write_color0_to_n_cbufs;
6428 unsigned i;
6429 struct tgsi_full_src_register color_src =
6430 make_src_temp_reg(fs_color_tmp_index);
6431
6432 assert(emit->unit == PIPE_SHADER_FRAGMENT);
6433
6434 for (i = 0; i < n; i++) {
6435 unsigned output_reg = emit->fs.color_out_index[i];
6436 struct tgsi_full_dst_register color_dst =
6437 make_dst_output_reg(output_reg);
6438
6439 /* Fill in this semantic here since we'll use it later in
6440 * emit_dst_register().
6441 */
6442 emit->info.output_semantic_name[output_reg] = TGSI_SEMANTIC_COLOR;
6443
6444 /* MOV output.color[i], tempcolor */
6445 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &color_dst,
6446 &color_src, FALSE); /* XXX saturate? */
6447 }
6448 }
6449
6450
6451 /**
6452 * Emit extra helper code after the original shader code, but before the
6453 * last END/RET instruction.
6454 * For vertex shaders this means emitting the extra code to apply the
6455 * prescale scale/translation.
6456 */
6457 static boolean
6458 emit_post_helpers(struct svga_shader_emitter_v10 *emit)
6459 {
6460 if (emit->unit == PIPE_SHADER_VERTEX) {
6461 emit_vertex_instructions(emit);
6462 }
6463 else if (emit->unit == PIPE_SHADER_FRAGMENT) {
6464 const unsigned fs_color_tmp_index = emit->fs.color_tmp_index;
6465
6466 /* We no longer want emit_dst_register() to substitute the
6467 * temporary fragment color register for the real color output.
6468 */
6469 emit->fs.color_tmp_index = INVALID_INDEX;
6470
6471 if (emit->key.fs.alpha_func != SVGA3D_CMP_ALWAYS) {
6472 emit_alpha_test_instructions(emit, fs_color_tmp_index);
6473 }
6474 if (emit->key.fs.white_fragments) {
6475 emit_set_color_white(emit, fs_color_tmp_index);
6476 }
6477 if (emit->key.fs.write_color0_to_n_cbufs > 1 ||
6478 emit->key.fs.white_fragments) {
6479 emit_broadcast_color_instructions(emit, fs_color_tmp_index);
6480 }
6481 }
6482
6483 return TRUE;
6484 }
6485
6486
6487 /**
6488 * Translate the TGSI tokens into VGPU10 tokens.
6489 */
6490 static boolean
6491 emit_vgpu10_instructions(struct svga_shader_emitter_v10 *emit,
6492 const struct tgsi_token *tokens)
6493 {
6494 struct tgsi_parse_context parse;
6495 boolean ret = TRUE;
6496 boolean pre_helpers_emitted = FALSE;
6497 unsigned inst_number = 0;
6498
6499 tgsi_parse_init(&parse, tokens);
6500
6501 while (!tgsi_parse_end_of_tokens(&parse)) {
6502 tgsi_parse_token(&parse);
6503
6504 switch (parse.FullToken.Token.Type) {
6505 case TGSI_TOKEN_TYPE_IMMEDIATE:
6506 ret = emit_vgpu10_immediate(emit, &parse.FullToken.FullImmediate);
6507 if (!ret)
6508 goto done;
6509 break;
6510
6511 case TGSI_TOKEN_TYPE_DECLARATION:
6512 ret = emit_vgpu10_declaration(emit, &parse.FullToken.FullDeclaration);
6513 if (!ret)
6514 goto done;
6515 break;
6516
6517 case TGSI_TOKEN_TYPE_INSTRUCTION:
6518 if (!pre_helpers_emitted) {
6519 ret = emit_pre_helpers(emit);
6520 if (!ret)
6521 goto done;
6522 pre_helpers_emitted = TRUE;
6523 }
6524 ret = emit_vgpu10_instruction(emit, inst_number++,
6525 &parse.FullToken.FullInstruction);
6526 if (!ret)
6527 goto done;
6528 break;
6529
6530 case TGSI_TOKEN_TYPE_PROPERTY:
6531 ret = emit_vgpu10_property(emit, &parse.FullToken.FullProperty);
6532 if (!ret)
6533 goto done;
6534 break;
6535
6536 default:
6537 break;
6538 }
6539 }
6540
6541 done:
6542 tgsi_parse_free(&parse);
6543 return ret;
6544 }
6545
6546
6547 /**
6548 * Emit the first VGPU10 shader tokens.
6549 */
6550 static boolean
6551 emit_vgpu10_header(struct svga_shader_emitter_v10 *emit)
6552 {
6553 VGPU10ProgramToken ptoken;
6554
6555 /* First token: VGPU10ProgramToken (version info, program type (VS,GS,PS)) */
6556 ptoken.majorVersion = 4;
6557 ptoken.minorVersion = 0;
6558 ptoken.programType = translate_shader_type(emit->unit);
6559 if (!emit_dword(emit, ptoken.value))
6560 return FALSE;
6561
6562 /* Second token: total length of shader, in tokens. We can't fill this
6563 * in until we're all done. Emit zero for now.
6564 */
6565 return emit_dword(emit, 0);
6566 }
6567
6568
6569 static boolean
6570 emit_vgpu10_tail(struct svga_shader_emitter_v10 *emit)
6571 {
6572 VGPU10ProgramToken *tokens;
6573
6574 /* Replace the second token with total shader length */
6575 tokens = (VGPU10ProgramToken *) emit->buf;
6576 tokens[1].value = emit_get_num_tokens(emit);
6577
6578 return TRUE;
6579 }
6580
6581
6582 /**
6583 * Modify the FS to read the BCOLORs and use the FACE register
6584 * to choose between the front/back colors.
6585 */
6586 static const struct tgsi_token *
6587 transform_fs_twoside(const struct tgsi_token *tokens)
6588 {
6589 if (0) {
6590 debug_printf("Before tgsi_add_two_side ------------------\n");
6591 tgsi_dump(tokens,0);
6592 }
6593 tokens = tgsi_add_two_side(tokens);
6594 if (0) {
6595 debug_printf("After tgsi_add_two_side ------------------\n");
6596 tgsi_dump(tokens, 0);
6597 }
6598 return tokens;
6599 }
6600
6601
6602 /**
6603 * Modify the FS to do polygon stipple.
6604 */
6605 static const struct tgsi_token *
6606 transform_fs_pstipple(struct svga_shader_emitter_v10 *emit,
6607 const struct tgsi_token *tokens)
6608 {
6609 const struct tgsi_token *new_tokens;
6610 unsigned unit;
6611
6612 if (0) {
6613 debug_printf("Before pstipple ------------------\n");
6614 tgsi_dump(tokens,0);
6615 }
6616
6617 new_tokens = util_pstipple_create_fragment_shader(tokens, &unit, 0,
6618 TGSI_FILE_INPUT);
6619
6620 emit->fs.pstipple_sampler_unit = unit;
6621
6622 /* Setup texture state for stipple */
6623 emit->sampler_target[unit] = TGSI_TEXTURE_2D;
6624 emit->key.tex[unit].swizzle_r = TGSI_SWIZZLE_X;
6625 emit->key.tex[unit].swizzle_g = TGSI_SWIZZLE_Y;
6626 emit->key.tex[unit].swizzle_b = TGSI_SWIZZLE_Z;
6627 emit->key.tex[unit].swizzle_a = TGSI_SWIZZLE_W;
6628
6629 if (0) {
6630 debug_printf("After pstipple ------------------\n");
6631 tgsi_dump(new_tokens, 0);
6632 }
6633
6634 return new_tokens;
6635 }
6636
6637 /**
6638 * Modify the FS to support anti-aliasing point.
6639 */
6640 static const struct tgsi_token *
6641 transform_fs_aapoint(const struct tgsi_token *tokens,
6642 int aa_coord_index)
6643 {
6644 if (0) {
6645 debug_printf("Before tgsi_add_aa_point ------------------\n");
6646 tgsi_dump(tokens,0);
6647 }
6648 tokens = tgsi_add_aa_point(tokens, aa_coord_index);
6649 if (0) {
6650 debug_printf("After tgsi_add_aa_point ------------------\n");
6651 tgsi_dump(tokens, 0);
6652 }
6653 return tokens;
6654 }
6655
6656 /**
6657 * This is the main entrypoint for the TGSI -> VPGU10 translator.
6658 */
6659 struct svga_shader_variant *
6660 svga_tgsi_vgpu10_translate(struct svga_context *svga,
6661 const struct svga_shader *shader,
6662 const struct svga_compile_key *key,
6663 unsigned unit)
6664 {
6665 struct svga_shader_variant *variant = NULL;
6666 struct svga_shader_emitter_v10 *emit;
6667 const struct tgsi_token *tokens = shader->tokens;
6668 struct svga_vertex_shader *vs = svga->curr.vs;
6669 struct svga_geometry_shader *gs = svga->curr.gs;
6670
6671 assert(unit == PIPE_SHADER_VERTEX ||
6672 unit == PIPE_SHADER_GEOMETRY ||
6673 unit == PIPE_SHADER_FRAGMENT);
6674
6675 /* These two flags cannot be used together */
6676 assert(key->vs.need_prescale + key->vs.undo_viewport <= 1);
6677
6678 SVGA_STATS_TIME_PUSH(svga_sws(svga), SVGA_STATS_TIME_TGSIVGPU10TRANSLATE);
6679 /*
6680 * Setup the code emitter
6681 */
6682 emit = alloc_emitter();
6683 if (!emit)
6684 goto done;
6685
6686 emit->unit = unit;
6687 emit->key = *key;
6688
6689 emit->vposition.need_prescale = (emit->key.vs.need_prescale ||
6690 emit->key.gs.need_prescale);
6691 emit->vposition.tmp_index = INVALID_INDEX;
6692 emit->vposition.so_index = INVALID_INDEX;
6693 emit->vposition.out_index = INVALID_INDEX;
6694
6695 emit->fs.color_tmp_index = INVALID_INDEX;
6696 emit->fs.face_input_index = INVALID_INDEX;
6697 emit->fs.fragcoord_input_index = INVALID_INDEX;
6698
6699 emit->gs.prim_id_index = INVALID_INDEX;
6700
6701 emit->clip_dist_out_index = INVALID_INDEX;
6702 emit->clip_dist_tmp_index = INVALID_INDEX;
6703 emit->clip_dist_so_index = INVALID_INDEX;
6704 emit->clip_vertex_out_index = INVALID_INDEX;
6705
6706 if (emit->key.fs.alpha_func == SVGA3D_CMP_INVALID) {
6707 emit->key.fs.alpha_func = SVGA3D_CMP_ALWAYS;
6708 }
6709
6710 if (unit == PIPE_SHADER_FRAGMENT) {
6711 if (key->fs.light_twoside) {
6712 tokens = transform_fs_twoside(tokens);
6713 }
6714 if (key->fs.pstipple) {
6715 const struct tgsi_token *new_tokens =
6716 transform_fs_pstipple(emit, tokens);
6717 if (tokens != shader->tokens) {
6718 /* free the two-sided shader tokens */
6719 tgsi_free_tokens(tokens);
6720 }
6721 tokens = new_tokens;
6722 }
6723 if (key->fs.aa_point) {
6724 tokens = transform_fs_aapoint(tokens, key->fs.aa_point_coord_index);
6725 }
6726 }
6727
6728 if (SVGA_DEBUG & DEBUG_TGSI) {
6729 debug_printf("#####################################\n");
6730 debug_printf("### TGSI Shader %u\n", shader->id);
6731 tgsi_dump(tokens, 0);
6732 }
6733
6734 /**
6735 * Rescan the header if the token string is different from the one
6736 * included in the shader; otherwise, the header info is already up-to-date
6737 */
6738 if (tokens != shader->tokens) {
6739 tgsi_scan_shader(tokens, &emit->info);
6740 } else {
6741 emit->info = shader->info;
6742 }
6743
6744 emit->num_outputs = emit->info.num_outputs;
6745
6746 if (unit == PIPE_SHADER_FRAGMENT) {
6747 /* Compute FS input remapping to match the output from VS/GS */
6748 if (gs) {
6749 svga_link_shaders(&gs->base.info, &emit->info, &emit->linkage);
6750 } else {
6751 assert(vs);
6752 svga_link_shaders(&vs->base.info, &emit->info, &emit->linkage);
6753 }
6754 } else if (unit == PIPE_SHADER_GEOMETRY) {
6755 assert(vs);
6756 svga_link_shaders(&vs->base.info, &emit->info, &emit->linkage);
6757 }
6758
6759 determine_clipping_mode(emit);
6760
6761 if (unit == PIPE_SHADER_GEOMETRY || unit == PIPE_SHADER_VERTEX) {
6762 if (shader->stream_output != NULL || emit->clip_mode == CLIP_DISTANCE) {
6763 /* if there is stream output declarations associated
6764 * with this shader or the shader writes to ClipDistance
6765 * then reserve extra registers for the non-adjusted vertex position
6766 * and the ClipDistance shadow copy
6767 */
6768 emit->vposition.so_index = emit->num_outputs++;
6769
6770 if (emit->clip_mode == CLIP_DISTANCE) {
6771 emit->clip_dist_so_index = emit->num_outputs++;
6772 if (emit->info.num_written_clipdistance > 4)
6773 emit->num_outputs++;
6774 }
6775 }
6776 }
6777
6778 /*
6779 * Do actual shader translation.
6780 */
6781 if (!emit_vgpu10_header(emit)) {
6782 debug_printf("svga: emit VGPU10 header failed\n");
6783 goto cleanup;
6784 }
6785
6786 if (!emit_vgpu10_instructions(emit, tokens)) {
6787 debug_printf("svga: emit VGPU10 instructions failed\n");
6788 goto cleanup;
6789 }
6790
6791 if (!emit_vgpu10_tail(emit)) {
6792 debug_printf("svga: emit VGPU10 tail failed\n");
6793 goto cleanup;
6794 }
6795
6796 if (emit->register_overflow) {
6797 goto cleanup;
6798 }
6799
6800 /*
6801 * Create, initialize the 'variant' object.
6802 */
6803 variant = svga_new_shader_variant(svga);
6804 if (!variant)
6805 goto cleanup;
6806
6807 variant->shader = shader;
6808 variant->nr_tokens = emit_get_num_tokens(emit);
6809 variant->tokens = (const unsigned *)emit->buf;
6810 emit->buf = NULL; /* buffer is no longer owed by emitter context */
6811 memcpy(&variant->key, key, sizeof(*key));
6812 variant->id = UTIL_BITMASK_INVALID_INDEX;
6813
6814 /* The extra constant starting offset starts with the number of
6815 * shader constants declared in the shader.
6816 */
6817 variant->extra_const_start = emit->num_shader_consts[0];
6818 if (key->gs.wide_point) {
6819 /**
6820 * The extra constant added in the transformed shader
6821 * for inverse viewport scale is to be supplied by the driver.
6822 * So the extra constant starting offset needs to be reduced by 1.
6823 */
6824 assert(variant->extra_const_start > 0);
6825 variant->extra_const_start--;
6826 }
6827
6828 variant->pstipple_sampler_unit = emit->fs.pstipple_sampler_unit;
6829
6830 /* If there was exactly one write to a fragment shader output register
6831 * and it came from a constant buffer, we know all fragments will have
6832 * the same color (except for blending).
6833 */
6834 variant->constant_color_output =
6835 emit->constant_color_output && emit->num_output_writes == 1;
6836
6837 /** keep track in the variant if flat interpolation is used
6838 * for any of the varyings.
6839 */
6840 variant->uses_flat_interp = emit->uses_flat_interp;
6841
6842 if (tokens != shader->tokens) {
6843 tgsi_free_tokens(tokens);
6844 }
6845
6846 cleanup:
6847 free_emitter(emit);
6848
6849 done:
6850 SVGA_STATS_TIME_POP(svga_sws(svga));
6851 return variant;
6852 }