projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
svga: add support for TXL2 opcode
[mesa.git] / src / gallium / drivers / svga / svga_tgsi_vgpu10.c
1 /**********************************************************
2 * Copyright 1998-2013 VMware, Inc. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 **********************************************************/
25
26 /**
27 * @file svga_tgsi_vgpu10.c
28 *
29 * TGSI -> VGPU10 shader translation.
30 *
31 * \author Mingcheng Chen
32 * \author Brian Paul
33 */
34
35 #include "pipe/p_compiler.h"
36 #include "pipe/p_shader_tokens.h"
37 #include "pipe/p_defines.h"
38 #include "tgsi/tgsi_build.h"
39 #include "tgsi/tgsi_dump.h"
40 #include "tgsi/tgsi_info.h"
41 #include "tgsi/tgsi_parse.h"
42 #include "tgsi/tgsi_scan.h"
43 #include "tgsi/tgsi_two_side.h"
44 #include "tgsi/tgsi_aa_point.h"
45 #include "tgsi/tgsi_util.h"
46 #include "util/u_math.h"
47 #include "util/u_memory.h"
48 #include "util/u_bitmask.h"
49 #include "util/u_debug.h"
50 #include "util/u_pstipple.h"
51
52 #include "svga_context.h"
53 #include "svga_debug.h"
54 #include "svga_link.h"
55 #include "svga_shader.h"
56 #include "svga_tgsi.h"
57
58 #include "VGPU10ShaderTokens.h"
59
60
61 #define INVALID_INDEX 99999
62 #define MAX_INTERNAL_TEMPS 3
63 #define MAX_SYSTEM_VALUES 4
64 #define MAX_IMMEDIATE_COUNT \
65 (VGPU10_MAX_IMMEDIATE_CONSTANT_BUFFER_ELEMENT_COUNT/4)
66 #define MAX_TEMP_ARRAYS 64 /* Enough? */
67
68
69 /**
70 * Clipping is complicated. There's four different cases which we
71 * handle during VS/GS shader translation:
72 */
73 enum clipping_mode
74 {
75 CLIP_NONE, /**< No clipping enabled */
76 CLIP_LEGACY, /**< The shader has no clipping declarations or code but
77 * one or more user-defined clip planes are enabled. We
78 * generate extra code to emit clip distances.
79 */
80 CLIP_DISTANCE, /**< The shader already declares clip distance output
81 * registers and has code to write to them.
82 */
83 CLIP_VERTEX /**< The shader declares a clip vertex output register and
84 * has code that writes to the register. We convert the
85 * clipvertex position into one or more clip distances.
86 */
87 };
88
89
90 struct svga_shader_emitter_v10
91 {
92 /* The token output buffer */
93 unsigned size;
94 char *buf;
95 char *ptr;
96
97 /* Information about the shader and state (does not change) */
98 struct svga_compile_key key;
99 struct tgsi_shader_info info;
100 unsigned unit;
101
102 unsigned inst_start_token;
103 boolean discard_instruction; /**< throw away current instruction? */
104
105 union tgsi_immediate_data immediates[MAX_IMMEDIATE_COUNT][4];
106 unsigned num_immediates; /**< Number of immediates emitted */
107 unsigned common_immediate_pos[8]; /**< literals for common immediates */
108 unsigned num_common_immediates;
109 boolean immediates_emitted;
110
111 unsigned num_outputs; /**< include any extra outputs */
112 /** The first extra output is reserved for
113 * non-adjusted vertex position for
114 * stream output purpose
115 */
116
117 /* Temporary Registers */
118 unsigned num_shader_temps; /**< num of temps used by original shader */
119 unsigned internal_temp_count; /**< currently allocated internal temps */
120 struct {
121 unsigned start, size;
122 } temp_arrays[MAX_TEMP_ARRAYS];
123 unsigned num_temp_arrays;
124
125 /** Map TGSI temp registers to VGPU10 temp array IDs and indexes */
126 struct {
127 unsigned arrayId, index;
128 } temp_map[VGPU10_MAX_TEMPS]; /**< arrayId, element */
129
130 /** Number of constants used by original shader for each constant buffer.
131 * The size should probably always match with that of svga_state.constbufs.
132 */
133 unsigned num_shader_consts[SVGA_MAX_CONST_BUFS];
134
135 /* Samplers */
136 unsigned num_samplers;
137 boolean sampler_view[PIPE_MAX_SAMPLERS]; /**< True if sampler view exists*/
138 ubyte sampler_target[PIPE_MAX_SAMPLERS]; /**< TGSI_TEXTURE_x */
139 ubyte sampler_return_type[PIPE_MAX_SAMPLERS]; /**< TGSI_RETURN_TYPE_x */
140
141 /* Address regs (really implemented with temps) */
142 unsigned num_address_regs;
143 unsigned address_reg_index[MAX_VGPU10_ADDR_REGS];
144
145 /* Output register usage masks */
146 ubyte output_usage_mask[PIPE_MAX_SHADER_OUTPUTS];
147
148 /* To map TGSI system value index to VGPU shader input indexes */
149 ubyte system_value_indexes[MAX_SYSTEM_VALUES];
150
151 struct {
152 /* vertex position scale/translation */
153 unsigned out_index; /**< the real position output reg */
154 unsigned tmp_index; /**< the fake/temp position output reg */
155 unsigned so_index; /**< the non-adjusted position output reg */
156 unsigned prescale_scale_index, prescale_trans_index;
157 boolean need_prescale;
158 } vposition;
159
160 /* For vertex shaders only */
161 struct {
162 /* viewport constant */
163 unsigned viewport_index;
164
165 /* temp index of adjusted vertex attributes */
166 unsigned adjusted_input[PIPE_MAX_SHADER_INPUTS];
167 } vs;
168
169 /* For fragment shaders only */
170 struct {
171 unsigned color_out_index[PIPE_MAX_COLOR_BUFS]; /**< the real color output regs */
172 unsigned num_color_outputs;
173 unsigned color_tmp_index; /**< fake/temp color output reg */
174 unsigned alpha_ref_index; /**< immediate constant for alpha ref */
175
176 /* front-face */
177 unsigned face_input_index; /**< real fragment shader face reg (bool) */
178 unsigned face_tmp_index; /**< temp face reg converted to -1 / +1 */
179
180 unsigned pstipple_sampler_unit;
181
182 unsigned fragcoord_input_index; /**< real fragment position input reg */
183 unsigned fragcoord_tmp_index; /**< 1/w modified position temp reg */
184
185 /** Which texture units are doing shadow comparison in the FS code */
186 unsigned shadow_compare_units;
187 } fs;
188
189 /* For geometry shaders only */
190 struct {
191 VGPU10_PRIMITIVE prim_type;/**< VGPU10 primitive type */
192 VGPU10_PRIMITIVE_TOPOLOGY prim_topology; /**< VGPU10 primitive topology */
193 unsigned input_size; /**< size of input arrays */
194 unsigned prim_id_index; /**< primitive id register index */
195 unsigned max_out_vertices; /**< maximum number of output vertices */
196 } gs;
197
198 /* For vertex or geometry shaders */
199 enum clipping_mode clip_mode;
200 unsigned clip_dist_out_index; /**< clip distance output register index */
201 unsigned clip_dist_tmp_index; /**< clip distance temporary register */
202 unsigned clip_dist_so_index; /**< clip distance shadow copy */
203
204 /** Index of temporary holding the clipvertex coordinate */
205 unsigned clip_vertex_out_index; /**< clip vertex output register index */
206 unsigned clip_vertex_tmp_index; /**< clip vertex temporary index */
207
208 /* user clip plane constant slot indexes */
209 unsigned clip_plane_const[PIPE_MAX_CLIP_PLANES];
210
211 unsigned num_output_writes;
212 boolean constant_color_output;
213
214 boolean uses_flat_interp;
215
216 /* For all shaders: const reg index for RECT coord scaling */
217 unsigned texcoord_scale_index[PIPE_MAX_SAMPLERS];
218
219 /* For all shaders: const reg index for texture buffer size */
220 unsigned texture_buffer_size_index[PIPE_MAX_SAMPLERS];
221
222 /* VS/GS/FS Linkage info */
223 struct shader_linkage linkage;
224
225 bool register_overflow; /**< Set if we exceed a VGPU10 register limit */
226 };
227
228
229 static boolean
230 emit_post_helpers(struct svga_shader_emitter_v10 *emit);
231
232 static boolean
233 emit_vertex(struct svga_shader_emitter_v10 *emit,
234 const struct tgsi_full_instruction *inst);
235
236 static char err_buf[128];
237
238 static boolean
239 expand(struct svga_shader_emitter_v10 *emit)
240 {
241 char *new_buf;
242 unsigned newsize = emit->size * 2;
243
244 if (emit->buf != err_buf)
245 new_buf = REALLOC(emit->buf, emit->size, newsize);
246 else
247 new_buf = NULL;
248
249 if (!new_buf) {
250 emit->ptr = err_buf;
251 emit->buf = err_buf;
252 emit->size = sizeof(err_buf);
253 return FALSE;
254 }
255
256 emit->size = newsize;
257 emit->ptr = new_buf + (emit->ptr - emit->buf);
258 emit->buf = new_buf;
259 return TRUE;
260 }
261
262 /**
263 * Create and initialize a new svga_shader_emitter_v10 object.
264 */
265 static struct svga_shader_emitter_v10 *
266 alloc_emitter(void)
267 {
268 struct svga_shader_emitter_v10 *emit = CALLOC(1, sizeof(*emit));
269
270 if (!emit)
271 return NULL;
272
273 /* to initialize the output buffer */
274 emit->size = 512;
275 if (!expand(emit)) {
276 FREE(emit);
277 return NULL;
278 }
279 return emit;
280 }
281
282 /**
283 * Free an svga_shader_emitter_v10 object.
284 */
285 static void
286 free_emitter(struct svga_shader_emitter_v10 *emit)
287 {
288 assert(emit);
289 FREE(emit->buf); /* will be NULL if translation succeeded */
290 FREE(emit);
291 }
292
293 static inline boolean
294 reserve(struct svga_shader_emitter_v10 *emit,
295 unsigned nr_dwords)
296 {
297 while (emit->ptr - emit->buf + nr_dwords * sizeof(uint32) >= emit->size) {
298 if (!expand(emit))
299 return FALSE;
300 }
301
302 return TRUE;
303 }
304
305 static boolean
306 emit_dword(struct svga_shader_emitter_v10 *emit, uint32 dword)
307 {
308 if (!reserve(emit, 1))
309 return FALSE;
310
311 *(uint32 *)emit->ptr = dword;
312 emit->ptr += sizeof dword;
313 return TRUE;
314 }
315
316 static boolean
317 emit_dwords(struct svga_shader_emitter_v10 *emit,
318 const uint32 *dwords,
319 unsigned nr)
320 {
321 if (!reserve(emit, nr))
322 return FALSE;
323
324 memcpy(emit->ptr, dwords, nr * sizeof *dwords);
325 emit->ptr += nr * sizeof *dwords;
326 return TRUE;
327 }
328
329 /** Return the number of tokens in the emitter's buffer */
330 static unsigned
331 emit_get_num_tokens(const struct svga_shader_emitter_v10 *emit)
332 {
333 return (emit->ptr - emit->buf) / sizeof(unsigned);
334 }
335
336
337 /**
338 * Check for register overflow. If we overflow we'll set an
339 * error flag. This function can be called for register declarations
340 * or use as src/dst instruction operands.
341 * \param type register type. One of VGPU10_OPERAND_TYPE_x
342 or VGPU10_OPCODE_DCL_x
343 * \param index the register index
344 */
345 static void
346 check_register_index(struct svga_shader_emitter_v10 *emit,
347 unsigned operandType, unsigned index)
348 {
349 bool overflow_before = emit->register_overflow;
350
351 switch (operandType) {
352 case VGPU10_OPERAND_TYPE_TEMP:
353 case VGPU10_OPERAND_TYPE_INDEXABLE_TEMP:
354 case VGPU10_OPCODE_DCL_TEMPS:
355 if (index >= VGPU10_MAX_TEMPS) {
356 emit->register_overflow = TRUE;
357 }
358 break;
359 case VGPU10_OPERAND_TYPE_CONSTANT_BUFFER:
360 case VGPU10_OPCODE_DCL_CONSTANT_BUFFER:
361 if (index >= VGPU10_MAX_CONSTANT_BUFFER_ELEMENT_COUNT) {
362 emit->register_overflow = TRUE;
363 }
364 break;
365 case VGPU10_OPERAND_TYPE_INPUT:
366 case VGPU10_OPERAND_TYPE_INPUT_PRIMITIVEID:
367 case VGPU10_OPCODE_DCL_INPUT:
368 case VGPU10_OPCODE_DCL_INPUT_SGV:
369 case VGPU10_OPCODE_DCL_INPUT_SIV:
370 case VGPU10_OPCODE_DCL_INPUT_PS:
371 case VGPU10_OPCODE_DCL_INPUT_PS_SGV:
372 case VGPU10_OPCODE_DCL_INPUT_PS_SIV:
373 if ((emit->unit == PIPE_SHADER_VERTEX &&
374 index >= VGPU10_MAX_VS_INPUTS) ||
375 (emit->unit == PIPE_SHADER_GEOMETRY &&
376 index >= VGPU10_MAX_GS_INPUTS) ||
377 (emit->unit == PIPE_SHADER_FRAGMENT &&
378 index >= VGPU10_MAX_FS_INPUTS)) {
379 emit->register_overflow = TRUE;
380 }
381 break;
382 case VGPU10_OPERAND_TYPE_OUTPUT:
383 case VGPU10_OPCODE_DCL_OUTPUT:
384 case VGPU10_OPCODE_DCL_OUTPUT_SGV:
385 case VGPU10_OPCODE_DCL_OUTPUT_SIV:
386 if ((emit->unit == PIPE_SHADER_VERTEX &&
387 index >= VGPU10_MAX_VS_OUTPUTS) ||
388 (emit->unit == PIPE_SHADER_GEOMETRY &&
389 index >= VGPU10_MAX_GS_OUTPUTS) ||
390 (emit->unit == PIPE_SHADER_FRAGMENT &&
391 index >= VGPU10_MAX_FS_OUTPUTS)) {
392 emit->register_overflow = TRUE;
393 }
394 break;
395 case VGPU10_OPERAND_TYPE_SAMPLER:
396 case VGPU10_OPCODE_DCL_SAMPLER:
397 if (index >= VGPU10_MAX_SAMPLERS) {
398 emit->register_overflow = TRUE;
399 }
400 break;
401 case VGPU10_OPERAND_TYPE_RESOURCE:
402 case VGPU10_OPCODE_DCL_RESOURCE:
403 if (index >= VGPU10_MAX_RESOURCES) {
404 emit->register_overflow = TRUE;
405 }
406 break;
407 case VGPU10_OPERAND_TYPE_IMMEDIATE_CONSTANT_BUFFER:
408 if (index >= MAX_IMMEDIATE_COUNT) {
409 emit->register_overflow = TRUE;
410 }
411 break;
412 default:
413 assert(0);
414 ; /* nothing */
415 }
416
417 if (emit->register_overflow && !overflow_before) {
418 debug_printf("svga: vgpu10 register overflow (reg %u, index %u)\n",
419 operandType, index);
420 }
421 }
422
423
424 /**
425 * Examine misc state to determine the clipping mode.
426 */
427 static void
428 determine_clipping_mode(struct svga_shader_emitter_v10 *emit)
429 {
430 if (emit->info.num_written_clipdistance > 0) {
431 emit->clip_mode = CLIP_DISTANCE;
432 }
433 else if (emit->info.writes_clipvertex) {
434 emit->clip_mode = CLIP_VERTEX;
435 }
436 else if (emit->key.clip_plane_enable) {
437 emit->clip_mode = CLIP_LEGACY;
438 }
439 else {
440 emit->clip_mode = CLIP_NONE;
441 }
442 }
443
444
445 /**
446 * For clip distance register declarations and clip distance register
447 * writes we need to mask the declaration usage or instruction writemask
448 * (respectively) against the set of the really-enabled clipping planes.
449 *
450 * The piglit test spec/glsl-1.30/execution/clipping/vs-clip-distance-enables
451 * has a VS that writes to all 8 clip distance registers, but the plane enable
452 * flags are a subset of that.
453 *
454 * This function is used to apply the plane enable flags to the register
455 * declaration or instruction writemask.
456 *
457 * \param writemask the declaration usage mask or instruction writemask
458 * \param clip_reg_index which clip plane register is being declared/written.
459 * The legal values are 0 and 1 (two clip planes per
460 * register, for a total of 8 clip planes)
461 */
462 static unsigned
463 apply_clip_plane_mask(struct svga_shader_emitter_v10 *emit,
464 unsigned writemask, unsigned clip_reg_index)
465 {
466 unsigned shift;
467
468 assert(clip_reg_index < 2);
469
470 /* four clip planes per clip register: */
471 shift = clip_reg_index * 4;
472 writemask &= ((emit->key.clip_plane_enable >> shift) & 0xf);
473
474 return writemask;
475 }
476
477
478 /**
479 * Translate gallium shader type into VGPU10 type.
480 */
481 static VGPU10_PROGRAM_TYPE
482 translate_shader_type(unsigned type)
483 {
484 switch (type) {
485 case PIPE_SHADER_VERTEX:
486 return VGPU10_VERTEX_SHADER;
487 case PIPE_SHADER_GEOMETRY:
488 return VGPU10_GEOMETRY_SHADER;
489 case PIPE_SHADER_FRAGMENT:
490 return VGPU10_PIXEL_SHADER;
491 default:
492 assert(!"Unexpected shader type");
493 return VGPU10_VERTEX_SHADER;
494 }
495 }
496
497
498 /**
499 * Translate a TGSI_OPCODE_x into a VGPU10_OPCODE_x
500 * Note: we only need to translate the opcodes for "simple" instructions,
501 * as seen below. All other opcodes are handled/translated specially.
502 */
503 static VGPU10_OPCODE_TYPE
504 translate_opcode(enum tgsi_opcode opcode)
505 {
506 switch (opcode) {
507 case TGSI_OPCODE_MOV:
508 return VGPU10_OPCODE_MOV;
509 case TGSI_OPCODE_MUL:
510 return VGPU10_OPCODE_MUL;
511 case TGSI_OPCODE_ADD:
512 return VGPU10_OPCODE_ADD;
513 case TGSI_OPCODE_DP3:
514 return VGPU10_OPCODE_DP3;
515 case TGSI_OPCODE_DP4:
516 return VGPU10_OPCODE_DP4;
517 case TGSI_OPCODE_MIN:
518 return VGPU10_OPCODE_MIN;
519 case TGSI_OPCODE_MAX:
520 return VGPU10_OPCODE_MAX;
521 case TGSI_OPCODE_MAD:
522 return VGPU10_OPCODE_MAD;
523 case TGSI_OPCODE_SQRT:
524 return VGPU10_OPCODE_SQRT;
525 case TGSI_OPCODE_FRC:
526 return VGPU10_OPCODE_FRC;
527 case TGSI_OPCODE_FLR:
528 return VGPU10_OPCODE_ROUND_NI;
529 case TGSI_OPCODE_FSEQ:
530 return VGPU10_OPCODE_EQ;
531 case TGSI_OPCODE_FSGE:
532 return VGPU10_OPCODE_GE;
533 case TGSI_OPCODE_FSNE:
534 return VGPU10_OPCODE_NE;
535 case TGSI_OPCODE_DDX:
536 return VGPU10_OPCODE_DERIV_RTX;
537 case TGSI_OPCODE_DDY:
538 return VGPU10_OPCODE_DERIV_RTY;
539 case TGSI_OPCODE_RET:
540 return VGPU10_OPCODE_RET;
541 case TGSI_OPCODE_DIV:
542 return VGPU10_OPCODE_DIV;
543 case TGSI_OPCODE_IDIV:
544 return VGPU10_OPCODE_IDIV;
545 case TGSI_OPCODE_DP2:
546 return VGPU10_OPCODE_DP2;
547 case TGSI_OPCODE_BRK:
548 return VGPU10_OPCODE_BREAK;
549 case TGSI_OPCODE_IF:
550 return VGPU10_OPCODE_IF;
551 case TGSI_OPCODE_ELSE:
552 return VGPU10_OPCODE_ELSE;
553 case TGSI_OPCODE_ENDIF:
554 return VGPU10_OPCODE_ENDIF;
555 case TGSI_OPCODE_CEIL:
556 return VGPU10_OPCODE_ROUND_PI;
557 case TGSI_OPCODE_I2F:
558 return VGPU10_OPCODE_ITOF;
559 case TGSI_OPCODE_NOT:
560 return VGPU10_OPCODE_NOT;
561 case TGSI_OPCODE_TRUNC:
562 return VGPU10_OPCODE_ROUND_Z;
563 case TGSI_OPCODE_SHL:
564 return VGPU10_OPCODE_ISHL;
565 case TGSI_OPCODE_AND:
566 return VGPU10_OPCODE_AND;
567 case TGSI_OPCODE_OR:
568 return VGPU10_OPCODE_OR;
569 case TGSI_OPCODE_XOR:
570 return VGPU10_OPCODE_XOR;
571 case TGSI_OPCODE_CONT:
572 return VGPU10_OPCODE_CONTINUE;
573 case TGSI_OPCODE_EMIT:
574 return VGPU10_OPCODE_EMIT;
575 case TGSI_OPCODE_ENDPRIM:
576 return VGPU10_OPCODE_CUT;
577 case TGSI_OPCODE_BGNLOOP:
578 return VGPU10_OPCODE_LOOP;
579 case TGSI_OPCODE_ENDLOOP:
580 return VGPU10_OPCODE_ENDLOOP;
581 case TGSI_OPCODE_ENDSUB:
582 return VGPU10_OPCODE_RET;
583 case TGSI_OPCODE_NOP:
584 return VGPU10_OPCODE_NOP;
585 case TGSI_OPCODE_END:
586 return VGPU10_OPCODE_RET;
587 case TGSI_OPCODE_F2I:
588 return VGPU10_OPCODE_FTOI;
589 case TGSI_OPCODE_IMAX:
590 return VGPU10_OPCODE_IMAX;
591 case TGSI_OPCODE_IMIN:
592 return VGPU10_OPCODE_IMIN;
593 case TGSI_OPCODE_UDIV:
594 case TGSI_OPCODE_UMOD:
595 case TGSI_OPCODE_MOD:
596 return VGPU10_OPCODE_UDIV;
597 case TGSI_OPCODE_IMUL_HI:
598 return VGPU10_OPCODE_IMUL;
599 case TGSI_OPCODE_INEG:
600 return VGPU10_OPCODE_INEG;
601 case TGSI_OPCODE_ISHR:
602 return VGPU10_OPCODE_ISHR;
603 case TGSI_OPCODE_ISGE:
604 return VGPU10_OPCODE_IGE;
605 case TGSI_OPCODE_ISLT:
606 return VGPU10_OPCODE_ILT;
607 case TGSI_OPCODE_F2U:
608 return VGPU10_OPCODE_FTOU;
609 case TGSI_OPCODE_UADD:
610 return VGPU10_OPCODE_IADD;
611 case TGSI_OPCODE_U2F:
612 return VGPU10_OPCODE_UTOF;
613 case TGSI_OPCODE_UCMP:
614 return VGPU10_OPCODE_MOVC;
615 case TGSI_OPCODE_UMAD:
616 return VGPU10_OPCODE_UMAD;
617 case TGSI_OPCODE_UMAX:
618 return VGPU10_OPCODE_UMAX;
619 case TGSI_OPCODE_UMIN:
620 return VGPU10_OPCODE_UMIN;
621 case TGSI_OPCODE_UMUL:
622 case TGSI_OPCODE_UMUL_HI:
623 return VGPU10_OPCODE_UMUL;
624 case TGSI_OPCODE_USEQ:
625 return VGPU10_OPCODE_IEQ;
626 case TGSI_OPCODE_USGE:
627 return VGPU10_OPCODE_UGE;
628 case TGSI_OPCODE_USHR:
629 return VGPU10_OPCODE_USHR;
630 case TGSI_OPCODE_USLT:
631 return VGPU10_OPCODE_ULT;
632 case TGSI_OPCODE_USNE:
633 return VGPU10_OPCODE_INE;
634 case TGSI_OPCODE_SWITCH:
635 return VGPU10_OPCODE_SWITCH;
636 case TGSI_OPCODE_CASE:
637 return VGPU10_OPCODE_CASE;
638 case TGSI_OPCODE_DEFAULT:
639 return VGPU10_OPCODE_DEFAULT;
640 case TGSI_OPCODE_ENDSWITCH:
641 return VGPU10_OPCODE_ENDSWITCH;
642 case TGSI_OPCODE_FSLT:
643 return VGPU10_OPCODE_LT;
644 case TGSI_OPCODE_ROUND:
645 return VGPU10_OPCODE_ROUND_NE;
646 default:
647 assert(!"Unexpected TGSI opcode in translate_opcode()");
648 return VGPU10_OPCODE_NOP;
649 }
650 }
651
652
653 /**
654 * Translate a TGSI register file type into a VGPU10 operand type.
655 * \param array is the TGSI_FILE_TEMPORARY register an array?
656 */
657 static VGPU10_OPERAND_TYPE
658 translate_register_file(enum tgsi_file_type file, boolean array)
659 {
660 switch (file) {
661 case TGSI_FILE_CONSTANT:
662 return VGPU10_OPERAND_TYPE_CONSTANT_BUFFER;
663 case TGSI_FILE_INPUT:
664 return VGPU10_OPERAND_TYPE_INPUT;
665 case TGSI_FILE_OUTPUT:
666 return VGPU10_OPERAND_TYPE_OUTPUT;
667 case TGSI_FILE_TEMPORARY:
668 return array ? VGPU10_OPERAND_TYPE_INDEXABLE_TEMP
669 : VGPU10_OPERAND_TYPE_TEMP;
670 case TGSI_FILE_IMMEDIATE:
671 /* all immediates are 32-bit values at this time so
672 * VGPU10_OPERAND_TYPE_IMMEDIATE64 is not possible at this time.
673 */
674 return VGPU10_OPERAND_TYPE_IMMEDIATE_CONSTANT_BUFFER;
675 case TGSI_FILE_SAMPLER:
676 return VGPU10_OPERAND_TYPE_SAMPLER;
677 case TGSI_FILE_SYSTEM_VALUE:
678 return VGPU10_OPERAND_TYPE_INPUT;
679
680 /* XXX TODO more cases to finish */
681
682 default:
683 assert(!"Bad tgsi register file!");
684 return VGPU10_OPERAND_TYPE_NULL;
685 }
686 }
687
688
689 /**
690 * Emit a null dst register
691 */
692 static void
693 emit_null_dst_register(struct svga_shader_emitter_v10 *emit)
694 {
695 VGPU10OperandToken0 operand;
696
697 operand.value = 0;
698 operand.operandType = VGPU10_OPERAND_TYPE_NULL;
699 operand.numComponents = VGPU10_OPERAND_0_COMPONENT;
700
701 emit_dword(emit, operand.value);
702 }
703
704
705 /**
706 * If the given register is a temporary, return the array ID.
707 * Else return zero.
708 */
709 static unsigned
710 get_temp_array_id(const struct svga_shader_emitter_v10 *emit,
711 enum tgsi_file_type file, unsigned index)
712 {
713 if (file == TGSI_FILE_TEMPORARY) {
714 return emit->temp_map[index].arrayId;
715 }
716 else {
717 return 0;
718 }
719 }
720
721
722 /**
723 * If the given register is a temporary, convert the index from a TGSI
724 * TEMPORARY index to a VGPU10 temp index.
725 */
726 static unsigned
727 remap_temp_index(const struct svga_shader_emitter_v10 *emit,
728 enum tgsi_file_type file, unsigned index)
729 {
730 if (file == TGSI_FILE_TEMPORARY) {
731 return emit->temp_map[index].index;
732 }
733 else {
734 return index;
735 }
736 }
737
738
739 /**
740 * Setup the operand0 fields related to indexing (1D, 2D, relative, etc).
741 * Note: the operandType field must already be initialized.
742 */
743 static VGPU10OperandToken0
744 setup_operand0_indexing(struct svga_shader_emitter_v10 *emit,
745 VGPU10OperandToken0 operand0,
746 enum tgsi_file_type file,
747 boolean indirect, boolean index2D,
748 unsigned tempArrayID)
749 {
750 unsigned indexDim, index0Rep, index1Rep = VGPU10_OPERAND_INDEX_IMMEDIATE32;
751
752 /*
753 * Compute index dimensions
754 */
755 if (operand0.operandType == VGPU10_OPERAND_TYPE_IMMEDIATE32 ||
756 operand0.operandType == VGPU10_OPERAND_TYPE_INPUT_PRIMITIVEID) {
757 /* there's no swizzle for in-line immediates */
758 indexDim = VGPU10_OPERAND_INDEX_0D;
759 assert(operand0.selectionMode == 0);
760 }
761 else {
762 if (index2D ||
763 tempArrayID > 0 ||
764 operand0.operandType == VGPU10_OPERAND_TYPE_CONSTANT_BUFFER) {
765 indexDim = VGPU10_OPERAND_INDEX_2D;
766 }
767 else {
768 indexDim = VGPU10_OPERAND_INDEX_1D;
769 }
770 }
771
772 /*
773 * Compute index representations (immediate, relative, etc).
774 */
775 if (tempArrayID > 0) {
776 assert(file == TGSI_FILE_TEMPORARY);
777 /* First index is the array ID, second index is the array element */
778 index0Rep = VGPU10_OPERAND_INDEX_IMMEDIATE32;
779 if (indirect) {
780 index1Rep = VGPU10_OPERAND_INDEX_IMMEDIATE32_PLUS_RELATIVE;
781 }
782 else {
783 index1Rep = VGPU10_OPERAND_INDEX_IMMEDIATE32;
784 }
785 }
786 else if (indirect) {
787 if (file == TGSI_FILE_CONSTANT) {
788 /* index[0] indicates which constant buffer while index[1] indicates
789 * the position in the constant buffer.
790 */
791 index0Rep = VGPU10_OPERAND_INDEX_IMMEDIATE32;
792 index1Rep = VGPU10_OPERAND_INDEX_IMMEDIATE32_PLUS_RELATIVE;
793 }
794 else {
795 /* All other register files are 1-dimensional */
796 index0Rep = VGPU10_OPERAND_INDEX_IMMEDIATE32_PLUS_RELATIVE;
797 }
798 }
799 else {
800 index0Rep = VGPU10_OPERAND_INDEX_IMMEDIATE32;
801 index1Rep = VGPU10_OPERAND_INDEX_IMMEDIATE32;
802 }
803
804 operand0.indexDimension = indexDim;
805 operand0.index0Representation = index0Rep;
806 operand0.index1Representation = index1Rep;
807
808 return operand0;
809 }
810
811
812 /**
813 * Emit the operand for expressing an address register for indirect indexing.
814 * Note that the address register is really just a temp register.
815 * \param addr_reg_index which address register to use
816 */
817 static void
818 emit_indirect_register(struct svga_shader_emitter_v10 *emit,
819 unsigned addr_reg_index)
820 {
821 unsigned tmp_reg_index;
822 VGPU10OperandToken0 operand0;
823
824 assert(addr_reg_index < MAX_VGPU10_ADDR_REGS);
825
826 tmp_reg_index = emit->address_reg_index[addr_reg_index];
827
828 /* operand0 is a simple temporary register, selecting one component */
829 operand0.value = 0;
830 operand0.operandType = VGPU10_OPERAND_TYPE_TEMP;
831 operand0.numComponents = VGPU10_OPERAND_4_COMPONENT;
832 operand0.indexDimension = VGPU10_OPERAND_INDEX_1D;
833 operand0.index0Representation = VGPU10_OPERAND_INDEX_IMMEDIATE32;
834 operand0.selectionMode = VGPU10_OPERAND_4_COMPONENT_SELECT_1_MODE;
835 operand0.swizzleX = 0;
836 operand0.swizzleY = 1;
837 operand0.swizzleZ = 2;
838 operand0.swizzleW = 3;
839
840 emit_dword(emit, operand0.value);
841 emit_dword(emit, remap_temp_index(emit, TGSI_FILE_TEMPORARY, tmp_reg_index));
842 }
843
844
845 /**
846 * Translate the dst register of a TGSI instruction and emit VGPU10 tokens.
847 * \param emit the emitter context
848 * \param reg the TGSI dst register to translate
849 */
850 static void
851 emit_dst_register(struct svga_shader_emitter_v10 *emit,
852 const struct tgsi_full_dst_register *reg)
853 {
854 enum tgsi_file_type file = reg->Register.File;
855 unsigned index = reg->Register.Index;
856 const enum tgsi_semantic sem_name = emit->info.output_semantic_name[index];
857 const unsigned sem_index = emit->info.output_semantic_index[index];
858 unsigned writemask = reg->Register.WriteMask;
859 const boolean indirect = reg->Register.Indirect;
860 const unsigned tempArrayId = get_temp_array_id(emit, file, index);
861 const boolean index2d = reg->Register.Dimension;
862 VGPU10OperandToken0 operand0;
863
864 if (file == TGSI_FILE_OUTPUT) {
865 if (emit->unit == PIPE_SHADER_VERTEX ||
866 emit->unit == PIPE_SHADER_GEOMETRY) {
867 if (index == emit->vposition.out_index &&
868 emit->vposition.tmp_index != INVALID_INDEX) {
869 /* replace OUTPUT[POS] with TEMP[POS]. We need to store the
870 * vertex position result in a temporary so that we can modify
871 * it in the post_helper() code.
872 */
873 file = TGSI_FILE_TEMPORARY;
874 index = emit->vposition.tmp_index;
875 }
876 else if (sem_name == TGSI_SEMANTIC_CLIPDIST &&
877 emit->clip_dist_tmp_index != INVALID_INDEX) {
878 /* replace OUTPUT[CLIPDIST] with TEMP[CLIPDIST].
879 * We store the clip distance in a temporary first, then
880 * we'll copy it to the shadow copy and to CLIPDIST with the
881 * enabled planes mask in emit_clip_distance_instructions().
882 */
883 file = TGSI_FILE_TEMPORARY;
884 index = emit->clip_dist_tmp_index + sem_index;
885 }
886 else if (sem_name == TGSI_SEMANTIC_CLIPVERTEX &&
887 emit->clip_vertex_tmp_index != INVALID_INDEX) {
888 /* replace the CLIPVERTEX output register with a temporary */
889 assert(emit->clip_mode == CLIP_VERTEX);
890 assert(sem_index == 0);
891 file = TGSI_FILE_TEMPORARY;
892 index = emit->clip_vertex_tmp_index;
893 }
894 }
895 else if (emit->unit == PIPE_SHADER_FRAGMENT) {
896 if (sem_name == TGSI_SEMANTIC_POSITION) {
897 /* Fragment depth output register */
898 operand0.value = 0;
899 operand0.operandType = VGPU10_OPERAND_TYPE_OUTPUT_DEPTH;
900 operand0.indexDimension = VGPU10_OPERAND_INDEX_0D;
901 operand0.numComponents = VGPU10_OPERAND_1_COMPONENT;
902 emit_dword(emit, operand0.value);
903 return;
904 }
905 else if (index == emit->fs.color_out_index[0] &&
906 emit->fs.color_tmp_index != INVALID_INDEX) {
907 /* replace OUTPUT[COLOR] with TEMP[COLOR]. We need to store the
908 * fragment color result in a temporary so that we can read it
909 * it in the post_helper() code.
910 */
911 file = TGSI_FILE_TEMPORARY;
912 index = emit->fs.color_tmp_index;
913 }
914 else {
915 /* Typically, for fragment shaders, the output register index
916 * matches the color semantic index. But not when we write to
917 * the fragment depth register. In that case, OUT[0] will be
918 * fragdepth and OUT[1] will be the 0th color output. We need
919 * to use the semantic index for color outputs.
920 */
921 assert(sem_name == TGSI_SEMANTIC_COLOR);
922 index = emit->info.output_semantic_index[index];
923
924 emit->num_output_writes++;
925 }
926 }
927 }
928
929 /* init operand tokens to all zero */
930 operand0.value = 0;
931
932 operand0.numComponents = VGPU10_OPERAND_4_COMPONENT;
933
934 /* the operand has a writemask */
935 operand0.selectionMode = VGPU10_OPERAND_4_COMPONENT_MASK_MODE;
936
937 /* Which of the four dest components to write to. Note that we can use a
938 * simple assignment here since TGSI writemasks match VGPU10 writemasks.
939 */
940 STATIC_ASSERT(TGSI_WRITEMASK_X == VGPU10_OPERAND_4_COMPONENT_MASK_X);
941 operand0.mask = writemask;
942
943 /* translate TGSI register file type to VGPU10 operand type */
944 operand0.operandType = translate_register_file(file, tempArrayId > 0);
945
946 check_register_index(emit, operand0.operandType, index);
947
948 operand0 = setup_operand0_indexing(emit, operand0, file, indirect,
949 index2d, tempArrayId);
950
951 /* Emit tokens */
952 emit_dword(emit, operand0.value);
953 if (tempArrayId > 0) {
954 emit_dword(emit, tempArrayId);
955 }
956
957 emit_dword(emit, remap_temp_index(emit, file, index));
958
959 if (indirect) {
960 emit_indirect_register(emit, reg->Indirect.Index);
961 }
962 }
963
964
965 /**
966 * Translate a src register of a TGSI instruction and emit VGPU10 tokens.
967 */
968 static void
969 emit_src_register(struct svga_shader_emitter_v10 *emit,
970 const struct tgsi_full_src_register *reg)
971 {
972 enum tgsi_file_type file = reg->Register.File;
973 unsigned index = reg->Register.Index;
974 const boolean indirect = reg->Register.Indirect;
975 const unsigned tempArrayId = get_temp_array_id(emit, file, index);
976 const boolean index2d = reg->Register.Dimension;
977 const unsigned swizzleX = reg->Register.SwizzleX;
978 const unsigned swizzleY = reg->Register.SwizzleY;
979 const unsigned swizzleZ = reg->Register.SwizzleZ;
980 const unsigned swizzleW = reg->Register.SwizzleW;
981 const boolean absolute = reg->Register.Absolute;
982 const boolean negate = reg->Register.Negate;
983 bool is_prim_id = FALSE;
984
985 VGPU10OperandToken0 operand0;
986 VGPU10OperandToken1 operand1;
987
988 if (emit->unit == PIPE_SHADER_FRAGMENT &&
989 file == TGSI_FILE_INPUT) {
990 if (index == emit->fs.face_input_index) {
991 /* Replace INPUT[FACE] with TEMP[FACE] */
992 file = TGSI_FILE_TEMPORARY;
993 index = emit->fs.face_tmp_index;
994 }
995 else if (index == emit->fs.fragcoord_input_index) {
996 /* Replace INPUT[POSITION] with TEMP[POSITION] */
997 file = TGSI_FILE_TEMPORARY;
998 index = emit->fs.fragcoord_tmp_index;
999 }
1000 else {
1001 /* We remap fragment shader inputs to that FS input indexes
1002 * match up with VS/GS output indexes.
1003 */
1004 index = emit->linkage.input_map[index];
1005 }
1006 }
1007 else if (emit->unit == PIPE_SHADER_GEOMETRY &&
1008 file == TGSI_FILE_INPUT) {
1009 is_prim_id = (index == emit->gs.prim_id_index);
1010 index = emit->linkage.input_map[index];
1011 }
1012 else if (emit->unit == PIPE_SHADER_VERTEX) {
1013 if (file == TGSI_FILE_INPUT) {
1014 /* if input is adjusted... */
1015 if ((emit->key.vs.adjust_attrib_w_1 |
1016 emit->key.vs.adjust_attrib_itof |
1017 emit->key.vs.adjust_attrib_utof |
1018 emit->key.vs.attrib_is_bgra |
1019 emit->key.vs.attrib_puint_to_snorm |
1020 emit->key.vs.attrib_puint_to_uscaled |
1021 emit->key.vs.attrib_puint_to_sscaled) & (1 << index)) {
1022 file = TGSI_FILE_TEMPORARY;
1023 index = emit->vs.adjusted_input[index];
1024 }
1025 }
1026 else if (file == TGSI_FILE_SYSTEM_VALUE) {
1027 assert(index < ARRAY_SIZE(emit->system_value_indexes));
1028 index = emit->system_value_indexes[index];
1029 }
1030 }
1031
1032 operand0.value = operand1.value = 0;
1033
1034 if (is_prim_id) {
1035 /* NOTE: we should be using VGPU10_OPERAND_1_COMPONENT here, but
1036 * our virtual GPU accepts this as-is.
1037 */
1038 operand0.numComponents = VGPU10_OPERAND_0_COMPONENT;
1039 operand0.operandType = VGPU10_OPERAND_TYPE_INPUT_PRIMITIVEID;
1040 }
1041 else {
1042 operand0.numComponents = VGPU10_OPERAND_4_COMPONENT;
1043 operand0.operandType = translate_register_file(file, tempArrayId > 0);
1044 }
1045
1046 operand0 = setup_operand0_indexing(emit, operand0, file, indirect,
1047 index2d, tempArrayId);
1048
1049 if (operand0.operandType != VGPU10_OPERAND_TYPE_IMMEDIATE32 &&
1050 operand0.operandType != VGPU10_OPERAND_TYPE_INPUT_PRIMITIVEID) {
1051 /* there's no swizzle for in-line immediates */
1052 if (swizzleX == swizzleY &&
1053 swizzleX == swizzleZ &&
1054 swizzleX == swizzleW) {
1055 operand0.selectionMode = VGPU10_OPERAND_4_COMPONENT_SELECT_1_MODE;
1056 }
1057 else {
1058 operand0.selectionMode = VGPU10_OPERAND_4_COMPONENT_SWIZZLE_MODE;
1059 }
1060
1061 operand0.swizzleX = swizzleX;
1062 operand0.swizzleY = swizzleY;
1063 operand0.swizzleZ = swizzleZ;
1064 operand0.swizzleW = swizzleW;
1065
1066 if (absolute || negate) {
1067 operand0.extended = 1;
1068 operand1.extendedOperandType = VGPU10_EXTENDED_OPERAND_MODIFIER;
1069 if (absolute && !negate)
1070 operand1.operandModifier = VGPU10_OPERAND_MODIFIER_ABS;
1071 if (!absolute && negate)
1072 operand1.operandModifier = VGPU10_OPERAND_MODIFIER_NEG;
1073 if (absolute && negate)
1074 operand1.operandModifier = VGPU10_OPERAND_MODIFIER_ABSNEG;
1075 }
1076 }
1077
1078 /* Emit the operand tokens */
1079 emit_dword(emit, operand0.value);
1080 if (operand0.extended)
1081 emit_dword(emit, operand1.value);
1082
1083 if (operand0.operandType == VGPU10_OPERAND_TYPE_IMMEDIATE32) {
1084 /* Emit the four float/int in-line immediate values */
1085 unsigned *c;
1086 assert(index < ARRAY_SIZE(emit->immediates));
1087 assert(file == TGSI_FILE_IMMEDIATE);
1088 assert(swizzleX < 4);
1089 assert(swizzleY < 4);
1090 assert(swizzleZ < 4);
1091 assert(swizzleW < 4);
1092 c = (unsigned *) emit->immediates[index];
1093 emit_dword(emit, c[swizzleX]);
1094 emit_dword(emit, c[swizzleY]);
1095 emit_dword(emit, c[swizzleZ]);
1096 emit_dword(emit, c[swizzleW]);
1097 }
1098 else if (operand0.indexDimension >= VGPU10_OPERAND_INDEX_1D) {
1099 /* Emit the register index(es) */
1100 if (index2d ||
1101 operand0.operandType == VGPU10_OPERAND_TYPE_CONSTANT_BUFFER) {
1102 emit_dword(emit, reg->Dimension.Index);
1103 }
1104
1105 if (tempArrayId > 0) {
1106 emit_dword(emit, tempArrayId);
1107 }
1108
1109 emit_dword(emit, remap_temp_index(emit, file, index));
1110
1111 if (indirect) {
1112 emit_indirect_register(emit, reg->Indirect.Index);
1113 }
1114 }
1115 }
1116
1117
1118 /**
1119 * Emit a resource operand (for use with a SAMPLE instruction).
1120 */
1121 static void
1122 emit_resource_register(struct svga_shader_emitter_v10 *emit,
1123 unsigned resource_number)
1124 {
1125 VGPU10OperandToken0 operand0;
1126
1127 check_register_index(emit, VGPU10_OPERAND_TYPE_RESOURCE, resource_number);
1128
1129 /* init */
1130 operand0.value = 0;
1131
1132 operand0.operandType = VGPU10_OPERAND_TYPE_RESOURCE;
1133 operand0.indexDimension = VGPU10_OPERAND_INDEX_1D;
1134 operand0.numComponents = VGPU10_OPERAND_4_COMPONENT;
1135 operand0.selectionMode = VGPU10_OPERAND_4_COMPONENT_SWIZZLE_MODE;
1136 operand0.swizzleX = VGPU10_COMPONENT_X;
1137 operand0.swizzleY = VGPU10_COMPONENT_Y;
1138 operand0.swizzleZ = VGPU10_COMPONENT_Z;
1139 operand0.swizzleW = VGPU10_COMPONENT_W;
1140
1141 emit_dword(emit, operand0.value);
1142 emit_dword(emit, resource_number);
1143 }
1144
1145
1146 /**
1147 * Emit a sampler operand (for use with a SAMPLE instruction).
1148 */
1149 static void
1150 emit_sampler_register(struct svga_shader_emitter_v10 *emit,
1151 unsigned sampler_number)
1152 {
1153 VGPU10OperandToken0 operand0;
1154
1155 check_register_index(emit, VGPU10_OPERAND_TYPE_SAMPLER, sampler_number);
1156
1157 /* init */
1158 operand0.value = 0;
1159
1160 operand0.operandType = VGPU10_OPERAND_TYPE_SAMPLER;
1161 operand0.indexDimension = VGPU10_OPERAND_INDEX_1D;
1162
1163 emit_dword(emit, operand0.value);
1164 emit_dword(emit, sampler_number);
1165 }
1166
1167
1168 /**
1169 * Emit an operand which reads the IS_FRONT_FACING register.
1170 */
1171 static void
1172 emit_face_register(struct svga_shader_emitter_v10 *emit)
1173 {
1174 VGPU10OperandToken0 operand0;
1175 unsigned index = emit->linkage.input_map[emit->fs.face_input_index];
1176
1177 /* init */
1178 operand0.value = 0;
1179
1180 operand0.operandType = VGPU10_OPERAND_TYPE_INPUT;
1181 operand0.indexDimension = VGPU10_OPERAND_INDEX_1D;
1182 operand0.selectionMode = VGPU10_OPERAND_4_COMPONENT_SELECT_1_MODE;
1183 operand0.numComponents = VGPU10_OPERAND_4_COMPONENT;
1184
1185 operand0.swizzleX = VGPU10_COMPONENT_X;
1186 operand0.swizzleY = VGPU10_COMPONENT_X;
1187 operand0.swizzleZ = VGPU10_COMPONENT_X;
1188 operand0.swizzleW = VGPU10_COMPONENT_X;
1189
1190 emit_dword(emit, operand0.value);
1191 emit_dword(emit, index);
1192 }
1193
1194
1195 /**
1196 * Emit the token for a VGPU10 opcode.
1197 * \param saturate clamp result to [0,1]?
1198 */
1199 static void
1200 emit_opcode(struct svga_shader_emitter_v10 *emit,
1201 VGPU10_OPCODE_TYPE vgpu10_opcode, boolean saturate)
1202 {
1203 VGPU10OpcodeToken0 token0;
1204
1205 token0.value = 0; /* init all fields to zero */
1206 token0.opcodeType = vgpu10_opcode;
1207 token0.instructionLength = 0; /* Filled in by end_emit_instruction() */
1208 token0.saturate = saturate;
1209
1210 emit_dword(emit, token0.value);
1211 }
1212
1213
1214 /**
1215 * Emit the token for a VGPU10 resinfo instruction.
1216 * \param modifier return type modifier, _uint or _rcpFloat.
1217 * TODO: We may want to remove this parameter if it will
1218 * only ever be used as _uint.
1219 */
1220 static void
1221 emit_opcode_resinfo(struct svga_shader_emitter_v10 *emit,
1222 VGPU10_RESINFO_RETURN_TYPE modifier)
1223 {
1224 VGPU10OpcodeToken0 token0;
1225
1226 token0.value = 0; /* init all fields to zero */
1227 token0.opcodeType = VGPU10_OPCODE_RESINFO;
1228 token0.instructionLength = 0; /* Filled in by end_emit_instruction() */
1229 token0.resinfoReturnType = modifier;
1230
1231 emit_dword(emit, token0.value);
1232 }
1233
1234
1235 /**
1236 * Emit opcode tokens for a texture sample instruction. Texture instructions
1237 * can be rather complicated (texel offsets, etc) so we have this specialized
1238 * function.
1239 */
1240 static void
1241 emit_sample_opcode(struct svga_shader_emitter_v10 *emit,
1242 unsigned vgpu10_opcode, boolean saturate,
1243 const int offsets[3])
1244 {
1245 VGPU10OpcodeToken0 token0;
1246 VGPU10OpcodeToken1 token1;
1247
1248 token0.value = 0; /* init all fields to zero */
1249 token0.opcodeType = vgpu10_opcode;
1250 token0.instructionLength = 0; /* Filled in by end_emit_instruction() */
1251 token0.saturate = saturate;
1252
1253 if (offsets[0] || offsets[1] || offsets[2]) {
1254 assert(offsets[0] >= VGPU10_MIN_TEXEL_FETCH_OFFSET);
1255 assert(offsets[1] >= VGPU10_MIN_TEXEL_FETCH_OFFSET);
1256 assert(offsets[2] >= VGPU10_MIN_TEXEL_FETCH_OFFSET);
1257 assert(offsets[0] <= VGPU10_MAX_TEXEL_FETCH_OFFSET);
1258 assert(offsets[1] <= VGPU10_MAX_TEXEL_FETCH_OFFSET);
1259 assert(offsets[2] <= VGPU10_MAX_TEXEL_FETCH_OFFSET);
1260
1261 token0.extended = 1;
1262 token1.value = 0;
1263 token1.opcodeType = VGPU10_EXTENDED_OPCODE_SAMPLE_CONTROLS;
1264 token1.offsetU = offsets[0];
1265 token1.offsetV = offsets[1];
1266 token1.offsetW = offsets[2];
1267 }
1268
1269 emit_dword(emit, token0.value);
1270 if (token0.extended) {
1271 emit_dword(emit, token1.value);
1272 }
1273 }
1274
1275
1276 /**
1277 * Emit a DISCARD opcode token.
1278 * If nonzero is set, we'll discard the fragment if the X component is not 0.
1279 * Otherwise, we'll discard the fragment if the X component is 0.
1280 */
1281 static void
1282 emit_discard_opcode(struct svga_shader_emitter_v10 *emit, boolean nonzero)
1283 {
1284 VGPU10OpcodeToken0 opcode0;
1285
1286 opcode0.value = 0;
1287 opcode0.opcodeType = VGPU10_OPCODE_DISCARD;
1288 if (nonzero)
1289 opcode0.testBoolean = VGPU10_INSTRUCTION_TEST_NONZERO;
1290
1291 emit_dword(emit, opcode0.value);
1292 }
1293
1294
1295 /**
1296 * We need to call this before we begin emitting a VGPU10 instruction.
1297 */
1298 static void
1299 begin_emit_instruction(struct svga_shader_emitter_v10 *emit)
1300 {
1301 assert(emit->inst_start_token == 0);
1302 /* Save location of the instruction's VGPU10OpcodeToken0 token.
1303 * Note, we can't save a pointer because it would become invalid if
1304 * we have to realloc the output buffer.
1305 */
1306 emit->inst_start_token = emit_get_num_tokens(emit);
1307 }
1308
1309
1310 /**
1311 * We need to call this after we emit the last token of a VGPU10 instruction.
1312 * This function patches in the opcode token's instructionLength field.
1313 */
1314 static void
1315 end_emit_instruction(struct svga_shader_emitter_v10 *emit)
1316 {
1317 VGPU10OpcodeToken0 *tokens = (VGPU10OpcodeToken0 *) emit->buf;
1318 unsigned inst_length;
1319
1320 assert(emit->inst_start_token > 0);
1321
1322 if (emit->discard_instruction) {
1323 /* Back up the emit->ptr to where this instruction started so
1324 * that we discard the current instruction.
1325 */
1326 emit->ptr = (char *) (tokens + emit->inst_start_token);
1327 }
1328 else {
1329 /* Compute instruction length and patch that into the start of
1330 * the instruction.
1331 */
1332 inst_length = emit_get_num_tokens(emit) - emit->inst_start_token;
1333
1334 assert(inst_length > 0);
1335
1336 tokens[emit->inst_start_token].instructionLength = inst_length;
1337 }
1338
1339 emit->inst_start_token = 0; /* reset to zero for error checking */
1340 emit->discard_instruction = FALSE;
1341 }
1342
1343
1344 /**
1345 * Return index for a free temporary register.
1346 */
1347 static unsigned
1348 get_temp_index(struct svga_shader_emitter_v10 *emit)
1349 {
1350 assert(emit->internal_temp_count < MAX_INTERNAL_TEMPS);
1351 return emit->num_shader_temps + emit->internal_temp_count++;
1352 }
1353
1354
1355 /**
1356 * Release the temporaries which were generated by get_temp_index().
1357 */
1358 static void
1359 free_temp_indexes(struct svga_shader_emitter_v10 *emit)
1360 {
1361 emit->internal_temp_count = 0;
1362 }
1363
1364
1365 /**
1366 * Create a tgsi_full_src_register.
1367 */
1368 static struct tgsi_full_src_register
1369 make_src_reg(enum tgsi_file_type file, unsigned index)
1370 {
1371 struct tgsi_full_src_register reg;
1372
1373 memset(&reg, 0, sizeof(reg));
1374 reg.Register.File = file;
1375 reg.Register.Index = index;
1376 reg.Register.SwizzleX = TGSI_SWIZZLE_X;
1377 reg.Register.SwizzleY = TGSI_SWIZZLE_Y;
1378 reg.Register.SwizzleZ = TGSI_SWIZZLE_Z;
1379 reg.Register.SwizzleW = TGSI_SWIZZLE_W;
1380 return reg;
1381 }
1382
1383
1384 /**
1385 * Create a tgsi_full_src_register for a temporary.
1386 */
1387 static struct tgsi_full_src_register
1388 make_src_temp_reg(unsigned index)
1389 {
1390 return make_src_reg(TGSI_FILE_TEMPORARY, index);
1391 }
1392
1393
1394 /**
1395 * Create a tgsi_full_src_register for a constant.
1396 */
1397 static struct tgsi_full_src_register
1398 make_src_const_reg(unsigned index)
1399 {
1400 return make_src_reg(TGSI_FILE_CONSTANT, index);
1401 }
1402
1403
1404 /**
1405 * Create a tgsi_full_src_register for an immediate constant.
1406 */
1407 static struct tgsi_full_src_register
1408 make_src_immediate_reg(unsigned index)
1409 {
1410 return make_src_reg(TGSI_FILE_IMMEDIATE, index);
1411 }
1412
1413
1414 /**
1415 * Create a tgsi_full_dst_register.
1416 */
1417 static struct tgsi_full_dst_register
1418 make_dst_reg(enum tgsi_file_type file, unsigned index)
1419 {
1420 struct tgsi_full_dst_register reg;
1421
1422 memset(&reg, 0, sizeof(reg));
1423 reg.Register.File = file;
1424 reg.Register.Index = index;
1425 reg.Register.WriteMask = TGSI_WRITEMASK_XYZW;
1426 return reg;
1427 }
1428
1429
1430 /**
1431 * Create a tgsi_full_dst_register for a temporary.
1432 */
1433 static struct tgsi_full_dst_register
1434 make_dst_temp_reg(unsigned index)
1435 {
1436 return make_dst_reg(TGSI_FILE_TEMPORARY, index);
1437 }
1438
1439
1440 /**
1441 * Create a tgsi_full_dst_register for an output.
1442 */
1443 static struct tgsi_full_dst_register
1444 make_dst_output_reg(unsigned index)
1445 {
1446 return make_dst_reg(TGSI_FILE_OUTPUT, index);
1447 }
1448
1449
1450 /**
1451 * Create negated tgsi_full_src_register.
1452 */
1453 static struct tgsi_full_src_register
1454 negate_src(const struct tgsi_full_src_register *reg)
1455 {
1456 struct tgsi_full_src_register neg = *reg;
1457 neg.Register.Negate = !reg->Register.Negate;
1458 return neg;
1459 }
1460
1461 /**
1462 * Create absolute value of a tgsi_full_src_register.
1463 */
1464 static struct tgsi_full_src_register
1465 absolute_src(const struct tgsi_full_src_register *reg)
1466 {
1467 struct tgsi_full_src_register absolute = *reg;
1468 absolute.Register.Absolute = 1;
1469 return absolute;
1470 }
1471
1472
1473 /** Return the named swizzle term from the src register */
1474 static inline unsigned
1475 get_swizzle(const struct tgsi_full_src_register *reg, enum tgsi_swizzle term)
1476 {
1477 switch (term) {
1478 case TGSI_SWIZZLE_X:
1479 return reg->Register.SwizzleX;
1480 case TGSI_SWIZZLE_Y:
1481 return reg->Register.SwizzleY;
1482 case TGSI_SWIZZLE_Z:
1483 return reg->Register.SwizzleZ;
1484 case TGSI_SWIZZLE_W:
1485 return reg->Register.SwizzleW;
1486 default:
1487 assert(!"Bad swizzle");
1488 return TGSI_SWIZZLE_X;
1489 }
1490 }
1491
1492
1493 /**
1494 * Create swizzled tgsi_full_src_register.
1495 */
1496 static struct tgsi_full_src_register
1497 swizzle_src(const struct tgsi_full_src_register *reg,
1498 enum tgsi_swizzle swizzleX, enum tgsi_swizzle swizzleY,
1499 enum tgsi_swizzle swizzleZ, enum tgsi_swizzle swizzleW)
1500 {
1501 struct tgsi_full_src_register swizzled = *reg;
1502 /* Note: we swizzle the current swizzle */
1503 swizzled.Register.SwizzleX = get_swizzle(reg, swizzleX);
1504 swizzled.Register.SwizzleY = get_swizzle(reg, swizzleY);
1505 swizzled.Register.SwizzleZ = get_swizzle(reg, swizzleZ);
1506 swizzled.Register.SwizzleW = get_swizzle(reg, swizzleW);
1507 return swizzled;
1508 }
1509
1510
1511 /**
1512 * Create swizzled tgsi_full_src_register where all the swizzle
1513 * terms are the same.
1514 */
1515 static struct tgsi_full_src_register
1516 scalar_src(const struct tgsi_full_src_register *reg, enum tgsi_swizzle swizzle)
1517 {
1518 struct tgsi_full_src_register swizzled = *reg;
1519 /* Note: we swizzle the current swizzle */
1520 swizzled.Register.SwizzleX =
1521 swizzled.Register.SwizzleY =
1522 swizzled.Register.SwizzleZ =
1523 swizzled.Register.SwizzleW = get_swizzle(reg, swizzle);
1524 return swizzled;
1525 }
1526
1527
1528 /**
1529 * Create new tgsi_full_dst_register with writemask.
1530 * \param mask bitmask of TGSI_WRITEMASK_[XYZW]
1531 */
1532 static struct tgsi_full_dst_register
1533 writemask_dst(const struct tgsi_full_dst_register *reg, unsigned mask)
1534 {
1535 struct tgsi_full_dst_register masked = *reg;
1536 masked.Register.WriteMask = mask;
1537 return masked;
1538 }
1539
1540
1541 /**
1542 * Check if the register's swizzle is XXXX, YYYY, ZZZZ, or WWWW.
1543 */
1544 static boolean
1545 same_swizzle_terms(const struct tgsi_full_src_register *reg)
1546 {
1547 return (reg->Register.SwizzleX == reg->Register.SwizzleY &&
1548 reg->Register.SwizzleY == reg->Register.SwizzleZ &&
1549 reg->Register.SwizzleZ == reg->Register.SwizzleW);
1550 }
1551
1552
1553 /**
1554 * Search the vector for the value 'x' and return its position.
1555 */
1556 static int
1557 find_imm_in_vec4(const union tgsi_immediate_data vec[4],
1558 union tgsi_immediate_data x)
1559 {
1560 unsigned i;
1561 for (i = 0; i < 4; i++) {
1562 if (vec[i].Int == x.Int)
1563 return i;
1564 }
1565 return -1;
1566 }
1567
1568
1569 /**
1570 * Helper used by make_immediate_reg(), make_immediate_reg_4().
1571 */
1572 static int
1573 find_immediate(struct svga_shader_emitter_v10 *emit,
1574 union tgsi_immediate_data x, unsigned startIndex)
1575 {
1576 const unsigned endIndex = emit->num_immediates;
1577 unsigned i;
1578
1579 assert(emit->immediates_emitted);
1580
1581 /* Search immediates for x, y, z, w */
1582 for (i = startIndex; i < endIndex; i++) {
1583 if (x.Int == emit->immediates[i][0].Int ||
1584 x.Int == emit->immediates[i][1].Int ||
1585 x.Int == emit->immediates[i][2].Int ||
1586 x.Int == emit->immediates[i][3].Int) {
1587 return i;
1588 }
1589 }
1590 /* Should never try to use an immediate value that wasn't pre-declared */
1591 assert(!"find_immediate() failed!");
1592 return -1;
1593 }
1594
1595
1596 /**
1597 * Return a tgsi_full_src_register for an immediate/literal
1598 * union tgsi_immediate_data[4] value.
1599 * Note: the values must have been previously declared/allocated in
1600 * emit_pre_helpers(). And, all of x,y,z,w must be located in the same
1601 * vec4 immediate.
1602 */
1603 static struct tgsi_full_src_register
1604 make_immediate_reg_4(struct svga_shader_emitter_v10 *emit,
1605 const union tgsi_immediate_data imm[4])
1606 {
1607 struct tgsi_full_src_register reg;
1608 unsigned i;
1609
1610 for (i = 0; i < emit->num_common_immediates; i++) {
1611 /* search for first component value */
1612 int immpos = find_immediate(emit, imm[0], i);
1613 int x, y, z, w;
1614
1615 assert(immpos >= 0);
1616
1617 /* find remaining components within the immediate vector */
1618 x = find_imm_in_vec4(emit->immediates[immpos], imm[0]);
1619 y = find_imm_in_vec4(emit->immediates[immpos], imm[1]);
1620 z = find_imm_in_vec4(emit->immediates[immpos], imm[2]);
1621 w = find_imm_in_vec4(emit->immediates[immpos], imm[3]);
1622
1623 if (x >=0 && y >= 0 && z >= 0 && w >= 0) {
1624 /* found them all */
1625 memset(&reg, 0, sizeof(reg));
1626 reg.Register.File = TGSI_FILE_IMMEDIATE;
1627 reg.Register.Index = immpos;
1628 reg.Register.SwizzleX = x;
1629 reg.Register.SwizzleY = y;
1630 reg.Register.SwizzleZ = z;
1631 reg.Register.SwizzleW = w;
1632 return reg;
1633 }
1634 /* else, keep searching */
1635 }
1636
1637 assert(!"Failed to find immediate register!");
1638
1639 /* Just return IMM[0].xxxx */
1640 memset(&reg, 0, sizeof(reg));
1641 reg.Register.File = TGSI_FILE_IMMEDIATE;
1642 return reg;
1643 }
1644
1645
1646 /**
1647 * Return a tgsi_full_src_register for an immediate/literal
1648 * union tgsi_immediate_data value of the form {value, value, value, value}.
1649 * \sa make_immediate_reg_4() regarding allowed values.
1650 */
1651 static struct tgsi_full_src_register
1652 make_immediate_reg(struct svga_shader_emitter_v10 *emit,
1653 union tgsi_immediate_data value)
1654 {
1655 struct tgsi_full_src_register reg;
1656 int immpos = find_immediate(emit, value, 0);
1657
1658 assert(immpos >= 0);
1659
1660 memset(&reg, 0, sizeof(reg));
1661 reg.Register.File = TGSI_FILE_IMMEDIATE;
1662 reg.Register.Index = immpos;
1663 reg.Register.SwizzleX =
1664 reg.Register.SwizzleY =
1665 reg.Register.SwizzleZ =
1666 reg.Register.SwizzleW = find_imm_in_vec4(emit->immediates[immpos], value);
1667
1668 return reg;
1669 }
1670
1671
1672 /**
1673 * Return a tgsi_full_src_register for an immediate/literal float[4] value.
1674 * \sa make_immediate_reg_4() regarding allowed values.
1675 */
1676 static struct tgsi_full_src_register
1677 make_immediate_reg_float4(struct svga_shader_emitter_v10 *emit,
1678 float x, float y, float z, float w)
1679 {
1680 union tgsi_immediate_data imm[4];
1681 imm[0].Float = x;
1682 imm[1].Float = y;
1683 imm[2].Float = z;
1684 imm[3].Float = w;
1685 return make_immediate_reg_4(emit, imm);
1686 }
1687
1688
1689 /**
1690 * Return a tgsi_full_src_register for an immediate/literal float value
1691 * of the form {value, value, value, value}.
1692 * \sa make_immediate_reg_4() regarding allowed values.
1693 */
1694 static struct tgsi_full_src_register
1695 make_immediate_reg_float(struct svga_shader_emitter_v10 *emit, float value)
1696 {
1697 union tgsi_immediate_data imm;
1698 imm.Float = value;
1699 return make_immediate_reg(emit, imm);
1700 }
1701
1702
1703 /**
1704 * Return a tgsi_full_src_register for an immediate/literal int[4] vector.
1705 */
1706 static struct tgsi_full_src_register
1707 make_immediate_reg_int4(struct svga_shader_emitter_v10 *emit,
1708 int x, int y, int z, int w)
1709 {
1710 union tgsi_immediate_data imm[4];
1711 imm[0].Int = x;
1712 imm[1].Int = y;
1713 imm[2].Int = z;
1714 imm[3].Int = w;
1715 return make_immediate_reg_4(emit, imm);
1716 }
1717
1718
1719 /**
1720 * Return a tgsi_full_src_register for an immediate/literal int value
1721 * of the form {value, value, value, value}.
1722 * \sa make_immediate_reg_4() regarding allowed values.
1723 */
1724 static struct tgsi_full_src_register
1725 make_immediate_reg_int(struct svga_shader_emitter_v10 *emit, int value)
1726 {
1727 union tgsi_immediate_data imm;
1728 imm.Int = value;
1729 return make_immediate_reg(emit, imm);
1730 }
1731
1732
1733 /**
1734 * Allocate space for a union tgsi_immediate_data[4] immediate.
1735 * \return the index/position of the immediate.
1736 */
1737 static unsigned
1738 alloc_immediate_4(struct svga_shader_emitter_v10 *emit,
1739 const union tgsi_immediate_data imm[4])
1740 {
1741 unsigned n = emit->num_immediates++;
1742 assert(!emit->immediates_emitted);
1743 assert(n < ARRAY_SIZE(emit->immediates));
1744 emit->immediates[n][0] = imm[0];
1745 emit->immediates[n][1] = imm[1];
1746 emit->immediates[n][2] = imm[2];
1747 emit->immediates[n][3] = imm[3];
1748 return n;
1749 }
1750
1751
1752 /**
1753 * Allocate space for a float[4] immediate.
1754 * \return the index/position of the immediate.
1755 */
1756 static unsigned
1757 alloc_immediate_float4(struct svga_shader_emitter_v10 *emit,
1758 float x, float y, float z, float w)
1759 {
1760 union tgsi_immediate_data imm[4];
1761 imm[0].Float = x;
1762 imm[1].Float = y;
1763 imm[2].Float = z;
1764 imm[3].Float = w;
1765 return alloc_immediate_4(emit, imm);
1766 }
1767
1768
1769 /**
1770 * Allocate space for an int[4] immediate.
1771 * \return the index/position of the immediate.
1772 */
1773 static unsigned
1774 alloc_immediate_int4(struct svga_shader_emitter_v10 *emit,
1775 int x, int y, int z, int w)
1776 {
1777 union tgsi_immediate_data imm[4];
1778 imm[0].Int = x;
1779 imm[1].Int = y;
1780 imm[2].Int = z;
1781 imm[3].Int = w;
1782 return alloc_immediate_4(emit, imm);
1783 }
1784
1785
1786 /**
1787 * Allocate a shader input to store a system value.
1788 */
1789 static unsigned
1790 alloc_system_value_index(struct svga_shader_emitter_v10 *emit, unsigned index)
1791 {
1792 const unsigned n = emit->info.file_max[TGSI_FILE_INPUT] + 1 + index;
1793 assert(index < ARRAY_SIZE(emit->system_value_indexes));
1794 emit->system_value_indexes[index] = n;
1795 return n;
1796 }
1797
1798
1799 /**
1800 * Translate a TGSI immediate value (union tgsi_immediate_data[4]) to VGPU10.
1801 */
1802 static boolean
1803 emit_vgpu10_immediate(struct svga_shader_emitter_v10 *emit,
1804 const struct tgsi_full_immediate *imm)
1805 {
1806 /* We don't actually emit any code here. We just save the
1807 * immediate values and emit them later.
1808 */
1809 alloc_immediate_4(emit, imm->u);
1810 return TRUE;
1811 }
1812
1813
1814 /**
1815 * Emit a VGPU10_CUSTOMDATA_DCL_IMMEDIATE_CONSTANT_BUFFER block
1816 * containing all the immediate values previously allocated
1817 * with alloc_immediate_4().
1818 */
1819 static boolean
1820 emit_vgpu10_immediates_block(struct svga_shader_emitter_v10 *emit)
1821 {
1822 VGPU10OpcodeToken0 token;
1823
1824 assert(!emit->immediates_emitted);
1825
1826 token.value = 0;
1827 token.opcodeType = VGPU10_OPCODE_CUSTOMDATA;
1828 token.customDataClass = VGPU10_CUSTOMDATA_DCL_IMMEDIATE_CONSTANT_BUFFER;
1829
1830 /* Note: no begin/end_emit_instruction() calls */
1831 emit_dword(emit, token.value);
1832 emit_dword(emit, 2 + 4 * emit->num_immediates);
1833 emit_dwords(emit, (unsigned *) emit->immediates, 4 * emit->num_immediates);
1834
1835 emit->immediates_emitted = TRUE;
1836
1837 return TRUE;
1838 }
1839
1840
1841 /**
1842 * Translate a fragment shader's TGSI_INTERPOLATE_x mode to a vgpu10
1843 * interpolation mode.
1844 * \return a VGPU10_INTERPOLATION_x value
1845 */
1846 static unsigned
1847 translate_interpolation(const struct svga_shader_emitter_v10 *emit,
1848 enum tgsi_interpolate_mode interp,
1849 enum tgsi_interpolate_loc interpolate_loc)
1850 {
1851 if (interp == TGSI_INTERPOLATE_COLOR) {
1852 interp = emit->key.fs.flatshade ?
1853 TGSI_INTERPOLATE_CONSTANT : TGSI_INTERPOLATE_PERSPECTIVE;
1854 }
1855
1856 switch (interp) {
1857 case TGSI_INTERPOLATE_CONSTANT:
1858 return VGPU10_INTERPOLATION_CONSTANT;
1859 case TGSI_INTERPOLATE_LINEAR:
1860 return interpolate_loc == TGSI_INTERPOLATE_LOC_CENTROID ?
1861 VGPU10_INTERPOLATION_LINEAR_NOPERSPECTIVE_CENTROID :
1862 VGPU10_INTERPOLATION_LINEAR_NOPERSPECTIVE;
1863 case TGSI_INTERPOLATE_PERSPECTIVE:
1864 return interpolate_loc == TGSI_INTERPOLATE_LOC_CENTROID ?
1865 VGPU10_INTERPOLATION_LINEAR_CENTROID :
1866 VGPU10_INTERPOLATION_LINEAR;
1867 default:
1868 assert(!"Unexpected interpolation mode");
1869 return VGPU10_INTERPOLATION_CONSTANT;
1870 }
1871 }
1872
1873
1874 /**
1875 * Translate a TGSI property to VGPU10.
1876 * Don't emit any instructions yet, only need to gather the primitive property
1877 * information. The output primitive topology might be changed later. The
1878 * final property instructions will be emitted as part of the pre-helper code.
1879 */
1880 static boolean
1881 emit_vgpu10_property(struct svga_shader_emitter_v10 *emit,
1882 const struct tgsi_full_property *prop)
1883 {
1884 static const VGPU10_PRIMITIVE primType[] = {
1885 VGPU10_PRIMITIVE_POINT, /* PIPE_PRIM_POINTS */
1886 VGPU10_PRIMITIVE_LINE, /* PIPE_PRIM_LINES */
1887 VGPU10_PRIMITIVE_LINE, /* PIPE_PRIM_LINE_LOOP */
1888 VGPU10_PRIMITIVE_LINE, /* PIPE_PRIM_LINE_STRIP */
1889 VGPU10_PRIMITIVE_TRIANGLE, /* PIPE_PRIM_TRIANGLES */
1890 VGPU10_PRIMITIVE_TRIANGLE, /* PIPE_PRIM_TRIANGLE_STRIP */
1891 VGPU10_PRIMITIVE_TRIANGLE, /* PIPE_PRIM_TRIANGLE_FAN */
1892 VGPU10_PRIMITIVE_UNDEFINED, /* PIPE_PRIM_QUADS */
1893 VGPU10_PRIMITIVE_UNDEFINED, /* PIPE_PRIM_QUAD_STRIP */
1894 VGPU10_PRIMITIVE_UNDEFINED, /* PIPE_PRIM_POLYGON */
1895 VGPU10_PRIMITIVE_LINE_ADJ, /* PIPE_PRIM_LINES_ADJACENCY */
1896 VGPU10_PRIMITIVE_LINE_ADJ, /* PIPE_PRIM_LINE_STRIP_ADJACENCY */
1897 VGPU10_PRIMITIVE_TRIANGLE_ADJ, /* PIPE_PRIM_TRIANGLES_ADJACENCY */
1898 VGPU10_PRIMITIVE_TRIANGLE_ADJ /* PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY */
1899 };
1900
1901 static const VGPU10_PRIMITIVE_TOPOLOGY primTopology[] = {
1902 VGPU10_PRIMITIVE_TOPOLOGY_POINTLIST, /* PIPE_PRIM_POINTS */
1903 VGPU10_PRIMITIVE_TOPOLOGY_LINELIST, /* PIPE_PRIM_LINES */
1904 VGPU10_PRIMITIVE_TOPOLOGY_LINELIST, /* PIPE_PRIM_LINE_LOOP */
1905 VGPU10_PRIMITIVE_TOPOLOGY_LINESTRIP, /* PIPE_PRIM_LINE_STRIP */
1906 VGPU10_PRIMITIVE_TOPOLOGY_TRIANGLELIST, /* PIPE_PRIM_TRIANGLES */
1907 VGPU10_PRIMITIVE_TOPOLOGY_TRIANGLESTRIP, /* PIPE_PRIM_TRIANGLE_STRIP */
1908 VGPU10_PRIMITIVE_TOPOLOGY_TRIANGLESTRIP, /* PIPE_PRIM_TRIANGLE_FAN */
1909 VGPU10_PRIMITIVE_TOPOLOGY_UNDEFINED, /* PIPE_PRIM_QUADS */
1910 VGPU10_PRIMITIVE_TOPOLOGY_UNDEFINED, /* PIPE_PRIM_QUAD_STRIP */
1911 VGPU10_PRIMITIVE_TOPOLOGY_UNDEFINED, /* PIPE_PRIM_POLYGON */
1912 VGPU10_PRIMITIVE_TOPOLOGY_LINELIST_ADJ, /* PIPE_PRIM_LINES_ADJACENCY */
1913 VGPU10_PRIMITIVE_TOPOLOGY_LINELIST_ADJ, /* PIPE_PRIM_LINE_STRIP_ADJACENCY */
1914 VGPU10_PRIMITIVE_TOPOLOGY_TRIANGLELIST_ADJ, /* PIPE_PRIM_TRIANGLES_ADJACENCY */
1915 VGPU10_PRIMITIVE_TOPOLOGY_TRIANGLESTRIP_ADJ /* PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY */
1916 };
1917
1918 static const unsigned inputArraySize[] = {
1919 0, /* VGPU10_PRIMITIVE_UNDEFINED */
1920 1, /* VGPU10_PRIMITIVE_POINT */
1921 2, /* VGPU10_PRIMITIVE_LINE */
1922 3, /* VGPU10_PRIMITIVE_TRIANGLE */
1923 0,
1924 0,
1925 4, /* VGPU10_PRIMITIVE_LINE_ADJ */
1926 6 /* VGPU10_PRIMITIVE_TRIANGLE_ADJ */
1927 };
1928
1929 switch (prop->Property.PropertyName) {
1930 case TGSI_PROPERTY_GS_INPUT_PRIM:
1931 assert(prop->u[0].Data < ARRAY_SIZE(primType));
1932 emit->gs.prim_type = primType[prop->u[0].Data];
1933 assert(emit->gs.prim_type != VGPU10_PRIMITIVE_UNDEFINED);
1934 emit->gs.input_size = inputArraySize[emit->gs.prim_type];
1935 break;
1936
1937 case TGSI_PROPERTY_GS_OUTPUT_PRIM:
1938 assert(prop->u[0].Data < ARRAY_SIZE(primTopology));
1939 emit->gs.prim_topology = primTopology[prop->u[0].Data];
1940 assert(emit->gs.prim_topology != VGPU10_PRIMITIVE_TOPOLOGY_UNDEFINED);
1941 break;
1942
1943 case TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES:
1944 emit->gs.max_out_vertices = prop->u[0].Data;
1945 break;
1946
1947 default:
1948 break;
1949 }
1950
1951 return TRUE;
1952 }
1953
1954
1955 static void
1956 emit_property_instruction(struct svga_shader_emitter_v10 *emit,
1957 VGPU10OpcodeToken0 opcode0, unsigned nData,
1958 unsigned data)
1959 {
1960 begin_emit_instruction(emit);
1961 emit_dword(emit, opcode0.value);
1962 if (nData)
1963 emit_dword(emit, data);
1964 end_emit_instruction(emit);
1965 }
1966
1967
1968 /**
1969 * Emit property instructions
1970 */
1971 static void
1972 emit_property_instructions(struct svga_shader_emitter_v10 *emit)
1973 {
1974 VGPU10OpcodeToken0 opcode0;
1975
1976 assert(emit->unit == PIPE_SHADER_GEOMETRY);
1977
1978 /* emit input primitive type declaration */
1979 opcode0.value = 0;
1980 opcode0.opcodeType = VGPU10_OPCODE_DCL_GS_INPUT_PRIMITIVE;
1981 opcode0.primitive = emit->gs.prim_type;
1982 emit_property_instruction(emit, opcode0, 0, 0);
1983
1984 /* emit output primitive topology declaration */
1985 opcode0.value = 0;
1986 opcode0.opcodeType = VGPU10_OPCODE_DCL_GS_OUTPUT_PRIMITIVE_TOPOLOGY;
1987 opcode0.primitiveTopology = emit->gs.prim_topology;
1988 emit_property_instruction(emit, opcode0, 0, 0);
1989
1990 /* emit max output vertices */
1991 opcode0.value = 0;
1992 opcode0.opcodeType = VGPU10_OPCODE_DCL_MAX_OUTPUT_VERTEX_COUNT;
1993 emit_property_instruction(emit, opcode0, 1, emit->gs.max_out_vertices);
1994 }
1995
1996
1997 /**
1998 * Emit a vgpu10 declaration "instruction".
1999 * \param index the register index
2000 * \param size array size of the operand. In most cases, it is 1,
2001 * but for inputs to geometry shader, the array size varies
2002 * depending on the primitive type.
2003 */
2004 static void
2005 emit_decl_instruction(struct svga_shader_emitter_v10 *emit,
2006 VGPU10OpcodeToken0 opcode0,
2007 VGPU10OperandToken0 operand0,
2008 VGPU10NameToken name_token,
2009 unsigned index, unsigned size)
2010 {
2011 assert(opcode0.opcodeType);
2012 assert(operand0.mask);
2013
2014 begin_emit_instruction(emit);
2015 emit_dword(emit, opcode0.value);
2016
2017 emit_dword(emit, operand0.value);
2018
2019 if (operand0.indexDimension == VGPU10_OPERAND_INDEX_1D) {
2020 /* Next token is the index of the register to declare */
2021 emit_dword(emit, index);
2022 }
2023 else if (operand0.indexDimension >= VGPU10_OPERAND_INDEX_2D) {
2024 /* Next token is the size of the register */
2025 emit_dword(emit, size);
2026
2027 /* Followed by the index of the register */
2028 emit_dword(emit, index);
2029 }
2030
2031 if (name_token.value) {
2032 emit_dword(emit, name_token.value);
2033 }
2034
2035 end_emit_instruction(emit);
2036 }
2037
2038
2039 /**
2040 * Emit the declaration for a shader input.
2041 * \param opcodeType opcode type, one of VGPU10_OPCODE_DCL_INPUTx
2042 * \param operandType operand type, one of VGPU10_OPERAND_TYPE_INPUT_x
2043 * \param dim index dimension
2044 * \param index the input register index
2045 * \param size array size of the operand. In most cases, it is 1,
2046 * but for inputs to geometry shader, the array size varies
2047 * depending on the primitive type.
2048 * \param name one of VGPU10_NAME_x
2049 * \parma numComp number of components
2050 * \param selMode component selection mode
2051 * \param usageMask bitfield of VGPU10_OPERAND_4_COMPONENT_MASK_x values
2052 * \param interpMode interpolation mode
2053 */
2054 static void
2055 emit_input_declaration(struct svga_shader_emitter_v10 *emit,
2056 VGPU10_OPCODE_TYPE opcodeType,
2057 VGPU10_OPERAND_TYPE operandType,
2058 VGPU10_OPERAND_INDEX_DIMENSION dim,
2059 unsigned index, unsigned size,
2060 VGPU10_SYSTEM_NAME name,
2061 VGPU10_OPERAND_NUM_COMPONENTS numComp,
2062 VGPU10_OPERAND_4_COMPONENT_SELECTION_MODE selMode,
2063 unsigned usageMask,
2064 VGPU10_INTERPOLATION_MODE interpMode)
2065 {
2066 VGPU10OpcodeToken0 opcode0;
2067 VGPU10OperandToken0 operand0;
2068 VGPU10NameToken name_token;
2069
2070 assert(usageMask <= VGPU10_OPERAND_4_COMPONENT_MASK_ALL);
2071 assert(opcodeType == VGPU10_OPCODE_DCL_INPUT ||
2072 opcodeType == VGPU10_OPCODE_DCL_INPUT_SIV ||
2073 opcodeType == VGPU10_OPCODE_DCL_INPUT_PS ||
2074 opcodeType == VGPU10_OPCODE_DCL_INPUT_PS_SGV);
2075 assert(operandType == VGPU10_OPERAND_TYPE_INPUT ||
2076 operandType == VGPU10_OPERAND_TYPE_INPUT_PRIMITIVEID);
2077 assert(numComp <= VGPU10_OPERAND_4_COMPONENT);
2078 assert(selMode <= VGPU10_OPERAND_4_COMPONENT_MASK_MODE);
2079 assert(dim <= VGPU10_OPERAND_INDEX_3D);
2080 assert(name == VGPU10_NAME_UNDEFINED ||
2081 name == VGPU10_NAME_POSITION ||
2082 name == VGPU10_NAME_INSTANCE_ID ||
2083 name == VGPU10_NAME_VERTEX_ID ||
2084 name == VGPU10_NAME_PRIMITIVE_ID ||
2085 name == VGPU10_NAME_IS_FRONT_FACE);
2086 assert(interpMode == VGPU10_INTERPOLATION_UNDEFINED ||
2087 interpMode == VGPU10_INTERPOLATION_CONSTANT ||
2088 interpMode == VGPU10_INTERPOLATION_LINEAR ||
2089 interpMode == VGPU10_INTERPOLATION_LINEAR_CENTROID ||
2090 interpMode == VGPU10_INTERPOLATION_LINEAR_NOPERSPECTIVE ||
2091 interpMode == VGPU10_INTERPOLATION_LINEAR_NOPERSPECTIVE_CENTROID);
2092
2093 check_register_index(emit, opcodeType, index);
2094
2095 opcode0.value = operand0.value = name_token.value = 0;
2096
2097 opcode0.opcodeType = opcodeType;
2098 opcode0.interpolationMode = interpMode;
2099
2100 operand0.operandType = operandType;
2101 operand0.numComponents = numComp;
2102 operand0.selectionMode = selMode;
2103 operand0.mask = usageMask;
2104 operand0.indexDimension = dim;
2105 operand0.index0Representation = VGPU10_OPERAND_INDEX_IMMEDIATE32;
2106 if (dim == VGPU10_OPERAND_INDEX_2D)
2107 operand0.index1Representation = VGPU10_OPERAND_INDEX_IMMEDIATE32;
2108
2109 name_token.name = name;
2110
2111 emit_decl_instruction(emit, opcode0, operand0, name_token, index, size);
2112 }
2113
2114
2115 /**
2116 * Emit the declaration for a shader output.
2117 * \param type one of VGPU10_OPCODE_DCL_OUTPUTx
2118 * \param index the output register index
2119 * \param name one of VGPU10_NAME_x
2120 * \param usageMask bitfield of VGPU10_OPERAND_4_COMPONENT_MASK_x values
2121 */
2122 static void
2123 emit_output_declaration(struct svga_shader_emitter_v10 *emit,
2124 VGPU10_OPCODE_TYPE type, unsigned index,
2125 VGPU10_SYSTEM_NAME name,
2126 unsigned usageMask)
2127 {
2128 VGPU10OpcodeToken0 opcode0;
2129 VGPU10OperandToken0 operand0;
2130 VGPU10NameToken name_token;
2131
2132 assert(usageMask <= VGPU10_OPERAND_4_COMPONENT_MASK_ALL);
2133 assert(type == VGPU10_OPCODE_DCL_OUTPUT ||
2134 type == VGPU10_OPCODE_DCL_OUTPUT_SGV ||
2135 type == VGPU10_OPCODE_DCL_OUTPUT_SIV);
2136 assert(name == VGPU10_NAME_UNDEFINED ||
2137 name == VGPU10_NAME_POSITION ||
2138 name == VGPU10_NAME_PRIMITIVE_ID ||
2139 name == VGPU10_NAME_RENDER_TARGET_ARRAY_INDEX ||
2140 name == VGPU10_NAME_CLIP_DISTANCE);
2141
2142 check_register_index(emit, type, index);
2143
2144 opcode0.value = operand0.value = name_token.value = 0;
2145
2146 opcode0.opcodeType = type;
2147 operand0.operandType = VGPU10_OPERAND_TYPE_OUTPUT;
2148 operand0.numComponents = VGPU10_OPERAND_4_COMPONENT;
2149 operand0.selectionMode = VGPU10_OPERAND_4_COMPONENT_MASK_MODE;
2150 operand0.mask = usageMask;
2151 operand0.indexDimension = VGPU10_OPERAND_INDEX_1D;
2152 operand0.index0Representation = VGPU10_OPERAND_INDEX_IMMEDIATE32;
2153
2154 name_token.name = name;
2155
2156 emit_decl_instruction(emit, opcode0, operand0, name_token, index, 1);
2157 }
2158
2159
2160 /**
2161 * Emit the declaration for the fragment depth output.
2162 */
2163 static void
2164 emit_fragdepth_output_declaration(struct svga_shader_emitter_v10 *emit)
2165 {
2166 VGPU10OpcodeToken0 opcode0;
2167 VGPU10OperandToken0 operand0;
2168 VGPU10NameToken name_token;
2169
2170 assert(emit->unit == PIPE_SHADER_FRAGMENT);
2171
2172 opcode0.value = operand0.value = name_token.value = 0;
2173
2174 opcode0.opcodeType = VGPU10_OPCODE_DCL_OUTPUT;
2175 operand0.operandType = VGPU10_OPERAND_TYPE_OUTPUT_DEPTH;
2176 operand0.numComponents = VGPU10_OPERAND_1_COMPONENT;
2177 operand0.indexDimension = VGPU10_OPERAND_INDEX_0D;
2178 operand0.mask = VGPU10_OPERAND_4_COMPONENT_MASK_ALL;
2179
2180 emit_decl_instruction(emit, opcode0, operand0, name_token, 0, 1);
2181 }
2182
2183
2184 /**
2185 * Emit the declaration for a system value input/output.
2186 */
2187 static void
2188 emit_system_value_declaration(struct svga_shader_emitter_v10 *emit,
2189 enum tgsi_semantic semantic_name, unsigned index)
2190 {
2191 switch (semantic_name) {
2192 case TGSI_SEMANTIC_INSTANCEID:
2193 index = alloc_system_value_index(emit, index);
2194 emit_input_declaration(emit, VGPU10_OPCODE_DCL_INPUT_SIV,
2195 VGPU10_OPERAND_TYPE_INPUT,
2196 VGPU10_OPERAND_INDEX_1D,
2197 index, 1,
2198 VGPU10_NAME_INSTANCE_ID,
2199 VGPU10_OPERAND_4_COMPONENT,
2200 VGPU10_OPERAND_4_COMPONENT_MASK_MODE,
2201 VGPU10_OPERAND_4_COMPONENT_MASK_X,
2202 VGPU10_INTERPOLATION_UNDEFINED);
2203 break;
2204 case TGSI_SEMANTIC_VERTEXID:
2205 index = alloc_system_value_index(emit, index);
2206 emit_input_declaration(emit, VGPU10_OPCODE_DCL_INPUT_SIV,
2207 VGPU10_OPERAND_TYPE_INPUT,
2208 VGPU10_OPERAND_INDEX_1D,
2209 index, 1,
2210 VGPU10_NAME_VERTEX_ID,
2211 VGPU10_OPERAND_4_COMPONENT,
2212 VGPU10_OPERAND_4_COMPONENT_MASK_MODE,
2213 VGPU10_OPERAND_4_COMPONENT_MASK_X,
2214 VGPU10_INTERPOLATION_UNDEFINED);
2215 break;
2216 default:
2217 ; /* XXX */
2218 }
2219 }
2220
2221 /**
2222 * Translate a TGSI declaration to VGPU10.
2223 */
2224 static boolean
2225 emit_vgpu10_declaration(struct svga_shader_emitter_v10 *emit,
2226 const struct tgsi_full_declaration *decl)
2227 {
2228 switch (decl->Declaration.File) {
2229 case TGSI_FILE_INPUT:
2230 /* do nothing - see emit_input_declarations() */
2231 return TRUE;
2232
2233 case TGSI_FILE_OUTPUT:
2234 assert(decl->Range.First == decl->Range.Last);
2235 emit->output_usage_mask[decl->Range.First] = decl->Declaration.UsageMask;
2236 return TRUE;
2237
2238 case TGSI_FILE_TEMPORARY:
2239 /* Don't declare the temps here. Just keep track of how many
2240 * and emit the declaration later.
2241 */
2242 if (decl->Declaration.Array) {
2243 /* Indexed temporary array. Save the start index of the array
2244 * and the size of the array.
2245 */
2246 const unsigned arrayID = MIN2(decl->Array.ArrayID, MAX_TEMP_ARRAYS);
2247 unsigned i;
2248
2249 assert(arrayID < ARRAY_SIZE(emit->temp_arrays));
2250
2251 /* Save this array so we can emit the declaration for it later */
2252 emit->temp_arrays[arrayID].start = decl->Range.First;
2253 emit->temp_arrays[arrayID].size =
2254 decl->Range.Last - decl->Range.First + 1;
2255
2256 emit->num_temp_arrays = MAX2(emit->num_temp_arrays, arrayID + 1);
2257 assert(emit->num_temp_arrays <= MAX_TEMP_ARRAYS);
2258 emit->num_temp_arrays = MIN2(emit->num_temp_arrays, MAX_TEMP_ARRAYS);
2259
2260 /* Fill in the temp_map entries for this array */
2261 for (i = decl->Range.First; i <= decl->Range.Last; i++) {
2262 emit->temp_map[i].arrayId = arrayID;
2263 emit->temp_map[i].index = i - decl->Range.First;
2264 }
2265 }
2266
2267 /* for all temps, indexed or not, keep track of highest index */
2268 emit->num_shader_temps = MAX2(emit->num_shader_temps,
2269 decl->Range.Last + 1);
2270 return TRUE;
2271
2272 case TGSI_FILE_CONSTANT:
2273 /* Don't declare constants here. Just keep track and emit later. */
2274 {
2275 unsigned constbuf = 0, num_consts;
2276 if (decl->Declaration.Dimension) {
2277 constbuf = decl->Dim.Index2D;
2278 }
2279 /* We throw an assertion here when, in fact, the shader should never
2280 * have linked due to constbuf index out of bounds, so we shouldn't
2281 * have reached here.
2282 */
2283 assert(constbuf < ARRAY_SIZE(emit->num_shader_consts));
2284
2285 num_consts = MAX2(emit->num_shader_consts[constbuf],
2286 decl->Range.Last + 1);
2287
2288 if (num_consts > VGPU10_MAX_CONSTANT_BUFFER_ELEMENT_COUNT) {
2289 debug_printf("Warning: constant buffer is declared to size [%u]"
2290 " but [%u] is the limit.\n",
2291 num_consts,
2292 VGPU10_MAX_CONSTANT_BUFFER_ELEMENT_COUNT);
2293 }
2294 /* The linker doesn't enforce the max UBO size so we clamp here */
2295 emit->num_shader_consts[constbuf] =
2296 MIN2(num_consts, VGPU10_MAX_CONSTANT_BUFFER_ELEMENT_COUNT);
2297 }
2298 return TRUE;
2299
2300 case TGSI_FILE_IMMEDIATE:
2301 assert(!"TGSI_FILE_IMMEDIATE not handled yet!");
2302 return FALSE;
2303
2304 case TGSI_FILE_SYSTEM_VALUE:
2305 emit_system_value_declaration(emit, decl->Semantic.Name,
2306 decl->Range.First);
2307 return TRUE;
2308
2309 case TGSI_FILE_SAMPLER:
2310 /* Don't declare samplers here. Just keep track and emit later. */
2311 emit->num_samplers = MAX2(emit->num_samplers, decl->Range.Last + 1);
2312 return TRUE;
2313
2314 #if 0
2315 case TGSI_FILE_RESOURCE:
2316 /*opcode0.opcodeType = VGPU10_OPCODE_DCL_RESOURCE;*/
2317 /* XXX more, VGPU10_RETURN_TYPE_FLOAT */
2318 assert(!"TGSI_FILE_RESOURCE not handled yet");
2319 return FALSE;
2320 #endif
2321
2322 case TGSI_FILE_ADDRESS:
2323 emit->num_address_regs = MAX2(emit->num_address_regs,
2324 decl->Range.Last + 1);
2325 return TRUE;
2326
2327 case TGSI_FILE_SAMPLER_VIEW:
2328 {
2329 unsigned unit = decl->Range.First;
2330 assert(decl->Range.First == decl->Range.Last);
2331 emit->sampler_target[unit] = decl->SamplerView.Resource;
2332 /* Note: we can ignore YZW return types for now */
2333 emit->sampler_return_type[unit] = decl->SamplerView.ReturnTypeX;
2334 emit->sampler_view[unit] = TRUE;
2335 }
2336 return TRUE;
2337
2338 default:
2339 assert(!"Unexpected type of declaration");
2340 return FALSE;
2341 }
2342 }
2343
2344
2345
2346 /**
2347 * Emit all input declarations.
2348 */
2349 static boolean
2350 emit_input_declarations(struct svga_shader_emitter_v10 *emit)
2351 {
2352 unsigned i;
2353
2354 if (emit->unit == PIPE_SHADER_FRAGMENT) {
2355
2356 for (i = 0; i < emit->linkage.num_inputs; i++) {
2357 enum tgsi_semantic semantic_name = emit->info.input_semantic_name[i];
2358 unsigned usage_mask = emit->info.input_usage_mask[i];
2359 unsigned index = emit->linkage.input_map[i];
2360 VGPU10_OPCODE_TYPE type;
2361 VGPU10_INTERPOLATION_MODE interpolationMode;
2362 VGPU10_SYSTEM_NAME name;
2363
2364 if (usage_mask == 0)
2365 continue; /* register is not actually used */
2366
2367 if (semantic_name == TGSI_SEMANTIC_POSITION) {
2368 /* fragment position input */
2369 type = VGPU10_OPCODE_DCL_INPUT_PS_SGV;
2370 interpolationMode = VGPU10_INTERPOLATION_LINEAR;
2371 name = VGPU10_NAME_POSITION;
2372 if (usage_mask & TGSI_WRITEMASK_W) {
2373 /* we need to replace use of 'w' with '1/w' */
2374 emit->fs.fragcoord_input_index = i;
2375 }
2376 }
2377 else if (semantic_name == TGSI_SEMANTIC_FACE) {
2378 /* fragment front-facing input */
2379 type = VGPU10_OPCODE_DCL_INPUT_PS_SGV;
2380 interpolationMode = VGPU10_INTERPOLATION_CONSTANT;
2381 name = VGPU10_NAME_IS_FRONT_FACE;
2382 emit->fs.face_input_index = i;
2383 }
2384 else if (semantic_name == TGSI_SEMANTIC_PRIMID) {
2385 /* primitive ID */
2386 type = VGPU10_OPCODE_DCL_INPUT_PS_SGV;
2387 interpolationMode = VGPU10_INTERPOLATION_CONSTANT;
2388 name = VGPU10_NAME_PRIMITIVE_ID;
2389 }
2390 else {
2391 /* general fragment input */
2392 type = VGPU10_OPCODE_DCL_INPUT_PS;
2393 interpolationMode =
2394 translate_interpolation(emit,
2395 emit->info.input_interpolate[i],
2396 emit->info.input_interpolate_loc[i]);
2397
2398 /* keeps track if flat interpolation mode is being used */
2399 emit->uses_flat_interp |=
2400 (interpolationMode == VGPU10_INTERPOLATION_CONSTANT);
2401
2402 name = VGPU10_NAME_UNDEFINED;
2403 }
2404
2405 emit_input_declaration(emit, type,
2406 VGPU10_OPERAND_TYPE_INPUT,
2407 VGPU10_OPERAND_INDEX_1D, index, 1,
2408 name,
2409 VGPU10_OPERAND_4_COMPONENT,
2410 VGPU10_OPERAND_4_COMPONENT_MASK_MODE,
2411 VGPU10_OPERAND_4_COMPONENT_MASK_ALL,
2412 interpolationMode);
2413 }
2414 }
2415 else if (emit->unit == PIPE_SHADER_GEOMETRY) {
2416
2417 for (i = 0; i < emit->info.num_inputs; i++) {
2418 enum tgsi_semantic semantic_name = emit->info.input_semantic_name[i];
2419 unsigned usage_mask = emit->info.input_usage_mask[i];
2420 unsigned index = emit->linkage.input_map[i];
2421 VGPU10_OPCODE_TYPE opcodeType, operandType;
2422 VGPU10_OPERAND_NUM_COMPONENTS numComp;
2423 VGPU10_OPERAND_4_COMPONENT_SELECTION_MODE selMode;
2424 VGPU10_SYSTEM_NAME name;
2425 VGPU10_OPERAND_INDEX_DIMENSION dim;
2426
2427 if (usage_mask == 0)
2428 continue; /* register is not actually used */
2429
2430 opcodeType = VGPU10_OPCODE_DCL_INPUT;
2431 operandType = VGPU10_OPERAND_TYPE_INPUT;
2432 numComp = VGPU10_OPERAND_4_COMPONENT;
2433 selMode = VGPU10_OPERAND_4_COMPONENT_MASK_MODE;
2434 name = VGPU10_NAME_UNDEFINED;
2435
2436 /* all geometry shader inputs are two dimensional except
2437 * gl_PrimitiveID
2438 */
2439 dim = VGPU10_OPERAND_INDEX_2D;
2440
2441 if (semantic_name == TGSI_SEMANTIC_PRIMID) {
2442 /* Primitive ID */
2443 operandType = VGPU10_OPERAND_TYPE_INPUT_PRIMITIVEID;
2444 dim = VGPU10_OPERAND_INDEX_0D;
2445 numComp = VGPU10_OPERAND_0_COMPONENT;
2446 selMode = 0;
2447
2448 /* also save the register index so we can check for
2449 * primitive id when emit src register. We need to modify the
2450 * operand type, index dimension when emit primitive id src reg.
2451 */
2452 emit->gs.prim_id_index = i;
2453 }
2454 else if (semantic_name == TGSI_SEMANTIC_POSITION) {
2455 /* vertex position input */
2456 opcodeType = VGPU10_OPCODE_DCL_INPUT_SIV;
2457 name = VGPU10_NAME_POSITION;
2458 }
2459
2460 emit_input_declaration(emit, opcodeType, operandType,
2461 dim, index,
2462 emit->gs.input_size,
2463 name,
2464 numComp, selMode,
2465 VGPU10_OPERAND_4_COMPONENT_MASK_ALL,
2466 VGPU10_INTERPOLATION_UNDEFINED);
2467 }
2468 }
2469 else {
2470 assert(emit->unit == PIPE_SHADER_VERTEX);
2471
2472 for (i = 0; i < emit->info.file_max[TGSI_FILE_INPUT] + 1; i++) {
2473 unsigned usage_mask = emit->info.input_usage_mask[i];
2474 unsigned index = i;
2475
2476 if (usage_mask == 0)
2477 continue; /* register is not actually used */
2478
2479 emit_input_declaration(emit, VGPU10_OPCODE_DCL_INPUT,
2480 VGPU10_OPERAND_TYPE_INPUT,
2481 VGPU10_OPERAND_INDEX_1D, index, 1,
2482 VGPU10_NAME_UNDEFINED,
2483 VGPU10_OPERAND_4_COMPONENT,
2484 VGPU10_OPERAND_4_COMPONENT_MASK_MODE,
2485 VGPU10_OPERAND_4_COMPONENT_MASK_ALL,
2486 VGPU10_INTERPOLATION_UNDEFINED);
2487 }
2488 }
2489
2490 return TRUE;
2491 }
2492
2493
2494 /**
2495 * Emit all output declarations.
2496 */
2497 static boolean
2498 emit_output_declarations(struct svga_shader_emitter_v10 *emit)
2499 {
2500 unsigned i;
2501
2502 for (i = 0; i < emit->info.num_outputs; i++) {
2503 /*const unsigned usage_mask = emit->info.output_usage_mask[i];*/
2504 const enum tgsi_semantic semantic_name =
2505 emit->info.output_semantic_name[i];
2506 const unsigned semantic_index = emit->info.output_semantic_index[i];
2507 unsigned index = i;
2508
2509 if (emit->unit == PIPE_SHADER_FRAGMENT) {
2510 if (semantic_name == TGSI_SEMANTIC_COLOR) {
2511 assert(semantic_index < ARRAY_SIZE(emit->fs.color_out_index));
2512
2513 emit->fs.color_out_index[semantic_index] = index;
2514
2515 emit->fs.num_color_outputs = MAX2(emit->fs.num_color_outputs,
2516 index + 1);
2517
2518 /* The semantic index is the shader's color output/buffer index */
2519 emit_output_declaration(emit,
2520 VGPU10_OPCODE_DCL_OUTPUT, semantic_index,
2521 VGPU10_NAME_UNDEFINED,
2522 VGPU10_OPERAND_4_COMPONENT_MASK_ALL);
2523
2524 if (semantic_index == 0) {
2525 if (emit->key.fs.write_color0_to_n_cbufs > 1) {
2526 /* Emit declarations for the additional color outputs
2527 * for broadcasting.
2528 */
2529 unsigned j;
2530 for (j = 1; j < emit->key.fs.write_color0_to_n_cbufs; j++) {
2531 /* Allocate a new output index */
2532 unsigned idx = emit->info.num_outputs + j - 1;
2533 emit->fs.color_out_index[j] = idx;
2534 emit_output_declaration(emit,
2535 VGPU10_OPCODE_DCL_OUTPUT, idx,
2536 VGPU10_NAME_UNDEFINED,
2537 VGPU10_OPERAND_4_COMPONENT_MASK_ALL);
2538 emit->info.output_semantic_index[idx] = j;
2539 }
2540
2541 emit->fs.num_color_outputs =
2542 emit->key.fs.write_color0_to_n_cbufs;
2543 }
2544 }
2545 else {
2546 assert(!emit->key.fs.write_color0_to_n_cbufs);
2547 }
2548 }
2549 else if (semantic_name == TGSI_SEMANTIC_POSITION) {
2550 /* Fragment depth output */
2551 emit_fragdepth_output_declaration(emit);
2552 }
2553 else {
2554 assert(!"Bad output semantic name");
2555 }
2556 }
2557 else {
2558 /* VS or GS */
2559 VGPU10_COMPONENT_NAME name;
2560 VGPU10_OPCODE_TYPE type;
2561 unsigned writemask = VGPU10_OPERAND_4_COMPONENT_MASK_ALL;
2562
2563 switch (semantic_name) {
2564 case TGSI_SEMANTIC_POSITION:
2565 assert(emit->unit != PIPE_SHADER_FRAGMENT);
2566 type = VGPU10_OPCODE_DCL_OUTPUT_SIV;
2567 name = VGPU10_NAME_POSITION;
2568 /* Save the index of the vertex position output register */
2569 emit->vposition.out_index = index;
2570 break;
2571 case TGSI_SEMANTIC_CLIPDIST:
2572 type = VGPU10_OPCODE_DCL_OUTPUT_SIV;
2573 name = VGPU10_NAME_CLIP_DISTANCE;
2574 /* save the starting index of the clip distance output register */
2575 if (semantic_index == 0)
2576 emit->clip_dist_out_index = index;
2577 writemask = emit->output_usage_mask[index];
2578 writemask = apply_clip_plane_mask(emit, writemask, semantic_index);
2579 if (writemask == 0x0) {
2580 continue; /* discard this do-nothing declaration */
2581 }
2582 break;
2583 case TGSI_SEMANTIC_PRIMID:
2584 assert(emit->unit == PIPE_SHADER_GEOMETRY);
2585 type = VGPU10_OPCODE_DCL_OUTPUT_SGV;
2586 name = VGPU10_NAME_PRIMITIVE_ID;
2587 break;
2588 case TGSI_SEMANTIC_LAYER:
2589 assert(emit->unit == PIPE_SHADER_GEOMETRY);
2590 type = VGPU10_OPCODE_DCL_OUTPUT_SGV;
2591 name = VGPU10_NAME_RENDER_TARGET_ARRAY_INDEX;
2592 break;
2593 case TGSI_SEMANTIC_CLIPVERTEX:
2594 type = VGPU10_OPCODE_DCL_OUTPUT;
2595 name = VGPU10_NAME_UNDEFINED;
2596 emit->clip_vertex_out_index = index;
2597 break;
2598 default:
2599 /* generic output */
2600 type = VGPU10_OPCODE_DCL_OUTPUT;
2601 name = VGPU10_NAME_UNDEFINED;
2602 }
2603
2604 emit_output_declaration(emit, type, index, name, writemask);
2605 }
2606 }
2607
2608 if (emit->vposition.so_index != INVALID_INDEX &&
2609 emit->vposition.out_index != INVALID_INDEX) {
2610
2611 assert(emit->unit != PIPE_SHADER_FRAGMENT);
2612
2613 /* Emit the declaration for the non-adjusted vertex position
2614 * for stream output purpose
2615 */
2616 emit_output_declaration(emit, VGPU10_OPCODE_DCL_OUTPUT,
2617 emit->vposition.so_index,
2618 VGPU10_NAME_UNDEFINED,
2619 VGPU10_OPERAND_4_COMPONENT_MASK_ALL);
2620 }
2621
2622 if (emit->clip_dist_so_index != INVALID_INDEX &&
2623 emit->clip_dist_out_index != INVALID_INDEX) {
2624
2625 assert(emit->unit != PIPE_SHADER_FRAGMENT);
2626
2627 /* Emit the declaration for the clip distance shadow copy which
2628 * will be used for stream output purpose and for clip distance
2629 * varying variable
2630 */
2631 emit_output_declaration(emit, VGPU10_OPCODE_DCL_OUTPUT,
2632 emit->clip_dist_so_index,
2633 VGPU10_NAME_UNDEFINED,
2634 emit->output_usage_mask[emit->clip_dist_out_index]);
2635
2636 if (emit->info.num_written_clipdistance > 4) {
2637 /* for the second clip distance register, each handles 4 planes */
2638 emit_output_declaration(emit, VGPU10_OPCODE_DCL_OUTPUT,
2639 emit->clip_dist_so_index + 1,
2640 VGPU10_NAME_UNDEFINED,
2641 emit->output_usage_mask[emit->clip_dist_out_index+1]);
2642 }
2643 }
2644
2645 return TRUE;
2646 }
2647
2648
2649 /**
2650 * Emit the declaration for the temporary registers.
2651 */
2652 static boolean
2653 emit_temporaries_declaration(struct svga_shader_emitter_v10 *emit)
2654 {
2655 unsigned total_temps, reg, i;
2656
2657 total_temps = emit->num_shader_temps;
2658
2659 /* If there is indirect access to non-indexable temps in the shader,
2660 * convert those temps to indexable temps. This works around a bug
2661 * in the GLSL->TGSI translator exposed in piglit test
2662 * glsl-1.20/execution/fs-const-array-of-struct-of-array.shader_test.
2663 * Internal temps added by the driver remain as non-indexable temps.
2664 */
2665 if ((emit->info.indirect_files & (1 << TGSI_FILE_TEMPORARY)) &&
2666 emit->num_temp_arrays == 0) {
2667 unsigned arrayID;
2668
2669 arrayID = 1;
2670 emit->num_temp_arrays = arrayID + 1;
2671 emit->temp_arrays[arrayID].start = 0;
2672 emit->temp_arrays[arrayID].size = total_temps;
2673
2674 /* Fill in the temp_map entries for this temp array */
2675 for (i = 0; i < total_temps; i++) {
2676 emit->temp_map[i].arrayId = arrayID;
2677 emit->temp_map[i].index = i;
2678 }
2679 }
2680
2681 /* Allocate extra temps for specially-implemented instructions,
2682 * such as LIT.
2683 */
2684 total_temps += MAX_INTERNAL_TEMPS;
2685
2686 if (emit->unit == PIPE_SHADER_VERTEX || emit->unit == PIPE_SHADER_GEOMETRY) {
2687 if (emit->vposition.need_prescale || emit->key.vs.undo_viewport ||
2688 emit->key.clip_plane_enable ||
2689 emit->vposition.so_index != INVALID_INDEX) {
2690 emit->vposition.tmp_index = total_temps;
2691 total_temps += 1;
2692 }
2693
2694 if (emit->unit == PIPE_SHADER_VERTEX) {
2695 unsigned attrib_mask = (emit->key.vs.adjust_attrib_w_1 |
2696 emit->key.vs.adjust_attrib_itof |
2697 emit->key.vs.adjust_attrib_utof |
2698 emit->key.vs.attrib_is_bgra |
2699 emit->key.vs.attrib_puint_to_snorm |
2700 emit->key.vs.attrib_puint_to_uscaled |
2701 emit->key.vs.attrib_puint_to_sscaled);
2702 while (attrib_mask) {
2703 unsigned index = u_bit_scan(&attrib_mask);
2704 emit->vs.adjusted_input[index] = total_temps++;
2705 }
2706 }
2707
2708 if (emit->clip_mode == CLIP_DISTANCE) {
2709 /* We need to write the clip distance to a temporary register
2710 * first. Then it will be copied to the shadow copy for
2711 * the clip distance varying variable and stream output purpose.
2712 * It will also be copied to the actual CLIPDIST register
2713 * according to the enabled clip planes
2714 */
2715 emit->clip_dist_tmp_index = total_temps++;
2716 if (emit->info.num_written_clipdistance > 4)
2717 total_temps++; /* second clip register */
2718 }
2719 else if (emit->clip_mode == CLIP_VERTEX) {
2720 /* We need to convert the TGSI CLIPVERTEX output to one or more
2721 * clip distances. Allocate a temp reg for the clipvertex here.
2722 */
2723 assert(emit->info.writes_clipvertex > 0);
2724 emit->clip_vertex_tmp_index = total_temps;
2725 total_temps++;
2726 }
2727 }
2728 else if (emit->unit == PIPE_SHADER_FRAGMENT) {
2729 if (emit->key.fs.alpha_func != SVGA3D_CMP_ALWAYS ||
2730 emit->key.fs.write_color0_to_n_cbufs > 1) {
2731 /* Allocate a temp to hold the output color */
2732 emit->fs.color_tmp_index = total_temps;
2733 total_temps += 1;
2734 }
2735
2736 if (emit->fs.face_input_index != INVALID_INDEX) {
2737 /* Allocate a temp for the +/-1 face register */
2738 emit->fs.face_tmp_index = total_temps;
2739 total_temps += 1;
2740 }
2741
2742 if (emit->fs.fragcoord_input_index != INVALID_INDEX) {
2743 /* Allocate a temp for modified fragment position register */
2744 emit->fs.fragcoord_tmp_index = total_temps;
2745 total_temps += 1;
2746 }
2747 }
2748
2749 for (i = 0; i < emit->num_address_regs; i++) {
2750 emit->address_reg_index[i] = total_temps++;
2751 }
2752
2753 /* Initialize the temp_map array which maps TGSI temp indexes to VGPU10
2754 * temp indexes. Basically, we compact all the non-array temp register
2755 * indexes into a consecutive series.
2756 *
2757 * Before, we may have some TGSI declarations like:
2758 * DCL TEMP[0..1], LOCAL
2759 * DCL TEMP[2..4], ARRAY(1), LOCAL
2760 * DCL TEMP[5..7], ARRAY(2), LOCAL
2761 * plus, some extra temps, like TEMP[8], TEMP[9] for misc things
2762 *
2763 * After, we'll have a map like this:
2764 * temp_map[0] = { array 0, index 0 }
2765 * temp_map[1] = { array 0, index 1 }
2766 * temp_map[2] = { array 1, index 0 }
2767 * temp_map[3] = { array 1, index 1 }
2768 * temp_map[4] = { array 1, index 2 }
2769 * temp_map[5] = { array 2, index 0 }
2770 * temp_map[6] = { array 2, index 1 }
2771 * temp_map[7] = { array 2, index 2 }
2772 * temp_map[8] = { array 0, index 2 }
2773 * temp_map[9] = { array 0, index 3 }
2774 *
2775 * We'll declare two arrays of 3 elements, plus a set of four non-indexed
2776 * temps numbered 0..3
2777 *
2778 * Any time we emit a temporary register index, we'll have to use the
2779 * temp_map[] table to convert the TGSI index to the VGPU10 index.
2780 *
2781 * Finally, we recompute the total_temps value here.
2782 */
2783 reg = 0;
2784 for (i = 0; i < total_temps; i++) {
2785 if (emit->temp_map[i].arrayId == 0) {
2786 emit->temp_map[i].index = reg++;
2787 }
2788 }
2789
2790 if (0) {
2791 debug_printf("total_temps %u\n", total_temps);
2792 for (i = 0; i < total_temps; i++) {
2793 debug_printf("temp %u -> array %u index %u\n",
2794 i, emit->temp_map[i].arrayId, emit->temp_map[i].index);
2795 }
2796 }
2797
2798 total_temps = reg;
2799
2800 /* Emit declaration of ordinary temp registers */
2801 if (total_temps > 0) {
2802 VGPU10OpcodeToken0 opcode0;
2803
2804 opcode0.value = 0;
2805 opcode0.opcodeType = VGPU10_OPCODE_DCL_TEMPS;
2806
2807 begin_emit_instruction(emit);
2808 emit_dword(emit, opcode0.value);
2809 emit_dword(emit, total_temps);
2810 end_emit_instruction(emit);
2811 }
2812
2813 /* Emit declarations for indexable temp arrays. Skip 0th entry since
2814 * it's unused.
2815 */
2816 for (i = 1; i < emit->num_temp_arrays; i++) {
2817 unsigned num_temps = emit->temp_arrays[i].size;
2818
2819 if (num_temps > 0) {
2820 VGPU10OpcodeToken0 opcode0;
2821
2822 opcode0.value = 0;
2823 opcode0.opcodeType = VGPU10_OPCODE_DCL_INDEXABLE_TEMP;
2824
2825 begin_emit_instruction(emit);
2826 emit_dword(emit, opcode0.value);
2827 emit_dword(emit, i); /* which array */
2828 emit_dword(emit, num_temps);
2829 emit_dword(emit, 4); /* num components */
2830 end_emit_instruction(emit);
2831
2832 total_temps += num_temps;
2833 }
2834 }
2835
2836 /* Check that the grand total of all regular and indexed temps is
2837 * under the limit.
2838 */
2839 check_register_index(emit, VGPU10_OPCODE_DCL_TEMPS, total_temps - 1);
2840
2841 return TRUE;
2842 }
2843
2844
2845 static boolean
2846 emit_constant_declaration(struct svga_shader_emitter_v10 *emit)
2847 {
2848 VGPU10OpcodeToken0 opcode0;
2849 VGPU10OperandToken0 operand0;
2850 unsigned total_consts, i;
2851
2852 opcode0.value = 0;
2853 opcode0.opcodeType = VGPU10_OPCODE_DCL_CONSTANT_BUFFER;
2854 opcode0.accessPattern = VGPU10_CB_IMMEDIATE_INDEXED;
2855 /* XXX or, access pattern = VGPU10_CB_DYNAMIC_INDEXED */
2856
2857 operand0.value = 0;
2858 operand0.numComponents = VGPU10_OPERAND_4_COMPONENT;
2859 operand0.indexDimension = VGPU10_OPERAND_INDEX_2D;
2860 operand0.index0Representation = VGPU10_OPERAND_INDEX_IMMEDIATE32;
2861 operand0.index1Representation = VGPU10_OPERAND_INDEX_IMMEDIATE32;
2862 operand0.operandType = VGPU10_OPERAND_TYPE_CONSTANT_BUFFER;
2863 operand0.selectionMode = VGPU10_OPERAND_4_COMPONENT_SWIZZLE_MODE;
2864 operand0.swizzleX = 0;
2865 operand0.swizzleY = 1;
2866 operand0.swizzleZ = 2;
2867 operand0.swizzleW = 3;
2868
2869 /**
2870 * Emit declaration for constant buffer [0]. We also allocate
2871 * room for the extra constants here.
2872 */
2873 total_consts = emit->num_shader_consts[0];
2874
2875 /* Now, allocate constant slots for the "extra" constants.
2876 * Note: it's critical that these extra constant locations
2877 * exactly match what's emitted by the "extra" constants code
2878 * in svga_state_constants.c
2879 */
2880
2881 /* Vertex position scale/translation */
2882 if (emit->vposition.need_prescale) {
2883 emit->vposition.prescale_scale_index = total_consts++;
2884 emit->vposition.prescale_trans_index = total_consts++;
2885 }
2886
2887 if (emit->unit == PIPE_SHADER_VERTEX) {
2888 if (emit->key.vs.undo_viewport) {
2889 emit->vs.viewport_index = total_consts++;
2890 }
2891 }
2892
2893 /* user-defined clip planes */
2894 if (emit->key.clip_plane_enable) {
2895 unsigned n = util_bitcount(emit->key.clip_plane_enable);
2896 assert(emit->unit == PIPE_SHADER_VERTEX ||
2897 emit->unit == PIPE_SHADER_GEOMETRY);
2898 for (i = 0; i < n; i++) {
2899 emit->clip_plane_const[i] = total_consts++;
2900 }
2901 }
2902
2903 for (i = 0; i < emit->num_samplers; i++) {
2904
2905 if (emit->sampler_view[i]) {
2906
2907 /* Texcoord scale factors for RECT textures */
2908 if (emit->key.tex[i].unnormalized) {
2909 emit->texcoord_scale_index[i] = total_consts++;
2910 }
2911
2912 /* Texture buffer sizes */
2913 if (emit->sampler_target[i] == TGSI_TEXTURE_BUFFER) {
2914 emit->texture_buffer_size_index[i] = total_consts++;
2915 }
2916 }
2917 }
2918
2919 if (total_consts > 0) {
2920 begin_emit_instruction(emit);
2921 emit_dword(emit, opcode0.value);
2922 emit_dword(emit, operand0.value);
2923 emit_dword(emit, 0); /* which const buffer slot */
2924 emit_dword(emit, total_consts);
2925 end_emit_instruction(emit);
2926 }
2927
2928 /* Declare remaining constant buffers (UBOs) */
2929 for (i = 1; i < ARRAY_SIZE(emit->num_shader_consts); i++) {
2930 if (emit->num_shader_consts[i] > 0) {
2931 begin_emit_instruction(emit);
2932 emit_dword(emit, opcode0.value);
2933 emit_dword(emit, operand0.value);
2934 emit_dword(emit, i); /* which const buffer slot */
2935 emit_dword(emit, emit->num_shader_consts[i]);
2936 end_emit_instruction(emit);
2937 }
2938 }
2939
2940 return TRUE;
2941 }
2942
2943
2944 /**
2945 * Emit declarations for samplers.
2946 */
2947 static boolean
2948 emit_sampler_declarations(struct svga_shader_emitter_v10 *emit)
2949 {
2950 unsigned i;
2951
2952 for (i = 0; i < emit->num_samplers; i++) {
2953 VGPU10OpcodeToken0 opcode0;
2954 VGPU10OperandToken0 operand0;
2955
2956 opcode0.value = 0;
2957 opcode0.opcodeType = VGPU10_OPCODE_DCL_SAMPLER;
2958 opcode0.samplerMode = VGPU10_SAMPLER_MODE_DEFAULT;
2959
2960 operand0.value = 0;
2961 operand0.numComponents = VGPU10_OPERAND_0_COMPONENT;
2962 operand0.operandType = VGPU10_OPERAND_TYPE_SAMPLER;
2963 operand0.indexDimension = VGPU10_OPERAND_INDEX_1D;
2964 operand0.index0Representation = VGPU10_OPERAND_INDEX_IMMEDIATE32;
2965
2966 begin_emit_instruction(emit);
2967 emit_dword(emit, opcode0.value);
2968 emit_dword(emit, operand0.value);
2969 emit_dword(emit, i);
2970 end_emit_instruction(emit);
2971 }
2972
2973 return TRUE;
2974 }
2975
2976
2977 /**
2978 * Translate TGSI_TEXTURE_x to VGAPU10_RESOURCE_DIMENSION_x.
2979 */
2980 static unsigned
2981 tgsi_texture_to_resource_dimension(enum tgsi_texture_type target,
2982 boolean is_array)
2983 {
2984 switch (target) {
2985 case TGSI_TEXTURE_BUFFER:
2986 return VGPU10_RESOURCE_DIMENSION_BUFFER;
2987 case TGSI_TEXTURE_1D:
2988 return VGPU10_RESOURCE_DIMENSION_TEXTURE1D;
2989 case TGSI_TEXTURE_2D:
2990 case TGSI_TEXTURE_RECT:
2991 return VGPU10_RESOURCE_DIMENSION_TEXTURE2D;
2992 case TGSI_TEXTURE_3D:
2993 return VGPU10_RESOURCE_DIMENSION_TEXTURE3D;
2994 case TGSI_TEXTURE_CUBE:
2995 return VGPU10_RESOURCE_DIMENSION_TEXTURECUBE;
2996 case TGSI_TEXTURE_SHADOW1D:
2997 return VGPU10_RESOURCE_DIMENSION_TEXTURE1D;
2998 case TGSI_TEXTURE_SHADOW2D:
2999 case TGSI_TEXTURE_SHADOWRECT:
3000 return VGPU10_RESOURCE_DIMENSION_TEXTURE2D;
3001 case TGSI_TEXTURE_1D_ARRAY:
3002 case TGSI_TEXTURE_SHADOW1D_ARRAY:
3003 return is_array ? VGPU10_RESOURCE_DIMENSION_TEXTURE1DARRAY
3004 : VGPU10_RESOURCE_DIMENSION_TEXTURE1D;
3005 case TGSI_TEXTURE_2D_ARRAY:
3006 case TGSI_TEXTURE_SHADOW2D_ARRAY:
3007 return is_array ? VGPU10_RESOURCE_DIMENSION_TEXTURE2DARRAY
3008 : VGPU10_RESOURCE_DIMENSION_TEXTURE2D;
3009 case TGSI_TEXTURE_SHADOWCUBE:
3010 return VGPU10_RESOURCE_DIMENSION_TEXTURECUBE;
3011 case TGSI_TEXTURE_2D_MSAA:
3012 return VGPU10_RESOURCE_DIMENSION_TEXTURE2DMS;
3013 case TGSI_TEXTURE_2D_ARRAY_MSAA:
3014 return is_array ? VGPU10_RESOURCE_DIMENSION_TEXTURE2DMSARRAY
3015 : VGPU10_RESOURCE_DIMENSION_TEXTURE2DMS;
3016 case TGSI_TEXTURE_CUBE_ARRAY:
3017 return VGPU10_RESOURCE_DIMENSION_TEXTURECUBEARRAY;
3018 default:
3019 assert(!"Unexpected resource type");
3020 return VGPU10_RESOURCE_DIMENSION_TEXTURE2D;
3021 }
3022 }
3023
3024
3025 /**
3026 * Given a tgsi_return_type, return true iff it is an integer type.
3027 */
3028 static boolean
3029 is_integer_type(enum tgsi_return_type type)
3030 {
3031 switch (type) {
3032 case TGSI_RETURN_TYPE_SINT:
3033 case TGSI_RETURN_TYPE_UINT:
3034 return TRUE;
3035 case TGSI_RETURN_TYPE_FLOAT:
3036 case TGSI_RETURN_TYPE_UNORM:
3037 case TGSI_RETURN_TYPE_SNORM:
3038 return FALSE;
3039 case TGSI_RETURN_TYPE_COUNT:
3040 default:
3041 assert(!"is_integer_type: Unknown tgsi_return_type");
3042 return FALSE;
3043 }
3044 }
3045
3046
3047 /**
3048 * Emit declarations for resources.
3049 * XXX When we're sure that all TGSI shaders will be generated with
3050 * sampler view declarations (Ex: DCL SVIEW[n], 2D, UINT) we may
3051 * rework this code.
3052 */
3053 static boolean
3054 emit_resource_declarations(struct svga_shader_emitter_v10 *emit)
3055 {
3056 unsigned i;
3057
3058 /* Emit resource decl for each sampler */
3059 for (i = 0; i < emit->num_samplers; i++) {
3060 VGPU10OpcodeToken0 opcode0;
3061 VGPU10OperandToken0 operand0;
3062 VGPU10ResourceReturnTypeToken return_type;
3063 VGPU10_RESOURCE_RETURN_TYPE rt;
3064
3065 opcode0.value = 0;
3066 opcode0.opcodeType = VGPU10_OPCODE_DCL_RESOURCE;
3067 opcode0.resourceDimension =
3068 tgsi_texture_to_resource_dimension(emit->sampler_target[i],
3069 emit->key.tex[i].is_array);
3070 opcode0.sampleCount = emit->key.tex[i].num_samples;
3071 operand0.value = 0;
3072 operand0.numComponents = VGPU10_OPERAND_0_COMPONENT;
3073 operand0.operandType = VGPU10_OPERAND_TYPE_RESOURCE;
3074 operand0.indexDimension = VGPU10_OPERAND_INDEX_1D;
3075 operand0.index0Representation = VGPU10_OPERAND_INDEX_IMMEDIATE32;
3076
3077 #if 1
3078 /* convert TGSI_RETURN_TYPE_x to VGPU10_RETURN_TYPE_x */
3079 STATIC_ASSERT(VGPU10_RETURN_TYPE_UNORM == TGSI_RETURN_TYPE_UNORM + 1);
3080 STATIC_ASSERT(VGPU10_RETURN_TYPE_SNORM == TGSI_RETURN_TYPE_SNORM + 1);
3081 STATIC_ASSERT(VGPU10_RETURN_TYPE_SINT == TGSI_RETURN_TYPE_SINT + 1);
3082 STATIC_ASSERT(VGPU10_RETURN_TYPE_UINT == TGSI_RETURN_TYPE_UINT + 1);
3083 STATIC_ASSERT(VGPU10_RETURN_TYPE_FLOAT == TGSI_RETURN_TYPE_FLOAT + 1);
3084 assert(emit->sampler_return_type[i] <= TGSI_RETURN_TYPE_FLOAT);
3085 rt = emit->sampler_return_type[i] + 1;
3086 #else
3087 switch (emit->sampler_return_type[i]) {
3088 case TGSI_RETURN_TYPE_UNORM: rt = VGPU10_RETURN_TYPE_UNORM; break;
3089 case TGSI_RETURN_TYPE_SNORM: rt = VGPU10_RETURN_TYPE_SNORM; break;
3090 case TGSI_RETURN_TYPE_SINT: rt = VGPU10_RETURN_TYPE_SINT; break;
3091 case TGSI_RETURN_TYPE_UINT: rt = VGPU10_RETURN_TYPE_UINT; break;
3092 case TGSI_RETURN_TYPE_FLOAT: rt = VGPU10_RETURN_TYPE_FLOAT; break;
3093 case TGSI_RETURN_TYPE_COUNT:
3094 default:
3095 rt = VGPU10_RETURN_TYPE_FLOAT;
3096 assert(!"emit_resource_declarations: Unknown tgsi_return_type");
3097 }
3098 #endif
3099
3100 return_type.value = 0;
3101 return_type.component0 = rt;
3102 return_type.component1 = rt;
3103 return_type.component2 = rt;
3104 return_type.component3 = rt;
3105
3106 begin_emit_instruction(emit);
3107 emit_dword(emit, opcode0.value);
3108 emit_dword(emit, operand0.value);
3109 emit_dword(emit, i);
3110 emit_dword(emit, return_type.value);
3111 end_emit_instruction(emit);
3112 }
3113
3114 return TRUE;
3115 }
3116
3117 static void
3118 emit_instruction_op1(struct svga_shader_emitter_v10 *emit,
3119 VGPU10_OPCODE_TYPE opcode,
3120 const struct tgsi_full_dst_register *dst,
3121 const struct tgsi_full_src_register *src,
3122 boolean saturate)
3123 {
3124 begin_emit_instruction(emit);
3125 emit_opcode(emit, opcode, saturate);
3126 emit_dst_register(emit, dst);
3127 emit_src_register(emit, src);
3128 end_emit_instruction(emit);
3129 }
3130
3131 static void
3132 emit_instruction_op2(struct svga_shader_emitter_v10 *emit,
3133 VGPU10_OPCODE_TYPE opcode,
3134 const struct tgsi_full_dst_register *dst,
3135 const struct tgsi_full_src_register *src1,
3136 const struct tgsi_full_src_register *src2,
3137 boolean saturate)
3138 {
3139 begin_emit_instruction(emit);
3140 emit_opcode(emit, opcode, saturate);
3141 emit_dst_register(emit, dst);
3142 emit_src_register(emit, src1);
3143 emit_src_register(emit, src2);
3144 end_emit_instruction(emit);
3145 }
3146
3147 static void
3148 emit_instruction_op3(struct svga_shader_emitter_v10 *emit,
3149 VGPU10_OPCODE_TYPE opcode,
3150 const struct tgsi_full_dst_register *dst,
3151 const struct tgsi_full_src_register *src1,
3152 const struct tgsi_full_src_register *src2,
3153 const struct tgsi_full_src_register *src3,
3154 boolean saturate)
3155 {
3156 begin_emit_instruction(emit);
3157 emit_opcode(emit, opcode, saturate);
3158 emit_dst_register(emit, dst);
3159 emit_src_register(emit, src1);
3160 emit_src_register(emit, src2);
3161 emit_src_register(emit, src3);
3162 end_emit_instruction(emit);
3163 }
3164
3165 /**
3166 * Emit the actual clip distance instructions to be used for clipping
3167 * by copying the clip distance from the temporary registers to the
3168 * CLIPDIST registers written with the enabled planes mask.
3169 * Also copy the clip distance from the temporary to the clip distance
3170 * shadow copy register which will be referenced by the input shader
3171 */
3172 static void
3173 emit_clip_distance_instructions(struct svga_shader_emitter_v10 *emit)
3174 {
3175 struct tgsi_full_src_register tmp_clip_dist_src;
3176 struct tgsi_full_dst_register clip_dist_dst;
3177
3178 unsigned i;
3179 unsigned clip_plane_enable = emit->key.clip_plane_enable;
3180 unsigned clip_dist_tmp_index = emit->clip_dist_tmp_index;
3181 int num_written_clipdist = emit->info.num_written_clipdistance;
3182
3183 assert(emit->clip_dist_out_index != INVALID_INDEX);
3184 assert(emit->clip_dist_tmp_index != INVALID_INDEX);
3185
3186 /**
3187 * Temporary reset the temporary clip dist register index so
3188 * that the copy to the real clip dist register will not
3189 * attempt to copy to the temporary register again
3190 */
3191 emit->clip_dist_tmp_index = INVALID_INDEX;
3192
3193 for (i = 0; i < 2 && num_written_clipdist > 0; i++, num_written_clipdist-=4) {
3194
3195 tmp_clip_dist_src = make_src_temp_reg(clip_dist_tmp_index + i);
3196
3197 /**
3198 * copy to the shadow copy for use by varying variable and
3199 * stream output. All clip distances
3200 * will be written regardless of the enabled clipping planes.
3201 */
3202 clip_dist_dst = make_dst_reg(TGSI_FILE_OUTPUT,
3203 emit->clip_dist_so_index + i);
3204
3205 /* MOV clip_dist_so, tmp_clip_dist */
3206 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &clip_dist_dst,
3207 &tmp_clip_dist_src, FALSE);
3208
3209 /**
3210 * copy those clip distances to enabled clipping planes
3211 * to CLIPDIST registers for clipping
3212 */
3213 if (clip_plane_enable & 0xf) {
3214 clip_dist_dst = make_dst_reg(TGSI_FILE_OUTPUT,
3215 emit->clip_dist_out_index + i);
3216 clip_dist_dst = writemask_dst(&clip_dist_dst, clip_plane_enable & 0xf);
3217
3218 /* MOV CLIPDIST, tmp_clip_dist */
3219 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &clip_dist_dst,
3220 &tmp_clip_dist_src, FALSE);
3221 }
3222 /* four clip planes per clip register */
3223 clip_plane_enable >>= 4;
3224 }
3225 /**
3226 * set the temporary clip dist register index back to the
3227 * temporary index for the next vertex
3228 */
3229 emit->clip_dist_tmp_index = clip_dist_tmp_index;
3230 }
3231
3232 /* Declare clip distance output registers for user-defined clip planes
3233 * or the TGSI_CLIPVERTEX output.
3234 */
3235 static void
3236 emit_clip_distance_declarations(struct svga_shader_emitter_v10 *emit)
3237 {
3238 unsigned num_clip_planes = util_bitcount(emit->key.clip_plane_enable);
3239 unsigned index = emit->num_outputs;
3240 unsigned plane_mask;
3241
3242 assert(emit->unit == PIPE_SHADER_VERTEX ||
3243 emit->unit == PIPE_SHADER_GEOMETRY);
3244 assert(num_clip_planes <= 8);
3245
3246 if (emit->clip_mode != CLIP_LEGACY &&
3247 emit->clip_mode != CLIP_VERTEX) {
3248 return;
3249 }
3250
3251 if (num_clip_planes == 0)
3252 return;
3253
3254 /* Declare one or two clip output registers. The number of components
3255 * in the mask reflects the number of clip planes. For example, if 5
3256 * clip planes are needed, we'll declare outputs similar to:
3257 * dcl_output_siv o2.xyzw, clip_distance
3258 * dcl_output_siv o3.x, clip_distance
3259 */
3260 emit->clip_dist_out_index = index; /* save the starting clip dist reg index */
3261
3262 plane_mask = (1 << num_clip_planes) - 1;
3263 if (plane_mask & 0xf) {
3264 unsigned cmask = plane_mask & VGPU10_OPERAND_4_COMPONENT_MASK_ALL;
3265 emit_output_declaration(emit, VGPU10_OPCODE_DCL_OUTPUT_SIV, index,
3266 VGPU10_NAME_CLIP_DISTANCE, cmask);
3267 emit->num_outputs++;
3268 }
3269 if (plane_mask & 0xf0) {
3270 unsigned cmask = (plane_mask >> 4) & VGPU10_OPERAND_4_COMPONENT_MASK_ALL;
3271 emit_output_declaration(emit, VGPU10_OPCODE_DCL_OUTPUT_SIV, index + 1,
3272 VGPU10_NAME_CLIP_DISTANCE, cmask);
3273 emit->num_outputs++;
3274 }
3275 }
3276
3277
3278 /**
3279 * Emit the instructions for writing to the clip distance registers
3280 * to handle legacy/automatic clip planes.
3281 * For each clip plane, the distance is the dot product of the vertex
3282 * position (found in TEMP[vpos_tmp_index]) and the clip plane coefficients.
3283 * This is not used when the shader has an explicit CLIPVERTEX or CLIPDISTANCE
3284 * output registers already declared.
3285 */
3286 static void
3287 emit_clip_distance_from_vpos(struct svga_shader_emitter_v10 *emit,
3288 unsigned vpos_tmp_index)
3289 {
3290 unsigned i, num_clip_planes = util_bitcount(emit->key.clip_plane_enable);
3291
3292 assert(emit->clip_mode == CLIP_LEGACY);
3293 assert(num_clip_planes <= 8);
3294
3295 assert(emit->unit == PIPE_SHADER_VERTEX ||
3296 emit->unit == PIPE_SHADER_GEOMETRY);
3297
3298 for (i = 0; i < num_clip_planes; i++) {
3299 struct tgsi_full_dst_register dst;
3300 struct tgsi_full_src_register plane_src, vpos_src;
3301 unsigned reg_index = emit->clip_dist_out_index + i / 4;
3302 unsigned comp = i % 4;
3303 unsigned writemask = VGPU10_OPERAND_4_COMPONENT_MASK_X << comp;
3304
3305 /* create dst, src regs */
3306 dst = make_dst_reg(TGSI_FILE_OUTPUT, reg_index);
3307 dst = writemask_dst(&dst, writemask);
3308
3309 plane_src = make_src_const_reg(emit->clip_plane_const[i]);
3310 vpos_src = make_src_temp_reg(vpos_tmp_index);
3311
3312 /* DP4 clip_dist, plane, vpos */
3313 emit_instruction_op2(emit, VGPU10_OPCODE_DP4, &dst,
3314 &plane_src, &vpos_src, FALSE);
3315 }
3316 }
3317
3318
3319 /**
3320 * Emit the instructions for computing the clip distance results from
3321 * the clip vertex temporary.
3322 * For each clip plane, the distance is the dot product of the clip vertex
3323 * position (found in a temp reg) and the clip plane coefficients.
3324 */
3325 static void
3326 emit_clip_vertex_instructions(struct svga_shader_emitter_v10 *emit)
3327 {
3328 const unsigned num_clip = util_bitcount(emit->key.clip_plane_enable);
3329 unsigned i;
3330 struct tgsi_full_dst_register dst;
3331 struct tgsi_full_src_register clipvert_src;
3332 const unsigned clip_vertex_tmp = emit->clip_vertex_tmp_index;
3333
3334 assert(emit->unit == PIPE_SHADER_VERTEX ||
3335 emit->unit == PIPE_SHADER_GEOMETRY);
3336
3337 assert(emit->clip_mode == CLIP_VERTEX);
3338
3339 clipvert_src = make_src_temp_reg(clip_vertex_tmp);
3340
3341 for (i = 0; i < num_clip; i++) {
3342 struct tgsi_full_src_register plane_src;
3343 unsigned reg_index = emit->clip_dist_out_index + i / 4;
3344 unsigned comp = i % 4;
3345 unsigned writemask = VGPU10_OPERAND_4_COMPONENT_MASK_X << comp;
3346
3347 /* create dst, src regs */
3348 dst = make_dst_reg(TGSI_FILE_OUTPUT, reg_index);
3349 dst = writemask_dst(&dst, writemask);
3350
3351 plane_src = make_src_const_reg(emit->clip_plane_const[i]);
3352
3353 /* DP4 clip_dist, plane, vpos */
3354 emit_instruction_op2(emit, VGPU10_OPCODE_DP4, &dst,
3355 &plane_src, &clipvert_src, FALSE);
3356 }
3357
3358 /* copy temporary clip vertex register to the clip vertex register */
3359
3360 assert(emit->clip_vertex_out_index != INVALID_INDEX);
3361
3362 /**
3363 * temporary reset the temporary clip vertex register index so
3364 * that copy to the clip vertex register will not attempt
3365 * to copy to the temporary register again
3366 */
3367 emit->clip_vertex_tmp_index = INVALID_INDEX;
3368
3369 /* MOV clip_vertex, clip_vertex_tmp */
3370 dst = make_dst_reg(TGSI_FILE_OUTPUT, emit->clip_vertex_out_index);
3371 emit_instruction_op1(emit, VGPU10_OPCODE_MOV,
3372 &dst, &clipvert_src, FALSE);
3373
3374 /**
3375 * set the temporary clip vertex register index back to the
3376 * temporary index for the next vertex
3377 */
3378 emit->clip_vertex_tmp_index = clip_vertex_tmp;
3379 }
3380
3381 /**
3382 * Emit code to convert RGBA to BGRA
3383 */
3384 static void
3385 emit_swap_r_b(struct svga_shader_emitter_v10 *emit,
3386 const struct tgsi_full_dst_register *dst,
3387 const struct tgsi_full_src_register *src)
3388 {
3389 struct tgsi_full_src_register bgra_src =
3390 swizzle_src(src, TGSI_SWIZZLE_Z, TGSI_SWIZZLE_Y, TGSI_SWIZZLE_X, TGSI_SWIZZLE_W);
3391
3392 begin_emit_instruction(emit);
3393 emit_opcode(emit, VGPU10_OPCODE_MOV, FALSE);
3394 emit_dst_register(emit, dst);
3395 emit_src_register(emit, &bgra_src);
3396 end_emit_instruction(emit);
3397 }
3398
3399
3400 /** Convert from 10_10_10_2 normalized to 10_10_10_2_snorm */
3401 static void
3402 emit_puint_to_snorm(struct svga_shader_emitter_v10 *emit,
3403 const struct tgsi_full_dst_register *dst,
3404 const struct tgsi_full_src_register *src)
3405 {
3406 struct tgsi_full_src_register half = make_immediate_reg_float(emit, 0.5f);
3407 struct tgsi_full_src_register two =
3408 make_immediate_reg_float4(emit, 2.0f, 2.0f, 2.0f, 3.0f);
3409 struct tgsi_full_src_register neg_two =
3410 make_immediate_reg_float4(emit, -2.0f, -2.0f, -2.0f, -1.66666f);
3411
3412 unsigned val_tmp = get_temp_index(emit);
3413 struct tgsi_full_dst_register val_dst = make_dst_temp_reg(val_tmp);
3414 struct tgsi_full_src_register val_src = make_src_temp_reg(val_tmp);
3415
3416 unsigned bias_tmp = get_temp_index(emit);
3417 struct tgsi_full_dst_register bias_dst = make_dst_temp_reg(bias_tmp);
3418 struct tgsi_full_src_register bias_src = make_src_temp_reg(bias_tmp);
3419
3420 /* val = src * 2.0 */
3421 emit_instruction_op2(emit, VGPU10_OPCODE_MUL, &val_dst,
3422 src, &two, FALSE);
3423
3424 /* bias = src > 0.5 */
3425 emit_instruction_op2(emit, VGPU10_OPCODE_GE, &bias_dst,
3426 src, &half, FALSE);
3427
3428 /* bias = bias & -2.0 */
3429 emit_instruction_op2(emit, VGPU10_OPCODE_AND, &bias_dst,
3430 &bias_src, &neg_two, FALSE);
3431
3432 /* dst = val + bias */
3433 emit_instruction_op2(emit, VGPU10_OPCODE_ADD, dst,
3434 &val_src, &bias_src, FALSE);
3435
3436 free_temp_indexes(emit);
3437 }
3438
3439
3440 /** Convert from 10_10_10_2_unorm to 10_10_10_2_uscaled */
3441 static void
3442 emit_puint_to_uscaled(struct svga_shader_emitter_v10 *emit,
3443 const struct tgsi_full_dst_register *dst,
3444 const struct tgsi_full_src_register *src)
3445 {
3446 struct tgsi_full_src_register scale =
3447 make_immediate_reg_float4(emit, 1023.0f, 1023.0f, 1023.0f, 3.0f);
3448
3449 /* dst = src * scale */
3450 emit_instruction_op2(emit, VGPU10_OPCODE_MUL, dst, src, &scale, FALSE);
3451 }
3452
3453
3454 /** Convert from R32_UINT to 10_10_10_2_sscaled */
3455 static void
3456 emit_puint_to_sscaled(struct svga_shader_emitter_v10 *emit,
3457 const struct tgsi_full_dst_register *dst,
3458 const struct tgsi_full_src_register *src)
3459 {
3460 struct tgsi_full_src_register lshift =
3461 make_immediate_reg_int4(emit, 22, 12, 2, 0);
3462 struct tgsi_full_src_register rshift =
3463 make_immediate_reg_int4(emit, 22, 22, 22, 30);
3464
3465 struct tgsi_full_src_register src_xxxx = scalar_src(src, TGSI_SWIZZLE_X);
3466
3467 unsigned tmp = get_temp_index(emit);
3468 struct tgsi_full_dst_register tmp_dst = make_dst_temp_reg(tmp);
3469 struct tgsi_full_src_register tmp_src = make_src_temp_reg(tmp);
3470
3471 /*
3472 * r = (pixel << 22) >> 22; # signed int in [511, -512]
3473 * g = (pixel << 12) >> 22; # signed int in [511, -512]
3474 * b = (pixel << 2) >> 22; # signed int in [511, -512]
3475 * a = (pixel << 0) >> 30; # signed int in [1, -2]
3476 * dst = i_to_f(r,g,b,a); # convert to float
3477 */
3478 emit_instruction_op2(emit, VGPU10_OPCODE_ISHL, &tmp_dst,
3479 &src_xxxx, &lshift, FALSE);
3480 emit_instruction_op2(emit, VGPU10_OPCODE_ISHR, &tmp_dst,
3481 &tmp_src, &rshift, FALSE);
3482 emit_instruction_op1(emit, VGPU10_OPCODE_ITOF, dst, &tmp_src, FALSE);
3483
3484 free_temp_indexes(emit);
3485 }
3486
3487
3488 /**
3489 * Emit code for TGSI_OPCODE_ARL or TGSI_OPCODE_UARL instruction.
3490 */
3491 static boolean
3492 emit_arl_uarl(struct svga_shader_emitter_v10 *emit,
3493 const struct tgsi_full_instruction *inst)
3494 {
3495 unsigned index = inst->Dst[0].Register.Index;
3496 struct tgsi_full_dst_register dst;
3497 VGPU10_OPCODE_TYPE opcode;
3498
3499 assert(index < MAX_VGPU10_ADDR_REGS);
3500 dst = make_dst_temp_reg(emit->address_reg_index[index]);
3501
3502 /* ARL dst, s0
3503 * Translates into:
3504 * FTOI address_tmp, s0
3505 *
3506 * UARL dst, s0
3507 * Translates into:
3508 * MOV address_tmp, s0
3509 */
3510 if (inst->Instruction.Opcode == TGSI_OPCODE_ARL)
3511 opcode = VGPU10_OPCODE_FTOI;
3512 else
3513 opcode = VGPU10_OPCODE_MOV;
3514
3515 emit_instruction_op1(emit, opcode, &dst, &inst->Src[0], FALSE);
3516
3517 return TRUE;
3518 }
3519
3520
3521 /**
3522 * Emit code for TGSI_OPCODE_CAL instruction.
3523 */
3524 static boolean
3525 emit_cal(struct svga_shader_emitter_v10 *emit,
3526 const struct tgsi_full_instruction *inst)
3527 {
3528 unsigned label = inst->Label.Label;
3529 VGPU10OperandToken0 operand;
3530 operand.value = 0;
3531 operand.operandType = VGPU10_OPERAND_TYPE_LABEL;
3532
3533 begin_emit_instruction(emit);
3534 emit_dword(emit, operand.value);
3535 emit_dword(emit, label);
3536 end_emit_instruction(emit);
3537
3538 return TRUE;
3539 }
3540
3541
3542 /**
3543 * Emit code for TGSI_OPCODE_IABS instruction.
3544 */
3545 static boolean
3546 emit_iabs(struct svga_shader_emitter_v10 *emit,
3547 const struct tgsi_full_instruction *inst)
3548 {
3549 /* dst.x = (src0.x < 0) ? -src0.x : src0.x
3550 * dst.y = (src0.y < 0) ? -src0.y : src0.y
3551 * dst.z = (src0.z < 0) ? -src0.z : src0.z
3552 * dst.w = (src0.w < 0) ? -src0.w : src0.w
3553 *
3554 * Translates into
3555 * IMAX dst, src, neg(src)
3556 */
3557 struct tgsi_full_src_register neg_src = negate_src(&inst->Src[0]);
3558 emit_instruction_op2(emit, VGPU10_OPCODE_IMAX, &inst->Dst[0],
3559 &inst->Src[0], &neg_src, FALSE);
3560
3561 return TRUE;
3562 }
3563
3564
3565 /**
3566 * Emit code for TGSI_OPCODE_CMP instruction.
3567 */
3568 static boolean
3569 emit_cmp(struct svga_shader_emitter_v10 *emit,
3570 const struct tgsi_full_instruction *inst)
3571 {
3572 /* dst.x = (src0.x < 0) ? src1.x : src2.x
3573 * dst.y = (src0.y < 0) ? src1.y : src2.y
3574 * dst.z = (src0.z < 0) ? src1.z : src2.z
3575 * dst.w = (src0.w < 0) ? src1.w : src2.w
3576 *
3577 * Translates into
3578 * LT tmp, src0, 0.0
3579 * MOVC dst, tmp, src1, src2
3580 */
3581 struct tgsi_full_src_register zero = make_immediate_reg_float(emit, 0.0f);
3582 unsigned tmp = get_temp_index(emit);
3583 struct tgsi_full_src_register tmp_src = make_src_temp_reg(tmp);
3584 struct tgsi_full_dst_register tmp_dst = make_dst_temp_reg(tmp);
3585
3586 emit_instruction_op2(emit, VGPU10_OPCODE_LT, &tmp_dst,
3587 &inst->Src[0], &zero, FALSE);
3588 emit_instruction_op3(emit, VGPU10_OPCODE_MOVC, &inst->Dst[0],
3589 &tmp_src, &inst->Src[1], &inst->Src[2],
3590 inst->Instruction.Saturate);
3591
3592 free_temp_indexes(emit);
3593
3594 return TRUE;
3595 }
3596
3597
3598 /**
3599 * Emit code for TGSI_OPCODE_DST instruction.
3600 */
3601 static boolean
3602 emit_dst(struct svga_shader_emitter_v10 *emit,
3603 const struct tgsi_full_instruction *inst)
3604 {
3605 /*
3606 * dst.x = 1
3607 * dst.y = src0.y * src1.y
3608 * dst.z = src0.z
3609 * dst.w = src1.w
3610 */
3611
3612 struct tgsi_full_src_register s0_yyyy =
3613 scalar_src(&inst->Src[0], TGSI_SWIZZLE_Y);
3614 struct tgsi_full_src_register s0_zzzz =
3615 scalar_src(&inst->Src[0], TGSI_SWIZZLE_Z);
3616 struct tgsi_full_src_register s1_yyyy =
3617 scalar_src(&inst->Src[1], TGSI_SWIZZLE_Y);
3618 struct tgsi_full_src_register s1_wwww =
3619 scalar_src(&inst->Src[1], TGSI_SWIZZLE_W);
3620
3621 /*
3622 * If dst and either src0 and src1 are the same we need
3623 * to create a temporary for it and insert a extra move.
3624 */
3625 unsigned tmp_move = get_temp_index(emit);
3626 struct tgsi_full_src_register move_src = make_src_temp_reg(tmp_move);
3627 struct tgsi_full_dst_register move_dst = make_dst_temp_reg(tmp_move);
3628
3629 /* MOV dst.x, 1.0 */
3630 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3631 struct tgsi_full_dst_register dst_x =
3632 writemask_dst(&move_dst, TGSI_WRITEMASK_X);
3633 struct tgsi_full_src_register one = make_immediate_reg_float(emit, 1.0f);
3634
3635 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &dst_x, &one, FALSE);
3636 }
3637
3638 /* MUL dst.y, s0.y, s1.y */
3639 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3640 struct tgsi_full_dst_register dst_y =
3641 writemask_dst(&move_dst, TGSI_WRITEMASK_Y);
3642
3643 emit_instruction_op2(emit, VGPU10_OPCODE_MUL, &dst_y, &s0_yyyy,
3644 &s1_yyyy, inst->Instruction.Saturate);
3645 }
3646
3647 /* MOV dst.z, s0.z */
3648 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3649 struct tgsi_full_dst_register dst_z =
3650 writemask_dst(&move_dst, TGSI_WRITEMASK_Z);
3651
3652 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &dst_z, &s0_zzzz,
3653 inst->Instruction.Saturate);
3654 }
3655
3656 /* MOV dst.w, s1.w */
3657 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3658 struct tgsi_full_dst_register dst_w =
3659 writemask_dst(&move_dst, TGSI_WRITEMASK_W);
3660
3661 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &dst_w, &s1_wwww,
3662 inst->Instruction.Saturate);
3663 }
3664
3665 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &inst->Dst[0], &move_src,
3666 FALSE);
3667 free_temp_indexes(emit);
3668
3669 return TRUE;
3670 }
3671
3672
3673
3674 /**
3675 * Emit code for TGSI_OPCODE_ENDPRIM (GS only)
3676 */
3677 static boolean
3678 emit_endprim(struct svga_shader_emitter_v10 *emit,
3679 const struct tgsi_full_instruction *inst)
3680 {
3681 assert(emit->unit == PIPE_SHADER_GEOMETRY);
3682
3683 /* We can't use emit_simple() because the TGSI instruction has one
3684 * operand (vertex stream number) which we must ignore for VGPU10.
3685 */
3686 begin_emit_instruction(emit);
3687 emit_opcode(emit, VGPU10_OPCODE_CUT, FALSE);
3688 end_emit_instruction(emit);
3689 return TRUE;
3690 }
3691
3692
3693 /**
3694 * Emit code for TGSI_OPCODE_EX2 (2^x) instruction.
3695 */
3696 static boolean
3697 emit_ex2(struct svga_shader_emitter_v10 *emit,
3698 const struct tgsi_full_instruction *inst)
3699 {
3700 /* Note that TGSI_OPCODE_EX2 computes only one value from src.x
3701 * while VGPU10 computes four values.
3702 *
3703 * dst = EX2(src):
3704 * dst.xyzw = 2.0 ^ src.x
3705 */
3706
3707 struct tgsi_full_src_register src_xxxx =
3708 swizzle_src(&inst->Src[0], TGSI_SWIZZLE_X, TGSI_SWIZZLE_X,
3709 TGSI_SWIZZLE_X, TGSI_SWIZZLE_X);
3710
3711 /* EXP tmp, s0.xxxx */
3712 emit_instruction_op1(emit, VGPU10_OPCODE_EXP, &inst->Dst[0], &src_xxxx,
3713 inst->Instruction.Saturate);
3714
3715 return TRUE;
3716 }
3717
3718
3719 /**
3720 * Emit code for TGSI_OPCODE_EXP instruction.
3721 */
3722 static boolean
3723 emit_exp(struct svga_shader_emitter_v10 *emit,
3724 const struct tgsi_full_instruction *inst)
3725 {
3726 /*
3727 * dst.x = 2 ^ floor(s0.x)
3728 * dst.y = s0.x - floor(s0.x)
3729 * dst.z = 2 ^ s0.x
3730 * dst.w = 1.0
3731 */
3732
3733 struct tgsi_full_src_register src_xxxx =
3734 scalar_src(&inst->Src[0], TGSI_SWIZZLE_X);
3735 unsigned tmp = get_temp_index(emit);
3736 struct tgsi_full_src_register tmp_src = make_src_temp_reg(tmp);
3737 struct tgsi_full_dst_register tmp_dst = make_dst_temp_reg(tmp);
3738
3739 /*
3740 * If dst and src are the same we need to create
3741 * a temporary for it and insert a extra move.
3742 */
3743 unsigned tmp_move = get_temp_index(emit);
3744 struct tgsi_full_src_register move_src = make_src_temp_reg(tmp_move);
3745 struct tgsi_full_dst_register move_dst = make_dst_temp_reg(tmp_move);
3746
3747 /* only use X component of temp reg */
3748 tmp_dst = writemask_dst(&tmp_dst, TGSI_WRITEMASK_X);
3749 tmp_src = scalar_src(&tmp_src, TGSI_SWIZZLE_X);
3750
3751 /* ROUND_NI tmp.x, s0.x */
3752 emit_instruction_op1(emit, VGPU10_OPCODE_ROUND_NI, &tmp_dst,
3753 &src_xxxx, FALSE); /* round to -infinity */
3754
3755 /* EXP dst.x, tmp.x */
3756 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3757 struct tgsi_full_dst_register dst_x =
3758 writemask_dst(&move_dst, TGSI_WRITEMASK_X);
3759
3760 emit_instruction_op1(emit, VGPU10_OPCODE_EXP, &dst_x, &tmp_src,
3761 inst->Instruction.Saturate);
3762 }
3763
3764 /* ADD dst.y, s0.x, -tmp */
3765 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3766 struct tgsi_full_dst_register dst_y =
3767 writemask_dst(&move_dst, TGSI_WRITEMASK_Y);
3768 struct tgsi_full_src_register neg_tmp_src = negate_src(&tmp_src);
3769
3770 emit_instruction_op2(emit, VGPU10_OPCODE_ADD, &dst_y, &src_xxxx,
3771 &neg_tmp_src, inst->Instruction.Saturate);
3772 }
3773
3774 /* EXP dst.z, s0.x */
3775 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3776 struct tgsi_full_dst_register dst_z =
3777 writemask_dst(&move_dst, TGSI_WRITEMASK_Z);
3778
3779 emit_instruction_op1(emit, VGPU10_OPCODE_EXP, &dst_z, &src_xxxx,
3780 inst->Instruction.Saturate);
3781 }
3782
3783 /* MOV dst.w, 1.0 */
3784 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3785 struct tgsi_full_dst_register dst_w =
3786 writemask_dst(&move_dst, TGSI_WRITEMASK_W);
3787 struct tgsi_full_src_register one = make_immediate_reg_float(emit, 1.0f);
3788
3789 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &dst_w, &one,
3790 FALSE);
3791 }
3792
3793 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &inst->Dst[0], &move_src,
3794 FALSE);
3795
3796 free_temp_indexes(emit);
3797
3798 return TRUE;
3799 }
3800
3801
3802 /**
3803 * Emit code for TGSI_OPCODE_IF instruction.
3804 */
3805 static boolean
3806 emit_if(struct svga_shader_emitter_v10 *emit,
3807 const struct tgsi_full_instruction *inst)
3808 {
3809 VGPU10OpcodeToken0 opcode0;
3810
3811 /* The src register should be a scalar */
3812 assert(inst->Src[0].Register.SwizzleX == inst->Src[0].Register.SwizzleY &&
3813 inst->Src[0].Register.SwizzleX == inst->Src[0].Register.SwizzleZ &&
3814 inst->Src[0].Register.SwizzleX == inst->Src[0].Register.SwizzleW);
3815
3816 /* The only special thing here is that we need to set the
3817 * VGPU10_INSTRUCTION_TEST_NONZERO flag since we want to test if
3818 * src.x is non-zero.
3819 */
3820 opcode0.value = 0;
3821 opcode0.opcodeType = VGPU10_OPCODE_IF;
3822 opcode0.testBoolean = VGPU10_INSTRUCTION_TEST_NONZERO;
3823
3824 begin_emit_instruction(emit);
3825 emit_dword(emit, opcode0.value);
3826 emit_src_register(emit, &inst->Src[0]);
3827 end_emit_instruction(emit);
3828
3829 return TRUE;
3830 }
3831
3832
3833 /**
3834 * Emit code for TGSI_OPCODE_KILL_IF instruction (kill fragment if any of
3835 * the register components are negative).
3836 */
3837 static boolean
3838 emit_kill_if(struct svga_shader_emitter_v10 *emit,
3839 const struct tgsi_full_instruction *inst)
3840 {
3841 unsigned tmp = get_temp_index(emit);
3842 struct tgsi_full_src_register tmp_src = make_src_temp_reg(tmp);
3843 struct tgsi_full_dst_register tmp_dst = make_dst_temp_reg(tmp);
3844
3845 struct tgsi_full_src_register zero = make_immediate_reg_float(emit, 0.0f);
3846
3847 struct tgsi_full_dst_register tmp_dst_x =
3848 writemask_dst(&tmp_dst, TGSI_WRITEMASK_X);
3849 struct tgsi_full_src_register tmp_src_xxxx =
3850 scalar_src(&tmp_src, TGSI_SWIZZLE_X);
3851
3852 /* tmp = src[0] < 0.0 */
3853 emit_instruction_op2(emit, VGPU10_OPCODE_LT, &tmp_dst, &inst->Src[0],
3854 &zero, FALSE);
3855
3856 if (!same_swizzle_terms(&inst->Src[0])) {
3857 /* If the swizzle is not XXXX, YYYY, ZZZZ or WWWW we need to
3858 * logically OR the swizzle terms. Most uses of KILL_IF only
3859 * test one channel so it's good to avoid these extra steps.
3860 */
3861 struct tgsi_full_src_register tmp_src_yyyy =
3862 scalar_src(&tmp_src, TGSI_SWIZZLE_Y);
3863 struct tgsi_full_src_register tmp_src_zzzz =
3864 scalar_src(&tmp_src, TGSI_SWIZZLE_Z);
3865 struct tgsi_full_src_register tmp_src_wwww =
3866 scalar_src(&tmp_src, TGSI_SWIZZLE_W);
3867
3868 emit_instruction_op2(emit, VGPU10_OPCODE_OR, &tmp_dst_x, &tmp_src_xxxx,
3869 &tmp_src_yyyy, FALSE);
3870 emit_instruction_op2(emit, VGPU10_OPCODE_OR, &tmp_dst_x, &tmp_src_xxxx,
3871 &tmp_src_zzzz, FALSE);
3872 emit_instruction_op2(emit, VGPU10_OPCODE_OR, &tmp_dst_x, &tmp_src_xxxx,
3873 &tmp_src_wwww, FALSE);
3874 }
3875
3876 begin_emit_instruction(emit);
3877 emit_discard_opcode(emit, TRUE); /* discard if src0.x is non-zero */
3878 emit_src_register(emit, &tmp_src_xxxx);
3879 end_emit_instruction(emit);
3880
3881 free_temp_indexes(emit);
3882
3883 return TRUE;
3884 }
3885
3886
3887 /**
3888 * Emit code for TGSI_OPCODE_KILL instruction (unconditional discard).
3889 */
3890 static boolean
3891 emit_kill(struct svga_shader_emitter_v10 *emit,
3892 const struct tgsi_full_instruction *inst)
3893 {
3894 struct tgsi_full_src_register zero = make_immediate_reg_float(emit, 0.0f);
3895
3896 /* DISCARD if 0.0 is zero */
3897 begin_emit_instruction(emit);
3898 emit_discard_opcode(emit, FALSE);
3899 emit_src_register(emit, &zero);
3900 end_emit_instruction(emit);
3901
3902 return TRUE;
3903 }
3904
3905
3906 /**
3907 * Emit code for TGSI_OPCODE_LG2 instruction.
3908 */
3909 static boolean
3910 emit_lg2(struct svga_shader_emitter_v10 *emit,
3911 const struct tgsi_full_instruction *inst)
3912 {
3913 /* Note that TGSI_OPCODE_LG2 computes only one value from src.x
3914 * while VGPU10 computes four values.
3915 *
3916 * dst = LG2(src):
3917 * dst.xyzw = log2(src.x)
3918 */
3919
3920 struct tgsi_full_src_register src_xxxx =
3921 swizzle_src(&inst->Src[0], TGSI_SWIZZLE_X, TGSI_SWIZZLE_X,
3922 TGSI_SWIZZLE_X, TGSI_SWIZZLE_X);
3923
3924 /* LOG tmp, s0.xxxx */
3925 emit_instruction_op1(emit, VGPU10_OPCODE_LOG, &inst->Dst[0], &src_xxxx,
3926 inst->Instruction.Saturate);
3927
3928 return TRUE;
3929 }
3930
3931
3932 /**
3933 * Emit code for TGSI_OPCODE_LIT instruction.
3934 */
3935 static boolean
3936 emit_lit(struct svga_shader_emitter_v10 *emit,
3937 const struct tgsi_full_instruction *inst)
3938 {
3939 struct tgsi_full_src_register one = make_immediate_reg_float(emit, 1.0f);
3940
3941 /*
3942 * If dst and src are the same we need to create
3943 * a temporary for it and insert a extra move.
3944 */
3945 unsigned tmp_move = get_temp_index(emit);
3946 struct tgsi_full_src_register move_src = make_src_temp_reg(tmp_move);
3947 struct tgsi_full_dst_register move_dst = make_dst_temp_reg(tmp_move);
3948
3949 /*
3950 * dst.x = 1
3951 * dst.y = max(src.x, 0)
3952 * dst.z = (src.x > 0) ? max(src.y, 0)^{clamp(src.w, -128, 128))} : 0
3953 * dst.w = 1
3954 */
3955
3956 /* MOV dst.x, 1.0 */
3957 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3958 struct tgsi_full_dst_register dst_x =
3959 writemask_dst(&move_dst, TGSI_WRITEMASK_X);
3960 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &dst_x, &one, FALSE);
3961 }
3962
3963 /* MOV dst.w, 1.0 */
3964 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3965 struct tgsi_full_dst_register dst_w =
3966 writemask_dst(&move_dst, TGSI_WRITEMASK_W);
3967 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &dst_w, &one, FALSE);
3968 }
3969
3970 /* MAX dst.y, src.x, 0.0 */
3971 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3972 struct tgsi_full_dst_register dst_y =
3973 writemask_dst(&move_dst, TGSI_WRITEMASK_Y);
3974 struct tgsi_full_src_register zero =
3975 make_immediate_reg_float(emit, 0.0f);
3976 struct tgsi_full_src_register src_xxxx =
3977 swizzle_src(&inst->Src[0], TGSI_SWIZZLE_X, TGSI_SWIZZLE_X,
3978 TGSI_SWIZZLE_X, TGSI_SWIZZLE_X);
3979
3980 emit_instruction_op2(emit, VGPU10_OPCODE_MAX, &dst_y, &src_xxxx,
3981 &zero, inst->Instruction.Saturate);
3982 }
3983
3984 /*
3985 * tmp1 = clamp(src.w, -128, 128);
3986 * MAX tmp1, src.w, -128
3987 * MIN tmp1, tmp1, 128
3988 *
3989 * tmp2 = max(tmp2, 0);
3990 * MAX tmp2, src.y, 0
3991 *
3992 * tmp1 = pow(tmp2, tmp1);
3993 * LOG tmp2, tmp2
3994 * MUL tmp1, tmp2, tmp1
3995 * EXP tmp1, tmp1
3996 *
3997 * tmp1 = (src.w == 0) ? 1 : tmp1;
3998 * EQ tmp2, 0, src.w
3999 * MOVC tmp1, tmp2, 1.0, tmp1
4000 *
4001 * dst.z = (0 < src.x) ? tmp1 : 0;
4002 * LT tmp2, 0, src.x
4003 * MOVC dst.z, tmp2, tmp1, 0.0
4004 */
4005 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
4006 struct tgsi_full_dst_register dst_z =
4007 writemask_dst(&move_dst, TGSI_WRITEMASK_Z);
4008
4009 unsigned tmp1 = get_temp_index(emit);
4010 struct tgsi_full_src_register tmp1_src = make_src_temp_reg(tmp1);
4011 struct tgsi_full_dst_register tmp1_dst = make_dst_temp_reg(tmp1);
4012 unsigned tmp2 = get_temp_index(emit);
4013 struct tgsi_full_src_register tmp2_src = make_src_temp_reg(tmp2);
4014 struct tgsi_full_dst_register tmp2_dst = make_dst_temp_reg(tmp2);
4015
4016 struct tgsi_full_src_register src_xxxx =
4017 scalar_src(&inst->Src[0], TGSI_SWIZZLE_X);
4018 struct tgsi_full_src_register src_yyyy =
4019 scalar_src(&inst->Src[0], TGSI_SWIZZLE_Y);
4020 struct tgsi_full_src_register src_wwww =
4021 scalar_src(&inst->Src[0], TGSI_SWIZZLE_W);
4022
4023 struct tgsi_full_src_register zero =
4024 make_immediate_reg_float(emit, 0.0f);
4025 struct tgsi_full_src_register lowerbound =
4026 make_immediate_reg_float(emit, -128.0f);
4027 struct tgsi_full_src_register upperbound =
4028 make_immediate_reg_float(emit, 128.0f);
4029
4030 emit_instruction_op2(emit, VGPU10_OPCODE_MAX, &tmp1_dst, &src_wwww,
4031 &lowerbound, FALSE);
4032 emit_instruction_op2(emit, VGPU10_OPCODE_MIN, &tmp1_dst, &tmp1_src,
4033 &upperbound, FALSE);
4034 emit_instruction_op2(emit, VGPU10_OPCODE_MAX, &tmp2_dst, &src_yyyy,
4035 &zero, FALSE);
4036
4037 /* POW tmp1, tmp2, tmp1 */
4038 /* LOG tmp2, tmp2 */
4039 emit_instruction_op1(emit, VGPU10_OPCODE_LOG, &tmp2_dst, &tmp2_src,
4040 FALSE);
4041
4042 /* MUL tmp1, tmp2, tmp1 */
4043 emit_instruction_op2(emit, VGPU10_OPCODE_MUL, &tmp1_dst, &tmp2_src,
4044 &tmp1_src, FALSE);
4045
4046 /* EXP tmp1, tmp1 */
4047 emit_instruction_op1(emit, VGPU10_OPCODE_EXP, &tmp1_dst, &tmp1_src,
4048 FALSE);
4049
4050 /* EQ tmp2, 0, src.w */
4051 emit_instruction_op2(emit, VGPU10_OPCODE_EQ, &tmp2_dst, &zero,
4052 &src_wwww, FALSE);
4053 /* MOVC tmp1.z, tmp2, tmp1, 1.0 */
4054 emit_instruction_op3(emit, VGPU10_OPCODE_MOVC, &tmp1_dst,
4055 &tmp2_src, &one, &tmp1_src, FALSE);
4056
4057 /* LT tmp2, 0, src.x */
4058 emit_instruction_op2(emit, VGPU10_OPCODE_LT, &tmp2_dst, &zero,
4059 &src_xxxx, FALSE);
4060 /* MOVC dst.z, tmp2, tmp1, 0.0 */
4061 emit_instruction_op3(emit, VGPU10_OPCODE_MOVC, &dst_z,
4062 &tmp2_src, &tmp1_src, &zero, FALSE);
4063 }
4064
4065 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &inst->Dst[0], &move_src,
4066 FALSE);
4067 free_temp_indexes(emit);
4068
4069 return TRUE;
4070 }
4071
4072
4073 /**
4074 * Emit code for TGSI_OPCODE_LOG instruction.
4075 */
4076 static boolean
4077 emit_log(struct svga_shader_emitter_v10 *emit,
4078 const struct tgsi_full_instruction *inst)
4079 {
4080 /*
4081 * dst.x = floor(lg2(abs(s0.x)))
4082 * dst.y = abs(s0.x) / (2 ^ floor(lg2(abs(s0.x))))
4083 * dst.z = lg2(abs(s0.x))
4084 * dst.w = 1.0
4085 */
4086
4087 struct tgsi_full_src_register src_xxxx =
4088 scalar_src(&inst->Src[0], TGSI_SWIZZLE_X);
4089 unsigned tmp = get_temp_index(emit);
4090 struct tgsi_full_src_register tmp_src = make_src_temp_reg(tmp);
4091 struct tgsi_full_dst_register tmp_dst = make_dst_temp_reg(tmp);
4092 struct tgsi_full_src_register abs_src_xxxx = absolute_src(&src_xxxx);
4093
4094 /* only use X component of temp reg */
4095 tmp_dst = writemask_dst(&tmp_dst, TGSI_WRITEMASK_X);
4096 tmp_src = scalar_src(&tmp_src, TGSI_SWIZZLE_X);
4097
4098 /* LOG tmp.x, abs(s0.x) */
4099 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XYZ) {
4100 emit_instruction_op1(emit, VGPU10_OPCODE_LOG, &tmp_dst,
4101 &abs_src_xxxx, FALSE);
4102 }
4103
4104 /* MOV dst.z, tmp.x */
4105 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
4106 struct tgsi_full_dst_register dst_z =
4107 writemask_dst(&inst->Dst[0], TGSI_WRITEMASK_Z);
4108
4109 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &dst_z,
4110 &tmp_src, inst->Instruction.Saturate);
4111 }
4112
4113 /* FLR tmp.x, tmp.x */
4114 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) {
4115 emit_instruction_op1(emit, VGPU10_OPCODE_ROUND_NI, &tmp_dst,
4116 &tmp_src, FALSE);
4117 }
4118
4119 /* MOV dst.x, tmp.x */
4120 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
4121 struct tgsi_full_dst_register dst_x =
4122 writemask_dst(&inst->Dst[0], TGSI_WRITEMASK_X);
4123
4124 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &dst_x, &tmp_src,
4125 inst->Instruction.Saturate);
4126 }
4127
4128 /* EXP tmp.x, tmp.x */
4129 /* DIV dst.y, abs(s0.x), tmp.x */
4130 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
4131 struct tgsi_full_dst_register dst_y =
4132 writemask_dst(&inst->Dst[0], TGSI_WRITEMASK_Y);
4133
4134 emit_instruction_op1(emit, VGPU10_OPCODE_EXP, &tmp_dst, &tmp_src,
4135 FALSE);
4136 emit_instruction_op2(emit, VGPU10_OPCODE_DIV, &dst_y, &abs_src_xxxx,
4137 &tmp_src, inst->Instruction.Saturate);
4138 }
4139
4140 /* MOV dst.w, 1.0 */
4141 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
4142 struct tgsi_full_dst_register dst_w =
4143 writemask_dst(&inst->Dst[0], TGSI_WRITEMASK_W);
4144 struct tgsi_full_src_register one =
4145 make_immediate_reg_float(emit, 1.0f);
4146
4147 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &dst_w, &one, FALSE);
4148 }
4149
4150 free_temp_indexes(emit);
4151
4152 return TRUE;
4153 }
4154
4155
4156 /**
4157 * Emit code for TGSI_OPCODE_LRP instruction.
4158 */
4159 static boolean
4160 emit_lrp(struct svga_shader_emitter_v10 *emit,
4161 const struct tgsi_full_instruction *inst)
4162 {
4163 /* dst = LRP(s0, s1, s2):
4164 * dst = s0 * (s1 - s2) + s2
4165 * Translates into:
4166 * SUB tmp, s1, s2; tmp = s1 - s2
4167 * MAD dst, s0, tmp, s2; dst = s0 * t1 + s2
4168 */
4169 unsigned tmp = get_temp_index(emit);
4170 struct tgsi_full_src_register src_tmp = make_src_temp_reg(tmp);
4171 struct tgsi_full_dst_register dst_tmp = make_dst_temp_reg(tmp);
4172 struct tgsi_full_src_register neg_src2 = negate_src(&inst->Src[2]);
4173
4174 /* ADD tmp, s1, -s2 */
4175 emit_instruction_op2(emit, VGPU10_OPCODE_ADD, &dst_tmp,
4176 &inst->Src[1], &neg_src2, FALSE);
4177
4178 /* MAD dst, s1, tmp, s3 */
4179 emit_instruction_op3(emit, VGPU10_OPCODE_MAD, &inst->Dst[0],
4180 &inst->Src[0], &src_tmp, &inst->Src[2],
4181 inst->Instruction.Saturate);
4182
4183 free_temp_indexes(emit);
4184
4185 return TRUE;
4186 }
4187
4188
4189 /**
4190 * Emit code for TGSI_OPCODE_POW instruction.
4191 */
4192 static boolean
4193 emit_pow(struct svga_shader_emitter_v10 *emit,
4194 const struct tgsi_full_instruction *inst)
4195 {
4196 /* Note that TGSI_OPCODE_POW computes only one value from src0.x and
4197 * src1.x while VGPU10 computes four values.
4198 *
4199 * dst = POW(src0, src1):
4200 * dst.xyzw = src0.x ^ src1.x
4201 */
4202 unsigned tmp = get_temp_index(emit);
4203 struct tgsi_full_src_register tmp_src = make_src_temp_reg(tmp);
4204 struct tgsi_full_dst_register tmp_dst = make_dst_temp_reg(tmp);
4205 struct tgsi_full_src_register src0_xxxx =
4206 swizzle_src(&inst->Src[0], TGSI_SWIZZLE_X, TGSI_SWIZZLE_X,
4207 TGSI_SWIZZLE_X, TGSI_SWIZZLE_X);
4208 struct tgsi_full_src_register src1_xxxx =
4209 swizzle_src(&inst->Src[1], TGSI_SWIZZLE_X, TGSI_SWIZZLE_X,
4210 TGSI_SWIZZLE_X, TGSI_SWIZZLE_X);
4211
4212 /* LOG tmp, s0.xxxx */
4213 emit_instruction_op1(emit, VGPU10_OPCODE_LOG, &tmp_dst, &src0_xxxx,
4214 FALSE);
4215
4216 /* MUL tmp, tmp, s1.xxxx */
4217 emit_instruction_op2(emit, VGPU10_OPCODE_MUL, &tmp_dst, &tmp_src,
4218 &src1_xxxx, FALSE);
4219
4220 /* EXP tmp, s0.xxxx */
4221 emit_instruction_op1(emit, VGPU10_OPCODE_EXP, &inst->Dst[0],
4222 &tmp_src, inst->Instruction.Saturate);
4223
4224 /* free tmp */
4225 free_temp_indexes(emit);
4226
4227 return TRUE;
4228 }
4229
4230
4231 /**
4232 * Emit code for TGSI_OPCODE_RCP (reciprocal) instruction.
4233 */
4234 static boolean
4235 emit_rcp(struct svga_shader_emitter_v10 *emit,
4236 const struct tgsi_full_instruction *inst)
4237 {
4238 struct tgsi_full_src_register one = make_immediate_reg_float(emit, 1.0f);
4239
4240 unsigned tmp = get_temp_index(emit);
4241 struct tgsi_full_src_register tmp_src = make_src_temp_reg(tmp);
4242 struct tgsi_full_dst_register tmp_dst = make_dst_temp_reg(tmp);
4243
4244 struct tgsi_full_dst_register tmp_dst_x =
4245 writemask_dst(&tmp_dst, TGSI_WRITEMASK_X);
4246 struct tgsi_full_src_register tmp_src_xxxx =
4247 scalar_src(&tmp_src, TGSI_SWIZZLE_X);
4248
4249 /* DIV tmp.x, 1.0, s0 */
4250 emit_instruction_op2(emit, VGPU10_OPCODE_DIV, &tmp_dst_x, &one,
4251 &inst->Src[0], FALSE);
4252
4253 /* MOV dst, tmp.xxxx */
4254 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &inst->Dst[0],
4255 &tmp_src_xxxx, inst->Instruction.Saturate);
4256
4257 free_temp_indexes(emit);
4258
4259 return TRUE;
4260 }
4261
4262
4263 /**
4264 * Emit code for TGSI_OPCODE_RSQ instruction.
4265 */
4266 static boolean
4267 emit_rsq(struct svga_shader_emitter_v10 *emit,
4268 const struct tgsi_full_instruction *inst)
4269 {
4270 /* dst = RSQ(src):
4271 * dst.xyzw = 1 / sqrt(src.x)
4272 * Translates into:
4273 * RSQ tmp, src.x
4274 * MOV dst, tmp.xxxx
4275 */
4276
4277 unsigned tmp = get_temp_index(emit);
4278 struct tgsi_full_src_register tmp_src = make_src_temp_reg(tmp);
4279 struct tgsi_full_dst_register tmp_dst = make_dst_temp_reg(tmp);
4280
4281 struct tgsi_full_dst_register tmp_dst_x =
4282 writemask_dst(&tmp_dst, TGSI_WRITEMASK_X);
4283 struct tgsi_full_src_register tmp_src_xxxx =
4284 scalar_src(&tmp_src, TGSI_SWIZZLE_X);
4285
4286 /* RSQ tmp, src.x */
4287 emit_instruction_op1(emit, VGPU10_OPCODE_RSQ, &tmp_dst_x,
4288 &inst->Src[0], FALSE);
4289
4290 /* MOV dst, tmp.xxxx */
4291 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &inst->Dst[0],
4292 &tmp_src_xxxx, inst->Instruction.Saturate);
4293
4294 /* free tmp */
4295 free_temp_indexes(emit);
4296
4297 return TRUE;
4298 }
4299
4300
4301 /**
4302 * Emit code for TGSI_OPCODE_SEQ (Set Equal) instruction.
4303 */
4304 static boolean
4305 emit_seq(struct svga_shader_emitter_v10 *emit,
4306 const struct tgsi_full_instruction *inst)
4307 {
4308 /* dst = SEQ(s0, s1):
4309 * dst = s0 == s1 ? 1.0 : 0.0 (per component)
4310 * Translates into:
4311 * EQ tmp, s0, s1; tmp = s0 == s1 : 0xffffffff : 0 (per comp)
4312 * MOVC dst, tmp, 1.0, 0.0; dst = tmp ? 1.0 : 0.0 (per component)
4313 */
4314 unsigned tmp = get_temp_index(emit);
4315 struct tgsi_full_src_register tmp_src = make_src_temp_reg(tmp);
4316 struct tgsi_full_dst_register tmp_dst = make_dst_temp_reg(tmp);
4317 struct tgsi_full_src_register zero = make_immediate_reg_float(emit, 0.0f);
4318 struct tgsi_full_src_register one = make_immediate_reg_float(emit, 1.0f);
4319
4320 /* EQ tmp, s0, s1 */
4321 emit_instruction_op2(emit, VGPU10_OPCODE_EQ, &tmp_dst, &inst->Src[0],
4322 &inst->Src[1], FALSE);
4323
4324 /* MOVC dst, tmp, one, zero */
4325 emit_instruction_op3(emit, VGPU10_OPCODE_MOVC, &inst->Dst[0], &tmp_src,
4326 &one, &zero, FALSE);
4327
4328 free_temp_indexes(emit);
4329
4330 return TRUE;
4331 }
4332
4333
4334 /**
4335 * Emit code for TGSI_OPCODE_SGE (Set Greater than or Equal) instruction.
4336 */
4337 static boolean
4338 emit_sge(struct svga_shader_emitter_v10 *emit,
4339 const struct tgsi_full_instruction *inst)
4340 {
4341 /* dst = SGE(s0, s1):
4342 * dst = s0 >= s1 ? 1.0 : 0.0 (per component)
4343 * Translates into:
4344 * GE tmp, s0, s1; tmp = s0 >= s1 : 0xffffffff : 0 (per comp)
4345 * MOVC dst, tmp, 1.0, 0.0; dst = tmp ? 1.0 : 0.0 (per component)
4346 */
4347 unsigned tmp = get_temp_index(emit);
4348 struct tgsi_full_src_register tmp_src = make_src_temp_reg(tmp);
4349 struct tgsi_full_dst_register tmp_dst = make_dst_temp_reg(tmp);
4350 struct tgsi_full_src_register zero = make_immediate_reg_float(emit, 0.0f);
4351 struct tgsi_full_src_register one = make_immediate_reg_float(emit, 1.0f);
4352
4353 /* GE tmp, s0, s1 */
4354 emit_instruction_op2(emit, VGPU10_OPCODE_GE, &tmp_dst, &inst->Src[0],
4355 &inst->Src[1], FALSE);
4356
4357 /* MOVC dst, tmp, one, zero */
4358 emit_instruction_op3(emit, VGPU10_OPCODE_MOVC, &inst->Dst[0], &tmp_src,
4359 &one, &zero, FALSE);
4360
4361 free_temp_indexes(emit);
4362
4363 return TRUE;
4364 }
4365
4366
4367 /**
4368 * Emit code for TGSI_OPCODE_SGT (Set Greater than) instruction.
4369 */
4370 static boolean
4371 emit_sgt(struct svga_shader_emitter_v10 *emit,
4372 const struct tgsi_full_instruction *inst)
4373 {
4374 /* dst = SGT(s0, s1):
4375 * dst = s0 > s1 ? 1.0 : 0.0 (per component)
4376 * Translates into:
4377 * LT tmp, s1, s0; tmp = s1 < s0 ? 0xffffffff : 0 (per comp)
4378 * MOVC dst, tmp, 1.0, 0.0; dst = tmp ? 1.0 : 0.0 (per component)
4379 */
4380 unsigned tmp = get_temp_index(emit);
4381 struct tgsi_full_src_register tmp_src = make_src_temp_reg(tmp);
4382 struct tgsi_full_dst_register tmp_dst = make_dst_temp_reg(tmp);
4383 struct tgsi_full_src_register zero = make_immediate_reg_float(emit, 0.0f);
4384 struct tgsi_full_src_register one = make_immediate_reg_float(emit, 1.0f);
4385
4386 /* LT tmp, s1, s0 */
4387 emit_instruction_op2(emit, VGPU10_OPCODE_LT, &tmp_dst, &inst->Src[1],
4388 &inst->Src[0], FALSE);
4389
4390 /* MOVC dst, tmp, one, zero */
4391 emit_instruction_op3(emit, VGPU10_OPCODE_MOVC, &inst->Dst[0], &tmp_src,
4392 &one, &zero, FALSE);
4393
4394 free_temp_indexes(emit);
4395
4396 return TRUE;
4397 }
4398
4399
4400 /**
4401 * Emit code for TGSI_OPCODE_SIN and TGSI_OPCODE_COS instructions.
4402 */
4403 static boolean
4404 emit_sincos(struct svga_shader_emitter_v10 *emit,
4405 const struct tgsi_full_instruction *inst)
4406 {
4407 unsigned tmp = get_temp_index(emit);
4408 struct tgsi_full_src_register tmp_src = make_src_temp_reg(tmp);
4409 struct tgsi_full_dst_register tmp_dst = make_dst_temp_reg(tmp);
4410
4411 struct tgsi_full_src_register tmp_src_xxxx =
4412 scalar_src(&tmp_src, TGSI_SWIZZLE_X);
4413 struct tgsi_full_dst_register tmp_dst_x =
4414 writemask_dst(&tmp_dst, TGSI_WRITEMASK_X);
4415
4416 begin_emit_instruction(emit);
4417 emit_opcode(emit, VGPU10_OPCODE_SINCOS, FALSE);
4418
4419 if(inst->Instruction.Opcode == TGSI_OPCODE_SIN)
4420 {
4421 emit_dst_register(emit, &tmp_dst_x); /* first destination register */
4422 emit_null_dst_register(emit); /* second destination register */
4423 }
4424 else {
4425 emit_null_dst_register(emit);
4426 emit_dst_register(emit, &tmp_dst_x);
4427 }
4428
4429 emit_src_register(emit, &inst->Src[0]);
4430 end_emit_instruction(emit);
4431
4432 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &inst->Dst[0],
4433 &tmp_src_xxxx, inst->Instruction.Saturate);
4434
4435 free_temp_indexes(emit);
4436
4437 return TRUE;
4438 }
4439
4440
4441 /**
4442 * Emit code for TGSI_OPCODE_SLE (Set Less than or Equal) instruction.
4443 */
4444 static boolean
4445 emit_sle(struct svga_shader_emitter_v10 *emit,
4446 const struct tgsi_full_instruction *inst)
4447 {
4448 /* dst = SLE(s0, s1):
4449 * dst = s0 <= s1 ? 1.0 : 0.0 (per component)
4450 * Translates into:
4451 * GE tmp, s1, s0; tmp = s1 >= s0 : 0xffffffff : 0 (per comp)
4452 * MOVC dst, tmp, 1.0, 0.0; dst = tmp ? 1.0 : 0.0 (per component)
4453 */
4454 unsigned tmp = get_temp_index(emit);
4455 struct tgsi_full_src_register tmp_src = make_src_temp_reg(tmp);
4456 struct tgsi_full_dst_register tmp_dst = make_dst_temp_reg(tmp);
4457 struct tgsi_full_src_register zero = make_immediate_reg_float(emit, 0.0f);
4458 struct tgsi_full_src_register one = make_immediate_reg_float(emit, 1.0f);
4459
4460 /* GE tmp, s1, s0 */
4461 emit_instruction_op2(emit, VGPU10_OPCODE_GE, &tmp_dst, &inst->Src[1],
4462 &inst->Src[0], FALSE);
4463
4464 /* MOVC dst, tmp, one, zero */
4465 emit_instruction_op3(emit, VGPU10_OPCODE_MOVC, &inst->Dst[0], &tmp_src,
4466 &one, &zero, FALSE);
4467
4468 free_temp_indexes(emit);
4469
4470 return TRUE;
4471 }
4472
4473
4474 /**
4475 * Emit code for TGSI_OPCODE_SLT (Set Less than) instruction.
4476 */
4477 static boolean
4478 emit_slt(struct svga_shader_emitter_v10 *emit,
4479 const struct tgsi_full_instruction *inst)
4480 {
4481 /* dst = SLT(s0, s1):
4482 * dst = s0 < s1 ? 1.0 : 0.0 (per component)
4483 * Translates into:
4484 * LT tmp, s0, s1; tmp = s0 < s1 ? 0xffffffff : 0 (per comp)
4485 * MOVC dst, tmp, 1.0, 0.0; dst = tmp ? 1.0 : 0.0 (per component)
4486 */
4487 unsigned tmp = get_temp_index(emit);
4488 struct tgsi_full_src_register tmp_src = make_src_temp_reg(tmp);
4489 struct tgsi_full_dst_register tmp_dst = make_dst_temp_reg(tmp);
4490 struct tgsi_full_src_register zero = make_immediate_reg_float(emit, 0.0f);
4491 struct tgsi_full_src_register one = make_immediate_reg_float(emit, 1.0f);
4492
4493 /* LT tmp, s0, s1 */
4494 emit_instruction_op2(emit, VGPU10_OPCODE_LT, &tmp_dst, &inst->Src[0],
4495 &inst->Src[1], FALSE);
4496
4497 /* MOVC dst, tmp, one, zero */
4498 emit_instruction_op3(emit, VGPU10_OPCODE_MOVC, &inst->Dst[0], &tmp_src,
4499 &one, &zero, FALSE);
4500
4501 free_temp_indexes(emit);
4502
4503 return TRUE;
4504 }
4505
4506
4507 /**
4508 * Emit code for TGSI_OPCODE_SNE (Set Not Equal) instruction.
4509 */
4510 static boolean
4511 emit_sne(struct svga_shader_emitter_v10 *emit,
4512 const struct tgsi_full_instruction *inst)
4513 {
4514 /* dst = SNE(s0, s1):
4515 * dst = s0 != s1 ? 1.0 : 0.0 (per component)
4516 * Translates into:
4517 * EQ tmp, s0, s1; tmp = s0 == s1 : 0xffffffff : 0 (per comp)
4518 * MOVC dst, tmp, 1.0, 0.0; dst = tmp ? 1.0 : 0.0 (per component)
4519 */
4520 unsigned tmp = get_temp_index(emit);
4521 struct tgsi_full_src_register tmp_src = make_src_temp_reg(tmp);
4522 struct tgsi_full_dst_register tmp_dst = make_dst_temp_reg(tmp);
4523 struct tgsi_full_src_register zero = make_immediate_reg_float(emit, 0.0f);
4524 struct tgsi_full_src_register one = make_immediate_reg_float(emit, 1.0f);
4525
4526 /* NE tmp, s0, s1 */
4527 emit_instruction_op2(emit, VGPU10_OPCODE_NE, &tmp_dst, &inst->Src[0],
4528 &inst->Src[1], FALSE);
4529
4530 /* MOVC dst, tmp, one, zero */
4531 emit_instruction_op3(emit, VGPU10_OPCODE_MOVC, &inst->Dst[0], &tmp_src,
4532 &one, &zero, FALSE);
4533
4534 free_temp_indexes(emit);
4535
4536 return TRUE;
4537 }
4538
4539
4540 /**
4541 * Emit code for TGSI_OPCODE_SSG (Set Sign) instruction.
4542 */
4543 static boolean
4544 emit_ssg(struct svga_shader_emitter_v10 *emit,
4545 const struct tgsi_full_instruction *inst)
4546 {
4547 /* dst.x = (src.x > 0.0) ? 1.0 : (src.x < 0.0) ? -1.0 : 0.0
4548 * dst.y = (src.y > 0.0) ? 1.0 : (src.y < 0.0) ? -1.0 : 0.0
4549 * dst.z = (src.z > 0.0) ? 1.0 : (src.z < 0.0) ? -1.0 : 0.0
4550 * dst.w = (src.w > 0.0) ? 1.0 : (src.w < 0.0) ? -1.0 : 0.0
4551 * Translates into:
4552 * LT tmp1, src, zero; tmp1 = src < zero ? 0xffffffff : 0 (per comp)
4553 * MOVC tmp2, tmp1, -1.0, 0.0; tmp2 = tmp1 ? -1.0 : 0.0 (per component)
4554 * LT tmp1, zero, src; tmp1 = zero < src ? 0xffffffff : 0 (per comp)
4555 * MOVC dst, tmp1, 1.0, tmp2; dst = tmp1 ? 1.0 : tmp2 (per component)
4556 */
4557 struct tgsi_full_src_register zero =
4558 make_immediate_reg_float(emit, 0.0f);
4559 struct tgsi_full_src_register one =
4560 make_immediate_reg_float(emit, 1.0f);
4561 struct tgsi_full_src_register neg_one =
4562 make_immediate_reg_float(emit, -1.0f);
4563
4564 unsigned tmp1 = get_temp_index(emit);
4565 struct tgsi_full_src_register tmp1_src = make_src_temp_reg(tmp1);
4566 struct tgsi_full_dst_register tmp1_dst = make_dst_temp_reg(tmp1);
4567
4568 unsigned tmp2 = get_temp_index(emit);
4569 struct tgsi_full_src_register tmp2_src = make_src_temp_reg(tmp2);
4570 struct tgsi_full_dst_register tmp2_dst = make_dst_temp_reg(tmp2);
4571
4572 emit_instruction_op2(emit, VGPU10_OPCODE_LT, &tmp1_dst, &inst->Src[0],
4573 &zero, FALSE);
4574 emit_instruction_op3(emit, VGPU10_OPCODE_MOVC, &tmp2_dst, &tmp1_src,
4575 &neg_one, &zero, FALSE);
4576 emit_instruction_op2(emit, VGPU10_OPCODE_LT, &tmp1_dst, &zero,
4577 &inst->Src[0], FALSE);
4578 emit_instruction_op3(emit, VGPU10_OPCODE_MOVC, &inst->Dst[0], &tmp1_src,
4579 &one, &tmp2_src, FALSE);
4580
4581 free_temp_indexes(emit);
4582
4583 return TRUE;
4584 }
4585
4586
4587 /**
4588 * Emit code for TGSI_OPCODE_ISSG (Integer Set Sign) instruction.
4589 */
4590 static boolean
4591 emit_issg(struct svga_shader_emitter_v10 *emit,
4592 const struct tgsi_full_instruction *inst)
4593 {
4594 /* dst.x = (src.x > 0) ? 1 : (src.x < 0) ? -1 : 0
4595 * dst.y = (src.y > 0) ? 1 : (src.y < 0) ? -1 : 0
4596 * dst.z = (src.z > 0) ? 1 : (src.z < 0) ? -1 : 0
4597 * dst.w = (src.w > 0) ? 1 : (src.w < 0) ? -1 : 0
4598 * Translates into:
4599 * ILT tmp1, src, 0 tmp1 = src < 0 ? -1 : 0 (per component)
4600 * ILT tmp2, 0, src tmp2 = 0 < src ? -1 : 0 (per component)
4601 * IADD dst, tmp1, neg(tmp2) dst = tmp1 - tmp2 (per component)
4602 */
4603 struct tgsi_full_src_register zero = make_immediate_reg_float(emit, 0.0f);
4604
4605 unsigned tmp1 = get_temp_index(emit);
4606 struct tgsi_full_src_register tmp1_src = make_src_temp_reg(tmp1);
4607 struct tgsi_full_dst_register tmp1_dst = make_dst_temp_reg(tmp1);
4608
4609 unsigned tmp2 = get_temp_index(emit);
4610 struct tgsi_full_src_register tmp2_src = make_src_temp_reg(tmp2);
4611 struct tgsi_full_dst_register tmp2_dst = make_dst_temp_reg(tmp2);
4612
4613 struct tgsi_full_src_register neg_tmp2 = negate_src(&tmp2_src);
4614
4615 emit_instruction_op2(emit, VGPU10_OPCODE_ILT, &tmp1_dst,
4616 &inst->Src[0], &zero, FALSE);
4617 emit_instruction_op2(emit, VGPU10_OPCODE_ILT, &tmp2_dst,
4618 &zero, &inst->Src[0], FALSE);
4619 emit_instruction_op2(emit, VGPU10_OPCODE_IADD, &inst->Dst[0],
4620 &tmp1_src, &neg_tmp2, FALSE);
4621
4622 free_temp_indexes(emit);
4623
4624 return TRUE;
4625 }
4626
4627
4628 /**
4629 * Emit a comparison instruction. The dest register will get
4630 * 0 or ~0 values depending on the outcome of comparing src0 to src1.
4631 */
4632 static void
4633 emit_comparison(struct svga_shader_emitter_v10 *emit,
4634 SVGA3dCmpFunc func,
4635 const struct tgsi_full_dst_register *dst,
4636 const struct tgsi_full_src_register *src0,
4637 const struct tgsi_full_src_register *src1)
4638 {
4639 struct tgsi_full_src_register immediate;
4640 VGPU10OpcodeToken0 opcode0;
4641 boolean swapSrc = FALSE;
4642
4643 /* Sanity checks for svga vs. gallium enums */
4644 STATIC_ASSERT(SVGA3D_CMP_LESS == (PIPE_FUNC_LESS + 1));
4645 STATIC_ASSERT(SVGA3D_CMP_GREATEREQUAL == (PIPE_FUNC_GEQUAL + 1));
4646
4647 opcode0.value = 0;
4648
4649 switch (func) {
4650 case SVGA3D_CMP_NEVER:
4651 immediate = make_immediate_reg_int(emit, 0);
4652 /* MOV dst, {0} */
4653 begin_emit_instruction(emit);
4654 emit_dword(emit, VGPU10_OPCODE_MOV);
4655 emit_dst_register(emit, dst);
4656 emit_src_register(emit, &immediate);
4657 end_emit_instruction(emit);
4658 return;
4659 case SVGA3D_CMP_ALWAYS:
4660 immediate = make_immediate_reg_int(emit, -1);
4661 /* MOV dst, {-1} */
4662 begin_emit_instruction(emit);
4663 emit_dword(emit, VGPU10_OPCODE_MOV);
4664 emit_dst_register(emit, dst);
4665 emit_src_register(emit, &immediate);
4666 end_emit_instruction(emit);
4667 return;
4668 case SVGA3D_CMP_LESS:
4669 opcode0.opcodeType = VGPU10_OPCODE_LT;
4670 break;
4671 case SVGA3D_CMP_EQUAL:
4672 opcode0.opcodeType = VGPU10_OPCODE_EQ;
4673 break;
4674 case SVGA3D_CMP_LESSEQUAL:
4675 opcode0.opcodeType = VGPU10_OPCODE_GE;
4676 swapSrc = TRUE;
4677 break;
4678 case SVGA3D_CMP_GREATER:
4679 opcode0.opcodeType = VGPU10_OPCODE_LT;
4680 swapSrc = TRUE;
4681 break;
4682 case SVGA3D_CMP_NOTEQUAL:
4683 opcode0.opcodeType = VGPU10_OPCODE_NE;
4684 break;
4685 case SVGA3D_CMP_GREATEREQUAL:
4686 opcode0.opcodeType = VGPU10_OPCODE_GE;
4687 break;
4688 default:
4689 assert(!"Unexpected comparison mode");
4690 opcode0.opcodeType = VGPU10_OPCODE_EQ;
4691 }
4692
4693 begin_emit_instruction(emit);
4694 emit_dword(emit, opcode0.value);
4695 emit_dst_register(emit, dst);
4696 if (swapSrc) {
4697 emit_src_register(emit, src1);
4698 emit_src_register(emit, src0);
4699 }
4700 else {
4701 emit_src_register(emit, src0);
4702 emit_src_register(emit, src1);
4703 }
4704 end_emit_instruction(emit);
4705 }
4706
4707
4708 /**
4709 * Get texel/address offsets for a texture instruction.
4710 */
4711 static void
4712 get_texel_offsets(const struct svga_shader_emitter_v10 *emit,
4713 const struct tgsi_full_instruction *inst, int offsets[3])
4714 {
4715 if (inst->Texture.NumOffsets == 1) {
4716 /* According to OpenGL Shader Language spec the offsets are only
4717 * fetched from a previously-declared immediate/literal.
4718 */
4719 const struct tgsi_texture_offset *off = inst->TexOffsets;
4720 const unsigned index = off[0].Index;
4721 const unsigned swizzleX = off[0].SwizzleX;
4722 const unsigned swizzleY = off[0].SwizzleY;
4723 const unsigned swizzleZ = off[0].SwizzleZ;
4724 const union tgsi_immediate_data *imm = emit->immediates[index];
4725
4726 assert(inst->TexOffsets[0].File == TGSI_FILE_IMMEDIATE);
4727
4728 offsets[0] = imm[swizzleX].Int;
4729 offsets[1] = imm[swizzleY].Int;
4730 offsets[2] = imm[swizzleZ].Int;
4731 }
4732 else {
4733 offsets[0] = offsets[1] = offsets[2] = 0;
4734 }
4735 }
4736
4737
4738 /**
4739 * Set up the coordinate register for texture sampling.
4740 * When we're sampling from a RECT texture we have to scale the
4741 * unnormalized coordinate to a normalized coordinate.
4742 * We do that by multiplying the coordinate by an "extra" constant.
4743 * An alternative would be to use the RESINFO instruction to query the
4744 * texture's size.
4745 */
4746 static struct tgsi_full_src_register
4747 setup_texcoord(struct svga_shader_emitter_v10 *emit,
4748 unsigned unit,
4749 const struct tgsi_full_src_register *coord)
4750 {
4751 if (emit->key.tex[unit].unnormalized) {
4752 unsigned scale_index = emit->texcoord_scale_index[unit];
4753 unsigned tmp = get_temp_index(emit);
4754 struct tgsi_full_src_register tmp_src = make_src_temp_reg(tmp);
4755 struct tgsi_full_dst_register tmp_dst = make_dst_temp_reg(tmp);
4756 struct tgsi_full_src_register scale_src = make_src_const_reg(scale_index);
4757
4758 if (emit->key.tex[unit].texel_bias) {
4759 /* to fix texture coordinate rounding issue, 0.0001 offset is
4760 * been added. This fixes piglit test fbo-blit-scaled-linear. */
4761 struct tgsi_full_src_register offset =
4762 make_immediate_reg_float(emit, 0.0001f);
4763
4764 /* ADD tmp, coord, offset */
4765 emit_instruction_op2(emit, VGPU10_OPCODE_ADD, &tmp_dst,
4766 coord, &offset, FALSE);
4767 /* MUL tmp, tmp, scale */
4768 emit_instruction_op2(emit, VGPU10_OPCODE_MUL, &tmp_dst,
4769 &tmp_src, &scale_src, FALSE);
4770 }
4771 else {
4772 /* MUL tmp, coord, const[] */
4773 emit_instruction_op2(emit, VGPU10_OPCODE_MUL, &tmp_dst,
4774 coord, &scale_src, FALSE);
4775 }
4776 return tmp_src;
4777 }
4778 else {
4779 /* use texcoord as-is */
4780 return *coord;
4781 }
4782 }
4783
4784
4785 /**
4786 * For SAMPLE_C instructions, emit the extra src register which indicates
4787 * the reference/comparision value.
4788 */
4789 static void
4790 emit_tex_compare_refcoord(struct svga_shader_emitter_v10 *emit,
4791 enum tgsi_texture_type target,
4792 const struct tgsi_full_src_register *coord)
4793 {
4794 struct tgsi_full_src_register coord_src_ref;
4795 int component;
4796
4797 assert(tgsi_is_shadow_target(target));
4798
4799 component = tgsi_util_get_shadow_ref_src_index(target) % 4;
4800 assert(component >= 0);
4801
4802 coord_src_ref = scalar_src(coord, component);
4803
4804 emit_src_register(emit, &coord_src_ref);
4805 }
4806
4807
4808 /**
4809 * Info for implementing texture swizzles.
4810 * The begin_tex_swizzle(), get_tex_swizzle_dst() and end_tex_swizzle()
4811 * functions use this to encapsulate the extra steps needed to perform
4812 * a texture swizzle, or shadow/depth comparisons.
4813 * The shadow/depth comparison is only done here if for the cases where
4814 * there's no VGPU10 opcode (like texture bias lookup w/ shadow compare).
4815 */
4816 struct tex_swizzle_info
4817 {
4818 boolean swizzled;
4819 boolean shadow_compare;
4820 unsigned unit;
4821 enum tgsi_texture_type texture_target; /**< TGSI_TEXTURE_x */
4822 struct tgsi_full_src_register tmp_src;
4823 struct tgsi_full_dst_register tmp_dst;
4824 const struct tgsi_full_dst_register *inst_dst;
4825 const struct tgsi_full_src_register *coord_src;
4826 };
4827
4828
4829 /**
4830 * Do setup for handling texture swizzles or shadow compares.
4831 * \param unit the texture unit
4832 * \param inst the TGSI texture instruction
4833 * \param shadow_compare do shadow/depth comparison?
4834 * \param swz returns the swizzle info
4835 */
4836 static void
4837 begin_tex_swizzle(struct svga_shader_emitter_v10 *emit,
4838 unsigned unit,
4839 const struct tgsi_full_instruction *inst,
4840 boolean shadow_compare,
4841 struct tex_swizzle_info *swz)
4842 {
4843 swz->swizzled = (emit->key.tex[unit].swizzle_r != TGSI_SWIZZLE_X ||
4844 emit->key.tex[unit].swizzle_g != TGSI_SWIZZLE_Y ||
4845 emit->key.tex[unit].swizzle_b != TGSI_SWIZZLE_Z ||
4846 emit->key.tex[unit].swizzle_a != TGSI_SWIZZLE_W);
4847
4848 swz->shadow_compare = shadow_compare;
4849 swz->texture_target = inst->Texture.Texture;
4850
4851 if (swz->swizzled || shadow_compare) {
4852 /* Allocate temp register for the result of the SAMPLE instruction
4853 * and the source of the MOV/compare/swizzle instructions.
4854 */
4855 unsigned tmp = get_temp_index(emit);
4856 swz->tmp_src = make_src_temp_reg(tmp);
4857 swz->tmp_dst = make_dst_temp_reg(tmp);
4858
4859 swz->unit = unit;
4860 }
4861 swz->inst_dst = &inst->Dst[0];
4862 swz->coord_src = &inst->Src[0];
4863
4864 emit->fs.shadow_compare_units |= shadow_compare << unit;
4865 }
4866
4867
4868 /**
4869 * Returns the register to put the SAMPLE instruction results into.
4870 * This will either be the original instruction dst reg (if no swizzle
4871 * and no shadow comparison) or a temporary reg if there is a swizzle.
4872 */
4873 static const struct tgsi_full_dst_register *
4874 get_tex_swizzle_dst(const struct tex_swizzle_info *swz)
4875 {
4876 return (swz->swizzled || swz->shadow_compare)
4877 ? &swz->tmp_dst : swz->inst_dst;
4878 }
4879
4880
4881 /**
4882 * This emits the MOV instruction that actually implements a texture swizzle
4883 * and/or shadow comparison.
4884 */
4885 static void
4886 end_tex_swizzle(struct svga_shader_emitter_v10 *emit,
4887 const struct tex_swizzle_info *swz)
4888 {
4889 if (swz->shadow_compare) {
4890 /* Emit extra instructions to compare the fetched texel value against
4891 * a texture coordinate component. The result of the comparison
4892 * is 0.0 or 1.0.
4893 */
4894 struct tgsi_full_src_register coord_src;
4895 struct tgsi_full_src_register texel_src =
4896 scalar_src(&swz->tmp_src, TGSI_SWIZZLE_X);
4897 struct tgsi_full_src_register one =
4898 make_immediate_reg_float(emit, 1.0f);
4899 /* convert gallium comparison func to SVGA comparison func */
4900 SVGA3dCmpFunc compare_func = emit->key.tex[swz->unit].compare_func + 1;
4901
4902 assert(emit->unit == PIPE_SHADER_FRAGMENT);
4903
4904 int component =
4905 tgsi_util_get_shadow_ref_src_index(swz->texture_target) % 4;
4906 assert(component >= 0);
4907 coord_src = scalar_src(swz->coord_src, component);
4908
4909 /* COMPARE tmp, coord, texel */
4910 emit_comparison(emit, compare_func,
4911 &swz->tmp_dst, &coord_src, &texel_src);
4912
4913 /* AND dest, tmp, {1.0} */
4914 begin_emit_instruction(emit);
4915 emit_opcode(emit, VGPU10_OPCODE_AND, FALSE);
4916 if (swz->swizzled) {
4917 emit_dst_register(emit, &swz->tmp_dst);
4918 }
4919 else {
4920 emit_dst_register(emit, swz->inst_dst);
4921 }
4922 emit_src_register(emit, &swz->tmp_src);
4923 emit_src_register(emit, &one);
4924 end_emit_instruction(emit);
4925 }
4926
4927 if (swz->swizzled) {
4928 unsigned swz_r = emit->key.tex[swz->unit].swizzle_r;
4929 unsigned swz_g = emit->key.tex[swz->unit].swizzle_g;
4930 unsigned swz_b = emit->key.tex[swz->unit].swizzle_b;
4931 unsigned swz_a = emit->key.tex[swz->unit].swizzle_a;
4932 unsigned writemask_0 = 0, writemask_1 = 0;
4933 boolean int_tex = is_integer_type(emit->sampler_return_type[swz->unit]);
4934
4935 /* Swizzle w/out zero/one terms */
4936 struct tgsi_full_src_register src_swizzled =
4937 swizzle_src(&swz->tmp_src,
4938 swz_r < PIPE_SWIZZLE_0 ? swz_r : PIPE_SWIZZLE_X,
4939 swz_g < PIPE_SWIZZLE_0 ? swz_g : PIPE_SWIZZLE_Y,
4940 swz_b < PIPE_SWIZZLE_0 ? swz_b : PIPE_SWIZZLE_Z,
4941 swz_a < PIPE_SWIZZLE_0 ? swz_a : PIPE_SWIZZLE_W);
4942
4943 /* MOV dst, color(tmp).<swizzle> */
4944 emit_instruction_op1(emit, VGPU10_OPCODE_MOV,
4945 swz->inst_dst, &src_swizzled, FALSE);
4946
4947 /* handle swizzle zero terms */
4948 writemask_0 = (((swz_r == PIPE_SWIZZLE_0) << 0) |
4949 ((swz_g == PIPE_SWIZZLE_0) << 1) |
4950 ((swz_b == PIPE_SWIZZLE_0) << 2) |
4951 ((swz_a == PIPE_SWIZZLE_0) << 3));
4952 writemask_0 &= swz->inst_dst->Register.WriteMask;
4953
4954 if (writemask_0) {
4955 struct tgsi_full_src_register zero = int_tex ?
4956 make_immediate_reg_int(emit, 0) :
4957 make_immediate_reg_float(emit, 0.0f);
4958 struct tgsi_full_dst_register dst =
4959 writemask_dst(swz->inst_dst, writemask_0);
4960
4961 /* MOV dst.writemask_0, {0,0,0,0} */
4962 emit_instruction_op1(emit, VGPU10_OPCODE_MOV,
4963 &dst, &zero, FALSE);
4964 }
4965
4966 /* handle swizzle one terms */
4967 writemask_1 = (((swz_r == PIPE_SWIZZLE_1) << 0) |
4968 ((swz_g == PIPE_SWIZZLE_1) << 1) |
4969 ((swz_b == PIPE_SWIZZLE_1) << 2) |
4970 ((swz_a == PIPE_SWIZZLE_1) << 3));
4971 writemask_1 &= swz->inst_dst->Register.WriteMask;
4972
4973 if (writemask_1) {
4974 struct tgsi_full_src_register one = int_tex ?
4975 make_immediate_reg_int(emit, 1) :
4976 make_immediate_reg_float(emit, 1.0f);
4977 struct tgsi_full_dst_register dst =
4978 writemask_dst(swz->inst_dst, writemask_1);
4979
4980 /* MOV dst.writemask_1, {1,1,1,1} */
4981 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &dst, &one, FALSE);
4982 }
4983 }
4984 }
4985
4986
4987 /**
4988 * Emit code for TGSI_OPCODE_SAMPLE instruction.
4989 */
4990 static boolean
4991 emit_sample(struct svga_shader_emitter_v10 *emit,
4992 const struct tgsi_full_instruction *inst)
4993 {
4994 const unsigned resource_unit = inst->Src[1].Register.Index;
4995 const unsigned sampler_unit = inst->Src[2].Register.Index;
4996 struct tgsi_full_src_register coord;
4997 int offsets[3];
4998 struct tex_swizzle_info swz_info;
4999
5000 begin_tex_swizzle(emit, sampler_unit, inst, FALSE, &swz_info);
5001
5002 get_texel_offsets(emit, inst, offsets);
5003
5004 coord = setup_texcoord(emit, resource_unit, &inst->Src[0]);
5005
5006 /* SAMPLE dst, coord(s0), resource, sampler */
5007 begin_emit_instruction(emit);
5008
5009 /* NOTE: for non-fragment shaders, we should use VGPU10_OPCODE_SAMPLE_L
5010 * with LOD=0. But our virtual GPU accepts this as-is.
5011 */
5012 emit_sample_opcode(emit, VGPU10_OPCODE_SAMPLE,
5013 inst->Instruction.Saturate, offsets);
5014 emit_dst_register(emit, get_tex_swizzle_dst(&swz_info));
5015 emit_src_register(emit, &coord);
5016 emit_resource_register(emit, resource_unit);
5017 emit_sampler_register(emit, sampler_unit);
5018 end_emit_instruction(emit);
5019
5020 end_tex_swizzle(emit, &swz_info);
5021
5022 free_temp_indexes(emit);
5023
5024 return TRUE;
5025 }
5026
5027
5028 /**
5029 * Check if a texture instruction is valid.
5030 * An example of an invalid texture instruction is doing shadow comparison
5031 * with an integer-valued texture.
5032 * If we detect an invalid texture instruction, we replace it with:
5033 * MOV dst, {1,1,1,1};
5034 * \return TRUE if valid, FALSE if invalid.
5035 */
5036 static boolean
5037 is_valid_tex_instruction(struct svga_shader_emitter_v10 *emit,
5038 const struct tgsi_full_instruction *inst)
5039 {
5040 const unsigned unit = inst->Src[1].Register.Index;
5041 const enum tgsi_texture_type target = inst->Texture.Texture;
5042 boolean valid = TRUE;
5043
5044 if (tgsi_is_shadow_target(target) &&
5045 is_integer_type(emit->sampler_return_type[unit])) {
5046 debug_printf("Invalid SAMPLE_C with an integer texture!\n");
5047 valid = FALSE;
5048 }
5049 /* XXX might check for other conditions in the future here */
5050
5051 if (!valid) {
5052 /* emit a MOV dst, {1,1,1,1} instruction. */
5053 struct tgsi_full_src_register one = make_immediate_reg_float(emit, 1.0f);
5054 begin_emit_instruction(emit);
5055 emit_opcode(emit, VGPU10_OPCODE_MOV, FALSE);
5056 emit_dst_register(emit, &inst->Dst[0]);
5057 emit_src_register(emit, &one);
5058 end_emit_instruction(emit);
5059 }
5060
5061 return valid;
5062 }
5063
5064
5065 /**
5066 * Emit code for TGSI_OPCODE_TEX (simple texture lookup)
5067 */
5068 static boolean
5069 emit_tex(struct svga_shader_emitter_v10 *emit,
5070 const struct tgsi_full_instruction *inst)
5071 {
5072 const uint unit = inst->Src[1].Register.Index;
5073 const enum tgsi_texture_type target = inst->Texture.Texture;
5074 VGPU10_OPCODE_TYPE opcode;
5075 struct tgsi_full_src_register coord;
5076 int offsets[3];
5077 struct tex_swizzle_info swz_info;
5078
5079 /* check that the sampler returns a float */
5080 if (!is_valid_tex_instruction(emit, inst))
5081 return TRUE;
5082
5083 begin_tex_swizzle(emit, unit, inst, FALSE, &swz_info);
5084
5085 get_texel_offsets(emit, inst, offsets);
5086
5087 coord = setup_texcoord(emit, unit, &inst->Src[0]);
5088
5089 /* SAMPLE dst, coord(s0), resource, sampler */
5090 begin_emit_instruction(emit);
5091
5092 if (tgsi_is_shadow_target(target))
5093 opcode = VGPU10_OPCODE_SAMPLE_C;
5094 else
5095 opcode = VGPU10_OPCODE_SAMPLE;
5096
5097 emit_sample_opcode(emit, opcode, inst->Instruction.Saturate, offsets);
5098 emit_dst_register(emit, get_tex_swizzle_dst(&swz_info));
5099 emit_src_register(emit, &coord);
5100 emit_resource_register(emit, unit);
5101 emit_sampler_register(emit, unit);
5102 if (opcode == VGPU10_OPCODE_SAMPLE_C) {
5103 emit_tex_compare_refcoord(emit, target, &coord);
5104 }
5105 end_emit_instruction(emit);
5106
5107 end_tex_swizzle(emit, &swz_info);
5108
5109 free_temp_indexes(emit);
5110
5111 return TRUE;
5112 }
5113
5114
5115 /**
5116 * Emit code for TGSI_OPCODE_TXP (projective texture)
5117 */
5118 static boolean
5119 emit_txp(struct svga_shader_emitter_v10 *emit,
5120 const struct tgsi_full_instruction *inst)
5121 {
5122 const uint unit = inst->Src[1].Register.Index;
5123 const enum tgsi_texture_type target = inst->Texture.Texture;
5124 VGPU10_OPCODE_TYPE opcode;
5125 int offsets[3];
5126 unsigned tmp = get_temp_index(emit);
5127 struct tgsi_full_src_register tmp_src = make_src_temp_reg(tmp);
5128 struct tgsi_full_dst_register tmp_dst = make_dst_temp_reg(tmp);
5129 struct tgsi_full_src_register src0_wwww =
5130 scalar_src(&inst->Src[0], TGSI_SWIZZLE_W);
5131 struct tgsi_full_src_register coord;
5132 struct tex_swizzle_info swz_info;
5133
5134 /* check that the sampler returns a float */
5135 if (!is_valid_tex_instruction(emit, inst))
5136 return TRUE;
5137
5138 begin_tex_swizzle(emit, unit, inst, FALSE, &swz_info);
5139
5140 get_texel_offsets(emit, inst, offsets);
5141
5142 coord = setup_texcoord(emit, unit, &inst->Src[0]);
5143
5144 /* DIV tmp, coord, coord.wwww */
5145 emit_instruction_op2(emit, VGPU10_OPCODE_DIV, &tmp_dst,
5146 &coord, &src0_wwww, FALSE);
5147
5148 /* SAMPLE dst, coord(tmp), resource, sampler */
5149 begin_emit_instruction(emit);
5150
5151 if (tgsi_is_shadow_target(target))
5152 /* NOTE: for non-fragment shaders, we should use
5153 * VGPU10_OPCODE_SAMPLE_C_LZ, but our virtual GPU accepts this as-is.
5154 */
5155 opcode = VGPU10_OPCODE_SAMPLE_C;
5156 else
5157 opcode = VGPU10_OPCODE_SAMPLE;
5158
5159 emit_sample_opcode(emit, opcode, inst->Instruction.Saturate, offsets);
5160 emit_dst_register(emit, get_tex_swizzle_dst(&swz_info));
5161 emit_src_register(emit, &tmp_src); /* projected coord */
5162 emit_resource_register(emit, unit);
5163 emit_sampler_register(emit, unit);
5164 if (opcode == VGPU10_OPCODE_SAMPLE_C) {
5165 emit_tex_compare_refcoord(emit, target, &tmp_src);
5166 }
5167 end_emit_instruction(emit);
5168
5169 end_tex_swizzle(emit, &swz_info);
5170
5171 free_temp_indexes(emit);
5172
5173 return TRUE;
5174 }
5175
5176
5177 /**
5178 * Emit code for TGSI_OPCODE_TXD (explicit derivatives)
5179 */
5180 static boolean
5181 emit_txd(struct svga_shader_emitter_v10 *emit,
5182 const struct tgsi_full_instruction *inst)
5183 {
5184 const uint unit = inst->Src[3].Register.Index;
5185 const enum tgsi_texture_type target = inst->Texture.Texture;
5186 int offsets[3];
5187 struct tgsi_full_src_register coord;
5188 struct tex_swizzle_info swz_info;
5189
5190 begin_tex_swizzle(emit, unit, inst, tgsi_is_shadow_target(target),
5191 &swz_info);
5192
5193 get_texel_offsets(emit, inst, offsets);
5194
5195 coord = setup_texcoord(emit, unit, &inst->Src[0]);
5196
5197 /* SAMPLE_D dst, coord(s0), resource, sampler, Xderiv(s1), Yderiv(s2) */
5198 begin_emit_instruction(emit);
5199 emit_sample_opcode(emit, VGPU10_OPCODE_SAMPLE_D,
5200 inst->Instruction.Saturate, offsets);
5201 emit_dst_register(emit, get_tex_swizzle_dst(&swz_info));
5202 emit_src_register(emit, &coord);
5203 emit_resource_register(emit, unit);
5204 emit_sampler_register(emit, unit);
5205 emit_src_register(emit, &inst->Src[1]); /* Xderiv */
5206 emit_src_register(emit, &inst->Src[2]); /* Yderiv */
5207 end_emit_instruction(emit);
5208
5209 end_tex_swizzle(emit, &swz_info);
5210
5211 free_temp_indexes(emit);
5212
5213 return TRUE;
5214 }
5215
5216
5217 /**
5218 * Emit code for TGSI_OPCODE_TXF (texel fetch)
5219 */
5220 static boolean
5221 emit_txf(struct svga_shader_emitter_v10 *emit,
5222 const struct tgsi_full_instruction *inst)
5223 {
5224 const uint unit = inst->Src[1].Register.Index;
5225 const boolean msaa = tgsi_is_msaa_target(inst->Texture.Texture);
5226 int offsets[3];
5227 struct tex_swizzle_info swz_info;
5228
5229 begin_tex_swizzle(emit, unit, inst, FALSE, &swz_info);
5230
5231 get_texel_offsets(emit, inst, offsets);
5232
5233 if (msaa) {
5234 /* Fetch one sample from an MSAA texture */
5235 struct tgsi_full_src_register sampleIndex =
5236 scalar_src(&inst->Src[0], TGSI_SWIZZLE_W);
5237 /* LD_MS dst, coord(s0), resource, sampleIndex */
5238 begin_emit_instruction(emit);
5239 emit_sample_opcode(emit, VGPU10_OPCODE_LD_MS,
5240 inst->Instruction.Saturate, offsets);
5241 emit_dst_register(emit, get_tex_swizzle_dst(&swz_info));
5242 emit_src_register(emit, &inst->Src[0]);
5243 emit_resource_register(emit, unit);
5244 emit_src_register(emit, &sampleIndex);
5245 end_emit_instruction(emit);
5246 }
5247 else {
5248 /* Fetch one texel specified by integer coordinate */
5249 /* LD dst, coord(s0), resource */
5250 begin_emit_instruction(emit);
5251 emit_sample_opcode(emit, VGPU10_OPCODE_LD,
5252 inst->Instruction.Saturate, offsets);
5253 emit_dst_register(emit, get_tex_swizzle_dst(&swz_info));
5254 emit_src_register(emit, &inst->Src[0]);
5255 emit_resource_register(emit, unit);
5256 end_emit_instruction(emit);
5257 }
5258
5259 end_tex_swizzle(emit, &swz_info);
5260
5261 free_temp_indexes(emit);
5262
5263 return TRUE;
5264 }
5265
5266
5267 /**
5268 * Emit code for TGSI_OPCODE_TXL (explicit LOD) or TGSI_OPCODE_TXB (LOD bias)
5269 * or TGSI_OPCODE_TXB2 (for cube shadow maps).
5270 */
5271 static boolean
5272 emit_txl_txb(struct svga_shader_emitter_v10 *emit,
5273 const struct tgsi_full_instruction *inst)
5274 {
5275 const enum tgsi_texture_type target = inst->Texture.Texture;
5276 VGPU10_OPCODE_TYPE opcode;
5277 unsigned unit;
5278 int offsets[3];
5279 struct tgsi_full_src_register coord, lod_bias;
5280 struct tex_swizzle_info swz_info;
5281
5282 assert(inst->Instruction.Opcode == TGSI_OPCODE_TXL ||
5283 inst->Instruction.Opcode == TGSI_OPCODE_TXB ||
5284 inst->Instruction.Opcode == TGSI_OPCODE_TXB2);
5285
5286 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB2) {
5287 lod_bias = scalar_src(&inst->Src[1], TGSI_SWIZZLE_X);
5288 unit = inst->Src[2].Register.Index;
5289 }
5290 else {
5291 lod_bias = scalar_src(&inst->Src[0], TGSI_SWIZZLE_W);
5292 unit = inst->Src[1].Register.Index;
5293 }
5294
5295 begin_tex_swizzle(emit, unit, inst, tgsi_is_shadow_target(target),
5296 &swz_info);
5297
5298 get_texel_offsets(emit, inst, offsets);
5299
5300 coord = setup_texcoord(emit, unit, &inst->Src[0]);
5301
5302 /* SAMPLE_L/B dst, coord(s0), resource, sampler, lod(s3) */
5303 begin_emit_instruction(emit);
5304 if (inst->Instruction.Opcode == TGSI_OPCODE_TXL) {
5305 opcode = VGPU10_OPCODE_SAMPLE_L;
5306 }
5307 else {
5308 opcode = VGPU10_OPCODE_SAMPLE_B;
5309 }
5310 emit_sample_opcode(emit, opcode, inst->Instruction.Saturate, offsets);
5311 emit_dst_register(emit, get_tex_swizzle_dst(&swz_info));
5312 emit_src_register(emit, &coord);
5313 emit_resource_register(emit, unit);
5314 emit_sampler_register(emit, unit);
5315 emit_src_register(emit, &lod_bias);
5316 end_emit_instruction(emit);
5317
5318 end_tex_swizzle(emit, &swz_info);
5319
5320 free_temp_indexes(emit);
5321
5322 return TRUE;
5323 }
5324
5325
5326 /**
5327 * Emit code for TGSI_OPCODE_TXL2 (explicit LOD) for cubemap array.
5328 */
5329 static boolean
5330 emit_txl2(struct svga_shader_emitter_v10 *emit,
5331 const struct tgsi_full_instruction *inst)
5332 {
5333 unsigned target = inst->Texture.Texture;
5334 unsigned opcode, unit;
5335 int offsets[3];
5336 struct tgsi_full_src_register coord, lod;
5337 struct tex_swizzle_info swz_info;
5338
5339 assert(inst->Instruction.Opcode == TGSI_OPCODE_TXL2);
5340
5341 lod = scalar_src(&inst->Src[1], TGSI_SWIZZLE_X);
5342 unit = inst->Src[2].Register.Index;
5343
5344 begin_tex_swizzle(emit, unit, inst, tgsi_is_shadow_target(target),
5345 &swz_info);
5346
5347 get_texel_offsets(emit, inst, offsets);
5348
5349 coord = setup_texcoord(emit, unit, &inst->Src[0]);
5350
5351 /* SAMPLE_L dst, coord(s0), resource, sampler, lod(s3) */
5352 begin_emit_instruction(emit);
5353 opcode = VGPU10_OPCODE_SAMPLE_L;
5354 emit_sample_opcode(emit, opcode, inst->Instruction.Saturate, offsets);
5355 emit_dst_register(emit, get_tex_swizzle_dst(&swz_info));
5356 emit_src_register(emit, &coord);
5357 emit_resource_register(emit, unit);
5358 emit_sampler_register(emit, unit);
5359 emit_src_register(emit, &lod);
5360 end_emit_instruction(emit);
5361
5362 end_tex_swizzle(emit, &swz_info);
5363
5364 free_temp_indexes(emit);
5365
5366 return TRUE;
5367 }
5368
5369
5370 /**
5371 * Emit code for TGSI_OPCODE_TXQ (texture query) instruction.
5372 */
5373 static boolean
5374 emit_txq(struct svga_shader_emitter_v10 *emit,
5375 const struct tgsi_full_instruction *inst)
5376 {
5377 const uint unit = inst->Src[1].Register.Index;
5378
5379 if (emit->sampler_target[unit] == TGSI_TEXTURE_BUFFER) {
5380 /* RESINFO does not support querying texture buffers, so we instead
5381 * store texture buffer sizes in shader constants, then copy them to
5382 * implement TXQ instead of emitting RESINFO.
5383 * MOV dst, const[texture_buffer_size_index[unit]]
5384 */
5385 struct tgsi_full_src_register size_src =
5386 make_src_const_reg(emit->texture_buffer_size_index[unit]);
5387 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &inst->Dst[0], &size_src,
5388 FALSE);
5389 } else {
5390 /* RESINFO dst, srcMipLevel, resource */
5391 begin_emit_instruction(emit);
5392 emit_opcode_resinfo(emit, VGPU10_RESINFO_RETURN_UINT);
5393 emit_dst_register(emit, &inst->Dst[0]);
5394 emit_src_register(emit, &inst->Src[0]);
5395 emit_resource_register(emit, unit);
5396 end_emit_instruction(emit);
5397 }
5398
5399 free_temp_indexes(emit);
5400
5401 return TRUE;
5402 }
5403
5404
5405 /**
5406 * Emit a simple instruction (like ADD, MUL, MIN, etc).
5407 */
5408 static boolean
5409 emit_simple(struct svga_shader_emitter_v10 *emit,
5410 const struct tgsi_full_instruction *inst)
5411 {
5412 const enum tgsi_opcode opcode = inst->Instruction.Opcode;
5413 const struct tgsi_opcode_info *op = tgsi_get_opcode_info(opcode);
5414 unsigned i;
5415
5416 begin_emit_instruction(emit);
5417 emit_opcode(emit, translate_opcode(opcode), inst->Instruction.Saturate);
5418 for (i = 0; i < op->num_dst; i++) {
5419 emit_dst_register(emit, &inst->Dst[i]);
5420 }
5421 for (i = 0; i < op->num_src; i++) {
5422 emit_src_register(emit, &inst->Src[i]);
5423 }
5424 end_emit_instruction(emit);
5425
5426 return TRUE;
5427 }
5428
5429
5430 /**
5431 * We only special case the MOV instruction to try to detect constant
5432 * color writes in the fragment shader.
5433 */
5434 static boolean
5435 emit_mov(struct svga_shader_emitter_v10 *emit,
5436 const struct tgsi_full_instruction *inst)
5437 {
5438 const struct tgsi_full_src_register *src = &inst->Src[0];
5439 const struct tgsi_full_dst_register *dst = &inst->Dst[0];
5440
5441 if (emit->unit == PIPE_SHADER_FRAGMENT &&
5442 dst->Register.File == TGSI_FILE_OUTPUT &&
5443 dst->Register.Index == 0 &&
5444 src->Register.File == TGSI_FILE_CONSTANT &&
5445 !src->Register.Indirect) {
5446 emit->constant_color_output = TRUE;
5447 }
5448
5449 return emit_simple(emit, inst);
5450 }
5451
5452
5453 /**
5454 * Emit a simple VGPU10 instruction which writes to multiple dest registers,
5455 * where TGSI only uses one dest register.
5456 */
5457 static boolean
5458 emit_simple_1dst(struct svga_shader_emitter_v10 *emit,
5459 const struct tgsi_full_instruction *inst,
5460 unsigned dst_count,
5461 unsigned dst_index)
5462 {
5463 const enum tgsi_opcode opcode = inst->Instruction.Opcode;
5464 const struct tgsi_opcode_info *op = tgsi_get_opcode_info(opcode);
5465 unsigned i;
5466
5467 begin_emit_instruction(emit);
5468 emit_opcode(emit, translate_opcode(opcode), inst->Instruction.Saturate);
5469
5470 for (i = 0; i < dst_count; i++) {
5471 if (i == dst_index) {
5472 emit_dst_register(emit, &inst->Dst[0]);
5473 } else {
5474 emit_null_dst_register(emit);
5475 }
5476 }
5477
5478 for (i = 0; i < op->num_src; i++) {
5479 emit_src_register(emit, &inst->Src[i]);
5480 }
5481 end_emit_instruction(emit);
5482
5483 return TRUE;
5484 }
5485
5486
5487 /**
5488 * Translate a single TGSI instruction to VGPU10.
5489 */
5490 static boolean
5491 emit_vgpu10_instruction(struct svga_shader_emitter_v10 *emit,
5492 unsigned inst_number,
5493 const struct tgsi_full_instruction *inst)
5494 {
5495 const enum tgsi_opcode opcode = inst->Instruction.Opcode;
5496
5497 switch (opcode) {
5498 case TGSI_OPCODE_ADD:
5499 case TGSI_OPCODE_AND:
5500 case TGSI_OPCODE_BGNLOOP:
5501 case TGSI_OPCODE_BRK:
5502 case TGSI_OPCODE_CEIL:
5503 case TGSI_OPCODE_CONT:
5504 case TGSI_OPCODE_DDX:
5505 case TGSI_OPCODE_DDY:
5506 case TGSI_OPCODE_DIV:
5507 case TGSI_OPCODE_DP2:
5508 case TGSI_OPCODE_DP3:
5509 case TGSI_OPCODE_DP4:
5510 case TGSI_OPCODE_ELSE:
5511 case TGSI_OPCODE_ENDIF:
5512 case TGSI_OPCODE_ENDLOOP:
5513 case TGSI_OPCODE_ENDSUB:
5514 case TGSI_OPCODE_F2I:
5515 case TGSI_OPCODE_F2U:
5516 case TGSI_OPCODE_FLR:
5517 case TGSI_OPCODE_FRC:
5518 case TGSI_OPCODE_FSEQ:
5519 case TGSI_OPCODE_FSGE:
5520 case TGSI_OPCODE_FSLT:
5521 case TGSI_OPCODE_FSNE:
5522 case TGSI_OPCODE_I2F:
5523 case TGSI_OPCODE_IMAX:
5524 case TGSI_OPCODE_IMIN:
5525 case TGSI_OPCODE_INEG:
5526 case TGSI_OPCODE_ISGE:
5527 case TGSI_OPCODE_ISHR:
5528 case TGSI_OPCODE_ISLT:
5529 case TGSI_OPCODE_MAD:
5530 case TGSI_OPCODE_MAX:
5531 case TGSI_OPCODE_MIN:
5532 case TGSI_OPCODE_MUL:
5533 case TGSI_OPCODE_NOP:
5534 case TGSI_OPCODE_NOT:
5535 case TGSI_OPCODE_OR:
5536 case TGSI_OPCODE_RET:
5537 case TGSI_OPCODE_UADD:
5538 case TGSI_OPCODE_USEQ:
5539 case TGSI_OPCODE_USGE:
5540 case TGSI_OPCODE_USLT:
5541 case TGSI_OPCODE_UMIN:
5542 case TGSI_OPCODE_UMAD:
5543 case TGSI_OPCODE_UMAX:
5544 case TGSI_OPCODE_ROUND:
5545 case TGSI_OPCODE_SQRT:
5546 case TGSI_OPCODE_SHL:
5547 case TGSI_OPCODE_TRUNC:
5548 case TGSI_OPCODE_U2F:
5549 case TGSI_OPCODE_UCMP:
5550 case TGSI_OPCODE_USHR:
5551 case TGSI_OPCODE_USNE:
5552 case TGSI_OPCODE_XOR:
5553 /* simple instructions */
5554 return emit_simple(emit, inst);
5555
5556 case TGSI_OPCODE_MOV:
5557 return emit_mov(emit, inst);
5558 case TGSI_OPCODE_EMIT:
5559 return emit_vertex(emit, inst);
5560 case TGSI_OPCODE_ENDPRIM:
5561 return emit_endprim(emit, inst);
5562 case TGSI_OPCODE_IABS:
5563 return emit_iabs(emit, inst);
5564 case TGSI_OPCODE_ARL:
5565 /* fall-through */
5566 case TGSI_OPCODE_UARL:
5567 return emit_arl_uarl(emit, inst);
5568 case TGSI_OPCODE_BGNSUB:
5569 /* no-op */
5570 return TRUE;
5571 case TGSI_OPCODE_CAL:
5572 return emit_cal(emit, inst);
5573 case TGSI_OPCODE_CMP:
5574 return emit_cmp(emit, inst);
5575 case TGSI_OPCODE_COS:
5576 return emit_sincos(emit, inst);
5577 case TGSI_OPCODE_DST:
5578 return emit_dst(emit, inst);
5579 case TGSI_OPCODE_EX2:
5580 return emit_ex2(emit, inst);
5581 case TGSI_OPCODE_EXP:
5582 return emit_exp(emit, inst);
5583 case TGSI_OPCODE_IF:
5584 return emit_if(emit, inst);
5585 case TGSI_OPCODE_KILL:
5586 return emit_kill(emit, inst);
5587 case TGSI_OPCODE_KILL_IF:
5588 return emit_kill_if(emit, inst);
5589 case TGSI_OPCODE_LG2:
5590 return emit_lg2(emit, inst);
5591 case TGSI_OPCODE_LIT:
5592 return emit_lit(emit, inst);
5593 case TGSI_OPCODE_LOG:
5594 return emit_log(emit, inst);
5595 case TGSI_OPCODE_LRP:
5596 return emit_lrp(emit, inst);
5597 case TGSI_OPCODE_POW:
5598 return emit_pow(emit, inst);
5599 case TGSI_OPCODE_RCP:
5600 return emit_rcp(emit, inst);
5601 case TGSI_OPCODE_RSQ:
5602 return emit_rsq(emit, inst);
5603 case TGSI_OPCODE_SAMPLE:
5604 return emit_sample(emit, inst);
5605 case TGSI_OPCODE_SEQ:
5606 return emit_seq(emit, inst);
5607 case TGSI_OPCODE_SGE:
5608 return emit_sge(emit, inst);
5609 case TGSI_OPCODE_SGT:
5610 return emit_sgt(emit, inst);
5611 case TGSI_OPCODE_SIN:
5612 return emit_sincos(emit, inst);
5613 case TGSI_OPCODE_SLE:
5614 return emit_sle(emit, inst);
5615 case TGSI_OPCODE_SLT:
5616 return emit_slt(emit, inst);
5617 case TGSI_OPCODE_SNE:
5618 return emit_sne(emit, inst);
5619 case TGSI_OPCODE_SSG:
5620 return emit_ssg(emit, inst);
5621 case TGSI_OPCODE_ISSG:
5622 return emit_issg(emit, inst);
5623 case TGSI_OPCODE_TEX:
5624 return emit_tex(emit, inst);
5625 case TGSI_OPCODE_TXP:
5626 return emit_txp(emit, inst);
5627 case TGSI_OPCODE_TXB:
5628 case TGSI_OPCODE_TXB2:
5629 case TGSI_OPCODE_TXL:
5630 return emit_txl_txb(emit, inst);
5631 case TGSI_OPCODE_TXD:
5632 return emit_txd(emit, inst);
5633 case TGSI_OPCODE_TXF:
5634 return emit_txf(emit, inst);
5635 case TGSI_OPCODE_TXL2:
5636 return emit_txl2(emit, inst);
5637 case TGSI_OPCODE_TXQ:
5638 return emit_txq(emit, inst);
5639 case TGSI_OPCODE_UIF:
5640 return emit_if(emit, inst);
5641 case TGSI_OPCODE_UMUL_HI:
5642 case TGSI_OPCODE_IMUL_HI:
5643 case TGSI_OPCODE_UDIV:
5644 case TGSI_OPCODE_IDIV:
5645 /* These cases use only the FIRST of two destination registers */
5646 return emit_simple_1dst(emit, inst, 2, 0);
5647 case TGSI_OPCODE_UMUL:
5648 case TGSI_OPCODE_UMOD:
5649 case TGSI_OPCODE_MOD:
5650 /* These cases use only the SECOND of two destination registers */
5651 return emit_simple_1dst(emit, inst, 2, 1);
5652 case TGSI_OPCODE_END:
5653 if (!emit_post_helpers(emit))
5654 return FALSE;
5655 return emit_simple(emit, inst);
5656
5657 default:
5658 debug_printf("Unimplemented tgsi instruction %s\n",
5659 tgsi_get_opcode_name(opcode));
5660 return FALSE;
5661 }
5662
5663 return TRUE;
5664 }
5665
5666
5667 /**
5668 * Emit the extra instructions to adjust the vertex position.
5669 * There are two possible adjustments:
5670 * 1. Converting from Gallium to VGPU10 coordinate space by applying the
5671 * "prescale" and "pretranslate" values.
5672 * 2. Undoing the viewport transformation when we use the swtnl/draw path.
5673 * \param vs_pos_tmp_index which temporary register contains the vertex pos.
5674 */
5675 static void
5676 emit_vpos_instructions(struct svga_shader_emitter_v10 *emit,
5677 unsigned vs_pos_tmp_index)
5678 {
5679 struct tgsi_full_src_register tmp_pos_src;
5680 struct tgsi_full_dst_register pos_dst;
5681
5682 /* Don't bother to emit any extra vertex instructions if vertex position is
5683 * not written out
5684 */
5685 if (emit->vposition.out_index == INVALID_INDEX)
5686 return;
5687
5688 tmp_pos_src = make_src_temp_reg(vs_pos_tmp_index);
5689 pos_dst = make_dst_output_reg(emit->vposition.out_index);
5690
5691 /* If non-adjusted vertex position register index
5692 * is valid, copy the vertex position from the temporary
5693 * vertex position register before it is modified by the
5694 * prescale computation.
5695 */
5696 if (emit->vposition.so_index != INVALID_INDEX) {
5697 struct tgsi_full_dst_register pos_so_dst =
5698 make_dst_output_reg(emit->vposition.so_index);
5699
5700 /* MOV pos_so, tmp_pos */
5701 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &pos_so_dst,
5702 &tmp_pos_src, FALSE);
5703 }
5704
5705 if (emit->vposition.need_prescale) {
5706 /* This code adjusts the vertex position to match the VGPU10 convention.
5707 * If p is the position computed by the shader (usually by applying the
5708 * modelview and projection matrices), the new position q is computed by:
5709 *
5710 * q.x = p.w * trans.x + p.x * scale.x
5711 * q.y = p.w * trans.y + p.y * scale.y
5712 * q.z = p.w * trans.z + p.z * scale.z;
5713 * q.w = p.w * trans.w + p.w;
5714 */
5715 struct tgsi_full_src_register tmp_pos_src_w =
5716 scalar_src(&tmp_pos_src, TGSI_SWIZZLE_W);
5717 struct tgsi_full_dst_register tmp_pos_dst =
5718 make_dst_temp_reg(vs_pos_tmp_index);
5719 struct tgsi_full_dst_register tmp_pos_dst_xyz =
5720 writemask_dst(&tmp_pos_dst, TGSI_WRITEMASK_XYZ);
5721
5722 struct tgsi_full_src_register prescale_scale =
5723 make_src_const_reg(emit->vposition.prescale_scale_index);
5724 struct tgsi_full_src_register prescale_trans =
5725 make_src_const_reg(emit->vposition.prescale_trans_index);
5726
5727 /* MUL tmp_pos.xyz, tmp_pos, prescale.scale */
5728 emit_instruction_op2(emit, VGPU10_OPCODE_MUL, &tmp_pos_dst_xyz,
5729 &tmp_pos_src, &prescale_scale, FALSE);
5730
5731 /* MAD pos, tmp_pos.wwww, prescale.trans, tmp_pos */
5732 emit_instruction_op3(emit, VGPU10_OPCODE_MAD, &pos_dst, &tmp_pos_src_w,
5733 &prescale_trans, &tmp_pos_src, FALSE);
5734 }
5735 else if (emit->key.vs.undo_viewport) {
5736 /* This code computes the final vertex position from the temporary
5737 * vertex position by undoing the viewport transformation and the
5738 * divide-by-W operation (we convert window coords back to clip coords).
5739 * This is needed when we use the 'draw' module for fallbacks.
5740 * If p is the temp pos in window coords, then the NDC coord q is:
5741 * q.x = (p.x - vp.x_trans) / vp.x_scale * p.w
5742 * q.y = (p.y - vp.y_trans) / vp.y_scale * p.w
5743 * q.z = p.z * p.w
5744 * q.w = p.w
5745 * CONST[vs_viewport_index] contains:
5746 * { 1/vp.x_scale, 1/vp.y_scale, -vp.x_trans, -vp.y_trans }
5747 */
5748 struct tgsi_full_dst_register tmp_pos_dst =
5749 make_dst_temp_reg(vs_pos_tmp_index);
5750 struct tgsi_full_dst_register tmp_pos_dst_xy =
5751 writemask_dst(&tmp_pos_dst, TGSI_WRITEMASK_XY);
5752 struct tgsi_full_src_register tmp_pos_src_wwww =
5753 scalar_src(&tmp_pos_src, TGSI_SWIZZLE_W);
5754
5755 struct tgsi_full_dst_register pos_dst_xyz =
5756 writemask_dst(&pos_dst, TGSI_WRITEMASK_XYZ);
5757 struct tgsi_full_dst_register pos_dst_w =
5758 writemask_dst(&pos_dst, TGSI_WRITEMASK_W);
5759
5760 struct tgsi_full_src_register vp_xyzw =
5761 make_src_const_reg(emit->vs.viewport_index);
5762 struct tgsi_full_src_register vp_zwww =
5763 swizzle_src(&vp_xyzw, TGSI_SWIZZLE_Z, TGSI_SWIZZLE_W,
5764 TGSI_SWIZZLE_W, TGSI_SWIZZLE_W);
5765
5766 /* ADD tmp_pos.xy, tmp_pos.xy, viewport.zwww */
5767 emit_instruction_op2(emit, VGPU10_OPCODE_ADD, &tmp_pos_dst_xy,
5768 &tmp_pos_src, &vp_zwww, FALSE);
5769
5770 /* MUL tmp_pos.xy, tmp_pos.xyzw, viewport.xyzy */
5771 emit_instruction_op2(emit, VGPU10_OPCODE_MUL, &tmp_pos_dst_xy,
5772 &tmp_pos_src, &vp_xyzw, FALSE);
5773
5774 /* MUL pos.xyz, tmp_pos.xyz, tmp_pos.www */
5775 emit_instruction_op2(emit, VGPU10_OPCODE_MUL, &pos_dst_xyz,
5776 &tmp_pos_src, &tmp_pos_src_wwww, FALSE);
5777
5778 /* MOV pos.w, tmp_pos.w */
5779 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &pos_dst_w,
5780 &tmp_pos_src, FALSE);
5781 }
5782 else if (vs_pos_tmp_index != INVALID_INDEX) {
5783 /* This code is to handle the case where the temporary vertex
5784 * position register is created when the vertex shader has stream
5785 * output and prescale is disabled because rasterization is to be
5786 * discarded.
5787 */
5788 struct tgsi_full_dst_register pos_dst =
5789 make_dst_output_reg(emit->vposition.out_index);
5790
5791 /* MOV pos, tmp_pos */
5792 begin_emit_instruction(emit);
5793 emit_opcode(emit, VGPU10_OPCODE_MOV, FALSE);
5794 emit_dst_register(emit, &pos_dst);
5795 emit_src_register(emit, &tmp_pos_src);
5796 end_emit_instruction(emit);
5797 }
5798 }
5799
5800 static void
5801 emit_clipping_instructions(struct svga_shader_emitter_v10 *emit)
5802 {
5803 if (emit->clip_mode == CLIP_DISTANCE) {
5804 /* Copy from copy distance temporary to CLIPDIST & the shadow copy */
5805 emit_clip_distance_instructions(emit);
5806
5807 } else if (emit->clip_mode == CLIP_VERTEX) {
5808 /* Convert TGSI CLIPVERTEX to CLIPDIST */
5809 emit_clip_vertex_instructions(emit);
5810 }
5811
5812 /**
5813 * Emit vertex position and take care of legacy user planes only if
5814 * there is a valid vertex position register index.
5815 * This is to take care of the case
5816 * where the shader doesn't output vertex position. Then in
5817 * this case, don't bother to emit more vertex instructions.
5818 */
5819 if (emit->vposition.out_index == INVALID_INDEX)
5820 return;
5821
5822 /**
5823 * Emit per-vertex clipping instructions for legacy user defined clip planes.
5824 * NOTE: we must emit the clip distance instructions before the
5825 * emit_vpos_instructions() call since the later function will change
5826 * the TEMP[vs_pos_tmp_index] value.
5827 */
5828 if (emit->clip_mode == CLIP_LEGACY) {
5829 /* Emit CLIPDIST for legacy user defined clip planes */
5830 emit_clip_distance_from_vpos(emit, emit->vposition.tmp_index);
5831 }
5832 }
5833
5834
5835 /**
5836 * Emit extra per-vertex instructions. This includes clip-coordinate
5837 * space conversion and computing clip distances. This is called for
5838 * each GS emit-vertex instruction and at the end of VS translation.
5839 */
5840 static void
5841 emit_vertex_instructions(struct svga_shader_emitter_v10 *emit)
5842 {
5843 const unsigned vs_pos_tmp_index = emit->vposition.tmp_index;
5844
5845 /* Emit clipping instructions based on clipping mode */
5846 emit_clipping_instructions(emit);
5847
5848 /**
5849 * Reset the temporary vertex position register index
5850 * so that emit_dst_register() will use the real vertex position output
5851 */
5852 emit->vposition.tmp_index = INVALID_INDEX;
5853
5854 /* Emit vertex position instructions */
5855 emit_vpos_instructions(emit, vs_pos_tmp_index);
5856
5857 /* Restore original vposition.tmp_index value for the next GS vertex.
5858 * It doesn't matter for VS.
5859 */
5860 emit->vposition.tmp_index = vs_pos_tmp_index;
5861 }
5862
5863 /**
5864 * Translate the TGSI_OPCODE_EMIT GS instruction.
5865 */
5866 static boolean
5867 emit_vertex(struct svga_shader_emitter_v10 *emit,
5868 const struct tgsi_full_instruction *inst)
5869 {
5870 unsigned ret = TRUE;
5871
5872 assert(emit->unit == PIPE_SHADER_GEOMETRY);
5873
5874 emit_vertex_instructions(emit);
5875
5876 /* We can't use emit_simple() because the TGSI instruction has one
5877 * operand (vertex stream number) which we must ignore for VGPU10.
5878 */
5879 begin_emit_instruction(emit);
5880 emit_opcode(emit, VGPU10_OPCODE_EMIT, FALSE);
5881 end_emit_instruction(emit);
5882
5883 return ret;
5884 }
5885
5886
5887 /**
5888 * Emit the extra code to convert from VGPU10's boolean front-face
5889 * register to TGSI's signed front-face register.
5890 *
5891 * TODO: Make temporary front-face register a scalar.
5892 */
5893 static void
5894 emit_frontface_instructions(struct svga_shader_emitter_v10 *emit)
5895 {
5896 assert(emit->unit == PIPE_SHADER_FRAGMENT);
5897
5898 if (emit->fs.face_input_index != INVALID_INDEX) {
5899 /* convert vgpu10 boolean face register to gallium +/-1 value */
5900 struct tgsi_full_dst_register tmp_dst =
5901 make_dst_temp_reg(emit->fs.face_tmp_index);
5902 struct tgsi_full_src_register one =
5903 make_immediate_reg_float(emit, 1.0f);
5904 struct tgsi_full_src_register neg_one =
5905 make_immediate_reg_float(emit, -1.0f);
5906
5907 /* MOVC face_tmp, IS_FRONT_FACE.x, 1.0, -1.0 */
5908 begin_emit_instruction(emit);
5909 emit_opcode(emit, VGPU10_OPCODE_MOVC, FALSE);
5910 emit_dst_register(emit, &tmp_dst);
5911 emit_face_register(emit);
5912 emit_src_register(emit, &one);
5913 emit_src_register(emit, &neg_one);
5914 end_emit_instruction(emit);
5915 }
5916 }
5917
5918
5919 /**
5920 * Emit the extra code to convert from VGPU10's fragcoord.w value to 1/w.
5921 */
5922 static void
5923 emit_fragcoord_instructions(struct svga_shader_emitter_v10 *emit)
5924 {
5925 assert(emit->unit == PIPE_SHADER_FRAGMENT);
5926
5927 if (emit->fs.fragcoord_input_index != INVALID_INDEX) {
5928 struct tgsi_full_dst_register tmp_dst =
5929 make_dst_temp_reg(emit->fs.fragcoord_tmp_index);
5930 struct tgsi_full_dst_register tmp_dst_xyz =
5931 writemask_dst(&tmp_dst, TGSI_WRITEMASK_XYZ);
5932 struct tgsi_full_dst_register tmp_dst_w =
5933 writemask_dst(&tmp_dst, TGSI_WRITEMASK_W);
5934 struct tgsi_full_src_register one =
5935 make_immediate_reg_float(emit, 1.0f);
5936 struct tgsi_full_src_register fragcoord =
5937 make_src_reg(TGSI_FILE_INPUT, emit->fs.fragcoord_input_index);
5938
5939 /* save the input index */
5940 unsigned fragcoord_input_index = emit->fs.fragcoord_input_index;
5941 /* set to invalid to prevent substitution in emit_src_register() */
5942 emit->fs.fragcoord_input_index = INVALID_INDEX;
5943
5944 /* MOV fragcoord_tmp.xyz, fragcoord.xyz */
5945 begin_emit_instruction(emit);
5946 emit_opcode(emit, VGPU10_OPCODE_MOV, FALSE);
5947 emit_dst_register(emit, &tmp_dst_xyz);
5948 emit_src_register(emit, &fragcoord);
5949 end_emit_instruction(emit);
5950
5951 /* DIV fragcoord_tmp.w, 1.0, fragcoord.w */
5952 begin_emit_instruction(emit);
5953 emit_opcode(emit, VGPU10_OPCODE_DIV, FALSE);
5954 emit_dst_register(emit, &tmp_dst_w);
5955 emit_src_register(emit, &one);
5956 emit_src_register(emit, &fragcoord);
5957 end_emit_instruction(emit);
5958
5959 /* restore saved value */
5960 emit->fs.fragcoord_input_index = fragcoord_input_index;
5961 }
5962 }
5963
5964
5965 /**
5966 * Emit extra instructions to adjust VS inputs/attributes. This can
5967 * mean casting a vertex attribute from int to float or setting the
5968 * W component to 1, or both.
5969 */
5970 static void
5971 emit_vertex_attrib_instructions(struct svga_shader_emitter_v10 *emit)
5972 {
5973 const unsigned save_w_1_mask = emit->key.vs.adjust_attrib_w_1;
5974 const unsigned save_itof_mask = emit->key.vs.adjust_attrib_itof;
5975 const unsigned save_utof_mask = emit->key.vs.adjust_attrib_utof;
5976 const unsigned save_is_bgra_mask = emit->key.vs.attrib_is_bgra;
5977 const unsigned save_puint_to_snorm_mask = emit->key.vs.attrib_puint_to_snorm;
5978 const unsigned save_puint_to_uscaled_mask = emit->key.vs.attrib_puint_to_uscaled;
5979 const unsigned save_puint_to_sscaled_mask = emit->key.vs.attrib_puint_to_sscaled;
5980
5981 unsigned adjust_mask = (save_w_1_mask |
5982 save_itof_mask |
5983 save_utof_mask |
5984 save_is_bgra_mask |
5985 save_puint_to_snorm_mask |
5986 save_puint_to_uscaled_mask |
5987 save_puint_to_sscaled_mask);
5988
5989 assert(emit->unit == PIPE_SHADER_VERTEX);
5990
5991 if (adjust_mask) {
5992 struct tgsi_full_src_register one =
5993 make_immediate_reg_float(emit, 1.0f);
5994
5995 struct tgsi_full_src_register one_int =
5996 make_immediate_reg_int(emit, 1);
5997
5998 /* We need to turn off these bitmasks while emitting the
5999 * instructions below, then restore them afterward.
6000 */
6001 emit->key.vs.adjust_attrib_w_1 = 0;
6002 emit->key.vs.adjust_attrib_itof = 0;
6003 emit->key.vs.adjust_attrib_utof = 0;
6004 emit->key.vs.attrib_is_bgra = 0;
6005 emit->key.vs.attrib_puint_to_snorm = 0;
6006 emit->key.vs.attrib_puint_to_uscaled = 0;
6007 emit->key.vs.attrib_puint_to_sscaled = 0;
6008
6009 while (adjust_mask) {
6010 unsigned index = u_bit_scan(&adjust_mask);
6011
6012 /* skip the instruction if this vertex attribute is not being used */
6013 if (emit->info.input_usage_mask[index] == 0)
6014 continue;
6015
6016 unsigned tmp = emit->vs.adjusted_input[index];
6017 struct tgsi_full_src_register input_src =
6018 make_src_reg(TGSI_FILE_INPUT, index);
6019
6020 struct tgsi_full_dst_register tmp_dst = make_dst_temp_reg(tmp);
6021 struct tgsi_full_src_register tmp_src = make_src_temp_reg(tmp);
6022 struct tgsi_full_dst_register tmp_dst_w =
6023 writemask_dst(&tmp_dst, TGSI_WRITEMASK_W);
6024
6025 /* ITOF/UTOF/MOV tmp, input[index] */
6026 if (save_itof_mask & (1 << index)) {
6027 emit_instruction_op1(emit, VGPU10_OPCODE_ITOF,
6028 &tmp_dst, &input_src, FALSE);
6029 }
6030 else if (save_utof_mask & (1 << index)) {
6031 emit_instruction_op1(emit, VGPU10_OPCODE_UTOF,
6032 &tmp_dst, &input_src, FALSE);
6033 }
6034 else if (save_puint_to_snorm_mask & (1 << index)) {
6035 emit_puint_to_snorm(emit, &tmp_dst, &input_src);
6036 }
6037 else if (save_puint_to_uscaled_mask & (1 << index)) {
6038 emit_puint_to_uscaled(emit, &tmp_dst, &input_src);
6039 }
6040 else if (save_puint_to_sscaled_mask & (1 << index)) {
6041 emit_puint_to_sscaled(emit, &tmp_dst, &input_src);
6042 }
6043 else {
6044 assert((save_w_1_mask | save_is_bgra_mask) & (1 << index));
6045 emit_instruction_op1(emit, VGPU10_OPCODE_MOV,
6046 &tmp_dst, &input_src, FALSE);
6047 }
6048
6049 if (save_is_bgra_mask & (1 << index)) {
6050 emit_swap_r_b(emit, &tmp_dst, &tmp_src);
6051 }
6052
6053 if (save_w_1_mask & (1 << index)) {
6054 /* MOV tmp.w, 1.0 */
6055 if (emit->key.vs.attrib_is_pure_int & (1 << index)) {
6056 emit_instruction_op1(emit, VGPU10_OPCODE_MOV,
6057 &tmp_dst_w, &one_int, FALSE);
6058 }
6059 else {
6060 emit_instruction_op1(emit, VGPU10_OPCODE_MOV,
6061 &tmp_dst_w, &one, FALSE);
6062 }
6063 }
6064 }
6065
6066 emit->key.vs.adjust_attrib_w_1 = save_w_1_mask;
6067 emit->key.vs.adjust_attrib_itof = save_itof_mask;
6068 emit->key.vs.adjust_attrib_utof = save_utof_mask;
6069 emit->key.vs.attrib_is_bgra = save_is_bgra_mask;
6070 emit->key.vs.attrib_puint_to_snorm = save_puint_to_snorm_mask;
6071 emit->key.vs.attrib_puint_to_uscaled = save_puint_to_uscaled_mask;
6072 emit->key.vs.attrib_puint_to_sscaled = save_puint_to_sscaled_mask;
6073 }
6074 }
6075
6076
6077 /**
6078 * Some common values like 0.0, 1.0, 0.5, etc. are frequently needed
6079 * to implement some instructions. We pre-allocate those values here
6080 * in the immediate constant buffer.
6081 */
6082 static void
6083 alloc_common_immediates(struct svga_shader_emitter_v10 *emit)
6084 {
6085 unsigned n = 0;
6086
6087 emit->common_immediate_pos[n++] =
6088 alloc_immediate_float4(emit, 0.0f, 1.0f, 0.5f, -1.0f);
6089
6090 if (emit->info.opcode_count[TGSI_OPCODE_LIT] > 0) {
6091 emit->common_immediate_pos[n++] =
6092 alloc_immediate_float4(emit, 128.0f, -128.0f, 0.0f, 0.0f);
6093 }
6094
6095 emit->common_immediate_pos[n++] =
6096 alloc_immediate_int4(emit, 0, 1, 0, -1);
6097
6098 if (emit->key.vs.attrib_puint_to_snorm) {
6099 emit->common_immediate_pos[n++] =
6100 alloc_immediate_float4(emit, -2.0f, 2.0f, 3.0f, -1.66666f);
6101 }
6102
6103 if (emit->key.vs.attrib_puint_to_uscaled) {
6104 emit->common_immediate_pos[n++] =
6105 alloc_immediate_float4(emit, 1023.0f, 3.0f, 0.0f, 0.0f);
6106 }
6107
6108 if (emit->key.vs.attrib_puint_to_sscaled) {
6109 emit->common_immediate_pos[n++] =
6110 alloc_immediate_int4(emit, 22, 12, 2, 0);
6111
6112 emit->common_immediate_pos[n++] =
6113 alloc_immediate_int4(emit, 22, 30, 0, 0);
6114 }
6115
6116 unsigned i;
6117
6118 for (i = 0; i < PIPE_MAX_SAMPLERS; i++) {
6119 if (emit->key.tex[i].texel_bias) {
6120 /* Replace 0.0f if more immediate float value is needed */
6121 emit->common_immediate_pos[n++] =
6122 alloc_immediate_float4(emit, 0.0001f, 0.0f, 0.0f, 0.0f);
6123 break;
6124 }
6125 }
6126
6127 assert(n <= ARRAY_SIZE(emit->common_immediate_pos));
6128 emit->num_common_immediates = n;
6129 }
6130
6131
6132 /**
6133 * Emit any extra/helper declarations/code that we might need between
6134 * the declaration section and code section.
6135 */
6136 static boolean
6137 emit_pre_helpers(struct svga_shader_emitter_v10 *emit)
6138 {
6139 /* Properties */
6140 if (emit->unit == PIPE_SHADER_GEOMETRY)
6141 emit_property_instructions(emit);
6142
6143 /* Declare inputs */
6144 if (!emit_input_declarations(emit))
6145 return FALSE;
6146
6147 /* Declare outputs */
6148 if (!emit_output_declarations(emit))
6149 return FALSE;
6150
6151 /* Declare temporary registers */
6152 emit_temporaries_declaration(emit);
6153
6154 /* Declare constant registers */
6155 emit_constant_declaration(emit);
6156
6157 /* Declare samplers and resources */
6158 emit_sampler_declarations(emit);
6159 emit_resource_declarations(emit);
6160
6161 /* Declare clip distance output registers */
6162 if (emit->unit == PIPE_SHADER_VERTEX ||
6163 emit->unit == PIPE_SHADER_GEOMETRY) {
6164 emit_clip_distance_declarations(emit);
6165 }
6166
6167 alloc_common_immediates(emit);
6168
6169 if (emit->unit == PIPE_SHADER_FRAGMENT &&
6170 emit->key.fs.alpha_func != SVGA3D_CMP_ALWAYS) {
6171 float alpha = emit->key.fs.alpha_ref;
6172 emit->fs.alpha_ref_index =
6173 alloc_immediate_float4(emit, alpha, alpha, alpha, alpha);
6174 }
6175
6176 /* Now, emit the constant block containing all the immediates
6177 * declared by shader, as well as the extra ones seen above.
6178 */
6179 emit_vgpu10_immediates_block(emit);
6180
6181 if (emit->unit == PIPE_SHADER_FRAGMENT) {
6182 emit_frontface_instructions(emit);
6183 emit_fragcoord_instructions(emit);
6184 }
6185 else if (emit->unit == PIPE_SHADER_VERTEX) {
6186 emit_vertex_attrib_instructions(emit);
6187 }
6188
6189 return TRUE;
6190 }
6191
6192
6193 /**
6194 * The device has no direct support for the pipe_blend_state::alpha_to_one
6195 * option so we implement it here with shader code.
6196 *
6197 * Note that this is kind of pointless, actually. Here we're clobbering
6198 * the alpha value with 1.0. So if alpha-to-coverage is enabled, we'll wind
6199 * up with 100% coverage. That's almost certainly not what the user wants.
6200 * The work-around is to add extra shader code to compute coverage from alpha
6201 * and write it to the coverage output register (if the user's shader doesn't
6202 * do so already). We'll probably do that in the future.
6203 */
6204 static void
6205 emit_alpha_to_one_instructions(struct svga_shader_emitter_v10 *emit,
6206 unsigned fs_color_tmp_index)
6207 {
6208 struct tgsi_full_src_register one = make_immediate_reg_float(emit, 1.0f);
6209 unsigned i;
6210
6211 /* Note: it's not 100% clear from the spec if we're supposed to clobber
6212 * the alpha for all render targets. But that's what NVIDIA does and
6213 * that's what Piglit tests.
6214 */
6215 for (i = 0; i < emit->fs.num_color_outputs; i++) {
6216 struct tgsi_full_dst_register color_dst;
6217
6218 if (fs_color_tmp_index != INVALID_INDEX && i == 0) {
6219 /* write to the temp color register */
6220 color_dst = make_dst_temp_reg(fs_color_tmp_index);
6221 }
6222 else {
6223 /* write directly to the color[i] output */
6224 color_dst = make_dst_output_reg(emit->fs.color_out_index[i]);
6225 }
6226
6227 color_dst = writemask_dst(&color_dst, TGSI_WRITEMASK_W);
6228
6229 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &color_dst, &one, FALSE);
6230 }
6231 }
6232
6233
6234 /**
6235 * Emit alpha test code. This compares TEMP[fs_color_tmp_index].w
6236 * against the alpha reference value and discards the fragment if the
6237 * comparison fails.
6238 */
6239 static void
6240 emit_alpha_test_instructions(struct svga_shader_emitter_v10 *emit,
6241 unsigned fs_color_tmp_index)
6242 {
6243 /* compare output color's alpha to alpha ref and kill */
6244 unsigned tmp = get_temp_index(emit);
6245 struct tgsi_full_src_register tmp_src = make_src_temp_reg(tmp);
6246 struct tgsi_full_src_register tmp_src_x =
6247 scalar_src(&tmp_src, TGSI_SWIZZLE_X);
6248 struct tgsi_full_dst_register tmp_dst = make_dst_temp_reg(tmp);
6249 struct tgsi_full_src_register color_src =
6250 make_src_temp_reg(fs_color_tmp_index);
6251 struct tgsi_full_src_register color_src_w =
6252 scalar_src(&color_src, TGSI_SWIZZLE_W);
6253 struct tgsi_full_src_register ref_src =
6254 make_src_immediate_reg(emit->fs.alpha_ref_index);
6255 struct tgsi_full_dst_register color_dst =
6256 make_dst_output_reg(emit->fs.color_out_index[0]);
6257
6258 assert(emit->unit == PIPE_SHADER_FRAGMENT);
6259
6260 /* dst = src0 'alpha_func' src1 */
6261 emit_comparison(emit, emit->key.fs.alpha_func, &tmp_dst,
6262 &color_src_w, &ref_src);
6263
6264 /* DISCARD if dst.x == 0 */
6265 begin_emit_instruction(emit);
6266 emit_discard_opcode(emit, FALSE); /* discard if src0.x is zero */
6267 emit_src_register(emit, &tmp_src_x);
6268 end_emit_instruction(emit);
6269
6270 /* If we don't need to broadcast the color below, emit the final color here.
6271 */
6272 if (emit->key.fs.write_color0_to_n_cbufs <= 1) {
6273 /* MOV output.color, tempcolor */
6274 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &color_dst,
6275 &color_src, FALSE); /* XXX saturate? */
6276 }
6277
6278 free_temp_indexes(emit);
6279 }
6280
6281
6282 /**
6283 * Emit instructions for writing a single color output to multiple
6284 * color buffers.
6285 * This is used when the TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS (or
6286 * when key.fs.white_fragments is true).
6287 * property is set and the number of render targets is greater than one.
6288 * \param fs_color_tmp_index index of the temp register that holds the
6289 * color to broadcast.
6290 */
6291 static void
6292 emit_broadcast_color_instructions(struct svga_shader_emitter_v10 *emit,
6293 unsigned fs_color_tmp_index)
6294 {
6295 const unsigned n = emit->key.fs.write_color0_to_n_cbufs;
6296 unsigned i;
6297 struct tgsi_full_src_register color_src;
6298
6299 if (emit->key.fs.white_fragments) {
6300 /* set all color outputs to white */
6301 color_src = make_immediate_reg_float(emit, 1.0f);
6302 }
6303 else {
6304 /* set all color outputs to TEMP[fs_color_tmp_index] */
6305 assert(fs_color_tmp_index != INVALID_INDEX);
6306 color_src = make_src_temp_reg(fs_color_tmp_index);
6307 }
6308
6309 assert(emit->unit == PIPE_SHADER_FRAGMENT);
6310
6311 for (i = 0; i < n; i++) {
6312 unsigned output_reg = emit->fs.color_out_index[i];
6313 struct tgsi_full_dst_register color_dst =
6314 make_dst_output_reg(output_reg);
6315
6316 /* Fill in this semantic here since we'll use it later in
6317 * emit_dst_register().
6318 */
6319 emit->info.output_semantic_name[output_reg] = TGSI_SEMANTIC_COLOR;
6320
6321 /* MOV output.color[i], tempcolor */
6322 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &color_dst,
6323 &color_src, FALSE); /* XXX saturate? */
6324 }
6325 }
6326
6327
6328 /**
6329 * Emit extra helper code after the original shader code, but before the
6330 * last END/RET instruction.
6331 * For vertex shaders this means emitting the extra code to apply the
6332 * prescale scale/translation.
6333 */
6334 static boolean
6335 emit_post_helpers(struct svga_shader_emitter_v10 *emit)
6336 {
6337 if (emit->unit == PIPE_SHADER_VERTEX) {
6338 emit_vertex_instructions(emit);
6339 }
6340 else if (emit->unit == PIPE_SHADER_FRAGMENT) {
6341 const unsigned fs_color_tmp_index = emit->fs.color_tmp_index;
6342
6343 assert(!(emit->key.fs.white_fragments &&
6344 emit->key.fs.write_color0_to_n_cbufs == 0));
6345
6346 /* We no longer want emit_dst_register() to substitute the
6347 * temporary fragment color register for the real color output.
6348 */
6349 emit->fs.color_tmp_index = INVALID_INDEX;
6350
6351 if (emit->key.fs.alpha_to_one) {
6352 emit_alpha_to_one_instructions(emit, fs_color_tmp_index);
6353 }
6354 if (emit->key.fs.alpha_func != SVGA3D_CMP_ALWAYS) {
6355 emit_alpha_test_instructions(emit, fs_color_tmp_index);
6356 }
6357 if (emit->key.fs.write_color0_to_n_cbufs > 1 ||
6358 emit->key.fs.white_fragments) {
6359 emit_broadcast_color_instructions(emit, fs_color_tmp_index);
6360 }
6361 }
6362
6363 return TRUE;
6364 }
6365
6366
6367 /**
6368 * Translate the TGSI tokens into VGPU10 tokens.
6369 */
6370 static boolean
6371 emit_vgpu10_instructions(struct svga_shader_emitter_v10 *emit,
6372 const struct tgsi_token *tokens)
6373 {
6374 struct tgsi_parse_context parse;
6375 boolean ret = TRUE;
6376 boolean pre_helpers_emitted = FALSE;
6377 unsigned inst_number = 0;
6378
6379 tgsi_parse_init(&parse, tokens);
6380
6381 while (!tgsi_parse_end_of_tokens(&parse)) {
6382 tgsi_parse_token(&parse);
6383
6384 switch (parse.FullToken.Token.Type) {
6385 case TGSI_TOKEN_TYPE_IMMEDIATE:
6386 ret = emit_vgpu10_immediate(emit, &parse.FullToken.FullImmediate);
6387 if (!ret)
6388 goto done;
6389 break;
6390
6391 case TGSI_TOKEN_TYPE_DECLARATION:
6392 ret = emit_vgpu10_declaration(emit, &parse.FullToken.FullDeclaration);
6393 if (!ret)
6394 goto done;
6395 break;
6396
6397 case TGSI_TOKEN_TYPE_INSTRUCTION:
6398 if (!pre_helpers_emitted) {
6399 ret = emit_pre_helpers(emit);
6400 if (!ret)
6401 goto done;
6402 pre_helpers_emitted = TRUE;
6403 }
6404 ret = emit_vgpu10_instruction(emit, inst_number++,
6405 &parse.FullToken.FullInstruction);
6406 if (!ret)
6407 goto done;
6408 break;
6409
6410 case TGSI_TOKEN_TYPE_PROPERTY:
6411 ret = emit_vgpu10_property(emit, &parse.FullToken.FullProperty);
6412 if (!ret)
6413 goto done;
6414 break;
6415
6416 default:
6417 break;
6418 }
6419 }
6420
6421 done:
6422 tgsi_parse_free(&parse);
6423 return ret;
6424 }
6425
6426
6427 /**
6428 * Emit the first VGPU10 shader tokens.
6429 */
6430 static boolean
6431 emit_vgpu10_header(struct svga_shader_emitter_v10 *emit)
6432 {
6433 VGPU10ProgramToken ptoken;
6434
6435 /* First token: VGPU10ProgramToken (version info, program type (VS,GS,PS)) */
6436 ptoken.majorVersion = 4;
6437 ptoken.minorVersion = 0;
6438 ptoken.programType = translate_shader_type(emit->unit);
6439 if (!emit_dword(emit, ptoken.value))
6440 return FALSE;
6441
6442 /* Second token: total length of shader, in tokens. We can't fill this
6443 * in until we're all done. Emit zero for now.
6444 */
6445 return emit_dword(emit, 0);
6446 }
6447
6448
6449 static boolean
6450 emit_vgpu10_tail(struct svga_shader_emitter_v10 *emit)
6451 {
6452 VGPU10ProgramToken *tokens;
6453
6454 /* Replace the second token with total shader length */
6455 tokens = (VGPU10ProgramToken *) emit->buf;
6456 tokens[1].value = emit_get_num_tokens(emit);
6457
6458 return TRUE;
6459 }
6460
6461
6462 /**
6463 * Modify the FS to read the BCOLORs and use the FACE register
6464 * to choose between the front/back colors.
6465 */
6466 static const struct tgsi_token *
6467 transform_fs_twoside(const struct tgsi_token *tokens)
6468 {
6469 if (0) {
6470 debug_printf("Before tgsi_add_two_side ------------------\n");
6471 tgsi_dump(tokens,0);
6472 }
6473 tokens = tgsi_add_two_side(tokens);
6474 if (0) {
6475 debug_printf("After tgsi_add_two_side ------------------\n");
6476 tgsi_dump(tokens, 0);
6477 }
6478 return tokens;
6479 }
6480
6481
6482 /**
6483 * Modify the FS to do polygon stipple.
6484 */
6485 static const struct tgsi_token *
6486 transform_fs_pstipple(struct svga_shader_emitter_v10 *emit,
6487 const struct tgsi_token *tokens)
6488 {
6489 const struct tgsi_token *new_tokens;
6490 unsigned unit;
6491
6492 if (0) {
6493 debug_printf("Before pstipple ------------------\n");
6494 tgsi_dump(tokens,0);
6495 }
6496
6497 new_tokens = util_pstipple_create_fragment_shader(tokens, &unit, 0,
6498 TGSI_FILE_INPUT);
6499
6500 emit->fs.pstipple_sampler_unit = unit;
6501
6502 /* Setup texture state for stipple */
6503 emit->sampler_target[unit] = TGSI_TEXTURE_2D;
6504 emit->key.tex[unit].swizzle_r = TGSI_SWIZZLE_X;
6505 emit->key.tex[unit].swizzle_g = TGSI_SWIZZLE_Y;
6506 emit->key.tex[unit].swizzle_b = TGSI_SWIZZLE_Z;
6507 emit->key.tex[unit].swizzle_a = TGSI_SWIZZLE_W;
6508
6509 if (0) {
6510 debug_printf("After pstipple ------------------\n");
6511 tgsi_dump(new_tokens, 0);
6512 }
6513
6514 return new_tokens;
6515 }
6516
6517 /**
6518 * Modify the FS to support anti-aliasing point.
6519 */
6520 static const struct tgsi_token *
6521 transform_fs_aapoint(const struct tgsi_token *tokens,
6522 int aa_coord_index)
6523 {
6524 if (0) {
6525 debug_printf("Before tgsi_add_aa_point ------------------\n");
6526 tgsi_dump(tokens,0);
6527 }
6528 tokens = tgsi_add_aa_point(tokens, aa_coord_index);
6529 if (0) {
6530 debug_printf("After tgsi_add_aa_point ------------------\n");
6531 tgsi_dump(tokens, 0);
6532 }
6533 return tokens;
6534 }
6535
6536 /**
6537 * This is the main entrypoint for the TGSI -> VPGU10 translator.
6538 */
6539 struct svga_shader_variant *
6540 svga_tgsi_vgpu10_translate(struct svga_context *svga,
6541 const struct svga_shader *shader,
6542 const struct svga_compile_key *key,
6543 enum pipe_shader_type unit)
6544 {
6545 struct svga_shader_variant *variant = NULL;
6546 struct svga_shader_emitter_v10 *emit;
6547 const struct tgsi_token *tokens = shader->tokens;
6548 struct svga_vertex_shader *vs = svga->curr.vs;
6549 struct svga_geometry_shader *gs = svga->curr.gs;
6550
6551 assert(unit == PIPE_SHADER_VERTEX ||
6552 unit == PIPE_SHADER_GEOMETRY ||
6553 unit == PIPE_SHADER_FRAGMENT);
6554
6555 /* These two flags cannot be used together */
6556 assert(key->vs.need_prescale + key->vs.undo_viewport <= 1);
6557
6558 SVGA_STATS_TIME_PUSH(svga_sws(svga), SVGA_STATS_TIME_TGSIVGPU10TRANSLATE);
6559 /*
6560 * Setup the code emitter
6561 */
6562 emit = alloc_emitter();
6563 if (!emit)
6564 goto done;
6565
6566 emit->unit = unit;
6567 emit->key = *key;
6568
6569 emit->vposition.need_prescale = (emit->key.vs.need_prescale ||
6570 emit->key.gs.need_prescale);
6571 emit->vposition.tmp_index = INVALID_INDEX;
6572 emit->vposition.so_index = INVALID_INDEX;
6573 emit->vposition.out_index = INVALID_INDEX;
6574
6575 emit->fs.color_tmp_index = INVALID_INDEX;
6576 emit->fs.face_input_index = INVALID_INDEX;
6577 emit->fs.fragcoord_input_index = INVALID_INDEX;
6578
6579 emit->gs.prim_id_index = INVALID_INDEX;
6580
6581 emit->clip_dist_out_index = INVALID_INDEX;
6582 emit->clip_dist_tmp_index = INVALID_INDEX;
6583 emit->clip_dist_so_index = INVALID_INDEX;
6584 emit->clip_vertex_out_index = INVALID_INDEX;
6585
6586 if (emit->key.fs.alpha_func == SVGA3D_CMP_INVALID) {
6587 emit->key.fs.alpha_func = SVGA3D_CMP_ALWAYS;
6588 }
6589
6590 if (unit == PIPE_SHADER_FRAGMENT) {
6591 if (key->fs.light_twoside) {
6592 tokens = transform_fs_twoside(tokens);
6593 }
6594 if (key->fs.pstipple) {
6595 const struct tgsi_token *new_tokens =
6596 transform_fs_pstipple(emit, tokens);
6597 if (tokens != shader->tokens) {
6598 /* free the two-sided shader tokens */
6599 tgsi_free_tokens(tokens);
6600 }
6601 tokens = new_tokens;
6602 }
6603 if (key->fs.aa_point) {
6604 tokens = transform_fs_aapoint(tokens, key->fs.aa_point_coord_index);
6605 }
6606 }
6607
6608 if (SVGA_DEBUG & DEBUG_TGSI) {
6609 debug_printf("#####################################\n");
6610 debug_printf("### TGSI Shader %u\n", shader->id);
6611 tgsi_dump(tokens, 0);
6612 }
6613
6614 /**
6615 * Rescan the header if the token string is different from the one
6616 * included in the shader; otherwise, the header info is already up-to-date
6617 */
6618 if (tokens != shader->tokens) {
6619 tgsi_scan_shader(tokens, &emit->info);
6620 } else {
6621 emit->info = shader->info;
6622 }
6623
6624 emit->num_outputs = emit->info.num_outputs;
6625
6626 if (unit == PIPE_SHADER_FRAGMENT) {
6627 /* Compute FS input remapping to match the output from VS/GS */
6628 if (gs) {
6629 svga_link_shaders(&gs->base.info, &emit->info, &emit->linkage);
6630 } else {
6631 assert(vs);
6632 svga_link_shaders(&vs->base.info, &emit->info, &emit->linkage);
6633 }
6634 } else if (unit == PIPE_SHADER_GEOMETRY) {
6635 assert(vs);
6636 svga_link_shaders(&vs->base.info, &emit->info, &emit->linkage);
6637 }
6638
6639 determine_clipping_mode(emit);
6640
6641 if (unit == PIPE_SHADER_GEOMETRY || unit == PIPE_SHADER_VERTEX) {
6642 if (shader->stream_output != NULL || emit->clip_mode == CLIP_DISTANCE) {
6643 /* if there is stream output declarations associated
6644 * with this shader or the shader writes to ClipDistance
6645 * then reserve extra registers for the non-adjusted vertex position
6646 * and the ClipDistance shadow copy
6647 */
6648 emit->vposition.so_index = emit->num_outputs++;
6649
6650 if (emit->clip_mode == CLIP_DISTANCE) {
6651 emit->clip_dist_so_index = emit->num_outputs++;
6652 if (emit->info.num_written_clipdistance > 4)
6653 emit->num_outputs++;
6654 }
6655 }
6656 }
6657
6658 /*
6659 * Do actual shader translation.
6660 */
6661 if (!emit_vgpu10_header(emit)) {
6662 debug_printf("svga: emit VGPU10 header failed\n");
6663 goto cleanup;
6664 }
6665
6666 if (!emit_vgpu10_instructions(emit, tokens)) {
6667 debug_printf("svga: emit VGPU10 instructions failed\n");
6668 goto cleanup;
6669 }
6670
6671 if (!emit_vgpu10_tail(emit)) {
6672 debug_printf("svga: emit VGPU10 tail failed\n");
6673 goto cleanup;
6674 }
6675
6676 if (emit->register_overflow) {
6677 goto cleanup;
6678 }
6679
6680 /*
6681 * Create, initialize the 'variant' object.
6682 */
6683 variant = svga_new_shader_variant(svga);
6684 if (!variant)
6685 goto cleanup;
6686
6687 variant->shader = shader;
6688 variant->nr_tokens = emit_get_num_tokens(emit);
6689 variant->tokens = (const unsigned *)emit->buf;
6690 emit->buf = NULL; /* buffer is no longer owed by emitter context */
6691 memcpy(&variant->key, key, sizeof(*key));
6692 variant->id = UTIL_BITMASK_INVALID_INDEX;
6693
6694 /* The extra constant starting offset starts with the number of
6695 * shader constants declared in the shader.
6696 */
6697 variant->extra_const_start = emit->num_shader_consts[0];
6698 if (key->gs.wide_point) {
6699 /**
6700 * The extra constant added in the transformed shader
6701 * for inverse viewport scale is to be supplied by the driver.
6702 * So the extra constant starting offset needs to be reduced by 1.
6703 */
6704 assert(variant->extra_const_start > 0);
6705 variant->extra_const_start--;
6706 }
6707
6708 variant->pstipple_sampler_unit = emit->fs.pstipple_sampler_unit;
6709
6710 /* If there was exactly one write to a fragment shader output register
6711 * and it came from a constant buffer, we know all fragments will have
6712 * the same color (except for blending).
6713 */
6714 variant->constant_color_output =
6715 emit->constant_color_output && emit->num_output_writes == 1;
6716
6717 /** keep track in the variant if flat interpolation is used
6718 * for any of the varyings.
6719 */
6720 variant->uses_flat_interp = emit->uses_flat_interp;
6721
6722 variant->fs_shadow_compare_units = emit->fs.shadow_compare_units;
6723
6724 if (tokens != shader->tokens) {
6725 tgsi_free_tokens(tokens);
6726 }
6727
6728 cleanup:
6729 free_emitter(emit);
6730
6731 done:
6732 SVGA_STATS_TIME_POP(svga_sws(svga));
6733 return variant;
6734 }