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5 * obtaining a copy of this software and associated documentation
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21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 **********************************************************/
27 * @file svga_tgsi_vgpu10.c
29 * TGSI -> VGPU10 shader translation.
31 * \author Mingcheng Chen
35 #include "pipe/p_compiler.h"
36 #include "pipe/p_shader_tokens.h"
37 #include "pipe/p_defines.h"
38 #include "tgsi/tgsi_build.h"
39 #include "tgsi/tgsi_dump.h"
40 #include "tgsi/tgsi_info.h"
41 #include "tgsi/tgsi_parse.h"
42 #include "tgsi/tgsi_scan.h"
43 #include "tgsi/tgsi_two_side.h"
44 #include "tgsi/tgsi_aa_point.h"
45 #include "tgsi/tgsi_util.h"
46 #include "util/u_math.h"
47 #include "util/u_memory.h"
48 #include "util/u_bitmask.h"
49 #include "util/u_debug.h"
50 #include "util/u_pstipple.h"
52 #include "svga_context.h"
53 #include "svga_debug.h"
54 #include "svga_link.h"
55 #include "svga_shader.h"
56 #include "svga_tgsi.h"
58 #include "VGPU10ShaderTokens.h"
61 #define INVALID_INDEX 99999
62 #define MAX_INTERNAL_TEMPS 3
63 #define MAX_SYSTEM_VALUES 4
64 #define MAX_IMMEDIATE_COUNT \
65 (VGPU10_MAX_IMMEDIATE_CONSTANT_BUFFER_ELEMENT_COUNT/4)
66 #define MAX_TEMP_ARRAYS 64 /* Enough? */
70 * Clipping is complicated. There's four different cases which we
71 * handle during VS/GS shader translation:
75 CLIP_NONE
, /**< No clipping enabled */
76 CLIP_LEGACY
, /**< The shader has no clipping declarations or code but
77 * one or more user-defined clip planes are enabled. We
78 * generate extra code to emit clip distances.
80 CLIP_DISTANCE
, /**< The shader already declares clip distance output
81 * registers and has code to write to them.
83 CLIP_VERTEX
/**< The shader declares a clip vertex output register and
84 * has code that writes to the register. We convert the
85 * clipvertex position into one or more clip distances.
90 struct svga_shader_emitter_v10
92 /* The token output buffer */
97 /* Information about the shader and state (does not change) */
98 struct svga_compile_key key
;
99 struct tgsi_shader_info info
;
102 unsigned inst_start_token
;
103 boolean discard_instruction
; /**< throw away current instruction? */
105 union tgsi_immediate_data immediates
[MAX_IMMEDIATE_COUNT
][4];
106 unsigned num_immediates
; /**< Number of immediates emitted */
107 unsigned common_immediate_pos
[8]; /**< literals for common immediates */
108 unsigned num_common_immediates
;
109 boolean immediates_emitted
;
111 unsigned num_outputs
; /**< include any extra outputs */
112 /** The first extra output is reserved for
113 * non-adjusted vertex position for
114 * stream output purpose
117 /* Temporary Registers */
118 unsigned num_shader_temps
; /**< num of temps used by original shader */
119 unsigned internal_temp_count
; /**< currently allocated internal temps */
121 unsigned start
, size
;
122 } temp_arrays
[MAX_TEMP_ARRAYS
];
123 unsigned num_temp_arrays
;
125 /** Map TGSI temp registers to VGPU10 temp array IDs and indexes */
127 unsigned arrayId
, index
;
128 } temp_map
[VGPU10_MAX_TEMPS
]; /**< arrayId, element */
130 /** Number of constants used by original shader for each constant buffer.
131 * The size should probably always match with that of svga_state.constbufs.
133 unsigned num_shader_consts
[SVGA_MAX_CONST_BUFS
];
136 unsigned num_samplers
;
137 ubyte sampler_target
[PIPE_MAX_SAMPLERS
]; /**< TGSI_TEXTURE_x */
138 ubyte sampler_return_type
[PIPE_MAX_SAMPLERS
]; /**< TGSI_RETURN_TYPE_x */
140 /* Address regs (really implemented with temps) */
141 unsigned num_address_regs
;
142 unsigned address_reg_index
[MAX_VGPU10_ADDR_REGS
];
144 /* Output register usage masks */
145 ubyte output_usage_mask
[PIPE_MAX_SHADER_OUTPUTS
];
147 /* To map TGSI system value index to VGPU shader input indexes */
148 ubyte system_value_indexes
[MAX_SYSTEM_VALUES
];
151 /* vertex position scale/translation */
152 unsigned out_index
; /**< the real position output reg */
153 unsigned tmp_index
; /**< the fake/temp position output reg */
154 unsigned so_index
; /**< the non-adjusted position output reg */
155 unsigned prescale_scale_index
, prescale_trans_index
;
156 boolean need_prescale
;
159 /* For vertex shaders only */
161 /* viewport constant */
162 unsigned viewport_index
;
164 /* temp index of adjusted vertex attributes */
165 unsigned adjusted_input
[PIPE_MAX_SHADER_INPUTS
];
168 /* For fragment shaders only */
171 unsigned color_out_index
[PIPE_MAX_COLOR_BUFS
]; /**< the real color output regs */
172 unsigned color_tmp_index
; /**< fake/temp color output reg */
173 unsigned alpha_ref_index
; /**< immediate constant for alpha ref */
176 unsigned face_input_index
; /**< real fragment shader face reg (bool) */
177 unsigned face_tmp_index
; /**< temp face reg converted to -1 / +1 */
179 unsigned pstipple_sampler_unit
;
181 unsigned fragcoord_input_index
; /**< real fragment position input reg */
182 unsigned fragcoord_tmp_index
; /**< 1/w modified position temp reg */
185 /* For geometry shaders only */
187 VGPU10_PRIMITIVE prim_type
;/**< VGPU10 primitive type */
188 VGPU10_PRIMITIVE_TOPOLOGY prim_topology
; /**< VGPU10 primitive topology */
189 unsigned input_size
; /**< size of input arrays */
190 unsigned prim_id_index
; /**< primitive id register index */
191 unsigned max_out_vertices
; /**< maximum number of output vertices */
194 /* For vertex or geometry shaders */
195 enum clipping_mode clip_mode
;
196 unsigned clip_dist_out_index
; /**< clip distance output register index */
197 unsigned clip_dist_tmp_index
; /**< clip distance temporary register */
198 unsigned clip_dist_so_index
; /**< clip distance shadow copy */
200 /** Index of temporary holding the clipvertex coordinate */
201 unsigned clip_vertex_out_index
; /**< clip vertex output register index */
202 unsigned clip_vertex_tmp_index
; /**< clip vertex temporary index */
204 /* user clip plane constant slot indexes */
205 unsigned clip_plane_const
[PIPE_MAX_CLIP_PLANES
];
207 unsigned num_output_writes
;
208 boolean constant_color_output
;
210 boolean uses_flat_interp
;
212 /* For all shaders: const reg index for RECT coord scaling */
213 unsigned texcoord_scale_index
[PIPE_MAX_SAMPLERS
];
215 /* For all shaders: const reg index for texture buffer size */
216 unsigned texture_buffer_size_index
[PIPE_MAX_SAMPLERS
];
218 /* VS/GS/FS Linkage info */
219 struct shader_linkage linkage
;
221 bool register_overflow
; /**< Set if we exceed a VGPU10 register limit */
226 emit_post_helpers(struct svga_shader_emitter_v10
*emit
);
229 emit_vertex(struct svga_shader_emitter_v10
*emit
,
230 const struct tgsi_full_instruction
*inst
);
232 static char err_buf
[128];
235 expand(struct svga_shader_emitter_v10
*emit
)
238 unsigned newsize
= emit
->size
* 2;
240 if (emit
->buf
!= err_buf
)
241 new_buf
= REALLOC(emit
->buf
, emit
->size
, newsize
);
248 emit
->size
= sizeof(err_buf
);
252 emit
->size
= newsize
;
253 emit
->ptr
= new_buf
+ (emit
->ptr
- emit
->buf
);
259 * Create and initialize a new svga_shader_emitter_v10 object.
261 static struct svga_shader_emitter_v10
*
264 struct svga_shader_emitter_v10
*emit
= CALLOC(1, sizeof(*emit
));
269 /* to initialize the output buffer */
279 * Free an svga_shader_emitter_v10 object.
282 free_emitter(struct svga_shader_emitter_v10
*emit
)
285 FREE(emit
->buf
); /* will be NULL if translation succeeded */
289 static inline boolean
290 reserve(struct svga_shader_emitter_v10
*emit
,
293 while (emit
->ptr
- emit
->buf
+ nr_dwords
* sizeof(uint32
) >= emit
->size
) {
302 emit_dword(struct svga_shader_emitter_v10
*emit
, uint32 dword
)
304 if (!reserve(emit
, 1))
307 *(uint32
*)emit
->ptr
= dword
;
308 emit
->ptr
+= sizeof dword
;
313 emit_dwords(struct svga_shader_emitter_v10
*emit
,
314 const uint32
*dwords
,
317 if (!reserve(emit
, nr
))
320 memcpy(emit
->ptr
, dwords
, nr
* sizeof *dwords
);
321 emit
->ptr
+= nr
* sizeof *dwords
;
325 /** Return the number of tokens in the emitter's buffer */
327 emit_get_num_tokens(const struct svga_shader_emitter_v10
*emit
)
329 return (emit
->ptr
- emit
->buf
) / sizeof(unsigned);
334 * Check for register overflow. If we overflow we'll set an
335 * error flag. This function can be called for register declarations
336 * or use as src/dst instruction operands.
337 * \param type register type. One of VGPU10_OPERAND_TYPE_x
338 or VGPU10_OPCODE_DCL_x
339 * \param index the register index
342 check_register_index(struct svga_shader_emitter_v10
*emit
,
343 unsigned operandType
, unsigned index
)
345 bool overflow_before
= emit
->register_overflow
;
347 switch (operandType
) {
348 case VGPU10_OPERAND_TYPE_TEMP
:
349 case VGPU10_OPERAND_TYPE_INDEXABLE_TEMP
:
350 case VGPU10_OPCODE_DCL_TEMPS
:
351 if (index
>= VGPU10_MAX_TEMPS
) {
352 emit
->register_overflow
= TRUE
;
355 case VGPU10_OPERAND_TYPE_CONSTANT_BUFFER
:
356 case VGPU10_OPCODE_DCL_CONSTANT_BUFFER
:
357 if (index
>= VGPU10_MAX_CONSTANT_BUFFER_ELEMENT_COUNT
) {
358 emit
->register_overflow
= TRUE
;
361 case VGPU10_OPERAND_TYPE_INPUT
:
362 case VGPU10_OPERAND_TYPE_INPUT_PRIMITIVEID
:
363 case VGPU10_OPCODE_DCL_INPUT
:
364 case VGPU10_OPCODE_DCL_INPUT_SGV
:
365 case VGPU10_OPCODE_DCL_INPUT_SIV
:
366 case VGPU10_OPCODE_DCL_INPUT_PS
:
367 case VGPU10_OPCODE_DCL_INPUT_PS_SGV
:
368 case VGPU10_OPCODE_DCL_INPUT_PS_SIV
:
369 if ((emit
->unit
== PIPE_SHADER_VERTEX
&&
370 index
>= VGPU10_MAX_VS_INPUTS
) ||
371 (emit
->unit
== PIPE_SHADER_GEOMETRY
&&
372 index
>= VGPU10_MAX_GS_INPUTS
) ||
373 (emit
->unit
== PIPE_SHADER_FRAGMENT
&&
374 index
>= VGPU10_MAX_FS_INPUTS
)) {
375 emit
->register_overflow
= TRUE
;
378 case VGPU10_OPERAND_TYPE_OUTPUT
:
379 case VGPU10_OPCODE_DCL_OUTPUT
:
380 case VGPU10_OPCODE_DCL_OUTPUT_SGV
:
381 case VGPU10_OPCODE_DCL_OUTPUT_SIV
:
382 if ((emit
->unit
== PIPE_SHADER_VERTEX
&&
383 index
>= VGPU10_MAX_VS_OUTPUTS
) ||
384 (emit
->unit
== PIPE_SHADER_GEOMETRY
&&
385 index
>= VGPU10_MAX_GS_OUTPUTS
) ||
386 (emit
->unit
== PIPE_SHADER_FRAGMENT
&&
387 index
>= VGPU10_MAX_FS_OUTPUTS
)) {
388 emit
->register_overflow
= TRUE
;
391 case VGPU10_OPERAND_TYPE_SAMPLER
:
392 case VGPU10_OPCODE_DCL_SAMPLER
:
393 if (index
>= VGPU10_MAX_SAMPLERS
) {
394 emit
->register_overflow
= TRUE
;
397 case VGPU10_OPERAND_TYPE_RESOURCE
:
398 case VGPU10_OPCODE_DCL_RESOURCE
:
399 if (index
>= VGPU10_MAX_RESOURCES
) {
400 emit
->register_overflow
= TRUE
;
403 case VGPU10_OPERAND_TYPE_IMMEDIATE_CONSTANT_BUFFER
:
404 if (index
>= MAX_IMMEDIATE_COUNT
) {
405 emit
->register_overflow
= TRUE
;
413 if (emit
->register_overflow
&& !overflow_before
) {
414 debug_printf("svga: vgpu10 register overflow (reg %u, index %u)\n",
421 * Examine misc state to determine the clipping mode.
424 determine_clipping_mode(struct svga_shader_emitter_v10
*emit
)
426 if (emit
->info
.num_written_clipdistance
> 0) {
427 emit
->clip_mode
= CLIP_DISTANCE
;
429 else if (emit
->info
.writes_clipvertex
) {
430 emit
->clip_mode
= CLIP_VERTEX
;
432 else if (emit
->key
.clip_plane_enable
) {
433 emit
->clip_mode
= CLIP_LEGACY
;
436 emit
->clip_mode
= CLIP_NONE
;
442 * For clip distance register declarations and clip distance register
443 * writes we need to mask the declaration usage or instruction writemask
444 * (respectively) against the set of the really-enabled clipping planes.
446 * The piglit test spec/glsl-1.30/execution/clipping/vs-clip-distance-enables
447 * has a VS that writes to all 8 clip distance registers, but the plane enable
448 * flags are a subset of that.
450 * This function is used to apply the plane enable flags to the register
451 * declaration or instruction writemask.
453 * \param writemask the declaration usage mask or instruction writemask
454 * \param clip_reg_index which clip plane register is being declared/written.
455 * The legal values are 0 and 1 (two clip planes per
456 * register, for a total of 8 clip planes)
459 apply_clip_plane_mask(struct svga_shader_emitter_v10
*emit
,
460 unsigned writemask
, unsigned clip_reg_index
)
464 assert(clip_reg_index
< 2);
466 /* four clip planes per clip register: */
467 shift
= clip_reg_index
* 4;
468 writemask
&= ((emit
->key
.clip_plane_enable
>> shift
) & 0xf);
475 * Translate gallium shader type into VGPU10 type.
477 static VGPU10_PROGRAM_TYPE
478 translate_shader_type(unsigned type
)
481 case PIPE_SHADER_VERTEX
:
482 return VGPU10_VERTEX_SHADER
;
483 case PIPE_SHADER_GEOMETRY
:
484 return VGPU10_GEOMETRY_SHADER
;
485 case PIPE_SHADER_FRAGMENT
:
486 return VGPU10_PIXEL_SHADER
;
488 assert(!"Unexpected shader type");
489 return VGPU10_VERTEX_SHADER
;
495 * Translate a TGSI_OPCODE_x into a VGPU10_OPCODE_x
496 * Note: we only need to translate the opcodes for "simple" instructions,
497 * as seen below. All other opcodes are handled/translated specially.
499 static VGPU10_OPCODE_TYPE
500 translate_opcode(unsigned opcode
)
503 case TGSI_OPCODE_MOV
:
504 return VGPU10_OPCODE_MOV
;
505 case TGSI_OPCODE_MUL
:
506 return VGPU10_OPCODE_MUL
;
507 case TGSI_OPCODE_ADD
:
508 return VGPU10_OPCODE_ADD
;
509 case TGSI_OPCODE_DP3
:
510 return VGPU10_OPCODE_DP3
;
511 case TGSI_OPCODE_DP4
:
512 return VGPU10_OPCODE_DP4
;
513 case TGSI_OPCODE_MIN
:
514 return VGPU10_OPCODE_MIN
;
515 case TGSI_OPCODE_MAX
:
516 return VGPU10_OPCODE_MAX
;
517 case TGSI_OPCODE_MAD
:
518 return VGPU10_OPCODE_MAD
;
519 case TGSI_OPCODE_SQRT
:
520 return VGPU10_OPCODE_SQRT
;
521 case TGSI_OPCODE_FRC
:
522 return VGPU10_OPCODE_FRC
;
523 case TGSI_OPCODE_FLR
:
524 return VGPU10_OPCODE_ROUND_NI
;
525 case TGSI_OPCODE_FSEQ
:
526 return VGPU10_OPCODE_EQ
;
527 case TGSI_OPCODE_FSGE
:
528 return VGPU10_OPCODE_GE
;
529 case TGSI_OPCODE_FSNE
:
530 return VGPU10_OPCODE_NE
;
531 case TGSI_OPCODE_DDX
:
532 return VGPU10_OPCODE_DERIV_RTX
;
533 case TGSI_OPCODE_DDY
:
534 return VGPU10_OPCODE_DERIV_RTY
;
535 case TGSI_OPCODE_RET
:
536 return VGPU10_OPCODE_RET
;
537 case TGSI_OPCODE_DIV
:
538 return VGPU10_OPCODE_DIV
;
539 case TGSI_OPCODE_IDIV
:
540 return VGPU10_OPCODE_IDIV
;
541 case TGSI_OPCODE_DP2
:
542 return VGPU10_OPCODE_DP2
;
543 case TGSI_OPCODE_BRK
:
544 return VGPU10_OPCODE_BREAK
;
546 return VGPU10_OPCODE_IF
;
547 case TGSI_OPCODE_ELSE
:
548 return VGPU10_OPCODE_ELSE
;
549 case TGSI_OPCODE_ENDIF
:
550 return VGPU10_OPCODE_ENDIF
;
551 case TGSI_OPCODE_CEIL
:
552 return VGPU10_OPCODE_ROUND_PI
;
553 case TGSI_OPCODE_I2F
:
554 return VGPU10_OPCODE_ITOF
;
555 case TGSI_OPCODE_NOT
:
556 return VGPU10_OPCODE_NOT
;
557 case TGSI_OPCODE_TRUNC
:
558 return VGPU10_OPCODE_ROUND_Z
;
559 case TGSI_OPCODE_SHL
:
560 return VGPU10_OPCODE_ISHL
;
561 case TGSI_OPCODE_AND
:
562 return VGPU10_OPCODE_AND
;
564 return VGPU10_OPCODE_OR
;
565 case TGSI_OPCODE_XOR
:
566 return VGPU10_OPCODE_XOR
;
567 case TGSI_OPCODE_CONT
:
568 return VGPU10_OPCODE_CONTINUE
;
569 case TGSI_OPCODE_EMIT
:
570 return VGPU10_OPCODE_EMIT
;
571 case TGSI_OPCODE_ENDPRIM
:
572 return VGPU10_OPCODE_CUT
;
573 case TGSI_OPCODE_BGNLOOP
:
574 return VGPU10_OPCODE_LOOP
;
575 case TGSI_OPCODE_ENDLOOP
:
576 return VGPU10_OPCODE_ENDLOOP
;
577 case TGSI_OPCODE_ENDSUB
:
578 return VGPU10_OPCODE_RET
;
579 case TGSI_OPCODE_NOP
:
580 return VGPU10_OPCODE_NOP
;
581 case TGSI_OPCODE_BREAKC
:
582 return VGPU10_OPCODE_BREAKC
;
583 case TGSI_OPCODE_END
:
584 return VGPU10_OPCODE_RET
;
585 case TGSI_OPCODE_F2I
:
586 return VGPU10_OPCODE_FTOI
;
587 case TGSI_OPCODE_IMAX
:
588 return VGPU10_OPCODE_IMAX
;
589 case TGSI_OPCODE_IMIN
:
590 return VGPU10_OPCODE_IMIN
;
591 case TGSI_OPCODE_UDIV
:
592 case TGSI_OPCODE_UMOD
:
593 case TGSI_OPCODE_MOD
:
594 return VGPU10_OPCODE_UDIV
;
595 case TGSI_OPCODE_IMUL_HI
:
596 return VGPU10_OPCODE_IMUL
;
597 case TGSI_OPCODE_INEG
:
598 return VGPU10_OPCODE_INEG
;
599 case TGSI_OPCODE_ISHR
:
600 return VGPU10_OPCODE_ISHR
;
601 case TGSI_OPCODE_ISGE
:
602 return VGPU10_OPCODE_IGE
;
603 case TGSI_OPCODE_ISLT
:
604 return VGPU10_OPCODE_ILT
;
605 case TGSI_OPCODE_F2U
:
606 return VGPU10_OPCODE_FTOU
;
607 case TGSI_OPCODE_UADD
:
608 return VGPU10_OPCODE_IADD
;
609 case TGSI_OPCODE_U2F
:
610 return VGPU10_OPCODE_UTOF
;
611 case TGSI_OPCODE_UCMP
:
612 return VGPU10_OPCODE_MOVC
;
613 case TGSI_OPCODE_UMAD
:
614 return VGPU10_OPCODE_UMAD
;
615 case TGSI_OPCODE_UMAX
:
616 return VGPU10_OPCODE_UMAX
;
617 case TGSI_OPCODE_UMIN
:
618 return VGPU10_OPCODE_UMIN
;
619 case TGSI_OPCODE_UMUL
:
620 case TGSI_OPCODE_UMUL_HI
:
621 return VGPU10_OPCODE_UMUL
;
622 case TGSI_OPCODE_USEQ
:
623 return VGPU10_OPCODE_IEQ
;
624 case TGSI_OPCODE_USGE
:
625 return VGPU10_OPCODE_UGE
;
626 case TGSI_OPCODE_USHR
:
627 return VGPU10_OPCODE_USHR
;
628 case TGSI_OPCODE_USLT
:
629 return VGPU10_OPCODE_ULT
;
630 case TGSI_OPCODE_USNE
:
631 return VGPU10_OPCODE_INE
;
632 case TGSI_OPCODE_SWITCH
:
633 return VGPU10_OPCODE_SWITCH
;
634 case TGSI_OPCODE_CASE
:
635 return VGPU10_OPCODE_CASE
;
636 case TGSI_OPCODE_DEFAULT
:
637 return VGPU10_OPCODE_DEFAULT
;
638 case TGSI_OPCODE_ENDSWITCH
:
639 return VGPU10_OPCODE_ENDSWITCH
;
640 case TGSI_OPCODE_FSLT
:
641 return VGPU10_OPCODE_LT
;
642 case TGSI_OPCODE_ROUND
:
643 return VGPU10_OPCODE_ROUND_NE
;
645 assert(!"Unexpected TGSI opcode in translate_opcode()");
646 return VGPU10_OPCODE_NOP
;
652 * Translate a TGSI register file type into a VGPU10 operand type.
653 * \param array is the TGSI_FILE_TEMPORARY register an array?
655 static VGPU10_OPERAND_TYPE
656 translate_register_file(enum tgsi_file_type file
, boolean array
)
659 case TGSI_FILE_CONSTANT
:
660 return VGPU10_OPERAND_TYPE_CONSTANT_BUFFER
;
661 case TGSI_FILE_INPUT
:
662 return VGPU10_OPERAND_TYPE_INPUT
;
663 case TGSI_FILE_OUTPUT
:
664 return VGPU10_OPERAND_TYPE_OUTPUT
;
665 case TGSI_FILE_TEMPORARY
:
666 return array
? VGPU10_OPERAND_TYPE_INDEXABLE_TEMP
667 : VGPU10_OPERAND_TYPE_TEMP
;
668 case TGSI_FILE_IMMEDIATE
:
669 /* all immediates are 32-bit values at this time so
670 * VGPU10_OPERAND_TYPE_IMMEDIATE64 is not possible at this time.
672 return VGPU10_OPERAND_TYPE_IMMEDIATE_CONSTANT_BUFFER
;
673 case TGSI_FILE_SAMPLER
:
674 return VGPU10_OPERAND_TYPE_SAMPLER
;
675 case TGSI_FILE_SYSTEM_VALUE
:
676 return VGPU10_OPERAND_TYPE_INPUT
;
678 /* XXX TODO more cases to finish */
681 assert(!"Bad tgsi register file!");
682 return VGPU10_OPERAND_TYPE_NULL
;
688 * Emit a null dst register
691 emit_null_dst_register(struct svga_shader_emitter_v10
*emit
)
693 VGPU10OperandToken0 operand
;
696 operand
.operandType
= VGPU10_OPERAND_TYPE_NULL
;
697 operand
.numComponents
= VGPU10_OPERAND_0_COMPONENT
;
699 emit_dword(emit
, operand
.value
);
704 * If the given register is a temporary, return the array ID.
708 get_temp_array_id(const struct svga_shader_emitter_v10
*emit
,
709 enum tgsi_file_type file
, unsigned index
)
711 if (file
== TGSI_FILE_TEMPORARY
) {
712 return emit
->temp_map
[index
].arrayId
;
721 * If the given register is a temporary, convert the index from a TGSI
722 * TEMPORARY index to a VGPU10 temp index.
725 remap_temp_index(const struct svga_shader_emitter_v10
*emit
,
726 enum tgsi_file_type file
, unsigned index
)
728 if (file
== TGSI_FILE_TEMPORARY
) {
729 return emit
->temp_map
[index
].index
;
738 * Setup the operand0 fields related to indexing (1D, 2D, relative, etc).
739 * Note: the operandType field must already be initialized.
741 static VGPU10OperandToken0
742 setup_operand0_indexing(struct svga_shader_emitter_v10
*emit
,
743 VGPU10OperandToken0 operand0
,
744 enum tgsi_file_type file
,
745 boolean indirect
, boolean index2D
,
746 unsigned tempArrayID
)
748 unsigned indexDim
, index0Rep
, index1Rep
= VGPU10_OPERAND_INDEX_IMMEDIATE32
;
751 * Compute index dimensions
753 if (operand0
.operandType
== VGPU10_OPERAND_TYPE_IMMEDIATE32
||
754 operand0
.operandType
== VGPU10_OPERAND_TYPE_INPUT_PRIMITIVEID
) {
755 /* there's no swizzle for in-line immediates */
756 indexDim
= VGPU10_OPERAND_INDEX_0D
;
757 assert(operand0
.selectionMode
== 0);
762 operand0
.operandType
== VGPU10_OPERAND_TYPE_CONSTANT_BUFFER
) {
763 indexDim
= VGPU10_OPERAND_INDEX_2D
;
766 indexDim
= VGPU10_OPERAND_INDEX_1D
;
771 * Compute index representations (immediate, relative, etc).
773 if (tempArrayID
> 0) {
774 assert(file
== TGSI_FILE_TEMPORARY
);
775 /* First index is the array ID, second index is the array element */
776 index0Rep
= VGPU10_OPERAND_INDEX_IMMEDIATE32
;
778 index1Rep
= VGPU10_OPERAND_INDEX_IMMEDIATE32_PLUS_RELATIVE
;
781 index1Rep
= VGPU10_OPERAND_INDEX_IMMEDIATE32
;
785 if (file
== TGSI_FILE_CONSTANT
) {
786 /* index[0] indicates which constant buffer while index[1] indicates
787 * the position in the constant buffer.
789 index0Rep
= VGPU10_OPERAND_INDEX_IMMEDIATE32
;
790 index1Rep
= VGPU10_OPERAND_INDEX_IMMEDIATE32_PLUS_RELATIVE
;
793 /* All other register files are 1-dimensional */
794 index0Rep
= VGPU10_OPERAND_INDEX_IMMEDIATE32_PLUS_RELATIVE
;
798 index0Rep
= VGPU10_OPERAND_INDEX_IMMEDIATE32
;
799 index1Rep
= VGPU10_OPERAND_INDEX_IMMEDIATE32
;
802 operand0
.indexDimension
= indexDim
;
803 operand0
.index0Representation
= index0Rep
;
804 operand0
.index1Representation
= index1Rep
;
811 * Emit the operand for expressing an address register for indirect indexing.
812 * Note that the address register is really just a temp register.
813 * \param addr_reg_index which address register to use
816 emit_indirect_register(struct svga_shader_emitter_v10
*emit
,
817 unsigned addr_reg_index
)
819 unsigned tmp_reg_index
;
820 VGPU10OperandToken0 operand0
;
822 assert(addr_reg_index
< MAX_VGPU10_ADDR_REGS
);
824 tmp_reg_index
= emit
->address_reg_index
[addr_reg_index
];
826 /* operand0 is a simple temporary register, selecting one component */
828 operand0
.operandType
= VGPU10_OPERAND_TYPE_TEMP
;
829 operand0
.numComponents
= VGPU10_OPERAND_4_COMPONENT
;
830 operand0
.indexDimension
= VGPU10_OPERAND_INDEX_1D
;
831 operand0
.index0Representation
= VGPU10_OPERAND_INDEX_IMMEDIATE32
;
832 operand0
.selectionMode
= VGPU10_OPERAND_4_COMPONENT_SELECT_1_MODE
;
833 operand0
.swizzleX
= 0;
834 operand0
.swizzleY
= 1;
835 operand0
.swizzleZ
= 2;
836 operand0
.swizzleW
= 3;
838 emit_dword(emit
, operand0
.value
);
839 emit_dword(emit
, remap_temp_index(emit
, TGSI_FILE_TEMPORARY
, tmp_reg_index
));
844 * Translate the dst register of a TGSI instruction and emit VGPU10 tokens.
845 * \param emit the emitter context
846 * \param reg the TGSI dst register to translate
849 emit_dst_register(struct svga_shader_emitter_v10
*emit
,
850 const struct tgsi_full_dst_register
*reg
)
852 enum tgsi_file_type file
= reg
->Register
.File
;
853 unsigned index
= reg
->Register
.Index
;
854 const enum tgsi_semantic sem_name
= emit
->info
.output_semantic_name
[index
];
855 const unsigned sem_index
= emit
->info
.output_semantic_index
[index
];
856 unsigned writemask
= reg
->Register
.WriteMask
;
857 const unsigned indirect
= reg
->Register
.Indirect
;
858 const unsigned tempArrayId
= get_temp_array_id(emit
, file
, index
);
859 const unsigned index2d
= reg
->Register
.Dimension
;
860 VGPU10OperandToken0 operand0
;
862 if (file
== TGSI_FILE_OUTPUT
) {
863 if (emit
->unit
== PIPE_SHADER_VERTEX
||
864 emit
->unit
== PIPE_SHADER_GEOMETRY
) {
865 if (index
== emit
->vposition
.out_index
&&
866 emit
->vposition
.tmp_index
!= INVALID_INDEX
) {
867 /* replace OUTPUT[POS] with TEMP[POS]. We need to store the
868 * vertex position result in a temporary so that we can modify
869 * it in the post_helper() code.
871 file
= TGSI_FILE_TEMPORARY
;
872 index
= emit
->vposition
.tmp_index
;
874 else if (sem_name
== TGSI_SEMANTIC_CLIPDIST
&&
875 emit
->clip_dist_tmp_index
!= INVALID_INDEX
) {
876 /* replace OUTPUT[CLIPDIST] with TEMP[CLIPDIST].
877 * We store the clip distance in a temporary first, then
878 * we'll copy it to the shadow copy and to CLIPDIST with the
879 * enabled planes mask in emit_clip_distance_instructions().
881 file
= TGSI_FILE_TEMPORARY
;
882 index
= emit
->clip_dist_tmp_index
+ sem_index
;
884 else if (sem_name
== TGSI_SEMANTIC_CLIPVERTEX
&&
885 emit
->clip_vertex_tmp_index
!= INVALID_INDEX
) {
886 /* replace the CLIPVERTEX output register with a temporary */
887 assert(emit
->clip_mode
== CLIP_VERTEX
);
888 assert(sem_index
== 0);
889 file
= TGSI_FILE_TEMPORARY
;
890 index
= emit
->clip_vertex_tmp_index
;
893 else if (emit
->unit
== PIPE_SHADER_FRAGMENT
) {
894 if (sem_name
== TGSI_SEMANTIC_POSITION
) {
895 /* Fragment depth output register */
897 operand0
.operandType
= VGPU10_OPERAND_TYPE_OUTPUT_DEPTH
;
898 operand0
.indexDimension
= VGPU10_OPERAND_INDEX_0D
;
899 operand0
.numComponents
= VGPU10_OPERAND_1_COMPONENT
;
900 emit_dword(emit
, operand0
.value
);
903 else if (index
== emit
->fs
.color_out_index
[0] &&
904 emit
->fs
.color_tmp_index
!= INVALID_INDEX
) {
905 /* replace OUTPUT[COLOR] with TEMP[COLOR]. We need to store the
906 * fragment color result in a temporary so that we can read it
907 * it in the post_helper() code.
909 file
= TGSI_FILE_TEMPORARY
;
910 index
= emit
->fs
.color_tmp_index
;
913 /* Typically, for fragment shaders, the output register index
914 * matches the color semantic index. But not when we write to
915 * the fragment depth register. In that case, OUT[0] will be
916 * fragdepth and OUT[1] will be the 0th color output. We need
917 * to use the semantic index for color outputs.
919 assert(sem_name
== TGSI_SEMANTIC_COLOR
);
920 index
= emit
->info
.output_semantic_index
[index
];
922 emit
->num_output_writes
++;
927 /* init operand tokens to all zero */
930 operand0
.numComponents
= VGPU10_OPERAND_4_COMPONENT
;
932 /* the operand has a writemask */
933 operand0
.selectionMode
= VGPU10_OPERAND_4_COMPONENT_MASK_MODE
;
935 /* Which of the four dest components to write to. Note that we can use a
936 * simple assignment here since TGSI writemasks match VGPU10 writemasks.
938 STATIC_ASSERT(TGSI_WRITEMASK_X
== VGPU10_OPERAND_4_COMPONENT_MASK_X
);
939 operand0
.mask
= writemask
;
941 /* translate TGSI register file type to VGPU10 operand type */
942 operand0
.operandType
= translate_register_file(file
, tempArrayId
> 0);
944 check_register_index(emit
, operand0
.operandType
, index
);
946 operand0
= setup_operand0_indexing(emit
, operand0
, file
, indirect
,
947 index2d
, tempArrayId
);
950 emit_dword(emit
, operand0
.value
);
951 if (tempArrayId
> 0) {
952 emit_dword(emit
, tempArrayId
);
955 emit_dword(emit
, remap_temp_index(emit
, file
, index
));
958 emit_indirect_register(emit
, reg
->Indirect
.Index
);
964 * Translate a src register of a TGSI instruction and emit VGPU10 tokens.
967 emit_src_register(struct svga_shader_emitter_v10
*emit
,
968 const struct tgsi_full_src_register
*reg
)
970 enum tgsi_file_type file
= reg
->Register
.File
;
971 unsigned index
= reg
->Register
.Index
;
972 const unsigned indirect
= reg
->Register
.Indirect
;
973 const unsigned tempArrayId
= get_temp_array_id(emit
, file
, index
);
974 const unsigned index2d
= reg
->Register
.Dimension
;
975 const unsigned swizzleX
= reg
->Register
.SwizzleX
;
976 const unsigned swizzleY
= reg
->Register
.SwizzleY
;
977 const unsigned swizzleZ
= reg
->Register
.SwizzleZ
;
978 const unsigned swizzleW
= reg
->Register
.SwizzleW
;
979 const unsigned absolute
= reg
->Register
.Absolute
;
980 const unsigned negate
= reg
->Register
.Negate
;
981 bool is_prim_id
= FALSE
;
983 VGPU10OperandToken0 operand0
;
984 VGPU10OperandToken1 operand1
;
986 if (emit
->unit
== PIPE_SHADER_FRAGMENT
&&
987 file
== TGSI_FILE_INPUT
) {
988 if (index
== emit
->fs
.face_input_index
) {
989 /* Replace INPUT[FACE] with TEMP[FACE] */
990 file
= TGSI_FILE_TEMPORARY
;
991 index
= emit
->fs
.face_tmp_index
;
993 else if (index
== emit
->fs
.fragcoord_input_index
) {
994 /* Replace INPUT[POSITION] with TEMP[POSITION] */
995 file
= TGSI_FILE_TEMPORARY
;
996 index
= emit
->fs
.fragcoord_tmp_index
;
999 /* We remap fragment shader inputs to that FS input indexes
1000 * match up with VS/GS output indexes.
1002 index
= emit
->linkage
.input_map
[index
];
1005 else if (emit
->unit
== PIPE_SHADER_GEOMETRY
&&
1006 file
== TGSI_FILE_INPUT
) {
1007 is_prim_id
= (index
== emit
->gs
.prim_id_index
);
1008 index
= emit
->linkage
.input_map
[index
];
1010 else if (emit
->unit
== PIPE_SHADER_VERTEX
) {
1011 if (file
== TGSI_FILE_INPUT
) {
1012 /* if input is adjusted... */
1013 if ((emit
->key
.vs
.adjust_attrib_w_1
|
1014 emit
->key
.vs
.adjust_attrib_itof
|
1015 emit
->key
.vs
.adjust_attrib_utof
|
1016 emit
->key
.vs
.attrib_is_bgra
|
1017 emit
->key
.vs
.attrib_puint_to_snorm
|
1018 emit
->key
.vs
.attrib_puint_to_uscaled
|
1019 emit
->key
.vs
.attrib_puint_to_sscaled
) & (1 << index
)) {
1020 file
= TGSI_FILE_TEMPORARY
;
1021 index
= emit
->vs
.adjusted_input
[index
];
1024 else if (file
== TGSI_FILE_SYSTEM_VALUE
) {
1025 assert(index
< ARRAY_SIZE(emit
->system_value_indexes
));
1026 index
= emit
->system_value_indexes
[index
];
1030 operand0
.value
= operand1
.value
= 0;
1033 /* NOTE: we should be using VGPU10_OPERAND_1_COMPONENT here, but
1034 * our virtual GPU accepts this as-is.
1036 operand0
.numComponents
= VGPU10_OPERAND_0_COMPONENT
;
1037 operand0
.operandType
= VGPU10_OPERAND_TYPE_INPUT_PRIMITIVEID
;
1040 operand0
.numComponents
= VGPU10_OPERAND_4_COMPONENT
;
1041 operand0
.operandType
= translate_register_file(file
, tempArrayId
> 0);
1044 operand0
= setup_operand0_indexing(emit
, operand0
, file
, indirect
,
1045 index2d
, tempArrayId
);
1047 if (operand0
.operandType
!= VGPU10_OPERAND_TYPE_IMMEDIATE32
&&
1048 operand0
.operandType
!= VGPU10_OPERAND_TYPE_INPUT_PRIMITIVEID
) {
1049 /* there's no swizzle for in-line immediates */
1050 if (swizzleX
== swizzleY
&&
1051 swizzleX
== swizzleZ
&&
1052 swizzleX
== swizzleW
) {
1053 operand0
.selectionMode
= VGPU10_OPERAND_4_COMPONENT_SELECT_1_MODE
;
1056 operand0
.selectionMode
= VGPU10_OPERAND_4_COMPONENT_SWIZZLE_MODE
;
1059 operand0
.swizzleX
= swizzleX
;
1060 operand0
.swizzleY
= swizzleY
;
1061 operand0
.swizzleZ
= swizzleZ
;
1062 operand0
.swizzleW
= swizzleW
;
1064 if (absolute
|| negate
) {
1065 operand0
.extended
= 1;
1066 operand1
.extendedOperandType
= VGPU10_EXTENDED_OPERAND_MODIFIER
;
1067 if (absolute
&& !negate
)
1068 operand1
.operandModifier
= VGPU10_OPERAND_MODIFIER_ABS
;
1069 if (!absolute
&& negate
)
1070 operand1
.operandModifier
= VGPU10_OPERAND_MODIFIER_NEG
;
1071 if (absolute
&& negate
)
1072 operand1
.operandModifier
= VGPU10_OPERAND_MODIFIER_ABSNEG
;
1076 /* Emit the operand tokens */
1077 emit_dword(emit
, operand0
.value
);
1078 if (operand0
.extended
)
1079 emit_dword(emit
, operand1
.value
);
1081 if (operand0
.operandType
== VGPU10_OPERAND_TYPE_IMMEDIATE32
) {
1082 /* Emit the four float/int in-line immediate values */
1084 assert(index
< ARRAY_SIZE(emit
->immediates
));
1085 assert(file
== TGSI_FILE_IMMEDIATE
);
1086 assert(swizzleX
< 4);
1087 assert(swizzleY
< 4);
1088 assert(swizzleZ
< 4);
1089 assert(swizzleW
< 4);
1090 c
= (unsigned *) emit
->immediates
[index
];
1091 emit_dword(emit
, c
[swizzleX
]);
1092 emit_dword(emit
, c
[swizzleY
]);
1093 emit_dword(emit
, c
[swizzleZ
]);
1094 emit_dword(emit
, c
[swizzleW
]);
1096 else if (operand0
.indexDimension
>= VGPU10_OPERAND_INDEX_1D
) {
1097 /* Emit the register index(es) */
1099 operand0
.operandType
== VGPU10_OPERAND_TYPE_CONSTANT_BUFFER
) {
1100 emit_dword(emit
, reg
->Dimension
.Index
);
1103 if (tempArrayId
> 0) {
1104 emit_dword(emit
, tempArrayId
);
1107 emit_dword(emit
, remap_temp_index(emit
, file
, index
));
1110 emit_indirect_register(emit
, reg
->Indirect
.Index
);
1117 * Emit a resource operand (for use with a SAMPLE instruction).
1120 emit_resource_register(struct svga_shader_emitter_v10
*emit
,
1121 unsigned resource_number
)
1123 VGPU10OperandToken0 operand0
;
1125 check_register_index(emit
, VGPU10_OPERAND_TYPE_RESOURCE
, resource_number
);
1130 operand0
.operandType
= VGPU10_OPERAND_TYPE_RESOURCE
;
1131 operand0
.indexDimension
= VGPU10_OPERAND_INDEX_1D
;
1132 operand0
.numComponents
= VGPU10_OPERAND_4_COMPONENT
;
1133 operand0
.selectionMode
= VGPU10_OPERAND_4_COMPONENT_SWIZZLE_MODE
;
1134 operand0
.swizzleX
= VGPU10_COMPONENT_X
;
1135 operand0
.swizzleY
= VGPU10_COMPONENT_Y
;
1136 operand0
.swizzleZ
= VGPU10_COMPONENT_Z
;
1137 operand0
.swizzleW
= VGPU10_COMPONENT_W
;
1139 emit_dword(emit
, operand0
.value
);
1140 emit_dword(emit
, resource_number
);
1145 * Emit a sampler operand (for use with a SAMPLE instruction).
1148 emit_sampler_register(struct svga_shader_emitter_v10
*emit
,
1149 unsigned sampler_number
)
1151 VGPU10OperandToken0 operand0
;
1153 check_register_index(emit
, VGPU10_OPERAND_TYPE_SAMPLER
, sampler_number
);
1158 operand0
.operandType
= VGPU10_OPERAND_TYPE_SAMPLER
;
1159 operand0
.indexDimension
= VGPU10_OPERAND_INDEX_1D
;
1161 emit_dword(emit
, operand0
.value
);
1162 emit_dword(emit
, sampler_number
);
1167 * Emit an operand which reads the IS_FRONT_FACING register.
1170 emit_face_register(struct svga_shader_emitter_v10
*emit
)
1172 VGPU10OperandToken0 operand0
;
1173 unsigned index
= emit
->linkage
.input_map
[emit
->fs
.face_input_index
];
1178 operand0
.operandType
= VGPU10_OPERAND_TYPE_INPUT
;
1179 operand0
.indexDimension
= VGPU10_OPERAND_INDEX_1D
;
1180 operand0
.selectionMode
= VGPU10_OPERAND_4_COMPONENT_SELECT_1_MODE
;
1181 operand0
.numComponents
= VGPU10_OPERAND_4_COMPONENT
;
1183 operand0
.swizzleX
= VGPU10_COMPONENT_X
;
1184 operand0
.swizzleY
= VGPU10_COMPONENT_X
;
1185 operand0
.swizzleZ
= VGPU10_COMPONENT_X
;
1186 operand0
.swizzleW
= VGPU10_COMPONENT_X
;
1188 emit_dword(emit
, operand0
.value
);
1189 emit_dword(emit
, index
);
1194 * Emit the token for a VGPU10 opcode.
1195 * \param saturate clamp result to [0,1]?
1198 emit_opcode(struct svga_shader_emitter_v10
*emit
,
1199 unsigned vgpu10_opcode
, boolean saturate
)
1201 VGPU10OpcodeToken0 token0
;
1203 token0
.value
= 0; /* init all fields to zero */
1204 token0
.opcodeType
= vgpu10_opcode
;
1205 token0
.instructionLength
= 0; /* Filled in by end_emit_instruction() */
1206 token0
.saturate
= saturate
;
1208 emit_dword(emit
, token0
.value
);
1213 * Emit the token for a VGPU10 resinfo instruction.
1214 * \param modifier return type modifier, _uint or _rcpFloat.
1215 * TODO: We may want to remove this parameter if it will
1216 * only ever be used as _uint.
1219 emit_opcode_resinfo(struct svga_shader_emitter_v10
*emit
,
1220 VGPU10_RESINFO_RETURN_TYPE modifier
)
1222 VGPU10OpcodeToken0 token0
;
1224 token0
.value
= 0; /* init all fields to zero */
1225 token0
.opcodeType
= VGPU10_OPCODE_RESINFO
;
1226 token0
.instructionLength
= 0; /* Filled in by end_emit_instruction() */
1227 token0
.resinfoReturnType
= modifier
;
1229 emit_dword(emit
, token0
.value
);
1234 * Emit opcode tokens for a texture sample instruction. Texture instructions
1235 * can be rather complicated (texel offsets, etc) so we have this specialized
1239 emit_sample_opcode(struct svga_shader_emitter_v10
*emit
,
1240 unsigned vgpu10_opcode
, boolean saturate
,
1241 const int offsets
[3])
1243 VGPU10OpcodeToken0 token0
;
1244 VGPU10OpcodeToken1 token1
;
1246 token0
.value
= 0; /* init all fields to zero */
1247 token0
.opcodeType
= vgpu10_opcode
;
1248 token0
.instructionLength
= 0; /* Filled in by end_emit_instruction() */
1249 token0
.saturate
= saturate
;
1251 if (offsets
[0] || offsets
[1] || offsets
[2]) {
1252 assert(offsets
[0] >= VGPU10_MIN_TEXEL_FETCH_OFFSET
);
1253 assert(offsets
[1] >= VGPU10_MIN_TEXEL_FETCH_OFFSET
);
1254 assert(offsets
[2] >= VGPU10_MIN_TEXEL_FETCH_OFFSET
);
1255 assert(offsets
[0] <= VGPU10_MAX_TEXEL_FETCH_OFFSET
);
1256 assert(offsets
[1] <= VGPU10_MAX_TEXEL_FETCH_OFFSET
);
1257 assert(offsets
[2] <= VGPU10_MAX_TEXEL_FETCH_OFFSET
);
1259 token0
.extended
= 1;
1261 token1
.opcodeType
= VGPU10_EXTENDED_OPCODE_SAMPLE_CONTROLS
;
1262 token1
.offsetU
= offsets
[0];
1263 token1
.offsetV
= offsets
[1];
1264 token1
.offsetW
= offsets
[2];
1267 emit_dword(emit
, token0
.value
);
1268 if (token0
.extended
) {
1269 emit_dword(emit
, token1
.value
);
1275 * Emit a DISCARD opcode token.
1276 * If nonzero is set, we'll discard the fragment if the X component is not 0.
1277 * Otherwise, we'll discard the fragment if the X component is 0.
1280 emit_discard_opcode(struct svga_shader_emitter_v10
*emit
, boolean nonzero
)
1282 VGPU10OpcodeToken0 opcode0
;
1285 opcode0
.opcodeType
= VGPU10_OPCODE_DISCARD
;
1287 opcode0
.testBoolean
= VGPU10_INSTRUCTION_TEST_NONZERO
;
1289 emit_dword(emit
, opcode0
.value
);
1294 * We need to call this before we begin emitting a VGPU10 instruction.
1297 begin_emit_instruction(struct svga_shader_emitter_v10
*emit
)
1299 assert(emit
->inst_start_token
== 0);
1300 /* Save location of the instruction's VGPU10OpcodeToken0 token.
1301 * Note, we can't save a pointer because it would become invalid if
1302 * we have to realloc the output buffer.
1304 emit
->inst_start_token
= emit_get_num_tokens(emit
);
1309 * We need to call this after we emit the last token of a VGPU10 instruction.
1310 * This function patches in the opcode token's instructionLength field.
1313 end_emit_instruction(struct svga_shader_emitter_v10
*emit
)
1315 VGPU10OpcodeToken0
*tokens
= (VGPU10OpcodeToken0
*) emit
->buf
;
1316 unsigned inst_length
;
1318 assert(emit
->inst_start_token
> 0);
1320 if (emit
->discard_instruction
) {
1321 /* Back up the emit->ptr to where this instruction started so
1322 * that we discard the current instruction.
1324 emit
->ptr
= (char *) (tokens
+ emit
->inst_start_token
);
1327 /* Compute instruction length and patch that into the start of
1330 inst_length
= emit_get_num_tokens(emit
) - emit
->inst_start_token
;
1332 assert(inst_length
> 0);
1334 tokens
[emit
->inst_start_token
].instructionLength
= inst_length
;
1337 emit
->inst_start_token
= 0; /* reset to zero for error checking */
1338 emit
->discard_instruction
= FALSE
;
1343 * Return index for a free temporary register.
1346 get_temp_index(struct svga_shader_emitter_v10
*emit
)
1348 assert(emit
->internal_temp_count
< MAX_INTERNAL_TEMPS
);
1349 return emit
->num_shader_temps
+ emit
->internal_temp_count
++;
1354 * Release the temporaries which were generated by get_temp_index().
1357 free_temp_indexes(struct svga_shader_emitter_v10
*emit
)
1359 emit
->internal_temp_count
= 0;
1364 * Create a tgsi_full_src_register.
1366 static struct tgsi_full_src_register
1367 make_src_reg(enum tgsi_file_type file
, unsigned index
)
1369 struct tgsi_full_src_register reg
;
1371 memset(®
, 0, sizeof(reg
));
1372 reg
.Register
.File
= file
;
1373 reg
.Register
.Index
= index
;
1374 reg
.Register
.SwizzleX
= TGSI_SWIZZLE_X
;
1375 reg
.Register
.SwizzleY
= TGSI_SWIZZLE_Y
;
1376 reg
.Register
.SwizzleZ
= TGSI_SWIZZLE_Z
;
1377 reg
.Register
.SwizzleW
= TGSI_SWIZZLE_W
;
1383 * Create a tgsi_full_src_register for a temporary.
1385 static struct tgsi_full_src_register
1386 make_src_temp_reg(unsigned index
)
1388 return make_src_reg(TGSI_FILE_TEMPORARY
, index
);
1393 * Create a tgsi_full_src_register for a constant.
1395 static struct tgsi_full_src_register
1396 make_src_const_reg(unsigned index
)
1398 return make_src_reg(TGSI_FILE_CONSTANT
, index
);
1403 * Create a tgsi_full_src_register for an immediate constant.
1405 static struct tgsi_full_src_register
1406 make_src_immediate_reg(unsigned index
)
1408 return make_src_reg(TGSI_FILE_IMMEDIATE
, index
);
1413 * Create a tgsi_full_dst_register.
1415 static struct tgsi_full_dst_register
1416 make_dst_reg(enum tgsi_file_type file
, unsigned index
)
1418 struct tgsi_full_dst_register reg
;
1420 memset(®
, 0, sizeof(reg
));
1421 reg
.Register
.File
= file
;
1422 reg
.Register
.Index
= index
;
1423 reg
.Register
.WriteMask
= TGSI_WRITEMASK_XYZW
;
1429 * Create a tgsi_full_dst_register for a temporary.
1431 static struct tgsi_full_dst_register
1432 make_dst_temp_reg(unsigned index
)
1434 return make_dst_reg(TGSI_FILE_TEMPORARY
, index
);
1439 * Create a tgsi_full_dst_register for an output.
1441 static struct tgsi_full_dst_register
1442 make_dst_output_reg(unsigned index
)
1444 return make_dst_reg(TGSI_FILE_OUTPUT
, index
);
1449 * Create negated tgsi_full_src_register.
1451 static struct tgsi_full_src_register
1452 negate_src(const struct tgsi_full_src_register
*reg
)
1454 struct tgsi_full_src_register neg
= *reg
;
1455 neg
.Register
.Negate
= !reg
->Register
.Negate
;
1460 * Create absolute value of a tgsi_full_src_register.
1462 static struct tgsi_full_src_register
1463 absolute_src(const struct tgsi_full_src_register
*reg
)
1465 struct tgsi_full_src_register absolute
= *reg
;
1466 absolute
.Register
.Absolute
= 1;
1471 /** Return the named swizzle term from the src register */
1472 static inline unsigned
1473 get_swizzle(const struct tgsi_full_src_register
*reg
, enum tgsi_swizzle term
)
1476 case TGSI_SWIZZLE_X
:
1477 return reg
->Register
.SwizzleX
;
1478 case TGSI_SWIZZLE_Y
:
1479 return reg
->Register
.SwizzleY
;
1480 case TGSI_SWIZZLE_Z
:
1481 return reg
->Register
.SwizzleZ
;
1482 case TGSI_SWIZZLE_W
:
1483 return reg
->Register
.SwizzleW
;
1485 assert(!"Bad swizzle");
1486 return TGSI_SWIZZLE_X
;
1492 * Create swizzled tgsi_full_src_register.
1494 static struct tgsi_full_src_register
1495 swizzle_src(const struct tgsi_full_src_register
*reg
,
1496 enum tgsi_swizzle swizzleX
, enum tgsi_swizzle swizzleY
,
1497 enum tgsi_swizzle swizzleZ
, enum tgsi_swizzle swizzleW
)
1499 struct tgsi_full_src_register swizzled
= *reg
;
1500 /* Note: we swizzle the current swizzle */
1501 swizzled
.Register
.SwizzleX
= get_swizzle(reg
, swizzleX
);
1502 swizzled
.Register
.SwizzleY
= get_swizzle(reg
, swizzleY
);
1503 swizzled
.Register
.SwizzleZ
= get_swizzle(reg
, swizzleZ
);
1504 swizzled
.Register
.SwizzleW
= get_swizzle(reg
, swizzleW
);
1510 * Create swizzled tgsi_full_src_register where all the swizzle
1511 * terms are the same.
1513 static struct tgsi_full_src_register
1514 scalar_src(const struct tgsi_full_src_register
*reg
, enum tgsi_swizzle swizzle
)
1516 struct tgsi_full_src_register swizzled
= *reg
;
1517 /* Note: we swizzle the current swizzle */
1518 swizzled
.Register
.SwizzleX
=
1519 swizzled
.Register
.SwizzleY
=
1520 swizzled
.Register
.SwizzleZ
=
1521 swizzled
.Register
.SwizzleW
= get_swizzle(reg
, swizzle
);
1527 * Create new tgsi_full_dst_register with writemask.
1528 * \param mask bitmask of TGSI_WRITEMASK_[XYZW]
1530 static struct tgsi_full_dst_register
1531 writemask_dst(const struct tgsi_full_dst_register
*reg
, unsigned mask
)
1533 struct tgsi_full_dst_register masked
= *reg
;
1534 masked
.Register
.WriteMask
= mask
;
1540 * Check if the register's swizzle is XXXX, YYYY, ZZZZ, or WWWW.
1543 same_swizzle_terms(const struct tgsi_full_src_register
*reg
)
1545 return (reg
->Register
.SwizzleX
== reg
->Register
.SwizzleY
&&
1546 reg
->Register
.SwizzleY
== reg
->Register
.SwizzleZ
&&
1547 reg
->Register
.SwizzleZ
== reg
->Register
.SwizzleW
);
1552 * Search the vector for the value 'x' and return its position.
1555 find_imm_in_vec4(const union tgsi_immediate_data vec
[4],
1556 union tgsi_immediate_data x
)
1559 for (i
= 0; i
< 4; i
++) {
1560 if (vec
[i
].Int
== x
.Int
)
1568 * Helper used by make_immediate_reg(), make_immediate_reg_4().
1571 find_immediate(struct svga_shader_emitter_v10
*emit
,
1572 union tgsi_immediate_data x
, unsigned startIndex
)
1574 const unsigned endIndex
= emit
->num_immediates
;
1577 assert(emit
->immediates_emitted
);
1579 /* Search immediates for x, y, z, w */
1580 for (i
= startIndex
; i
< endIndex
; i
++) {
1581 if (x
.Int
== emit
->immediates
[i
][0].Int
||
1582 x
.Int
== emit
->immediates
[i
][1].Int
||
1583 x
.Int
== emit
->immediates
[i
][2].Int
||
1584 x
.Int
== emit
->immediates
[i
][3].Int
) {
1588 /* Should never try to use an immediate value that wasn't pre-declared */
1589 assert(!"find_immediate() failed!");
1595 * Return a tgsi_full_src_register for an immediate/literal
1596 * union tgsi_immediate_data[4] value.
1597 * Note: the values must have been previously declared/allocated in
1598 * emit_pre_helpers(). And, all of x,y,z,w must be located in the same
1601 static struct tgsi_full_src_register
1602 make_immediate_reg_4(struct svga_shader_emitter_v10
*emit
,
1603 const union tgsi_immediate_data imm
[4])
1605 struct tgsi_full_src_register reg
;
1608 for (i
= 0; i
< emit
->num_common_immediates
; i
++) {
1609 /* search for first component value */
1610 int immpos
= find_immediate(emit
, imm
[0], i
);
1613 assert(immpos
>= 0);
1615 /* find remaining components within the immediate vector */
1616 x
= find_imm_in_vec4(emit
->immediates
[immpos
], imm
[0]);
1617 y
= find_imm_in_vec4(emit
->immediates
[immpos
], imm
[1]);
1618 z
= find_imm_in_vec4(emit
->immediates
[immpos
], imm
[2]);
1619 w
= find_imm_in_vec4(emit
->immediates
[immpos
], imm
[3]);
1621 if (x
>=0 && y
>= 0 && z
>= 0 && w
>= 0) {
1622 /* found them all */
1623 memset(®
, 0, sizeof(reg
));
1624 reg
.Register
.File
= TGSI_FILE_IMMEDIATE
;
1625 reg
.Register
.Index
= immpos
;
1626 reg
.Register
.SwizzleX
= x
;
1627 reg
.Register
.SwizzleY
= y
;
1628 reg
.Register
.SwizzleZ
= z
;
1629 reg
.Register
.SwizzleW
= w
;
1632 /* else, keep searching */
1635 assert(!"Failed to find immediate register!");
1637 /* Just return IMM[0].xxxx */
1638 memset(®
, 0, sizeof(reg
));
1639 reg
.Register
.File
= TGSI_FILE_IMMEDIATE
;
1645 * Return a tgsi_full_src_register for an immediate/literal
1646 * union tgsi_immediate_data value of the form {value, value, value, value}.
1647 * \sa make_immediate_reg_4() regarding allowed values.
1649 static struct tgsi_full_src_register
1650 make_immediate_reg(struct svga_shader_emitter_v10
*emit
,
1651 union tgsi_immediate_data value
)
1653 struct tgsi_full_src_register reg
;
1654 int immpos
= find_immediate(emit
, value
, 0);
1656 assert(immpos
>= 0);
1658 memset(®
, 0, sizeof(reg
));
1659 reg
.Register
.File
= TGSI_FILE_IMMEDIATE
;
1660 reg
.Register
.Index
= immpos
;
1661 reg
.Register
.SwizzleX
=
1662 reg
.Register
.SwizzleY
=
1663 reg
.Register
.SwizzleZ
=
1664 reg
.Register
.SwizzleW
= find_imm_in_vec4(emit
->immediates
[immpos
], value
);
1671 * Return a tgsi_full_src_register for an immediate/literal float[4] value.
1672 * \sa make_immediate_reg_4() regarding allowed values.
1674 static struct tgsi_full_src_register
1675 make_immediate_reg_float4(struct svga_shader_emitter_v10
*emit
,
1676 float x
, float y
, float z
, float w
)
1678 union tgsi_immediate_data imm
[4];
1683 return make_immediate_reg_4(emit
, imm
);
1688 * Return a tgsi_full_src_register for an immediate/literal float value
1689 * of the form {value, value, value, value}.
1690 * \sa make_immediate_reg_4() regarding allowed values.
1692 static struct tgsi_full_src_register
1693 make_immediate_reg_float(struct svga_shader_emitter_v10
*emit
, float value
)
1695 union tgsi_immediate_data imm
;
1697 return make_immediate_reg(emit
, imm
);
1702 * Return a tgsi_full_src_register for an immediate/literal int[4] vector.
1704 static struct tgsi_full_src_register
1705 make_immediate_reg_int4(struct svga_shader_emitter_v10
*emit
,
1706 int x
, int y
, int z
, int w
)
1708 union tgsi_immediate_data imm
[4];
1713 return make_immediate_reg_4(emit
, imm
);
1718 * Return a tgsi_full_src_register for an immediate/literal int value
1719 * of the form {value, value, value, value}.
1720 * \sa make_immediate_reg_4() regarding allowed values.
1722 static struct tgsi_full_src_register
1723 make_immediate_reg_int(struct svga_shader_emitter_v10
*emit
, int value
)
1725 union tgsi_immediate_data imm
;
1727 return make_immediate_reg(emit
, imm
);
1732 * Allocate space for a union tgsi_immediate_data[4] immediate.
1733 * \return the index/position of the immediate.
1736 alloc_immediate_4(struct svga_shader_emitter_v10
*emit
,
1737 const union tgsi_immediate_data imm
[4])
1739 unsigned n
= emit
->num_immediates
++;
1740 assert(!emit
->immediates_emitted
);
1741 assert(n
< ARRAY_SIZE(emit
->immediates
));
1742 emit
->immediates
[n
][0] = imm
[0];
1743 emit
->immediates
[n
][1] = imm
[1];
1744 emit
->immediates
[n
][2] = imm
[2];
1745 emit
->immediates
[n
][3] = imm
[3];
1751 * Allocate space for a float[4] immediate.
1752 * \return the index/position of the immediate.
1755 alloc_immediate_float4(struct svga_shader_emitter_v10
*emit
,
1756 float x
, float y
, float z
, float w
)
1758 union tgsi_immediate_data imm
[4];
1763 return alloc_immediate_4(emit
, imm
);
1768 * Allocate space for an int[4] immediate.
1769 * \return the index/position of the immediate.
1772 alloc_immediate_int4(struct svga_shader_emitter_v10
*emit
,
1773 int x
, int y
, int z
, int w
)
1775 union tgsi_immediate_data imm
[4];
1780 return alloc_immediate_4(emit
, imm
);
1785 * Allocate a shader input to store a system value.
1788 alloc_system_value_index(struct svga_shader_emitter_v10
*emit
, unsigned index
)
1790 const unsigned n
= emit
->info
.file_max
[TGSI_FILE_INPUT
] + 1 + index
;
1791 assert(index
< ARRAY_SIZE(emit
->system_value_indexes
));
1792 emit
->system_value_indexes
[index
] = n
;
1798 * Translate a TGSI immediate value (union tgsi_immediate_data[4]) to VGPU10.
1801 emit_vgpu10_immediate(struct svga_shader_emitter_v10
*emit
,
1802 const struct tgsi_full_immediate
*imm
)
1804 /* We don't actually emit any code here. We just save the
1805 * immediate values and emit them later.
1807 alloc_immediate_4(emit
, imm
->u
);
1813 * Emit a VGPU10_CUSTOMDATA_DCL_IMMEDIATE_CONSTANT_BUFFER block
1814 * containing all the immediate values previously allocated
1815 * with alloc_immediate_4().
1818 emit_vgpu10_immediates_block(struct svga_shader_emitter_v10
*emit
)
1820 VGPU10OpcodeToken0 token
;
1822 assert(!emit
->immediates_emitted
);
1825 token
.opcodeType
= VGPU10_OPCODE_CUSTOMDATA
;
1826 token
.customDataClass
= VGPU10_CUSTOMDATA_DCL_IMMEDIATE_CONSTANT_BUFFER
;
1828 /* Note: no begin/end_emit_instruction() calls */
1829 emit_dword(emit
, token
.value
);
1830 emit_dword(emit
, 2 + 4 * emit
->num_immediates
);
1831 emit_dwords(emit
, (unsigned *) emit
->immediates
, 4 * emit
->num_immediates
);
1833 emit
->immediates_emitted
= TRUE
;
1840 * Translate a fragment shader's TGSI_INTERPOLATE_x mode to a vgpu10
1841 * interpolation mode.
1842 * \return a VGPU10_INTERPOLATION_x value
1845 translate_interpolation(const struct svga_shader_emitter_v10
*emit
,
1846 enum tgsi_interpolate_mode interp
,
1847 enum tgsi_interpolate_loc interpolate_loc
)
1849 if (interp
== TGSI_INTERPOLATE_COLOR
) {
1850 interp
= emit
->key
.fs
.flatshade
?
1851 TGSI_INTERPOLATE_CONSTANT
: TGSI_INTERPOLATE_PERSPECTIVE
;
1855 case TGSI_INTERPOLATE_CONSTANT
:
1856 return VGPU10_INTERPOLATION_CONSTANT
;
1857 case TGSI_INTERPOLATE_LINEAR
:
1858 return interpolate_loc
== TGSI_INTERPOLATE_LOC_CENTROID
?
1859 VGPU10_INTERPOLATION_LINEAR_NOPERSPECTIVE_CENTROID
:
1860 VGPU10_INTERPOLATION_LINEAR_NOPERSPECTIVE
;
1861 case TGSI_INTERPOLATE_PERSPECTIVE
:
1862 return interpolate_loc
== TGSI_INTERPOLATE_LOC_CENTROID
?
1863 VGPU10_INTERPOLATION_LINEAR_CENTROID
:
1864 VGPU10_INTERPOLATION_LINEAR
;
1866 assert(!"Unexpected interpolation mode");
1867 return VGPU10_INTERPOLATION_CONSTANT
;
1873 * Translate a TGSI property to VGPU10.
1874 * Don't emit any instructions yet, only need to gather the primitive property information.
1875 * The output primitive topology might be changed later. The final property instructions
1876 * will be emitted as part of the pre-helper code.
1879 emit_vgpu10_property(struct svga_shader_emitter_v10
*emit
,
1880 const struct tgsi_full_property
*prop
)
1882 static const VGPU10_PRIMITIVE primType
[] = {
1883 VGPU10_PRIMITIVE_POINT
, /* PIPE_PRIM_POINTS */
1884 VGPU10_PRIMITIVE_LINE
, /* PIPE_PRIM_LINES */
1885 VGPU10_PRIMITIVE_LINE
, /* PIPE_PRIM_LINE_LOOP */
1886 VGPU10_PRIMITIVE_LINE
, /* PIPE_PRIM_LINE_STRIP */
1887 VGPU10_PRIMITIVE_TRIANGLE
, /* PIPE_PRIM_TRIANGLES */
1888 VGPU10_PRIMITIVE_TRIANGLE
, /* PIPE_PRIM_TRIANGLE_STRIP */
1889 VGPU10_PRIMITIVE_TRIANGLE
, /* PIPE_PRIM_TRIANGLE_FAN */
1890 VGPU10_PRIMITIVE_UNDEFINED
, /* PIPE_PRIM_QUADS */
1891 VGPU10_PRIMITIVE_UNDEFINED
, /* PIPE_PRIM_QUAD_STRIP */
1892 VGPU10_PRIMITIVE_UNDEFINED
, /* PIPE_PRIM_POLYGON */
1893 VGPU10_PRIMITIVE_LINE_ADJ
, /* PIPE_PRIM_LINES_ADJACENCY */
1894 VGPU10_PRIMITIVE_LINE_ADJ
, /* PIPE_PRIM_LINE_STRIP_ADJACENCY */
1895 VGPU10_PRIMITIVE_TRIANGLE_ADJ
, /* PIPE_PRIM_TRIANGLES_ADJACENCY */
1896 VGPU10_PRIMITIVE_TRIANGLE_ADJ
/* PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY */
1899 static const VGPU10_PRIMITIVE_TOPOLOGY primTopology
[] = {
1900 VGPU10_PRIMITIVE_TOPOLOGY_POINTLIST
, /* PIPE_PRIM_POINTS */
1901 VGPU10_PRIMITIVE_TOPOLOGY_LINELIST
, /* PIPE_PRIM_LINES */
1902 VGPU10_PRIMITIVE_TOPOLOGY_LINELIST
, /* PIPE_PRIM_LINE_LOOP */
1903 VGPU10_PRIMITIVE_TOPOLOGY_LINESTRIP
, /* PIPE_PRIM_LINE_STRIP */
1904 VGPU10_PRIMITIVE_TOPOLOGY_TRIANGLELIST
, /* PIPE_PRIM_TRIANGLES */
1905 VGPU10_PRIMITIVE_TOPOLOGY_TRIANGLESTRIP
, /* PIPE_PRIM_TRIANGLE_STRIP */
1906 VGPU10_PRIMITIVE_TOPOLOGY_TRIANGLESTRIP
, /* PIPE_PRIM_TRIANGLE_FAN */
1907 VGPU10_PRIMITIVE_TOPOLOGY_UNDEFINED
, /* PIPE_PRIM_QUADS */
1908 VGPU10_PRIMITIVE_TOPOLOGY_UNDEFINED
, /* PIPE_PRIM_QUAD_STRIP */
1909 VGPU10_PRIMITIVE_TOPOLOGY_UNDEFINED
, /* PIPE_PRIM_POLYGON */
1910 VGPU10_PRIMITIVE_TOPOLOGY_LINELIST_ADJ
, /* PIPE_PRIM_LINES_ADJACENCY */
1911 VGPU10_PRIMITIVE_TOPOLOGY_LINELIST_ADJ
, /* PIPE_PRIM_LINE_STRIP_ADJACENCY */
1912 VGPU10_PRIMITIVE_TOPOLOGY_TRIANGLELIST_ADJ
, /* PIPE_PRIM_TRIANGLES_ADJACENCY */
1913 VGPU10_PRIMITIVE_TOPOLOGY_TRIANGLESTRIP_ADJ
/* PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY */
1916 static const unsigned inputArraySize
[] = {
1917 0, /* VGPU10_PRIMITIVE_UNDEFINED */
1918 1, /* VGPU10_PRIMITIVE_POINT */
1919 2, /* VGPU10_PRIMITIVE_LINE */
1920 3, /* VGPU10_PRIMITIVE_TRIANGLE */
1923 4, /* VGPU10_PRIMITIVE_LINE_ADJ */
1924 6 /* VGPU10_PRIMITIVE_TRIANGLE_ADJ */
1927 switch (prop
->Property
.PropertyName
) {
1928 case TGSI_PROPERTY_GS_INPUT_PRIM
:
1929 assert(prop
->u
[0].Data
< ARRAY_SIZE(primType
));
1930 emit
->gs
.prim_type
= primType
[prop
->u
[0].Data
];
1931 assert(emit
->gs
.prim_type
!= VGPU10_PRIMITIVE_UNDEFINED
);
1932 emit
->gs
.input_size
= inputArraySize
[emit
->gs
.prim_type
];
1935 case TGSI_PROPERTY_GS_OUTPUT_PRIM
:
1936 assert(prop
->u
[0].Data
< ARRAY_SIZE(primTopology
));
1937 emit
->gs
.prim_topology
= primTopology
[prop
->u
[0].Data
];
1938 assert(emit
->gs
.prim_topology
!= VGPU10_PRIMITIVE_TOPOLOGY_UNDEFINED
);
1941 case TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
:
1942 emit
->gs
.max_out_vertices
= prop
->u
[0].Data
;
1954 emit_property_instruction(struct svga_shader_emitter_v10
*emit
,
1955 VGPU10OpcodeToken0 opcode0
, unsigned nData
,
1958 begin_emit_instruction(emit
);
1959 emit_dword(emit
, opcode0
.value
);
1961 emit_dword(emit
, data
);
1962 end_emit_instruction(emit
);
1967 * Emit property instructions
1970 emit_property_instructions(struct svga_shader_emitter_v10
*emit
)
1972 VGPU10OpcodeToken0 opcode0
;
1974 assert(emit
->unit
== PIPE_SHADER_GEOMETRY
);
1976 /* emit input primitive type declaration */
1978 opcode0
.opcodeType
= VGPU10_OPCODE_DCL_GS_INPUT_PRIMITIVE
;
1979 opcode0
.primitive
= emit
->gs
.prim_type
;
1980 emit_property_instruction(emit
, opcode0
, 0, 0);
1982 /* emit output primitive topology declaration */
1984 opcode0
.opcodeType
= VGPU10_OPCODE_DCL_GS_OUTPUT_PRIMITIVE_TOPOLOGY
;
1985 opcode0
.primitiveTopology
= emit
->gs
.prim_topology
;
1986 emit_property_instruction(emit
, opcode0
, 0, 0);
1988 /* emit max output vertices */
1990 opcode0
.opcodeType
= VGPU10_OPCODE_DCL_MAX_OUTPUT_VERTEX_COUNT
;
1991 emit_property_instruction(emit
, opcode0
, 1, emit
->gs
.max_out_vertices
);
1996 * Emit a vgpu10 declaration "instruction".
1997 * \param index the register index
1998 * \param size array size of the operand. In most cases, it is 1,
1999 * but for inputs to geometry shader, the array size varies
2000 * depending on the primitive type.
2003 emit_decl_instruction(struct svga_shader_emitter_v10
*emit
,
2004 VGPU10OpcodeToken0 opcode0
,
2005 VGPU10OperandToken0 operand0
,
2006 VGPU10NameToken name_token
,
2007 unsigned index
, unsigned size
)
2009 assert(opcode0
.opcodeType
);
2010 assert(operand0
.mask
);
2012 begin_emit_instruction(emit
);
2013 emit_dword(emit
, opcode0
.value
);
2015 emit_dword(emit
, operand0
.value
);
2017 if (operand0
.indexDimension
== VGPU10_OPERAND_INDEX_1D
) {
2018 /* Next token is the index of the register to declare */
2019 emit_dword(emit
, index
);
2021 else if (operand0
.indexDimension
>= VGPU10_OPERAND_INDEX_2D
) {
2022 /* Next token is the size of the register */
2023 emit_dword(emit
, size
);
2025 /* Followed by the index of the register */
2026 emit_dword(emit
, index
);
2029 if (name_token
.value
) {
2030 emit_dword(emit
, name_token
.value
);
2033 end_emit_instruction(emit
);
2038 * Emit the declaration for a shader input.
2039 * \param opcodeType opcode type, one of VGPU10_OPCODE_DCL_INPUTx
2040 * \param operandType operand type, one of VGPU10_OPERAND_TYPE_INPUT_x
2041 * \param dim index dimension
2042 * \param index the input register index
2043 * \param size array size of the operand. In most cases, it is 1,
2044 * but for inputs to geometry shader, the array size varies
2045 * depending on the primitive type.
2046 * \param name one of VGPU10_NAME_x
2047 * \parma numComp number of components
2048 * \param selMode component selection mode
2049 * \param usageMask bitfield of VGPU10_OPERAND_4_COMPONENT_MASK_x values
2050 * \param interpMode interpolation mode
2053 emit_input_declaration(struct svga_shader_emitter_v10
*emit
,
2054 unsigned opcodeType
, unsigned operandType
,
2055 unsigned dim
, unsigned index
, unsigned size
,
2056 unsigned name
, unsigned numComp
,
2057 unsigned selMode
, unsigned usageMask
,
2058 unsigned interpMode
)
2060 VGPU10OpcodeToken0 opcode0
;
2061 VGPU10OperandToken0 operand0
;
2062 VGPU10NameToken name_token
;
2064 assert(usageMask
<= VGPU10_OPERAND_4_COMPONENT_MASK_ALL
);
2065 assert(opcodeType
== VGPU10_OPCODE_DCL_INPUT
||
2066 opcodeType
== VGPU10_OPCODE_DCL_INPUT_SIV
||
2067 opcodeType
== VGPU10_OPCODE_DCL_INPUT_PS
||
2068 opcodeType
== VGPU10_OPCODE_DCL_INPUT_PS_SGV
);
2069 assert(operandType
== VGPU10_OPERAND_TYPE_INPUT
||
2070 operandType
== VGPU10_OPERAND_TYPE_INPUT_PRIMITIVEID
);
2071 assert(numComp
<= VGPU10_OPERAND_4_COMPONENT
);
2072 assert(selMode
<= VGPU10_OPERAND_4_COMPONENT_MASK_MODE
);
2073 assert(dim
<= VGPU10_OPERAND_INDEX_3D
);
2074 assert(name
== VGPU10_NAME_UNDEFINED
||
2075 name
== VGPU10_NAME_POSITION
||
2076 name
== VGPU10_NAME_INSTANCE_ID
||
2077 name
== VGPU10_NAME_VERTEX_ID
||
2078 name
== VGPU10_NAME_PRIMITIVE_ID
||
2079 name
== VGPU10_NAME_IS_FRONT_FACE
);
2080 assert(interpMode
== VGPU10_INTERPOLATION_UNDEFINED
||
2081 interpMode
== VGPU10_INTERPOLATION_CONSTANT
||
2082 interpMode
== VGPU10_INTERPOLATION_LINEAR
||
2083 interpMode
== VGPU10_INTERPOLATION_LINEAR_CENTROID
||
2084 interpMode
== VGPU10_INTERPOLATION_LINEAR_NOPERSPECTIVE
||
2085 interpMode
== VGPU10_INTERPOLATION_LINEAR_NOPERSPECTIVE_CENTROID
);
2087 check_register_index(emit
, opcodeType
, index
);
2089 opcode0
.value
= operand0
.value
= name_token
.value
= 0;
2091 opcode0
.opcodeType
= opcodeType
;
2092 opcode0
.interpolationMode
= interpMode
;
2094 operand0
.operandType
= operandType
;
2095 operand0
.numComponents
= numComp
;
2096 operand0
.selectionMode
= selMode
;
2097 operand0
.mask
= usageMask
;
2098 operand0
.indexDimension
= dim
;
2099 operand0
.index0Representation
= VGPU10_OPERAND_INDEX_IMMEDIATE32
;
2100 if (dim
== VGPU10_OPERAND_INDEX_2D
)
2101 operand0
.index1Representation
= VGPU10_OPERAND_INDEX_IMMEDIATE32
;
2103 name_token
.name
= name
;
2105 emit_decl_instruction(emit
, opcode0
, operand0
, name_token
, index
, size
);
2110 * Emit the declaration for a shader output.
2111 * \param type one of VGPU10_OPCODE_DCL_OUTPUTx
2112 * \param index the output register index
2113 * \param name one of VGPU10_NAME_x
2114 * \param usageMask bitfield of VGPU10_OPERAND_4_COMPONENT_MASK_x values
2117 emit_output_declaration(struct svga_shader_emitter_v10
*emit
,
2118 unsigned type
, unsigned index
,
2119 unsigned name
, unsigned usageMask
)
2121 VGPU10OpcodeToken0 opcode0
;
2122 VGPU10OperandToken0 operand0
;
2123 VGPU10NameToken name_token
;
2125 assert(usageMask
<= VGPU10_OPERAND_4_COMPONENT_MASK_ALL
);
2126 assert(type
== VGPU10_OPCODE_DCL_OUTPUT
||
2127 type
== VGPU10_OPCODE_DCL_OUTPUT_SGV
||
2128 type
== VGPU10_OPCODE_DCL_OUTPUT_SIV
);
2129 assert(name
== VGPU10_NAME_UNDEFINED
||
2130 name
== VGPU10_NAME_POSITION
||
2131 name
== VGPU10_NAME_PRIMITIVE_ID
||
2132 name
== VGPU10_NAME_RENDER_TARGET_ARRAY_INDEX
||
2133 name
== VGPU10_NAME_CLIP_DISTANCE
);
2135 check_register_index(emit
, type
, index
);
2137 opcode0
.value
= operand0
.value
= name_token
.value
= 0;
2139 opcode0
.opcodeType
= type
;
2140 operand0
.operandType
= VGPU10_OPERAND_TYPE_OUTPUT
;
2141 operand0
.numComponents
= VGPU10_OPERAND_4_COMPONENT
;
2142 operand0
.selectionMode
= VGPU10_OPERAND_4_COMPONENT_MASK_MODE
;
2143 operand0
.mask
= usageMask
;
2144 operand0
.indexDimension
= VGPU10_OPERAND_INDEX_1D
;
2145 operand0
.index0Representation
= VGPU10_OPERAND_INDEX_IMMEDIATE32
;
2147 name_token
.name
= name
;
2149 emit_decl_instruction(emit
, opcode0
, operand0
, name_token
, index
, 1);
2154 * Emit the declaration for the fragment depth output.
2157 emit_fragdepth_output_declaration(struct svga_shader_emitter_v10
*emit
)
2159 VGPU10OpcodeToken0 opcode0
;
2160 VGPU10OperandToken0 operand0
;
2161 VGPU10NameToken name_token
;
2163 assert(emit
->unit
== PIPE_SHADER_FRAGMENT
);
2165 opcode0
.value
= operand0
.value
= name_token
.value
= 0;
2167 opcode0
.opcodeType
= VGPU10_OPCODE_DCL_OUTPUT
;
2168 operand0
.operandType
= VGPU10_OPERAND_TYPE_OUTPUT_DEPTH
;
2169 operand0
.numComponents
= VGPU10_OPERAND_1_COMPONENT
;
2170 operand0
.indexDimension
= VGPU10_OPERAND_INDEX_0D
;
2171 operand0
.mask
= VGPU10_OPERAND_4_COMPONENT_MASK_ALL
;
2173 emit_decl_instruction(emit
, opcode0
, operand0
, name_token
, 0, 1);
2178 * Emit the declaration for a system value input/output.
2181 emit_system_value_declaration(struct svga_shader_emitter_v10
*emit
,
2182 enum tgsi_semantic semantic_name
, unsigned index
)
2184 switch (semantic_name
) {
2185 case TGSI_SEMANTIC_INSTANCEID
:
2186 index
= alloc_system_value_index(emit
, index
);
2187 emit_input_declaration(emit
, VGPU10_OPCODE_DCL_INPUT_SIV
,
2188 VGPU10_OPERAND_TYPE_INPUT
,
2189 VGPU10_OPERAND_INDEX_1D
,
2191 VGPU10_NAME_INSTANCE_ID
,
2192 VGPU10_OPERAND_4_COMPONENT
,
2193 VGPU10_OPERAND_4_COMPONENT_MASK_MODE
,
2194 VGPU10_OPERAND_4_COMPONENT_MASK_X
,
2195 VGPU10_INTERPOLATION_UNDEFINED
);
2197 case TGSI_SEMANTIC_VERTEXID
:
2198 index
= alloc_system_value_index(emit
, index
);
2199 emit_input_declaration(emit
, VGPU10_OPCODE_DCL_INPUT_SIV
,
2200 VGPU10_OPERAND_TYPE_INPUT
,
2201 VGPU10_OPERAND_INDEX_1D
,
2203 VGPU10_NAME_VERTEX_ID
,
2204 VGPU10_OPERAND_4_COMPONENT
,
2205 VGPU10_OPERAND_4_COMPONENT_MASK_MODE
,
2206 VGPU10_OPERAND_4_COMPONENT_MASK_X
,
2207 VGPU10_INTERPOLATION_UNDEFINED
);
2215 * Translate a TGSI declaration to VGPU10.
2218 emit_vgpu10_declaration(struct svga_shader_emitter_v10
*emit
,
2219 const struct tgsi_full_declaration
*decl
)
2221 switch (decl
->Declaration
.File
) {
2222 case TGSI_FILE_INPUT
:
2223 /* do nothing - see emit_input_declarations() */
2226 case TGSI_FILE_OUTPUT
:
2227 assert(decl
->Range
.First
== decl
->Range
.Last
);
2228 emit
->output_usage_mask
[decl
->Range
.First
] = decl
->Declaration
.UsageMask
;
2231 case TGSI_FILE_TEMPORARY
:
2232 /* Don't declare the temps here. Just keep track of how many
2233 * and emit the declaration later.
2235 if (decl
->Declaration
.Array
) {
2236 /* Indexed temporary array. Save the start index of the array
2237 * and the size of the array.
2239 const unsigned arrayID
= MIN2(decl
->Array
.ArrayID
, MAX_TEMP_ARRAYS
);
2242 assert(arrayID
< ARRAY_SIZE(emit
->temp_arrays
));
2244 /* Save this array so we can emit the declaration for it later */
2245 emit
->temp_arrays
[arrayID
].start
= decl
->Range
.First
;
2246 emit
->temp_arrays
[arrayID
].size
=
2247 decl
->Range
.Last
- decl
->Range
.First
+ 1;
2249 emit
->num_temp_arrays
= MAX2(emit
->num_temp_arrays
, arrayID
+ 1);
2250 assert(emit
->num_temp_arrays
<= MAX_TEMP_ARRAYS
);
2251 emit
->num_temp_arrays
= MIN2(emit
->num_temp_arrays
, MAX_TEMP_ARRAYS
);
2253 /* Fill in the temp_map entries for this array */
2254 for (i
= decl
->Range
.First
; i
<= decl
->Range
.Last
; i
++) {
2255 emit
->temp_map
[i
].arrayId
= arrayID
;
2256 emit
->temp_map
[i
].index
= i
- decl
->Range
.First
;
2260 /* for all temps, indexed or not, keep track of highest index */
2261 emit
->num_shader_temps
= MAX2(emit
->num_shader_temps
,
2262 decl
->Range
.Last
+ 1);
2265 case TGSI_FILE_CONSTANT
:
2266 /* Don't declare constants here. Just keep track and emit later. */
2268 unsigned constbuf
= 0, num_consts
;
2269 if (decl
->Declaration
.Dimension
) {
2270 constbuf
= decl
->Dim
.Index2D
;
2272 /* We throw an assertion here when, in fact, the shader should never
2273 * have linked due to constbuf index out of bounds, so we shouldn't
2274 * have reached here.
2276 assert(constbuf
< ARRAY_SIZE(emit
->num_shader_consts
));
2278 num_consts
= MAX2(emit
->num_shader_consts
[constbuf
],
2279 decl
->Range
.Last
+ 1);
2281 if (num_consts
> VGPU10_MAX_CONSTANT_BUFFER_ELEMENT_COUNT
) {
2282 debug_printf("Warning: constant buffer is declared to size [%u]"
2283 " but [%u] is the limit.\n",
2285 VGPU10_MAX_CONSTANT_BUFFER_ELEMENT_COUNT
);
2287 /* The linker doesn't enforce the max UBO size so we clamp here */
2288 emit
->num_shader_consts
[constbuf
] =
2289 MIN2(num_consts
, VGPU10_MAX_CONSTANT_BUFFER_ELEMENT_COUNT
);
2293 case TGSI_FILE_IMMEDIATE
:
2294 assert(!"TGSI_FILE_IMMEDIATE not handled yet!");
2297 case TGSI_FILE_SYSTEM_VALUE
:
2298 emit_system_value_declaration(emit
, decl
->Semantic
.Name
,
2302 case TGSI_FILE_SAMPLER
:
2303 /* Don't declare samplers here. Just keep track and emit later. */
2304 emit
->num_samplers
= MAX2(emit
->num_samplers
, decl
->Range
.Last
+ 1);
2308 case TGSI_FILE_RESOURCE
:
2309 /*opcode0.opcodeType = VGPU10_OPCODE_DCL_RESOURCE;*/
2310 /* XXX more, VGPU10_RETURN_TYPE_FLOAT */
2311 assert(!"TGSI_FILE_RESOURCE not handled yet");
2315 case TGSI_FILE_ADDRESS
:
2316 emit
->num_address_regs
= MAX2(emit
->num_address_regs
,
2317 decl
->Range
.Last
+ 1);
2320 case TGSI_FILE_SAMPLER_VIEW
:
2322 unsigned unit
= decl
->Range
.First
;
2323 assert(decl
->Range
.First
== decl
->Range
.Last
);
2324 emit
->sampler_target
[unit
] = decl
->SamplerView
.Resource
;
2325 /* Note: we can ignore YZW return types for now */
2326 emit
->sampler_return_type
[unit
] = decl
->SamplerView
.ReturnTypeX
;
2331 assert(!"Unexpected type of declaration");
2339 * Emit all input declarations.
2342 emit_input_declarations(struct svga_shader_emitter_v10
*emit
)
2346 if (emit
->unit
== PIPE_SHADER_FRAGMENT
) {
2348 for (i
= 0; i
< emit
->linkage
.num_inputs
; i
++) {
2349 enum tgsi_semantic semantic_name
= emit
->info
.input_semantic_name
[i
];
2350 unsigned usage_mask
= emit
->info
.input_usage_mask
[i
];
2351 unsigned index
= emit
->linkage
.input_map
[i
];
2352 unsigned type
, interpolationMode
, name
;
2354 if (usage_mask
== 0)
2355 continue; /* register is not actually used */
2357 if (semantic_name
== TGSI_SEMANTIC_POSITION
) {
2358 /* fragment position input */
2359 type
= VGPU10_OPCODE_DCL_INPUT_PS_SGV
;
2360 interpolationMode
= VGPU10_INTERPOLATION_LINEAR
;
2361 name
= VGPU10_NAME_POSITION
;
2362 if (usage_mask
& TGSI_WRITEMASK_W
) {
2363 /* we need to replace use of 'w' with '1/w' */
2364 emit
->fs
.fragcoord_input_index
= i
;
2367 else if (semantic_name
== TGSI_SEMANTIC_FACE
) {
2368 /* fragment front-facing input */
2369 type
= VGPU10_OPCODE_DCL_INPUT_PS_SGV
;
2370 interpolationMode
= VGPU10_INTERPOLATION_CONSTANT
;
2371 name
= VGPU10_NAME_IS_FRONT_FACE
;
2372 emit
->fs
.face_input_index
= i
;
2374 else if (semantic_name
== TGSI_SEMANTIC_PRIMID
) {
2376 type
= VGPU10_OPCODE_DCL_INPUT_PS_SGV
;
2377 interpolationMode
= VGPU10_INTERPOLATION_CONSTANT
;
2378 name
= VGPU10_NAME_PRIMITIVE_ID
;
2381 /* general fragment input */
2382 type
= VGPU10_OPCODE_DCL_INPUT_PS
;
2384 translate_interpolation(emit
,
2385 emit
->info
.input_interpolate
[i
],
2386 emit
->info
.input_interpolate_loc
[i
]);
2388 /* keeps track if flat interpolation mode is being used */
2389 emit
->uses_flat_interp
= emit
->uses_flat_interp
||
2390 (interpolationMode
== VGPU10_INTERPOLATION_CONSTANT
);
2392 name
= VGPU10_NAME_UNDEFINED
;
2395 emit_input_declaration(emit
, type
,
2396 VGPU10_OPERAND_TYPE_INPUT
,
2397 VGPU10_OPERAND_INDEX_1D
, index
, 1,
2399 VGPU10_OPERAND_4_COMPONENT
,
2400 VGPU10_OPERAND_4_COMPONENT_MASK_MODE
,
2401 VGPU10_OPERAND_4_COMPONENT_MASK_ALL
,
2405 else if (emit
->unit
== PIPE_SHADER_GEOMETRY
) {
2407 for (i
= 0; i
< emit
->info
.num_inputs
; i
++) {
2408 enum tgsi_semantic semantic_name
= emit
->info
.input_semantic_name
[i
];
2409 unsigned usage_mask
= emit
->info
.input_usage_mask
[i
];
2410 unsigned index
= emit
->linkage
.input_map
[i
];
2411 unsigned opcodeType
, operandType
;
2412 unsigned numComp
, selMode
;
2416 if (usage_mask
== 0)
2417 continue; /* register is not actually used */
2419 opcodeType
= VGPU10_OPCODE_DCL_INPUT
;
2420 operandType
= VGPU10_OPERAND_TYPE_INPUT
;
2421 numComp
= VGPU10_OPERAND_4_COMPONENT
;
2422 selMode
= VGPU10_OPERAND_4_COMPONENT_MASK_MODE
;
2423 name
= VGPU10_NAME_UNDEFINED
;
2425 /* all geometry shader inputs are two dimensional except gl_PrimitiveID */
2426 dim
= VGPU10_OPERAND_INDEX_2D
;
2428 if (semantic_name
== TGSI_SEMANTIC_PRIMID
) {
2430 operandType
= VGPU10_OPERAND_TYPE_INPUT_PRIMITIVEID
;
2431 dim
= VGPU10_OPERAND_INDEX_0D
;
2432 numComp
= VGPU10_OPERAND_0_COMPONENT
;
2435 /* also save the register index so we can check for
2436 * primitive id when emit src register. We need to modify the
2437 * operand type, index dimension when emit primitive id src reg.
2439 emit
->gs
.prim_id_index
= i
;
2441 else if (semantic_name
== TGSI_SEMANTIC_POSITION
) {
2442 /* vertex position input */
2443 opcodeType
= VGPU10_OPCODE_DCL_INPUT_SIV
;
2444 name
= VGPU10_NAME_POSITION
;
2447 emit_input_declaration(emit
, opcodeType
, operandType
,
2449 emit
->gs
.input_size
,
2452 VGPU10_OPERAND_4_COMPONENT_MASK_ALL
,
2453 VGPU10_INTERPOLATION_UNDEFINED
);
2457 assert(emit
->unit
== PIPE_SHADER_VERTEX
);
2459 for (i
= 0; i
< emit
->info
.file_max
[TGSI_FILE_INPUT
] + 1; i
++) {
2460 unsigned usage_mask
= emit
->info
.input_usage_mask
[i
];
2463 if (usage_mask
== 0)
2464 continue; /* register is not actually used */
2466 emit_input_declaration(emit
, VGPU10_OPCODE_DCL_INPUT
,
2467 VGPU10_OPERAND_TYPE_INPUT
,
2468 VGPU10_OPERAND_INDEX_1D
, index
, 1,
2469 VGPU10_NAME_UNDEFINED
,
2470 VGPU10_OPERAND_4_COMPONENT
,
2471 VGPU10_OPERAND_4_COMPONENT_MASK_MODE
,
2472 VGPU10_OPERAND_4_COMPONENT_MASK_ALL
,
2473 VGPU10_INTERPOLATION_UNDEFINED
);
2482 * Emit all output declarations.
2485 emit_output_declarations(struct svga_shader_emitter_v10
*emit
)
2489 for (i
= 0; i
< emit
->info
.num_outputs
; i
++) {
2490 /*const unsigned usage_mask = emit->info.output_usage_mask[i];*/
2491 const enum tgsi_semantic semantic_name
=
2492 emit
->info
.output_semantic_name
[i
];
2493 const unsigned semantic_index
= emit
->info
.output_semantic_index
[i
];
2496 if (emit
->unit
== PIPE_SHADER_FRAGMENT
) {
2497 if (semantic_name
== TGSI_SEMANTIC_COLOR
) {
2498 assert(semantic_index
< ARRAY_SIZE(emit
->fs
.color_out_index
));
2500 emit
->fs
.color_out_index
[semantic_index
] = index
;
2502 /* The semantic index is the shader's color output/buffer index */
2503 emit_output_declaration(emit
,
2504 VGPU10_OPCODE_DCL_OUTPUT
, semantic_index
,
2505 VGPU10_NAME_UNDEFINED
,
2506 VGPU10_OPERAND_4_COMPONENT_MASK_ALL
);
2508 if (semantic_index
== 0) {
2509 if (emit
->key
.fs
.write_color0_to_n_cbufs
> 1) {
2510 /* Emit declarations for the additional color outputs
2514 for (j
= 1; j
< emit
->key
.fs
.write_color0_to_n_cbufs
; j
++) {
2515 /* Allocate a new output index */
2516 unsigned idx
= emit
->info
.num_outputs
+ j
- 1;
2517 emit
->fs
.color_out_index
[j
] = idx
;
2518 emit_output_declaration(emit
,
2519 VGPU10_OPCODE_DCL_OUTPUT
, idx
,
2520 VGPU10_NAME_UNDEFINED
,
2521 VGPU10_OPERAND_4_COMPONENT_MASK_ALL
);
2522 emit
->info
.output_semantic_index
[idx
] = j
;
2527 assert(!emit
->key
.fs
.write_color0_to_n_cbufs
);
2530 else if (semantic_name
== TGSI_SEMANTIC_POSITION
) {
2531 /* Fragment depth output */
2532 emit_fragdepth_output_declaration(emit
);
2535 assert(!"Bad output semantic name");
2540 unsigned name
, type
;
2541 unsigned writemask
= VGPU10_OPERAND_4_COMPONENT_MASK_ALL
;
2543 switch (semantic_name
) {
2544 case TGSI_SEMANTIC_POSITION
:
2545 assert(emit
->unit
!= PIPE_SHADER_FRAGMENT
);
2546 type
= VGPU10_OPCODE_DCL_OUTPUT_SIV
;
2547 name
= VGPU10_NAME_POSITION
;
2548 /* Save the index of the vertex position output register */
2549 emit
->vposition
.out_index
= index
;
2551 case TGSI_SEMANTIC_CLIPDIST
:
2552 type
= VGPU10_OPCODE_DCL_OUTPUT_SIV
;
2553 name
= VGPU10_NAME_CLIP_DISTANCE
;
2554 /* save the starting index of the clip distance output register */
2555 if (semantic_index
== 0)
2556 emit
->clip_dist_out_index
= index
;
2557 writemask
= emit
->output_usage_mask
[index
];
2558 writemask
= apply_clip_plane_mask(emit
, writemask
, semantic_index
);
2559 if (writemask
== 0x0) {
2560 continue; /* discard this do-nothing declaration */
2563 case TGSI_SEMANTIC_PRIMID
:
2564 assert(emit
->unit
== PIPE_SHADER_GEOMETRY
);
2565 type
= VGPU10_OPCODE_DCL_OUTPUT_SGV
;
2566 name
= VGPU10_NAME_PRIMITIVE_ID
;
2568 case TGSI_SEMANTIC_LAYER
:
2569 assert(emit
->unit
== PIPE_SHADER_GEOMETRY
);
2570 type
= VGPU10_OPCODE_DCL_OUTPUT_SGV
;
2571 name
= VGPU10_NAME_RENDER_TARGET_ARRAY_INDEX
;
2573 case TGSI_SEMANTIC_CLIPVERTEX
:
2574 type
= VGPU10_OPCODE_DCL_OUTPUT
;
2575 name
= VGPU10_NAME_UNDEFINED
;
2576 emit
->clip_vertex_out_index
= index
;
2579 /* generic output */
2580 type
= VGPU10_OPCODE_DCL_OUTPUT
;
2581 name
= VGPU10_NAME_UNDEFINED
;
2584 emit_output_declaration(emit
, type
, index
, name
, writemask
);
2588 if (emit
->vposition
.so_index
!= INVALID_INDEX
&&
2589 emit
->vposition
.out_index
!= INVALID_INDEX
) {
2591 assert(emit
->unit
!= PIPE_SHADER_FRAGMENT
);
2593 /* Emit the declaration for the non-adjusted vertex position
2594 * for stream output purpose
2596 emit_output_declaration(emit
, VGPU10_OPCODE_DCL_OUTPUT
,
2597 emit
->vposition
.so_index
,
2598 VGPU10_NAME_UNDEFINED
,
2599 VGPU10_OPERAND_4_COMPONENT_MASK_ALL
);
2602 if (emit
->clip_dist_so_index
!= INVALID_INDEX
&&
2603 emit
->clip_dist_out_index
!= INVALID_INDEX
) {
2605 assert(emit
->unit
!= PIPE_SHADER_FRAGMENT
);
2607 /* Emit the declaration for the clip distance shadow copy which
2608 * will be used for stream output purpose and for clip distance
2611 emit_output_declaration(emit
, VGPU10_OPCODE_DCL_OUTPUT
,
2612 emit
->clip_dist_so_index
,
2613 VGPU10_NAME_UNDEFINED
,
2614 emit
->output_usage_mask
[emit
->clip_dist_out_index
]);
2616 if (emit
->info
.num_written_clipdistance
> 4) {
2617 /* for the second clip distance register, each handles 4 planes */
2618 emit_output_declaration(emit
, VGPU10_OPCODE_DCL_OUTPUT
,
2619 emit
->clip_dist_so_index
+ 1,
2620 VGPU10_NAME_UNDEFINED
,
2621 emit
->output_usage_mask
[emit
->clip_dist_out_index
+1]);
2630 * Emit the declaration for the temporary registers.
2633 emit_temporaries_declaration(struct svga_shader_emitter_v10
*emit
)
2635 unsigned total_temps
, reg
, i
;
2637 total_temps
= emit
->num_shader_temps
;
2639 /* If there is indirect access to non-indexable temps in the shader,
2640 * convert those temps to indexable temps. This works around a bug
2641 * in the GLSL->TGSI translator exposed in piglit test
2642 * glsl-1.20/execution/fs-const-array-of-struct-of-array.shader_test.
2643 * Internal temps added by the driver remain as non-indexable temps.
2645 if ((emit
->info
.indirect_files
& (1 << TGSI_FILE_TEMPORARY
)) &&
2646 emit
->num_temp_arrays
== 0) {
2650 emit
->num_temp_arrays
= arrayID
+ 1;
2651 emit
->temp_arrays
[arrayID
].start
= 0;
2652 emit
->temp_arrays
[arrayID
].size
= total_temps
;
2654 /* Fill in the temp_map entries for this temp array */
2655 for (i
= 0; i
< total_temps
; i
++) {
2656 emit
->temp_map
[i
].arrayId
= arrayID
;
2657 emit
->temp_map
[i
].index
= i
;
2661 /* Allocate extra temps for specially-implemented instructions,
2664 total_temps
+= MAX_INTERNAL_TEMPS
;
2666 if (emit
->unit
== PIPE_SHADER_VERTEX
|| emit
->unit
== PIPE_SHADER_GEOMETRY
) {
2667 if (emit
->vposition
.need_prescale
|| emit
->key
.vs
.undo_viewport
||
2668 emit
->key
.clip_plane_enable
||
2669 emit
->vposition
.so_index
!= INVALID_INDEX
) {
2670 emit
->vposition
.tmp_index
= total_temps
;
2674 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
2675 unsigned attrib_mask
= (emit
->key
.vs
.adjust_attrib_w_1
|
2676 emit
->key
.vs
.adjust_attrib_itof
|
2677 emit
->key
.vs
.adjust_attrib_utof
|
2678 emit
->key
.vs
.attrib_is_bgra
|
2679 emit
->key
.vs
.attrib_puint_to_snorm
|
2680 emit
->key
.vs
.attrib_puint_to_uscaled
|
2681 emit
->key
.vs
.attrib_puint_to_sscaled
);
2682 while (attrib_mask
) {
2683 unsigned index
= u_bit_scan(&attrib_mask
);
2684 emit
->vs
.adjusted_input
[index
] = total_temps
++;
2688 if (emit
->clip_mode
== CLIP_DISTANCE
) {
2689 /* We need to write the clip distance to a temporary register
2690 * first. Then it will be copied to the shadow copy for
2691 * the clip distance varying variable and stream output purpose.
2692 * It will also be copied to the actual CLIPDIST register
2693 * according to the enabled clip planes
2695 emit
->clip_dist_tmp_index
= total_temps
++;
2696 if (emit
->info
.num_written_clipdistance
> 4)
2697 total_temps
++; /* second clip register */
2699 else if (emit
->clip_mode
== CLIP_VERTEX
) {
2700 /* We need to convert the TGSI CLIPVERTEX output to one or more
2701 * clip distances. Allocate a temp reg for the clipvertex here.
2703 assert(emit
->info
.writes_clipvertex
> 0);
2704 emit
->clip_vertex_tmp_index
= total_temps
;
2708 else if (emit
->unit
== PIPE_SHADER_FRAGMENT
) {
2709 if (emit
->key
.fs
.alpha_func
!= SVGA3D_CMP_ALWAYS
||
2710 emit
->key
.fs
.white_fragments
||
2711 emit
->key
.fs
.write_color0_to_n_cbufs
> 1) {
2712 /* Allocate a temp to hold the output color */
2713 emit
->fs
.color_tmp_index
= total_temps
;
2717 if (emit
->fs
.face_input_index
!= INVALID_INDEX
) {
2718 /* Allocate a temp for the +/-1 face register */
2719 emit
->fs
.face_tmp_index
= total_temps
;
2723 if (emit
->fs
.fragcoord_input_index
!= INVALID_INDEX
) {
2724 /* Allocate a temp for modified fragment position register */
2725 emit
->fs
.fragcoord_tmp_index
= total_temps
;
2730 for (i
= 0; i
< emit
->num_address_regs
; i
++) {
2731 emit
->address_reg_index
[i
] = total_temps
++;
2734 /* Initialize the temp_map array which maps TGSI temp indexes to VGPU10
2735 * temp indexes. Basically, we compact all the non-array temp register
2736 * indexes into a consecutive series.
2738 * Before, we may have some TGSI declarations like:
2739 * DCL TEMP[0..1], LOCAL
2740 * DCL TEMP[2..4], ARRAY(1), LOCAL
2741 * DCL TEMP[5..7], ARRAY(2), LOCAL
2742 * plus, some extra temps, like TEMP[8], TEMP[9] for misc things
2744 * After, we'll have a map like this:
2745 * temp_map[0] = { array 0, index 0 }
2746 * temp_map[1] = { array 0, index 1 }
2747 * temp_map[2] = { array 1, index 0 }
2748 * temp_map[3] = { array 1, index 1 }
2749 * temp_map[4] = { array 1, index 2 }
2750 * temp_map[5] = { array 2, index 0 }
2751 * temp_map[6] = { array 2, index 1 }
2752 * temp_map[7] = { array 2, index 2 }
2753 * temp_map[8] = { array 0, index 2 }
2754 * temp_map[9] = { array 0, index 3 }
2756 * We'll declare two arrays of 3 elements, plus a set of four non-indexed
2757 * temps numbered 0..3
2759 * Any time we emit a temporary register index, we'll have to use the
2760 * temp_map[] table to convert the TGSI index to the VGPU10 index.
2762 * Finally, we recompute the total_temps value here.
2765 for (i
= 0; i
< total_temps
; i
++) {
2766 if (emit
->temp_map
[i
].arrayId
== 0) {
2767 emit
->temp_map
[i
].index
= reg
++;
2772 debug_printf("total_temps %u\n", total_temps
);
2773 for (i
= 0; i
< total_temps
; i
++) {
2774 debug_printf("temp %u -> array %u index %u\n",
2775 i
, emit
->temp_map
[i
].arrayId
, emit
->temp_map
[i
].index
);
2781 /* Emit declaration of ordinary temp registers */
2782 if (total_temps
> 0) {
2783 VGPU10OpcodeToken0 opcode0
;
2786 opcode0
.opcodeType
= VGPU10_OPCODE_DCL_TEMPS
;
2788 begin_emit_instruction(emit
);
2789 emit_dword(emit
, opcode0
.value
);
2790 emit_dword(emit
, total_temps
);
2791 end_emit_instruction(emit
);
2794 /* Emit declarations for indexable temp arrays. Skip 0th entry since
2797 for (i
= 1; i
< emit
->num_temp_arrays
; i
++) {
2798 unsigned num_temps
= emit
->temp_arrays
[i
].size
;
2800 if (num_temps
> 0) {
2801 VGPU10OpcodeToken0 opcode0
;
2804 opcode0
.opcodeType
= VGPU10_OPCODE_DCL_INDEXABLE_TEMP
;
2806 begin_emit_instruction(emit
);
2807 emit_dword(emit
, opcode0
.value
);
2808 emit_dword(emit
, i
); /* which array */
2809 emit_dword(emit
, num_temps
);
2810 emit_dword(emit
, 4); /* num components */
2811 end_emit_instruction(emit
);
2813 total_temps
+= num_temps
;
2817 /* Check that the grand total of all regular and indexed temps is
2820 check_register_index(emit
, VGPU10_OPCODE_DCL_TEMPS
, total_temps
- 1);
2827 emit_constant_declaration(struct svga_shader_emitter_v10
*emit
)
2829 VGPU10OpcodeToken0 opcode0
;
2830 VGPU10OperandToken0 operand0
;
2831 unsigned total_consts
, i
;
2834 opcode0
.opcodeType
= VGPU10_OPCODE_DCL_CONSTANT_BUFFER
;
2835 opcode0
.accessPattern
= VGPU10_CB_IMMEDIATE_INDEXED
;
2836 /* XXX or, access pattern = VGPU10_CB_DYNAMIC_INDEXED */
2839 operand0
.numComponents
= VGPU10_OPERAND_4_COMPONENT
;
2840 operand0
.indexDimension
= VGPU10_OPERAND_INDEX_2D
;
2841 operand0
.index0Representation
= VGPU10_OPERAND_INDEX_IMMEDIATE32
;
2842 operand0
.index1Representation
= VGPU10_OPERAND_INDEX_IMMEDIATE32
;
2843 operand0
.operandType
= VGPU10_OPERAND_TYPE_CONSTANT_BUFFER
;
2844 operand0
.selectionMode
= VGPU10_OPERAND_4_COMPONENT_SWIZZLE_MODE
;
2845 operand0
.swizzleX
= 0;
2846 operand0
.swizzleY
= 1;
2847 operand0
.swizzleZ
= 2;
2848 operand0
.swizzleW
= 3;
2851 * Emit declaration for constant buffer [0]. We also allocate
2852 * room for the extra constants here.
2854 total_consts
= emit
->num_shader_consts
[0];
2856 /* Now, allocate constant slots for the "extra" constants */
2858 /* Vertex position scale/translation */
2859 if (emit
->vposition
.need_prescale
) {
2860 emit
->vposition
.prescale_scale_index
= total_consts
++;
2861 emit
->vposition
.prescale_trans_index
= total_consts
++;
2864 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
2865 if (emit
->key
.vs
.undo_viewport
) {
2866 emit
->vs
.viewport_index
= total_consts
++;
2870 /* user-defined clip planes */
2871 if (emit
->key
.clip_plane_enable
) {
2872 unsigned n
= util_bitcount(emit
->key
.clip_plane_enable
);
2873 assert(emit
->unit
== PIPE_SHADER_VERTEX
||
2874 emit
->unit
== PIPE_SHADER_GEOMETRY
);
2875 for (i
= 0; i
< n
; i
++) {
2876 emit
->clip_plane_const
[i
] = total_consts
++;
2880 /* Texcoord scale factors for RECT textures */
2882 for (i
= 0; i
< emit
->num_samplers
; i
++) {
2883 if (emit
->key
.tex
[i
].unnormalized
) {
2884 emit
->texcoord_scale_index
[i
] = total_consts
++;
2889 /* Texture buffer sizes */
2890 for (i
= 0; i
< emit
->num_samplers
; i
++) {
2891 if (emit
->sampler_target
[i
] == TGSI_TEXTURE_BUFFER
) {
2892 emit
->texture_buffer_size_index
[i
] = total_consts
++;
2896 if (total_consts
> 0) {
2897 begin_emit_instruction(emit
);
2898 emit_dword(emit
, opcode0
.value
);
2899 emit_dword(emit
, operand0
.value
);
2900 emit_dword(emit
, 0); /* which const buffer slot */
2901 emit_dword(emit
, total_consts
);
2902 end_emit_instruction(emit
);
2905 /* Declare remaining constant buffers (UBOs) */
2906 for (i
= 1; i
< ARRAY_SIZE(emit
->num_shader_consts
); i
++) {
2907 if (emit
->num_shader_consts
[i
] > 0) {
2908 begin_emit_instruction(emit
);
2909 emit_dword(emit
, opcode0
.value
);
2910 emit_dword(emit
, operand0
.value
);
2911 emit_dword(emit
, i
); /* which const buffer slot */
2912 emit_dword(emit
, emit
->num_shader_consts
[i
]);
2913 end_emit_instruction(emit
);
2922 * Emit declarations for samplers.
2925 emit_sampler_declarations(struct svga_shader_emitter_v10
*emit
)
2929 for (i
= 0; i
< emit
->num_samplers
; i
++) {
2930 VGPU10OpcodeToken0 opcode0
;
2931 VGPU10OperandToken0 operand0
;
2934 opcode0
.opcodeType
= VGPU10_OPCODE_DCL_SAMPLER
;
2935 opcode0
.samplerMode
= VGPU10_SAMPLER_MODE_DEFAULT
;
2938 operand0
.numComponents
= VGPU10_OPERAND_0_COMPONENT
;
2939 operand0
.operandType
= VGPU10_OPERAND_TYPE_SAMPLER
;
2940 operand0
.indexDimension
= VGPU10_OPERAND_INDEX_1D
;
2941 operand0
.index0Representation
= VGPU10_OPERAND_INDEX_IMMEDIATE32
;
2943 begin_emit_instruction(emit
);
2944 emit_dword(emit
, opcode0
.value
);
2945 emit_dword(emit
, operand0
.value
);
2946 emit_dword(emit
, i
);
2947 end_emit_instruction(emit
);
2955 * Translate TGSI_TEXTURE_x to VGAPU10_RESOURCE_DIMENSION_x.
2958 tgsi_texture_to_resource_dimension(enum tgsi_texture_type target
,
2962 case TGSI_TEXTURE_BUFFER
:
2963 return VGPU10_RESOURCE_DIMENSION_BUFFER
;
2964 case TGSI_TEXTURE_1D
:
2965 return VGPU10_RESOURCE_DIMENSION_TEXTURE1D
;
2966 case TGSI_TEXTURE_2D
:
2967 case TGSI_TEXTURE_RECT
:
2968 return VGPU10_RESOURCE_DIMENSION_TEXTURE2D
;
2969 case TGSI_TEXTURE_3D
:
2970 return VGPU10_RESOURCE_DIMENSION_TEXTURE3D
;
2971 case TGSI_TEXTURE_CUBE
:
2972 return VGPU10_RESOURCE_DIMENSION_TEXTURECUBE
;
2973 case TGSI_TEXTURE_SHADOW1D
:
2974 return VGPU10_RESOURCE_DIMENSION_TEXTURE1D
;
2975 case TGSI_TEXTURE_SHADOW2D
:
2976 case TGSI_TEXTURE_SHADOWRECT
:
2977 return VGPU10_RESOURCE_DIMENSION_TEXTURE2D
;
2978 case TGSI_TEXTURE_1D_ARRAY
:
2979 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
2980 return is_array
? VGPU10_RESOURCE_DIMENSION_TEXTURE1DARRAY
2981 : VGPU10_RESOURCE_DIMENSION_TEXTURE1D
;
2982 case TGSI_TEXTURE_2D_ARRAY
:
2983 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
2984 return is_array
? VGPU10_RESOURCE_DIMENSION_TEXTURE2DARRAY
2985 : VGPU10_RESOURCE_DIMENSION_TEXTURE2D
;
2986 case TGSI_TEXTURE_SHADOWCUBE
:
2987 return VGPU10_RESOURCE_DIMENSION_TEXTURECUBE
;
2988 case TGSI_TEXTURE_2D_MSAA
:
2989 return VGPU10_RESOURCE_DIMENSION_TEXTURE2DMS
;
2990 case TGSI_TEXTURE_2D_ARRAY_MSAA
:
2991 return is_array
? VGPU10_RESOURCE_DIMENSION_TEXTURE2DMSARRAY
2992 : VGPU10_RESOURCE_DIMENSION_TEXTURE2DMS
;
2993 case TGSI_TEXTURE_CUBE_ARRAY
:
2994 return VGPU10_RESOURCE_DIMENSION_TEXTURECUBEARRAY
;
2996 assert(!"Unexpected resource type");
2997 return VGPU10_RESOURCE_DIMENSION_TEXTURE2D
;
3003 * Given a tgsi_return_type, return true iff it is an integer type.
3006 is_integer_type(enum tgsi_return_type type
)
3009 case TGSI_RETURN_TYPE_SINT
:
3010 case TGSI_RETURN_TYPE_UINT
:
3012 case TGSI_RETURN_TYPE_FLOAT
:
3013 case TGSI_RETURN_TYPE_UNORM
:
3014 case TGSI_RETURN_TYPE_SNORM
:
3016 case TGSI_RETURN_TYPE_COUNT
:
3018 assert(!"is_integer_type: Unknown tgsi_return_type");
3025 * Emit declarations for resources.
3026 * XXX When we're sure that all TGSI shaders will be generated with
3027 * sampler view declarations (Ex: DCL SVIEW[n], 2D, UINT) we may
3031 emit_resource_declarations(struct svga_shader_emitter_v10
*emit
)
3035 /* Emit resource decl for each sampler */
3036 for (i
= 0; i
< emit
->num_samplers
; i
++) {
3037 VGPU10OpcodeToken0 opcode0
;
3038 VGPU10OperandToken0 operand0
;
3039 VGPU10ResourceReturnTypeToken return_type
;
3040 VGPU10_RESOURCE_RETURN_TYPE rt
;
3043 opcode0
.opcodeType
= VGPU10_OPCODE_DCL_RESOURCE
;
3044 opcode0
.resourceDimension
=
3045 tgsi_texture_to_resource_dimension(emit
->sampler_target
[i
],
3046 emit
->key
.tex
[i
].is_array
);
3048 operand0
.numComponents
= VGPU10_OPERAND_0_COMPONENT
;
3049 operand0
.operandType
= VGPU10_OPERAND_TYPE_RESOURCE
;
3050 operand0
.indexDimension
= VGPU10_OPERAND_INDEX_1D
;
3051 operand0
.index0Representation
= VGPU10_OPERAND_INDEX_IMMEDIATE32
;
3054 /* convert TGSI_RETURN_TYPE_x to VGPU10_RETURN_TYPE_x */
3055 STATIC_ASSERT(VGPU10_RETURN_TYPE_UNORM
== TGSI_RETURN_TYPE_UNORM
+ 1);
3056 STATIC_ASSERT(VGPU10_RETURN_TYPE_SNORM
== TGSI_RETURN_TYPE_SNORM
+ 1);
3057 STATIC_ASSERT(VGPU10_RETURN_TYPE_SINT
== TGSI_RETURN_TYPE_SINT
+ 1);
3058 STATIC_ASSERT(VGPU10_RETURN_TYPE_UINT
== TGSI_RETURN_TYPE_UINT
+ 1);
3059 STATIC_ASSERT(VGPU10_RETURN_TYPE_FLOAT
== TGSI_RETURN_TYPE_FLOAT
+ 1);
3060 assert(emit
->sampler_return_type
[i
] <= TGSI_RETURN_TYPE_FLOAT
);
3061 rt
= emit
->sampler_return_type
[i
] + 1;
3063 switch (emit
->sampler_return_type
[i
]) {
3064 case TGSI_RETURN_TYPE_UNORM
: rt
= VGPU10_RETURN_TYPE_UNORM
; break;
3065 case TGSI_RETURN_TYPE_SNORM
: rt
= VGPU10_RETURN_TYPE_SNORM
; break;
3066 case TGSI_RETURN_TYPE_SINT
: rt
= VGPU10_RETURN_TYPE_SINT
; break;
3067 case TGSI_RETURN_TYPE_UINT
: rt
= VGPU10_RETURN_TYPE_UINT
; break;
3068 case TGSI_RETURN_TYPE_FLOAT
: rt
= VGPU10_RETURN_TYPE_FLOAT
; break;
3069 case TGSI_RETURN_TYPE_COUNT
:
3071 rt
= VGPU10_RETURN_TYPE_FLOAT
;
3072 assert(!"emit_resource_declarations: Unknown tgsi_return_type");
3076 return_type
.value
= 0;
3077 return_type
.component0
= rt
;
3078 return_type
.component1
= rt
;
3079 return_type
.component2
= rt
;
3080 return_type
.component3
= rt
;
3082 begin_emit_instruction(emit
);
3083 emit_dword(emit
, opcode0
.value
);
3084 emit_dword(emit
, operand0
.value
);
3085 emit_dword(emit
, i
);
3086 emit_dword(emit
, return_type
.value
);
3087 end_emit_instruction(emit
);
3094 emit_instruction_op1(struct svga_shader_emitter_v10
*emit
,
3096 const struct tgsi_full_dst_register
*dst
,
3097 const struct tgsi_full_src_register
*src
,
3100 begin_emit_instruction(emit
);
3101 emit_opcode(emit
, opcode
, saturate
);
3102 emit_dst_register(emit
, dst
);
3103 emit_src_register(emit
, src
);
3104 end_emit_instruction(emit
);
3108 emit_instruction_op2(struct svga_shader_emitter_v10
*emit
,
3110 const struct tgsi_full_dst_register
*dst
,
3111 const struct tgsi_full_src_register
*src1
,
3112 const struct tgsi_full_src_register
*src2
,
3115 begin_emit_instruction(emit
);
3116 emit_opcode(emit
, opcode
, saturate
);
3117 emit_dst_register(emit
, dst
);
3118 emit_src_register(emit
, src1
);
3119 emit_src_register(emit
, src2
);
3120 end_emit_instruction(emit
);
3124 emit_instruction_op3(struct svga_shader_emitter_v10
*emit
,
3126 const struct tgsi_full_dst_register
*dst
,
3127 const struct tgsi_full_src_register
*src1
,
3128 const struct tgsi_full_src_register
*src2
,
3129 const struct tgsi_full_src_register
*src3
,
3132 begin_emit_instruction(emit
);
3133 emit_opcode(emit
, opcode
, saturate
);
3134 emit_dst_register(emit
, dst
);
3135 emit_src_register(emit
, src1
);
3136 emit_src_register(emit
, src2
);
3137 emit_src_register(emit
, src3
);
3138 end_emit_instruction(emit
);
3142 * Emit the actual clip distance instructions to be used for clipping
3143 * by copying the clip distance from the temporary registers to the
3144 * CLIPDIST registers written with the enabled planes mask.
3145 * Also copy the clip distance from the temporary to the clip distance
3146 * shadow copy register which will be referenced by the input shader
3149 emit_clip_distance_instructions(struct svga_shader_emitter_v10
*emit
)
3151 struct tgsi_full_src_register tmp_clip_dist_src
;
3152 struct tgsi_full_dst_register clip_dist_dst
;
3155 unsigned clip_plane_enable
= emit
->key
.clip_plane_enable
;
3156 unsigned clip_dist_tmp_index
= emit
->clip_dist_tmp_index
;
3157 int num_written_clipdist
= emit
->info
.num_written_clipdistance
;
3159 assert(emit
->clip_dist_out_index
!= INVALID_INDEX
);
3160 assert(emit
->clip_dist_tmp_index
!= INVALID_INDEX
);
3163 * Temporary reset the temporary clip dist register index so
3164 * that the copy to the real clip dist register will not
3165 * attempt to copy to the temporary register again
3167 emit
->clip_dist_tmp_index
= INVALID_INDEX
;
3169 for (i
= 0; i
< 2 && num_written_clipdist
> 0; i
++, num_written_clipdist
-=4) {
3171 tmp_clip_dist_src
= make_src_temp_reg(clip_dist_tmp_index
+ i
);
3174 * copy to the shadow copy for use by varying variable and
3175 * stream output. All clip distances
3176 * will be written regardless of the enabled clipping planes.
3178 clip_dist_dst
= make_dst_reg(TGSI_FILE_OUTPUT
,
3179 emit
->clip_dist_so_index
+ i
);
3181 /* MOV clip_dist_so, tmp_clip_dist */
3182 emit_instruction_op1(emit
, VGPU10_OPCODE_MOV
, &clip_dist_dst
,
3183 &tmp_clip_dist_src
, FALSE
);
3186 * copy those clip distances to enabled clipping planes
3187 * to CLIPDIST registers for clipping
3189 if (clip_plane_enable
& 0xf) {
3190 clip_dist_dst
= make_dst_reg(TGSI_FILE_OUTPUT
,
3191 emit
->clip_dist_out_index
+ i
);
3192 clip_dist_dst
= writemask_dst(&clip_dist_dst
, clip_plane_enable
& 0xf);
3194 /* MOV CLIPDIST, tmp_clip_dist */
3195 emit_instruction_op1(emit
, VGPU10_OPCODE_MOV
, &clip_dist_dst
,
3196 &tmp_clip_dist_src
, FALSE
);
3198 /* four clip planes per clip register */
3199 clip_plane_enable
>>= 4;
3202 * set the temporary clip dist register index back to the
3203 * temporary index for the next vertex
3205 emit
->clip_dist_tmp_index
= clip_dist_tmp_index
;
3208 /* Declare clip distance output registers for user-defined clip planes
3209 * or the TGSI_CLIPVERTEX output.
3212 emit_clip_distance_declarations(struct svga_shader_emitter_v10
*emit
)
3214 unsigned num_clip_planes
= util_bitcount(emit
->key
.clip_plane_enable
);
3215 unsigned index
= emit
->num_outputs
;
3216 unsigned plane_mask
;
3218 assert(emit
->unit
== PIPE_SHADER_VERTEX
||
3219 emit
->unit
== PIPE_SHADER_GEOMETRY
);
3220 assert(num_clip_planes
<= 8);
3222 if (emit
->clip_mode
!= CLIP_LEGACY
&&
3223 emit
->clip_mode
!= CLIP_VERTEX
) {
3227 if (num_clip_planes
== 0)
3230 /* Declare one or two clip output registers. The number of components
3231 * in the mask reflects the number of clip planes. For example, if 5
3232 * clip planes are needed, we'll declare outputs similar to:
3233 * dcl_output_siv o2.xyzw, clip_distance
3234 * dcl_output_siv o3.x, clip_distance
3236 emit
->clip_dist_out_index
= index
; /* save the starting clip dist reg index */
3238 plane_mask
= (1 << num_clip_planes
) - 1;
3239 if (plane_mask
& 0xf) {
3240 unsigned cmask
= plane_mask
& VGPU10_OPERAND_4_COMPONENT_MASK_ALL
;
3241 emit_output_declaration(emit
, VGPU10_OPCODE_DCL_OUTPUT_SIV
, index
,
3242 VGPU10_NAME_CLIP_DISTANCE
, cmask
);
3243 emit
->num_outputs
++;
3245 if (plane_mask
& 0xf0) {
3246 unsigned cmask
= (plane_mask
>> 4) & VGPU10_OPERAND_4_COMPONENT_MASK_ALL
;
3247 emit_output_declaration(emit
, VGPU10_OPCODE_DCL_OUTPUT_SIV
, index
+ 1,
3248 VGPU10_NAME_CLIP_DISTANCE
, cmask
);
3249 emit
->num_outputs
++;
3255 * Emit the instructions for writing to the clip distance registers
3256 * to handle legacy/automatic clip planes.
3257 * For each clip plane, the distance is the dot product of the vertex
3258 * position (found in TEMP[vpos_tmp_index]) and the clip plane coefficients.
3259 * This is not used when the shader has an explicit CLIPVERTEX or CLIPDISTANCE
3260 * output registers already declared.
3263 emit_clip_distance_from_vpos(struct svga_shader_emitter_v10
*emit
,
3264 unsigned vpos_tmp_index
)
3266 unsigned i
, num_clip_planes
= util_bitcount(emit
->key
.clip_plane_enable
);
3268 assert(emit
->clip_mode
== CLIP_LEGACY
);
3269 assert(num_clip_planes
<= 8);
3271 assert(emit
->unit
== PIPE_SHADER_VERTEX
||
3272 emit
->unit
== PIPE_SHADER_GEOMETRY
);
3274 for (i
= 0; i
< num_clip_planes
; i
++) {
3275 struct tgsi_full_dst_register dst
;
3276 struct tgsi_full_src_register plane_src
, vpos_src
;
3277 unsigned reg_index
= emit
->clip_dist_out_index
+ i
/ 4;
3278 unsigned comp
= i
% 4;
3279 unsigned writemask
= VGPU10_OPERAND_4_COMPONENT_MASK_X
<< comp
;
3281 /* create dst, src regs */
3282 dst
= make_dst_reg(TGSI_FILE_OUTPUT
, reg_index
);
3283 dst
= writemask_dst(&dst
, writemask
);
3285 plane_src
= make_src_const_reg(emit
->clip_plane_const
[i
]);
3286 vpos_src
= make_src_temp_reg(vpos_tmp_index
);
3288 /* DP4 clip_dist, plane, vpos */
3289 emit_instruction_op2(emit
, VGPU10_OPCODE_DP4
, &dst
,
3290 &plane_src
, &vpos_src
, FALSE
);
3296 * Emit the instructions for computing the clip distance results from
3297 * the clip vertex temporary.
3298 * For each clip plane, the distance is the dot product of the clip vertex
3299 * position (found in a temp reg) and the clip plane coefficients.
3302 emit_clip_vertex_instructions(struct svga_shader_emitter_v10
*emit
)
3304 const unsigned num_clip
= util_bitcount(emit
->key
.clip_plane_enable
);
3306 struct tgsi_full_dst_register dst
;
3307 struct tgsi_full_src_register clipvert_src
;
3308 const unsigned clip_vertex_tmp
= emit
->clip_vertex_tmp_index
;
3310 assert(emit
->unit
== PIPE_SHADER_VERTEX
||
3311 emit
->unit
== PIPE_SHADER_GEOMETRY
);
3313 assert(emit
->clip_mode
== CLIP_VERTEX
);
3315 clipvert_src
= make_src_temp_reg(clip_vertex_tmp
);
3317 for (i
= 0; i
< num_clip
; i
++) {
3318 struct tgsi_full_src_register plane_src
;
3319 unsigned reg_index
= emit
->clip_dist_out_index
+ i
/ 4;
3320 unsigned comp
= i
% 4;
3321 unsigned writemask
= VGPU10_OPERAND_4_COMPONENT_MASK_X
<< comp
;
3323 /* create dst, src regs */
3324 dst
= make_dst_reg(TGSI_FILE_OUTPUT
, reg_index
);
3325 dst
= writemask_dst(&dst
, writemask
);
3327 plane_src
= make_src_const_reg(emit
->clip_plane_const
[i
]);
3329 /* DP4 clip_dist, plane, vpos */
3330 emit_instruction_op2(emit
, VGPU10_OPCODE_DP4
, &dst
,
3331 &plane_src
, &clipvert_src
, FALSE
);
3334 /* copy temporary clip vertex register to the clip vertex register */
3336 assert(emit
->clip_vertex_out_index
!= INVALID_INDEX
);
3339 * temporary reset the temporary clip vertex register index so
3340 * that copy to the clip vertex register will not attempt
3341 * to copy to the temporary register again
3343 emit
->clip_vertex_tmp_index
= INVALID_INDEX
;
3345 /* MOV clip_vertex, clip_vertex_tmp */
3346 dst
= make_dst_reg(TGSI_FILE_OUTPUT
, emit
->clip_vertex_out_index
);
3347 emit_instruction_op1(emit
, VGPU10_OPCODE_MOV
,
3348 &dst
, &clipvert_src
, FALSE
);
3351 * set the temporary clip vertex register index back to the
3352 * temporary index for the next vertex
3354 emit
->clip_vertex_tmp_index
= clip_vertex_tmp
;
3358 * Emit code to convert RGBA to BGRA
3361 emit_swap_r_b(struct svga_shader_emitter_v10
*emit
,
3362 const struct tgsi_full_dst_register
*dst
,
3363 const struct tgsi_full_src_register
*src
)
3365 struct tgsi_full_src_register bgra_src
=
3366 swizzle_src(src
, TGSI_SWIZZLE_Z
, TGSI_SWIZZLE_Y
, TGSI_SWIZZLE_X
, TGSI_SWIZZLE_W
);
3368 begin_emit_instruction(emit
);
3369 emit_opcode(emit
, VGPU10_OPCODE_MOV
, FALSE
);
3370 emit_dst_register(emit
, dst
);
3371 emit_src_register(emit
, &bgra_src
);
3372 end_emit_instruction(emit
);
3376 /** Convert from 10_10_10_2 normalized to 10_10_10_2_snorm */
3378 emit_puint_to_snorm(struct svga_shader_emitter_v10
*emit
,
3379 const struct tgsi_full_dst_register
*dst
,
3380 const struct tgsi_full_src_register
*src
)
3382 struct tgsi_full_src_register half
= make_immediate_reg_float(emit
, 0.5f
);
3383 struct tgsi_full_src_register two
=
3384 make_immediate_reg_float4(emit
, 2.0f
, 2.0f
, 2.0f
, 3.0f
);
3385 struct tgsi_full_src_register neg_two
=
3386 make_immediate_reg_float4(emit
, -2.0f
, -2.0f
, -2.0f
, -1.66666f
);
3388 unsigned val_tmp
= get_temp_index(emit
);
3389 struct tgsi_full_dst_register val_dst
= make_dst_temp_reg(val_tmp
);
3390 struct tgsi_full_src_register val_src
= make_src_temp_reg(val_tmp
);
3392 unsigned bias_tmp
= get_temp_index(emit
);
3393 struct tgsi_full_dst_register bias_dst
= make_dst_temp_reg(bias_tmp
);
3394 struct tgsi_full_src_register bias_src
= make_src_temp_reg(bias_tmp
);
3396 /* val = src * 2.0 */
3397 emit_instruction_op2(emit
, VGPU10_OPCODE_MUL
, &val_dst
,
3400 /* bias = src > 0.5 */
3401 emit_instruction_op2(emit
, VGPU10_OPCODE_GE
, &bias_dst
,
3404 /* bias = bias & -2.0 */
3405 emit_instruction_op2(emit
, VGPU10_OPCODE_AND
, &bias_dst
,
3406 &bias_src
, &neg_two
, FALSE
);
3408 /* dst = val + bias */
3409 emit_instruction_op2(emit
, VGPU10_OPCODE_ADD
, dst
,
3410 &val_src
, &bias_src
, FALSE
);
3412 free_temp_indexes(emit
);
3416 /** Convert from 10_10_10_2_unorm to 10_10_10_2_uscaled */
3418 emit_puint_to_uscaled(struct svga_shader_emitter_v10
*emit
,
3419 const struct tgsi_full_dst_register
*dst
,
3420 const struct tgsi_full_src_register
*src
)
3422 struct tgsi_full_src_register scale
=
3423 make_immediate_reg_float4(emit
, 1023.0f
, 1023.0f
, 1023.0f
, 3.0f
);
3425 /* dst = src * scale */
3426 emit_instruction_op2(emit
, VGPU10_OPCODE_MUL
, dst
, src
, &scale
, FALSE
);
3430 /** Convert from R32_UINT to 10_10_10_2_sscaled */
3432 emit_puint_to_sscaled(struct svga_shader_emitter_v10
*emit
,
3433 const struct tgsi_full_dst_register
*dst
,
3434 const struct tgsi_full_src_register
*src
)
3436 struct tgsi_full_src_register lshift
=
3437 make_immediate_reg_int4(emit
, 22, 12, 2, 0);
3438 struct tgsi_full_src_register rshift
=
3439 make_immediate_reg_int4(emit
, 22, 22, 22, 30);
3441 struct tgsi_full_src_register src_xxxx
= scalar_src(src
, TGSI_SWIZZLE_X
);
3443 unsigned tmp
= get_temp_index(emit
);
3444 struct tgsi_full_dst_register tmp_dst
= make_dst_temp_reg(tmp
);
3445 struct tgsi_full_src_register tmp_src
= make_src_temp_reg(tmp
);
3448 * r = (pixel << 22) >> 22; # signed int in [511, -512]
3449 * g = (pixel << 12) >> 22; # signed int in [511, -512]
3450 * b = (pixel << 2) >> 22; # signed int in [511, -512]
3451 * a = (pixel << 0) >> 30; # signed int in [1, -2]
3452 * dst = i_to_f(r,g,b,a); # convert to float
3454 emit_instruction_op2(emit
, VGPU10_OPCODE_ISHL
, &tmp_dst
,
3455 &src_xxxx
, &lshift
, FALSE
);
3456 emit_instruction_op2(emit
, VGPU10_OPCODE_ISHR
, &tmp_dst
,
3457 &tmp_src
, &rshift
, FALSE
);
3458 emit_instruction_op1(emit
, VGPU10_OPCODE_ITOF
, dst
, &tmp_src
, FALSE
);
3460 free_temp_indexes(emit
);
3465 * Emit code for TGSI_OPCODE_ARL or TGSI_OPCODE_UARL instruction.
3468 emit_arl_uarl(struct svga_shader_emitter_v10
*emit
,
3469 const struct tgsi_full_instruction
*inst
)
3471 unsigned index
= inst
->Dst
[0].Register
.Index
;
3472 struct tgsi_full_dst_register dst
;
3475 assert(index
< MAX_VGPU10_ADDR_REGS
);
3476 dst
= make_dst_temp_reg(emit
->address_reg_index
[index
]);
3480 * FTOI address_tmp, s0
3484 * MOV address_tmp, s0
3486 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ARL
)
3487 opcode
= VGPU10_OPCODE_FTOI
;
3489 opcode
= VGPU10_OPCODE_MOV
;
3491 emit_instruction_op1(emit
, opcode
, &dst
, &inst
->Src
[0], FALSE
);
3498 * Emit code for TGSI_OPCODE_CAL instruction.
3501 emit_cal(struct svga_shader_emitter_v10
*emit
,
3502 const struct tgsi_full_instruction
*inst
)
3504 unsigned label
= inst
->Label
.Label
;
3505 VGPU10OperandToken0 operand
;
3507 operand
.operandType
= VGPU10_OPERAND_TYPE_LABEL
;
3509 begin_emit_instruction(emit
);
3510 emit_dword(emit
, operand
.value
);
3511 emit_dword(emit
, label
);
3512 end_emit_instruction(emit
);
3519 * Emit code for TGSI_OPCODE_IABS instruction.
3522 emit_iabs(struct svga_shader_emitter_v10
*emit
,
3523 const struct tgsi_full_instruction
*inst
)
3525 /* dst.x = (src0.x < 0) ? -src0.x : src0.x
3526 * dst.y = (src0.y < 0) ? -src0.y : src0.y
3527 * dst.z = (src0.z < 0) ? -src0.z : src0.z
3528 * dst.w = (src0.w < 0) ? -src0.w : src0.w
3531 * IMAX dst, src, neg(src)
3533 struct tgsi_full_src_register neg_src
= negate_src(&inst
->Src
[0]);
3534 emit_instruction_op2(emit
, VGPU10_OPCODE_IMAX
, &inst
->Dst
[0],
3535 &inst
->Src
[0], &neg_src
, FALSE
);
3542 * Emit code for TGSI_OPCODE_CMP instruction.
3545 emit_cmp(struct svga_shader_emitter_v10
*emit
,
3546 const struct tgsi_full_instruction
*inst
)
3548 /* dst.x = (src0.x < 0) ? src1.x : src2.x
3549 * dst.y = (src0.y < 0) ? src1.y : src2.y
3550 * dst.z = (src0.z < 0) ? src1.z : src2.z
3551 * dst.w = (src0.w < 0) ? src1.w : src2.w
3555 * MOVC dst, tmp, src1, src2
3557 struct tgsi_full_src_register zero
= make_immediate_reg_float(emit
, 0.0f
);
3558 unsigned tmp
= get_temp_index(emit
);
3559 struct tgsi_full_src_register tmp_src
= make_src_temp_reg(tmp
);
3560 struct tgsi_full_dst_register tmp_dst
= make_dst_temp_reg(tmp
);
3562 emit_instruction_op2(emit
, VGPU10_OPCODE_LT
, &tmp_dst
,
3563 &inst
->Src
[0], &zero
, FALSE
);
3564 emit_instruction_op3(emit
, VGPU10_OPCODE_MOVC
, &inst
->Dst
[0],
3565 &tmp_src
, &inst
->Src
[1], &inst
->Src
[2],
3566 inst
->Instruction
.Saturate
);
3568 free_temp_indexes(emit
);
3575 * Emit code for TGSI_OPCODE_DP2A instruction.
3578 emit_dp2a(struct svga_shader_emitter_v10
*emit
,
3579 const struct tgsi_full_instruction
*inst
)
3581 /* dst.x = src0.x * src1.x + src0.y * src1.y + src2.x
3582 * dst.y = src0.x * src1.x + src0.y * src1.y + src2.x
3583 * dst.z = src0.x * src1.x + src0.y * src1.y + src2.x
3584 * dst.w = src0.x * src1.x + src0.y * src1.y + src2.x
3586 * MAD tmp.x, s0.y, s1.y, s2.x
3587 * MAD tmp.x, s0.x, s1.x, tmp.x
3588 * MOV dst.xyzw, tmp.xxxx
3590 unsigned tmp
= get_temp_index(emit
);
3591 struct tgsi_full_src_register tmp_src
= make_src_temp_reg(tmp
);
3592 struct tgsi_full_dst_register tmp_dst
= make_dst_temp_reg(tmp
);
3594 struct tgsi_full_src_register tmp_src_xxxx
=
3595 scalar_src(&tmp_src
, TGSI_SWIZZLE_X
);
3596 struct tgsi_full_dst_register tmp_dst_x
=
3597 writemask_dst(&tmp_dst
, TGSI_WRITEMASK_X
);
3599 struct tgsi_full_src_register src0_xxxx
=
3600 scalar_src(&inst
->Src
[0], TGSI_SWIZZLE_X
);
3601 struct tgsi_full_src_register src0_yyyy
=
3602 scalar_src(&inst
->Src
[0], TGSI_SWIZZLE_Y
);
3603 struct tgsi_full_src_register src1_xxxx
=
3604 scalar_src(&inst
->Src
[1], TGSI_SWIZZLE_X
);
3605 struct tgsi_full_src_register src1_yyyy
=
3606 scalar_src(&inst
->Src
[1], TGSI_SWIZZLE_Y
);
3607 struct tgsi_full_src_register src2_xxxx
=
3608 scalar_src(&inst
->Src
[2], TGSI_SWIZZLE_X
);
3610 emit_instruction_op3(emit
, VGPU10_OPCODE_MAD
, &tmp_dst_x
, &src0_yyyy
,
3611 &src1_yyyy
, &src2_xxxx
, FALSE
);
3612 emit_instruction_op3(emit
, VGPU10_OPCODE_MAD
, &tmp_dst_x
, &src0_xxxx
,
3613 &src1_xxxx
, &tmp_src_xxxx
, FALSE
);
3614 emit_instruction_op1(emit
, VGPU10_OPCODE_MOV
, &inst
->Dst
[0],
3615 &tmp_src_xxxx
, inst
->Instruction
.Saturate
);
3617 free_temp_indexes(emit
);
3624 * Emit code for TGSI_OPCODE_DPH instruction.
3627 emit_dph(struct svga_shader_emitter_v10
*emit
,
3628 const struct tgsi_full_instruction
*inst
)
3632 * ADD dst, tmp, s1.wwww
3635 struct tgsi_full_src_register s1_wwww
=
3636 swizzle_src(&inst
->Src
[1], TGSI_SWIZZLE_W
, TGSI_SWIZZLE_W
,
3637 TGSI_SWIZZLE_W
, TGSI_SWIZZLE_W
);
3639 unsigned tmp
= get_temp_index(emit
);
3640 struct tgsi_full_src_register tmp_src
= make_src_temp_reg(tmp
);
3641 struct tgsi_full_dst_register tmp_dst
= make_dst_temp_reg(tmp
);
3643 /* DP3 tmp, s0, s1 */
3644 emit_instruction_op2(emit
, VGPU10_OPCODE_DP3
, &tmp_dst
, &inst
->Src
[0],
3645 &inst
->Src
[1], FALSE
);
3647 /* ADD dst, tmp, s1.wwww */
3648 emit_instruction_op2(emit
, VGPU10_OPCODE_ADD
, &inst
->Dst
[0], &tmp_src
,
3649 &s1_wwww
, inst
->Instruction
.Saturate
);
3651 free_temp_indexes(emit
);
3658 * Emit code for TGSI_OPCODE_DST instruction.
3661 emit_dst(struct svga_shader_emitter_v10
*emit
,
3662 const struct tgsi_full_instruction
*inst
)
3666 * dst.y = src0.y * src1.y
3671 struct tgsi_full_src_register s0_yyyy
=
3672 scalar_src(&inst
->Src
[0], TGSI_SWIZZLE_Y
);
3673 struct tgsi_full_src_register s0_zzzz
=
3674 scalar_src(&inst
->Src
[0], TGSI_SWIZZLE_Z
);
3675 struct tgsi_full_src_register s1_yyyy
=
3676 scalar_src(&inst
->Src
[1], TGSI_SWIZZLE_Y
);
3677 struct tgsi_full_src_register s1_wwww
=
3678 scalar_src(&inst
->Src
[1], TGSI_SWIZZLE_W
);
3681 * If dst and either src0 and src1 are the same we need
3682 * to create a temporary for it and insert a extra move.
3684 unsigned tmp_move
= get_temp_index(emit
);
3685 struct tgsi_full_src_register move_src
= make_src_temp_reg(tmp_move
);
3686 struct tgsi_full_dst_register move_dst
= make_dst_temp_reg(tmp_move
);
3688 /* MOV dst.x, 1.0 */
3689 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3690 struct tgsi_full_dst_register dst_x
=
3691 writemask_dst(&move_dst
, TGSI_WRITEMASK_X
);
3692 struct tgsi_full_src_register one
= make_immediate_reg_float(emit
, 1.0f
);
3694 emit_instruction_op1(emit
, VGPU10_OPCODE_MOV
, &dst_x
, &one
, FALSE
);
3697 /* MUL dst.y, s0.y, s1.y */
3698 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3699 struct tgsi_full_dst_register dst_y
=
3700 writemask_dst(&move_dst
, TGSI_WRITEMASK_Y
);
3702 emit_instruction_op2(emit
, VGPU10_OPCODE_MUL
, &dst_y
, &s0_yyyy
,
3703 &s1_yyyy
, inst
->Instruction
.Saturate
);
3706 /* MOV dst.z, s0.z */
3707 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3708 struct tgsi_full_dst_register dst_z
=
3709 writemask_dst(&move_dst
, TGSI_WRITEMASK_Z
);
3711 emit_instruction_op1(emit
, VGPU10_OPCODE_MOV
, &dst_z
, &s0_zzzz
,
3712 inst
->Instruction
.Saturate
);
3715 /* MOV dst.w, s1.w */
3716 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3717 struct tgsi_full_dst_register dst_w
=
3718 writemask_dst(&move_dst
, TGSI_WRITEMASK_W
);
3720 emit_instruction_op1(emit
, VGPU10_OPCODE_MOV
, &dst_w
, &s1_wwww
,
3721 inst
->Instruction
.Saturate
);
3724 emit_instruction_op1(emit
, VGPU10_OPCODE_MOV
, &inst
->Dst
[0], &move_src
,
3726 free_temp_indexes(emit
);
3734 * Emit code for TGSI_OPCODE_ENDPRIM (GS only)
3737 emit_endprim(struct svga_shader_emitter_v10
*emit
,
3738 const struct tgsi_full_instruction
*inst
)
3740 assert(emit
->unit
== PIPE_SHADER_GEOMETRY
);
3742 /* We can't use emit_simple() because the TGSI instruction has one
3743 * operand (vertex stream number) which we must ignore for VGPU10.
3745 begin_emit_instruction(emit
);
3746 emit_opcode(emit
, VGPU10_OPCODE_CUT
, FALSE
);
3747 end_emit_instruction(emit
);
3753 * Emit code for TGSI_OPCODE_EX2 (2^x) instruction.
3756 emit_ex2(struct svga_shader_emitter_v10
*emit
,
3757 const struct tgsi_full_instruction
*inst
)
3759 /* Note that TGSI_OPCODE_EX2 computes only one value from src.x
3760 * while VGPU10 computes four values.
3763 * dst.xyzw = 2.0 ^ src.x
3766 struct tgsi_full_src_register src_xxxx
=
3767 swizzle_src(&inst
->Src
[0], TGSI_SWIZZLE_X
, TGSI_SWIZZLE_X
,
3768 TGSI_SWIZZLE_X
, TGSI_SWIZZLE_X
);
3770 /* EXP tmp, s0.xxxx */
3771 emit_instruction_op1(emit
, VGPU10_OPCODE_EXP
, &inst
->Dst
[0], &src_xxxx
,
3772 inst
->Instruction
.Saturate
);
3779 * Emit code for TGSI_OPCODE_EXP instruction.
3782 emit_exp(struct svga_shader_emitter_v10
*emit
,
3783 const struct tgsi_full_instruction
*inst
)
3786 * dst.x = 2 ^ floor(s0.x)
3787 * dst.y = s0.x - floor(s0.x)
3792 struct tgsi_full_src_register src_xxxx
=
3793 scalar_src(&inst
->Src
[0], TGSI_SWIZZLE_X
);
3794 unsigned tmp
= get_temp_index(emit
);
3795 struct tgsi_full_src_register tmp_src
= make_src_temp_reg(tmp
);
3796 struct tgsi_full_dst_register tmp_dst
= make_dst_temp_reg(tmp
);
3799 * If dst and src are the same we need to create
3800 * a temporary for it and insert a extra move.
3802 unsigned tmp_move
= get_temp_index(emit
);
3803 struct tgsi_full_src_register move_src
= make_src_temp_reg(tmp_move
);
3804 struct tgsi_full_dst_register move_dst
= make_dst_temp_reg(tmp_move
);
3806 /* only use X component of temp reg */
3807 tmp_dst
= writemask_dst(&tmp_dst
, TGSI_WRITEMASK_X
);
3808 tmp_src
= scalar_src(&tmp_src
, TGSI_SWIZZLE_X
);
3810 /* ROUND_NI tmp.x, s0.x */
3811 emit_instruction_op1(emit
, VGPU10_OPCODE_ROUND_NI
, &tmp_dst
,
3812 &src_xxxx
, FALSE
); /* round to -infinity */
3814 /* EXP dst.x, tmp.x */
3815 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
3816 struct tgsi_full_dst_register dst_x
=
3817 writemask_dst(&move_dst
, TGSI_WRITEMASK_X
);
3819 emit_instruction_op1(emit
, VGPU10_OPCODE_EXP
, &dst_x
, &tmp_src
,
3820 inst
->Instruction
.Saturate
);
3823 /* ADD dst.y, s0.x, -tmp */
3824 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
3825 struct tgsi_full_dst_register dst_y
=
3826 writemask_dst(&move_dst
, TGSI_WRITEMASK_Y
);
3827 struct tgsi_full_src_register neg_tmp_src
= negate_src(&tmp_src
);
3829 emit_instruction_op2(emit
, VGPU10_OPCODE_ADD
, &dst_y
, &src_xxxx
,
3830 &neg_tmp_src
, inst
->Instruction
.Saturate
);
3833 /* EXP dst.z, s0.x */
3834 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
3835 struct tgsi_full_dst_register dst_z
=
3836 writemask_dst(&move_dst
, TGSI_WRITEMASK_Z
);
3838 emit_instruction_op1(emit
, VGPU10_OPCODE_EXP
, &dst_z
, &src_xxxx
,
3839 inst
->Instruction
.Saturate
);
3842 /* MOV dst.w, 1.0 */
3843 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
3844 struct tgsi_full_dst_register dst_w
=
3845 writemask_dst(&move_dst
, TGSI_WRITEMASK_W
);
3846 struct tgsi_full_src_register one
= make_immediate_reg_float(emit
, 1.0f
);
3848 emit_instruction_op1(emit
, VGPU10_OPCODE_MOV
, &dst_w
, &one
,
3852 emit_instruction_op1(emit
, VGPU10_OPCODE_MOV
, &inst
->Dst
[0], &move_src
,
3855 free_temp_indexes(emit
);
3862 * Emit code for TGSI_OPCODE_IF instruction.
3865 emit_if(struct svga_shader_emitter_v10
*emit
,
3866 const struct tgsi_full_instruction
*inst
)
3868 VGPU10OpcodeToken0 opcode0
;
3870 /* The src register should be a scalar */
3871 assert(inst
->Src
[0].Register
.SwizzleX
== inst
->Src
[0].Register
.SwizzleY
&&
3872 inst
->Src
[0].Register
.SwizzleX
== inst
->Src
[0].Register
.SwizzleZ
&&
3873 inst
->Src
[0].Register
.SwizzleX
== inst
->Src
[0].Register
.SwizzleW
);
3875 /* The only special thing here is that we need to set the
3876 * VGPU10_INSTRUCTION_TEST_NONZERO flag since we want to test if
3877 * src.x is non-zero.
3880 opcode0
.opcodeType
= VGPU10_OPCODE_IF
;
3881 opcode0
.testBoolean
= VGPU10_INSTRUCTION_TEST_NONZERO
;
3883 begin_emit_instruction(emit
);
3884 emit_dword(emit
, opcode0
.value
);
3885 emit_src_register(emit
, &inst
->Src
[0]);
3886 end_emit_instruction(emit
);
3893 * Emit code for TGSI_OPCODE_KILL_IF instruction (kill fragment if any of
3894 * the register components are negative).
3897 emit_kill_if(struct svga_shader_emitter_v10
*emit
,
3898 const struct tgsi_full_instruction
*inst
)
3900 unsigned tmp
= get_temp_index(emit
);
3901 struct tgsi_full_src_register tmp_src
= make_src_temp_reg(tmp
);
3902 struct tgsi_full_dst_register tmp_dst
= make_dst_temp_reg(tmp
);
3904 struct tgsi_full_src_register zero
= make_immediate_reg_float(emit
, 0.0f
);
3906 struct tgsi_full_dst_register tmp_dst_x
=
3907 writemask_dst(&tmp_dst
, TGSI_WRITEMASK_X
);
3908 struct tgsi_full_src_register tmp_src_xxxx
=
3909 scalar_src(&tmp_src
, TGSI_SWIZZLE_X
);
3911 /* tmp = src[0] < 0.0 */
3912 emit_instruction_op2(emit
, VGPU10_OPCODE_LT
, &tmp_dst
, &inst
->Src
[0],
3915 if (!same_swizzle_terms(&inst
->Src
[0])) {
3916 /* If the swizzle is not XXXX, YYYY, ZZZZ or WWWW we need to
3917 * logically OR the swizzle terms. Most uses of KILL_IF only
3918 * test one channel so it's good to avoid these extra steps.
3920 struct tgsi_full_src_register tmp_src_yyyy
=
3921 scalar_src(&tmp_src
, TGSI_SWIZZLE_Y
);
3922 struct tgsi_full_src_register tmp_src_zzzz
=
3923 scalar_src(&tmp_src
, TGSI_SWIZZLE_Z
);
3924 struct tgsi_full_src_register tmp_src_wwww
=
3925 scalar_src(&tmp_src
, TGSI_SWIZZLE_W
);
3927 emit_instruction_op2(emit
, VGPU10_OPCODE_OR
, &tmp_dst_x
, &tmp_src_xxxx
,
3928 &tmp_src_yyyy
, FALSE
);
3929 emit_instruction_op2(emit
, VGPU10_OPCODE_OR
, &tmp_dst_x
, &tmp_src_xxxx
,
3930 &tmp_src_zzzz
, FALSE
);
3931 emit_instruction_op2(emit
, VGPU10_OPCODE_OR
, &tmp_dst_x
, &tmp_src_xxxx
,
3932 &tmp_src_wwww
, FALSE
);
3935 begin_emit_instruction(emit
);
3936 emit_discard_opcode(emit
, TRUE
); /* discard if src0.x is non-zero */
3937 emit_src_register(emit
, &tmp_src_xxxx
);
3938 end_emit_instruction(emit
);
3940 free_temp_indexes(emit
);
3947 * Emit code for TGSI_OPCODE_KILL instruction (unconditional discard).
3950 emit_kill(struct svga_shader_emitter_v10
*emit
,
3951 const struct tgsi_full_instruction
*inst
)
3953 struct tgsi_full_src_register zero
= make_immediate_reg_float(emit
, 0.0f
);
3955 /* DISCARD if 0.0 is zero */
3956 begin_emit_instruction(emit
);
3957 emit_discard_opcode(emit
, FALSE
);
3958 emit_src_register(emit
, &zero
);
3959 end_emit_instruction(emit
);
3966 * Emit code for TGSI_OPCODE_LG2 instruction.
3969 emit_lg2(struct svga_shader_emitter_v10
*emit
,
3970 const struct tgsi_full_instruction
*inst
)
3972 /* Note that TGSI_OPCODE_LG2 computes only one value from src.x
3973 * while VGPU10 computes four values.
3976 * dst.xyzw = log2(src.x)
3979 struct tgsi_full_src_register src_xxxx
=
3980 swizzle_src(&inst
->Src
[0], TGSI_SWIZZLE_X
, TGSI_SWIZZLE_X
,
3981 TGSI_SWIZZLE_X
, TGSI_SWIZZLE_X
);
3983 /* LOG tmp, s0.xxxx */
3984 emit_instruction_op1(emit
, VGPU10_OPCODE_LOG
, &inst
->Dst
[0], &src_xxxx
,
3985 inst
->Instruction
.Saturate
);
3992 * Emit code for TGSI_OPCODE_LIT instruction.
3995 emit_lit(struct svga_shader_emitter_v10
*emit
,
3996 const struct tgsi_full_instruction
*inst
)
3998 struct tgsi_full_src_register one
= make_immediate_reg_float(emit
, 1.0f
);
4001 * If dst and src are the same we need to create
4002 * a temporary for it and insert a extra move.
4004 unsigned tmp_move
= get_temp_index(emit
);
4005 struct tgsi_full_src_register move_src
= make_src_temp_reg(tmp_move
);
4006 struct tgsi_full_dst_register move_dst
= make_dst_temp_reg(tmp_move
);
4010 * dst.y = max(src.x, 0)
4011 * dst.z = (src.x > 0) ? max(src.y, 0)^{clamp(src.w, -128, 128))} : 0
4015 /* MOV dst.x, 1.0 */
4016 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
4017 struct tgsi_full_dst_register dst_x
=
4018 writemask_dst(&move_dst
, TGSI_WRITEMASK_X
);
4019 emit_instruction_op1(emit
, VGPU10_OPCODE_MOV
, &dst_x
, &one
, FALSE
);
4022 /* MOV dst.w, 1.0 */
4023 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
4024 struct tgsi_full_dst_register dst_w
=
4025 writemask_dst(&move_dst
, TGSI_WRITEMASK_W
);
4026 emit_instruction_op1(emit
, VGPU10_OPCODE_MOV
, &dst_w
, &one
, FALSE
);
4029 /* MAX dst.y, src.x, 0.0 */
4030 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
4031 struct tgsi_full_dst_register dst_y
=
4032 writemask_dst(&move_dst
, TGSI_WRITEMASK_Y
);
4033 struct tgsi_full_src_register zero
=
4034 make_immediate_reg_float(emit
, 0.0f
);
4035 struct tgsi_full_src_register src_xxxx
=
4036 swizzle_src(&inst
->Src
[0], TGSI_SWIZZLE_X
, TGSI_SWIZZLE_X
,
4037 TGSI_SWIZZLE_X
, TGSI_SWIZZLE_X
);
4039 emit_instruction_op2(emit
, VGPU10_OPCODE_MAX
, &dst_y
, &src_xxxx
,
4040 &zero
, inst
->Instruction
.Saturate
);
4044 * tmp1 = clamp(src.w, -128, 128);
4045 * MAX tmp1, src.w, -128
4046 * MIN tmp1, tmp1, 128
4048 * tmp2 = max(tmp2, 0);
4049 * MAX tmp2, src.y, 0
4051 * tmp1 = pow(tmp2, tmp1);
4053 * MUL tmp1, tmp2, tmp1
4056 * tmp1 = (src.w == 0) ? 1 : tmp1;
4058 * MOVC tmp1, tmp2, 1.0, tmp1
4060 * dst.z = (0 < src.x) ? tmp1 : 0;
4062 * MOVC dst.z, tmp2, tmp1, 0.0
4064 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
4065 struct tgsi_full_dst_register dst_z
=
4066 writemask_dst(&move_dst
, TGSI_WRITEMASK_Z
);
4068 unsigned tmp1
= get_temp_index(emit
);
4069 struct tgsi_full_src_register tmp1_src
= make_src_temp_reg(tmp1
);
4070 struct tgsi_full_dst_register tmp1_dst
= make_dst_temp_reg(tmp1
);
4071 unsigned tmp2
= get_temp_index(emit
);
4072 struct tgsi_full_src_register tmp2_src
= make_src_temp_reg(tmp2
);
4073 struct tgsi_full_dst_register tmp2_dst
= make_dst_temp_reg(tmp2
);
4075 struct tgsi_full_src_register src_xxxx
=
4076 scalar_src(&inst
->Src
[0], TGSI_SWIZZLE_X
);
4077 struct tgsi_full_src_register src_yyyy
=
4078 scalar_src(&inst
->Src
[0], TGSI_SWIZZLE_Y
);
4079 struct tgsi_full_src_register src_wwww
=
4080 scalar_src(&inst
->Src
[0], TGSI_SWIZZLE_W
);
4082 struct tgsi_full_src_register zero
=
4083 make_immediate_reg_float(emit
, 0.0f
);
4084 struct tgsi_full_src_register lowerbound
=
4085 make_immediate_reg_float(emit
, -128.0f
);
4086 struct tgsi_full_src_register upperbound
=
4087 make_immediate_reg_float(emit
, 128.0f
);
4089 emit_instruction_op2(emit
, VGPU10_OPCODE_MAX
, &tmp1_dst
, &src_wwww
,
4090 &lowerbound
, FALSE
);
4091 emit_instruction_op2(emit
, VGPU10_OPCODE_MIN
, &tmp1_dst
, &tmp1_src
,
4092 &upperbound
, FALSE
);
4093 emit_instruction_op2(emit
, VGPU10_OPCODE_MAX
, &tmp2_dst
, &src_yyyy
,
4096 /* POW tmp1, tmp2, tmp1 */
4097 /* LOG tmp2, tmp2 */
4098 emit_instruction_op1(emit
, VGPU10_OPCODE_LOG
, &tmp2_dst
, &tmp2_src
,
4101 /* MUL tmp1, tmp2, tmp1 */
4102 emit_instruction_op2(emit
, VGPU10_OPCODE_MUL
, &tmp1_dst
, &tmp2_src
,
4105 /* EXP tmp1, tmp1 */
4106 emit_instruction_op1(emit
, VGPU10_OPCODE_EXP
, &tmp1_dst
, &tmp1_src
,
4109 /* EQ tmp2, 0, src.w */
4110 emit_instruction_op2(emit
, VGPU10_OPCODE_EQ
, &tmp2_dst
, &zero
,
4112 /* MOVC tmp1.z, tmp2, tmp1, 1.0 */
4113 emit_instruction_op3(emit
, VGPU10_OPCODE_MOVC
, &tmp1_dst
,
4114 &tmp2_src
, &one
, &tmp1_src
, FALSE
);
4116 /* LT tmp2, 0, src.x */
4117 emit_instruction_op2(emit
, VGPU10_OPCODE_LT
, &tmp2_dst
, &zero
,
4119 /* MOVC dst.z, tmp2, tmp1, 0.0 */
4120 emit_instruction_op3(emit
, VGPU10_OPCODE_MOVC
, &dst_z
,
4121 &tmp2_src
, &tmp1_src
, &zero
, FALSE
);
4124 emit_instruction_op1(emit
, VGPU10_OPCODE_MOV
, &inst
->Dst
[0], &move_src
,
4126 free_temp_indexes(emit
);
4133 * Emit code for TGSI_OPCODE_LOG instruction.
4136 emit_log(struct svga_shader_emitter_v10
*emit
,
4137 const struct tgsi_full_instruction
*inst
)
4140 * dst.x = floor(lg2(abs(s0.x)))
4141 * dst.y = abs(s0.x) / (2 ^ floor(lg2(abs(s0.x))))
4142 * dst.z = lg2(abs(s0.x))
4146 struct tgsi_full_src_register src_xxxx
=
4147 scalar_src(&inst
->Src
[0], TGSI_SWIZZLE_X
);
4148 unsigned tmp
= get_temp_index(emit
);
4149 struct tgsi_full_src_register tmp_src
= make_src_temp_reg(tmp
);
4150 struct tgsi_full_dst_register tmp_dst
= make_dst_temp_reg(tmp
);
4151 struct tgsi_full_src_register abs_src_xxxx
= absolute_src(&src_xxxx
);
4153 /* only use X component of temp reg */
4154 tmp_dst
= writemask_dst(&tmp_dst
, TGSI_WRITEMASK_X
);
4155 tmp_src
= scalar_src(&tmp_src
, TGSI_SWIZZLE_X
);
4157 /* LOG tmp.x, abs(s0.x) */
4158 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XYZ
) {
4159 emit_instruction_op1(emit
, VGPU10_OPCODE_LOG
, &tmp_dst
,
4160 &abs_src_xxxx
, FALSE
);
4163 /* MOV dst.z, tmp.x */
4164 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
4165 struct tgsi_full_dst_register dst_z
=
4166 writemask_dst(&inst
->Dst
[0], TGSI_WRITEMASK_Z
);
4168 emit_instruction_op1(emit
, VGPU10_OPCODE_MOV
, &dst_z
,
4169 &tmp_src
, inst
->Instruction
.Saturate
);
4172 /* FLR tmp.x, tmp.x */
4173 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_XY
) {
4174 emit_instruction_op1(emit
, VGPU10_OPCODE_ROUND_NI
, &tmp_dst
,
4178 /* MOV dst.x, tmp.x */
4179 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
4180 struct tgsi_full_dst_register dst_x
=
4181 writemask_dst(&inst
->Dst
[0], TGSI_WRITEMASK_X
);
4183 emit_instruction_op1(emit
, VGPU10_OPCODE_MOV
, &dst_x
, &tmp_src
,
4184 inst
->Instruction
.Saturate
);
4187 /* EXP tmp.x, tmp.x */
4188 /* DIV dst.y, abs(s0.x), tmp.x */
4189 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
4190 struct tgsi_full_dst_register dst_y
=
4191 writemask_dst(&inst
->Dst
[0], TGSI_WRITEMASK_Y
);
4193 emit_instruction_op1(emit
, VGPU10_OPCODE_EXP
, &tmp_dst
, &tmp_src
,
4195 emit_instruction_op2(emit
, VGPU10_OPCODE_DIV
, &dst_y
, &abs_src_xxxx
,
4196 &tmp_src
, inst
->Instruction
.Saturate
);
4199 /* MOV dst.w, 1.0 */
4200 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
4201 struct tgsi_full_dst_register dst_w
=
4202 writemask_dst(&inst
->Dst
[0], TGSI_WRITEMASK_W
);
4203 struct tgsi_full_src_register one
=
4204 make_immediate_reg_float(emit
, 1.0f
);
4206 emit_instruction_op1(emit
, VGPU10_OPCODE_MOV
, &dst_w
, &one
, FALSE
);
4209 free_temp_indexes(emit
);
4216 * Emit code for TGSI_OPCODE_LRP instruction.
4219 emit_lrp(struct svga_shader_emitter_v10
*emit
,
4220 const struct tgsi_full_instruction
*inst
)
4222 /* dst = LRP(s0, s1, s2):
4223 * dst = s0 * (s1 - s2) + s2
4225 * SUB tmp, s1, s2; tmp = s1 - s2
4226 * MAD dst, s0, tmp, s2; dst = s0 * t1 + s2
4228 unsigned tmp
= get_temp_index(emit
);
4229 struct tgsi_full_src_register src_tmp
= make_src_temp_reg(tmp
);
4230 struct tgsi_full_dst_register dst_tmp
= make_dst_temp_reg(tmp
);
4231 struct tgsi_full_src_register neg_src2
= negate_src(&inst
->Src
[2]);
4233 /* ADD tmp, s1, -s2 */
4234 emit_instruction_op2(emit
, VGPU10_OPCODE_ADD
, &dst_tmp
,
4235 &inst
->Src
[1], &neg_src2
, FALSE
);
4237 /* MAD dst, s1, tmp, s3 */
4238 emit_instruction_op3(emit
, VGPU10_OPCODE_MAD
, &inst
->Dst
[0],
4239 &inst
->Src
[0], &src_tmp
, &inst
->Src
[2],
4240 inst
->Instruction
.Saturate
);
4242 free_temp_indexes(emit
);
4249 * Emit code for TGSI_OPCODE_POW instruction.
4252 emit_pow(struct svga_shader_emitter_v10
*emit
,
4253 const struct tgsi_full_instruction
*inst
)
4255 /* Note that TGSI_OPCODE_POW computes only one value from src0.x and
4256 * src1.x while VGPU10 computes four values.
4258 * dst = POW(src0, src1):
4259 * dst.xyzw = src0.x ^ src1.x
4261 unsigned tmp
= get_temp_index(emit
);
4262 struct tgsi_full_src_register tmp_src
= make_src_temp_reg(tmp
);
4263 struct tgsi_full_dst_register tmp_dst
= make_dst_temp_reg(tmp
);
4264 struct tgsi_full_src_register src0_xxxx
=
4265 swizzle_src(&inst
->Src
[0], TGSI_SWIZZLE_X
, TGSI_SWIZZLE_X
,
4266 TGSI_SWIZZLE_X
, TGSI_SWIZZLE_X
);
4267 struct tgsi_full_src_register src1_xxxx
=
4268 swizzle_src(&inst
->Src
[1], TGSI_SWIZZLE_X
, TGSI_SWIZZLE_X
,
4269 TGSI_SWIZZLE_X
, TGSI_SWIZZLE_X
);
4271 /* LOG tmp, s0.xxxx */
4272 emit_instruction_op1(emit
, VGPU10_OPCODE_LOG
, &tmp_dst
, &src0_xxxx
,
4275 /* MUL tmp, tmp, s1.xxxx */
4276 emit_instruction_op2(emit
, VGPU10_OPCODE_MUL
, &tmp_dst
, &tmp_src
,
4279 /* EXP tmp, s0.xxxx */
4280 emit_instruction_op1(emit
, VGPU10_OPCODE_EXP
, &inst
->Dst
[0],
4281 &tmp_src
, inst
->Instruction
.Saturate
);
4284 free_temp_indexes(emit
);
4291 * Emit code for TGSI_OPCODE_RCP (reciprocal) instruction.
4294 emit_rcp(struct svga_shader_emitter_v10
*emit
,
4295 const struct tgsi_full_instruction
*inst
)
4297 struct tgsi_full_src_register one
= make_immediate_reg_float(emit
, 1.0f
);
4299 unsigned tmp
= get_temp_index(emit
);
4300 struct tgsi_full_src_register tmp_src
= make_src_temp_reg(tmp
);
4301 struct tgsi_full_dst_register tmp_dst
= make_dst_temp_reg(tmp
);
4303 struct tgsi_full_dst_register tmp_dst_x
=
4304 writemask_dst(&tmp_dst
, TGSI_WRITEMASK_X
);
4305 struct tgsi_full_src_register tmp_src_xxxx
=
4306 scalar_src(&tmp_src
, TGSI_SWIZZLE_X
);
4308 /* DIV tmp.x, 1.0, s0 */
4309 emit_instruction_op2(emit
, VGPU10_OPCODE_DIV
, &tmp_dst_x
, &one
,
4310 &inst
->Src
[0], FALSE
);
4312 /* MOV dst, tmp.xxxx */
4313 emit_instruction_op1(emit
, VGPU10_OPCODE_MOV
, &inst
->Dst
[0],
4314 &tmp_src_xxxx
, inst
->Instruction
.Saturate
);
4316 free_temp_indexes(emit
);
4323 * Emit code for TGSI_OPCODE_RSQ instruction.
4326 emit_rsq(struct svga_shader_emitter_v10
*emit
,
4327 const struct tgsi_full_instruction
*inst
)
4330 * dst.xyzw = 1 / sqrt(src.x)
4336 unsigned tmp
= get_temp_index(emit
);
4337 struct tgsi_full_src_register tmp_src
= make_src_temp_reg(tmp
);
4338 struct tgsi_full_dst_register tmp_dst
= make_dst_temp_reg(tmp
);
4340 struct tgsi_full_dst_register tmp_dst_x
=
4341 writemask_dst(&tmp_dst
, TGSI_WRITEMASK_X
);
4342 struct tgsi_full_src_register tmp_src_xxxx
=
4343 scalar_src(&tmp_src
, TGSI_SWIZZLE_X
);
4345 /* RSQ tmp, src.x */
4346 emit_instruction_op1(emit
, VGPU10_OPCODE_RSQ
, &tmp_dst_x
,
4347 &inst
->Src
[0], FALSE
);
4349 /* MOV dst, tmp.xxxx */
4350 emit_instruction_op1(emit
, VGPU10_OPCODE_MOV
, &inst
->Dst
[0],
4351 &tmp_src_xxxx
, inst
->Instruction
.Saturate
);
4354 free_temp_indexes(emit
);
4361 * Emit code for TGSI_OPCODE_SCS instruction.
4364 emit_scs(struct svga_shader_emitter_v10
*emit
,
4365 const struct tgsi_full_instruction
*inst
)
4367 /* dst.x = cos(src.x)
4368 * dst.y = sin(src.x)
4372 struct tgsi_full_dst_register dst_x
=
4373 writemask_dst(&inst
->Dst
[0], TGSI_WRITEMASK_X
);
4374 struct tgsi_full_dst_register dst_y
=
4375 writemask_dst(&inst
->Dst
[0], TGSI_WRITEMASK_Y
);
4376 struct tgsi_full_dst_register dst_zw
=
4377 writemask_dst(&inst
->Dst
[0], TGSI_WRITEMASK_ZW
);
4379 struct tgsi_full_src_register zero_one
=
4380 make_immediate_reg_float4(emit
, 0.0f
, 0.0f
, 0.0f
, 1.0f
);
4382 begin_emit_instruction(emit
);
4383 emit_opcode(emit
, VGPU10_OPCODE_SINCOS
, inst
->Instruction
.Saturate
);
4384 emit_dst_register(emit
, &dst_y
);
4385 emit_dst_register(emit
, &dst_x
);
4386 emit_src_register(emit
, &inst
->Src
[0]);
4387 end_emit_instruction(emit
);
4389 emit_instruction_op1(emit
, VGPU10_OPCODE_MOV
,
4390 &dst_zw
, &zero_one
, inst
->Instruction
.Saturate
);
4397 * Emit code for TGSI_OPCODE_SEQ (Set Equal) instruction.
4400 emit_seq(struct svga_shader_emitter_v10
*emit
,
4401 const struct tgsi_full_instruction
*inst
)
4403 /* dst = SEQ(s0, s1):
4404 * dst = s0 == s1 ? 1.0 : 0.0 (per component)
4406 * EQ tmp, s0, s1; tmp = s0 == s1 : 0xffffffff : 0 (per comp)
4407 * MOVC dst, tmp, 1.0, 0.0; dst = tmp ? 1.0 : 0.0 (per component)
4409 unsigned tmp
= get_temp_index(emit
);
4410 struct tgsi_full_src_register tmp_src
= make_src_temp_reg(tmp
);
4411 struct tgsi_full_dst_register tmp_dst
= make_dst_temp_reg(tmp
);
4412 struct tgsi_full_src_register zero
= make_immediate_reg_float(emit
, 0.0f
);
4413 struct tgsi_full_src_register one
= make_immediate_reg_float(emit
, 1.0f
);
4415 /* EQ tmp, s0, s1 */
4416 emit_instruction_op2(emit
, VGPU10_OPCODE_EQ
, &tmp_dst
, &inst
->Src
[0],
4417 &inst
->Src
[1], FALSE
);
4419 /* MOVC dst, tmp, one, zero */
4420 emit_instruction_op3(emit
, VGPU10_OPCODE_MOVC
, &inst
->Dst
[0], &tmp_src
,
4421 &one
, &zero
, FALSE
);
4423 free_temp_indexes(emit
);
4430 * Emit code for TGSI_OPCODE_SGE (Set Greater than or Equal) instruction.
4433 emit_sge(struct svga_shader_emitter_v10
*emit
,
4434 const struct tgsi_full_instruction
*inst
)
4436 /* dst = SGE(s0, s1):
4437 * dst = s0 >= s1 ? 1.0 : 0.0 (per component)
4439 * GE tmp, s0, s1; tmp = s0 >= s1 : 0xffffffff : 0 (per comp)
4440 * MOVC dst, tmp, 1.0, 0.0; dst = tmp ? 1.0 : 0.0 (per component)
4442 unsigned tmp
= get_temp_index(emit
);
4443 struct tgsi_full_src_register tmp_src
= make_src_temp_reg(tmp
);
4444 struct tgsi_full_dst_register tmp_dst
= make_dst_temp_reg(tmp
);
4445 struct tgsi_full_src_register zero
= make_immediate_reg_float(emit
, 0.0f
);
4446 struct tgsi_full_src_register one
= make_immediate_reg_float(emit
, 1.0f
);
4448 /* GE tmp, s0, s1 */
4449 emit_instruction_op2(emit
, VGPU10_OPCODE_GE
, &tmp_dst
, &inst
->Src
[0],
4450 &inst
->Src
[1], FALSE
);
4452 /* MOVC dst, tmp, one, zero */
4453 emit_instruction_op3(emit
, VGPU10_OPCODE_MOVC
, &inst
->Dst
[0], &tmp_src
,
4454 &one
, &zero
, FALSE
);
4456 free_temp_indexes(emit
);
4463 * Emit code for TGSI_OPCODE_SGT (Set Greater than) instruction.
4466 emit_sgt(struct svga_shader_emitter_v10
*emit
,
4467 const struct tgsi_full_instruction
*inst
)
4469 /* dst = SGT(s0, s1):
4470 * dst = s0 > s1 ? 1.0 : 0.0 (per component)
4472 * LT tmp, s1, s0; tmp = s1 < s0 ? 0xffffffff : 0 (per comp)
4473 * MOVC dst, tmp, 1.0, 0.0; dst = tmp ? 1.0 : 0.0 (per component)
4475 unsigned tmp
= get_temp_index(emit
);
4476 struct tgsi_full_src_register tmp_src
= make_src_temp_reg(tmp
);
4477 struct tgsi_full_dst_register tmp_dst
= make_dst_temp_reg(tmp
);
4478 struct tgsi_full_src_register zero
= make_immediate_reg_float(emit
, 0.0f
);
4479 struct tgsi_full_src_register one
= make_immediate_reg_float(emit
, 1.0f
);
4481 /* LT tmp, s1, s0 */
4482 emit_instruction_op2(emit
, VGPU10_OPCODE_LT
, &tmp_dst
, &inst
->Src
[1],
4483 &inst
->Src
[0], FALSE
);
4485 /* MOVC dst, tmp, one, zero */
4486 emit_instruction_op3(emit
, VGPU10_OPCODE_MOVC
, &inst
->Dst
[0], &tmp_src
,
4487 &one
, &zero
, FALSE
);
4489 free_temp_indexes(emit
);
4496 * Emit code for TGSI_OPCODE_SIN and TGSI_OPCODE_COS instructions.
4499 emit_sincos(struct svga_shader_emitter_v10
*emit
,
4500 const struct tgsi_full_instruction
*inst
)
4502 unsigned tmp
= get_temp_index(emit
);
4503 struct tgsi_full_src_register tmp_src
= make_src_temp_reg(tmp
);
4504 struct tgsi_full_dst_register tmp_dst
= make_dst_temp_reg(tmp
);
4506 struct tgsi_full_src_register tmp_src_xxxx
=
4507 scalar_src(&tmp_src
, TGSI_SWIZZLE_X
);
4508 struct tgsi_full_dst_register tmp_dst_x
=
4509 writemask_dst(&tmp_dst
, TGSI_WRITEMASK_X
);
4511 begin_emit_instruction(emit
);
4512 emit_opcode(emit
, VGPU10_OPCODE_SINCOS
, FALSE
);
4514 if(inst
->Instruction
.Opcode
== TGSI_OPCODE_SIN
)
4516 emit_dst_register(emit
, &tmp_dst_x
); /* first destination register */
4517 emit_null_dst_register(emit
); /* second destination register */
4520 emit_null_dst_register(emit
);
4521 emit_dst_register(emit
, &tmp_dst_x
);
4524 emit_src_register(emit
, &inst
->Src
[0]);
4525 end_emit_instruction(emit
);
4527 emit_instruction_op1(emit
, VGPU10_OPCODE_MOV
, &inst
->Dst
[0],
4528 &tmp_src_xxxx
, inst
->Instruction
.Saturate
);
4530 free_temp_indexes(emit
);
4537 * Emit code for TGSI_OPCODE_SLE (Set Less than or Equal) instruction.
4540 emit_sle(struct svga_shader_emitter_v10
*emit
,
4541 const struct tgsi_full_instruction
*inst
)
4543 /* dst = SLE(s0, s1):
4544 * dst = s0 <= s1 ? 1.0 : 0.0 (per component)
4546 * GE tmp, s1, s0; tmp = s1 >= s0 : 0xffffffff : 0 (per comp)
4547 * MOVC dst, tmp, 1.0, 0.0; dst = tmp ? 1.0 : 0.0 (per component)
4549 unsigned tmp
= get_temp_index(emit
);
4550 struct tgsi_full_src_register tmp_src
= make_src_temp_reg(tmp
);
4551 struct tgsi_full_dst_register tmp_dst
= make_dst_temp_reg(tmp
);
4552 struct tgsi_full_src_register zero
= make_immediate_reg_float(emit
, 0.0f
);
4553 struct tgsi_full_src_register one
= make_immediate_reg_float(emit
, 1.0f
);
4555 /* GE tmp, s1, s0 */
4556 emit_instruction_op2(emit
, VGPU10_OPCODE_GE
, &tmp_dst
, &inst
->Src
[1],
4557 &inst
->Src
[0], FALSE
);
4559 /* MOVC dst, tmp, one, zero */
4560 emit_instruction_op3(emit
, VGPU10_OPCODE_MOVC
, &inst
->Dst
[0], &tmp_src
,
4561 &one
, &zero
, FALSE
);
4563 free_temp_indexes(emit
);
4570 * Emit code for TGSI_OPCODE_SLT (Set Less than) instruction.
4573 emit_slt(struct svga_shader_emitter_v10
*emit
,
4574 const struct tgsi_full_instruction
*inst
)
4576 /* dst = SLT(s0, s1):
4577 * dst = s0 < s1 ? 1.0 : 0.0 (per component)
4579 * LT tmp, s0, s1; tmp = s0 < s1 ? 0xffffffff : 0 (per comp)
4580 * MOVC dst, tmp, 1.0, 0.0; dst = tmp ? 1.0 : 0.0 (per component)
4582 unsigned tmp
= get_temp_index(emit
);
4583 struct tgsi_full_src_register tmp_src
= make_src_temp_reg(tmp
);
4584 struct tgsi_full_dst_register tmp_dst
= make_dst_temp_reg(tmp
);
4585 struct tgsi_full_src_register zero
= make_immediate_reg_float(emit
, 0.0f
);
4586 struct tgsi_full_src_register one
= make_immediate_reg_float(emit
, 1.0f
);
4588 /* LT tmp, s0, s1 */
4589 emit_instruction_op2(emit
, VGPU10_OPCODE_LT
, &tmp_dst
, &inst
->Src
[0],
4590 &inst
->Src
[1], FALSE
);
4592 /* MOVC dst, tmp, one, zero */
4593 emit_instruction_op3(emit
, VGPU10_OPCODE_MOVC
, &inst
->Dst
[0], &tmp_src
,
4594 &one
, &zero
, FALSE
);
4596 free_temp_indexes(emit
);
4603 * Emit code for TGSI_OPCODE_SNE (Set Not Equal) instruction.
4606 emit_sne(struct svga_shader_emitter_v10
*emit
,
4607 const struct tgsi_full_instruction
*inst
)
4609 /* dst = SNE(s0, s1):
4610 * dst = s0 != s1 ? 1.0 : 0.0 (per component)
4612 * EQ tmp, s0, s1; tmp = s0 == s1 : 0xffffffff : 0 (per comp)
4613 * MOVC dst, tmp, 1.0, 0.0; dst = tmp ? 1.0 : 0.0 (per component)
4615 unsigned tmp
= get_temp_index(emit
);
4616 struct tgsi_full_src_register tmp_src
= make_src_temp_reg(tmp
);
4617 struct tgsi_full_dst_register tmp_dst
= make_dst_temp_reg(tmp
);
4618 struct tgsi_full_src_register zero
= make_immediate_reg_float(emit
, 0.0f
);
4619 struct tgsi_full_src_register one
= make_immediate_reg_float(emit
, 1.0f
);
4621 /* NE tmp, s0, s1 */
4622 emit_instruction_op2(emit
, VGPU10_OPCODE_NE
, &tmp_dst
, &inst
->Src
[0],
4623 &inst
->Src
[1], FALSE
);
4625 /* MOVC dst, tmp, one, zero */
4626 emit_instruction_op3(emit
, VGPU10_OPCODE_MOVC
, &inst
->Dst
[0], &tmp_src
,
4627 &one
, &zero
, FALSE
);
4629 free_temp_indexes(emit
);
4636 * Emit code for TGSI_OPCODE_SSG (Set Sign) instruction.
4639 emit_ssg(struct svga_shader_emitter_v10
*emit
,
4640 const struct tgsi_full_instruction
*inst
)
4642 /* dst.x = (src.x > 0.0) ? 1.0 : (src.x < 0.0) ? -1.0 : 0.0
4643 * dst.y = (src.y > 0.0) ? 1.0 : (src.y < 0.0) ? -1.0 : 0.0
4644 * dst.z = (src.z > 0.0) ? 1.0 : (src.z < 0.0) ? -1.0 : 0.0
4645 * dst.w = (src.w > 0.0) ? 1.0 : (src.w < 0.0) ? -1.0 : 0.0
4647 * LT tmp1, src, zero; tmp1 = src < zero ? 0xffffffff : 0 (per comp)
4648 * MOVC tmp2, tmp1, -1.0, 0.0; tmp2 = tmp1 ? -1.0 : 0.0 (per component)
4649 * LT tmp1, zero, src; tmp1 = zero < src ? 0xffffffff : 0 (per comp)
4650 * MOVC dst, tmp1, 1.0, tmp2; dst = tmp1 ? 1.0 : tmp2 (per component)
4652 struct tgsi_full_src_register zero
=
4653 make_immediate_reg_float(emit
, 0.0f
);
4654 struct tgsi_full_src_register one
=
4655 make_immediate_reg_float(emit
, 1.0f
);
4656 struct tgsi_full_src_register neg_one
=
4657 make_immediate_reg_float(emit
, -1.0f
);
4659 unsigned tmp1
= get_temp_index(emit
);
4660 struct tgsi_full_src_register tmp1_src
= make_src_temp_reg(tmp1
);
4661 struct tgsi_full_dst_register tmp1_dst
= make_dst_temp_reg(tmp1
);
4663 unsigned tmp2
= get_temp_index(emit
);
4664 struct tgsi_full_src_register tmp2_src
= make_src_temp_reg(tmp2
);
4665 struct tgsi_full_dst_register tmp2_dst
= make_dst_temp_reg(tmp2
);
4667 emit_instruction_op2(emit
, VGPU10_OPCODE_LT
, &tmp1_dst
, &inst
->Src
[0],
4669 emit_instruction_op3(emit
, VGPU10_OPCODE_MOVC
, &tmp2_dst
, &tmp1_src
,
4670 &neg_one
, &zero
, FALSE
);
4671 emit_instruction_op2(emit
, VGPU10_OPCODE_LT
, &tmp1_dst
, &zero
,
4672 &inst
->Src
[0], FALSE
);
4673 emit_instruction_op3(emit
, VGPU10_OPCODE_MOVC
, &inst
->Dst
[0], &tmp1_src
,
4674 &one
, &tmp2_src
, FALSE
);
4676 free_temp_indexes(emit
);
4683 * Emit code for TGSI_OPCODE_ISSG (Integer Set Sign) instruction.
4686 emit_issg(struct svga_shader_emitter_v10
*emit
,
4687 const struct tgsi_full_instruction
*inst
)
4689 /* dst.x = (src.x > 0) ? 1 : (src.x < 0) ? -1 : 0
4690 * dst.y = (src.y > 0) ? 1 : (src.y < 0) ? -1 : 0
4691 * dst.z = (src.z > 0) ? 1 : (src.z < 0) ? -1 : 0
4692 * dst.w = (src.w > 0) ? 1 : (src.w < 0) ? -1 : 0
4694 * ILT tmp1, src, 0 tmp1 = src < 0 ? -1 : 0 (per component)
4695 * ILT tmp2, 0, src tmp2 = 0 < src ? -1 : 0 (per component)
4696 * IADD dst, tmp1, neg(tmp2) dst = tmp1 - tmp2 (per component)
4698 struct tgsi_full_src_register zero
= make_immediate_reg_float(emit
, 0.0f
);
4700 unsigned tmp1
= get_temp_index(emit
);
4701 struct tgsi_full_src_register tmp1_src
= make_src_temp_reg(tmp1
);
4702 struct tgsi_full_dst_register tmp1_dst
= make_dst_temp_reg(tmp1
);
4704 unsigned tmp2
= get_temp_index(emit
);
4705 struct tgsi_full_src_register tmp2_src
= make_src_temp_reg(tmp2
);
4706 struct tgsi_full_dst_register tmp2_dst
= make_dst_temp_reg(tmp2
);
4708 struct tgsi_full_src_register neg_tmp2
= negate_src(&tmp2_src
);
4710 emit_instruction_op2(emit
, VGPU10_OPCODE_ILT
, &tmp1_dst
,
4711 &inst
->Src
[0], &zero
, FALSE
);
4712 emit_instruction_op2(emit
, VGPU10_OPCODE_ILT
, &tmp2_dst
,
4713 &zero
, &inst
->Src
[0], FALSE
);
4714 emit_instruction_op2(emit
, VGPU10_OPCODE_IADD
, &inst
->Dst
[0],
4715 &tmp1_src
, &neg_tmp2
, FALSE
);
4717 free_temp_indexes(emit
);
4724 * Emit a comparison instruction. The dest register will get
4725 * 0 or ~0 values depending on the outcome of comparing src0 to src1.
4728 emit_comparison(struct svga_shader_emitter_v10
*emit
,
4730 const struct tgsi_full_dst_register
*dst
,
4731 const struct tgsi_full_src_register
*src0
,
4732 const struct tgsi_full_src_register
*src1
)
4734 struct tgsi_full_src_register immediate
;
4735 VGPU10OpcodeToken0 opcode0
;
4736 boolean swapSrc
= FALSE
;
4738 /* Sanity checks for svga vs. gallium enums */
4739 STATIC_ASSERT(SVGA3D_CMP_LESS
== (PIPE_FUNC_LESS
+ 1));
4740 STATIC_ASSERT(SVGA3D_CMP_GREATEREQUAL
== (PIPE_FUNC_GEQUAL
+ 1));
4745 case SVGA3D_CMP_NEVER
:
4746 immediate
= make_immediate_reg_int(emit
, 0);
4748 begin_emit_instruction(emit
);
4749 emit_dword(emit
, VGPU10_OPCODE_MOV
);
4750 emit_dst_register(emit
, dst
);
4751 emit_src_register(emit
, &immediate
);
4752 end_emit_instruction(emit
);
4754 case SVGA3D_CMP_ALWAYS
:
4755 immediate
= make_immediate_reg_int(emit
, -1);
4757 begin_emit_instruction(emit
);
4758 emit_dword(emit
, VGPU10_OPCODE_MOV
);
4759 emit_dst_register(emit
, dst
);
4760 emit_src_register(emit
, &immediate
);
4761 end_emit_instruction(emit
);
4763 case SVGA3D_CMP_LESS
:
4764 opcode0
.opcodeType
= VGPU10_OPCODE_LT
;
4766 case SVGA3D_CMP_EQUAL
:
4767 opcode0
.opcodeType
= VGPU10_OPCODE_EQ
;
4769 case SVGA3D_CMP_LESSEQUAL
:
4770 opcode0
.opcodeType
= VGPU10_OPCODE_GE
;
4773 case SVGA3D_CMP_GREATER
:
4774 opcode0
.opcodeType
= VGPU10_OPCODE_LT
;
4777 case SVGA3D_CMP_NOTEQUAL
:
4778 opcode0
.opcodeType
= VGPU10_OPCODE_NE
;
4780 case SVGA3D_CMP_GREATEREQUAL
:
4781 opcode0
.opcodeType
= VGPU10_OPCODE_GE
;
4784 assert(!"Unexpected comparison mode");
4785 opcode0
.opcodeType
= VGPU10_OPCODE_EQ
;
4788 begin_emit_instruction(emit
);
4789 emit_dword(emit
, opcode0
.value
);
4790 emit_dst_register(emit
, dst
);
4792 emit_src_register(emit
, src1
);
4793 emit_src_register(emit
, src0
);
4796 emit_src_register(emit
, src0
);
4797 emit_src_register(emit
, src1
);
4799 end_emit_instruction(emit
);
4804 * Get texel/address offsets for a texture instruction.
4807 get_texel_offsets(const struct svga_shader_emitter_v10
*emit
,
4808 const struct tgsi_full_instruction
*inst
, int offsets
[3])
4810 if (inst
->Texture
.NumOffsets
== 1) {
4811 /* According to OpenGL Shader Language spec the offsets are only
4812 * fetched from a previously-declared immediate/literal.
4814 const struct tgsi_texture_offset
*off
= inst
->TexOffsets
;
4815 const unsigned index
= off
[0].Index
;
4816 const unsigned swizzleX
= off
[0].SwizzleX
;
4817 const unsigned swizzleY
= off
[0].SwizzleY
;
4818 const unsigned swizzleZ
= off
[0].SwizzleZ
;
4819 const union tgsi_immediate_data
*imm
= emit
->immediates
[index
];
4821 assert(inst
->TexOffsets
[0].File
== TGSI_FILE_IMMEDIATE
);
4823 offsets
[0] = imm
[swizzleX
].Int
;
4824 offsets
[1] = imm
[swizzleY
].Int
;
4825 offsets
[2] = imm
[swizzleZ
].Int
;
4828 offsets
[0] = offsets
[1] = offsets
[2] = 0;
4834 * Set up the coordinate register for texture sampling.
4835 * When we're sampling from a RECT texture we have to scale the
4836 * unnormalized coordinate to a normalized coordinate.
4837 * We do that by multiplying the coordinate by an "extra" constant.
4838 * An alternative would be to use the RESINFO instruction to query the
4841 static struct tgsi_full_src_register
4842 setup_texcoord(struct svga_shader_emitter_v10
*emit
,
4844 const struct tgsi_full_src_register
*coord
)
4846 if (emit
->key
.tex
[unit
].unnormalized
) {
4847 unsigned scale_index
= emit
->texcoord_scale_index
[unit
];
4848 unsigned tmp
= get_temp_index(emit
);
4849 struct tgsi_full_src_register tmp_src
= make_src_temp_reg(tmp
);
4850 struct tgsi_full_dst_register tmp_dst
= make_dst_temp_reg(tmp
);
4851 struct tgsi_full_src_register scale_src
= make_src_const_reg(scale_index
);
4853 /* MUL tmp, coord, const[] */
4854 emit_instruction_op2(emit
, VGPU10_OPCODE_MUL
, &tmp_dst
,
4855 coord
, &scale_src
, FALSE
);
4859 /* use texcoord as-is */
4866 * For SAMPLE_C instructions, emit the extra src register which indicates
4867 * the reference/comparision value.
4870 emit_tex_compare_refcoord(struct svga_shader_emitter_v10
*emit
,
4871 enum tgsi_texture_type target
,
4872 const struct tgsi_full_src_register
*coord
)
4874 struct tgsi_full_src_register coord_src_ref
;
4877 assert(tgsi_is_shadow_target(target
));
4879 assert(target
!= TGSI_TEXTURE_SHADOWCUBE_ARRAY
); /* XXX not implemented */
4880 if (target
== TGSI_TEXTURE_SHADOW2D_ARRAY
||
4881 target
== TGSI_TEXTURE_SHADOWCUBE
)
4882 component
= TGSI_SWIZZLE_W
;
4884 component
= TGSI_SWIZZLE_Z
;
4886 coord_src_ref
= scalar_src(coord
, component
);
4888 emit_src_register(emit
, &coord_src_ref
);
4893 * Info for implementing texture swizzles.
4894 * The begin_tex_swizzle(), get_tex_swizzle_dst() and end_tex_swizzle()
4895 * functions use this to encapsulate the extra steps needed to perform
4896 * a texture swizzle, or shadow/depth comparisons.
4897 * The shadow/depth comparison is only done here if for the cases where
4898 * there's no VGPU10 opcode (like texture bias lookup w/ shadow compare).
4900 struct tex_swizzle_info
4903 boolean shadow_compare
;
4905 enum tgsi_texture_type texture_target
; /**< TGSI_TEXTURE_x */
4906 struct tgsi_full_src_register tmp_src
;
4907 struct tgsi_full_dst_register tmp_dst
;
4908 const struct tgsi_full_dst_register
*inst_dst
;
4909 const struct tgsi_full_src_register
*coord_src
;
4914 * Do setup for handling texture swizzles or shadow compares.
4915 * \param unit the texture unit
4916 * \param inst the TGSI texture instruction
4917 * \param shadow_compare do shadow/depth comparison?
4918 * \param swz returns the swizzle info
4921 begin_tex_swizzle(struct svga_shader_emitter_v10
*emit
,
4923 const struct tgsi_full_instruction
*inst
,
4924 boolean shadow_compare
,
4925 struct tex_swizzle_info
*swz
)
4927 swz
->swizzled
= (emit
->key
.tex
[unit
].swizzle_r
!= TGSI_SWIZZLE_X
||
4928 emit
->key
.tex
[unit
].swizzle_g
!= TGSI_SWIZZLE_Y
||
4929 emit
->key
.tex
[unit
].swizzle_b
!= TGSI_SWIZZLE_Z
||
4930 emit
->key
.tex
[unit
].swizzle_a
!= TGSI_SWIZZLE_W
);
4932 swz
->shadow_compare
= shadow_compare
;
4933 swz
->texture_target
= inst
->Texture
.Texture
;
4935 if (swz
->swizzled
|| shadow_compare
) {
4936 /* Allocate temp register for the result of the SAMPLE instruction
4937 * and the source of the MOV/compare/swizzle instructions.
4939 unsigned tmp
= get_temp_index(emit
);
4940 swz
->tmp_src
= make_src_temp_reg(tmp
);
4941 swz
->tmp_dst
= make_dst_temp_reg(tmp
);
4945 swz
->inst_dst
= &inst
->Dst
[0];
4946 swz
->coord_src
= &inst
->Src
[0];
4951 * Returns the register to put the SAMPLE instruction results into.
4952 * This will either be the original instruction dst reg (if no swizzle
4953 * and no shadow comparison) or a temporary reg if there is a swizzle.
4955 static const struct tgsi_full_dst_register
*
4956 get_tex_swizzle_dst(const struct tex_swizzle_info
*swz
)
4958 return (swz
->swizzled
|| swz
->shadow_compare
)
4959 ? &swz
->tmp_dst
: swz
->inst_dst
;
4964 * This emits the MOV instruction that actually implements a texture swizzle
4965 * and/or shadow comparison.
4968 end_tex_swizzle(struct svga_shader_emitter_v10
*emit
,
4969 const struct tex_swizzle_info
*swz
)
4971 if (swz
->shadow_compare
) {
4972 /* Emit extra instructions to compare the fetched texel value against
4973 * a texture coordinate component. The result of the comparison
4976 struct tgsi_full_src_register coord_src
;
4977 struct tgsi_full_src_register texel_src
=
4978 scalar_src(&swz
->tmp_src
, TGSI_SWIZZLE_X
);
4979 struct tgsi_full_src_register one
=
4980 make_immediate_reg_float(emit
, 1.0f
);
4981 /* convert gallium comparison func to SVGA comparison func */
4982 SVGA3dCmpFunc compare_func
= emit
->key
.tex
[swz
->unit
].compare_func
+ 1;
4984 assert(emit
->unit
== PIPE_SHADER_FRAGMENT
);
4986 switch (swz
->texture_target
) {
4987 case TGSI_TEXTURE_SHADOW2D
:
4988 case TGSI_TEXTURE_SHADOWRECT
:
4989 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
4990 coord_src
= scalar_src(swz
->coord_src
, TGSI_SWIZZLE_Z
);
4992 case TGSI_TEXTURE_SHADOW1D
:
4993 coord_src
= scalar_src(swz
->coord_src
, TGSI_SWIZZLE_Y
);
4995 case TGSI_TEXTURE_SHADOWCUBE
:
4996 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
4997 coord_src
= scalar_src(swz
->coord_src
, TGSI_SWIZZLE_W
);
5000 assert(!"Unexpected texture target in end_tex_swizzle()");
5001 coord_src
= scalar_src(swz
->coord_src
, TGSI_SWIZZLE_Z
);
5004 /* COMPARE tmp, coord, texel */
5005 /* XXX it would seem that the texel and coord arguments should
5006 * be transposed here, but piglit tests indicate otherwise.
5008 emit_comparison(emit
, compare_func
,
5009 &swz
->tmp_dst
, &texel_src
, &coord_src
);
5011 /* AND dest, tmp, {1.0} */
5012 begin_emit_instruction(emit
);
5013 emit_opcode(emit
, VGPU10_OPCODE_AND
, FALSE
);
5014 if (swz
->swizzled
) {
5015 emit_dst_register(emit
, &swz
->tmp_dst
);
5018 emit_dst_register(emit
, swz
->inst_dst
);
5020 emit_src_register(emit
, &swz
->tmp_src
);
5021 emit_src_register(emit
, &one
);
5022 end_emit_instruction(emit
);
5025 if (swz
->swizzled
) {
5026 unsigned swz_r
= emit
->key
.tex
[swz
->unit
].swizzle_r
;
5027 unsigned swz_g
= emit
->key
.tex
[swz
->unit
].swizzle_g
;
5028 unsigned swz_b
= emit
->key
.tex
[swz
->unit
].swizzle_b
;
5029 unsigned swz_a
= emit
->key
.tex
[swz
->unit
].swizzle_a
;
5030 unsigned writemask_0
= 0, writemask_1
= 0;
5031 boolean int_tex
= is_integer_type(emit
->sampler_return_type
[swz
->unit
]);
5033 /* Swizzle w/out zero/one terms */
5034 struct tgsi_full_src_register src_swizzled
=
5035 swizzle_src(&swz
->tmp_src
,
5036 swz_r
< PIPE_SWIZZLE_0
? swz_r
: PIPE_SWIZZLE_X
,
5037 swz_g
< PIPE_SWIZZLE_0
? swz_g
: PIPE_SWIZZLE_Y
,
5038 swz_b
< PIPE_SWIZZLE_0
? swz_b
: PIPE_SWIZZLE_Z
,
5039 swz_a
< PIPE_SWIZZLE_0
? swz_a
: PIPE_SWIZZLE_W
);
5041 /* MOV dst, color(tmp).<swizzle> */
5042 emit_instruction_op1(emit
, VGPU10_OPCODE_MOV
,
5043 swz
->inst_dst
, &src_swizzled
, FALSE
);
5045 /* handle swizzle zero terms */
5046 writemask_0
= (((swz_r
== PIPE_SWIZZLE_0
) << 0) |
5047 ((swz_g
== PIPE_SWIZZLE_0
) << 1) |
5048 ((swz_b
== PIPE_SWIZZLE_0
) << 2) |
5049 ((swz_a
== PIPE_SWIZZLE_0
) << 3));
5050 writemask_0
&= swz
->inst_dst
->Register
.WriteMask
;
5053 struct tgsi_full_src_register zero
= int_tex
?
5054 make_immediate_reg_int(emit
, 0) :
5055 make_immediate_reg_float(emit
, 0.0f
);
5056 struct tgsi_full_dst_register dst
=
5057 writemask_dst(swz
->inst_dst
, writemask_0
);
5059 /* MOV dst.writemask_0, {0,0,0,0} */
5060 emit_instruction_op1(emit
, VGPU10_OPCODE_MOV
,
5061 &dst
, &zero
, FALSE
);
5064 /* handle swizzle one terms */
5065 writemask_1
= (((swz_r
== PIPE_SWIZZLE_1
) << 0) |
5066 ((swz_g
== PIPE_SWIZZLE_1
) << 1) |
5067 ((swz_b
== PIPE_SWIZZLE_1
) << 2) |
5068 ((swz_a
== PIPE_SWIZZLE_1
) << 3));
5069 writemask_1
&= swz
->inst_dst
->Register
.WriteMask
;
5072 struct tgsi_full_src_register one
= int_tex
?
5073 make_immediate_reg_int(emit
, 1) :
5074 make_immediate_reg_float(emit
, 1.0f
);
5075 struct tgsi_full_dst_register dst
=
5076 writemask_dst(swz
->inst_dst
, writemask_1
);
5078 /* MOV dst.writemask_1, {1,1,1,1} */
5079 emit_instruction_op1(emit
, VGPU10_OPCODE_MOV
, &dst
, &one
, FALSE
);
5086 * Emit code for TGSI_OPCODE_SAMPLE instruction.
5089 emit_sample(struct svga_shader_emitter_v10
*emit
,
5090 const struct tgsi_full_instruction
*inst
)
5092 const unsigned resource_unit
= inst
->Src
[1].Register
.Index
;
5093 const unsigned sampler_unit
= inst
->Src
[2].Register
.Index
;
5094 struct tgsi_full_src_register coord
;
5096 struct tex_swizzle_info swz_info
;
5098 begin_tex_swizzle(emit
, sampler_unit
, inst
, FALSE
, &swz_info
);
5100 get_texel_offsets(emit
, inst
, offsets
);
5102 coord
= setup_texcoord(emit
, resource_unit
, &inst
->Src
[0]);
5104 /* SAMPLE dst, coord(s0), resource, sampler */
5105 begin_emit_instruction(emit
);
5107 /* NOTE: for non-fragment shaders, we should use VGPU10_OPCODE_SAMPLE_L
5108 * with LOD=0. But our virtual GPU accepts this as-is.
5110 emit_sample_opcode(emit
, VGPU10_OPCODE_SAMPLE
,
5111 inst
->Instruction
.Saturate
, offsets
);
5112 emit_dst_register(emit
, get_tex_swizzle_dst(&swz_info
));
5113 emit_src_register(emit
, &coord
);
5114 emit_resource_register(emit
, resource_unit
);
5115 emit_sampler_register(emit
, sampler_unit
);
5116 end_emit_instruction(emit
);
5118 end_tex_swizzle(emit
, &swz_info
);
5120 free_temp_indexes(emit
);
5127 * Check if a texture instruction is valid.
5128 * An example of an invalid texture instruction is doing shadow comparison
5129 * with an integer-valued texture.
5130 * If we detect an invalid texture instruction, we replace it with:
5131 * MOV dst, {1,1,1,1};
5132 * \return TRUE if valid, FALSE if invalid.
5135 is_valid_tex_instruction(struct svga_shader_emitter_v10
*emit
,
5136 const struct tgsi_full_instruction
*inst
)
5138 const unsigned unit
= inst
->Src
[1].Register
.Index
;
5139 const unsigned target
= inst
->Texture
.Texture
;
5140 boolean valid
= TRUE
;
5142 if (tgsi_is_shadow_target(target
) &&
5143 is_integer_type(emit
->sampler_return_type
[unit
])) {
5144 debug_printf("Invalid SAMPLE_C with an integer texture!\n");
5147 /* XXX might check for other conditions in the future here */
5150 /* emit a MOV dst, {1,1,1,1} instruction. */
5151 struct tgsi_full_src_register one
= make_immediate_reg_float(emit
, 1.0f
);
5152 begin_emit_instruction(emit
);
5153 emit_opcode(emit
, VGPU10_OPCODE_MOV
, FALSE
);
5154 emit_dst_register(emit
, &inst
->Dst
[0]);
5155 emit_src_register(emit
, &one
);
5156 end_emit_instruction(emit
);
5164 * Emit code for TGSI_OPCODE_TEX (simple texture lookup)
5167 emit_tex(struct svga_shader_emitter_v10
*emit
,
5168 const struct tgsi_full_instruction
*inst
)
5170 const uint unit
= inst
->Src
[1].Register
.Index
;
5171 unsigned target
= inst
->Texture
.Texture
;
5173 struct tgsi_full_src_register coord
;
5175 struct tex_swizzle_info swz_info
;
5177 /* check that the sampler returns a float */
5178 if (!is_valid_tex_instruction(emit
, inst
))
5181 begin_tex_swizzle(emit
, unit
, inst
, FALSE
, &swz_info
);
5183 get_texel_offsets(emit
, inst
, offsets
);
5185 coord
= setup_texcoord(emit
, unit
, &inst
->Src
[0]);
5187 /* SAMPLE dst, coord(s0), resource, sampler */
5188 begin_emit_instruction(emit
);
5190 if (tgsi_is_shadow_target(target
))
5191 opcode
= VGPU10_OPCODE_SAMPLE_C
;
5193 opcode
= VGPU10_OPCODE_SAMPLE
;
5195 emit_sample_opcode(emit
, opcode
, inst
->Instruction
.Saturate
, offsets
);
5196 emit_dst_register(emit
, get_tex_swizzle_dst(&swz_info
));
5197 emit_src_register(emit
, &coord
);
5198 emit_resource_register(emit
, unit
);
5199 emit_sampler_register(emit
, unit
);
5200 if (opcode
== VGPU10_OPCODE_SAMPLE_C
) {
5201 emit_tex_compare_refcoord(emit
, target
, &coord
);
5203 end_emit_instruction(emit
);
5205 end_tex_swizzle(emit
, &swz_info
);
5207 free_temp_indexes(emit
);
5214 * Emit code for TGSI_OPCODE_TXP (projective texture)
5217 emit_txp(struct svga_shader_emitter_v10
*emit
,
5218 const struct tgsi_full_instruction
*inst
)
5220 const uint unit
= inst
->Src
[1].Register
.Index
;
5221 unsigned target
= inst
->Texture
.Texture
;
5224 unsigned tmp
= get_temp_index(emit
);
5225 struct tgsi_full_src_register tmp_src
= make_src_temp_reg(tmp
);
5226 struct tgsi_full_dst_register tmp_dst
= make_dst_temp_reg(tmp
);
5227 struct tgsi_full_src_register src0_wwww
=
5228 scalar_src(&inst
->Src
[0], TGSI_SWIZZLE_W
);
5229 struct tgsi_full_src_register coord
;
5230 struct tex_swizzle_info swz_info
;
5232 /* check that the sampler returns a float */
5233 if (!is_valid_tex_instruction(emit
, inst
))
5236 begin_tex_swizzle(emit
, unit
, inst
, FALSE
, &swz_info
);
5238 get_texel_offsets(emit
, inst
, offsets
);
5240 coord
= setup_texcoord(emit
, unit
, &inst
->Src
[0]);
5242 /* DIV tmp, coord, coord.wwww */
5243 emit_instruction_op2(emit
, VGPU10_OPCODE_DIV
, &tmp_dst
,
5244 &coord
, &src0_wwww
, FALSE
);
5246 /* SAMPLE dst, coord(tmp), resource, sampler */
5247 begin_emit_instruction(emit
);
5249 if (tgsi_is_shadow_target(target
))
5250 /* NOTE: for non-fragment shaders, we should use
5251 * VGPU10_OPCODE_SAMPLE_C_LZ, but our virtual GPU accepts this as-is.
5253 opcode
= VGPU10_OPCODE_SAMPLE_C
;
5255 opcode
= VGPU10_OPCODE_SAMPLE
;
5257 emit_sample_opcode(emit
, opcode
, inst
->Instruction
.Saturate
, offsets
);
5258 emit_dst_register(emit
, get_tex_swizzle_dst(&swz_info
));
5259 emit_src_register(emit
, &tmp_src
); /* projected coord */
5260 emit_resource_register(emit
, unit
);
5261 emit_sampler_register(emit
, unit
);
5262 if (opcode
== VGPU10_OPCODE_SAMPLE_C
) {
5263 emit_tex_compare_refcoord(emit
, target
, &tmp_src
);
5265 end_emit_instruction(emit
);
5267 end_tex_swizzle(emit
, &swz_info
);
5269 free_temp_indexes(emit
);
5276 * Emit code for TGSI_OPCODE_XPD instruction.
5279 emit_xpd(struct svga_shader_emitter_v10
*emit
,
5280 const struct tgsi_full_instruction
*inst
)
5282 /* dst.x = src0.y * src1.z - src1.y * src0.z
5283 * dst.y = src0.z * src1.x - src1.z * src0.x
5284 * dst.z = src0.x * src1.y - src1.x * src0.y
5287 struct tgsi_full_src_register s0_xxxx
=
5288 scalar_src(&inst
->Src
[0], TGSI_SWIZZLE_X
);
5289 struct tgsi_full_src_register s0_yyyy
=
5290 scalar_src(&inst
->Src
[0], TGSI_SWIZZLE_Y
);
5291 struct tgsi_full_src_register s0_zzzz
=
5292 scalar_src(&inst
->Src
[0], TGSI_SWIZZLE_Z
);
5294 struct tgsi_full_src_register s1_xxxx
=
5295 scalar_src(&inst
->Src
[1], TGSI_SWIZZLE_X
);
5296 struct tgsi_full_src_register s1_yyyy
=
5297 scalar_src(&inst
->Src
[1], TGSI_SWIZZLE_Y
);
5298 struct tgsi_full_src_register s1_zzzz
=
5299 scalar_src(&inst
->Src
[1], TGSI_SWIZZLE_Z
);
5301 unsigned tmp1
= get_temp_index(emit
);
5302 struct tgsi_full_src_register tmp1_src
= make_src_temp_reg(tmp1
);
5303 struct tgsi_full_dst_register tmp1_dst
= make_dst_temp_reg(tmp1
);
5305 unsigned tmp2
= get_temp_index(emit
);
5306 struct tgsi_full_src_register tmp2_src
= make_src_temp_reg(tmp2
);
5307 struct tgsi_full_dst_register tmp2_dst
= make_dst_temp_reg(tmp2
);
5308 struct tgsi_full_src_register neg_tmp2_src
= negate_src(&tmp2_src
);
5310 unsigned tmp3
= get_temp_index(emit
);
5311 struct tgsi_full_src_register tmp3_src
= make_src_temp_reg(tmp3
);
5312 struct tgsi_full_dst_register tmp3_dst
= make_dst_temp_reg(tmp3
);
5313 struct tgsi_full_dst_register tmp3_dst_x
=
5314 writemask_dst(&tmp3_dst
, TGSI_WRITEMASK_X
);
5315 struct tgsi_full_dst_register tmp3_dst_y
=
5316 writemask_dst(&tmp3_dst
, TGSI_WRITEMASK_Y
);
5317 struct tgsi_full_dst_register tmp3_dst_z
=
5318 writemask_dst(&tmp3_dst
, TGSI_WRITEMASK_Z
);
5319 struct tgsi_full_dst_register tmp3_dst_w
=
5320 writemask_dst(&tmp3_dst
, TGSI_WRITEMASK_W
);
5322 /* Note: we put all the intermediate computations into tmp3 in case
5323 * the XPD dest register is that same as one of the src regs (in which
5324 * case we could clobber a src reg before we're done with it) .
5326 * Note: we could get by with just one temp register instead of three
5327 * since we're doing scalar operations and there's enough room in one
5328 * temp for everything.
5331 /* MUL tmp1, src0.y, src1.z */
5332 /* MUL tmp2, src1.y, src0.z */
5333 /* ADD tmp3.x, tmp1, -tmp2 */
5334 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_X
) {
5335 emit_instruction_op2(emit
, VGPU10_OPCODE_MUL
, &tmp1_dst
,
5336 &s0_yyyy
, &s1_zzzz
, FALSE
);
5337 emit_instruction_op2(emit
, VGPU10_OPCODE_MUL
, &tmp2_dst
,
5338 &s1_yyyy
, &s0_zzzz
, FALSE
);
5339 emit_instruction_op2(emit
, VGPU10_OPCODE_ADD
, &tmp3_dst_x
,
5340 &tmp1_src
, &neg_tmp2_src
, FALSE
);
5343 /* MUL tmp1, src0.z, src1.x */
5344 /* MUL tmp2, src1.z, src0.x */
5345 /* ADD tmp3.y, tmp1, -tmp2 */
5346 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Y
) {
5347 emit_instruction_op2(emit
, VGPU10_OPCODE_MUL
, &tmp1_dst
, &s0_zzzz
,
5349 emit_instruction_op2(emit
, VGPU10_OPCODE_MUL
, &tmp2_dst
, &s1_zzzz
,
5351 emit_instruction_op2(emit
, VGPU10_OPCODE_ADD
, &tmp3_dst_y
,
5352 &tmp1_src
, &neg_tmp2_src
, FALSE
);
5355 /* MUL tmp1, src0.x, src1.y */
5356 /* MUL tmp2, src1.x, src0.y */
5357 /* ADD tmp3.z, tmp1, -tmp2 */
5358 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_Z
) {
5359 emit_instruction_op2(emit
, VGPU10_OPCODE_MUL
, &tmp1_dst
, &s0_xxxx
,
5361 emit_instruction_op2(emit
, VGPU10_OPCODE_MUL
, &tmp2_dst
, &s1_xxxx
,
5363 emit_instruction_op2(emit
, VGPU10_OPCODE_ADD
, &tmp3_dst_z
,
5364 &tmp1_src
, &neg_tmp2_src
, FALSE
);
5367 /* MOV tmp3.w, 1.0 */
5368 if (inst
->Dst
[0].Register
.WriteMask
& TGSI_WRITEMASK_W
) {
5369 struct tgsi_full_src_register one
=
5370 make_immediate_reg_float(emit
, 1.0f
);
5372 emit_instruction_op1(emit
, VGPU10_OPCODE_MOV
, &tmp3_dst_w
, &one
, FALSE
);
5376 emit_instruction_op1(emit
, VGPU10_OPCODE_MOV
, &inst
->Dst
[0], &tmp3_src
,
5377 inst
->Instruction
.Saturate
);
5380 free_temp_indexes(emit
);
5387 * Emit code for TGSI_OPCODE_TXD (explicit derivatives)
5390 emit_txd(struct svga_shader_emitter_v10
*emit
,
5391 const struct tgsi_full_instruction
*inst
)
5393 const uint unit
= inst
->Src
[3].Register
.Index
;
5394 unsigned target
= inst
->Texture
.Texture
;
5396 struct tgsi_full_src_register coord
;
5397 struct tex_swizzle_info swz_info
;
5399 begin_tex_swizzle(emit
, unit
, inst
, tgsi_is_shadow_target(target
),
5402 get_texel_offsets(emit
, inst
, offsets
);
5404 coord
= setup_texcoord(emit
, unit
, &inst
->Src
[0]);
5406 /* SAMPLE_D dst, coord(s0), resource, sampler, Xderiv(s1), Yderiv(s2) */
5407 begin_emit_instruction(emit
);
5408 emit_sample_opcode(emit
, VGPU10_OPCODE_SAMPLE_D
,
5409 inst
->Instruction
.Saturate
, offsets
);
5410 emit_dst_register(emit
, get_tex_swizzle_dst(&swz_info
));
5411 emit_src_register(emit
, &coord
);
5412 emit_resource_register(emit
, unit
);
5413 emit_sampler_register(emit
, unit
);
5414 emit_src_register(emit
, &inst
->Src
[1]); /* Xderiv */
5415 emit_src_register(emit
, &inst
->Src
[2]); /* Yderiv */
5416 end_emit_instruction(emit
);
5418 end_tex_swizzle(emit
, &swz_info
);
5420 free_temp_indexes(emit
);
5427 * Emit code for TGSI_OPCODE_TXF (texel fetch)
5430 emit_txf(struct svga_shader_emitter_v10
*emit
,
5431 const struct tgsi_full_instruction
*inst
)
5433 const uint unit
= inst
->Src
[1].Register
.Index
;
5434 const boolean msaa
= tgsi_is_msaa_target(inst
->Texture
.Texture
);
5436 struct tex_swizzle_info swz_info
;
5438 begin_tex_swizzle(emit
, unit
, inst
, FALSE
, &swz_info
);
5440 get_texel_offsets(emit
, inst
, offsets
);
5443 /* Fetch one sample from an MSAA texture */
5444 struct tgsi_full_src_register sampleIndex
=
5445 scalar_src(&inst
->Src
[0], TGSI_SWIZZLE_W
);
5446 /* LD_MS dst, coord(s0), resource, sampleIndex */
5447 begin_emit_instruction(emit
);
5448 emit_sample_opcode(emit
, VGPU10_OPCODE_LD_MS
,
5449 inst
->Instruction
.Saturate
, offsets
);
5450 emit_dst_register(emit
, get_tex_swizzle_dst(&swz_info
));
5451 emit_src_register(emit
, &inst
->Src
[0]);
5452 emit_resource_register(emit
, unit
);
5453 emit_src_register(emit
, &sampleIndex
);
5454 end_emit_instruction(emit
);
5457 /* Fetch one texel specified by integer coordinate */
5458 /* LD dst, coord(s0), resource */
5459 begin_emit_instruction(emit
);
5460 emit_sample_opcode(emit
, VGPU10_OPCODE_LD
,
5461 inst
->Instruction
.Saturate
, offsets
);
5462 emit_dst_register(emit
, get_tex_swizzle_dst(&swz_info
));
5463 emit_src_register(emit
, &inst
->Src
[0]);
5464 emit_resource_register(emit
, unit
);
5465 end_emit_instruction(emit
);
5468 end_tex_swizzle(emit
, &swz_info
);
5470 free_temp_indexes(emit
);
5477 * Emit code for TGSI_OPCODE_TXL (explicit LOD) or TGSI_OPCODE_TXB (LOD bias)
5478 * or TGSI_OPCODE_TXB2 (for cube shadow maps).
5481 emit_txl_txb(struct svga_shader_emitter_v10
*emit
,
5482 const struct tgsi_full_instruction
*inst
)
5484 unsigned target
= inst
->Texture
.Texture
;
5485 unsigned opcode
, unit
;
5487 struct tgsi_full_src_register coord
, lod_bias
;
5488 struct tex_swizzle_info swz_info
;
5490 assert(inst
->Instruction
.Opcode
== TGSI_OPCODE_TXL
||
5491 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXB
||
5492 inst
->Instruction
.Opcode
== TGSI_OPCODE_TXB2
);
5494 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXB2
) {
5495 lod_bias
= scalar_src(&inst
->Src
[1], TGSI_SWIZZLE_X
);
5496 unit
= inst
->Src
[2].Register
.Index
;
5499 lod_bias
= scalar_src(&inst
->Src
[0], TGSI_SWIZZLE_W
);
5500 unit
= inst
->Src
[1].Register
.Index
;
5503 begin_tex_swizzle(emit
, unit
, inst
, tgsi_is_shadow_target(target
),
5506 get_texel_offsets(emit
, inst
, offsets
);
5508 coord
= setup_texcoord(emit
, unit
, &inst
->Src
[0]);
5510 /* SAMPLE_L/B dst, coord(s0), resource, sampler, lod(s3) */
5511 begin_emit_instruction(emit
);
5512 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXL
) {
5513 opcode
= VGPU10_OPCODE_SAMPLE_L
;
5516 opcode
= VGPU10_OPCODE_SAMPLE_B
;
5518 emit_sample_opcode(emit
, opcode
, inst
->Instruction
.Saturate
, offsets
);
5519 emit_dst_register(emit
, get_tex_swizzle_dst(&swz_info
));
5520 emit_src_register(emit
, &coord
);
5521 emit_resource_register(emit
, unit
);
5522 emit_sampler_register(emit
, unit
);
5523 emit_src_register(emit
, &lod_bias
);
5524 end_emit_instruction(emit
);
5526 end_tex_swizzle(emit
, &swz_info
);
5528 free_temp_indexes(emit
);
5535 * Emit code for TGSI_OPCODE_TXQ (texture query) instruction.
5538 emit_txq(struct svga_shader_emitter_v10
*emit
,
5539 const struct tgsi_full_instruction
*inst
)
5541 const uint unit
= inst
->Src
[1].Register
.Index
;
5543 if (emit
->sampler_target
[unit
] == TGSI_TEXTURE_BUFFER
) {
5544 /* RESINFO does not support querying texture buffers, so we instead
5545 * store texture buffer sizes in shader constants, then copy them to
5546 * implement TXQ instead of emitting RESINFO.
5547 * MOV dst, const[texture_buffer_size_index[unit]]
5549 struct tgsi_full_src_register size_src
=
5550 make_src_const_reg(emit
->texture_buffer_size_index
[unit
]);
5551 emit_instruction_op1(emit
, VGPU10_OPCODE_MOV
, &inst
->Dst
[0], &size_src
,
5554 /* RESINFO dst, srcMipLevel, resource */
5555 begin_emit_instruction(emit
);
5556 emit_opcode_resinfo(emit
, VGPU10_RESINFO_RETURN_UINT
);
5557 emit_dst_register(emit
, &inst
->Dst
[0]);
5558 emit_src_register(emit
, &inst
->Src
[0]);
5559 emit_resource_register(emit
, unit
);
5560 end_emit_instruction(emit
);
5563 free_temp_indexes(emit
);
5570 * Emit a simple instruction (like ADD, MUL, MIN, etc).
5573 emit_simple(struct svga_shader_emitter_v10
*emit
,
5574 const struct tgsi_full_instruction
*inst
)
5576 const unsigned opcode
= inst
->Instruction
.Opcode
;
5577 const struct tgsi_opcode_info
*op
= tgsi_get_opcode_info(opcode
);
5580 begin_emit_instruction(emit
);
5581 emit_opcode(emit
, translate_opcode(inst
->Instruction
.Opcode
),
5582 inst
->Instruction
.Saturate
);
5583 for (i
= 0; i
< op
->num_dst
; i
++) {
5584 emit_dst_register(emit
, &inst
->Dst
[i
]);
5586 for (i
= 0; i
< op
->num_src
; i
++) {
5587 emit_src_register(emit
, &inst
->Src
[i
]);
5589 end_emit_instruction(emit
);
5596 * We only special case the MOV instruction to try to detect constant
5597 * color writes in the fragment shader.
5600 emit_mov(struct svga_shader_emitter_v10
*emit
,
5601 const struct tgsi_full_instruction
*inst
)
5603 const struct tgsi_full_src_register
*src
= &inst
->Src
[0];
5604 const struct tgsi_full_dst_register
*dst
= &inst
->Dst
[0];
5606 if (emit
->unit
== PIPE_SHADER_FRAGMENT
&&
5607 dst
->Register
.File
== TGSI_FILE_OUTPUT
&&
5608 dst
->Register
.Index
== 0 &&
5609 src
->Register
.File
== TGSI_FILE_CONSTANT
&&
5610 !src
->Register
.Indirect
) {
5611 emit
->constant_color_output
= TRUE
;
5614 return emit_simple(emit
, inst
);
5619 * Emit a simple VGPU10 instruction which writes to multiple dest registers,
5620 * where TGSI only uses one dest register.
5623 emit_simple_1dst(struct svga_shader_emitter_v10
*emit
,
5624 const struct tgsi_full_instruction
*inst
,
5628 const unsigned opcode
= inst
->Instruction
.Opcode
;
5629 const struct tgsi_opcode_info
*op
= tgsi_get_opcode_info(opcode
);
5632 begin_emit_instruction(emit
);
5633 emit_opcode(emit
, translate_opcode(inst
->Instruction
.Opcode
),
5634 inst
->Instruction
.Saturate
);
5636 for (i
= 0; i
< dst_count
; i
++) {
5637 if (i
== dst_index
) {
5638 emit_dst_register(emit
, &inst
->Dst
[0]);
5640 emit_null_dst_register(emit
);
5644 for (i
= 0; i
< op
->num_src
; i
++) {
5645 emit_src_register(emit
, &inst
->Src
[i
]);
5647 end_emit_instruction(emit
);
5654 * Translate a single TGSI instruction to VGPU10.
5657 emit_vgpu10_instruction(struct svga_shader_emitter_v10
*emit
,
5658 unsigned inst_number
,
5659 const struct tgsi_full_instruction
*inst
)
5661 const unsigned opcode
= inst
->Instruction
.Opcode
;
5664 case TGSI_OPCODE_ADD
:
5665 case TGSI_OPCODE_AND
:
5666 case TGSI_OPCODE_BGNLOOP
:
5667 case TGSI_OPCODE_BRK
:
5668 case TGSI_OPCODE_CEIL
:
5669 case TGSI_OPCODE_CONT
:
5670 case TGSI_OPCODE_DDX
:
5671 case TGSI_OPCODE_DDY
:
5672 case TGSI_OPCODE_DIV
:
5673 case TGSI_OPCODE_DP2
:
5674 case TGSI_OPCODE_DP3
:
5675 case TGSI_OPCODE_DP4
:
5676 case TGSI_OPCODE_ELSE
:
5677 case TGSI_OPCODE_ENDIF
:
5678 case TGSI_OPCODE_ENDLOOP
:
5679 case TGSI_OPCODE_ENDSUB
:
5680 case TGSI_OPCODE_F2I
:
5681 case TGSI_OPCODE_F2U
:
5682 case TGSI_OPCODE_FLR
:
5683 case TGSI_OPCODE_FRC
:
5684 case TGSI_OPCODE_FSEQ
:
5685 case TGSI_OPCODE_FSGE
:
5686 case TGSI_OPCODE_FSLT
:
5687 case TGSI_OPCODE_FSNE
:
5688 case TGSI_OPCODE_I2F
:
5689 case TGSI_OPCODE_IMAX
:
5690 case TGSI_OPCODE_IMIN
:
5691 case TGSI_OPCODE_INEG
:
5692 case TGSI_OPCODE_ISGE
:
5693 case TGSI_OPCODE_ISHR
:
5694 case TGSI_OPCODE_ISLT
:
5695 case TGSI_OPCODE_MAD
:
5696 case TGSI_OPCODE_MAX
:
5697 case TGSI_OPCODE_MIN
:
5698 case TGSI_OPCODE_MUL
:
5699 case TGSI_OPCODE_NOP
:
5700 case TGSI_OPCODE_NOT
:
5701 case TGSI_OPCODE_OR
:
5702 case TGSI_OPCODE_RET
:
5703 case TGSI_OPCODE_UADD
:
5704 case TGSI_OPCODE_USEQ
:
5705 case TGSI_OPCODE_USGE
:
5706 case TGSI_OPCODE_USLT
:
5707 case TGSI_OPCODE_UMIN
:
5708 case TGSI_OPCODE_UMAD
:
5709 case TGSI_OPCODE_UMAX
:
5710 case TGSI_OPCODE_ROUND
:
5711 case TGSI_OPCODE_SQRT
:
5712 case TGSI_OPCODE_SHL
:
5713 case TGSI_OPCODE_TRUNC
:
5714 case TGSI_OPCODE_U2F
:
5715 case TGSI_OPCODE_UCMP
:
5716 case TGSI_OPCODE_USHR
:
5717 case TGSI_OPCODE_USNE
:
5718 case TGSI_OPCODE_XOR
:
5719 /* simple instructions */
5720 return emit_simple(emit
, inst
);
5722 case TGSI_OPCODE_MOV
:
5723 return emit_mov(emit
, inst
);
5724 case TGSI_OPCODE_EMIT
:
5725 return emit_vertex(emit
, inst
);
5726 case TGSI_OPCODE_ENDPRIM
:
5727 return emit_endprim(emit
, inst
);
5728 case TGSI_OPCODE_IABS
:
5729 return emit_iabs(emit
, inst
);
5730 case TGSI_OPCODE_ARL
:
5732 case TGSI_OPCODE_UARL
:
5733 return emit_arl_uarl(emit
, inst
);
5734 case TGSI_OPCODE_BGNSUB
:
5737 case TGSI_OPCODE_CAL
:
5738 return emit_cal(emit
, inst
);
5739 case TGSI_OPCODE_CMP
:
5740 return emit_cmp(emit
, inst
);
5741 case TGSI_OPCODE_COS
:
5742 return emit_sincos(emit
, inst
);
5743 case TGSI_OPCODE_DP2A
:
5744 return emit_dp2a(emit
, inst
);
5745 case TGSI_OPCODE_DPH
:
5746 return emit_dph(emit
, inst
);
5747 case TGSI_OPCODE_DST
:
5748 return emit_dst(emit
, inst
);
5749 case TGSI_OPCODE_EX2
:
5750 return emit_ex2(emit
, inst
);
5751 case TGSI_OPCODE_EXP
:
5752 return emit_exp(emit
, inst
);
5753 case TGSI_OPCODE_IF
:
5754 return emit_if(emit
, inst
);
5755 case TGSI_OPCODE_KILL
:
5756 return emit_kill(emit
, inst
);
5757 case TGSI_OPCODE_KILL_IF
:
5758 return emit_kill_if(emit
, inst
);
5759 case TGSI_OPCODE_LG2
:
5760 return emit_lg2(emit
, inst
);
5761 case TGSI_OPCODE_LIT
:
5762 return emit_lit(emit
, inst
);
5763 case TGSI_OPCODE_LOG
:
5764 return emit_log(emit
, inst
);
5765 case TGSI_OPCODE_LRP
:
5766 return emit_lrp(emit
, inst
);
5767 case TGSI_OPCODE_POW
:
5768 return emit_pow(emit
, inst
);
5769 case TGSI_OPCODE_RCP
:
5770 return emit_rcp(emit
, inst
);
5771 case TGSI_OPCODE_RSQ
:
5772 return emit_rsq(emit
, inst
);
5773 case TGSI_OPCODE_SAMPLE
:
5774 return emit_sample(emit
, inst
);
5775 case TGSI_OPCODE_SCS
:
5776 return emit_scs(emit
, inst
);
5777 case TGSI_OPCODE_SEQ
:
5778 return emit_seq(emit
, inst
);
5779 case TGSI_OPCODE_SGE
:
5780 return emit_sge(emit
, inst
);
5781 case TGSI_OPCODE_SGT
:
5782 return emit_sgt(emit
, inst
);
5783 case TGSI_OPCODE_SIN
:
5784 return emit_sincos(emit
, inst
);
5785 case TGSI_OPCODE_SLE
:
5786 return emit_sle(emit
, inst
);
5787 case TGSI_OPCODE_SLT
:
5788 return emit_slt(emit
, inst
);
5789 case TGSI_OPCODE_SNE
:
5790 return emit_sne(emit
, inst
);
5791 case TGSI_OPCODE_SSG
:
5792 return emit_ssg(emit
, inst
);
5793 case TGSI_OPCODE_ISSG
:
5794 return emit_issg(emit
, inst
);
5795 case TGSI_OPCODE_TEX
:
5796 return emit_tex(emit
, inst
);
5797 case TGSI_OPCODE_TXP
:
5798 return emit_txp(emit
, inst
);
5799 case TGSI_OPCODE_TXB
:
5800 case TGSI_OPCODE_TXB2
:
5801 case TGSI_OPCODE_TXL
:
5802 return emit_txl_txb(emit
, inst
);
5803 case TGSI_OPCODE_TXD
:
5804 return emit_txd(emit
, inst
);
5805 case TGSI_OPCODE_TXF
:
5806 return emit_txf(emit
, inst
);
5807 case TGSI_OPCODE_TXQ
:
5808 return emit_txq(emit
, inst
);
5809 case TGSI_OPCODE_UIF
:
5810 return emit_if(emit
, inst
);
5811 case TGSI_OPCODE_XPD
:
5812 return emit_xpd(emit
, inst
);
5813 case TGSI_OPCODE_UMUL_HI
:
5814 case TGSI_OPCODE_IMUL_HI
:
5815 case TGSI_OPCODE_UDIV
:
5816 case TGSI_OPCODE_IDIV
:
5817 /* These cases use only the FIRST of two destination registers */
5818 return emit_simple_1dst(emit
, inst
, 2, 0);
5819 case TGSI_OPCODE_UMUL
:
5820 case TGSI_OPCODE_UMOD
:
5821 case TGSI_OPCODE_MOD
:
5822 /* These cases use only the SECOND of two destination registers */
5823 return emit_simple_1dst(emit
, inst
, 2, 1);
5824 case TGSI_OPCODE_END
:
5825 if (!emit_post_helpers(emit
))
5827 return emit_simple(emit
, inst
);
5830 debug_printf("Unimplemented tgsi instruction %s\n",
5831 tgsi_get_opcode_name(opcode
));
5840 * Emit the extra instructions to adjust the vertex position.
5841 * There are two possible adjustments:
5842 * 1. Converting from Gallium to VGPU10 coordinate space by applying the
5843 * "prescale" and "pretranslate" values.
5844 * 2. Undoing the viewport transformation when we use the swtnl/draw path.
5845 * \param vs_pos_tmp_index which temporary register contains the vertex pos.
5848 emit_vpos_instructions(struct svga_shader_emitter_v10
*emit
,
5849 unsigned vs_pos_tmp_index
)
5851 struct tgsi_full_src_register tmp_pos_src
;
5852 struct tgsi_full_dst_register pos_dst
;
5854 /* Don't bother to emit any extra vertex instructions if vertex position is
5857 if (emit
->vposition
.out_index
== INVALID_INDEX
)
5860 tmp_pos_src
= make_src_temp_reg(vs_pos_tmp_index
);
5861 pos_dst
= make_dst_output_reg(emit
->vposition
.out_index
);
5863 /* If non-adjusted vertex position register index
5864 * is valid, copy the vertex position from the temporary
5865 * vertex position register before it is modified by the
5866 * prescale computation.
5868 if (emit
->vposition
.so_index
!= INVALID_INDEX
) {
5869 struct tgsi_full_dst_register pos_so_dst
=
5870 make_dst_output_reg(emit
->vposition
.so_index
);
5872 /* MOV pos_so, tmp_pos */
5873 emit_instruction_op1(emit
, VGPU10_OPCODE_MOV
, &pos_so_dst
,
5874 &tmp_pos_src
, FALSE
);
5877 if (emit
->vposition
.need_prescale
) {
5878 /* This code adjusts the vertex position to match the VGPU10 convention.
5879 * If p is the position computed by the shader (usually by applying the
5880 * modelview and projection matrices), the new position q is computed by:
5882 * q.x = p.w * trans.x + p.x * scale.x
5883 * q.y = p.w * trans.y + p.y * scale.y
5884 * q.z = p.w * trans.z + p.z * scale.z;
5885 * q.w = p.w * trans.w + p.w;
5887 struct tgsi_full_src_register tmp_pos_src_w
=
5888 scalar_src(&tmp_pos_src
, TGSI_SWIZZLE_W
);
5889 struct tgsi_full_dst_register tmp_pos_dst
=
5890 make_dst_temp_reg(vs_pos_tmp_index
);
5891 struct tgsi_full_dst_register tmp_pos_dst_xyz
=
5892 writemask_dst(&tmp_pos_dst
, TGSI_WRITEMASK_XYZ
);
5894 struct tgsi_full_src_register prescale_scale
=
5895 make_src_const_reg(emit
->vposition
.prescale_scale_index
);
5896 struct tgsi_full_src_register prescale_trans
=
5897 make_src_const_reg(emit
->vposition
.prescale_trans_index
);
5899 /* MUL tmp_pos.xyz, tmp_pos, prescale.scale */
5900 emit_instruction_op2(emit
, VGPU10_OPCODE_MUL
, &tmp_pos_dst_xyz
,
5901 &tmp_pos_src
, &prescale_scale
, FALSE
);
5903 /* MAD pos, tmp_pos.wwww, prescale.trans, tmp_pos */
5904 emit_instruction_op3(emit
, VGPU10_OPCODE_MAD
, &pos_dst
, &tmp_pos_src_w
,
5905 &prescale_trans
, &tmp_pos_src
, FALSE
);
5907 else if (emit
->key
.vs
.undo_viewport
) {
5908 /* This code computes the final vertex position from the temporary
5909 * vertex position by undoing the viewport transformation and the
5910 * divide-by-W operation (we convert window coords back to clip coords).
5911 * This is needed when we use the 'draw' module for fallbacks.
5912 * If p is the temp pos in window coords, then the NDC coord q is:
5913 * q.x = (p.x - vp.x_trans) / vp.x_scale * p.w
5914 * q.y = (p.y - vp.y_trans) / vp.y_scale * p.w
5917 * CONST[vs_viewport_index] contains:
5918 * { 1/vp.x_scale, 1/vp.y_scale, -vp.x_trans, -vp.y_trans }
5920 struct tgsi_full_dst_register tmp_pos_dst
=
5921 make_dst_temp_reg(vs_pos_tmp_index
);
5922 struct tgsi_full_dst_register tmp_pos_dst_xy
=
5923 writemask_dst(&tmp_pos_dst
, TGSI_WRITEMASK_XY
);
5924 struct tgsi_full_src_register tmp_pos_src_wwww
=
5925 scalar_src(&tmp_pos_src
, TGSI_SWIZZLE_W
);
5927 struct tgsi_full_dst_register pos_dst_xyz
=
5928 writemask_dst(&pos_dst
, TGSI_WRITEMASK_XYZ
);
5929 struct tgsi_full_dst_register pos_dst_w
=
5930 writemask_dst(&pos_dst
, TGSI_WRITEMASK_W
);
5932 struct tgsi_full_src_register vp_xyzw
=
5933 make_src_const_reg(emit
->vs
.viewport_index
);
5934 struct tgsi_full_src_register vp_zwww
=
5935 swizzle_src(&vp_xyzw
, TGSI_SWIZZLE_Z
, TGSI_SWIZZLE_W
,
5936 TGSI_SWIZZLE_W
, TGSI_SWIZZLE_W
);
5938 /* ADD tmp_pos.xy, tmp_pos.xy, viewport.zwww */
5939 emit_instruction_op2(emit
, VGPU10_OPCODE_ADD
, &tmp_pos_dst_xy
,
5940 &tmp_pos_src
, &vp_zwww
, FALSE
);
5942 /* MUL tmp_pos.xy, tmp_pos.xyzw, viewport.xyzy */
5943 emit_instruction_op2(emit
, VGPU10_OPCODE_MUL
, &tmp_pos_dst_xy
,
5944 &tmp_pos_src
, &vp_xyzw
, FALSE
);
5946 /* MUL pos.xyz, tmp_pos.xyz, tmp_pos.www */
5947 emit_instruction_op2(emit
, VGPU10_OPCODE_MUL
, &pos_dst_xyz
,
5948 &tmp_pos_src
, &tmp_pos_src_wwww
, FALSE
);
5950 /* MOV pos.w, tmp_pos.w */
5951 emit_instruction_op1(emit
, VGPU10_OPCODE_MOV
, &pos_dst_w
,
5952 &tmp_pos_src
, FALSE
);
5954 else if (vs_pos_tmp_index
!= INVALID_INDEX
) {
5955 /* This code is to handle the case where the temporary vertex
5956 * position register is created when the vertex shader has stream
5957 * output and prescale is disabled because rasterization is to be
5960 struct tgsi_full_dst_register pos_dst
=
5961 make_dst_output_reg(emit
->vposition
.out_index
);
5963 /* MOV pos, tmp_pos */
5964 begin_emit_instruction(emit
);
5965 emit_opcode(emit
, VGPU10_OPCODE_MOV
, FALSE
);
5966 emit_dst_register(emit
, &pos_dst
);
5967 emit_src_register(emit
, &tmp_pos_src
);
5968 end_emit_instruction(emit
);
5973 emit_clipping_instructions(struct svga_shader_emitter_v10
*emit
)
5975 if (emit
->clip_mode
== CLIP_DISTANCE
) {
5976 /* Copy from copy distance temporary to CLIPDIST & the shadow copy */
5977 emit_clip_distance_instructions(emit
);
5979 } else if (emit
->clip_mode
== CLIP_VERTEX
) {
5980 /* Convert TGSI CLIPVERTEX to CLIPDIST */
5981 emit_clip_vertex_instructions(emit
);
5985 * Emit vertex position and take care of legacy user planes only if
5986 * there is a valid vertex position register index.
5987 * This is to take care of the case
5988 * where the shader doesn't output vertex position. Then in
5989 * this case, don't bother to emit more vertex instructions.
5991 if (emit
->vposition
.out_index
== INVALID_INDEX
)
5995 * Emit per-vertex clipping instructions for legacy user defined clip planes.
5996 * NOTE: we must emit the clip distance instructions before the
5997 * emit_vpos_instructions() call since the later function will change
5998 * the TEMP[vs_pos_tmp_index] value.
6000 if (emit
->clip_mode
== CLIP_LEGACY
) {
6001 /* Emit CLIPDIST for legacy user defined clip planes */
6002 emit_clip_distance_from_vpos(emit
, emit
->vposition
.tmp_index
);
6008 * Emit extra per-vertex instructions. This includes clip-coordinate
6009 * space conversion and computing clip distances. This is called for
6010 * each GS emit-vertex instruction and at the end of VS translation.
6013 emit_vertex_instructions(struct svga_shader_emitter_v10
*emit
)
6015 const unsigned vs_pos_tmp_index
= emit
->vposition
.tmp_index
;
6017 /* Emit clipping instructions based on clipping mode */
6018 emit_clipping_instructions(emit
);
6021 * Reset the temporary vertex position register index
6022 * so that emit_dst_register() will use the real vertex position output
6024 emit
->vposition
.tmp_index
= INVALID_INDEX
;
6026 /* Emit vertex position instructions */
6027 emit_vpos_instructions(emit
, vs_pos_tmp_index
);
6029 /* Restore original vposition.tmp_index value for the next GS vertex.
6030 * It doesn't matter for VS.
6032 emit
->vposition
.tmp_index
= vs_pos_tmp_index
;
6036 * Translate the TGSI_OPCODE_EMIT GS instruction.
6039 emit_vertex(struct svga_shader_emitter_v10
*emit
,
6040 const struct tgsi_full_instruction
*inst
)
6042 unsigned ret
= TRUE
;
6044 assert(emit
->unit
== PIPE_SHADER_GEOMETRY
);
6046 emit_vertex_instructions(emit
);
6048 /* We can't use emit_simple() because the TGSI instruction has one
6049 * operand (vertex stream number) which we must ignore for VGPU10.
6051 begin_emit_instruction(emit
);
6052 emit_opcode(emit
, VGPU10_OPCODE_EMIT
, FALSE
);
6053 end_emit_instruction(emit
);
6060 * Emit the extra code to convert from VGPU10's boolean front-face
6061 * register to TGSI's signed front-face register.
6063 * TODO: Make temporary front-face register a scalar.
6066 emit_frontface_instructions(struct svga_shader_emitter_v10
*emit
)
6068 assert(emit
->unit
== PIPE_SHADER_FRAGMENT
);
6070 if (emit
->fs
.face_input_index
!= INVALID_INDEX
) {
6071 /* convert vgpu10 boolean face register to gallium +/-1 value */
6072 struct tgsi_full_dst_register tmp_dst
=
6073 make_dst_temp_reg(emit
->fs
.face_tmp_index
);
6074 struct tgsi_full_src_register one
=
6075 make_immediate_reg_float(emit
, 1.0f
);
6076 struct tgsi_full_src_register neg_one
=
6077 make_immediate_reg_float(emit
, -1.0f
);
6079 /* MOVC face_tmp, IS_FRONT_FACE.x, 1.0, -1.0 */
6080 begin_emit_instruction(emit
);
6081 emit_opcode(emit
, VGPU10_OPCODE_MOVC
, FALSE
);
6082 emit_dst_register(emit
, &tmp_dst
);
6083 emit_face_register(emit
);
6084 emit_src_register(emit
, &one
);
6085 emit_src_register(emit
, &neg_one
);
6086 end_emit_instruction(emit
);
6092 * Emit the extra code to convert from VGPU10's fragcoord.w value to 1/w.
6095 emit_fragcoord_instructions(struct svga_shader_emitter_v10
*emit
)
6097 assert(emit
->unit
== PIPE_SHADER_FRAGMENT
);
6099 if (emit
->fs
.fragcoord_input_index
!= INVALID_INDEX
) {
6100 struct tgsi_full_dst_register tmp_dst
=
6101 make_dst_temp_reg(emit
->fs
.fragcoord_tmp_index
);
6102 struct tgsi_full_dst_register tmp_dst_xyz
=
6103 writemask_dst(&tmp_dst
, TGSI_WRITEMASK_XYZ
);
6104 struct tgsi_full_dst_register tmp_dst_w
=
6105 writemask_dst(&tmp_dst
, TGSI_WRITEMASK_W
);
6106 struct tgsi_full_src_register one
=
6107 make_immediate_reg_float(emit
, 1.0f
);
6108 struct tgsi_full_src_register fragcoord
=
6109 make_src_reg(TGSI_FILE_INPUT
, emit
->fs
.fragcoord_input_index
);
6111 /* save the input index */
6112 unsigned fragcoord_input_index
= emit
->fs
.fragcoord_input_index
;
6113 /* set to invalid to prevent substitution in emit_src_register() */
6114 emit
->fs
.fragcoord_input_index
= INVALID_INDEX
;
6116 /* MOV fragcoord_tmp.xyz, fragcoord.xyz */
6117 begin_emit_instruction(emit
);
6118 emit_opcode(emit
, VGPU10_OPCODE_MOV
, FALSE
);
6119 emit_dst_register(emit
, &tmp_dst_xyz
);
6120 emit_src_register(emit
, &fragcoord
);
6121 end_emit_instruction(emit
);
6123 /* DIV fragcoord_tmp.w, 1.0, fragcoord.w */
6124 begin_emit_instruction(emit
);
6125 emit_opcode(emit
, VGPU10_OPCODE_DIV
, FALSE
);
6126 emit_dst_register(emit
, &tmp_dst_w
);
6127 emit_src_register(emit
, &one
);
6128 emit_src_register(emit
, &fragcoord
);
6129 end_emit_instruction(emit
);
6131 /* restore saved value */
6132 emit
->fs
.fragcoord_input_index
= fragcoord_input_index
;
6138 * Emit extra instructions to adjust VS inputs/attributes. This can
6139 * mean casting a vertex attribute from int to float or setting the
6140 * W component to 1, or both.
6143 emit_vertex_attrib_instructions(struct svga_shader_emitter_v10
*emit
)
6145 const unsigned save_w_1_mask
= emit
->key
.vs
.adjust_attrib_w_1
;
6146 const unsigned save_itof_mask
= emit
->key
.vs
.adjust_attrib_itof
;
6147 const unsigned save_utof_mask
= emit
->key
.vs
.adjust_attrib_utof
;
6148 const unsigned save_is_bgra_mask
= emit
->key
.vs
.attrib_is_bgra
;
6149 const unsigned save_puint_to_snorm_mask
= emit
->key
.vs
.attrib_puint_to_snorm
;
6150 const unsigned save_puint_to_uscaled_mask
= emit
->key
.vs
.attrib_puint_to_uscaled
;
6151 const unsigned save_puint_to_sscaled_mask
= emit
->key
.vs
.attrib_puint_to_sscaled
;
6153 unsigned adjust_mask
= (save_w_1_mask
|
6157 save_puint_to_snorm_mask
|
6158 save_puint_to_uscaled_mask
|
6159 save_puint_to_sscaled_mask
);
6161 assert(emit
->unit
== PIPE_SHADER_VERTEX
);
6164 struct tgsi_full_src_register one
=
6165 make_immediate_reg_float(emit
, 1.0f
);
6167 struct tgsi_full_src_register one_int
=
6168 make_immediate_reg_int(emit
, 1);
6170 /* We need to turn off these bitmasks while emitting the
6171 * instructions below, then restore them afterward.
6173 emit
->key
.vs
.adjust_attrib_w_1
= 0;
6174 emit
->key
.vs
.adjust_attrib_itof
= 0;
6175 emit
->key
.vs
.adjust_attrib_utof
= 0;
6176 emit
->key
.vs
.attrib_is_bgra
= 0;
6177 emit
->key
.vs
.attrib_puint_to_snorm
= 0;
6178 emit
->key
.vs
.attrib_puint_to_uscaled
= 0;
6179 emit
->key
.vs
.attrib_puint_to_sscaled
= 0;
6181 while (adjust_mask
) {
6182 unsigned index
= u_bit_scan(&adjust_mask
);
6184 /* skip the instruction if this vertex attribute is not being used */
6185 if (emit
->info
.input_usage_mask
[index
] == 0)
6188 unsigned tmp
= emit
->vs
.adjusted_input
[index
];
6189 struct tgsi_full_src_register input_src
=
6190 make_src_reg(TGSI_FILE_INPUT
, index
);
6192 struct tgsi_full_dst_register tmp_dst
= make_dst_temp_reg(tmp
);
6193 struct tgsi_full_src_register tmp_src
= make_src_temp_reg(tmp
);
6194 struct tgsi_full_dst_register tmp_dst_w
=
6195 writemask_dst(&tmp_dst
, TGSI_WRITEMASK_W
);
6197 /* ITOF/UTOF/MOV tmp, input[index] */
6198 if (save_itof_mask
& (1 << index
)) {
6199 emit_instruction_op1(emit
, VGPU10_OPCODE_ITOF
,
6200 &tmp_dst
, &input_src
, FALSE
);
6202 else if (save_utof_mask
& (1 << index
)) {
6203 emit_instruction_op1(emit
, VGPU10_OPCODE_UTOF
,
6204 &tmp_dst
, &input_src
, FALSE
);
6206 else if (save_puint_to_snorm_mask
& (1 << index
)) {
6207 emit_puint_to_snorm(emit
, &tmp_dst
, &input_src
);
6209 else if (save_puint_to_uscaled_mask
& (1 << index
)) {
6210 emit_puint_to_uscaled(emit
, &tmp_dst
, &input_src
);
6212 else if (save_puint_to_sscaled_mask
& (1 << index
)) {
6213 emit_puint_to_sscaled(emit
, &tmp_dst
, &input_src
);
6216 assert((save_w_1_mask
| save_is_bgra_mask
) & (1 << index
));
6217 emit_instruction_op1(emit
, VGPU10_OPCODE_MOV
,
6218 &tmp_dst
, &input_src
, FALSE
);
6221 if (save_is_bgra_mask
& (1 << index
)) {
6222 emit_swap_r_b(emit
, &tmp_dst
, &tmp_src
);
6225 if (save_w_1_mask
& (1 << index
)) {
6226 /* MOV tmp.w, 1.0 */
6227 if (emit
->key
.vs
.attrib_is_pure_int
& (1 << index
)) {
6228 emit_instruction_op1(emit
, VGPU10_OPCODE_MOV
,
6229 &tmp_dst_w
, &one_int
, FALSE
);
6232 emit_instruction_op1(emit
, VGPU10_OPCODE_MOV
,
6233 &tmp_dst_w
, &one
, FALSE
);
6238 emit
->key
.vs
.adjust_attrib_w_1
= save_w_1_mask
;
6239 emit
->key
.vs
.adjust_attrib_itof
= save_itof_mask
;
6240 emit
->key
.vs
.adjust_attrib_utof
= save_utof_mask
;
6241 emit
->key
.vs
.attrib_is_bgra
= save_is_bgra_mask
;
6242 emit
->key
.vs
.attrib_puint_to_snorm
= save_puint_to_snorm_mask
;
6243 emit
->key
.vs
.attrib_puint_to_uscaled
= save_puint_to_uscaled_mask
;
6244 emit
->key
.vs
.attrib_puint_to_sscaled
= save_puint_to_sscaled_mask
;
6250 * Some common values like 0.0, 1.0, 0.5, etc. are frequently needed
6251 * to implement some instructions. We pre-allocate those values here
6252 * in the immediate constant buffer.
6255 alloc_common_immediates(struct svga_shader_emitter_v10
*emit
)
6259 emit
->common_immediate_pos
[n
++] =
6260 alloc_immediate_float4(emit
, 0.0f
, 1.0f
, 0.5f
, -1.0f
);
6262 emit
->common_immediate_pos
[n
++] =
6263 alloc_immediate_float4(emit
, 128.0f
, -128.0f
, 2.0f
, 3.0f
);
6265 emit
->common_immediate_pos
[n
++] =
6266 alloc_immediate_int4(emit
, 0, 1, 0, -1);
6268 if (emit
->key
.vs
.attrib_puint_to_snorm
) {
6269 emit
->common_immediate_pos
[n
++] =
6270 alloc_immediate_float4(emit
, -2.0f
, -2.0f
, -2.0f
, -1.66666f
);
6273 if (emit
->key
.vs
.attrib_puint_to_uscaled
) {
6274 emit
->common_immediate_pos
[n
++] =
6275 alloc_immediate_float4(emit
, 1023.0f
, 3.0f
, 0.0f
, 0.0f
);
6278 if (emit
->key
.vs
.attrib_puint_to_sscaled
) {
6279 emit
->common_immediate_pos
[n
++] =
6280 alloc_immediate_int4(emit
, 22, 12, 2, 0);
6282 emit
->common_immediate_pos
[n
++] =
6283 alloc_immediate_int4(emit
, 22, 30, 0, 0);
6286 assert(n
<= ARRAY_SIZE(emit
->common_immediate_pos
));
6287 emit
->num_common_immediates
= n
;
6292 * Emit any extra/helper declarations/code that we might need between
6293 * the declaration section and code section.
6296 emit_pre_helpers(struct svga_shader_emitter_v10
*emit
)
6299 if (emit
->unit
== PIPE_SHADER_GEOMETRY
)
6300 emit_property_instructions(emit
);
6302 /* Declare inputs */
6303 if (!emit_input_declarations(emit
))
6306 /* Declare outputs */
6307 if (!emit_output_declarations(emit
))
6310 /* Declare temporary registers */
6311 emit_temporaries_declaration(emit
);
6313 /* Declare constant registers */
6314 emit_constant_declaration(emit
);
6316 /* Declare samplers and resources */
6317 emit_sampler_declarations(emit
);
6318 emit_resource_declarations(emit
);
6320 /* Declare clip distance output registers */
6321 if (emit
->unit
== PIPE_SHADER_VERTEX
||
6322 emit
->unit
== PIPE_SHADER_GEOMETRY
) {
6323 emit_clip_distance_declarations(emit
);
6326 alloc_common_immediates(emit
);
6328 if (emit
->unit
== PIPE_SHADER_FRAGMENT
&&
6329 emit
->key
.fs
.alpha_func
!= SVGA3D_CMP_ALWAYS
) {
6330 float alpha
= emit
->key
.fs
.alpha_ref
;
6331 emit
->fs
.alpha_ref_index
=
6332 alloc_immediate_float4(emit
, alpha
, alpha
, alpha
, alpha
);
6335 /* Now, emit the constant block containing all the immediates
6336 * declared by shader, as well as the extra ones seen above.
6338 emit_vgpu10_immediates_block(emit
);
6340 if (emit
->unit
== PIPE_SHADER_FRAGMENT
) {
6341 emit_frontface_instructions(emit
);
6342 emit_fragcoord_instructions(emit
);
6344 else if (emit
->unit
== PIPE_SHADER_VERTEX
) {
6345 emit_vertex_attrib_instructions(emit
);
6353 * Emit alpha test code. This compares TEMP[fs_color_tmp_index].w
6354 * against the alpha reference value and discards the fragment if the
6358 emit_alpha_test_instructions(struct svga_shader_emitter_v10
*emit
,
6359 unsigned fs_color_tmp_index
)
6361 /* compare output color's alpha to alpha ref and kill */
6362 unsigned tmp
= get_temp_index(emit
);
6363 struct tgsi_full_src_register tmp_src
= make_src_temp_reg(tmp
);
6364 struct tgsi_full_src_register tmp_src_x
=
6365 scalar_src(&tmp_src
, TGSI_SWIZZLE_X
);
6366 struct tgsi_full_dst_register tmp_dst
= make_dst_temp_reg(tmp
);
6367 struct tgsi_full_src_register color_src
=
6368 make_src_temp_reg(fs_color_tmp_index
);
6369 struct tgsi_full_src_register color_src_w
=
6370 scalar_src(&color_src
, TGSI_SWIZZLE_W
);
6371 struct tgsi_full_src_register ref_src
=
6372 make_src_immediate_reg(emit
->fs
.alpha_ref_index
);
6373 struct tgsi_full_dst_register color_dst
=
6374 make_dst_output_reg(emit
->fs
.color_out_index
[0]);
6376 assert(emit
->unit
== PIPE_SHADER_FRAGMENT
);
6378 /* dst = src0 'alpha_func' src1 */
6379 emit_comparison(emit
, emit
->key
.fs
.alpha_func
, &tmp_dst
,
6380 &color_src_w
, &ref_src
);
6382 /* DISCARD if dst.x == 0 */
6383 begin_emit_instruction(emit
);
6384 emit_discard_opcode(emit
, FALSE
); /* discard if src0.x is zero */
6385 emit_src_register(emit
, &tmp_src_x
);
6386 end_emit_instruction(emit
);
6388 /* If we don't need to broadcast the color below or set fragments to
6389 * white, emit final color here.
6391 if (emit
->key
.fs
.write_color0_to_n_cbufs
<= 1 &&
6392 !emit
->key
.fs
.white_fragments
) {
6393 /* MOV output.color, tempcolor */
6394 emit_instruction_op1(emit
, VGPU10_OPCODE_MOV
, &color_dst
,
6395 &color_src
, FALSE
); /* XXX saturate? */
6398 free_temp_indexes(emit
);
6403 * When we need to emit white for all fragments (for emulating XOR logicop
6404 * mode), this function copies white into the temporary color output register.
6407 emit_set_color_white(struct svga_shader_emitter_v10
*emit
,
6408 unsigned fs_color_tmp_index
)
6410 struct tgsi_full_dst_register color_dst
=
6411 make_dst_temp_reg(fs_color_tmp_index
);
6412 struct tgsi_full_src_register white
=
6413 make_immediate_reg_float(emit
, 1.0f
);
6415 emit_instruction_op1(emit
, VGPU10_OPCODE_MOV
, &color_dst
, &white
, FALSE
);
6420 * Emit instructions for writing a single color output to multiple
6422 * This is used when the TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS (or
6423 * when key.fs.white_fragments is true).
6424 * property is set and the number of render targets is greater than one.
6425 * \param fs_color_tmp_index index of the temp register that holds the
6426 * color to broadcast.
6429 emit_broadcast_color_instructions(struct svga_shader_emitter_v10
*emit
,
6430 unsigned fs_color_tmp_index
)
6432 const unsigned n
= emit
->key
.fs
.write_color0_to_n_cbufs
;
6434 struct tgsi_full_src_register color_src
=
6435 make_src_temp_reg(fs_color_tmp_index
);
6437 assert(emit
->unit
== PIPE_SHADER_FRAGMENT
);
6439 for (i
= 0; i
< n
; i
++) {
6440 unsigned output_reg
= emit
->fs
.color_out_index
[i
];
6441 struct tgsi_full_dst_register color_dst
=
6442 make_dst_output_reg(output_reg
);
6444 /* Fill in this semantic here since we'll use it later in
6445 * emit_dst_register().
6447 emit
->info
.output_semantic_name
[output_reg
] = TGSI_SEMANTIC_COLOR
;
6449 /* MOV output.color[i], tempcolor */
6450 emit_instruction_op1(emit
, VGPU10_OPCODE_MOV
, &color_dst
,
6451 &color_src
, FALSE
); /* XXX saturate? */
6457 * Emit extra helper code after the original shader code, but before the
6458 * last END/RET instruction.
6459 * For vertex shaders this means emitting the extra code to apply the
6460 * prescale scale/translation.
6463 emit_post_helpers(struct svga_shader_emitter_v10
*emit
)
6465 if (emit
->unit
== PIPE_SHADER_VERTEX
) {
6466 emit_vertex_instructions(emit
);
6468 else if (emit
->unit
== PIPE_SHADER_FRAGMENT
) {
6469 const unsigned fs_color_tmp_index
= emit
->fs
.color_tmp_index
;
6471 /* We no longer want emit_dst_register() to substitute the
6472 * temporary fragment color register for the real color output.
6474 emit
->fs
.color_tmp_index
= INVALID_INDEX
;
6476 if (emit
->key
.fs
.alpha_func
!= SVGA3D_CMP_ALWAYS
) {
6477 emit_alpha_test_instructions(emit
, fs_color_tmp_index
);
6479 if (emit
->key
.fs
.white_fragments
) {
6480 emit_set_color_white(emit
, fs_color_tmp_index
);
6482 if (emit
->key
.fs
.write_color0_to_n_cbufs
> 1 ||
6483 emit
->key
.fs
.white_fragments
) {
6484 emit_broadcast_color_instructions(emit
, fs_color_tmp_index
);
6493 * Translate the TGSI tokens into VGPU10 tokens.
6496 emit_vgpu10_instructions(struct svga_shader_emitter_v10
*emit
,
6497 const struct tgsi_token
*tokens
)
6499 struct tgsi_parse_context parse
;
6501 boolean pre_helpers_emitted
= FALSE
;
6502 unsigned inst_number
= 0;
6504 tgsi_parse_init(&parse
, tokens
);
6506 while (!tgsi_parse_end_of_tokens(&parse
)) {
6507 tgsi_parse_token(&parse
);
6509 switch (parse
.FullToken
.Token
.Type
) {
6510 case TGSI_TOKEN_TYPE_IMMEDIATE
:
6511 ret
= emit_vgpu10_immediate(emit
, &parse
.FullToken
.FullImmediate
);
6516 case TGSI_TOKEN_TYPE_DECLARATION
:
6517 ret
= emit_vgpu10_declaration(emit
, &parse
.FullToken
.FullDeclaration
);
6522 case TGSI_TOKEN_TYPE_INSTRUCTION
:
6523 if (!pre_helpers_emitted
) {
6524 ret
= emit_pre_helpers(emit
);
6527 pre_helpers_emitted
= TRUE
;
6529 ret
= emit_vgpu10_instruction(emit
, inst_number
++,
6530 &parse
.FullToken
.FullInstruction
);
6535 case TGSI_TOKEN_TYPE_PROPERTY
:
6536 ret
= emit_vgpu10_property(emit
, &parse
.FullToken
.FullProperty
);
6547 tgsi_parse_free(&parse
);
6553 * Emit the first VGPU10 shader tokens.
6556 emit_vgpu10_header(struct svga_shader_emitter_v10
*emit
)
6558 VGPU10ProgramToken ptoken
;
6560 /* First token: VGPU10ProgramToken (version info, program type (VS,GS,PS)) */
6561 ptoken
.majorVersion
= 4;
6562 ptoken
.minorVersion
= 0;
6563 ptoken
.programType
= translate_shader_type(emit
->unit
);
6564 if (!emit_dword(emit
, ptoken
.value
))
6567 /* Second token: total length of shader, in tokens. We can't fill this
6568 * in until we're all done. Emit zero for now.
6570 return emit_dword(emit
, 0);
6575 emit_vgpu10_tail(struct svga_shader_emitter_v10
*emit
)
6577 VGPU10ProgramToken
*tokens
;
6579 /* Replace the second token with total shader length */
6580 tokens
= (VGPU10ProgramToken
*) emit
->buf
;
6581 tokens
[1].value
= emit_get_num_tokens(emit
);
6588 * Modify the FS to read the BCOLORs and use the FACE register
6589 * to choose between the front/back colors.
6591 static const struct tgsi_token
*
6592 transform_fs_twoside(const struct tgsi_token
*tokens
)
6595 debug_printf("Before tgsi_add_two_side ------------------\n");
6596 tgsi_dump(tokens
,0);
6598 tokens
= tgsi_add_two_side(tokens
);
6600 debug_printf("After tgsi_add_two_side ------------------\n");
6601 tgsi_dump(tokens
, 0);
6608 * Modify the FS to do polygon stipple.
6610 static const struct tgsi_token
*
6611 transform_fs_pstipple(struct svga_shader_emitter_v10
*emit
,
6612 const struct tgsi_token
*tokens
)
6614 const struct tgsi_token
*new_tokens
;
6618 debug_printf("Before pstipple ------------------\n");
6619 tgsi_dump(tokens
,0);
6622 new_tokens
= util_pstipple_create_fragment_shader(tokens
, &unit
, 0,
6625 emit
->fs
.pstipple_sampler_unit
= unit
;
6627 /* Setup texture state for stipple */
6628 emit
->sampler_target
[unit
] = TGSI_TEXTURE_2D
;
6629 emit
->key
.tex
[unit
].swizzle_r
= TGSI_SWIZZLE_X
;
6630 emit
->key
.tex
[unit
].swizzle_g
= TGSI_SWIZZLE_Y
;
6631 emit
->key
.tex
[unit
].swizzle_b
= TGSI_SWIZZLE_Z
;
6632 emit
->key
.tex
[unit
].swizzle_a
= TGSI_SWIZZLE_W
;
6635 debug_printf("After pstipple ------------------\n");
6636 tgsi_dump(new_tokens
, 0);
6643 * Modify the FS to support anti-aliasing point.
6645 static const struct tgsi_token
*
6646 transform_fs_aapoint(const struct tgsi_token
*tokens
,
6650 debug_printf("Before tgsi_add_aa_point ------------------\n");
6651 tgsi_dump(tokens
,0);
6653 tokens
= tgsi_add_aa_point(tokens
, aa_coord_index
);
6655 debug_printf("After tgsi_add_aa_point ------------------\n");
6656 tgsi_dump(tokens
, 0);
6662 * This is the main entrypoint for the TGSI -> VPGU10 translator.
6664 struct svga_shader_variant
*
6665 svga_tgsi_vgpu10_translate(struct svga_context
*svga
,
6666 const struct svga_shader
*shader
,
6667 const struct svga_compile_key
*key
,
6670 struct svga_shader_variant
*variant
= NULL
;
6671 struct svga_shader_emitter_v10
*emit
;
6672 const struct tgsi_token
*tokens
= shader
->tokens
;
6673 struct svga_vertex_shader
*vs
= svga
->curr
.vs
;
6674 struct svga_geometry_shader
*gs
= svga
->curr
.gs
;
6676 assert(unit
== PIPE_SHADER_VERTEX
||
6677 unit
== PIPE_SHADER_GEOMETRY
||
6678 unit
== PIPE_SHADER_FRAGMENT
);
6680 /* These two flags cannot be used together */
6681 assert(key
->vs
.need_prescale
+ key
->vs
.undo_viewport
<= 1);
6683 SVGA_STATS_TIME_PUSH(svga_sws(svga
), SVGA_STATS_TIME_TGSIVGPU10TRANSLATE
);
6685 * Setup the code emitter
6687 emit
= alloc_emitter();
6694 emit
->vposition
.need_prescale
= (emit
->key
.vs
.need_prescale
||
6695 emit
->key
.gs
.need_prescale
);
6696 emit
->vposition
.tmp_index
= INVALID_INDEX
;
6697 emit
->vposition
.so_index
= INVALID_INDEX
;
6698 emit
->vposition
.out_index
= INVALID_INDEX
;
6700 emit
->fs
.color_tmp_index
= INVALID_INDEX
;
6701 emit
->fs
.face_input_index
= INVALID_INDEX
;
6702 emit
->fs
.fragcoord_input_index
= INVALID_INDEX
;
6704 emit
->gs
.prim_id_index
= INVALID_INDEX
;
6706 emit
->clip_dist_out_index
= INVALID_INDEX
;
6707 emit
->clip_dist_tmp_index
= INVALID_INDEX
;
6708 emit
->clip_dist_so_index
= INVALID_INDEX
;
6709 emit
->clip_vertex_out_index
= INVALID_INDEX
;
6711 if (emit
->key
.fs
.alpha_func
== SVGA3D_CMP_INVALID
) {
6712 emit
->key
.fs
.alpha_func
= SVGA3D_CMP_ALWAYS
;
6715 if (unit
== PIPE_SHADER_FRAGMENT
) {
6716 if (key
->fs
.light_twoside
) {
6717 tokens
= transform_fs_twoside(tokens
);
6719 if (key
->fs
.pstipple
) {
6720 const struct tgsi_token
*new_tokens
=
6721 transform_fs_pstipple(emit
, tokens
);
6722 if (tokens
!= shader
->tokens
) {
6723 /* free the two-sided shader tokens */
6724 tgsi_free_tokens(tokens
);
6726 tokens
= new_tokens
;
6728 if (key
->fs
.aa_point
) {
6729 tokens
= transform_fs_aapoint(tokens
, key
->fs
.aa_point_coord_index
);
6733 if (SVGA_DEBUG
& DEBUG_TGSI
) {
6734 debug_printf("#####################################\n");
6735 debug_printf("### TGSI Shader %u\n", shader
->id
);
6736 tgsi_dump(tokens
, 0);
6740 * Rescan the header if the token string is different from the one
6741 * included in the shader; otherwise, the header info is already up-to-date
6743 if (tokens
!= shader
->tokens
) {
6744 tgsi_scan_shader(tokens
, &emit
->info
);
6746 emit
->info
= shader
->info
;
6749 emit
->num_outputs
= emit
->info
.num_outputs
;
6751 if (unit
== PIPE_SHADER_FRAGMENT
) {
6752 /* Compute FS input remapping to match the output from VS/GS */
6754 svga_link_shaders(&gs
->base
.info
, &emit
->info
, &emit
->linkage
);
6757 svga_link_shaders(&vs
->base
.info
, &emit
->info
, &emit
->linkage
);
6759 } else if (unit
== PIPE_SHADER_GEOMETRY
) {
6761 svga_link_shaders(&vs
->base
.info
, &emit
->info
, &emit
->linkage
);
6764 determine_clipping_mode(emit
);
6766 if (unit
== PIPE_SHADER_GEOMETRY
|| unit
== PIPE_SHADER_VERTEX
) {
6767 if (shader
->stream_output
!= NULL
|| emit
->clip_mode
== CLIP_DISTANCE
) {
6768 /* if there is stream output declarations associated
6769 * with this shader or the shader writes to ClipDistance
6770 * then reserve extra registers for the non-adjusted vertex position
6771 * and the ClipDistance shadow copy
6773 emit
->vposition
.so_index
= emit
->num_outputs
++;
6775 if (emit
->clip_mode
== CLIP_DISTANCE
) {
6776 emit
->clip_dist_so_index
= emit
->num_outputs
++;
6777 if (emit
->info
.num_written_clipdistance
> 4)
6778 emit
->num_outputs
++;
6784 * Do actual shader translation.
6786 if (!emit_vgpu10_header(emit
)) {
6787 debug_printf("svga: emit VGPU10 header failed\n");
6791 if (!emit_vgpu10_instructions(emit
, tokens
)) {
6792 debug_printf("svga: emit VGPU10 instructions failed\n");
6796 if (!emit_vgpu10_tail(emit
)) {
6797 debug_printf("svga: emit VGPU10 tail failed\n");
6801 if (emit
->register_overflow
) {
6806 * Create, initialize the 'variant' object.
6808 variant
= svga_new_shader_variant(svga
);
6812 variant
->shader
= shader
;
6813 variant
->nr_tokens
= emit_get_num_tokens(emit
);
6814 variant
->tokens
= (const unsigned *)emit
->buf
;
6815 emit
->buf
= NULL
; /* buffer is no longer owed by emitter context */
6816 memcpy(&variant
->key
, key
, sizeof(*key
));
6817 variant
->id
= UTIL_BITMASK_INVALID_INDEX
;
6819 /* The extra constant starting offset starts with the number of
6820 * shader constants declared in the shader.
6822 variant
->extra_const_start
= emit
->num_shader_consts
[0];
6823 if (key
->gs
.wide_point
) {
6825 * The extra constant added in the transformed shader
6826 * for inverse viewport scale is to be supplied by the driver.
6827 * So the extra constant starting offset needs to be reduced by 1.
6829 assert(variant
->extra_const_start
> 0);
6830 variant
->extra_const_start
--;
6833 variant
->pstipple_sampler_unit
= emit
->fs
.pstipple_sampler_unit
;
6835 /* If there was exactly one write to a fragment shader output register
6836 * and it came from a constant buffer, we know all fragments will have
6837 * the same color (except for blending).
6839 variant
->constant_color_output
=
6840 emit
->constant_color_output
&& emit
->num_output_writes
== 1;
6842 /** keep track in the variant if flat interpolation is used
6843 * for any of the varyings.
6845 variant
->uses_flat_interp
= emit
->uses_flat_interp
;
6847 if (tokens
!= shader
->tokens
) {
6848 tgsi_free_tokens(tokens
);
6855 SVGA_STATS_TIME_POP(svga_sws(svga
));