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[mesa.git] / src / gallium / drivers / svga / svga_tgsi_vgpu10.c
1 /**********************************************************
2 * Copyright 1998-2013 VMware, Inc. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
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12 * The above copyright notice and this permission notice shall be
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14 *
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25
26 /**
27 * @file svga_tgsi_vgpu10.c
28 *
29 * TGSI -> VGPU10 shader translation.
30 *
31 * \author Mingcheng Chen
32 * \author Brian Paul
33 */
34
35 #include "pipe/p_compiler.h"
36 #include "pipe/p_shader_tokens.h"
37 #include "pipe/p_defines.h"
38 #include "tgsi/tgsi_build.h"
39 #include "tgsi/tgsi_dump.h"
40 #include "tgsi/tgsi_info.h"
41 #include "tgsi/tgsi_parse.h"
42 #include "tgsi/tgsi_scan.h"
43 #include "tgsi/tgsi_two_side.h"
44 #include "tgsi/tgsi_aa_point.h"
45 #include "tgsi/tgsi_util.h"
46 #include "util/u_math.h"
47 #include "util/u_memory.h"
48 #include "util/u_bitmask.h"
49 #include "util/u_debug.h"
50 #include "util/u_pstipple.h"
51
52 #include "svga_context.h"
53 #include "svga_debug.h"
54 #include "svga_link.h"
55 #include "svga_shader.h"
56 #include "svga_tgsi.h"
57
58 #include "VGPU10ShaderTokens.h"
59
60
61 #define INVALID_INDEX 99999
62 #define MAX_INTERNAL_TEMPS 3
63 #define MAX_SYSTEM_VALUES 4
64 #define MAX_IMMEDIATE_COUNT \
65 (VGPU10_MAX_IMMEDIATE_CONSTANT_BUFFER_ELEMENT_COUNT/4)
66 #define MAX_TEMP_ARRAYS 64 /* Enough? */
67
68
69 /**
70 * Clipping is complicated. There's four different cases which we
71 * handle during VS/GS shader translation:
72 */
73 enum clipping_mode
74 {
75 CLIP_NONE, /**< No clipping enabled */
76 CLIP_LEGACY, /**< The shader has no clipping declarations or code but
77 * one or more user-defined clip planes are enabled. We
78 * generate extra code to emit clip distances.
79 */
80 CLIP_DISTANCE, /**< The shader already declares clip distance output
81 * registers and has code to write to them.
82 */
83 CLIP_VERTEX /**< The shader declares a clip vertex output register and
84 * has code that writes to the register. We convert the
85 * clipvertex position into one or more clip distances.
86 */
87 };
88
89
90 struct svga_shader_emitter_v10
91 {
92 /* The token output buffer */
93 unsigned size;
94 char *buf;
95 char *ptr;
96
97 /* Information about the shader and state (does not change) */
98 struct svga_compile_key key;
99 struct tgsi_shader_info info;
100 unsigned unit;
101
102 unsigned inst_start_token;
103 boolean discard_instruction; /**< throw away current instruction? */
104
105 union tgsi_immediate_data immediates[MAX_IMMEDIATE_COUNT][4];
106 unsigned num_immediates; /**< Number of immediates emitted */
107 unsigned common_immediate_pos[8]; /**< literals for common immediates */
108 unsigned num_common_immediates;
109 boolean immediates_emitted;
110
111 unsigned num_outputs; /**< include any extra outputs */
112 /** The first extra output is reserved for
113 * non-adjusted vertex position for
114 * stream output purpose
115 */
116
117 /* Temporary Registers */
118 unsigned num_shader_temps; /**< num of temps used by original shader */
119 unsigned internal_temp_count; /**< currently allocated internal temps */
120 struct {
121 unsigned start, size;
122 } temp_arrays[MAX_TEMP_ARRAYS];
123 unsigned num_temp_arrays;
124
125 /** Map TGSI temp registers to VGPU10 temp array IDs and indexes */
126 struct {
127 unsigned arrayId, index;
128 } temp_map[VGPU10_MAX_TEMPS]; /**< arrayId, element */
129
130 /** Number of constants used by original shader for each constant buffer.
131 * The size should probably always match with that of svga_state.constbufs.
132 */
133 unsigned num_shader_consts[SVGA_MAX_CONST_BUFS];
134
135 /* Samplers */
136 unsigned num_samplers;
137 ubyte sampler_target[PIPE_MAX_SAMPLERS]; /**< TGSI_TEXTURE_x */
138 ubyte sampler_return_type[PIPE_MAX_SAMPLERS]; /**< TGSI_RETURN_TYPE_x */
139
140 /* Address regs (really implemented with temps) */
141 unsigned num_address_regs;
142 unsigned address_reg_index[MAX_VGPU10_ADDR_REGS];
143
144 /* Output register usage masks */
145 ubyte output_usage_mask[PIPE_MAX_SHADER_OUTPUTS];
146
147 /* To map TGSI system value index to VGPU shader input indexes */
148 ubyte system_value_indexes[MAX_SYSTEM_VALUES];
149
150 struct {
151 /* vertex position scale/translation */
152 unsigned out_index; /**< the real position output reg */
153 unsigned tmp_index; /**< the fake/temp position output reg */
154 unsigned so_index; /**< the non-adjusted position output reg */
155 unsigned prescale_scale_index, prescale_trans_index;
156 boolean need_prescale;
157 } vposition;
158
159 /* For vertex shaders only */
160 struct {
161 /* viewport constant */
162 unsigned viewport_index;
163
164 /* temp index of adjusted vertex attributes */
165 unsigned adjusted_input[PIPE_MAX_SHADER_INPUTS];
166 } vs;
167
168 /* For fragment shaders only */
169 struct {
170 unsigned color_out_index[PIPE_MAX_COLOR_BUFS]; /**< the real color output regs */
171 unsigned num_color_outputs;
172 unsigned color_tmp_index; /**< fake/temp color output reg */
173 unsigned alpha_ref_index; /**< immediate constant for alpha ref */
174
175 /* front-face */
176 unsigned face_input_index; /**< real fragment shader face reg (bool) */
177 unsigned face_tmp_index; /**< temp face reg converted to -1 / +1 */
178
179 unsigned pstipple_sampler_unit;
180
181 unsigned fragcoord_input_index; /**< real fragment position input reg */
182 unsigned fragcoord_tmp_index; /**< 1/w modified position temp reg */
183 } fs;
184
185 /* For geometry shaders only */
186 struct {
187 VGPU10_PRIMITIVE prim_type;/**< VGPU10 primitive type */
188 VGPU10_PRIMITIVE_TOPOLOGY prim_topology; /**< VGPU10 primitive topology */
189 unsigned input_size; /**< size of input arrays */
190 unsigned prim_id_index; /**< primitive id register index */
191 unsigned max_out_vertices; /**< maximum number of output vertices */
192 } gs;
193
194 /* For vertex or geometry shaders */
195 enum clipping_mode clip_mode;
196 unsigned clip_dist_out_index; /**< clip distance output register index */
197 unsigned clip_dist_tmp_index; /**< clip distance temporary register */
198 unsigned clip_dist_so_index; /**< clip distance shadow copy */
199
200 /** Index of temporary holding the clipvertex coordinate */
201 unsigned clip_vertex_out_index; /**< clip vertex output register index */
202 unsigned clip_vertex_tmp_index; /**< clip vertex temporary index */
203
204 /* user clip plane constant slot indexes */
205 unsigned clip_plane_const[PIPE_MAX_CLIP_PLANES];
206
207 unsigned num_output_writes;
208 boolean constant_color_output;
209
210 boolean uses_flat_interp;
211
212 /* For all shaders: const reg index for RECT coord scaling */
213 unsigned texcoord_scale_index[PIPE_MAX_SAMPLERS];
214
215 /* For all shaders: const reg index for texture buffer size */
216 unsigned texture_buffer_size_index[PIPE_MAX_SAMPLERS];
217
218 /* VS/GS/FS Linkage info */
219 struct shader_linkage linkage;
220
221 bool register_overflow; /**< Set if we exceed a VGPU10 register limit */
222 };
223
224
225 static boolean
226 emit_post_helpers(struct svga_shader_emitter_v10 *emit);
227
228 static boolean
229 emit_vertex(struct svga_shader_emitter_v10 *emit,
230 const struct tgsi_full_instruction *inst);
231
232 static char err_buf[128];
233
234 static boolean
235 expand(struct svga_shader_emitter_v10 *emit)
236 {
237 char *new_buf;
238 unsigned newsize = emit->size * 2;
239
240 if (emit->buf != err_buf)
241 new_buf = REALLOC(emit->buf, emit->size, newsize);
242 else
243 new_buf = NULL;
244
245 if (!new_buf) {
246 emit->ptr = err_buf;
247 emit->buf = err_buf;
248 emit->size = sizeof(err_buf);
249 return FALSE;
250 }
251
252 emit->size = newsize;
253 emit->ptr = new_buf + (emit->ptr - emit->buf);
254 emit->buf = new_buf;
255 return TRUE;
256 }
257
258 /**
259 * Create and initialize a new svga_shader_emitter_v10 object.
260 */
261 static struct svga_shader_emitter_v10 *
262 alloc_emitter(void)
263 {
264 struct svga_shader_emitter_v10 *emit = CALLOC(1, sizeof(*emit));
265
266 if (!emit)
267 return NULL;
268
269 /* to initialize the output buffer */
270 emit->size = 512;
271 if (!expand(emit)) {
272 FREE(emit);
273 return NULL;
274 }
275 return emit;
276 }
277
278 /**
279 * Free an svga_shader_emitter_v10 object.
280 */
281 static void
282 free_emitter(struct svga_shader_emitter_v10 *emit)
283 {
284 assert(emit);
285 FREE(emit->buf); /* will be NULL if translation succeeded */
286 FREE(emit);
287 }
288
289 static inline boolean
290 reserve(struct svga_shader_emitter_v10 *emit,
291 unsigned nr_dwords)
292 {
293 while (emit->ptr - emit->buf + nr_dwords * sizeof(uint32) >= emit->size) {
294 if (!expand(emit))
295 return FALSE;
296 }
297
298 return TRUE;
299 }
300
301 static boolean
302 emit_dword(struct svga_shader_emitter_v10 *emit, uint32 dword)
303 {
304 if (!reserve(emit, 1))
305 return FALSE;
306
307 *(uint32 *)emit->ptr = dword;
308 emit->ptr += sizeof dword;
309 return TRUE;
310 }
311
312 static boolean
313 emit_dwords(struct svga_shader_emitter_v10 *emit,
314 const uint32 *dwords,
315 unsigned nr)
316 {
317 if (!reserve(emit, nr))
318 return FALSE;
319
320 memcpy(emit->ptr, dwords, nr * sizeof *dwords);
321 emit->ptr += nr * sizeof *dwords;
322 return TRUE;
323 }
324
325 /** Return the number of tokens in the emitter's buffer */
326 static unsigned
327 emit_get_num_tokens(const struct svga_shader_emitter_v10 *emit)
328 {
329 return (emit->ptr - emit->buf) / sizeof(unsigned);
330 }
331
332
333 /**
334 * Check for register overflow. If we overflow we'll set an
335 * error flag. This function can be called for register declarations
336 * or use as src/dst instruction operands.
337 * \param type register type. One of VGPU10_OPERAND_TYPE_x
338 or VGPU10_OPCODE_DCL_x
339 * \param index the register index
340 */
341 static void
342 check_register_index(struct svga_shader_emitter_v10 *emit,
343 unsigned operandType, unsigned index)
344 {
345 bool overflow_before = emit->register_overflow;
346
347 switch (operandType) {
348 case VGPU10_OPERAND_TYPE_TEMP:
349 case VGPU10_OPERAND_TYPE_INDEXABLE_TEMP:
350 case VGPU10_OPCODE_DCL_TEMPS:
351 if (index >= VGPU10_MAX_TEMPS) {
352 emit->register_overflow = TRUE;
353 }
354 break;
355 case VGPU10_OPERAND_TYPE_CONSTANT_BUFFER:
356 case VGPU10_OPCODE_DCL_CONSTANT_BUFFER:
357 if (index >= VGPU10_MAX_CONSTANT_BUFFER_ELEMENT_COUNT) {
358 emit->register_overflow = TRUE;
359 }
360 break;
361 case VGPU10_OPERAND_TYPE_INPUT:
362 case VGPU10_OPERAND_TYPE_INPUT_PRIMITIVEID:
363 case VGPU10_OPCODE_DCL_INPUT:
364 case VGPU10_OPCODE_DCL_INPUT_SGV:
365 case VGPU10_OPCODE_DCL_INPUT_SIV:
366 case VGPU10_OPCODE_DCL_INPUT_PS:
367 case VGPU10_OPCODE_DCL_INPUT_PS_SGV:
368 case VGPU10_OPCODE_DCL_INPUT_PS_SIV:
369 if ((emit->unit == PIPE_SHADER_VERTEX &&
370 index >= VGPU10_MAX_VS_INPUTS) ||
371 (emit->unit == PIPE_SHADER_GEOMETRY &&
372 index >= VGPU10_MAX_GS_INPUTS) ||
373 (emit->unit == PIPE_SHADER_FRAGMENT &&
374 index >= VGPU10_MAX_FS_INPUTS)) {
375 emit->register_overflow = TRUE;
376 }
377 break;
378 case VGPU10_OPERAND_TYPE_OUTPUT:
379 case VGPU10_OPCODE_DCL_OUTPUT:
380 case VGPU10_OPCODE_DCL_OUTPUT_SGV:
381 case VGPU10_OPCODE_DCL_OUTPUT_SIV:
382 if ((emit->unit == PIPE_SHADER_VERTEX &&
383 index >= VGPU10_MAX_VS_OUTPUTS) ||
384 (emit->unit == PIPE_SHADER_GEOMETRY &&
385 index >= VGPU10_MAX_GS_OUTPUTS) ||
386 (emit->unit == PIPE_SHADER_FRAGMENT &&
387 index >= VGPU10_MAX_FS_OUTPUTS)) {
388 emit->register_overflow = TRUE;
389 }
390 break;
391 case VGPU10_OPERAND_TYPE_SAMPLER:
392 case VGPU10_OPCODE_DCL_SAMPLER:
393 if (index >= VGPU10_MAX_SAMPLERS) {
394 emit->register_overflow = TRUE;
395 }
396 break;
397 case VGPU10_OPERAND_TYPE_RESOURCE:
398 case VGPU10_OPCODE_DCL_RESOURCE:
399 if (index >= VGPU10_MAX_RESOURCES) {
400 emit->register_overflow = TRUE;
401 }
402 break;
403 case VGPU10_OPERAND_TYPE_IMMEDIATE_CONSTANT_BUFFER:
404 if (index >= MAX_IMMEDIATE_COUNT) {
405 emit->register_overflow = TRUE;
406 }
407 break;
408 default:
409 assert(0);
410 ; /* nothing */
411 }
412
413 if (emit->register_overflow && !overflow_before) {
414 debug_printf("svga: vgpu10 register overflow (reg %u, index %u)\n",
415 operandType, index);
416 }
417 }
418
419
420 /**
421 * Examine misc state to determine the clipping mode.
422 */
423 static void
424 determine_clipping_mode(struct svga_shader_emitter_v10 *emit)
425 {
426 if (emit->info.num_written_clipdistance > 0) {
427 emit->clip_mode = CLIP_DISTANCE;
428 }
429 else if (emit->info.writes_clipvertex) {
430 emit->clip_mode = CLIP_VERTEX;
431 }
432 else if (emit->key.clip_plane_enable) {
433 emit->clip_mode = CLIP_LEGACY;
434 }
435 else {
436 emit->clip_mode = CLIP_NONE;
437 }
438 }
439
440
441 /**
442 * For clip distance register declarations and clip distance register
443 * writes we need to mask the declaration usage or instruction writemask
444 * (respectively) against the set of the really-enabled clipping planes.
445 *
446 * The piglit test spec/glsl-1.30/execution/clipping/vs-clip-distance-enables
447 * has a VS that writes to all 8 clip distance registers, but the plane enable
448 * flags are a subset of that.
449 *
450 * This function is used to apply the plane enable flags to the register
451 * declaration or instruction writemask.
452 *
453 * \param writemask the declaration usage mask or instruction writemask
454 * \param clip_reg_index which clip plane register is being declared/written.
455 * The legal values are 0 and 1 (two clip planes per
456 * register, for a total of 8 clip planes)
457 */
458 static unsigned
459 apply_clip_plane_mask(struct svga_shader_emitter_v10 *emit,
460 unsigned writemask, unsigned clip_reg_index)
461 {
462 unsigned shift;
463
464 assert(clip_reg_index < 2);
465
466 /* four clip planes per clip register: */
467 shift = clip_reg_index * 4;
468 writemask &= ((emit->key.clip_plane_enable >> shift) & 0xf);
469
470 return writemask;
471 }
472
473
474 /**
475 * Translate gallium shader type into VGPU10 type.
476 */
477 static VGPU10_PROGRAM_TYPE
478 translate_shader_type(unsigned type)
479 {
480 switch (type) {
481 case PIPE_SHADER_VERTEX:
482 return VGPU10_VERTEX_SHADER;
483 case PIPE_SHADER_GEOMETRY:
484 return VGPU10_GEOMETRY_SHADER;
485 case PIPE_SHADER_FRAGMENT:
486 return VGPU10_PIXEL_SHADER;
487 default:
488 assert(!"Unexpected shader type");
489 return VGPU10_VERTEX_SHADER;
490 }
491 }
492
493
494 /**
495 * Translate a TGSI_OPCODE_x into a VGPU10_OPCODE_x
496 * Note: we only need to translate the opcodes for "simple" instructions,
497 * as seen below. All other opcodes are handled/translated specially.
498 */
499 static VGPU10_OPCODE_TYPE
500 translate_opcode(unsigned opcode)
501 {
502 switch (opcode) {
503 case TGSI_OPCODE_MOV:
504 return VGPU10_OPCODE_MOV;
505 case TGSI_OPCODE_MUL:
506 return VGPU10_OPCODE_MUL;
507 case TGSI_OPCODE_ADD:
508 return VGPU10_OPCODE_ADD;
509 case TGSI_OPCODE_DP3:
510 return VGPU10_OPCODE_DP3;
511 case TGSI_OPCODE_DP4:
512 return VGPU10_OPCODE_DP4;
513 case TGSI_OPCODE_MIN:
514 return VGPU10_OPCODE_MIN;
515 case TGSI_OPCODE_MAX:
516 return VGPU10_OPCODE_MAX;
517 case TGSI_OPCODE_MAD:
518 return VGPU10_OPCODE_MAD;
519 case TGSI_OPCODE_SQRT:
520 return VGPU10_OPCODE_SQRT;
521 case TGSI_OPCODE_FRC:
522 return VGPU10_OPCODE_FRC;
523 case TGSI_OPCODE_FLR:
524 return VGPU10_OPCODE_ROUND_NI;
525 case TGSI_OPCODE_FSEQ:
526 return VGPU10_OPCODE_EQ;
527 case TGSI_OPCODE_FSGE:
528 return VGPU10_OPCODE_GE;
529 case TGSI_OPCODE_FSNE:
530 return VGPU10_OPCODE_NE;
531 case TGSI_OPCODE_DDX:
532 return VGPU10_OPCODE_DERIV_RTX;
533 case TGSI_OPCODE_DDY:
534 return VGPU10_OPCODE_DERIV_RTY;
535 case TGSI_OPCODE_RET:
536 return VGPU10_OPCODE_RET;
537 case TGSI_OPCODE_DIV:
538 return VGPU10_OPCODE_DIV;
539 case TGSI_OPCODE_IDIV:
540 return VGPU10_OPCODE_IDIV;
541 case TGSI_OPCODE_DP2:
542 return VGPU10_OPCODE_DP2;
543 case TGSI_OPCODE_BRK:
544 return VGPU10_OPCODE_BREAK;
545 case TGSI_OPCODE_IF:
546 return VGPU10_OPCODE_IF;
547 case TGSI_OPCODE_ELSE:
548 return VGPU10_OPCODE_ELSE;
549 case TGSI_OPCODE_ENDIF:
550 return VGPU10_OPCODE_ENDIF;
551 case TGSI_OPCODE_CEIL:
552 return VGPU10_OPCODE_ROUND_PI;
553 case TGSI_OPCODE_I2F:
554 return VGPU10_OPCODE_ITOF;
555 case TGSI_OPCODE_NOT:
556 return VGPU10_OPCODE_NOT;
557 case TGSI_OPCODE_TRUNC:
558 return VGPU10_OPCODE_ROUND_Z;
559 case TGSI_OPCODE_SHL:
560 return VGPU10_OPCODE_ISHL;
561 case TGSI_OPCODE_AND:
562 return VGPU10_OPCODE_AND;
563 case TGSI_OPCODE_OR:
564 return VGPU10_OPCODE_OR;
565 case TGSI_OPCODE_XOR:
566 return VGPU10_OPCODE_XOR;
567 case TGSI_OPCODE_CONT:
568 return VGPU10_OPCODE_CONTINUE;
569 case TGSI_OPCODE_EMIT:
570 return VGPU10_OPCODE_EMIT;
571 case TGSI_OPCODE_ENDPRIM:
572 return VGPU10_OPCODE_CUT;
573 case TGSI_OPCODE_BGNLOOP:
574 return VGPU10_OPCODE_LOOP;
575 case TGSI_OPCODE_ENDLOOP:
576 return VGPU10_OPCODE_ENDLOOP;
577 case TGSI_OPCODE_ENDSUB:
578 return VGPU10_OPCODE_RET;
579 case TGSI_OPCODE_NOP:
580 return VGPU10_OPCODE_NOP;
581 case TGSI_OPCODE_BREAKC:
582 return VGPU10_OPCODE_BREAKC;
583 case TGSI_OPCODE_END:
584 return VGPU10_OPCODE_RET;
585 case TGSI_OPCODE_F2I:
586 return VGPU10_OPCODE_FTOI;
587 case TGSI_OPCODE_IMAX:
588 return VGPU10_OPCODE_IMAX;
589 case TGSI_OPCODE_IMIN:
590 return VGPU10_OPCODE_IMIN;
591 case TGSI_OPCODE_UDIV:
592 case TGSI_OPCODE_UMOD:
593 case TGSI_OPCODE_MOD:
594 return VGPU10_OPCODE_UDIV;
595 case TGSI_OPCODE_IMUL_HI:
596 return VGPU10_OPCODE_IMUL;
597 case TGSI_OPCODE_INEG:
598 return VGPU10_OPCODE_INEG;
599 case TGSI_OPCODE_ISHR:
600 return VGPU10_OPCODE_ISHR;
601 case TGSI_OPCODE_ISGE:
602 return VGPU10_OPCODE_IGE;
603 case TGSI_OPCODE_ISLT:
604 return VGPU10_OPCODE_ILT;
605 case TGSI_OPCODE_F2U:
606 return VGPU10_OPCODE_FTOU;
607 case TGSI_OPCODE_UADD:
608 return VGPU10_OPCODE_IADD;
609 case TGSI_OPCODE_U2F:
610 return VGPU10_OPCODE_UTOF;
611 case TGSI_OPCODE_UCMP:
612 return VGPU10_OPCODE_MOVC;
613 case TGSI_OPCODE_UMAD:
614 return VGPU10_OPCODE_UMAD;
615 case TGSI_OPCODE_UMAX:
616 return VGPU10_OPCODE_UMAX;
617 case TGSI_OPCODE_UMIN:
618 return VGPU10_OPCODE_UMIN;
619 case TGSI_OPCODE_UMUL:
620 case TGSI_OPCODE_UMUL_HI:
621 return VGPU10_OPCODE_UMUL;
622 case TGSI_OPCODE_USEQ:
623 return VGPU10_OPCODE_IEQ;
624 case TGSI_OPCODE_USGE:
625 return VGPU10_OPCODE_UGE;
626 case TGSI_OPCODE_USHR:
627 return VGPU10_OPCODE_USHR;
628 case TGSI_OPCODE_USLT:
629 return VGPU10_OPCODE_ULT;
630 case TGSI_OPCODE_USNE:
631 return VGPU10_OPCODE_INE;
632 case TGSI_OPCODE_SWITCH:
633 return VGPU10_OPCODE_SWITCH;
634 case TGSI_OPCODE_CASE:
635 return VGPU10_OPCODE_CASE;
636 case TGSI_OPCODE_DEFAULT:
637 return VGPU10_OPCODE_DEFAULT;
638 case TGSI_OPCODE_ENDSWITCH:
639 return VGPU10_OPCODE_ENDSWITCH;
640 case TGSI_OPCODE_FSLT:
641 return VGPU10_OPCODE_LT;
642 case TGSI_OPCODE_ROUND:
643 return VGPU10_OPCODE_ROUND_NE;
644 default:
645 assert(!"Unexpected TGSI opcode in translate_opcode()");
646 return VGPU10_OPCODE_NOP;
647 }
648 }
649
650
651 /**
652 * Translate a TGSI register file type into a VGPU10 operand type.
653 * \param array is the TGSI_FILE_TEMPORARY register an array?
654 */
655 static VGPU10_OPERAND_TYPE
656 translate_register_file(enum tgsi_file_type file, boolean array)
657 {
658 switch (file) {
659 case TGSI_FILE_CONSTANT:
660 return VGPU10_OPERAND_TYPE_CONSTANT_BUFFER;
661 case TGSI_FILE_INPUT:
662 return VGPU10_OPERAND_TYPE_INPUT;
663 case TGSI_FILE_OUTPUT:
664 return VGPU10_OPERAND_TYPE_OUTPUT;
665 case TGSI_FILE_TEMPORARY:
666 return array ? VGPU10_OPERAND_TYPE_INDEXABLE_TEMP
667 : VGPU10_OPERAND_TYPE_TEMP;
668 case TGSI_FILE_IMMEDIATE:
669 /* all immediates are 32-bit values at this time so
670 * VGPU10_OPERAND_TYPE_IMMEDIATE64 is not possible at this time.
671 */
672 return VGPU10_OPERAND_TYPE_IMMEDIATE_CONSTANT_BUFFER;
673 case TGSI_FILE_SAMPLER:
674 return VGPU10_OPERAND_TYPE_SAMPLER;
675 case TGSI_FILE_SYSTEM_VALUE:
676 return VGPU10_OPERAND_TYPE_INPUT;
677
678 /* XXX TODO more cases to finish */
679
680 default:
681 assert(!"Bad tgsi register file!");
682 return VGPU10_OPERAND_TYPE_NULL;
683 }
684 }
685
686
687 /**
688 * Emit a null dst register
689 */
690 static void
691 emit_null_dst_register(struct svga_shader_emitter_v10 *emit)
692 {
693 VGPU10OperandToken0 operand;
694
695 operand.value = 0;
696 operand.operandType = VGPU10_OPERAND_TYPE_NULL;
697 operand.numComponents = VGPU10_OPERAND_0_COMPONENT;
698
699 emit_dword(emit, operand.value);
700 }
701
702
703 /**
704 * If the given register is a temporary, return the array ID.
705 * Else return zero.
706 */
707 static unsigned
708 get_temp_array_id(const struct svga_shader_emitter_v10 *emit,
709 enum tgsi_file_type file, unsigned index)
710 {
711 if (file == TGSI_FILE_TEMPORARY) {
712 return emit->temp_map[index].arrayId;
713 }
714 else {
715 return 0;
716 }
717 }
718
719
720 /**
721 * If the given register is a temporary, convert the index from a TGSI
722 * TEMPORARY index to a VGPU10 temp index.
723 */
724 static unsigned
725 remap_temp_index(const struct svga_shader_emitter_v10 *emit,
726 enum tgsi_file_type file, unsigned index)
727 {
728 if (file == TGSI_FILE_TEMPORARY) {
729 return emit->temp_map[index].index;
730 }
731 else {
732 return index;
733 }
734 }
735
736
737 /**
738 * Setup the operand0 fields related to indexing (1D, 2D, relative, etc).
739 * Note: the operandType field must already be initialized.
740 */
741 static VGPU10OperandToken0
742 setup_operand0_indexing(struct svga_shader_emitter_v10 *emit,
743 VGPU10OperandToken0 operand0,
744 enum tgsi_file_type file,
745 boolean indirect, boolean index2D,
746 unsigned tempArrayID)
747 {
748 unsigned indexDim, index0Rep, index1Rep = VGPU10_OPERAND_INDEX_IMMEDIATE32;
749
750 /*
751 * Compute index dimensions
752 */
753 if (operand0.operandType == VGPU10_OPERAND_TYPE_IMMEDIATE32 ||
754 operand0.operandType == VGPU10_OPERAND_TYPE_INPUT_PRIMITIVEID) {
755 /* there's no swizzle for in-line immediates */
756 indexDim = VGPU10_OPERAND_INDEX_0D;
757 assert(operand0.selectionMode == 0);
758 }
759 else {
760 if (index2D ||
761 tempArrayID > 0 ||
762 operand0.operandType == VGPU10_OPERAND_TYPE_CONSTANT_BUFFER) {
763 indexDim = VGPU10_OPERAND_INDEX_2D;
764 }
765 else {
766 indexDim = VGPU10_OPERAND_INDEX_1D;
767 }
768 }
769
770 /*
771 * Compute index representations (immediate, relative, etc).
772 */
773 if (tempArrayID > 0) {
774 assert(file == TGSI_FILE_TEMPORARY);
775 /* First index is the array ID, second index is the array element */
776 index0Rep = VGPU10_OPERAND_INDEX_IMMEDIATE32;
777 if (indirect) {
778 index1Rep = VGPU10_OPERAND_INDEX_IMMEDIATE32_PLUS_RELATIVE;
779 }
780 else {
781 index1Rep = VGPU10_OPERAND_INDEX_IMMEDIATE32;
782 }
783 }
784 else if (indirect) {
785 if (file == TGSI_FILE_CONSTANT) {
786 /* index[0] indicates which constant buffer while index[1] indicates
787 * the position in the constant buffer.
788 */
789 index0Rep = VGPU10_OPERAND_INDEX_IMMEDIATE32;
790 index1Rep = VGPU10_OPERAND_INDEX_IMMEDIATE32_PLUS_RELATIVE;
791 }
792 else {
793 /* All other register files are 1-dimensional */
794 index0Rep = VGPU10_OPERAND_INDEX_IMMEDIATE32_PLUS_RELATIVE;
795 }
796 }
797 else {
798 index0Rep = VGPU10_OPERAND_INDEX_IMMEDIATE32;
799 index1Rep = VGPU10_OPERAND_INDEX_IMMEDIATE32;
800 }
801
802 operand0.indexDimension = indexDim;
803 operand0.index0Representation = index0Rep;
804 operand0.index1Representation = index1Rep;
805
806 return operand0;
807 }
808
809
810 /**
811 * Emit the operand for expressing an address register for indirect indexing.
812 * Note that the address register is really just a temp register.
813 * \param addr_reg_index which address register to use
814 */
815 static void
816 emit_indirect_register(struct svga_shader_emitter_v10 *emit,
817 unsigned addr_reg_index)
818 {
819 unsigned tmp_reg_index;
820 VGPU10OperandToken0 operand0;
821
822 assert(addr_reg_index < MAX_VGPU10_ADDR_REGS);
823
824 tmp_reg_index = emit->address_reg_index[addr_reg_index];
825
826 /* operand0 is a simple temporary register, selecting one component */
827 operand0.value = 0;
828 operand0.operandType = VGPU10_OPERAND_TYPE_TEMP;
829 operand0.numComponents = VGPU10_OPERAND_4_COMPONENT;
830 operand0.indexDimension = VGPU10_OPERAND_INDEX_1D;
831 operand0.index0Representation = VGPU10_OPERAND_INDEX_IMMEDIATE32;
832 operand0.selectionMode = VGPU10_OPERAND_4_COMPONENT_SELECT_1_MODE;
833 operand0.swizzleX = 0;
834 operand0.swizzleY = 1;
835 operand0.swizzleZ = 2;
836 operand0.swizzleW = 3;
837
838 emit_dword(emit, operand0.value);
839 emit_dword(emit, remap_temp_index(emit, TGSI_FILE_TEMPORARY, tmp_reg_index));
840 }
841
842
843 /**
844 * Translate the dst register of a TGSI instruction and emit VGPU10 tokens.
845 * \param emit the emitter context
846 * \param reg the TGSI dst register to translate
847 */
848 static void
849 emit_dst_register(struct svga_shader_emitter_v10 *emit,
850 const struct tgsi_full_dst_register *reg)
851 {
852 enum tgsi_file_type file = reg->Register.File;
853 unsigned index = reg->Register.Index;
854 const enum tgsi_semantic sem_name = emit->info.output_semantic_name[index];
855 const unsigned sem_index = emit->info.output_semantic_index[index];
856 unsigned writemask = reg->Register.WriteMask;
857 const unsigned indirect = reg->Register.Indirect;
858 const unsigned tempArrayId = get_temp_array_id(emit, file, index);
859 const unsigned index2d = reg->Register.Dimension;
860 VGPU10OperandToken0 operand0;
861
862 if (file == TGSI_FILE_OUTPUT) {
863 if (emit->unit == PIPE_SHADER_VERTEX ||
864 emit->unit == PIPE_SHADER_GEOMETRY) {
865 if (index == emit->vposition.out_index &&
866 emit->vposition.tmp_index != INVALID_INDEX) {
867 /* replace OUTPUT[POS] with TEMP[POS]. We need to store the
868 * vertex position result in a temporary so that we can modify
869 * it in the post_helper() code.
870 */
871 file = TGSI_FILE_TEMPORARY;
872 index = emit->vposition.tmp_index;
873 }
874 else if (sem_name == TGSI_SEMANTIC_CLIPDIST &&
875 emit->clip_dist_tmp_index != INVALID_INDEX) {
876 /* replace OUTPUT[CLIPDIST] with TEMP[CLIPDIST].
877 * We store the clip distance in a temporary first, then
878 * we'll copy it to the shadow copy and to CLIPDIST with the
879 * enabled planes mask in emit_clip_distance_instructions().
880 */
881 file = TGSI_FILE_TEMPORARY;
882 index = emit->clip_dist_tmp_index + sem_index;
883 }
884 else if (sem_name == TGSI_SEMANTIC_CLIPVERTEX &&
885 emit->clip_vertex_tmp_index != INVALID_INDEX) {
886 /* replace the CLIPVERTEX output register with a temporary */
887 assert(emit->clip_mode == CLIP_VERTEX);
888 assert(sem_index == 0);
889 file = TGSI_FILE_TEMPORARY;
890 index = emit->clip_vertex_tmp_index;
891 }
892 }
893 else if (emit->unit == PIPE_SHADER_FRAGMENT) {
894 if (sem_name == TGSI_SEMANTIC_POSITION) {
895 /* Fragment depth output register */
896 operand0.value = 0;
897 operand0.operandType = VGPU10_OPERAND_TYPE_OUTPUT_DEPTH;
898 operand0.indexDimension = VGPU10_OPERAND_INDEX_0D;
899 operand0.numComponents = VGPU10_OPERAND_1_COMPONENT;
900 emit_dword(emit, operand0.value);
901 return;
902 }
903 else if (index == emit->fs.color_out_index[0] &&
904 emit->fs.color_tmp_index != INVALID_INDEX) {
905 /* replace OUTPUT[COLOR] with TEMP[COLOR]. We need to store the
906 * fragment color result in a temporary so that we can read it
907 * it in the post_helper() code.
908 */
909 file = TGSI_FILE_TEMPORARY;
910 index = emit->fs.color_tmp_index;
911 }
912 else {
913 /* Typically, for fragment shaders, the output register index
914 * matches the color semantic index. But not when we write to
915 * the fragment depth register. In that case, OUT[0] will be
916 * fragdepth and OUT[1] will be the 0th color output. We need
917 * to use the semantic index for color outputs.
918 */
919 assert(sem_name == TGSI_SEMANTIC_COLOR);
920 index = emit->info.output_semantic_index[index];
921
922 emit->num_output_writes++;
923 }
924 }
925 }
926
927 /* init operand tokens to all zero */
928 operand0.value = 0;
929
930 operand0.numComponents = VGPU10_OPERAND_4_COMPONENT;
931
932 /* the operand has a writemask */
933 operand0.selectionMode = VGPU10_OPERAND_4_COMPONENT_MASK_MODE;
934
935 /* Which of the four dest components to write to. Note that we can use a
936 * simple assignment here since TGSI writemasks match VGPU10 writemasks.
937 */
938 STATIC_ASSERT(TGSI_WRITEMASK_X == VGPU10_OPERAND_4_COMPONENT_MASK_X);
939 operand0.mask = writemask;
940
941 /* translate TGSI register file type to VGPU10 operand type */
942 operand0.operandType = translate_register_file(file, tempArrayId > 0);
943
944 check_register_index(emit, operand0.operandType, index);
945
946 operand0 = setup_operand0_indexing(emit, operand0, file, indirect,
947 index2d, tempArrayId);
948
949 /* Emit tokens */
950 emit_dword(emit, operand0.value);
951 if (tempArrayId > 0) {
952 emit_dword(emit, tempArrayId);
953 }
954
955 emit_dword(emit, remap_temp_index(emit, file, index));
956
957 if (indirect) {
958 emit_indirect_register(emit, reg->Indirect.Index);
959 }
960 }
961
962
963 /**
964 * Translate a src register of a TGSI instruction and emit VGPU10 tokens.
965 */
966 static void
967 emit_src_register(struct svga_shader_emitter_v10 *emit,
968 const struct tgsi_full_src_register *reg)
969 {
970 enum tgsi_file_type file = reg->Register.File;
971 unsigned index = reg->Register.Index;
972 const unsigned indirect = reg->Register.Indirect;
973 const unsigned tempArrayId = get_temp_array_id(emit, file, index);
974 const unsigned index2d = reg->Register.Dimension;
975 const unsigned swizzleX = reg->Register.SwizzleX;
976 const unsigned swizzleY = reg->Register.SwizzleY;
977 const unsigned swizzleZ = reg->Register.SwizzleZ;
978 const unsigned swizzleW = reg->Register.SwizzleW;
979 const unsigned absolute = reg->Register.Absolute;
980 const unsigned negate = reg->Register.Negate;
981 bool is_prim_id = FALSE;
982
983 VGPU10OperandToken0 operand0;
984 VGPU10OperandToken1 operand1;
985
986 if (emit->unit == PIPE_SHADER_FRAGMENT &&
987 file == TGSI_FILE_INPUT) {
988 if (index == emit->fs.face_input_index) {
989 /* Replace INPUT[FACE] with TEMP[FACE] */
990 file = TGSI_FILE_TEMPORARY;
991 index = emit->fs.face_tmp_index;
992 }
993 else if (index == emit->fs.fragcoord_input_index) {
994 /* Replace INPUT[POSITION] with TEMP[POSITION] */
995 file = TGSI_FILE_TEMPORARY;
996 index = emit->fs.fragcoord_tmp_index;
997 }
998 else {
999 /* We remap fragment shader inputs to that FS input indexes
1000 * match up with VS/GS output indexes.
1001 */
1002 index = emit->linkage.input_map[index];
1003 }
1004 }
1005 else if (emit->unit == PIPE_SHADER_GEOMETRY &&
1006 file == TGSI_FILE_INPUT) {
1007 is_prim_id = (index == emit->gs.prim_id_index);
1008 index = emit->linkage.input_map[index];
1009 }
1010 else if (emit->unit == PIPE_SHADER_VERTEX) {
1011 if (file == TGSI_FILE_INPUT) {
1012 /* if input is adjusted... */
1013 if ((emit->key.vs.adjust_attrib_w_1 |
1014 emit->key.vs.adjust_attrib_itof |
1015 emit->key.vs.adjust_attrib_utof |
1016 emit->key.vs.attrib_is_bgra |
1017 emit->key.vs.attrib_puint_to_snorm |
1018 emit->key.vs.attrib_puint_to_uscaled |
1019 emit->key.vs.attrib_puint_to_sscaled) & (1 << index)) {
1020 file = TGSI_FILE_TEMPORARY;
1021 index = emit->vs.adjusted_input[index];
1022 }
1023 }
1024 else if (file == TGSI_FILE_SYSTEM_VALUE) {
1025 assert(index < ARRAY_SIZE(emit->system_value_indexes));
1026 index = emit->system_value_indexes[index];
1027 }
1028 }
1029
1030 operand0.value = operand1.value = 0;
1031
1032 if (is_prim_id) {
1033 /* NOTE: we should be using VGPU10_OPERAND_1_COMPONENT here, but
1034 * our virtual GPU accepts this as-is.
1035 */
1036 operand0.numComponents = VGPU10_OPERAND_0_COMPONENT;
1037 operand0.operandType = VGPU10_OPERAND_TYPE_INPUT_PRIMITIVEID;
1038 }
1039 else {
1040 operand0.numComponents = VGPU10_OPERAND_4_COMPONENT;
1041 operand0.operandType = translate_register_file(file, tempArrayId > 0);
1042 }
1043
1044 operand0 = setup_operand0_indexing(emit, operand0, file, indirect,
1045 index2d, tempArrayId);
1046
1047 if (operand0.operandType != VGPU10_OPERAND_TYPE_IMMEDIATE32 &&
1048 operand0.operandType != VGPU10_OPERAND_TYPE_INPUT_PRIMITIVEID) {
1049 /* there's no swizzle for in-line immediates */
1050 if (swizzleX == swizzleY &&
1051 swizzleX == swizzleZ &&
1052 swizzleX == swizzleW) {
1053 operand0.selectionMode = VGPU10_OPERAND_4_COMPONENT_SELECT_1_MODE;
1054 }
1055 else {
1056 operand0.selectionMode = VGPU10_OPERAND_4_COMPONENT_SWIZZLE_MODE;
1057 }
1058
1059 operand0.swizzleX = swizzleX;
1060 operand0.swizzleY = swizzleY;
1061 operand0.swizzleZ = swizzleZ;
1062 operand0.swizzleW = swizzleW;
1063
1064 if (absolute || negate) {
1065 operand0.extended = 1;
1066 operand1.extendedOperandType = VGPU10_EXTENDED_OPERAND_MODIFIER;
1067 if (absolute && !negate)
1068 operand1.operandModifier = VGPU10_OPERAND_MODIFIER_ABS;
1069 if (!absolute && negate)
1070 operand1.operandModifier = VGPU10_OPERAND_MODIFIER_NEG;
1071 if (absolute && negate)
1072 operand1.operandModifier = VGPU10_OPERAND_MODIFIER_ABSNEG;
1073 }
1074 }
1075
1076 /* Emit the operand tokens */
1077 emit_dword(emit, operand0.value);
1078 if (operand0.extended)
1079 emit_dword(emit, operand1.value);
1080
1081 if (operand0.operandType == VGPU10_OPERAND_TYPE_IMMEDIATE32) {
1082 /* Emit the four float/int in-line immediate values */
1083 unsigned *c;
1084 assert(index < ARRAY_SIZE(emit->immediates));
1085 assert(file == TGSI_FILE_IMMEDIATE);
1086 assert(swizzleX < 4);
1087 assert(swizzleY < 4);
1088 assert(swizzleZ < 4);
1089 assert(swizzleW < 4);
1090 c = (unsigned *) emit->immediates[index];
1091 emit_dword(emit, c[swizzleX]);
1092 emit_dword(emit, c[swizzleY]);
1093 emit_dword(emit, c[swizzleZ]);
1094 emit_dword(emit, c[swizzleW]);
1095 }
1096 else if (operand0.indexDimension >= VGPU10_OPERAND_INDEX_1D) {
1097 /* Emit the register index(es) */
1098 if (index2d ||
1099 operand0.operandType == VGPU10_OPERAND_TYPE_CONSTANT_BUFFER) {
1100 emit_dword(emit, reg->Dimension.Index);
1101 }
1102
1103 if (tempArrayId > 0) {
1104 emit_dword(emit, tempArrayId);
1105 }
1106
1107 emit_dword(emit, remap_temp_index(emit, file, index));
1108
1109 if (indirect) {
1110 emit_indirect_register(emit, reg->Indirect.Index);
1111 }
1112 }
1113 }
1114
1115
1116 /**
1117 * Emit a resource operand (for use with a SAMPLE instruction).
1118 */
1119 static void
1120 emit_resource_register(struct svga_shader_emitter_v10 *emit,
1121 unsigned resource_number)
1122 {
1123 VGPU10OperandToken0 operand0;
1124
1125 check_register_index(emit, VGPU10_OPERAND_TYPE_RESOURCE, resource_number);
1126
1127 /* init */
1128 operand0.value = 0;
1129
1130 operand0.operandType = VGPU10_OPERAND_TYPE_RESOURCE;
1131 operand0.indexDimension = VGPU10_OPERAND_INDEX_1D;
1132 operand0.numComponents = VGPU10_OPERAND_4_COMPONENT;
1133 operand0.selectionMode = VGPU10_OPERAND_4_COMPONENT_SWIZZLE_MODE;
1134 operand0.swizzleX = VGPU10_COMPONENT_X;
1135 operand0.swizzleY = VGPU10_COMPONENT_Y;
1136 operand0.swizzleZ = VGPU10_COMPONENT_Z;
1137 operand0.swizzleW = VGPU10_COMPONENT_W;
1138
1139 emit_dword(emit, operand0.value);
1140 emit_dword(emit, resource_number);
1141 }
1142
1143
1144 /**
1145 * Emit a sampler operand (for use with a SAMPLE instruction).
1146 */
1147 static void
1148 emit_sampler_register(struct svga_shader_emitter_v10 *emit,
1149 unsigned sampler_number)
1150 {
1151 VGPU10OperandToken0 operand0;
1152
1153 check_register_index(emit, VGPU10_OPERAND_TYPE_SAMPLER, sampler_number);
1154
1155 /* init */
1156 operand0.value = 0;
1157
1158 operand0.operandType = VGPU10_OPERAND_TYPE_SAMPLER;
1159 operand0.indexDimension = VGPU10_OPERAND_INDEX_1D;
1160
1161 emit_dword(emit, operand0.value);
1162 emit_dword(emit, sampler_number);
1163 }
1164
1165
1166 /**
1167 * Emit an operand which reads the IS_FRONT_FACING register.
1168 */
1169 static void
1170 emit_face_register(struct svga_shader_emitter_v10 *emit)
1171 {
1172 VGPU10OperandToken0 operand0;
1173 unsigned index = emit->linkage.input_map[emit->fs.face_input_index];
1174
1175 /* init */
1176 operand0.value = 0;
1177
1178 operand0.operandType = VGPU10_OPERAND_TYPE_INPUT;
1179 operand0.indexDimension = VGPU10_OPERAND_INDEX_1D;
1180 operand0.selectionMode = VGPU10_OPERAND_4_COMPONENT_SELECT_1_MODE;
1181 operand0.numComponents = VGPU10_OPERAND_4_COMPONENT;
1182
1183 operand0.swizzleX = VGPU10_COMPONENT_X;
1184 operand0.swizzleY = VGPU10_COMPONENT_X;
1185 operand0.swizzleZ = VGPU10_COMPONENT_X;
1186 operand0.swizzleW = VGPU10_COMPONENT_X;
1187
1188 emit_dword(emit, operand0.value);
1189 emit_dword(emit, index);
1190 }
1191
1192
1193 /**
1194 * Emit the token for a VGPU10 opcode.
1195 * \param saturate clamp result to [0,1]?
1196 */
1197 static void
1198 emit_opcode(struct svga_shader_emitter_v10 *emit,
1199 unsigned vgpu10_opcode, boolean saturate)
1200 {
1201 VGPU10OpcodeToken0 token0;
1202
1203 token0.value = 0; /* init all fields to zero */
1204 token0.opcodeType = vgpu10_opcode;
1205 token0.instructionLength = 0; /* Filled in by end_emit_instruction() */
1206 token0.saturate = saturate;
1207
1208 emit_dword(emit, token0.value);
1209 }
1210
1211
1212 /**
1213 * Emit the token for a VGPU10 resinfo instruction.
1214 * \param modifier return type modifier, _uint or _rcpFloat.
1215 * TODO: We may want to remove this parameter if it will
1216 * only ever be used as _uint.
1217 */
1218 static void
1219 emit_opcode_resinfo(struct svga_shader_emitter_v10 *emit,
1220 VGPU10_RESINFO_RETURN_TYPE modifier)
1221 {
1222 VGPU10OpcodeToken0 token0;
1223
1224 token0.value = 0; /* init all fields to zero */
1225 token0.opcodeType = VGPU10_OPCODE_RESINFO;
1226 token0.instructionLength = 0; /* Filled in by end_emit_instruction() */
1227 token0.resinfoReturnType = modifier;
1228
1229 emit_dword(emit, token0.value);
1230 }
1231
1232
1233 /**
1234 * Emit opcode tokens for a texture sample instruction. Texture instructions
1235 * can be rather complicated (texel offsets, etc) so we have this specialized
1236 * function.
1237 */
1238 static void
1239 emit_sample_opcode(struct svga_shader_emitter_v10 *emit,
1240 unsigned vgpu10_opcode, boolean saturate,
1241 const int offsets[3])
1242 {
1243 VGPU10OpcodeToken0 token0;
1244 VGPU10OpcodeToken1 token1;
1245
1246 token0.value = 0; /* init all fields to zero */
1247 token0.opcodeType = vgpu10_opcode;
1248 token0.instructionLength = 0; /* Filled in by end_emit_instruction() */
1249 token0.saturate = saturate;
1250
1251 if (offsets[0] || offsets[1] || offsets[2]) {
1252 assert(offsets[0] >= VGPU10_MIN_TEXEL_FETCH_OFFSET);
1253 assert(offsets[1] >= VGPU10_MIN_TEXEL_FETCH_OFFSET);
1254 assert(offsets[2] >= VGPU10_MIN_TEXEL_FETCH_OFFSET);
1255 assert(offsets[0] <= VGPU10_MAX_TEXEL_FETCH_OFFSET);
1256 assert(offsets[1] <= VGPU10_MAX_TEXEL_FETCH_OFFSET);
1257 assert(offsets[2] <= VGPU10_MAX_TEXEL_FETCH_OFFSET);
1258
1259 token0.extended = 1;
1260 token1.value = 0;
1261 token1.opcodeType = VGPU10_EXTENDED_OPCODE_SAMPLE_CONTROLS;
1262 token1.offsetU = offsets[0];
1263 token1.offsetV = offsets[1];
1264 token1.offsetW = offsets[2];
1265 }
1266
1267 emit_dword(emit, token0.value);
1268 if (token0.extended) {
1269 emit_dword(emit, token1.value);
1270 }
1271 }
1272
1273
1274 /**
1275 * Emit a DISCARD opcode token.
1276 * If nonzero is set, we'll discard the fragment if the X component is not 0.
1277 * Otherwise, we'll discard the fragment if the X component is 0.
1278 */
1279 static void
1280 emit_discard_opcode(struct svga_shader_emitter_v10 *emit, boolean nonzero)
1281 {
1282 VGPU10OpcodeToken0 opcode0;
1283
1284 opcode0.value = 0;
1285 opcode0.opcodeType = VGPU10_OPCODE_DISCARD;
1286 if (nonzero)
1287 opcode0.testBoolean = VGPU10_INSTRUCTION_TEST_NONZERO;
1288
1289 emit_dword(emit, opcode0.value);
1290 }
1291
1292
1293 /**
1294 * We need to call this before we begin emitting a VGPU10 instruction.
1295 */
1296 static void
1297 begin_emit_instruction(struct svga_shader_emitter_v10 *emit)
1298 {
1299 assert(emit->inst_start_token == 0);
1300 /* Save location of the instruction's VGPU10OpcodeToken0 token.
1301 * Note, we can't save a pointer because it would become invalid if
1302 * we have to realloc the output buffer.
1303 */
1304 emit->inst_start_token = emit_get_num_tokens(emit);
1305 }
1306
1307
1308 /**
1309 * We need to call this after we emit the last token of a VGPU10 instruction.
1310 * This function patches in the opcode token's instructionLength field.
1311 */
1312 static void
1313 end_emit_instruction(struct svga_shader_emitter_v10 *emit)
1314 {
1315 VGPU10OpcodeToken0 *tokens = (VGPU10OpcodeToken0 *) emit->buf;
1316 unsigned inst_length;
1317
1318 assert(emit->inst_start_token > 0);
1319
1320 if (emit->discard_instruction) {
1321 /* Back up the emit->ptr to where this instruction started so
1322 * that we discard the current instruction.
1323 */
1324 emit->ptr = (char *) (tokens + emit->inst_start_token);
1325 }
1326 else {
1327 /* Compute instruction length and patch that into the start of
1328 * the instruction.
1329 */
1330 inst_length = emit_get_num_tokens(emit) - emit->inst_start_token;
1331
1332 assert(inst_length > 0);
1333
1334 tokens[emit->inst_start_token].instructionLength = inst_length;
1335 }
1336
1337 emit->inst_start_token = 0; /* reset to zero for error checking */
1338 emit->discard_instruction = FALSE;
1339 }
1340
1341
1342 /**
1343 * Return index for a free temporary register.
1344 */
1345 static unsigned
1346 get_temp_index(struct svga_shader_emitter_v10 *emit)
1347 {
1348 assert(emit->internal_temp_count < MAX_INTERNAL_TEMPS);
1349 return emit->num_shader_temps + emit->internal_temp_count++;
1350 }
1351
1352
1353 /**
1354 * Release the temporaries which were generated by get_temp_index().
1355 */
1356 static void
1357 free_temp_indexes(struct svga_shader_emitter_v10 *emit)
1358 {
1359 emit->internal_temp_count = 0;
1360 }
1361
1362
1363 /**
1364 * Create a tgsi_full_src_register.
1365 */
1366 static struct tgsi_full_src_register
1367 make_src_reg(enum tgsi_file_type file, unsigned index)
1368 {
1369 struct tgsi_full_src_register reg;
1370
1371 memset(&reg, 0, sizeof(reg));
1372 reg.Register.File = file;
1373 reg.Register.Index = index;
1374 reg.Register.SwizzleX = TGSI_SWIZZLE_X;
1375 reg.Register.SwizzleY = TGSI_SWIZZLE_Y;
1376 reg.Register.SwizzleZ = TGSI_SWIZZLE_Z;
1377 reg.Register.SwizzleW = TGSI_SWIZZLE_W;
1378 return reg;
1379 }
1380
1381
1382 /**
1383 * Create a tgsi_full_src_register for a temporary.
1384 */
1385 static struct tgsi_full_src_register
1386 make_src_temp_reg(unsigned index)
1387 {
1388 return make_src_reg(TGSI_FILE_TEMPORARY, index);
1389 }
1390
1391
1392 /**
1393 * Create a tgsi_full_src_register for a constant.
1394 */
1395 static struct tgsi_full_src_register
1396 make_src_const_reg(unsigned index)
1397 {
1398 return make_src_reg(TGSI_FILE_CONSTANT, index);
1399 }
1400
1401
1402 /**
1403 * Create a tgsi_full_src_register for an immediate constant.
1404 */
1405 static struct tgsi_full_src_register
1406 make_src_immediate_reg(unsigned index)
1407 {
1408 return make_src_reg(TGSI_FILE_IMMEDIATE, index);
1409 }
1410
1411
1412 /**
1413 * Create a tgsi_full_dst_register.
1414 */
1415 static struct tgsi_full_dst_register
1416 make_dst_reg(enum tgsi_file_type file, unsigned index)
1417 {
1418 struct tgsi_full_dst_register reg;
1419
1420 memset(&reg, 0, sizeof(reg));
1421 reg.Register.File = file;
1422 reg.Register.Index = index;
1423 reg.Register.WriteMask = TGSI_WRITEMASK_XYZW;
1424 return reg;
1425 }
1426
1427
1428 /**
1429 * Create a tgsi_full_dst_register for a temporary.
1430 */
1431 static struct tgsi_full_dst_register
1432 make_dst_temp_reg(unsigned index)
1433 {
1434 return make_dst_reg(TGSI_FILE_TEMPORARY, index);
1435 }
1436
1437
1438 /**
1439 * Create a tgsi_full_dst_register for an output.
1440 */
1441 static struct tgsi_full_dst_register
1442 make_dst_output_reg(unsigned index)
1443 {
1444 return make_dst_reg(TGSI_FILE_OUTPUT, index);
1445 }
1446
1447
1448 /**
1449 * Create negated tgsi_full_src_register.
1450 */
1451 static struct tgsi_full_src_register
1452 negate_src(const struct tgsi_full_src_register *reg)
1453 {
1454 struct tgsi_full_src_register neg = *reg;
1455 neg.Register.Negate = !reg->Register.Negate;
1456 return neg;
1457 }
1458
1459 /**
1460 * Create absolute value of a tgsi_full_src_register.
1461 */
1462 static struct tgsi_full_src_register
1463 absolute_src(const struct tgsi_full_src_register *reg)
1464 {
1465 struct tgsi_full_src_register absolute = *reg;
1466 absolute.Register.Absolute = 1;
1467 return absolute;
1468 }
1469
1470
1471 /** Return the named swizzle term from the src register */
1472 static inline unsigned
1473 get_swizzle(const struct tgsi_full_src_register *reg, enum tgsi_swizzle term)
1474 {
1475 switch (term) {
1476 case TGSI_SWIZZLE_X:
1477 return reg->Register.SwizzleX;
1478 case TGSI_SWIZZLE_Y:
1479 return reg->Register.SwizzleY;
1480 case TGSI_SWIZZLE_Z:
1481 return reg->Register.SwizzleZ;
1482 case TGSI_SWIZZLE_W:
1483 return reg->Register.SwizzleW;
1484 default:
1485 assert(!"Bad swizzle");
1486 return TGSI_SWIZZLE_X;
1487 }
1488 }
1489
1490
1491 /**
1492 * Create swizzled tgsi_full_src_register.
1493 */
1494 static struct tgsi_full_src_register
1495 swizzle_src(const struct tgsi_full_src_register *reg,
1496 enum tgsi_swizzle swizzleX, enum tgsi_swizzle swizzleY,
1497 enum tgsi_swizzle swizzleZ, enum tgsi_swizzle swizzleW)
1498 {
1499 struct tgsi_full_src_register swizzled = *reg;
1500 /* Note: we swizzle the current swizzle */
1501 swizzled.Register.SwizzleX = get_swizzle(reg, swizzleX);
1502 swizzled.Register.SwizzleY = get_swizzle(reg, swizzleY);
1503 swizzled.Register.SwizzleZ = get_swizzle(reg, swizzleZ);
1504 swizzled.Register.SwizzleW = get_swizzle(reg, swizzleW);
1505 return swizzled;
1506 }
1507
1508
1509 /**
1510 * Create swizzled tgsi_full_src_register where all the swizzle
1511 * terms are the same.
1512 */
1513 static struct tgsi_full_src_register
1514 scalar_src(const struct tgsi_full_src_register *reg, enum tgsi_swizzle swizzle)
1515 {
1516 struct tgsi_full_src_register swizzled = *reg;
1517 /* Note: we swizzle the current swizzle */
1518 swizzled.Register.SwizzleX =
1519 swizzled.Register.SwizzleY =
1520 swizzled.Register.SwizzleZ =
1521 swizzled.Register.SwizzleW = get_swizzle(reg, swizzle);
1522 return swizzled;
1523 }
1524
1525
1526 /**
1527 * Create new tgsi_full_dst_register with writemask.
1528 * \param mask bitmask of TGSI_WRITEMASK_[XYZW]
1529 */
1530 static struct tgsi_full_dst_register
1531 writemask_dst(const struct tgsi_full_dst_register *reg, unsigned mask)
1532 {
1533 struct tgsi_full_dst_register masked = *reg;
1534 masked.Register.WriteMask = mask;
1535 return masked;
1536 }
1537
1538
1539 /**
1540 * Check if the register's swizzle is XXXX, YYYY, ZZZZ, or WWWW.
1541 */
1542 static boolean
1543 same_swizzle_terms(const struct tgsi_full_src_register *reg)
1544 {
1545 return (reg->Register.SwizzleX == reg->Register.SwizzleY &&
1546 reg->Register.SwizzleY == reg->Register.SwizzleZ &&
1547 reg->Register.SwizzleZ == reg->Register.SwizzleW);
1548 }
1549
1550
1551 /**
1552 * Search the vector for the value 'x' and return its position.
1553 */
1554 static int
1555 find_imm_in_vec4(const union tgsi_immediate_data vec[4],
1556 union tgsi_immediate_data x)
1557 {
1558 unsigned i;
1559 for (i = 0; i < 4; i++) {
1560 if (vec[i].Int == x.Int)
1561 return i;
1562 }
1563 return -1;
1564 }
1565
1566
1567 /**
1568 * Helper used by make_immediate_reg(), make_immediate_reg_4().
1569 */
1570 static int
1571 find_immediate(struct svga_shader_emitter_v10 *emit,
1572 union tgsi_immediate_data x, unsigned startIndex)
1573 {
1574 const unsigned endIndex = emit->num_immediates;
1575 unsigned i;
1576
1577 assert(emit->immediates_emitted);
1578
1579 /* Search immediates for x, y, z, w */
1580 for (i = startIndex; i < endIndex; i++) {
1581 if (x.Int == emit->immediates[i][0].Int ||
1582 x.Int == emit->immediates[i][1].Int ||
1583 x.Int == emit->immediates[i][2].Int ||
1584 x.Int == emit->immediates[i][3].Int) {
1585 return i;
1586 }
1587 }
1588 /* Should never try to use an immediate value that wasn't pre-declared */
1589 assert(!"find_immediate() failed!");
1590 return -1;
1591 }
1592
1593
1594 /**
1595 * Return a tgsi_full_src_register for an immediate/literal
1596 * union tgsi_immediate_data[4] value.
1597 * Note: the values must have been previously declared/allocated in
1598 * emit_pre_helpers(). And, all of x,y,z,w must be located in the same
1599 * vec4 immediate.
1600 */
1601 static struct tgsi_full_src_register
1602 make_immediate_reg_4(struct svga_shader_emitter_v10 *emit,
1603 const union tgsi_immediate_data imm[4])
1604 {
1605 struct tgsi_full_src_register reg;
1606 unsigned i;
1607
1608 for (i = 0; i < emit->num_common_immediates; i++) {
1609 /* search for first component value */
1610 int immpos = find_immediate(emit, imm[0], i);
1611 int x, y, z, w;
1612
1613 assert(immpos >= 0);
1614
1615 /* find remaining components within the immediate vector */
1616 x = find_imm_in_vec4(emit->immediates[immpos], imm[0]);
1617 y = find_imm_in_vec4(emit->immediates[immpos], imm[1]);
1618 z = find_imm_in_vec4(emit->immediates[immpos], imm[2]);
1619 w = find_imm_in_vec4(emit->immediates[immpos], imm[3]);
1620
1621 if (x >=0 && y >= 0 && z >= 0 && w >= 0) {
1622 /* found them all */
1623 memset(&reg, 0, sizeof(reg));
1624 reg.Register.File = TGSI_FILE_IMMEDIATE;
1625 reg.Register.Index = immpos;
1626 reg.Register.SwizzleX = x;
1627 reg.Register.SwizzleY = y;
1628 reg.Register.SwizzleZ = z;
1629 reg.Register.SwizzleW = w;
1630 return reg;
1631 }
1632 /* else, keep searching */
1633 }
1634
1635 assert(!"Failed to find immediate register!");
1636
1637 /* Just return IMM[0].xxxx */
1638 memset(&reg, 0, sizeof(reg));
1639 reg.Register.File = TGSI_FILE_IMMEDIATE;
1640 return reg;
1641 }
1642
1643
1644 /**
1645 * Return a tgsi_full_src_register for an immediate/literal
1646 * union tgsi_immediate_data value of the form {value, value, value, value}.
1647 * \sa make_immediate_reg_4() regarding allowed values.
1648 */
1649 static struct tgsi_full_src_register
1650 make_immediate_reg(struct svga_shader_emitter_v10 *emit,
1651 union tgsi_immediate_data value)
1652 {
1653 struct tgsi_full_src_register reg;
1654 int immpos = find_immediate(emit, value, 0);
1655
1656 assert(immpos >= 0);
1657
1658 memset(&reg, 0, sizeof(reg));
1659 reg.Register.File = TGSI_FILE_IMMEDIATE;
1660 reg.Register.Index = immpos;
1661 reg.Register.SwizzleX =
1662 reg.Register.SwizzleY =
1663 reg.Register.SwizzleZ =
1664 reg.Register.SwizzleW = find_imm_in_vec4(emit->immediates[immpos], value);
1665
1666 return reg;
1667 }
1668
1669
1670 /**
1671 * Return a tgsi_full_src_register for an immediate/literal float[4] value.
1672 * \sa make_immediate_reg_4() regarding allowed values.
1673 */
1674 static struct tgsi_full_src_register
1675 make_immediate_reg_float4(struct svga_shader_emitter_v10 *emit,
1676 float x, float y, float z, float w)
1677 {
1678 union tgsi_immediate_data imm[4];
1679 imm[0].Float = x;
1680 imm[1].Float = y;
1681 imm[2].Float = z;
1682 imm[3].Float = w;
1683 return make_immediate_reg_4(emit, imm);
1684 }
1685
1686
1687 /**
1688 * Return a tgsi_full_src_register for an immediate/literal float value
1689 * of the form {value, value, value, value}.
1690 * \sa make_immediate_reg_4() regarding allowed values.
1691 */
1692 static struct tgsi_full_src_register
1693 make_immediate_reg_float(struct svga_shader_emitter_v10 *emit, float value)
1694 {
1695 union tgsi_immediate_data imm;
1696 imm.Float = value;
1697 return make_immediate_reg(emit, imm);
1698 }
1699
1700
1701 /**
1702 * Return a tgsi_full_src_register for an immediate/literal int[4] vector.
1703 */
1704 static struct tgsi_full_src_register
1705 make_immediate_reg_int4(struct svga_shader_emitter_v10 *emit,
1706 int x, int y, int z, int w)
1707 {
1708 union tgsi_immediate_data imm[4];
1709 imm[0].Int = x;
1710 imm[1].Int = y;
1711 imm[2].Int = z;
1712 imm[3].Int = w;
1713 return make_immediate_reg_4(emit, imm);
1714 }
1715
1716
1717 /**
1718 * Return a tgsi_full_src_register for an immediate/literal int value
1719 * of the form {value, value, value, value}.
1720 * \sa make_immediate_reg_4() regarding allowed values.
1721 */
1722 static struct tgsi_full_src_register
1723 make_immediate_reg_int(struct svga_shader_emitter_v10 *emit, int value)
1724 {
1725 union tgsi_immediate_data imm;
1726 imm.Int = value;
1727 return make_immediate_reg(emit, imm);
1728 }
1729
1730
1731 /**
1732 * Allocate space for a union tgsi_immediate_data[4] immediate.
1733 * \return the index/position of the immediate.
1734 */
1735 static unsigned
1736 alloc_immediate_4(struct svga_shader_emitter_v10 *emit,
1737 const union tgsi_immediate_data imm[4])
1738 {
1739 unsigned n = emit->num_immediates++;
1740 assert(!emit->immediates_emitted);
1741 assert(n < ARRAY_SIZE(emit->immediates));
1742 emit->immediates[n][0] = imm[0];
1743 emit->immediates[n][1] = imm[1];
1744 emit->immediates[n][2] = imm[2];
1745 emit->immediates[n][3] = imm[3];
1746 return n;
1747 }
1748
1749
1750 /**
1751 * Allocate space for a float[4] immediate.
1752 * \return the index/position of the immediate.
1753 */
1754 static unsigned
1755 alloc_immediate_float4(struct svga_shader_emitter_v10 *emit,
1756 float x, float y, float z, float w)
1757 {
1758 union tgsi_immediate_data imm[4];
1759 imm[0].Float = x;
1760 imm[1].Float = y;
1761 imm[2].Float = z;
1762 imm[3].Float = w;
1763 return alloc_immediate_4(emit, imm);
1764 }
1765
1766
1767 /**
1768 * Allocate space for an int[4] immediate.
1769 * \return the index/position of the immediate.
1770 */
1771 static unsigned
1772 alloc_immediate_int4(struct svga_shader_emitter_v10 *emit,
1773 int x, int y, int z, int w)
1774 {
1775 union tgsi_immediate_data imm[4];
1776 imm[0].Int = x;
1777 imm[1].Int = y;
1778 imm[2].Int = z;
1779 imm[3].Int = w;
1780 return alloc_immediate_4(emit, imm);
1781 }
1782
1783
1784 /**
1785 * Allocate a shader input to store a system value.
1786 */
1787 static unsigned
1788 alloc_system_value_index(struct svga_shader_emitter_v10 *emit, unsigned index)
1789 {
1790 const unsigned n = emit->info.file_max[TGSI_FILE_INPUT] + 1 + index;
1791 assert(index < ARRAY_SIZE(emit->system_value_indexes));
1792 emit->system_value_indexes[index] = n;
1793 return n;
1794 }
1795
1796
1797 /**
1798 * Translate a TGSI immediate value (union tgsi_immediate_data[4]) to VGPU10.
1799 */
1800 static boolean
1801 emit_vgpu10_immediate(struct svga_shader_emitter_v10 *emit,
1802 const struct tgsi_full_immediate *imm)
1803 {
1804 /* We don't actually emit any code here. We just save the
1805 * immediate values and emit them later.
1806 */
1807 alloc_immediate_4(emit, imm->u);
1808 return TRUE;
1809 }
1810
1811
1812 /**
1813 * Emit a VGPU10_CUSTOMDATA_DCL_IMMEDIATE_CONSTANT_BUFFER block
1814 * containing all the immediate values previously allocated
1815 * with alloc_immediate_4().
1816 */
1817 static boolean
1818 emit_vgpu10_immediates_block(struct svga_shader_emitter_v10 *emit)
1819 {
1820 VGPU10OpcodeToken0 token;
1821
1822 assert(!emit->immediates_emitted);
1823
1824 token.value = 0;
1825 token.opcodeType = VGPU10_OPCODE_CUSTOMDATA;
1826 token.customDataClass = VGPU10_CUSTOMDATA_DCL_IMMEDIATE_CONSTANT_BUFFER;
1827
1828 /* Note: no begin/end_emit_instruction() calls */
1829 emit_dword(emit, token.value);
1830 emit_dword(emit, 2 + 4 * emit->num_immediates);
1831 emit_dwords(emit, (unsigned *) emit->immediates, 4 * emit->num_immediates);
1832
1833 emit->immediates_emitted = TRUE;
1834
1835 return TRUE;
1836 }
1837
1838
1839 /**
1840 * Translate a fragment shader's TGSI_INTERPOLATE_x mode to a vgpu10
1841 * interpolation mode.
1842 * \return a VGPU10_INTERPOLATION_x value
1843 */
1844 static unsigned
1845 translate_interpolation(const struct svga_shader_emitter_v10 *emit,
1846 enum tgsi_interpolate_mode interp,
1847 enum tgsi_interpolate_loc interpolate_loc)
1848 {
1849 if (interp == TGSI_INTERPOLATE_COLOR) {
1850 interp = emit->key.fs.flatshade ?
1851 TGSI_INTERPOLATE_CONSTANT : TGSI_INTERPOLATE_PERSPECTIVE;
1852 }
1853
1854 switch (interp) {
1855 case TGSI_INTERPOLATE_CONSTANT:
1856 return VGPU10_INTERPOLATION_CONSTANT;
1857 case TGSI_INTERPOLATE_LINEAR:
1858 return interpolate_loc == TGSI_INTERPOLATE_LOC_CENTROID ?
1859 VGPU10_INTERPOLATION_LINEAR_NOPERSPECTIVE_CENTROID :
1860 VGPU10_INTERPOLATION_LINEAR_NOPERSPECTIVE;
1861 case TGSI_INTERPOLATE_PERSPECTIVE:
1862 return interpolate_loc == TGSI_INTERPOLATE_LOC_CENTROID ?
1863 VGPU10_INTERPOLATION_LINEAR_CENTROID :
1864 VGPU10_INTERPOLATION_LINEAR;
1865 default:
1866 assert(!"Unexpected interpolation mode");
1867 return VGPU10_INTERPOLATION_CONSTANT;
1868 }
1869 }
1870
1871
1872 /**
1873 * Translate a TGSI property to VGPU10.
1874 * Don't emit any instructions yet, only need to gather the primitive property information.
1875 * The output primitive topology might be changed later. The final property instructions
1876 * will be emitted as part of the pre-helper code.
1877 */
1878 static boolean
1879 emit_vgpu10_property(struct svga_shader_emitter_v10 *emit,
1880 const struct tgsi_full_property *prop)
1881 {
1882 static const VGPU10_PRIMITIVE primType[] = {
1883 VGPU10_PRIMITIVE_POINT, /* PIPE_PRIM_POINTS */
1884 VGPU10_PRIMITIVE_LINE, /* PIPE_PRIM_LINES */
1885 VGPU10_PRIMITIVE_LINE, /* PIPE_PRIM_LINE_LOOP */
1886 VGPU10_PRIMITIVE_LINE, /* PIPE_PRIM_LINE_STRIP */
1887 VGPU10_PRIMITIVE_TRIANGLE, /* PIPE_PRIM_TRIANGLES */
1888 VGPU10_PRIMITIVE_TRIANGLE, /* PIPE_PRIM_TRIANGLE_STRIP */
1889 VGPU10_PRIMITIVE_TRIANGLE, /* PIPE_PRIM_TRIANGLE_FAN */
1890 VGPU10_PRIMITIVE_UNDEFINED, /* PIPE_PRIM_QUADS */
1891 VGPU10_PRIMITIVE_UNDEFINED, /* PIPE_PRIM_QUAD_STRIP */
1892 VGPU10_PRIMITIVE_UNDEFINED, /* PIPE_PRIM_POLYGON */
1893 VGPU10_PRIMITIVE_LINE_ADJ, /* PIPE_PRIM_LINES_ADJACENCY */
1894 VGPU10_PRIMITIVE_LINE_ADJ, /* PIPE_PRIM_LINE_STRIP_ADJACENCY */
1895 VGPU10_PRIMITIVE_TRIANGLE_ADJ, /* PIPE_PRIM_TRIANGLES_ADJACENCY */
1896 VGPU10_PRIMITIVE_TRIANGLE_ADJ /* PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY */
1897 };
1898
1899 static const VGPU10_PRIMITIVE_TOPOLOGY primTopology[] = {
1900 VGPU10_PRIMITIVE_TOPOLOGY_POINTLIST, /* PIPE_PRIM_POINTS */
1901 VGPU10_PRIMITIVE_TOPOLOGY_LINELIST, /* PIPE_PRIM_LINES */
1902 VGPU10_PRIMITIVE_TOPOLOGY_LINELIST, /* PIPE_PRIM_LINE_LOOP */
1903 VGPU10_PRIMITIVE_TOPOLOGY_LINESTRIP, /* PIPE_PRIM_LINE_STRIP */
1904 VGPU10_PRIMITIVE_TOPOLOGY_TRIANGLELIST, /* PIPE_PRIM_TRIANGLES */
1905 VGPU10_PRIMITIVE_TOPOLOGY_TRIANGLESTRIP, /* PIPE_PRIM_TRIANGLE_STRIP */
1906 VGPU10_PRIMITIVE_TOPOLOGY_TRIANGLESTRIP, /* PIPE_PRIM_TRIANGLE_FAN */
1907 VGPU10_PRIMITIVE_TOPOLOGY_UNDEFINED, /* PIPE_PRIM_QUADS */
1908 VGPU10_PRIMITIVE_TOPOLOGY_UNDEFINED, /* PIPE_PRIM_QUAD_STRIP */
1909 VGPU10_PRIMITIVE_TOPOLOGY_UNDEFINED, /* PIPE_PRIM_POLYGON */
1910 VGPU10_PRIMITIVE_TOPOLOGY_LINELIST_ADJ, /* PIPE_PRIM_LINES_ADJACENCY */
1911 VGPU10_PRIMITIVE_TOPOLOGY_LINELIST_ADJ, /* PIPE_PRIM_LINE_STRIP_ADJACENCY */
1912 VGPU10_PRIMITIVE_TOPOLOGY_TRIANGLELIST_ADJ, /* PIPE_PRIM_TRIANGLES_ADJACENCY */
1913 VGPU10_PRIMITIVE_TOPOLOGY_TRIANGLESTRIP_ADJ /* PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY */
1914 };
1915
1916 static const unsigned inputArraySize[] = {
1917 0, /* VGPU10_PRIMITIVE_UNDEFINED */
1918 1, /* VGPU10_PRIMITIVE_POINT */
1919 2, /* VGPU10_PRIMITIVE_LINE */
1920 3, /* VGPU10_PRIMITIVE_TRIANGLE */
1921 0,
1922 0,
1923 4, /* VGPU10_PRIMITIVE_LINE_ADJ */
1924 6 /* VGPU10_PRIMITIVE_TRIANGLE_ADJ */
1925 };
1926
1927 switch (prop->Property.PropertyName) {
1928 case TGSI_PROPERTY_GS_INPUT_PRIM:
1929 assert(prop->u[0].Data < ARRAY_SIZE(primType));
1930 emit->gs.prim_type = primType[prop->u[0].Data];
1931 assert(emit->gs.prim_type != VGPU10_PRIMITIVE_UNDEFINED);
1932 emit->gs.input_size = inputArraySize[emit->gs.prim_type];
1933 break;
1934
1935 case TGSI_PROPERTY_GS_OUTPUT_PRIM:
1936 assert(prop->u[0].Data < ARRAY_SIZE(primTopology));
1937 emit->gs.prim_topology = primTopology[prop->u[0].Data];
1938 assert(emit->gs.prim_topology != VGPU10_PRIMITIVE_TOPOLOGY_UNDEFINED);
1939 break;
1940
1941 case TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES:
1942 emit->gs.max_out_vertices = prop->u[0].Data;
1943 break;
1944
1945 default:
1946 break;
1947 }
1948
1949 return TRUE;
1950 }
1951
1952
1953 static void
1954 emit_property_instruction(struct svga_shader_emitter_v10 *emit,
1955 VGPU10OpcodeToken0 opcode0, unsigned nData,
1956 unsigned data)
1957 {
1958 begin_emit_instruction(emit);
1959 emit_dword(emit, opcode0.value);
1960 if (nData)
1961 emit_dword(emit, data);
1962 end_emit_instruction(emit);
1963 }
1964
1965
1966 /**
1967 * Emit property instructions
1968 */
1969 static void
1970 emit_property_instructions(struct svga_shader_emitter_v10 *emit)
1971 {
1972 VGPU10OpcodeToken0 opcode0;
1973
1974 assert(emit->unit == PIPE_SHADER_GEOMETRY);
1975
1976 /* emit input primitive type declaration */
1977 opcode0.value = 0;
1978 opcode0.opcodeType = VGPU10_OPCODE_DCL_GS_INPUT_PRIMITIVE;
1979 opcode0.primitive = emit->gs.prim_type;
1980 emit_property_instruction(emit, opcode0, 0, 0);
1981
1982 /* emit output primitive topology declaration */
1983 opcode0.value = 0;
1984 opcode0.opcodeType = VGPU10_OPCODE_DCL_GS_OUTPUT_PRIMITIVE_TOPOLOGY;
1985 opcode0.primitiveTopology = emit->gs.prim_topology;
1986 emit_property_instruction(emit, opcode0, 0, 0);
1987
1988 /* emit max output vertices */
1989 opcode0.value = 0;
1990 opcode0.opcodeType = VGPU10_OPCODE_DCL_MAX_OUTPUT_VERTEX_COUNT;
1991 emit_property_instruction(emit, opcode0, 1, emit->gs.max_out_vertices);
1992 }
1993
1994
1995 /**
1996 * Emit a vgpu10 declaration "instruction".
1997 * \param index the register index
1998 * \param size array size of the operand. In most cases, it is 1,
1999 * but for inputs to geometry shader, the array size varies
2000 * depending on the primitive type.
2001 */
2002 static void
2003 emit_decl_instruction(struct svga_shader_emitter_v10 *emit,
2004 VGPU10OpcodeToken0 opcode0,
2005 VGPU10OperandToken0 operand0,
2006 VGPU10NameToken name_token,
2007 unsigned index, unsigned size)
2008 {
2009 assert(opcode0.opcodeType);
2010 assert(operand0.mask);
2011
2012 begin_emit_instruction(emit);
2013 emit_dword(emit, opcode0.value);
2014
2015 emit_dword(emit, operand0.value);
2016
2017 if (operand0.indexDimension == VGPU10_OPERAND_INDEX_1D) {
2018 /* Next token is the index of the register to declare */
2019 emit_dword(emit, index);
2020 }
2021 else if (operand0.indexDimension >= VGPU10_OPERAND_INDEX_2D) {
2022 /* Next token is the size of the register */
2023 emit_dword(emit, size);
2024
2025 /* Followed by the index of the register */
2026 emit_dword(emit, index);
2027 }
2028
2029 if (name_token.value) {
2030 emit_dword(emit, name_token.value);
2031 }
2032
2033 end_emit_instruction(emit);
2034 }
2035
2036
2037 /**
2038 * Emit the declaration for a shader input.
2039 * \param opcodeType opcode type, one of VGPU10_OPCODE_DCL_INPUTx
2040 * \param operandType operand type, one of VGPU10_OPERAND_TYPE_INPUT_x
2041 * \param dim index dimension
2042 * \param index the input register index
2043 * \param size array size of the operand. In most cases, it is 1,
2044 * but for inputs to geometry shader, the array size varies
2045 * depending on the primitive type.
2046 * \param name one of VGPU10_NAME_x
2047 * \parma numComp number of components
2048 * \param selMode component selection mode
2049 * \param usageMask bitfield of VGPU10_OPERAND_4_COMPONENT_MASK_x values
2050 * \param interpMode interpolation mode
2051 */
2052 static void
2053 emit_input_declaration(struct svga_shader_emitter_v10 *emit,
2054 unsigned opcodeType, unsigned operandType,
2055 unsigned dim, unsigned index, unsigned size,
2056 unsigned name, unsigned numComp,
2057 unsigned selMode, unsigned usageMask,
2058 unsigned interpMode)
2059 {
2060 VGPU10OpcodeToken0 opcode0;
2061 VGPU10OperandToken0 operand0;
2062 VGPU10NameToken name_token;
2063
2064 assert(usageMask <= VGPU10_OPERAND_4_COMPONENT_MASK_ALL);
2065 assert(opcodeType == VGPU10_OPCODE_DCL_INPUT ||
2066 opcodeType == VGPU10_OPCODE_DCL_INPUT_SIV ||
2067 opcodeType == VGPU10_OPCODE_DCL_INPUT_PS ||
2068 opcodeType == VGPU10_OPCODE_DCL_INPUT_PS_SGV);
2069 assert(operandType == VGPU10_OPERAND_TYPE_INPUT ||
2070 operandType == VGPU10_OPERAND_TYPE_INPUT_PRIMITIVEID);
2071 assert(numComp <= VGPU10_OPERAND_4_COMPONENT);
2072 assert(selMode <= VGPU10_OPERAND_4_COMPONENT_MASK_MODE);
2073 assert(dim <= VGPU10_OPERAND_INDEX_3D);
2074 assert(name == VGPU10_NAME_UNDEFINED ||
2075 name == VGPU10_NAME_POSITION ||
2076 name == VGPU10_NAME_INSTANCE_ID ||
2077 name == VGPU10_NAME_VERTEX_ID ||
2078 name == VGPU10_NAME_PRIMITIVE_ID ||
2079 name == VGPU10_NAME_IS_FRONT_FACE);
2080 assert(interpMode == VGPU10_INTERPOLATION_UNDEFINED ||
2081 interpMode == VGPU10_INTERPOLATION_CONSTANT ||
2082 interpMode == VGPU10_INTERPOLATION_LINEAR ||
2083 interpMode == VGPU10_INTERPOLATION_LINEAR_CENTROID ||
2084 interpMode == VGPU10_INTERPOLATION_LINEAR_NOPERSPECTIVE ||
2085 interpMode == VGPU10_INTERPOLATION_LINEAR_NOPERSPECTIVE_CENTROID);
2086
2087 check_register_index(emit, opcodeType, index);
2088
2089 opcode0.value = operand0.value = name_token.value = 0;
2090
2091 opcode0.opcodeType = opcodeType;
2092 opcode0.interpolationMode = interpMode;
2093
2094 operand0.operandType = operandType;
2095 operand0.numComponents = numComp;
2096 operand0.selectionMode = selMode;
2097 operand0.mask = usageMask;
2098 operand0.indexDimension = dim;
2099 operand0.index0Representation = VGPU10_OPERAND_INDEX_IMMEDIATE32;
2100 if (dim == VGPU10_OPERAND_INDEX_2D)
2101 operand0.index1Representation = VGPU10_OPERAND_INDEX_IMMEDIATE32;
2102
2103 name_token.name = name;
2104
2105 emit_decl_instruction(emit, opcode0, operand0, name_token, index, size);
2106 }
2107
2108
2109 /**
2110 * Emit the declaration for a shader output.
2111 * \param type one of VGPU10_OPCODE_DCL_OUTPUTx
2112 * \param index the output register index
2113 * \param name one of VGPU10_NAME_x
2114 * \param usageMask bitfield of VGPU10_OPERAND_4_COMPONENT_MASK_x values
2115 */
2116 static void
2117 emit_output_declaration(struct svga_shader_emitter_v10 *emit,
2118 unsigned type, unsigned index,
2119 unsigned name, unsigned usageMask)
2120 {
2121 VGPU10OpcodeToken0 opcode0;
2122 VGPU10OperandToken0 operand0;
2123 VGPU10NameToken name_token;
2124
2125 assert(usageMask <= VGPU10_OPERAND_4_COMPONENT_MASK_ALL);
2126 assert(type == VGPU10_OPCODE_DCL_OUTPUT ||
2127 type == VGPU10_OPCODE_DCL_OUTPUT_SGV ||
2128 type == VGPU10_OPCODE_DCL_OUTPUT_SIV);
2129 assert(name == VGPU10_NAME_UNDEFINED ||
2130 name == VGPU10_NAME_POSITION ||
2131 name == VGPU10_NAME_PRIMITIVE_ID ||
2132 name == VGPU10_NAME_RENDER_TARGET_ARRAY_INDEX ||
2133 name == VGPU10_NAME_CLIP_DISTANCE);
2134
2135 check_register_index(emit, type, index);
2136
2137 opcode0.value = operand0.value = name_token.value = 0;
2138
2139 opcode0.opcodeType = type;
2140 operand0.operandType = VGPU10_OPERAND_TYPE_OUTPUT;
2141 operand0.numComponents = VGPU10_OPERAND_4_COMPONENT;
2142 operand0.selectionMode = VGPU10_OPERAND_4_COMPONENT_MASK_MODE;
2143 operand0.mask = usageMask;
2144 operand0.indexDimension = VGPU10_OPERAND_INDEX_1D;
2145 operand0.index0Representation = VGPU10_OPERAND_INDEX_IMMEDIATE32;
2146
2147 name_token.name = name;
2148
2149 emit_decl_instruction(emit, opcode0, operand0, name_token, index, 1);
2150 }
2151
2152
2153 /**
2154 * Emit the declaration for the fragment depth output.
2155 */
2156 static void
2157 emit_fragdepth_output_declaration(struct svga_shader_emitter_v10 *emit)
2158 {
2159 VGPU10OpcodeToken0 opcode0;
2160 VGPU10OperandToken0 operand0;
2161 VGPU10NameToken name_token;
2162
2163 assert(emit->unit == PIPE_SHADER_FRAGMENT);
2164
2165 opcode0.value = operand0.value = name_token.value = 0;
2166
2167 opcode0.opcodeType = VGPU10_OPCODE_DCL_OUTPUT;
2168 operand0.operandType = VGPU10_OPERAND_TYPE_OUTPUT_DEPTH;
2169 operand0.numComponents = VGPU10_OPERAND_1_COMPONENT;
2170 operand0.indexDimension = VGPU10_OPERAND_INDEX_0D;
2171 operand0.mask = VGPU10_OPERAND_4_COMPONENT_MASK_ALL;
2172
2173 emit_decl_instruction(emit, opcode0, operand0, name_token, 0, 1);
2174 }
2175
2176
2177 /**
2178 * Emit the declaration for a system value input/output.
2179 */
2180 static void
2181 emit_system_value_declaration(struct svga_shader_emitter_v10 *emit,
2182 enum tgsi_semantic semantic_name, unsigned index)
2183 {
2184 switch (semantic_name) {
2185 case TGSI_SEMANTIC_INSTANCEID:
2186 index = alloc_system_value_index(emit, index);
2187 emit_input_declaration(emit, VGPU10_OPCODE_DCL_INPUT_SIV,
2188 VGPU10_OPERAND_TYPE_INPUT,
2189 VGPU10_OPERAND_INDEX_1D,
2190 index, 1,
2191 VGPU10_NAME_INSTANCE_ID,
2192 VGPU10_OPERAND_4_COMPONENT,
2193 VGPU10_OPERAND_4_COMPONENT_MASK_MODE,
2194 VGPU10_OPERAND_4_COMPONENT_MASK_X,
2195 VGPU10_INTERPOLATION_UNDEFINED);
2196 break;
2197 case TGSI_SEMANTIC_VERTEXID:
2198 index = alloc_system_value_index(emit, index);
2199 emit_input_declaration(emit, VGPU10_OPCODE_DCL_INPUT_SIV,
2200 VGPU10_OPERAND_TYPE_INPUT,
2201 VGPU10_OPERAND_INDEX_1D,
2202 index, 1,
2203 VGPU10_NAME_VERTEX_ID,
2204 VGPU10_OPERAND_4_COMPONENT,
2205 VGPU10_OPERAND_4_COMPONENT_MASK_MODE,
2206 VGPU10_OPERAND_4_COMPONENT_MASK_X,
2207 VGPU10_INTERPOLATION_UNDEFINED);
2208 break;
2209 default:
2210 ; /* XXX */
2211 }
2212 }
2213
2214 /**
2215 * Translate a TGSI declaration to VGPU10.
2216 */
2217 static boolean
2218 emit_vgpu10_declaration(struct svga_shader_emitter_v10 *emit,
2219 const struct tgsi_full_declaration *decl)
2220 {
2221 switch (decl->Declaration.File) {
2222 case TGSI_FILE_INPUT:
2223 /* do nothing - see emit_input_declarations() */
2224 return TRUE;
2225
2226 case TGSI_FILE_OUTPUT:
2227 assert(decl->Range.First == decl->Range.Last);
2228 emit->output_usage_mask[decl->Range.First] = decl->Declaration.UsageMask;
2229 return TRUE;
2230
2231 case TGSI_FILE_TEMPORARY:
2232 /* Don't declare the temps here. Just keep track of how many
2233 * and emit the declaration later.
2234 */
2235 if (decl->Declaration.Array) {
2236 /* Indexed temporary array. Save the start index of the array
2237 * and the size of the array.
2238 */
2239 const unsigned arrayID = MIN2(decl->Array.ArrayID, MAX_TEMP_ARRAYS);
2240 unsigned i;
2241
2242 assert(arrayID < ARRAY_SIZE(emit->temp_arrays));
2243
2244 /* Save this array so we can emit the declaration for it later */
2245 emit->temp_arrays[arrayID].start = decl->Range.First;
2246 emit->temp_arrays[arrayID].size =
2247 decl->Range.Last - decl->Range.First + 1;
2248
2249 emit->num_temp_arrays = MAX2(emit->num_temp_arrays, arrayID + 1);
2250 assert(emit->num_temp_arrays <= MAX_TEMP_ARRAYS);
2251 emit->num_temp_arrays = MIN2(emit->num_temp_arrays, MAX_TEMP_ARRAYS);
2252
2253 /* Fill in the temp_map entries for this array */
2254 for (i = decl->Range.First; i <= decl->Range.Last; i++) {
2255 emit->temp_map[i].arrayId = arrayID;
2256 emit->temp_map[i].index = i - decl->Range.First;
2257 }
2258 }
2259
2260 /* for all temps, indexed or not, keep track of highest index */
2261 emit->num_shader_temps = MAX2(emit->num_shader_temps,
2262 decl->Range.Last + 1);
2263 return TRUE;
2264
2265 case TGSI_FILE_CONSTANT:
2266 /* Don't declare constants here. Just keep track and emit later. */
2267 {
2268 unsigned constbuf = 0, num_consts;
2269 if (decl->Declaration.Dimension) {
2270 constbuf = decl->Dim.Index2D;
2271 }
2272 /* We throw an assertion here when, in fact, the shader should never
2273 * have linked due to constbuf index out of bounds, so we shouldn't
2274 * have reached here.
2275 */
2276 assert(constbuf < ARRAY_SIZE(emit->num_shader_consts));
2277
2278 num_consts = MAX2(emit->num_shader_consts[constbuf],
2279 decl->Range.Last + 1);
2280
2281 if (num_consts > VGPU10_MAX_CONSTANT_BUFFER_ELEMENT_COUNT) {
2282 debug_printf("Warning: constant buffer is declared to size [%u]"
2283 " but [%u] is the limit.\n",
2284 num_consts,
2285 VGPU10_MAX_CONSTANT_BUFFER_ELEMENT_COUNT);
2286 }
2287 /* The linker doesn't enforce the max UBO size so we clamp here */
2288 emit->num_shader_consts[constbuf] =
2289 MIN2(num_consts, VGPU10_MAX_CONSTANT_BUFFER_ELEMENT_COUNT);
2290 }
2291 return TRUE;
2292
2293 case TGSI_FILE_IMMEDIATE:
2294 assert(!"TGSI_FILE_IMMEDIATE not handled yet!");
2295 return FALSE;
2296
2297 case TGSI_FILE_SYSTEM_VALUE:
2298 emit_system_value_declaration(emit, decl->Semantic.Name,
2299 decl->Range.First);
2300 return TRUE;
2301
2302 case TGSI_FILE_SAMPLER:
2303 /* Don't declare samplers here. Just keep track and emit later. */
2304 emit->num_samplers = MAX2(emit->num_samplers, decl->Range.Last + 1);
2305 return TRUE;
2306
2307 #if 0
2308 case TGSI_FILE_RESOURCE:
2309 /*opcode0.opcodeType = VGPU10_OPCODE_DCL_RESOURCE;*/
2310 /* XXX more, VGPU10_RETURN_TYPE_FLOAT */
2311 assert(!"TGSI_FILE_RESOURCE not handled yet");
2312 return FALSE;
2313 #endif
2314
2315 case TGSI_FILE_ADDRESS:
2316 emit->num_address_regs = MAX2(emit->num_address_regs,
2317 decl->Range.Last + 1);
2318 return TRUE;
2319
2320 case TGSI_FILE_SAMPLER_VIEW:
2321 {
2322 unsigned unit = decl->Range.First;
2323 assert(decl->Range.First == decl->Range.Last);
2324 emit->sampler_target[unit] = decl->SamplerView.Resource;
2325 /* Note: we can ignore YZW return types for now */
2326 emit->sampler_return_type[unit] = decl->SamplerView.ReturnTypeX;
2327 }
2328 return TRUE;
2329
2330 default:
2331 assert(!"Unexpected type of declaration");
2332 return FALSE;
2333 }
2334 }
2335
2336
2337
2338 /**
2339 * Emit all input declarations.
2340 */
2341 static boolean
2342 emit_input_declarations(struct svga_shader_emitter_v10 *emit)
2343 {
2344 unsigned i;
2345
2346 if (emit->unit == PIPE_SHADER_FRAGMENT) {
2347
2348 for (i = 0; i < emit->linkage.num_inputs; i++) {
2349 enum tgsi_semantic semantic_name = emit->info.input_semantic_name[i];
2350 unsigned usage_mask = emit->info.input_usage_mask[i];
2351 unsigned index = emit->linkage.input_map[i];
2352 unsigned type, interpolationMode, name;
2353
2354 if (usage_mask == 0)
2355 continue; /* register is not actually used */
2356
2357 if (semantic_name == TGSI_SEMANTIC_POSITION) {
2358 /* fragment position input */
2359 type = VGPU10_OPCODE_DCL_INPUT_PS_SGV;
2360 interpolationMode = VGPU10_INTERPOLATION_LINEAR;
2361 name = VGPU10_NAME_POSITION;
2362 if (usage_mask & TGSI_WRITEMASK_W) {
2363 /* we need to replace use of 'w' with '1/w' */
2364 emit->fs.fragcoord_input_index = i;
2365 }
2366 }
2367 else if (semantic_name == TGSI_SEMANTIC_FACE) {
2368 /* fragment front-facing input */
2369 type = VGPU10_OPCODE_DCL_INPUT_PS_SGV;
2370 interpolationMode = VGPU10_INTERPOLATION_CONSTANT;
2371 name = VGPU10_NAME_IS_FRONT_FACE;
2372 emit->fs.face_input_index = i;
2373 }
2374 else if (semantic_name == TGSI_SEMANTIC_PRIMID) {
2375 /* primitive ID */
2376 type = VGPU10_OPCODE_DCL_INPUT_PS_SGV;
2377 interpolationMode = VGPU10_INTERPOLATION_CONSTANT;
2378 name = VGPU10_NAME_PRIMITIVE_ID;
2379 }
2380 else {
2381 /* general fragment input */
2382 type = VGPU10_OPCODE_DCL_INPUT_PS;
2383 interpolationMode =
2384 translate_interpolation(emit,
2385 emit->info.input_interpolate[i],
2386 emit->info.input_interpolate_loc[i]);
2387
2388 /* keeps track if flat interpolation mode is being used */
2389 emit->uses_flat_interp = emit->uses_flat_interp ||
2390 (interpolationMode == VGPU10_INTERPOLATION_CONSTANT);
2391
2392 name = VGPU10_NAME_UNDEFINED;
2393 }
2394
2395 emit_input_declaration(emit, type,
2396 VGPU10_OPERAND_TYPE_INPUT,
2397 VGPU10_OPERAND_INDEX_1D, index, 1,
2398 name,
2399 VGPU10_OPERAND_4_COMPONENT,
2400 VGPU10_OPERAND_4_COMPONENT_MASK_MODE,
2401 VGPU10_OPERAND_4_COMPONENT_MASK_ALL,
2402 interpolationMode);
2403 }
2404 }
2405 else if (emit->unit == PIPE_SHADER_GEOMETRY) {
2406
2407 for (i = 0; i < emit->info.num_inputs; i++) {
2408 enum tgsi_semantic semantic_name = emit->info.input_semantic_name[i];
2409 unsigned usage_mask = emit->info.input_usage_mask[i];
2410 unsigned index = emit->linkage.input_map[i];
2411 unsigned opcodeType, operandType;
2412 unsigned numComp, selMode;
2413 unsigned name;
2414 unsigned dim;
2415
2416 if (usage_mask == 0)
2417 continue; /* register is not actually used */
2418
2419 opcodeType = VGPU10_OPCODE_DCL_INPUT;
2420 operandType = VGPU10_OPERAND_TYPE_INPUT;
2421 numComp = VGPU10_OPERAND_4_COMPONENT;
2422 selMode = VGPU10_OPERAND_4_COMPONENT_MASK_MODE;
2423 name = VGPU10_NAME_UNDEFINED;
2424
2425 /* all geometry shader inputs are two dimensional except gl_PrimitiveID */
2426 dim = VGPU10_OPERAND_INDEX_2D;
2427
2428 if (semantic_name == TGSI_SEMANTIC_PRIMID) {
2429 /* Primitive ID */
2430 operandType = VGPU10_OPERAND_TYPE_INPUT_PRIMITIVEID;
2431 dim = VGPU10_OPERAND_INDEX_0D;
2432 numComp = VGPU10_OPERAND_0_COMPONENT;
2433 selMode = 0;
2434
2435 /* also save the register index so we can check for
2436 * primitive id when emit src register. We need to modify the
2437 * operand type, index dimension when emit primitive id src reg.
2438 */
2439 emit->gs.prim_id_index = i;
2440 }
2441 else if (semantic_name == TGSI_SEMANTIC_POSITION) {
2442 /* vertex position input */
2443 opcodeType = VGPU10_OPCODE_DCL_INPUT_SIV;
2444 name = VGPU10_NAME_POSITION;
2445 }
2446
2447 emit_input_declaration(emit, opcodeType, operandType,
2448 dim, index,
2449 emit->gs.input_size,
2450 name,
2451 numComp, selMode,
2452 VGPU10_OPERAND_4_COMPONENT_MASK_ALL,
2453 VGPU10_INTERPOLATION_UNDEFINED);
2454 }
2455 }
2456 else {
2457 assert(emit->unit == PIPE_SHADER_VERTEX);
2458
2459 for (i = 0; i < emit->info.file_max[TGSI_FILE_INPUT] + 1; i++) {
2460 unsigned usage_mask = emit->info.input_usage_mask[i];
2461 unsigned index = i;
2462
2463 if (usage_mask == 0)
2464 continue; /* register is not actually used */
2465
2466 emit_input_declaration(emit, VGPU10_OPCODE_DCL_INPUT,
2467 VGPU10_OPERAND_TYPE_INPUT,
2468 VGPU10_OPERAND_INDEX_1D, index, 1,
2469 VGPU10_NAME_UNDEFINED,
2470 VGPU10_OPERAND_4_COMPONENT,
2471 VGPU10_OPERAND_4_COMPONENT_MASK_MODE,
2472 VGPU10_OPERAND_4_COMPONENT_MASK_ALL,
2473 VGPU10_INTERPOLATION_UNDEFINED);
2474 }
2475 }
2476
2477 return TRUE;
2478 }
2479
2480
2481 /**
2482 * Emit all output declarations.
2483 */
2484 static boolean
2485 emit_output_declarations(struct svga_shader_emitter_v10 *emit)
2486 {
2487 unsigned i;
2488
2489 for (i = 0; i < emit->info.num_outputs; i++) {
2490 /*const unsigned usage_mask = emit->info.output_usage_mask[i];*/
2491 const enum tgsi_semantic semantic_name =
2492 emit->info.output_semantic_name[i];
2493 const unsigned semantic_index = emit->info.output_semantic_index[i];
2494 unsigned index = i;
2495
2496 if (emit->unit == PIPE_SHADER_FRAGMENT) {
2497 if (semantic_name == TGSI_SEMANTIC_COLOR) {
2498 assert(semantic_index < ARRAY_SIZE(emit->fs.color_out_index));
2499
2500 emit->fs.color_out_index[semantic_index] = index;
2501
2502 emit->fs.num_color_outputs = MAX2(emit->fs.num_color_outputs,
2503 index + 1);
2504
2505 /* The semantic index is the shader's color output/buffer index */
2506 emit_output_declaration(emit,
2507 VGPU10_OPCODE_DCL_OUTPUT, semantic_index,
2508 VGPU10_NAME_UNDEFINED,
2509 VGPU10_OPERAND_4_COMPONENT_MASK_ALL);
2510
2511 if (semantic_index == 0) {
2512 if (emit->key.fs.write_color0_to_n_cbufs > 1) {
2513 /* Emit declarations for the additional color outputs
2514 * for broadcasting.
2515 */
2516 unsigned j;
2517 for (j = 1; j < emit->key.fs.write_color0_to_n_cbufs; j++) {
2518 /* Allocate a new output index */
2519 unsigned idx = emit->info.num_outputs + j - 1;
2520 emit->fs.color_out_index[j] = idx;
2521 emit_output_declaration(emit,
2522 VGPU10_OPCODE_DCL_OUTPUT, idx,
2523 VGPU10_NAME_UNDEFINED,
2524 VGPU10_OPERAND_4_COMPONENT_MASK_ALL);
2525 emit->info.output_semantic_index[idx] = j;
2526 }
2527
2528 emit->fs.num_color_outputs =
2529 emit->key.fs.write_color0_to_n_cbufs;
2530 }
2531 }
2532 else {
2533 assert(!emit->key.fs.write_color0_to_n_cbufs);
2534 }
2535 }
2536 else if (semantic_name == TGSI_SEMANTIC_POSITION) {
2537 /* Fragment depth output */
2538 emit_fragdepth_output_declaration(emit);
2539 }
2540 else {
2541 assert(!"Bad output semantic name");
2542 }
2543 }
2544 else {
2545 /* VS or GS */
2546 unsigned name, type;
2547 unsigned writemask = VGPU10_OPERAND_4_COMPONENT_MASK_ALL;
2548
2549 switch (semantic_name) {
2550 case TGSI_SEMANTIC_POSITION:
2551 assert(emit->unit != PIPE_SHADER_FRAGMENT);
2552 type = VGPU10_OPCODE_DCL_OUTPUT_SIV;
2553 name = VGPU10_NAME_POSITION;
2554 /* Save the index of the vertex position output register */
2555 emit->vposition.out_index = index;
2556 break;
2557 case TGSI_SEMANTIC_CLIPDIST:
2558 type = VGPU10_OPCODE_DCL_OUTPUT_SIV;
2559 name = VGPU10_NAME_CLIP_DISTANCE;
2560 /* save the starting index of the clip distance output register */
2561 if (semantic_index == 0)
2562 emit->clip_dist_out_index = index;
2563 writemask = emit->output_usage_mask[index];
2564 writemask = apply_clip_plane_mask(emit, writemask, semantic_index);
2565 if (writemask == 0x0) {
2566 continue; /* discard this do-nothing declaration */
2567 }
2568 break;
2569 case TGSI_SEMANTIC_PRIMID:
2570 assert(emit->unit == PIPE_SHADER_GEOMETRY);
2571 type = VGPU10_OPCODE_DCL_OUTPUT_SGV;
2572 name = VGPU10_NAME_PRIMITIVE_ID;
2573 break;
2574 case TGSI_SEMANTIC_LAYER:
2575 assert(emit->unit == PIPE_SHADER_GEOMETRY);
2576 type = VGPU10_OPCODE_DCL_OUTPUT_SGV;
2577 name = VGPU10_NAME_RENDER_TARGET_ARRAY_INDEX;
2578 break;
2579 case TGSI_SEMANTIC_CLIPVERTEX:
2580 type = VGPU10_OPCODE_DCL_OUTPUT;
2581 name = VGPU10_NAME_UNDEFINED;
2582 emit->clip_vertex_out_index = index;
2583 break;
2584 default:
2585 /* generic output */
2586 type = VGPU10_OPCODE_DCL_OUTPUT;
2587 name = VGPU10_NAME_UNDEFINED;
2588 }
2589
2590 emit_output_declaration(emit, type, index, name, writemask);
2591 }
2592 }
2593
2594 if (emit->vposition.so_index != INVALID_INDEX &&
2595 emit->vposition.out_index != INVALID_INDEX) {
2596
2597 assert(emit->unit != PIPE_SHADER_FRAGMENT);
2598
2599 /* Emit the declaration for the non-adjusted vertex position
2600 * for stream output purpose
2601 */
2602 emit_output_declaration(emit, VGPU10_OPCODE_DCL_OUTPUT,
2603 emit->vposition.so_index,
2604 VGPU10_NAME_UNDEFINED,
2605 VGPU10_OPERAND_4_COMPONENT_MASK_ALL);
2606 }
2607
2608 if (emit->clip_dist_so_index != INVALID_INDEX &&
2609 emit->clip_dist_out_index != INVALID_INDEX) {
2610
2611 assert(emit->unit != PIPE_SHADER_FRAGMENT);
2612
2613 /* Emit the declaration for the clip distance shadow copy which
2614 * will be used for stream output purpose and for clip distance
2615 * varying variable
2616 */
2617 emit_output_declaration(emit, VGPU10_OPCODE_DCL_OUTPUT,
2618 emit->clip_dist_so_index,
2619 VGPU10_NAME_UNDEFINED,
2620 emit->output_usage_mask[emit->clip_dist_out_index]);
2621
2622 if (emit->info.num_written_clipdistance > 4) {
2623 /* for the second clip distance register, each handles 4 planes */
2624 emit_output_declaration(emit, VGPU10_OPCODE_DCL_OUTPUT,
2625 emit->clip_dist_so_index + 1,
2626 VGPU10_NAME_UNDEFINED,
2627 emit->output_usage_mask[emit->clip_dist_out_index+1]);
2628 }
2629 }
2630
2631 return TRUE;
2632 }
2633
2634
2635 /**
2636 * Emit the declaration for the temporary registers.
2637 */
2638 static boolean
2639 emit_temporaries_declaration(struct svga_shader_emitter_v10 *emit)
2640 {
2641 unsigned total_temps, reg, i;
2642
2643 total_temps = emit->num_shader_temps;
2644
2645 /* If there is indirect access to non-indexable temps in the shader,
2646 * convert those temps to indexable temps. This works around a bug
2647 * in the GLSL->TGSI translator exposed in piglit test
2648 * glsl-1.20/execution/fs-const-array-of-struct-of-array.shader_test.
2649 * Internal temps added by the driver remain as non-indexable temps.
2650 */
2651 if ((emit->info.indirect_files & (1 << TGSI_FILE_TEMPORARY)) &&
2652 emit->num_temp_arrays == 0) {
2653 unsigned arrayID;
2654
2655 arrayID = 1;
2656 emit->num_temp_arrays = arrayID + 1;
2657 emit->temp_arrays[arrayID].start = 0;
2658 emit->temp_arrays[arrayID].size = total_temps;
2659
2660 /* Fill in the temp_map entries for this temp array */
2661 for (i = 0; i < total_temps; i++) {
2662 emit->temp_map[i].arrayId = arrayID;
2663 emit->temp_map[i].index = i;
2664 }
2665 }
2666
2667 /* Allocate extra temps for specially-implemented instructions,
2668 * such as LIT.
2669 */
2670 total_temps += MAX_INTERNAL_TEMPS;
2671
2672 if (emit->unit == PIPE_SHADER_VERTEX || emit->unit == PIPE_SHADER_GEOMETRY) {
2673 if (emit->vposition.need_prescale || emit->key.vs.undo_viewport ||
2674 emit->key.clip_plane_enable ||
2675 emit->vposition.so_index != INVALID_INDEX) {
2676 emit->vposition.tmp_index = total_temps;
2677 total_temps += 1;
2678 }
2679
2680 if (emit->unit == PIPE_SHADER_VERTEX) {
2681 unsigned attrib_mask = (emit->key.vs.adjust_attrib_w_1 |
2682 emit->key.vs.adjust_attrib_itof |
2683 emit->key.vs.adjust_attrib_utof |
2684 emit->key.vs.attrib_is_bgra |
2685 emit->key.vs.attrib_puint_to_snorm |
2686 emit->key.vs.attrib_puint_to_uscaled |
2687 emit->key.vs.attrib_puint_to_sscaled);
2688 while (attrib_mask) {
2689 unsigned index = u_bit_scan(&attrib_mask);
2690 emit->vs.adjusted_input[index] = total_temps++;
2691 }
2692 }
2693
2694 if (emit->clip_mode == CLIP_DISTANCE) {
2695 /* We need to write the clip distance to a temporary register
2696 * first. Then it will be copied to the shadow copy for
2697 * the clip distance varying variable and stream output purpose.
2698 * It will also be copied to the actual CLIPDIST register
2699 * according to the enabled clip planes
2700 */
2701 emit->clip_dist_tmp_index = total_temps++;
2702 if (emit->info.num_written_clipdistance > 4)
2703 total_temps++; /* second clip register */
2704 }
2705 else if (emit->clip_mode == CLIP_VERTEX) {
2706 /* We need to convert the TGSI CLIPVERTEX output to one or more
2707 * clip distances. Allocate a temp reg for the clipvertex here.
2708 */
2709 assert(emit->info.writes_clipvertex > 0);
2710 emit->clip_vertex_tmp_index = total_temps;
2711 total_temps++;
2712 }
2713 }
2714 else if (emit->unit == PIPE_SHADER_FRAGMENT) {
2715 if (emit->key.fs.alpha_func != SVGA3D_CMP_ALWAYS ||
2716 emit->key.fs.write_color0_to_n_cbufs > 1) {
2717 /* Allocate a temp to hold the output color */
2718 emit->fs.color_tmp_index = total_temps;
2719 total_temps += 1;
2720 }
2721
2722 if (emit->fs.face_input_index != INVALID_INDEX) {
2723 /* Allocate a temp for the +/-1 face register */
2724 emit->fs.face_tmp_index = total_temps;
2725 total_temps += 1;
2726 }
2727
2728 if (emit->fs.fragcoord_input_index != INVALID_INDEX) {
2729 /* Allocate a temp for modified fragment position register */
2730 emit->fs.fragcoord_tmp_index = total_temps;
2731 total_temps += 1;
2732 }
2733 }
2734
2735 for (i = 0; i < emit->num_address_regs; i++) {
2736 emit->address_reg_index[i] = total_temps++;
2737 }
2738
2739 /* Initialize the temp_map array which maps TGSI temp indexes to VGPU10
2740 * temp indexes. Basically, we compact all the non-array temp register
2741 * indexes into a consecutive series.
2742 *
2743 * Before, we may have some TGSI declarations like:
2744 * DCL TEMP[0..1], LOCAL
2745 * DCL TEMP[2..4], ARRAY(1), LOCAL
2746 * DCL TEMP[5..7], ARRAY(2), LOCAL
2747 * plus, some extra temps, like TEMP[8], TEMP[9] for misc things
2748 *
2749 * After, we'll have a map like this:
2750 * temp_map[0] = { array 0, index 0 }
2751 * temp_map[1] = { array 0, index 1 }
2752 * temp_map[2] = { array 1, index 0 }
2753 * temp_map[3] = { array 1, index 1 }
2754 * temp_map[4] = { array 1, index 2 }
2755 * temp_map[5] = { array 2, index 0 }
2756 * temp_map[6] = { array 2, index 1 }
2757 * temp_map[7] = { array 2, index 2 }
2758 * temp_map[8] = { array 0, index 2 }
2759 * temp_map[9] = { array 0, index 3 }
2760 *
2761 * We'll declare two arrays of 3 elements, plus a set of four non-indexed
2762 * temps numbered 0..3
2763 *
2764 * Any time we emit a temporary register index, we'll have to use the
2765 * temp_map[] table to convert the TGSI index to the VGPU10 index.
2766 *
2767 * Finally, we recompute the total_temps value here.
2768 */
2769 reg = 0;
2770 for (i = 0; i < total_temps; i++) {
2771 if (emit->temp_map[i].arrayId == 0) {
2772 emit->temp_map[i].index = reg++;
2773 }
2774 }
2775
2776 if (0) {
2777 debug_printf("total_temps %u\n", total_temps);
2778 for (i = 0; i < total_temps; i++) {
2779 debug_printf("temp %u -> array %u index %u\n",
2780 i, emit->temp_map[i].arrayId, emit->temp_map[i].index);
2781 }
2782 }
2783
2784 total_temps = reg;
2785
2786 /* Emit declaration of ordinary temp registers */
2787 if (total_temps > 0) {
2788 VGPU10OpcodeToken0 opcode0;
2789
2790 opcode0.value = 0;
2791 opcode0.opcodeType = VGPU10_OPCODE_DCL_TEMPS;
2792
2793 begin_emit_instruction(emit);
2794 emit_dword(emit, opcode0.value);
2795 emit_dword(emit, total_temps);
2796 end_emit_instruction(emit);
2797 }
2798
2799 /* Emit declarations for indexable temp arrays. Skip 0th entry since
2800 * it's unused.
2801 */
2802 for (i = 1; i < emit->num_temp_arrays; i++) {
2803 unsigned num_temps = emit->temp_arrays[i].size;
2804
2805 if (num_temps > 0) {
2806 VGPU10OpcodeToken0 opcode0;
2807
2808 opcode0.value = 0;
2809 opcode0.opcodeType = VGPU10_OPCODE_DCL_INDEXABLE_TEMP;
2810
2811 begin_emit_instruction(emit);
2812 emit_dword(emit, opcode0.value);
2813 emit_dword(emit, i); /* which array */
2814 emit_dword(emit, num_temps);
2815 emit_dword(emit, 4); /* num components */
2816 end_emit_instruction(emit);
2817
2818 total_temps += num_temps;
2819 }
2820 }
2821
2822 /* Check that the grand total of all regular and indexed temps is
2823 * under the limit.
2824 */
2825 check_register_index(emit, VGPU10_OPCODE_DCL_TEMPS, total_temps - 1);
2826
2827 return TRUE;
2828 }
2829
2830
2831 static boolean
2832 emit_constant_declaration(struct svga_shader_emitter_v10 *emit)
2833 {
2834 VGPU10OpcodeToken0 opcode0;
2835 VGPU10OperandToken0 operand0;
2836 unsigned total_consts, i;
2837
2838 opcode0.value = 0;
2839 opcode0.opcodeType = VGPU10_OPCODE_DCL_CONSTANT_BUFFER;
2840 opcode0.accessPattern = VGPU10_CB_IMMEDIATE_INDEXED;
2841 /* XXX or, access pattern = VGPU10_CB_DYNAMIC_INDEXED */
2842
2843 operand0.value = 0;
2844 operand0.numComponents = VGPU10_OPERAND_4_COMPONENT;
2845 operand0.indexDimension = VGPU10_OPERAND_INDEX_2D;
2846 operand0.index0Representation = VGPU10_OPERAND_INDEX_IMMEDIATE32;
2847 operand0.index1Representation = VGPU10_OPERAND_INDEX_IMMEDIATE32;
2848 operand0.operandType = VGPU10_OPERAND_TYPE_CONSTANT_BUFFER;
2849 operand0.selectionMode = VGPU10_OPERAND_4_COMPONENT_SWIZZLE_MODE;
2850 operand0.swizzleX = 0;
2851 operand0.swizzleY = 1;
2852 operand0.swizzleZ = 2;
2853 operand0.swizzleW = 3;
2854
2855 /**
2856 * Emit declaration for constant buffer [0]. We also allocate
2857 * room for the extra constants here.
2858 */
2859 total_consts = emit->num_shader_consts[0];
2860
2861 /* Now, allocate constant slots for the "extra" constants.
2862 * Note: it's critical that these extra constant locations
2863 * exactly match what's emitted by the "extra" constants code
2864 * in svga_state_constants.c
2865 */
2866
2867 /* Vertex position scale/translation */
2868 if (emit->vposition.need_prescale) {
2869 emit->vposition.prescale_scale_index = total_consts++;
2870 emit->vposition.prescale_trans_index = total_consts++;
2871 }
2872
2873 if (emit->unit == PIPE_SHADER_VERTEX) {
2874 if (emit->key.vs.undo_viewport) {
2875 emit->vs.viewport_index = total_consts++;
2876 }
2877 }
2878
2879 /* user-defined clip planes */
2880 if (emit->key.clip_plane_enable) {
2881 unsigned n = util_bitcount(emit->key.clip_plane_enable);
2882 assert(emit->unit == PIPE_SHADER_VERTEX ||
2883 emit->unit == PIPE_SHADER_GEOMETRY);
2884 for (i = 0; i < n; i++) {
2885 emit->clip_plane_const[i] = total_consts++;
2886 }
2887 }
2888
2889 for (i = 0; i < emit->num_samplers; i++) {
2890
2891 /* Texcoord scale factors for RECT textures */
2892 if (emit->key.tex[i].unnormalized) {
2893 emit->texcoord_scale_index[i] = total_consts++;
2894 }
2895
2896 /* Texture buffer sizes */
2897 if (emit->sampler_target[i] == TGSI_TEXTURE_BUFFER) {
2898 emit->texture_buffer_size_index[i] = total_consts++;
2899 }
2900 }
2901
2902 if (total_consts > 0) {
2903 begin_emit_instruction(emit);
2904 emit_dword(emit, opcode0.value);
2905 emit_dword(emit, operand0.value);
2906 emit_dword(emit, 0); /* which const buffer slot */
2907 emit_dword(emit, total_consts);
2908 end_emit_instruction(emit);
2909 }
2910
2911 /* Declare remaining constant buffers (UBOs) */
2912 for (i = 1; i < ARRAY_SIZE(emit->num_shader_consts); i++) {
2913 if (emit->num_shader_consts[i] > 0) {
2914 begin_emit_instruction(emit);
2915 emit_dword(emit, opcode0.value);
2916 emit_dword(emit, operand0.value);
2917 emit_dword(emit, i); /* which const buffer slot */
2918 emit_dword(emit, emit->num_shader_consts[i]);
2919 end_emit_instruction(emit);
2920 }
2921 }
2922
2923 return TRUE;
2924 }
2925
2926
2927 /**
2928 * Emit declarations for samplers.
2929 */
2930 static boolean
2931 emit_sampler_declarations(struct svga_shader_emitter_v10 *emit)
2932 {
2933 unsigned i;
2934
2935 for (i = 0; i < emit->num_samplers; i++) {
2936 VGPU10OpcodeToken0 opcode0;
2937 VGPU10OperandToken0 operand0;
2938
2939 opcode0.value = 0;
2940 opcode0.opcodeType = VGPU10_OPCODE_DCL_SAMPLER;
2941 opcode0.samplerMode = VGPU10_SAMPLER_MODE_DEFAULT;
2942
2943 operand0.value = 0;
2944 operand0.numComponents = VGPU10_OPERAND_0_COMPONENT;
2945 operand0.operandType = VGPU10_OPERAND_TYPE_SAMPLER;
2946 operand0.indexDimension = VGPU10_OPERAND_INDEX_1D;
2947 operand0.index0Representation = VGPU10_OPERAND_INDEX_IMMEDIATE32;
2948
2949 begin_emit_instruction(emit);
2950 emit_dword(emit, opcode0.value);
2951 emit_dword(emit, operand0.value);
2952 emit_dword(emit, i);
2953 end_emit_instruction(emit);
2954 }
2955
2956 return TRUE;
2957 }
2958
2959
2960 /**
2961 * Translate TGSI_TEXTURE_x to VGAPU10_RESOURCE_DIMENSION_x.
2962 */
2963 static unsigned
2964 tgsi_texture_to_resource_dimension(enum tgsi_texture_type target,
2965 boolean is_array)
2966 {
2967 switch (target) {
2968 case TGSI_TEXTURE_BUFFER:
2969 return VGPU10_RESOURCE_DIMENSION_BUFFER;
2970 case TGSI_TEXTURE_1D:
2971 return VGPU10_RESOURCE_DIMENSION_TEXTURE1D;
2972 case TGSI_TEXTURE_2D:
2973 case TGSI_TEXTURE_RECT:
2974 return VGPU10_RESOURCE_DIMENSION_TEXTURE2D;
2975 case TGSI_TEXTURE_3D:
2976 return VGPU10_RESOURCE_DIMENSION_TEXTURE3D;
2977 case TGSI_TEXTURE_CUBE:
2978 return VGPU10_RESOURCE_DIMENSION_TEXTURECUBE;
2979 case TGSI_TEXTURE_SHADOW1D:
2980 return VGPU10_RESOURCE_DIMENSION_TEXTURE1D;
2981 case TGSI_TEXTURE_SHADOW2D:
2982 case TGSI_TEXTURE_SHADOWRECT:
2983 return VGPU10_RESOURCE_DIMENSION_TEXTURE2D;
2984 case TGSI_TEXTURE_1D_ARRAY:
2985 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2986 return is_array ? VGPU10_RESOURCE_DIMENSION_TEXTURE1DARRAY
2987 : VGPU10_RESOURCE_DIMENSION_TEXTURE1D;
2988 case TGSI_TEXTURE_2D_ARRAY:
2989 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2990 return is_array ? VGPU10_RESOURCE_DIMENSION_TEXTURE2DARRAY
2991 : VGPU10_RESOURCE_DIMENSION_TEXTURE2D;
2992 case TGSI_TEXTURE_SHADOWCUBE:
2993 return VGPU10_RESOURCE_DIMENSION_TEXTURECUBE;
2994 case TGSI_TEXTURE_2D_MSAA:
2995 return VGPU10_RESOURCE_DIMENSION_TEXTURE2DMS;
2996 case TGSI_TEXTURE_2D_ARRAY_MSAA:
2997 return is_array ? VGPU10_RESOURCE_DIMENSION_TEXTURE2DMSARRAY
2998 : VGPU10_RESOURCE_DIMENSION_TEXTURE2DMS;
2999 case TGSI_TEXTURE_CUBE_ARRAY:
3000 return VGPU10_RESOURCE_DIMENSION_TEXTURECUBEARRAY;
3001 default:
3002 assert(!"Unexpected resource type");
3003 return VGPU10_RESOURCE_DIMENSION_TEXTURE2D;
3004 }
3005 }
3006
3007
3008 /**
3009 * Given a tgsi_return_type, return true iff it is an integer type.
3010 */
3011 static boolean
3012 is_integer_type(enum tgsi_return_type type)
3013 {
3014 switch (type) {
3015 case TGSI_RETURN_TYPE_SINT:
3016 case TGSI_RETURN_TYPE_UINT:
3017 return TRUE;
3018 case TGSI_RETURN_TYPE_FLOAT:
3019 case TGSI_RETURN_TYPE_UNORM:
3020 case TGSI_RETURN_TYPE_SNORM:
3021 return FALSE;
3022 case TGSI_RETURN_TYPE_COUNT:
3023 default:
3024 assert(!"is_integer_type: Unknown tgsi_return_type");
3025 return FALSE;
3026 }
3027 }
3028
3029
3030 /**
3031 * Emit declarations for resources.
3032 * XXX When we're sure that all TGSI shaders will be generated with
3033 * sampler view declarations (Ex: DCL SVIEW[n], 2D, UINT) we may
3034 * rework this code.
3035 */
3036 static boolean
3037 emit_resource_declarations(struct svga_shader_emitter_v10 *emit)
3038 {
3039 unsigned i;
3040
3041 /* Emit resource decl for each sampler */
3042 for (i = 0; i < emit->num_samplers; i++) {
3043 VGPU10OpcodeToken0 opcode0;
3044 VGPU10OperandToken0 operand0;
3045 VGPU10ResourceReturnTypeToken return_type;
3046 VGPU10_RESOURCE_RETURN_TYPE rt;
3047
3048 opcode0.value = 0;
3049 opcode0.opcodeType = VGPU10_OPCODE_DCL_RESOURCE;
3050 opcode0.resourceDimension =
3051 tgsi_texture_to_resource_dimension(emit->sampler_target[i],
3052 emit->key.tex[i].is_array);
3053 operand0.value = 0;
3054 operand0.numComponents = VGPU10_OPERAND_0_COMPONENT;
3055 operand0.operandType = VGPU10_OPERAND_TYPE_RESOURCE;
3056 operand0.indexDimension = VGPU10_OPERAND_INDEX_1D;
3057 operand0.index0Representation = VGPU10_OPERAND_INDEX_IMMEDIATE32;
3058
3059 #if 1
3060 /* convert TGSI_RETURN_TYPE_x to VGPU10_RETURN_TYPE_x */
3061 STATIC_ASSERT(VGPU10_RETURN_TYPE_UNORM == TGSI_RETURN_TYPE_UNORM + 1);
3062 STATIC_ASSERT(VGPU10_RETURN_TYPE_SNORM == TGSI_RETURN_TYPE_SNORM + 1);
3063 STATIC_ASSERT(VGPU10_RETURN_TYPE_SINT == TGSI_RETURN_TYPE_SINT + 1);
3064 STATIC_ASSERT(VGPU10_RETURN_TYPE_UINT == TGSI_RETURN_TYPE_UINT + 1);
3065 STATIC_ASSERT(VGPU10_RETURN_TYPE_FLOAT == TGSI_RETURN_TYPE_FLOAT + 1);
3066 assert(emit->sampler_return_type[i] <= TGSI_RETURN_TYPE_FLOAT);
3067 rt = emit->sampler_return_type[i] + 1;
3068 #else
3069 switch (emit->sampler_return_type[i]) {
3070 case TGSI_RETURN_TYPE_UNORM: rt = VGPU10_RETURN_TYPE_UNORM; break;
3071 case TGSI_RETURN_TYPE_SNORM: rt = VGPU10_RETURN_TYPE_SNORM; break;
3072 case TGSI_RETURN_TYPE_SINT: rt = VGPU10_RETURN_TYPE_SINT; break;
3073 case TGSI_RETURN_TYPE_UINT: rt = VGPU10_RETURN_TYPE_UINT; break;
3074 case TGSI_RETURN_TYPE_FLOAT: rt = VGPU10_RETURN_TYPE_FLOAT; break;
3075 case TGSI_RETURN_TYPE_COUNT:
3076 default:
3077 rt = VGPU10_RETURN_TYPE_FLOAT;
3078 assert(!"emit_resource_declarations: Unknown tgsi_return_type");
3079 }
3080 #endif
3081
3082 return_type.value = 0;
3083 return_type.component0 = rt;
3084 return_type.component1 = rt;
3085 return_type.component2 = rt;
3086 return_type.component3 = rt;
3087
3088 begin_emit_instruction(emit);
3089 emit_dword(emit, opcode0.value);
3090 emit_dword(emit, operand0.value);
3091 emit_dword(emit, i);
3092 emit_dword(emit, return_type.value);
3093 end_emit_instruction(emit);
3094 }
3095
3096 return TRUE;
3097 }
3098
3099 static void
3100 emit_instruction_op1(struct svga_shader_emitter_v10 *emit,
3101 unsigned opcode,
3102 const struct tgsi_full_dst_register *dst,
3103 const struct tgsi_full_src_register *src,
3104 boolean saturate)
3105 {
3106 begin_emit_instruction(emit);
3107 emit_opcode(emit, opcode, saturate);
3108 emit_dst_register(emit, dst);
3109 emit_src_register(emit, src);
3110 end_emit_instruction(emit);
3111 }
3112
3113 static void
3114 emit_instruction_op2(struct svga_shader_emitter_v10 *emit,
3115 unsigned opcode,
3116 const struct tgsi_full_dst_register *dst,
3117 const struct tgsi_full_src_register *src1,
3118 const struct tgsi_full_src_register *src2,
3119 boolean saturate)
3120 {
3121 begin_emit_instruction(emit);
3122 emit_opcode(emit, opcode, saturate);
3123 emit_dst_register(emit, dst);
3124 emit_src_register(emit, src1);
3125 emit_src_register(emit, src2);
3126 end_emit_instruction(emit);
3127 }
3128
3129 static void
3130 emit_instruction_op3(struct svga_shader_emitter_v10 *emit,
3131 unsigned opcode,
3132 const struct tgsi_full_dst_register *dst,
3133 const struct tgsi_full_src_register *src1,
3134 const struct tgsi_full_src_register *src2,
3135 const struct tgsi_full_src_register *src3,
3136 boolean saturate)
3137 {
3138 begin_emit_instruction(emit);
3139 emit_opcode(emit, opcode, saturate);
3140 emit_dst_register(emit, dst);
3141 emit_src_register(emit, src1);
3142 emit_src_register(emit, src2);
3143 emit_src_register(emit, src3);
3144 end_emit_instruction(emit);
3145 }
3146
3147 /**
3148 * Emit the actual clip distance instructions to be used for clipping
3149 * by copying the clip distance from the temporary registers to the
3150 * CLIPDIST registers written with the enabled planes mask.
3151 * Also copy the clip distance from the temporary to the clip distance
3152 * shadow copy register which will be referenced by the input shader
3153 */
3154 static void
3155 emit_clip_distance_instructions(struct svga_shader_emitter_v10 *emit)
3156 {
3157 struct tgsi_full_src_register tmp_clip_dist_src;
3158 struct tgsi_full_dst_register clip_dist_dst;
3159
3160 unsigned i;
3161 unsigned clip_plane_enable = emit->key.clip_plane_enable;
3162 unsigned clip_dist_tmp_index = emit->clip_dist_tmp_index;
3163 int num_written_clipdist = emit->info.num_written_clipdistance;
3164
3165 assert(emit->clip_dist_out_index != INVALID_INDEX);
3166 assert(emit->clip_dist_tmp_index != INVALID_INDEX);
3167
3168 /**
3169 * Temporary reset the temporary clip dist register index so
3170 * that the copy to the real clip dist register will not
3171 * attempt to copy to the temporary register again
3172 */
3173 emit->clip_dist_tmp_index = INVALID_INDEX;
3174
3175 for (i = 0; i < 2 && num_written_clipdist > 0; i++, num_written_clipdist-=4) {
3176
3177 tmp_clip_dist_src = make_src_temp_reg(clip_dist_tmp_index + i);
3178
3179 /**
3180 * copy to the shadow copy for use by varying variable and
3181 * stream output. All clip distances
3182 * will be written regardless of the enabled clipping planes.
3183 */
3184 clip_dist_dst = make_dst_reg(TGSI_FILE_OUTPUT,
3185 emit->clip_dist_so_index + i);
3186
3187 /* MOV clip_dist_so, tmp_clip_dist */
3188 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &clip_dist_dst,
3189 &tmp_clip_dist_src, FALSE);
3190
3191 /**
3192 * copy those clip distances to enabled clipping planes
3193 * to CLIPDIST registers for clipping
3194 */
3195 if (clip_plane_enable & 0xf) {
3196 clip_dist_dst = make_dst_reg(TGSI_FILE_OUTPUT,
3197 emit->clip_dist_out_index + i);
3198 clip_dist_dst = writemask_dst(&clip_dist_dst, clip_plane_enable & 0xf);
3199
3200 /* MOV CLIPDIST, tmp_clip_dist */
3201 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &clip_dist_dst,
3202 &tmp_clip_dist_src, FALSE);
3203 }
3204 /* four clip planes per clip register */
3205 clip_plane_enable >>= 4;
3206 }
3207 /**
3208 * set the temporary clip dist register index back to the
3209 * temporary index for the next vertex
3210 */
3211 emit->clip_dist_tmp_index = clip_dist_tmp_index;
3212 }
3213
3214 /* Declare clip distance output registers for user-defined clip planes
3215 * or the TGSI_CLIPVERTEX output.
3216 */
3217 static void
3218 emit_clip_distance_declarations(struct svga_shader_emitter_v10 *emit)
3219 {
3220 unsigned num_clip_planes = util_bitcount(emit->key.clip_plane_enable);
3221 unsigned index = emit->num_outputs;
3222 unsigned plane_mask;
3223
3224 assert(emit->unit == PIPE_SHADER_VERTEX ||
3225 emit->unit == PIPE_SHADER_GEOMETRY);
3226 assert(num_clip_planes <= 8);
3227
3228 if (emit->clip_mode != CLIP_LEGACY &&
3229 emit->clip_mode != CLIP_VERTEX) {
3230 return;
3231 }
3232
3233 if (num_clip_planes == 0)
3234 return;
3235
3236 /* Declare one or two clip output registers. The number of components
3237 * in the mask reflects the number of clip planes. For example, if 5
3238 * clip planes are needed, we'll declare outputs similar to:
3239 * dcl_output_siv o2.xyzw, clip_distance
3240 * dcl_output_siv o3.x, clip_distance
3241 */
3242 emit->clip_dist_out_index = index; /* save the starting clip dist reg index */
3243
3244 plane_mask = (1 << num_clip_planes) - 1;
3245 if (plane_mask & 0xf) {
3246 unsigned cmask = plane_mask & VGPU10_OPERAND_4_COMPONENT_MASK_ALL;
3247 emit_output_declaration(emit, VGPU10_OPCODE_DCL_OUTPUT_SIV, index,
3248 VGPU10_NAME_CLIP_DISTANCE, cmask);
3249 emit->num_outputs++;
3250 }
3251 if (plane_mask & 0xf0) {
3252 unsigned cmask = (plane_mask >> 4) & VGPU10_OPERAND_4_COMPONENT_MASK_ALL;
3253 emit_output_declaration(emit, VGPU10_OPCODE_DCL_OUTPUT_SIV, index + 1,
3254 VGPU10_NAME_CLIP_DISTANCE, cmask);
3255 emit->num_outputs++;
3256 }
3257 }
3258
3259
3260 /**
3261 * Emit the instructions for writing to the clip distance registers
3262 * to handle legacy/automatic clip planes.
3263 * For each clip plane, the distance is the dot product of the vertex
3264 * position (found in TEMP[vpos_tmp_index]) and the clip plane coefficients.
3265 * This is not used when the shader has an explicit CLIPVERTEX or CLIPDISTANCE
3266 * output registers already declared.
3267 */
3268 static void
3269 emit_clip_distance_from_vpos(struct svga_shader_emitter_v10 *emit,
3270 unsigned vpos_tmp_index)
3271 {
3272 unsigned i, num_clip_planes = util_bitcount(emit->key.clip_plane_enable);
3273
3274 assert(emit->clip_mode == CLIP_LEGACY);
3275 assert(num_clip_planes <= 8);
3276
3277 assert(emit->unit == PIPE_SHADER_VERTEX ||
3278 emit->unit == PIPE_SHADER_GEOMETRY);
3279
3280 for (i = 0; i < num_clip_planes; i++) {
3281 struct tgsi_full_dst_register dst;
3282 struct tgsi_full_src_register plane_src, vpos_src;
3283 unsigned reg_index = emit->clip_dist_out_index + i / 4;
3284 unsigned comp = i % 4;
3285 unsigned writemask = VGPU10_OPERAND_4_COMPONENT_MASK_X << comp;
3286
3287 /* create dst, src regs */
3288 dst = make_dst_reg(TGSI_FILE_OUTPUT, reg_index);
3289 dst = writemask_dst(&dst, writemask);
3290
3291 plane_src = make_src_const_reg(emit->clip_plane_const[i]);
3292 vpos_src = make_src_temp_reg(vpos_tmp_index);
3293
3294 /* DP4 clip_dist, plane, vpos */
3295 emit_instruction_op2(emit, VGPU10_OPCODE_DP4, &dst,
3296 &plane_src, &vpos_src, FALSE);
3297 }
3298 }
3299
3300
3301 /**
3302 * Emit the instructions for computing the clip distance results from
3303 * the clip vertex temporary.
3304 * For each clip plane, the distance is the dot product of the clip vertex
3305 * position (found in a temp reg) and the clip plane coefficients.
3306 */
3307 static void
3308 emit_clip_vertex_instructions(struct svga_shader_emitter_v10 *emit)
3309 {
3310 const unsigned num_clip = util_bitcount(emit->key.clip_plane_enable);
3311 unsigned i;
3312 struct tgsi_full_dst_register dst;
3313 struct tgsi_full_src_register clipvert_src;
3314 const unsigned clip_vertex_tmp = emit->clip_vertex_tmp_index;
3315
3316 assert(emit->unit == PIPE_SHADER_VERTEX ||
3317 emit->unit == PIPE_SHADER_GEOMETRY);
3318
3319 assert(emit->clip_mode == CLIP_VERTEX);
3320
3321 clipvert_src = make_src_temp_reg(clip_vertex_tmp);
3322
3323 for (i = 0; i < num_clip; i++) {
3324 struct tgsi_full_src_register plane_src;
3325 unsigned reg_index = emit->clip_dist_out_index + i / 4;
3326 unsigned comp = i % 4;
3327 unsigned writemask = VGPU10_OPERAND_4_COMPONENT_MASK_X << comp;
3328
3329 /* create dst, src regs */
3330 dst = make_dst_reg(TGSI_FILE_OUTPUT, reg_index);
3331 dst = writemask_dst(&dst, writemask);
3332
3333 plane_src = make_src_const_reg(emit->clip_plane_const[i]);
3334
3335 /* DP4 clip_dist, plane, vpos */
3336 emit_instruction_op2(emit, VGPU10_OPCODE_DP4, &dst,
3337 &plane_src, &clipvert_src, FALSE);
3338 }
3339
3340 /* copy temporary clip vertex register to the clip vertex register */
3341
3342 assert(emit->clip_vertex_out_index != INVALID_INDEX);
3343
3344 /**
3345 * temporary reset the temporary clip vertex register index so
3346 * that copy to the clip vertex register will not attempt
3347 * to copy to the temporary register again
3348 */
3349 emit->clip_vertex_tmp_index = INVALID_INDEX;
3350
3351 /* MOV clip_vertex, clip_vertex_tmp */
3352 dst = make_dst_reg(TGSI_FILE_OUTPUT, emit->clip_vertex_out_index);
3353 emit_instruction_op1(emit, VGPU10_OPCODE_MOV,
3354 &dst, &clipvert_src, FALSE);
3355
3356 /**
3357 * set the temporary clip vertex register index back to the
3358 * temporary index for the next vertex
3359 */
3360 emit->clip_vertex_tmp_index = clip_vertex_tmp;
3361 }
3362
3363 /**
3364 * Emit code to convert RGBA to BGRA
3365 */
3366 static void
3367 emit_swap_r_b(struct svga_shader_emitter_v10 *emit,
3368 const struct tgsi_full_dst_register *dst,
3369 const struct tgsi_full_src_register *src)
3370 {
3371 struct tgsi_full_src_register bgra_src =
3372 swizzle_src(src, TGSI_SWIZZLE_Z, TGSI_SWIZZLE_Y, TGSI_SWIZZLE_X, TGSI_SWIZZLE_W);
3373
3374 begin_emit_instruction(emit);
3375 emit_opcode(emit, VGPU10_OPCODE_MOV, FALSE);
3376 emit_dst_register(emit, dst);
3377 emit_src_register(emit, &bgra_src);
3378 end_emit_instruction(emit);
3379 }
3380
3381
3382 /** Convert from 10_10_10_2 normalized to 10_10_10_2_snorm */
3383 static void
3384 emit_puint_to_snorm(struct svga_shader_emitter_v10 *emit,
3385 const struct tgsi_full_dst_register *dst,
3386 const struct tgsi_full_src_register *src)
3387 {
3388 struct tgsi_full_src_register half = make_immediate_reg_float(emit, 0.5f);
3389 struct tgsi_full_src_register two =
3390 make_immediate_reg_float4(emit, 2.0f, 2.0f, 2.0f, 3.0f);
3391 struct tgsi_full_src_register neg_two =
3392 make_immediate_reg_float4(emit, -2.0f, -2.0f, -2.0f, -1.66666f);
3393
3394 unsigned val_tmp = get_temp_index(emit);
3395 struct tgsi_full_dst_register val_dst = make_dst_temp_reg(val_tmp);
3396 struct tgsi_full_src_register val_src = make_src_temp_reg(val_tmp);
3397
3398 unsigned bias_tmp = get_temp_index(emit);
3399 struct tgsi_full_dst_register bias_dst = make_dst_temp_reg(bias_tmp);
3400 struct tgsi_full_src_register bias_src = make_src_temp_reg(bias_tmp);
3401
3402 /* val = src * 2.0 */
3403 emit_instruction_op2(emit, VGPU10_OPCODE_MUL, &val_dst,
3404 src, &two, FALSE);
3405
3406 /* bias = src > 0.5 */
3407 emit_instruction_op2(emit, VGPU10_OPCODE_GE, &bias_dst,
3408 src, &half, FALSE);
3409
3410 /* bias = bias & -2.0 */
3411 emit_instruction_op2(emit, VGPU10_OPCODE_AND, &bias_dst,
3412 &bias_src, &neg_two, FALSE);
3413
3414 /* dst = val + bias */
3415 emit_instruction_op2(emit, VGPU10_OPCODE_ADD, dst,
3416 &val_src, &bias_src, FALSE);
3417
3418 free_temp_indexes(emit);
3419 }
3420
3421
3422 /** Convert from 10_10_10_2_unorm to 10_10_10_2_uscaled */
3423 static void
3424 emit_puint_to_uscaled(struct svga_shader_emitter_v10 *emit,
3425 const struct tgsi_full_dst_register *dst,
3426 const struct tgsi_full_src_register *src)
3427 {
3428 struct tgsi_full_src_register scale =
3429 make_immediate_reg_float4(emit, 1023.0f, 1023.0f, 1023.0f, 3.0f);
3430
3431 /* dst = src * scale */
3432 emit_instruction_op2(emit, VGPU10_OPCODE_MUL, dst, src, &scale, FALSE);
3433 }
3434
3435
3436 /** Convert from R32_UINT to 10_10_10_2_sscaled */
3437 static void
3438 emit_puint_to_sscaled(struct svga_shader_emitter_v10 *emit,
3439 const struct tgsi_full_dst_register *dst,
3440 const struct tgsi_full_src_register *src)
3441 {
3442 struct tgsi_full_src_register lshift =
3443 make_immediate_reg_int4(emit, 22, 12, 2, 0);
3444 struct tgsi_full_src_register rshift =
3445 make_immediate_reg_int4(emit, 22, 22, 22, 30);
3446
3447 struct tgsi_full_src_register src_xxxx = scalar_src(src, TGSI_SWIZZLE_X);
3448
3449 unsigned tmp = get_temp_index(emit);
3450 struct tgsi_full_dst_register tmp_dst = make_dst_temp_reg(tmp);
3451 struct tgsi_full_src_register tmp_src = make_src_temp_reg(tmp);
3452
3453 /*
3454 * r = (pixel << 22) >> 22; # signed int in [511, -512]
3455 * g = (pixel << 12) >> 22; # signed int in [511, -512]
3456 * b = (pixel << 2) >> 22; # signed int in [511, -512]
3457 * a = (pixel << 0) >> 30; # signed int in [1, -2]
3458 * dst = i_to_f(r,g,b,a); # convert to float
3459 */
3460 emit_instruction_op2(emit, VGPU10_OPCODE_ISHL, &tmp_dst,
3461 &src_xxxx, &lshift, FALSE);
3462 emit_instruction_op2(emit, VGPU10_OPCODE_ISHR, &tmp_dst,
3463 &tmp_src, &rshift, FALSE);
3464 emit_instruction_op1(emit, VGPU10_OPCODE_ITOF, dst, &tmp_src, FALSE);
3465
3466 free_temp_indexes(emit);
3467 }
3468
3469
3470 /**
3471 * Emit code for TGSI_OPCODE_ARL or TGSI_OPCODE_UARL instruction.
3472 */
3473 static boolean
3474 emit_arl_uarl(struct svga_shader_emitter_v10 *emit,
3475 const struct tgsi_full_instruction *inst)
3476 {
3477 unsigned index = inst->Dst[0].Register.Index;
3478 struct tgsi_full_dst_register dst;
3479 unsigned opcode;
3480
3481 assert(index < MAX_VGPU10_ADDR_REGS);
3482 dst = make_dst_temp_reg(emit->address_reg_index[index]);
3483
3484 /* ARL dst, s0
3485 * Translates into:
3486 * FTOI address_tmp, s0
3487 *
3488 * UARL dst, s0
3489 * Translates into:
3490 * MOV address_tmp, s0
3491 */
3492 if (inst->Instruction.Opcode == TGSI_OPCODE_ARL)
3493 opcode = VGPU10_OPCODE_FTOI;
3494 else
3495 opcode = VGPU10_OPCODE_MOV;
3496
3497 emit_instruction_op1(emit, opcode, &dst, &inst->Src[0], FALSE);
3498
3499 return TRUE;
3500 }
3501
3502
3503 /**
3504 * Emit code for TGSI_OPCODE_CAL instruction.
3505 */
3506 static boolean
3507 emit_cal(struct svga_shader_emitter_v10 *emit,
3508 const struct tgsi_full_instruction *inst)
3509 {
3510 unsigned label = inst->Label.Label;
3511 VGPU10OperandToken0 operand;
3512 operand.value = 0;
3513 operand.operandType = VGPU10_OPERAND_TYPE_LABEL;
3514
3515 begin_emit_instruction(emit);
3516 emit_dword(emit, operand.value);
3517 emit_dword(emit, label);
3518 end_emit_instruction(emit);
3519
3520 return TRUE;
3521 }
3522
3523
3524 /**
3525 * Emit code for TGSI_OPCODE_IABS instruction.
3526 */
3527 static boolean
3528 emit_iabs(struct svga_shader_emitter_v10 *emit,
3529 const struct tgsi_full_instruction *inst)
3530 {
3531 /* dst.x = (src0.x < 0) ? -src0.x : src0.x
3532 * dst.y = (src0.y < 0) ? -src0.y : src0.y
3533 * dst.z = (src0.z < 0) ? -src0.z : src0.z
3534 * dst.w = (src0.w < 0) ? -src0.w : src0.w
3535 *
3536 * Translates into
3537 * IMAX dst, src, neg(src)
3538 */
3539 struct tgsi_full_src_register neg_src = negate_src(&inst->Src[0]);
3540 emit_instruction_op2(emit, VGPU10_OPCODE_IMAX, &inst->Dst[0],
3541 &inst->Src[0], &neg_src, FALSE);
3542
3543 return TRUE;
3544 }
3545
3546
3547 /**
3548 * Emit code for TGSI_OPCODE_CMP instruction.
3549 */
3550 static boolean
3551 emit_cmp(struct svga_shader_emitter_v10 *emit,
3552 const struct tgsi_full_instruction *inst)
3553 {
3554 /* dst.x = (src0.x < 0) ? src1.x : src2.x
3555 * dst.y = (src0.y < 0) ? src1.y : src2.y
3556 * dst.z = (src0.z < 0) ? src1.z : src2.z
3557 * dst.w = (src0.w < 0) ? src1.w : src2.w
3558 *
3559 * Translates into
3560 * LT tmp, src0, 0.0
3561 * MOVC dst, tmp, src1, src2
3562 */
3563 struct tgsi_full_src_register zero = make_immediate_reg_float(emit, 0.0f);
3564 unsigned tmp = get_temp_index(emit);
3565 struct tgsi_full_src_register tmp_src = make_src_temp_reg(tmp);
3566 struct tgsi_full_dst_register tmp_dst = make_dst_temp_reg(tmp);
3567
3568 emit_instruction_op2(emit, VGPU10_OPCODE_LT, &tmp_dst,
3569 &inst->Src[0], &zero, FALSE);
3570 emit_instruction_op3(emit, VGPU10_OPCODE_MOVC, &inst->Dst[0],
3571 &tmp_src, &inst->Src[1], &inst->Src[2],
3572 inst->Instruction.Saturate);
3573
3574 free_temp_indexes(emit);
3575
3576 return TRUE;
3577 }
3578
3579
3580 /**
3581 * Emit code for TGSI_OPCODE_DST instruction.
3582 */
3583 static boolean
3584 emit_dst(struct svga_shader_emitter_v10 *emit,
3585 const struct tgsi_full_instruction *inst)
3586 {
3587 /*
3588 * dst.x = 1
3589 * dst.y = src0.y * src1.y
3590 * dst.z = src0.z
3591 * dst.w = src1.w
3592 */
3593
3594 struct tgsi_full_src_register s0_yyyy =
3595 scalar_src(&inst->Src[0], TGSI_SWIZZLE_Y);
3596 struct tgsi_full_src_register s0_zzzz =
3597 scalar_src(&inst->Src[0], TGSI_SWIZZLE_Z);
3598 struct tgsi_full_src_register s1_yyyy =
3599 scalar_src(&inst->Src[1], TGSI_SWIZZLE_Y);
3600 struct tgsi_full_src_register s1_wwww =
3601 scalar_src(&inst->Src[1], TGSI_SWIZZLE_W);
3602
3603 /*
3604 * If dst and either src0 and src1 are the same we need
3605 * to create a temporary for it and insert a extra move.
3606 */
3607 unsigned tmp_move = get_temp_index(emit);
3608 struct tgsi_full_src_register move_src = make_src_temp_reg(tmp_move);
3609 struct tgsi_full_dst_register move_dst = make_dst_temp_reg(tmp_move);
3610
3611 /* MOV dst.x, 1.0 */
3612 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3613 struct tgsi_full_dst_register dst_x =
3614 writemask_dst(&move_dst, TGSI_WRITEMASK_X);
3615 struct tgsi_full_src_register one = make_immediate_reg_float(emit, 1.0f);
3616
3617 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &dst_x, &one, FALSE);
3618 }
3619
3620 /* MUL dst.y, s0.y, s1.y */
3621 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3622 struct tgsi_full_dst_register dst_y =
3623 writemask_dst(&move_dst, TGSI_WRITEMASK_Y);
3624
3625 emit_instruction_op2(emit, VGPU10_OPCODE_MUL, &dst_y, &s0_yyyy,
3626 &s1_yyyy, inst->Instruction.Saturate);
3627 }
3628
3629 /* MOV dst.z, s0.z */
3630 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3631 struct tgsi_full_dst_register dst_z =
3632 writemask_dst(&move_dst, TGSI_WRITEMASK_Z);
3633
3634 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &dst_z, &s0_zzzz,
3635 inst->Instruction.Saturate);
3636 }
3637
3638 /* MOV dst.w, s1.w */
3639 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3640 struct tgsi_full_dst_register dst_w =
3641 writemask_dst(&move_dst, TGSI_WRITEMASK_W);
3642
3643 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &dst_w, &s1_wwww,
3644 inst->Instruction.Saturate);
3645 }
3646
3647 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &inst->Dst[0], &move_src,
3648 FALSE);
3649 free_temp_indexes(emit);
3650
3651 return TRUE;
3652 }
3653
3654
3655
3656 /**
3657 * Emit code for TGSI_OPCODE_ENDPRIM (GS only)
3658 */
3659 static boolean
3660 emit_endprim(struct svga_shader_emitter_v10 *emit,
3661 const struct tgsi_full_instruction *inst)
3662 {
3663 assert(emit->unit == PIPE_SHADER_GEOMETRY);
3664
3665 /* We can't use emit_simple() because the TGSI instruction has one
3666 * operand (vertex stream number) which we must ignore for VGPU10.
3667 */
3668 begin_emit_instruction(emit);
3669 emit_opcode(emit, VGPU10_OPCODE_CUT, FALSE);
3670 end_emit_instruction(emit);
3671 return TRUE;
3672 }
3673
3674
3675 /**
3676 * Emit code for TGSI_OPCODE_EX2 (2^x) instruction.
3677 */
3678 static boolean
3679 emit_ex2(struct svga_shader_emitter_v10 *emit,
3680 const struct tgsi_full_instruction *inst)
3681 {
3682 /* Note that TGSI_OPCODE_EX2 computes only one value from src.x
3683 * while VGPU10 computes four values.
3684 *
3685 * dst = EX2(src):
3686 * dst.xyzw = 2.0 ^ src.x
3687 */
3688
3689 struct tgsi_full_src_register src_xxxx =
3690 swizzle_src(&inst->Src[0], TGSI_SWIZZLE_X, TGSI_SWIZZLE_X,
3691 TGSI_SWIZZLE_X, TGSI_SWIZZLE_X);
3692
3693 /* EXP tmp, s0.xxxx */
3694 emit_instruction_op1(emit, VGPU10_OPCODE_EXP, &inst->Dst[0], &src_xxxx,
3695 inst->Instruction.Saturate);
3696
3697 return TRUE;
3698 }
3699
3700
3701 /**
3702 * Emit code for TGSI_OPCODE_EXP instruction.
3703 */
3704 static boolean
3705 emit_exp(struct svga_shader_emitter_v10 *emit,
3706 const struct tgsi_full_instruction *inst)
3707 {
3708 /*
3709 * dst.x = 2 ^ floor(s0.x)
3710 * dst.y = s0.x - floor(s0.x)
3711 * dst.z = 2 ^ s0.x
3712 * dst.w = 1.0
3713 */
3714
3715 struct tgsi_full_src_register src_xxxx =
3716 scalar_src(&inst->Src[0], TGSI_SWIZZLE_X);
3717 unsigned tmp = get_temp_index(emit);
3718 struct tgsi_full_src_register tmp_src = make_src_temp_reg(tmp);
3719 struct tgsi_full_dst_register tmp_dst = make_dst_temp_reg(tmp);
3720
3721 /*
3722 * If dst and src are the same we need to create
3723 * a temporary for it and insert a extra move.
3724 */
3725 unsigned tmp_move = get_temp_index(emit);
3726 struct tgsi_full_src_register move_src = make_src_temp_reg(tmp_move);
3727 struct tgsi_full_dst_register move_dst = make_dst_temp_reg(tmp_move);
3728
3729 /* only use X component of temp reg */
3730 tmp_dst = writemask_dst(&tmp_dst, TGSI_WRITEMASK_X);
3731 tmp_src = scalar_src(&tmp_src, TGSI_SWIZZLE_X);
3732
3733 /* ROUND_NI tmp.x, s0.x */
3734 emit_instruction_op1(emit, VGPU10_OPCODE_ROUND_NI, &tmp_dst,
3735 &src_xxxx, FALSE); /* round to -infinity */
3736
3737 /* EXP dst.x, tmp.x */
3738 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3739 struct tgsi_full_dst_register dst_x =
3740 writemask_dst(&move_dst, TGSI_WRITEMASK_X);
3741
3742 emit_instruction_op1(emit, VGPU10_OPCODE_EXP, &dst_x, &tmp_src,
3743 inst->Instruction.Saturate);
3744 }
3745
3746 /* ADD dst.y, s0.x, -tmp */
3747 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3748 struct tgsi_full_dst_register dst_y =
3749 writemask_dst(&move_dst, TGSI_WRITEMASK_Y);
3750 struct tgsi_full_src_register neg_tmp_src = negate_src(&tmp_src);
3751
3752 emit_instruction_op2(emit, VGPU10_OPCODE_ADD, &dst_y, &src_xxxx,
3753 &neg_tmp_src, inst->Instruction.Saturate);
3754 }
3755
3756 /* EXP dst.z, s0.x */
3757 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3758 struct tgsi_full_dst_register dst_z =
3759 writemask_dst(&move_dst, TGSI_WRITEMASK_Z);
3760
3761 emit_instruction_op1(emit, VGPU10_OPCODE_EXP, &dst_z, &src_xxxx,
3762 inst->Instruction.Saturate);
3763 }
3764
3765 /* MOV dst.w, 1.0 */
3766 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3767 struct tgsi_full_dst_register dst_w =
3768 writemask_dst(&move_dst, TGSI_WRITEMASK_W);
3769 struct tgsi_full_src_register one = make_immediate_reg_float(emit, 1.0f);
3770
3771 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &dst_w, &one,
3772 FALSE);
3773 }
3774
3775 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &inst->Dst[0], &move_src,
3776 FALSE);
3777
3778 free_temp_indexes(emit);
3779
3780 return TRUE;
3781 }
3782
3783
3784 /**
3785 * Emit code for TGSI_OPCODE_IF instruction.
3786 */
3787 static boolean
3788 emit_if(struct svga_shader_emitter_v10 *emit,
3789 const struct tgsi_full_instruction *inst)
3790 {
3791 VGPU10OpcodeToken0 opcode0;
3792
3793 /* The src register should be a scalar */
3794 assert(inst->Src[0].Register.SwizzleX == inst->Src[0].Register.SwizzleY &&
3795 inst->Src[0].Register.SwizzleX == inst->Src[0].Register.SwizzleZ &&
3796 inst->Src[0].Register.SwizzleX == inst->Src[0].Register.SwizzleW);
3797
3798 /* The only special thing here is that we need to set the
3799 * VGPU10_INSTRUCTION_TEST_NONZERO flag since we want to test if
3800 * src.x is non-zero.
3801 */
3802 opcode0.value = 0;
3803 opcode0.opcodeType = VGPU10_OPCODE_IF;
3804 opcode0.testBoolean = VGPU10_INSTRUCTION_TEST_NONZERO;
3805
3806 begin_emit_instruction(emit);
3807 emit_dword(emit, opcode0.value);
3808 emit_src_register(emit, &inst->Src[0]);
3809 end_emit_instruction(emit);
3810
3811 return TRUE;
3812 }
3813
3814
3815 /**
3816 * Emit code for TGSI_OPCODE_KILL_IF instruction (kill fragment if any of
3817 * the register components are negative).
3818 */
3819 static boolean
3820 emit_kill_if(struct svga_shader_emitter_v10 *emit,
3821 const struct tgsi_full_instruction *inst)
3822 {
3823 unsigned tmp = get_temp_index(emit);
3824 struct tgsi_full_src_register tmp_src = make_src_temp_reg(tmp);
3825 struct tgsi_full_dst_register tmp_dst = make_dst_temp_reg(tmp);
3826
3827 struct tgsi_full_src_register zero = make_immediate_reg_float(emit, 0.0f);
3828
3829 struct tgsi_full_dst_register tmp_dst_x =
3830 writemask_dst(&tmp_dst, TGSI_WRITEMASK_X);
3831 struct tgsi_full_src_register tmp_src_xxxx =
3832 scalar_src(&tmp_src, TGSI_SWIZZLE_X);
3833
3834 /* tmp = src[0] < 0.0 */
3835 emit_instruction_op2(emit, VGPU10_OPCODE_LT, &tmp_dst, &inst->Src[0],
3836 &zero, FALSE);
3837
3838 if (!same_swizzle_terms(&inst->Src[0])) {
3839 /* If the swizzle is not XXXX, YYYY, ZZZZ or WWWW we need to
3840 * logically OR the swizzle terms. Most uses of KILL_IF only
3841 * test one channel so it's good to avoid these extra steps.
3842 */
3843 struct tgsi_full_src_register tmp_src_yyyy =
3844 scalar_src(&tmp_src, TGSI_SWIZZLE_Y);
3845 struct tgsi_full_src_register tmp_src_zzzz =
3846 scalar_src(&tmp_src, TGSI_SWIZZLE_Z);
3847 struct tgsi_full_src_register tmp_src_wwww =
3848 scalar_src(&tmp_src, TGSI_SWIZZLE_W);
3849
3850 emit_instruction_op2(emit, VGPU10_OPCODE_OR, &tmp_dst_x, &tmp_src_xxxx,
3851 &tmp_src_yyyy, FALSE);
3852 emit_instruction_op2(emit, VGPU10_OPCODE_OR, &tmp_dst_x, &tmp_src_xxxx,
3853 &tmp_src_zzzz, FALSE);
3854 emit_instruction_op2(emit, VGPU10_OPCODE_OR, &tmp_dst_x, &tmp_src_xxxx,
3855 &tmp_src_wwww, FALSE);
3856 }
3857
3858 begin_emit_instruction(emit);
3859 emit_discard_opcode(emit, TRUE); /* discard if src0.x is non-zero */
3860 emit_src_register(emit, &tmp_src_xxxx);
3861 end_emit_instruction(emit);
3862
3863 free_temp_indexes(emit);
3864
3865 return TRUE;
3866 }
3867
3868
3869 /**
3870 * Emit code for TGSI_OPCODE_KILL instruction (unconditional discard).
3871 */
3872 static boolean
3873 emit_kill(struct svga_shader_emitter_v10 *emit,
3874 const struct tgsi_full_instruction *inst)
3875 {
3876 struct tgsi_full_src_register zero = make_immediate_reg_float(emit, 0.0f);
3877
3878 /* DISCARD if 0.0 is zero */
3879 begin_emit_instruction(emit);
3880 emit_discard_opcode(emit, FALSE);
3881 emit_src_register(emit, &zero);
3882 end_emit_instruction(emit);
3883
3884 return TRUE;
3885 }
3886
3887
3888 /**
3889 * Emit code for TGSI_OPCODE_LG2 instruction.
3890 */
3891 static boolean
3892 emit_lg2(struct svga_shader_emitter_v10 *emit,
3893 const struct tgsi_full_instruction *inst)
3894 {
3895 /* Note that TGSI_OPCODE_LG2 computes only one value from src.x
3896 * while VGPU10 computes four values.
3897 *
3898 * dst = LG2(src):
3899 * dst.xyzw = log2(src.x)
3900 */
3901
3902 struct tgsi_full_src_register src_xxxx =
3903 swizzle_src(&inst->Src[0], TGSI_SWIZZLE_X, TGSI_SWIZZLE_X,
3904 TGSI_SWIZZLE_X, TGSI_SWIZZLE_X);
3905
3906 /* LOG tmp, s0.xxxx */
3907 emit_instruction_op1(emit, VGPU10_OPCODE_LOG, &inst->Dst[0], &src_xxxx,
3908 inst->Instruction.Saturate);
3909
3910 return TRUE;
3911 }
3912
3913
3914 /**
3915 * Emit code for TGSI_OPCODE_LIT instruction.
3916 */
3917 static boolean
3918 emit_lit(struct svga_shader_emitter_v10 *emit,
3919 const struct tgsi_full_instruction *inst)
3920 {
3921 struct tgsi_full_src_register one = make_immediate_reg_float(emit, 1.0f);
3922
3923 /*
3924 * If dst and src are the same we need to create
3925 * a temporary for it and insert a extra move.
3926 */
3927 unsigned tmp_move = get_temp_index(emit);
3928 struct tgsi_full_src_register move_src = make_src_temp_reg(tmp_move);
3929 struct tgsi_full_dst_register move_dst = make_dst_temp_reg(tmp_move);
3930
3931 /*
3932 * dst.x = 1
3933 * dst.y = max(src.x, 0)
3934 * dst.z = (src.x > 0) ? max(src.y, 0)^{clamp(src.w, -128, 128))} : 0
3935 * dst.w = 1
3936 */
3937
3938 /* MOV dst.x, 1.0 */
3939 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3940 struct tgsi_full_dst_register dst_x =
3941 writemask_dst(&move_dst, TGSI_WRITEMASK_X);
3942 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &dst_x, &one, FALSE);
3943 }
3944
3945 /* MOV dst.w, 1.0 */
3946 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3947 struct tgsi_full_dst_register dst_w =
3948 writemask_dst(&move_dst, TGSI_WRITEMASK_W);
3949 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &dst_w, &one, FALSE);
3950 }
3951
3952 /* MAX dst.y, src.x, 0.0 */
3953 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3954 struct tgsi_full_dst_register dst_y =
3955 writemask_dst(&move_dst, TGSI_WRITEMASK_Y);
3956 struct tgsi_full_src_register zero =
3957 make_immediate_reg_float(emit, 0.0f);
3958 struct tgsi_full_src_register src_xxxx =
3959 swizzle_src(&inst->Src[0], TGSI_SWIZZLE_X, TGSI_SWIZZLE_X,
3960 TGSI_SWIZZLE_X, TGSI_SWIZZLE_X);
3961
3962 emit_instruction_op2(emit, VGPU10_OPCODE_MAX, &dst_y, &src_xxxx,
3963 &zero, inst->Instruction.Saturate);
3964 }
3965
3966 /*
3967 * tmp1 = clamp(src.w, -128, 128);
3968 * MAX tmp1, src.w, -128
3969 * MIN tmp1, tmp1, 128
3970 *
3971 * tmp2 = max(tmp2, 0);
3972 * MAX tmp2, src.y, 0
3973 *
3974 * tmp1 = pow(tmp2, tmp1);
3975 * LOG tmp2, tmp2
3976 * MUL tmp1, tmp2, tmp1
3977 * EXP tmp1, tmp1
3978 *
3979 * tmp1 = (src.w == 0) ? 1 : tmp1;
3980 * EQ tmp2, 0, src.w
3981 * MOVC tmp1, tmp2, 1.0, tmp1
3982 *
3983 * dst.z = (0 < src.x) ? tmp1 : 0;
3984 * LT tmp2, 0, src.x
3985 * MOVC dst.z, tmp2, tmp1, 0.0
3986 */
3987 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3988 struct tgsi_full_dst_register dst_z =
3989 writemask_dst(&move_dst, TGSI_WRITEMASK_Z);
3990
3991 unsigned tmp1 = get_temp_index(emit);
3992 struct tgsi_full_src_register tmp1_src = make_src_temp_reg(tmp1);
3993 struct tgsi_full_dst_register tmp1_dst = make_dst_temp_reg(tmp1);
3994 unsigned tmp2 = get_temp_index(emit);
3995 struct tgsi_full_src_register tmp2_src = make_src_temp_reg(tmp2);
3996 struct tgsi_full_dst_register tmp2_dst = make_dst_temp_reg(tmp2);
3997
3998 struct tgsi_full_src_register src_xxxx =
3999 scalar_src(&inst->Src[0], TGSI_SWIZZLE_X);
4000 struct tgsi_full_src_register src_yyyy =
4001 scalar_src(&inst->Src[0], TGSI_SWIZZLE_Y);
4002 struct tgsi_full_src_register src_wwww =
4003 scalar_src(&inst->Src[0], TGSI_SWIZZLE_W);
4004
4005 struct tgsi_full_src_register zero =
4006 make_immediate_reg_float(emit, 0.0f);
4007 struct tgsi_full_src_register lowerbound =
4008 make_immediate_reg_float(emit, -128.0f);
4009 struct tgsi_full_src_register upperbound =
4010 make_immediate_reg_float(emit, 128.0f);
4011
4012 emit_instruction_op2(emit, VGPU10_OPCODE_MAX, &tmp1_dst, &src_wwww,
4013 &lowerbound, FALSE);
4014 emit_instruction_op2(emit, VGPU10_OPCODE_MIN, &tmp1_dst, &tmp1_src,
4015 &upperbound, FALSE);
4016 emit_instruction_op2(emit, VGPU10_OPCODE_MAX, &tmp2_dst, &src_yyyy,
4017 &zero, FALSE);
4018
4019 /* POW tmp1, tmp2, tmp1 */
4020 /* LOG tmp2, tmp2 */
4021 emit_instruction_op1(emit, VGPU10_OPCODE_LOG, &tmp2_dst, &tmp2_src,
4022 FALSE);
4023
4024 /* MUL tmp1, tmp2, tmp1 */
4025 emit_instruction_op2(emit, VGPU10_OPCODE_MUL, &tmp1_dst, &tmp2_src,
4026 &tmp1_src, FALSE);
4027
4028 /* EXP tmp1, tmp1 */
4029 emit_instruction_op1(emit, VGPU10_OPCODE_EXP, &tmp1_dst, &tmp1_src,
4030 FALSE);
4031
4032 /* EQ tmp2, 0, src.w */
4033 emit_instruction_op2(emit, VGPU10_OPCODE_EQ, &tmp2_dst, &zero,
4034 &src_wwww, FALSE);
4035 /* MOVC tmp1.z, tmp2, tmp1, 1.0 */
4036 emit_instruction_op3(emit, VGPU10_OPCODE_MOVC, &tmp1_dst,
4037 &tmp2_src, &one, &tmp1_src, FALSE);
4038
4039 /* LT tmp2, 0, src.x */
4040 emit_instruction_op2(emit, VGPU10_OPCODE_LT, &tmp2_dst, &zero,
4041 &src_xxxx, FALSE);
4042 /* MOVC dst.z, tmp2, tmp1, 0.0 */
4043 emit_instruction_op3(emit, VGPU10_OPCODE_MOVC, &dst_z,
4044 &tmp2_src, &tmp1_src, &zero, FALSE);
4045 }
4046
4047 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &inst->Dst[0], &move_src,
4048 FALSE);
4049 free_temp_indexes(emit);
4050
4051 return TRUE;
4052 }
4053
4054
4055 /**
4056 * Emit code for TGSI_OPCODE_LOG instruction.
4057 */
4058 static boolean
4059 emit_log(struct svga_shader_emitter_v10 *emit,
4060 const struct tgsi_full_instruction *inst)
4061 {
4062 /*
4063 * dst.x = floor(lg2(abs(s0.x)))
4064 * dst.y = abs(s0.x) / (2 ^ floor(lg2(abs(s0.x))))
4065 * dst.z = lg2(abs(s0.x))
4066 * dst.w = 1.0
4067 */
4068
4069 struct tgsi_full_src_register src_xxxx =
4070 scalar_src(&inst->Src[0], TGSI_SWIZZLE_X);
4071 unsigned tmp = get_temp_index(emit);
4072 struct tgsi_full_src_register tmp_src = make_src_temp_reg(tmp);
4073 struct tgsi_full_dst_register tmp_dst = make_dst_temp_reg(tmp);
4074 struct tgsi_full_src_register abs_src_xxxx = absolute_src(&src_xxxx);
4075
4076 /* only use X component of temp reg */
4077 tmp_dst = writemask_dst(&tmp_dst, TGSI_WRITEMASK_X);
4078 tmp_src = scalar_src(&tmp_src, TGSI_SWIZZLE_X);
4079
4080 /* LOG tmp.x, abs(s0.x) */
4081 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XYZ) {
4082 emit_instruction_op1(emit, VGPU10_OPCODE_LOG, &tmp_dst,
4083 &abs_src_xxxx, FALSE);
4084 }
4085
4086 /* MOV dst.z, tmp.x */
4087 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
4088 struct tgsi_full_dst_register dst_z =
4089 writemask_dst(&inst->Dst[0], TGSI_WRITEMASK_Z);
4090
4091 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &dst_z,
4092 &tmp_src, inst->Instruction.Saturate);
4093 }
4094
4095 /* FLR tmp.x, tmp.x */
4096 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) {
4097 emit_instruction_op1(emit, VGPU10_OPCODE_ROUND_NI, &tmp_dst,
4098 &tmp_src, FALSE);
4099 }
4100
4101 /* MOV dst.x, tmp.x */
4102 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
4103 struct tgsi_full_dst_register dst_x =
4104 writemask_dst(&inst->Dst[0], TGSI_WRITEMASK_X);
4105
4106 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &dst_x, &tmp_src,
4107 inst->Instruction.Saturate);
4108 }
4109
4110 /* EXP tmp.x, tmp.x */
4111 /* DIV dst.y, abs(s0.x), tmp.x */
4112 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
4113 struct tgsi_full_dst_register dst_y =
4114 writemask_dst(&inst->Dst[0], TGSI_WRITEMASK_Y);
4115
4116 emit_instruction_op1(emit, VGPU10_OPCODE_EXP, &tmp_dst, &tmp_src,
4117 FALSE);
4118 emit_instruction_op2(emit, VGPU10_OPCODE_DIV, &dst_y, &abs_src_xxxx,
4119 &tmp_src, inst->Instruction.Saturate);
4120 }
4121
4122 /* MOV dst.w, 1.0 */
4123 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
4124 struct tgsi_full_dst_register dst_w =
4125 writemask_dst(&inst->Dst[0], TGSI_WRITEMASK_W);
4126 struct tgsi_full_src_register one =
4127 make_immediate_reg_float(emit, 1.0f);
4128
4129 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &dst_w, &one, FALSE);
4130 }
4131
4132 free_temp_indexes(emit);
4133
4134 return TRUE;
4135 }
4136
4137
4138 /**
4139 * Emit code for TGSI_OPCODE_LRP instruction.
4140 */
4141 static boolean
4142 emit_lrp(struct svga_shader_emitter_v10 *emit,
4143 const struct tgsi_full_instruction *inst)
4144 {
4145 /* dst = LRP(s0, s1, s2):
4146 * dst = s0 * (s1 - s2) + s2
4147 * Translates into:
4148 * SUB tmp, s1, s2; tmp = s1 - s2
4149 * MAD dst, s0, tmp, s2; dst = s0 * t1 + s2
4150 */
4151 unsigned tmp = get_temp_index(emit);
4152 struct tgsi_full_src_register src_tmp = make_src_temp_reg(tmp);
4153 struct tgsi_full_dst_register dst_tmp = make_dst_temp_reg(tmp);
4154 struct tgsi_full_src_register neg_src2 = negate_src(&inst->Src[2]);
4155
4156 /* ADD tmp, s1, -s2 */
4157 emit_instruction_op2(emit, VGPU10_OPCODE_ADD, &dst_tmp,
4158 &inst->Src[1], &neg_src2, FALSE);
4159
4160 /* MAD dst, s1, tmp, s3 */
4161 emit_instruction_op3(emit, VGPU10_OPCODE_MAD, &inst->Dst[0],
4162 &inst->Src[0], &src_tmp, &inst->Src[2],
4163 inst->Instruction.Saturate);
4164
4165 free_temp_indexes(emit);
4166
4167 return TRUE;
4168 }
4169
4170
4171 /**
4172 * Emit code for TGSI_OPCODE_POW instruction.
4173 */
4174 static boolean
4175 emit_pow(struct svga_shader_emitter_v10 *emit,
4176 const struct tgsi_full_instruction *inst)
4177 {
4178 /* Note that TGSI_OPCODE_POW computes only one value from src0.x and
4179 * src1.x while VGPU10 computes four values.
4180 *
4181 * dst = POW(src0, src1):
4182 * dst.xyzw = src0.x ^ src1.x
4183 */
4184 unsigned tmp = get_temp_index(emit);
4185 struct tgsi_full_src_register tmp_src = make_src_temp_reg(tmp);
4186 struct tgsi_full_dst_register tmp_dst = make_dst_temp_reg(tmp);
4187 struct tgsi_full_src_register src0_xxxx =
4188 swizzle_src(&inst->Src[0], TGSI_SWIZZLE_X, TGSI_SWIZZLE_X,
4189 TGSI_SWIZZLE_X, TGSI_SWIZZLE_X);
4190 struct tgsi_full_src_register src1_xxxx =
4191 swizzle_src(&inst->Src[1], TGSI_SWIZZLE_X, TGSI_SWIZZLE_X,
4192 TGSI_SWIZZLE_X, TGSI_SWIZZLE_X);
4193
4194 /* LOG tmp, s0.xxxx */
4195 emit_instruction_op1(emit, VGPU10_OPCODE_LOG, &tmp_dst, &src0_xxxx,
4196 FALSE);
4197
4198 /* MUL tmp, tmp, s1.xxxx */
4199 emit_instruction_op2(emit, VGPU10_OPCODE_MUL, &tmp_dst, &tmp_src,
4200 &src1_xxxx, FALSE);
4201
4202 /* EXP tmp, s0.xxxx */
4203 emit_instruction_op1(emit, VGPU10_OPCODE_EXP, &inst->Dst[0],
4204 &tmp_src, inst->Instruction.Saturate);
4205
4206 /* free tmp */
4207 free_temp_indexes(emit);
4208
4209 return TRUE;
4210 }
4211
4212
4213 /**
4214 * Emit code for TGSI_OPCODE_RCP (reciprocal) instruction.
4215 */
4216 static boolean
4217 emit_rcp(struct svga_shader_emitter_v10 *emit,
4218 const struct tgsi_full_instruction *inst)
4219 {
4220 struct tgsi_full_src_register one = make_immediate_reg_float(emit, 1.0f);
4221
4222 unsigned tmp = get_temp_index(emit);
4223 struct tgsi_full_src_register tmp_src = make_src_temp_reg(tmp);
4224 struct tgsi_full_dst_register tmp_dst = make_dst_temp_reg(tmp);
4225
4226 struct tgsi_full_dst_register tmp_dst_x =
4227 writemask_dst(&tmp_dst, TGSI_WRITEMASK_X);
4228 struct tgsi_full_src_register tmp_src_xxxx =
4229 scalar_src(&tmp_src, TGSI_SWIZZLE_X);
4230
4231 /* DIV tmp.x, 1.0, s0 */
4232 emit_instruction_op2(emit, VGPU10_OPCODE_DIV, &tmp_dst_x, &one,
4233 &inst->Src[0], FALSE);
4234
4235 /* MOV dst, tmp.xxxx */
4236 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &inst->Dst[0],
4237 &tmp_src_xxxx, inst->Instruction.Saturate);
4238
4239 free_temp_indexes(emit);
4240
4241 return TRUE;
4242 }
4243
4244
4245 /**
4246 * Emit code for TGSI_OPCODE_RSQ instruction.
4247 */
4248 static boolean
4249 emit_rsq(struct svga_shader_emitter_v10 *emit,
4250 const struct tgsi_full_instruction *inst)
4251 {
4252 /* dst = RSQ(src):
4253 * dst.xyzw = 1 / sqrt(src.x)
4254 * Translates into:
4255 * RSQ tmp, src.x
4256 * MOV dst, tmp.xxxx
4257 */
4258
4259 unsigned tmp = get_temp_index(emit);
4260 struct tgsi_full_src_register tmp_src = make_src_temp_reg(tmp);
4261 struct tgsi_full_dst_register tmp_dst = make_dst_temp_reg(tmp);
4262
4263 struct tgsi_full_dst_register tmp_dst_x =
4264 writemask_dst(&tmp_dst, TGSI_WRITEMASK_X);
4265 struct tgsi_full_src_register tmp_src_xxxx =
4266 scalar_src(&tmp_src, TGSI_SWIZZLE_X);
4267
4268 /* RSQ tmp, src.x */
4269 emit_instruction_op1(emit, VGPU10_OPCODE_RSQ, &tmp_dst_x,
4270 &inst->Src[0], FALSE);
4271
4272 /* MOV dst, tmp.xxxx */
4273 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &inst->Dst[0],
4274 &tmp_src_xxxx, inst->Instruction.Saturate);
4275
4276 /* free tmp */
4277 free_temp_indexes(emit);
4278
4279 return TRUE;
4280 }
4281
4282
4283 /**
4284 * Emit code for TGSI_OPCODE_SCS instruction.
4285 */
4286 static boolean
4287 emit_scs(struct svga_shader_emitter_v10 *emit,
4288 const struct tgsi_full_instruction *inst)
4289 {
4290 /* dst.x = cos(src.x)
4291 * dst.y = sin(src.x)
4292 * dst.z = 0.0
4293 * dst.w = 1.0
4294 */
4295 struct tgsi_full_dst_register dst_x =
4296 writemask_dst(&inst->Dst[0], TGSI_WRITEMASK_X);
4297 struct tgsi_full_dst_register dst_y =
4298 writemask_dst(&inst->Dst[0], TGSI_WRITEMASK_Y);
4299 struct tgsi_full_dst_register dst_zw =
4300 writemask_dst(&inst->Dst[0], TGSI_WRITEMASK_ZW);
4301
4302 struct tgsi_full_src_register zero_one =
4303 make_immediate_reg_float4(emit, 0.0f, 0.0f, 0.0f, 1.0f);
4304
4305 begin_emit_instruction(emit);
4306 emit_opcode(emit, VGPU10_OPCODE_SINCOS, inst->Instruction.Saturate);
4307 emit_dst_register(emit, &dst_y);
4308 emit_dst_register(emit, &dst_x);
4309 emit_src_register(emit, &inst->Src[0]);
4310 end_emit_instruction(emit);
4311
4312 emit_instruction_op1(emit, VGPU10_OPCODE_MOV,
4313 &dst_zw, &zero_one, inst->Instruction.Saturate);
4314
4315 return TRUE;
4316 }
4317
4318
4319 /**
4320 * Emit code for TGSI_OPCODE_SEQ (Set Equal) instruction.
4321 */
4322 static boolean
4323 emit_seq(struct svga_shader_emitter_v10 *emit,
4324 const struct tgsi_full_instruction *inst)
4325 {
4326 /* dst = SEQ(s0, s1):
4327 * dst = s0 == s1 ? 1.0 : 0.0 (per component)
4328 * Translates into:
4329 * EQ tmp, s0, s1; tmp = s0 == s1 : 0xffffffff : 0 (per comp)
4330 * MOVC dst, tmp, 1.0, 0.0; dst = tmp ? 1.0 : 0.0 (per component)
4331 */
4332 unsigned tmp = get_temp_index(emit);
4333 struct tgsi_full_src_register tmp_src = make_src_temp_reg(tmp);
4334 struct tgsi_full_dst_register tmp_dst = make_dst_temp_reg(tmp);
4335 struct tgsi_full_src_register zero = make_immediate_reg_float(emit, 0.0f);
4336 struct tgsi_full_src_register one = make_immediate_reg_float(emit, 1.0f);
4337
4338 /* EQ tmp, s0, s1 */
4339 emit_instruction_op2(emit, VGPU10_OPCODE_EQ, &tmp_dst, &inst->Src[0],
4340 &inst->Src[1], FALSE);
4341
4342 /* MOVC dst, tmp, one, zero */
4343 emit_instruction_op3(emit, VGPU10_OPCODE_MOVC, &inst->Dst[0], &tmp_src,
4344 &one, &zero, FALSE);
4345
4346 free_temp_indexes(emit);
4347
4348 return TRUE;
4349 }
4350
4351
4352 /**
4353 * Emit code for TGSI_OPCODE_SGE (Set Greater than or Equal) instruction.
4354 */
4355 static boolean
4356 emit_sge(struct svga_shader_emitter_v10 *emit,
4357 const struct tgsi_full_instruction *inst)
4358 {
4359 /* dst = SGE(s0, s1):
4360 * dst = s0 >= s1 ? 1.0 : 0.0 (per component)
4361 * Translates into:
4362 * GE tmp, s0, s1; tmp = s0 >= s1 : 0xffffffff : 0 (per comp)
4363 * MOVC dst, tmp, 1.0, 0.0; dst = tmp ? 1.0 : 0.0 (per component)
4364 */
4365 unsigned tmp = get_temp_index(emit);
4366 struct tgsi_full_src_register tmp_src = make_src_temp_reg(tmp);
4367 struct tgsi_full_dst_register tmp_dst = make_dst_temp_reg(tmp);
4368 struct tgsi_full_src_register zero = make_immediate_reg_float(emit, 0.0f);
4369 struct tgsi_full_src_register one = make_immediate_reg_float(emit, 1.0f);
4370
4371 /* GE tmp, s0, s1 */
4372 emit_instruction_op2(emit, VGPU10_OPCODE_GE, &tmp_dst, &inst->Src[0],
4373 &inst->Src[1], FALSE);
4374
4375 /* MOVC dst, tmp, one, zero */
4376 emit_instruction_op3(emit, VGPU10_OPCODE_MOVC, &inst->Dst[0], &tmp_src,
4377 &one, &zero, FALSE);
4378
4379 free_temp_indexes(emit);
4380
4381 return TRUE;
4382 }
4383
4384
4385 /**
4386 * Emit code for TGSI_OPCODE_SGT (Set Greater than) instruction.
4387 */
4388 static boolean
4389 emit_sgt(struct svga_shader_emitter_v10 *emit,
4390 const struct tgsi_full_instruction *inst)
4391 {
4392 /* dst = SGT(s0, s1):
4393 * dst = s0 > s1 ? 1.0 : 0.0 (per component)
4394 * Translates into:
4395 * LT tmp, s1, s0; tmp = s1 < s0 ? 0xffffffff : 0 (per comp)
4396 * MOVC dst, tmp, 1.0, 0.0; dst = tmp ? 1.0 : 0.0 (per component)
4397 */
4398 unsigned tmp = get_temp_index(emit);
4399 struct tgsi_full_src_register tmp_src = make_src_temp_reg(tmp);
4400 struct tgsi_full_dst_register tmp_dst = make_dst_temp_reg(tmp);
4401 struct tgsi_full_src_register zero = make_immediate_reg_float(emit, 0.0f);
4402 struct tgsi_full_src_register one = make_immediate_reg_float(emit, 1.0f);
4403
4404 /* LT tmp, s1, s0 */
4405 emit_instruction_op2(emit, VGPU10_OPCODE_LT, &tmp_dst, &inst->Src[1],
4406 &inst->Src[0], FALSE);
4407
4408 /* MOVC dst, tmp, one, zero */
4409 emit_instruction_op3(emit, VGPU10_OPCODE_MOVC, &inst->Dst[0], &tmp_src,
4410 &one, &zero, FALSE);
4411
4412 free_temp_indexes(emit);
4413
4414 return TRUE;
4415 }
4416
4417
4418 /**
4419 * Emit code for TGSI_OPCODE_SIN and TGSI_OPCODE_COS instructions.
4420 */
4421 static boolean
4422 emit_sincos(struct svga_shader_emitter_v10 *emit,
4423 const struct tgsi_full_instruction *inst)
4424 {
4425 unsigned tmp = get_temp_index(emit);
4426 struct tgsi_full_src_register tmp_src = make_src_temp_reg(tmp);
4427 struct tgsi_full_dst_register tmp_dst = make_dst_temp_reg(tmp);
4428
4429 struct tgsi_full_src_register tmp_src_xxxx =
4430 scalar_src(&tmp_src, TGSI_SWIZZLE_X);
4431 struct tgsi_full_dst_register tmp_dst_x =
4432 writemask_dst(&tmp_dst, TGSI_WRITEMASK_X);
4433
4434 begin_emit_instruction(emit);
4435 emit_opcode(emit, VGPU10_OPCODE_SINCOS, FALSE);
4436
4437 if(inst->Instruction.Opcode == TGSI_OPCODE_SIN)
4438 {
4439 emit_dst_register(emit, &tmp_dst_x); /* first destination register */
4440 emit_null_dst_register(emit); /* second destination register */
4441 }
4442 else {
4443 emit_null_dst_register(emit);
4444 emit_dst_register(emit, &tmp_dst_x);
4445 }
4446
4447 emit_src_register(emit, &inst->Src[0]);
4448 end_emit_instruction(emit);
4449
4450 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &inst->Dst[0],
4451 &tmp_src_xxxx, inst->Instruction.Saturate);
4452
4453 free_temp_indexes(emit);
4454
4455 return TRUE;
4456 }
4457
4458
4459 /**
4460 * Emit code for TGSI_OPCODE_SLE (Set Less than or Equal) instruction.
4461 */
4462 static boolean
4463 emit_sle(struct svga_shader_emitter_v10 *emit,
4464 const struct tgsi_full_instruction *inst)
4465 {
4466 /* dst = SLE(s0, s1):
4467 * dst = s0 <= s1 ? 1.0 : 0.0 (per component)
4468 * Translates into:
4469 * GE tmp, s1, s0; tmp = s1 >= s0 : 0xffffffff : 0 (per comp)
4470 * MOVC dst, tmp, 1.0, 0.0; dst = tmp ? 1.0 : 0.0 (per component)
4471 */
4472 unsigned tmp = get_temp_index(emit);
4473 struct tgsi_full_src_register tmp_src = make_src_temp_reg(tmp);
4474 struct tgsi_full_dst_register tmp_dst = make_dst_temp_reg(tmp);
4475 struct tgsi_full_src_register zero = make_immediate_reg_float(emit, 0.0f);
4476 struct tgsi_full_src_register one = make_immediate_reg_float(emit, 1.0f);
4477
4478 /* GE tmp, s1, s0 */
4479 emit_instruction_op2(emit, VGPU10_OPCODE_GE, &tmp_dst, &inst->Src[1],
4480 &inst->Src[0], FALSE);
4481
4482 /* MOVC dst, tmp, one, zero */
4483 emit_instruction_op3(emit, VGPU10_OPCODE_MOVC, &inst->Dst[0], &tmp_src,
4484 &one, &zero, FALSE);
4485
4486 free_temp_indexes(emit);
4487
4488 return TRUE;
4489 }
4490
4491
4492 /**
4493 * Emit code for TGSI_OPCODE_SLT (Set Less than) instruction.
4494 */
4495 static boolean
4496 emit_slt(struct svga_shader_emitter_v10 *emit,
4497 const struct tgsi_full_instruction *inst)
4498 {
4499 /* dst = SLT(s0, s1):
4500 * dst = s0 < s1 ? 1.0 : 0.0 (per component)
4501 * Translates into:
4502 * LT tmp, s0, s1; tmp = s0 < s1 ? 0xffffffff : 0 (per comp)
4503 * MOVC dst, tmp, 1.0, 0.0; dst = tmp ? 1.0 : 0.0 (per component)
4504 */
4505 unsigned tmp = get_temp_index(emit);
4506 struct tgsi_full_src_register tmp_src = make_src_temp_reg(tmp);
4507 struct tgsi_full_dst_register tmp_dst = make_dst_temp_reg(tmp);
4508 struct tgsi_full_src_register zero = make_immediate_reg_float(emit, 0.0f);
4509 struct tgsi_full_src_register one = make_immediate_reg_float(emit, 1.0f);
4510
4511 /* LT tmp, s0, s1 */
4512 emit_instruction_op2(emit, VGPU10_OPCODE_LT, &tmp_dst, &inst->Src[0],
4513 &inst->Src[1], FALSE);
4514
4515 /* MOVC dst, tmp, one, zero */
4516 emit_instruction_op3(emit, VGPU10_OPCODE_MOVC, &inst->Dst[0], &tmp_src,
4517 &one, &zero, FALSE);
4518
4519 free_temp_indexes(emit);
4520
4521 return TRUE;
4522 }
4523
4524
4525 /**
4526 * Emit code for TGSI_OPCODE_SNE (Set Not Equal) instruction.
4527 */
4528 static boolean
4529 emit_sne(struct svga_shader_emitter_v10 *emit,
4530 const struct tgsi_full_instruction *inst)
4531 {
4532 /* dst = SNE(s0, s1):
4533 * dst = s0 != s1 ? 1.0 : 0.0 (per component)
4534 * Translates into:
4535 * EQ tmp, s0, s1; tmp = s0 == s1 : 0xffffffff : 0 (per comp)
4536 * MOVC dst, tmp, 1.0, 0.0; dst = tmp ? 1.0 : 0.0 (per component)
4537 */
4538 unsigned tmp = get_temp_index(emit);
4539 struct tgsi_full_src_register tmp_src = make_src_temp_reg(tmp);
4540 struct tgsi_full_dst_register tmp_dst = make_dst_temp_reg(tmp);
4541 struct tgsi_full_src_register zero = make_immediate_reg_float(emit, 0.0f);
4542 struct tgsi_full_src_register one = make_immediate_reg_float(emit, 1.0f);
4543
4544 /* NE tmp, s0, s1 */
4545 emit_instruction_op2(emit, VGPU10_OPCODE_NE, &tmp_dst, &inst->Src[0],
4546 &inst->Src[1], FALSE);
4547
4548 /* MOVC dst, tmp, one, zero */
4549 emit_instruction_op3(emit, VGPU10_OPCODE_MOVC, &inst->Dst[0], &tmp_src,
4550 &one, &zero, FALSE);
4551
4552 free_temp_indexes(emit);
4553
4554 return TRUE;
4555 }
4556
4557
4558 /**
4559 * Emit code for TGSI_OPCODE_SSG (Set Sign) instruction.
4560 */
4561 static boolean
4562 emit_ssg(struct svga_shader_emitter_v10 *emit,
4563 const struct tgsi_full_instruction *inst)
4564 {
4565 /* dst.x = (src.x > 0.0) ? 1.0 : (src.x < 0.0) ? -1.0 : 0.0
4566 * dst.y = (src.y > 0.0) ? 1.0 : (src.y < 0.0) ? -1.0 : 0.0
4567 * dst.z = (src.z > 0.0) ? 1.0 : (src.z < 0.0) ? -1.0 : 0.0
4568 * dst.w = (src.w > 0.0) ? 1.0 : (src.w < 0.0) ? -1.0 : 0.0
4569 * Translates into:
4570 * LT tmp1, src, zero; tmp1 = src < zero ? 0xffffffff : 0 (per comp)
4571 * MOVC tmp2, tmp1, -1.0, 0.0; tmp2 = tmp1 ? -1.0 : 0.0 (per component)
4572 * LT tmp1, zero, src; tmp1 = zero < src ? 0xffffffff : 0 (per comp)
4573 * MOVC dst, tmp1, 1.0, tmp2; dst = tmp1 ? 1.0 : tmp2 (per component)
4574 */
4575 struct tgsi_full_src_register zero =
4576 make_immediate_reg_float(emit, 0.0f);
4577 struct tgsi_full_src_register one =
4578 make_immediate_reg_float(emit, 1.0f);
4579 struct tgsi_full_src_register neg_one =
4580 make_immediate_reg_float(emit, -1.0f);
4581
4582 unsigned tmp1 = get_temp_index(emit);
4583 struct tgsi_full_src_register tmp1_src = make_src_temp_reg(tmp1);
4584 struct tgsi_full_dst_register tmp1_dst = make_dst_temp_reg(tmp1);
4585
4586 unsigned tmp2 = get_temp_index(emit);
4587 struct tgsi_full_src_register tmp2_src = make_src_temp_reg(tmp2);
4588 struct tgsi_full_dst_register tmp2_dst = make_dst_temp_reg(tmp2);
4589
4590 emit_instruction_op2(emit, VGPU10_OPCODE_LT, &tmp1_dst, &inst->Src[0],
4591 &zero, FALSE);
4592 emit_instruction_op3(emit, VGPU10_OPCODE_MOVC, &tmp2_dst, &tmp1_src,
4593 &neg_one, &zero, FALSE);
4594 emit_instruction_op2(emit, VGPU10_OPCODE_LT, &tmp1_dst, &zero,
4595 &inst->Src[0], FALSE);
4596 emit_instruction_op3(emit, VGPU10_OPCODE_MOVC, &inst->Dst[0], &tmp1_src,
4597 &one, &tmp2_src, FALSE);
4598
4599 free_temp_indexes(emit);
4600
4601 return TRUE;
4602 }
4603
4604
4605 /**
4606 * Emit code for TGSI_OPCODE_ISSG (Integer Set Sign) instruction.
4607 */
4608 static boolean
4609 emit_issg(struct svga_shader_emitter_v10 *emit,
4610 const struct tgsi_full_instruction *inst)
4611 {
4612 /* dst.x = (src.x > 0) ? 1 : (src.x < 0) ? -1 : 0
4613 * dst.y = (src.y > 0) ? 1 : (src.y < 0) ? -1 : 0
4614 * dst.z = (src.z > 0) ? 1 : (src.z < 0) ? -1 : 0
4615 * dst.w = (src.w > 0) ? 1 : (src.w < 0) ? -1 : 0
4616 * Translates into:
4617 * ILT tmp1, src, 0 tmp1 = src < 0 ? -1 : 0 (per component)
4618 * ILT tmp2, 0, src tmp2 = 0 < src ? -1 : 0 (per component)
4619 * IADD dst, tmp1, neg(tmp2) dst = tmp1 - tmp2 (per component)
4620 */
4621 struct tgsi_full_src_register zero = make_immediate_reg_float(emit, 0.0f);
4622
4623 unsigned tmp1 = get_temp_index(emit);
4624 struct tgsi_full_src_register tmp1_src = make_src_temp_reg(tmp1);
4625 struct tgsi_full_dst_register tmp1_dst = make_dst_temp_reg(tmp1);
4626
4627 unsigned tmp2 = get_temp_index(emit);
4628 struct tgsi_full_src_register tmp2_src = make_src_temp_reg(tmp2);
4629 struct tgsi_full_dst_register tmp2_dst = make_dst_temp_reg(tmp2);
4630
4631 struct tgsi_full_src_register neg_tmp2 = negate_src(&tmp2_src);
4632
4633 emit_instruction_op2(emit, VGPU10_OPCODE_ILT, &tmp1_dst,
4634 &inst->Src[0], &zero, FALSE);
4635 emit_instruction_op2(emit, VGPU10_OPCODE_ILT, &tmp2_dst,
4636 &zero, &inst->Src[0], FALSE);
4637 emit_instruction_op2(emit, VGPU10_OPCODE_IADD, &inst->Dst[0],
4638 &tmp1_src, &neg_tmp2, FALSE);
4639
4640 free_temp_indexes(emit);
4641
4642 return TRUE;
4643 }
4644
4645
4646 /**
4647 * Emit a comparison instruction. The dest register will get
4648 * 0 or ~0 values depending on the outcome of comparing src0 to src1.
4649 */
4650 static void
4651 emit_comparison(struct svga_shader_emitter_v10 *emit,
4652 SVGA3dCmpFunc func,
4653 const struct tgsi_full_dst_register *dst,
4654 const struct tgsi_full_src_register *src0,
4655 const struct tgsi_full_src_register *src1)
4656 {
4657 struct tgsi_full_src_register immediate;
4658 VGPU10OpcodeToken0 opcode0;
4659 boolean swapSrc = FALSE;
4660
4661 /* Sanity checks for svga vs. gallium enums */
4662 STATIC_ASSERT(SVGA3D_CMP_LESS == (PIPE_FUNC_LESS + 1));
4663 STATIC_ASSERT(SVGA3D_CMP_GREATEREQUAL == (PIPE_FUNC_GEQUAL + 1));
4664
4665 opcode0.value = 0;
4666
4667 switch (func) {
4668 case SVGA3D_CMP_NEVER:
4669 immediate = make_immediate_reg_int(emit, 0);
4670 /* MOV dst, {0} */
4671 begin_emit_instruction(emit);
4672 emit_dword(emit, VGPU10_OPCODE_MOV);
4673 emit_dst_register(emit, dst);
4674 emit_src_register(emit, &immediate);
4675 end_emit_instruction(emit);
4676 return;
4677 case SVGA3D_CMP_ALWAYS:
4678 immediate = make_immediate_reg_int(emit, -1);
4679 /* MOV dst, {-1} */
4680 begin_emit_instruction(emit);
4681 emit_dword(emit, VGPU10_OPCODE_MOV);
4682 emit_dst_register(emit, dst);
4683 emit_src_register(emit, &immediate);
4684 end_emit_instruction(emit);
4685 return;
4686 case SVGA3D_CMP_LESS:
4687 opcode0.opcodeType = VGPU10_OPCODE_LT;
4688 break;
4689 case SVGA3D_CMP_EQUAL:
4690 opcode0.opcodeType = VGPU10_OPCODE_EQ;
4691 break;
4692 case SVGA3D_CMP_LESSEQUAL:
4693 opcode0.opcodeType = VGPU10_OPCODE_GE;
4694 swapSrc = TRUE;
4695 break;
4696 case SVGA3D_CMP_GREATER:
4697 opcode0.opcodeType = VGPU10_OPCODE_LT;
4698 swapSrc = TRUE;
4699 break;
4700 case SVGA3D_CMP_NOTEQUAL:
4701 opcode0.opcodeType = VGPU10_OPCODE_NE;
4702 break;
4703 case SVGA3D_CMP_GREATEREQUAL:
4704 opcode0.opcodeType = VGPU10_OPCODE_GE;
4705 break;
4706 default:
4707 assert(!"Unexpected comparison mode");
4708 opcode0.opcodeType = VGPU10_OPCODE_EQ;
4709 }
4710
4711 begin_emit_instruction(emit);
4712 emit_dword(emit, opcode0.value);
4713 emit_dst_register(emit, dst);
4714 if (swapSrc) {
4715 emit_src_register(emit, src1);
4716 emit_src_register(emit, src0);
4717 }
4718 else {
4719 emit_src_register(emit, src0);
4720 emit_src_register(emit, src1);
4721 }
4722 end_emit_instruction(emit);
4723 }
4724
4725
4726 /**
4727 * Get texel/address offsets for a texture instruction.
4728 */
4729 static void
4730 get_texel_offsets(const struct svga_shader_emitter_v10 *emit,
4731 const struct tgsi_full_instruction *inst, int offsets[3])
4732 {
4733 if (inst->Texture.NumOffsets == 1) {
4734 /* According to OpenGL Shader Language spec the offsets are only
4735 * fetched from a previously-declared immediate/literal.
4736 */
4737 const struct tgsi_texture_offset *off = inst->TexOffsets;
4738 const unsigned index = off[0].Index;
4739 const unsigned swizzleX = off[0].SwizzleX;
4740 const unsigned swizzleY = off[0].SwizzleY;
4741 const unsigned swizzleZ = off[0].SwizzleZ;
4742 const union tgsi_immediate_data *imm = emit->immediates[index];
4743
4744 assert(inst->TexOffsets[0].File == TGSI_FILE_IMMEDIATE);
4745
4746 offsets[0] = imm[swizzleX].Int;
4747 offsets[1] = imm[swizzleY].Int;
4748 offsets[2] = imm[swizzleZ].Int;
4749 }
4750 else {
4751 offsets[0] = offsets[1] = offsets[2] = 0;
4752 }
4753 }
4754
4755
4756 /**
4757 * Set up the coordinate register for texture sampling.
4758 * When we're sampling from a RECT texture we have to scale the
4759 * unnormalized coordinate to a normalized coordinate.
4760 * We do that by multiplying the coordinate by an "extra" constant.
4761 * An alternative would be to use the RESINFO instruction to query the
4762 * texture's size.
4763 */
4764 static struct tgsi_full_src_register
4765 setup_texcoord(struct svga_shader_emitter_v10 *emit,
4766 unsigned unit,
4767 const struct tgsi_full_src_register *coord)
4768 {
4769 if (emit->key.tex[unit].unnormalized) {
4770 unsigned scale_index = emit->texcoord_scale_index[unit];
4771 unsigned tmp = get_temp_index(emit);
4772 struct tgsi_full_src_register tmp_src = make_src_temp_reg(tmp);
4773 struct tgsi_full_dst_register tmp_dst = make_dst_temp_reg(tmp);
4774 struct tgsi_full_src_register scale_src = make_src_const_reg(scale_index);
4775
4776 if (emit->key.tex[unit].texel_bias) {
4777 /* to fix texture coordinate rounding issue, 0.0001 offset is
4778 * been added. This fixes piglit test fbo-blit-scaled-linear. */
4779 struct tgsi_full_src_register offset =
4780 make_immediate_reg_float(emit, 0.0001f);
4781
4782 /* ADD tmp, coord, offset */
4783 emit_instruction_op2(emit, VGPU10_OPCODE_ADD, &tmp_dst,
4784 coord, &offset, FALSE);
4785 /* MUL tmp, tmp, scale */
4786 emit_instruction_op2(emit, VGPU10_OPCODE_MUL, &tmp_dst,
4787 &tmp_src, &scale_src, FALSE);
4788 }
4789 else {
4790 /* MUL tmp, coord, const[] */
4791 emit_instruction_op2(emit, VGPU10_OPCODE_MUL, &tmp_dst,
4792 coord, &scale_src, FALSE);
4793 }
4794 return tmp_src;
4795 }
4796 else {
4797 /* use texcoord as-is */
4798 return *coord;
4799 }
4800 }
4801
4802
4803 /**
4804 * For SAMPLE_C instructions, emit the extra src register which indicates
4805 * the reference/comparision value.
4806 */
4807 static void
4808 emit_tex_compare_refcoord(struct svga_shader_emitter_v10 *emit,
4809 enum tgsi_texture_type target,
4810 const struct tgsi_full_src_register *coord)
4811 {
4812 struct tgsi_full_src_register coord_src_ref;
4813 unsigned component;
4814
4815 assert(tgsi_is_shadow_target(target));
4816
4817 assert(target != TGSI_TEXTURE_SHADOWCUBE_ARRAY); /* XXX not implemented */
4818 if (target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
4819 target == TGSI_TEXTURE_SHADOWCUBE)
4820 component = TGSI_SWIZZLE_W;
4821 else
4822 component = TGSI_SWIZZLE_Z;
4823
4824 coord_src_ref = scalar_src(coord, component);
4825
4826 emit_src_register(emit, &coord_src_ref);
4827 }
4828
4829
4830 /**
4831 * Info for implementing texture swizzles.
4832 * The begin_tex_swizzle(), get_tex_swizzle_dst() and end_tex_swizzle()
4833 * functions use this to encapsulate the extra steps needed to perform
4834 * a texture swizzle, or shadow/depth comparisons.
4835 * The shadow/depth comparison is only done here if for the cases where
4836 * there's no VGPU10 opcode (like texture bias lookup w/ shadow compare).
4837 */
4838 struct tex_swizzle_info
4839 {
4840 boolean swizzled;
4841 boolean shadow_compare;
4842 unsigned unit;
4843 enum tgsi_texture_type texture_target; /**< TGSI_TEXTURE_x */
4844 struct tgsi_full_src_register tmp_src;
4845 struct tgsi_full_dst_register tmp_dst;
4846 const struct tgsi_full_dst_register *inst_dst;
4847 const struct tgsi_full_src_register *coord_src;
4848 };
4849
4850
4851 /**
4852 * Do setup for handling texture swizzles or shadow compares.
4853 * \param unit the texture unit
4854 * \param inst the TGSI texture instruction
4855 * \param shadow_compare do shadow/depth comparison?
4856 * \param swz returns the swizzle info
4857 */
4858 static void
4859 begin_tex_swizzle(struct svga_shader_emitter_v10 *emit,
4860 unsigned unit,
4861 const struct tgsi_full_instruction *inst,
4862 boolean shadow_compare,
4863 struct tex_swizzle_info *swz)
4864 {
4865 swz->swizzled = (emit->key.tex[unit].swizzle_r != TGSI_SWIZZLE_X ||
4866 emit->key.tex[unit].swizzle_g != TGSI_SWIZZLE_Y ||
4867 emit->key.tex[unit].swizzle_b != TGSI_SWIZZLE_Z ||
4868 emit->key.tex[unit].swizzle_a != TGSI_SWIZZLE_W);
4869
4870 swz->shadow_compare = shadow_compare;
4871 swz->texture_target = inst->Texture.Texture;
4872
4873 if (swz->swizzled || shadow_compare) {
4874 /* Allocate temp register for the result of the SAMPLE instruction
4875 * and the source of the MOV/compare/swizzle instructions.
4876 */
4877 unsigned tmp = get_temp_index(emit);
4878 swz->tmp_src = make_src_temp_reg(tmp);
4879 swz->tmp_dst = make_dst_temp_reg(tmp);
4880
4881 swz->unit = unit;
4882 }
4883 swz->inst_dst = &inst->Dst[0];
4884 swz->coord_src = &inst->Src[0];
4885 }
4886
4887
4888 /**
4889 * Returns the register to put the SAMPLE instruction results into.
4890 * This will either be the original instruction dst reg (if no swizzle
4891 * and no shadow comparison) or a temporary reg if there is a swizzle.
4892 */
4893 static const struct tgsi_full_dst_register *
4894 get_tex_swizzle_dst(const struct tex_swizzle_info *swz)
4895 {
4896 return (swz->swizzled || swz->shadow_compare)
4897 ? &swz->tmp_dst : swz->inst_dst;
4898 }
4899
4900
4901 /**
4902 * This emits the MOV instruction that actually implements a texture swizzle
4903 * and/or shadow comparison.
4904 */
4905 static void
4906 end_tex_swizzle(struct svga_shader_emitter_v10 *emit,
4907 const struct tex_swizzle_info *swz)
4908 {
4909 if (swz->shadow_compare) {
4910 /* Emit extra instructions to compare the fetched texel value against
4911 * a texture coordinate component. The result of the comparison
4912 * is 0.0 or 1.0.
4913 */
4914 struct tgsi_full_src_register coord_src;
4915 struct tgsi_full_src_register texel_src =
4916 scalar_src(&swz->tmp_src, TGSI_SWIZZLE_X);
4917 struct tgsi_full_src_register one =
4918 make_immediate_reg_float(emit, 1.0f);
4919 /* convert gallium comparison func to SVGA comparison func */
4920 SVGA3dCmpFunc compare_func = emit->key.tex[swz->unit].compare_func + 1;
4921
4922 assert(emit->unit == PIPE_SHADER_FRAGMENT);
4923
4924 switch (swz->texture_target) {
4925 case TGSI_TEXTURE_SHADOW2D:
4926 case TGSI_TEXTURE_SHADOWRECT:
4927 case TGSI_TEXTURE_SHADOW1D_ARRAY:
4928 coord_src = scalar_src(swz->coord_src, TGSI_SWIZZLE_Z);
4929 break;
4930 case TGSI_TEXTURE_SHADOW1D:
4931 coord_src = scalar_src(swz->coord_src, TGSI_SWIZZLE_Y);
4932 break;
4933 case TGSI_TEXTURE_SHADOWCUBE:
4934 case TGSI_TEXTURE_SHADOW2D_ARRAY:
4935 coord_src = scalar_src(swz->coord_src, TGSI_SWIZZLE_W);
4936 break;
4937 default:
4938 assert(!"Unexpected texture target in end_tex_swizzle()");
4939 coord_src = scalar_src(swz->coord_src, TGSI_SWIZZLE_Z);
4940 }
4941
4942 /* COMPARE tmp, coord, texel */
4943 /* XXX it would seem that the texel and coord arguments should
4944 * be transposed here, but piglit tests indicate otherwise.
4945 */
4946 emit_comparison(emit, compare_func,
4947 &swz->tmp_dst, &texel_src, &coord_src);
4948
4949 /* AND dest, tmp, {1.0} */
4950 begin_emit_instruction(emit);
4951 emit_opcode(emit, VGPU10_OPCODE_AND, FALSE);
4952 if (swz->swizzled) {
4953 emit_dst_register(emit, &swz->tmp_dst);
4954 }
4955 else {
4956 emit_dst_register(emit, swz->inst_dst);
4957 }
4958 emit_src_register(emit, &swz->tmp_src);
4959 emit_src_register(emit, &one);
4960 end_emit_instruction(emit);
4961 }
4962
4963 if (swz->swizzled) {
4964 unsigned swz_r = emit->key.tex[swz->unit].swizzle_r;
4965 unsigned swz_g = emit->key.tex[swz->unit].swizzle_g;
4966 unsigned swz_b = emit->key.tex[swz->unit].swizzle_b;
4967 unsigned swz_a = emit->key.tex[swz->unit].swizzle_a;
4968 unsigned writemask_0 = 0, writemask_1 = 0;
4969 boolean int_tex = is_integer_type(emit->sampler_return_type[swz->unit]);
4970
4971 /* Swizzle w/out zero/one terms */
4972 struct tgsi_full_src_register src_swizzled =
4973 swizzle_src(&swz->tmp_src,
4974 swz_r < PIPE_SWIZZLE_0 ? swz_r : PIPE_SWIZZLE_X,
4975 swz_g < PIPE_SWIZZLE_0 ? swz_g : PIPE_SWIZZLE_Y,
4976 swz_b < PIPE_SWIZZLE_0 ? swz_b : PIPE_SWIZZLE_Z,
4977 swz_a < PIPE_SWIZZLE_0 ? swz_a : PIPE_SWIZZLE_W);
4978
4979 /* MOV dst, color(tmp).<swizzle> */
4980 emit_instruction_op1(emit, VGPU10_OPCODE_MOV,
4981 swz->inst_dst, &src_swizzled, FALSE);
4982
4983 /* handle swizzle zero terms */
4984 writemask_0 = (((swz_r == PIPE_SWIZZLE_0) << 0) |
4985 ((swz_g == PIPE_SWIZZLE_0) << 1) |
4986 ((swz_b == PIPE_SWIZZLE_0) << 2) |
4987 ((swz_a == PIPE_SWIZZLE_0) << 3));
4988 writemask_0 &= swz->inst_dst->Register.WriteMask;
4989
4990 if (writemask_0) {
4991 struct tgsi_full_src_register zero = int_tex ?
4992 make_immediate_reg_int(emit, 0) :
4993 make_immediate_reg_float(emit, 0.0f);
4994 struct tgsi_full_dst_register dst =
4995 writemask_dst(swz->inst_dst, writemask_0);
4996
4997 /* MOV dst.writemask_0, {0,0,0,0} */
4998 emit_instruction_op1(emit, VGPU10_OPCODE_MOV,
4999 &dst, &zero, FALSE);
5000 }
5001
5002 /* handle swizzle one terms */
5003 writemask_1 = (((swz_r == PIPE_SWIZZLE_1) << 0) |
5004 ((swz_g == PIPE_SWIZZLE_1) << 1) |
5005 ((swz_b == PIPE_SWIZZLE_1) << 2) |
5006 ((swz_a == PIPE_SWIZZLE_1) << 3));
5007 writemask_1 &= swz->inst_dst->Register.WriteMask;
5008
5009 if (writemask_1) {
5010 struct tgsi_full_src_register one = int_tex ?
5011 make_immediate_reg_int(emit, 1) :
5012 make_immediate_reg_float(emit, 1.0f);
5013 struct tgsi_full_dst_register dst =
5014 writemask_dst(swz->inst_dst, writemask_1);
5015
5016 /* MOV dst.writemask_1, {1,1,1,1} */
5017 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &dst, &one, FALSE);
5018 }
5019 }
5020 }
5021
5022
5023 /**
5024 * Emit code for TGSI_OPCODE_SAMPLE instruction.
5025 */
5026 static boolean
5027 emit_sample(struct svga_shader_emitter_v10 *emit,
5028 const struct tgsi_full_instruction *inst)
5029 {
5030 const unsigned resource_unit = inst->Src[1].Register.Index;
5031 const unsigned sampler_unit = inst->Src[2].Register.Index;
5032 struct tgsi_full_src_register coord;
5033 int offsets[3];
5034 struct tex_swizzle_info swz_info;
5035
5036 begin_tex_swizzle(emit, sampler_unit, inst, FALSE, &swz_info);
5037
5038 get_texel_offsets(emit, inst, offsets);
5039
5040 coord = setup_texcoord(emit, resource_unit, &inst->Src[0]);
5041
5042 /* SAMPLE dst, coord(s0), resource, sampler */
5043 begin_emit_instruction(emit);
5044
5045 /* NOTE: for non-fragment shaders, we should use VGPU10_OPCODE_SAMPLE_L
5046 * with LOD=0. But our virtual GPU accepts this as-is.
5047 */
5048 emit_sample_opcode(emit, VGPU10_OPCODE_SAMPLE,
5049 inst->Instruction.Saturate, offsets);
5050 emit_dst_register(emit, get_tex_swizzle_dst(&swz_info));
5051 emit_src_register(emit, &coord);
5052 emit_resource_register(emit, resource_unit);
5053 emit_sampler_register(emit, sampler_unit);
5054 end_emit_instruction(emit);
5055
5056 end_tex_swizzle(emit, &swz_info);
5057
5058 free_temp_indexes(emit);
5059
5060 return TRUE;
5061 }
5062
5063
5064 /**
5065 * Check if a texture instruction is valid.
5066 * An example of an invalid texture instruction is doing shadow comparison
5067 * with an integer-valued texture.
5068 * If we detect an invalid texture instruction, we replace it with:
5069 * MOV dst, {1,1,1,1};
5070 * \return TRUE if valid, FALSE if invalid.
5071 */
5072 static boolean
5073 is_valid_tex_instruction(struct svga_shader_emitter_v10 *emit,
5074 const struct tgsi_full_instruction *inst)
5075 {
5076 const unsigned unit = inst->Src[1].Register.Index;
5077 const unsigned target = inst->Texture.Texture;
5078 boolean valid = TRUE;
5079
5080 if (tgsi_is_shadow_target(target) &&
5081 is_integer_type(emit->sampler_return_type[unit])) {
5082 debug_printf("Invalid SAMPLE_C with an integer texture!\n");
5083 valid = FALSE;
5084 }
5085 /* XXX might check for other conditions in the future here */
5086
5087 if (!valid) {
5088 /* emit a MOV dst, {1,1,1,1} instruction. */
5089 struct tgsi_full_src_register one = make_immediate_reg_float(emit, 1.0f);
5090 begin_emit_instruction(emit);
5091 emit_opcode(emit, VGPU10_OPCODE_MOV, FALSE);
5092 emit_dst_register(emit, &inst->Dst[0]);
5093 emit_src_register(emit, &one);
5094 end_emit_instruction(emit);
5095 }
5096
5097 return valid;
5098 }
5099
5100
5101 /**
5102 * Emit code for TGSI_OPCODE_TEX (simple texture lookup)
5103 */
5104 static boolean
5105 emit_tex(struct svga_shader_emitter_v10 *emit,
5106 const struct tgsi_full_instruction *inst)
5107 {
5108 const uint unit = inst->Src[1].Register.Index;
5109 unsigned target = inst->Texture.Texture;
5110 unsigned opcode;
5111 struct tgsi_full_src_register coord;
5112 int offsets[3];
5113 struct tex_swizzle_info swz_info;
5114
5115 /* check that the sampler returns a float */
5116 if (!is_valid_tex_instruction(emit, inst))
5117 return TRUE;
5118
5119 begin_tex_swizzle(emit, unit, inst, FALSE, &swz_info);
5120
5121 get_texel_offsets(emit, inst, offsets);
5122
5123 coord = setup_texcoord(emit, unit, &inst->Src[0]);
5124
5125 /* SAMPLE dst, coord(s0), resource, sampler */
5126 begin_emit_instruction(emit);
5127
5128 if (tgsi_is_shadow_target(target))
5129 opcode = VGPU10_OPCODE_SAMPLE_C;
5130 else
5131 opcode = VGPU10_OPCODE_SAMPLE;
5132
5133 emit_sample_opcode(emit, opcode, inst->Instruction.Saturate, offsets);
5134 emit_dst_register(emit, get_tex_swizzle_dst(&swz_info));
5135 emit_src_register(emit, &coord);
5136 emit_resource_register(emit, unit);
5137 emit_sampler_register(emit, unit);
5138 if (opcode == VGPU10_OPCODE_SAMPLE_C) {
5139 emit_tex_compare_refcoord(emit, target, &coord);
5140 }
5141 end_emit_instruction(emit);
5142
5143 end_tex_swizzle(emit, &swz_info);
5144
5145 free_temp_indexes(emit);
5146
5147 return TRUE;
5148 }
5149
5150
5151 /**
5152 * Emit code for TGSI_OPCODE_TXP (projective texture)
5153 */
5154 static boolean
5155 emit_txp(struct svga_shader_emitter_v10 *emit,
5156 const struct tgsi_full_instruction *inst)
5157 {
5158 const uint unit = inst->Src[1].Register.Index;
5159 unsigned target = inst->Texture.Texture;
5160 unsigned opcode;
5161 int offsets[3];
5162 unsigned tmp = get_temp_index(emit);
5163 struct tgsi_full_src_register tmp_src = make_src_temp_reg(tmp);
5164 struct tgsi_full_dst_register tmp_dst = make_dst_temp_reg(tmp);
5165 struct tgsi_full_src_register src0_wwww =
5166 scalar_src(&inst->Src[0], TGSI_SWIZZLE_W);
5167 struct tgsi_full_src_register coord;
5168 struct tex_swizzle_info swz_info;
5169
5170 /* check that the sampler returns a float */
5171 if (!is_valid_tex_instruction(emit, inst))
5172 return TRUE;
5173
5174 begin_tex_swizzle(emit, unit, inst, FALSE, &swz_info);
5175
5176 get_texel_offsets(emit, inst, offsets);
5177
5178 coord = setup_texcoord(emit, unit, &inst->Src[0]);
5179
5180 /* DIV tmp, coord, coord.wwww */
5181 emit_instruction_op2(emit, VGPU10_OPCODE_DIV, &tmp_dst,
5182 &coord, &src0_wwww, FALSE);
5183
5184 /* SAMPLE dst, coord(tmp), resource, sampler */
5185 begin_emit_instruction(emit);
5186
5187 if (tgsi_is_shadow_target(target))
5188 /* NOTE: for non-fragment shaders, we should use
5189 * VGPU10_OPCODE_SAMPLE_C_LZ, but our virtual GPU accepts this as-is.
5190 */
5191 opcode = VGPU10_OPCODE_SAMPLE_C;
5192 else
5193 opcode = VGPU10_OPCODE_SAMPLE;
5194
5195 emit_sample_opcode(emit, opcode, inst->Instruction.Saturate, offsets);
5196 emit_dst_register(emit, get_tex_swizzle_dst(&swz_info));
5197 emit_src_register(emit, &tmp_src); /* projected coord */
5198 emit_resource_register(emit, unit);
5199 emit_sampler_register(emit, unit);
5200 if (opcode == VGPU10_OPCODE_SAMPLE_C) {
5201 emit_tex_compare_refcoord(emit, target, &tmp_src);
5202 }
5203 end_emit_instruction(emit);
5204
5205 end_tex_swizzle(emit, &swz_info);
5206
5207 free_temp_indexes(emit);
5208
5209 return TRUE;
5210 }
5211
5212
5213 /**
5214 * Emit code for TGSI_OPCODE_TXD (explicit derivatives)
5215 */
5216 static boolean
5217 emit_txd(struct svga_shader_emitter_v10 *emit,
5218 const struct tgsi_full_instruction *inst)
5219 {
5220 const uint unit = inst->Src[3].Register.Index;
5221 unsigned target = inst->Texture.Texture;
5222 int offsets[3];
5223 struct tgsi_full_src_register coord;
5224 struct tex_swizzle_info swz_info;
5225
5226 begin_tex_swizzle(emit, unit, inst, tgsi_is_shadow_target(target),
5227 &swz_info);
5228
5229 get_texel_offsets(emit, inst, offsets);
5230
5231 coord = setup_texcoord(emit, unit, &inst->Src[0]);
5232
5233 /* SAMPLE_D dst, coord(s0), resource, sampler, Xderiv(s1), Yderiv(s2) */
5234 begin_emit_instruction(emit);
5235 emit_sample_opcode(emit, VGPU10_OPCODE_SAMPLE_D,
5236 inst->Instruction.Saturate, offsets);
5237 emit_dst_register(emit, get_tex_swizzle_dst(&swz_info));
5238 emit_src_register(emit, &coord);
5239 emit_resource_register(emit, unit);
5240 emit_sampler_register(emit, unit);
5241 emit_src_register(emit, &inst->Src[1]); /* Xderiv */
5242 emit_src_register(emit, &inst->Src[2]); /* Yderiv */
5243 end_emit_instruction(emit);
5244
5245 end_tex_swizzle(emit, &swz_info);
5246
5247 free_temp_indexes(emit);
5248
5249 return TRUE;
5250 }
5251
5252
5253 /**
5254 * Emit code for TGSI_OPCODE_TXF (texel fetch)
5255 */
5256 static boolean
5257 emit_txf(struct svga_shader_emitter_v10 *emit,
5258 const struct tgsi_full_instruction *inst)
5259 {
5260 const uint unit = inst->Src[1].Register.Index;
5261 const boolean msaa = tgsi_is_msaa_target(inst->Texture.Texture);
5262 int offsets[3];
5263 struct tex_swizzle_info swz_info;
5264
5265 begin_tex_swizzle(emit, unit, inst, FALSE, &swz_info);
5266
5267 get_texel_offsets(emit, inst, offsets);
5268
5269 if (msaa) {
5270 /* Fetch one sample from an MSAA texture */
5271 struct tgsi_full_src_register sampleIndex =
5272 scalar_src(&inst->Src[0], TGSI_SWIZZLE_W);
5273 /* LD_MS dst, coord(s0), resource, sampleIndex */
5274 begin_emit_instruction(emit);
5275 emit_sample_opcode(emit, VGPU10_OPCODE_LD_MS,
5276 inst->Instruction.Saturate, offsets);
5277 emit_dst_register(emit, get_tex_swizzle_dst(&swz_info));
5278 emit_src_register(emit, &inst->Src[0]);
5279 emit_resource_register(emit, unit);
5280 emit_src_register(emit, &sampleIndex);
5281 end_emit_instruction(emit);
5282 }
5283 else {
5284 /* Fetch one texel specified by integer coordinate */
5285 /* LD dst, coord(s0), resource */
5286 begin_emit_instruction(emit);
5287 emit_sample_opcode(emit, VGPU10_OPCODE_LD,
5288 inst->Instruction.Saturate, offsets);
5289 emit_dst_register(emit, get_tex_swizzle_dst(&swz_info));
5290 emit_src_register(emit, &inst->Src[0]);
5291 emit_resource_register(emit, unit);
5292 end_emit_instruction(emit);
5293 }
5294
5295 end_tex_swizzle(emit, &swz_info);
5296
5297 free_temp_indexes(emit);
5298
5299 return TRUE;
5300 }
5301
5302
5303 /**
5304 * Emit code for TGSI_OPCODE_TXL (explicit LOD) or TGSI_OPCODE_TXB (LOD bias)
5305 * or TGSI_OPCODE_TXB2 (for cube shadow maps).
5306 */
5307 static boolean
5308 emit_txl_txb(struct svga_shader_emitter_v10 *emit,
5309 const struct tgsi_full_instruction *inst)
5310 {
5311 unsigned target = inst->Texture.Texture;
5312 unsigned opcode, unit;
5313 int offsets[3];
5314 struct tgsi_full_src_register coord, lod_bias;
5315 struct tex_swizzle_info swz_info;
5316
5317 assert(inst->Instruction.Opcode == TGSI_OPCODE_TXL ||
5318 inst->Instruction.Opcode == TGSI_OPCODE_TXB ||
5319 inst->Instruction.Opcode == TGSI_OPCODE_TXB2);
5320
5321 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB2) {
5322 lod_bias = scalar_src(&inst->Src[1], TGSI_SWIZZLE_X);
5323 unit = inst->Src[2].Register.Index;
5324 }
5325 else {
5326 lod_bias = scalar_src(&inst->Src[0], TGSI_SWIZZLE_W);
5327 unit = inst->Src[1].Register.Index;
5328 }
5329
5330 begin_tex_swizzle(emit, unit, inst, tgsi_is_shadow_target(target),
5331 &swz_info);
5332
5333 get_texel_offsets(emit, inst, offsets);
5334
5335 coord = setup_texcoord(emit, unit, &inst->Src[0]);
5336
5337 /* SAMPLE_L/B dst, coord(s0), resource, sampler, lod(s3) */
5338 begin_emit_instruction(emit);
5339 if (inst->Instruction.Opcode == TGSI_OPCODE_TXL) {
5340 opcode = VGPU10_OPCODE_SAMPLE_L;
5341 }
5342 else {
5343 opcode = VGPU10_OPCODE_SAMPLE_B;
5344 }
5345 emit_sample_opcode(emit, opcode, inst->Instruction.Saturate, offsets);
5346 emit_dst_register(emit, get_tex_swizzle_dst(&swz_info));
5347 emit_src_register(emit, &coord);
5348 emit_resource_register(emit, unit);
5349 emit_sampler_register(emit, unit);
5350 emit_src_register(emit, &lod_bias);
5351 end_emit_instruction(emit);
5352
5353 end_tex_swizzle(emit, &swz_info);
5354
5355 free_temp_indexes(emit);
5356
5357 return TRUE;
5358 }
5359
5360
5361 /**
5362 * Emit code for TGSI_OPCODE_TXQ (texture query) instruction.
5363 */
5364 static boolean
5365 emit_txq(struct svga_shader_emitter_v10 *emit,
5366 const struct tgsi_full_instruction *inst)
5367 {
5368 const uint unit = inst->Src[1].Register.Index;
5369
5370 if (emit->sampler_target[unit] == TGSI_TEXTURE_BUFFER) {
5371 /* RESINFO does not support querying texture buffers, so we instead
5372 * store texture buffer sizes in shader constants, then copy them to
5373 * implement TXQ instead of emitting RESINFO.
5374 * MOV dst, const[texture_buffer_size_index[unit]]
5375 */
5376 struct tgsi_full_src_register size_src =
5377 make_src_const_reg(emit->texture_buffer_size_index[unit]);
5378 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &inst->Dst[0], &size_src,
5379 FALSE);
5380 } else {
5381 /* RESINFO dst, srcMipLevel, resource */
5382 begin_emit_instruction(emit);
5383 emit_opcode_resinfo(emit, VGPU10_RESINFO_RETURN_UINT);
5384 emit_dst_register(emit, &inst->Dst[0]);
5385 emit_src_register(emit, &inst->Src[0]);
5386 emit_resource_register(emit, unit);
5387 end_emit_instruction(emit);
5388 }
5389
5390 free_temp_indexes(emit);
5391
5392 return TRUE;
5393 }
5394
5395
5396 /**
5397 * Emit a simple instruction (like ADD, MUL, MIN, etc).
5398 */
5399 static boolean
5400 emit_simple(struct svga_shader_emitter_v10 *emit,
5401 const struct tgsi_full_instruction *inst)
5402 {
5403 const unsigned opcode = inst->Instruction.Opcode;
5404 const struct tgsi_opcode_info *op = tgsi_get_opcode_info(opcode);
5405 unsigned i;
5406
5407 begin_emit_instruction(emit);
5408 emit_opcode(emit, translate_opcode(inst->Instruction.Opcode),
5409 inst->Instruction.Saturate);
5410 for (i = 0; i < op->num_dst; i++) {
5411 emit_dst_register(emit, &inst->Dst[i]);
5412 }
5413 for (i = 0; i < op->num_src; i++) {
5414 emit_src_register(emit, &inst->Src[i]);
5415 }
5416 end_emit_instruction(emit);
5417
5418 return TRUE;
5419 }
5420
5421
5422 /**
5423 * We only special case the MOV instruction to try to detect constant
5424 * color writes in the fragment shader.
5425 */
5426 static boolean
5427 emit_mov(struct svga_shader_emitter_v10 *emit,
5428 const struct tgsi_full_instruction *inst)
5429 {
5430 const struct tgsi_full_src_register *src = &inst->Src[0];
5431 const struct tgsi_full_dst_register *dst = &inst->Dst[0];
5432
5433 if (emit->unit == PIPE_SHADER_FRAGMENT &&
5434 dst->Register.File == TGSI_FILE_OUTPUT &&
5435 dst->Register.Index == 0 &&
5436 src->Register.File == TGSI_FILE_CONSTANT &&
5437 !src->Register.Indirect) {
5438 emit->constant_color_output = TRUE;
5439 }
5440
5441 return emit_simple(emit, inst);
5442 }
5443
5444
5445 /**
5446 * Emit a simple VGPU10 instruction which writes to multiple dest registers,
5447 * where TGSI only uses one dest register.
5448 */
5449 static boolean
5450 emit_simple_1dst(struct svga_shader_emitter_v10 *emit,
5451 const struct tgsi_full_instruction *inst,
5452 unsigned dst_count,
5453 unsigned dst_index)
5454 {
5455 const unsigned opcode = inst->Instruction.Opcode;
5456 const struct tgsi_opcode_info *op = tgsi_get_opcode_info(opcode);
5457 unsigned i;
5458
5459 begin_emit_instruction(emit);
5460 emit_opcode(emit, translate_opcode(inst->Instruction.Opcode),
5461 inst->Instruction.Saturate);
5462
5463 for (i = 0; i < dst_count; i++) {
5464 if (i == dst_index) {
5465 emit_dst_register(emit, &inst->Dst[0]);
5466 } else {
5467 emit_null_dst_register(emit);
5468 }
5469 }
5470
5471 for (i = 0; i < op->num_src; i++) {
5472 emit_src_register(emit, &inst->Src[i]);
5473 }
5474 end_emit_instruction(emit);
5475
5476 return TRUE;
5477 }
5478
5479
5480 /**
5481 * Translate a single TGSI instruction to VGPU10.
5482 */
5483 static boolean
5484 emit_vgpu10_instruction(struct svga_shader_emitter_v10 *emit,
5485 unsigned inst_number,
5486 const struct tgsi_full_instruction *inst)
5487 {
5488 const unsigned opcode = inst->Instruction.Opcode;
5489
5490 switch (opcode) {
5491 case TGSI_OPCODE_ADD:
5492 case TGSI_OPCODE_AND:
5493 case TGSI_OPCODE_BGNLOOP:
5494 case TGSI_OPCODE_BRK:
5495 case TGSI_OPCODE_CEIL:
5496 case TGSI_OPCODE_CONT:
5497 case TGSI_OPCODE_DDX:
5498 case TGSI_OPCODE_DDY:
5499 case TGSI_OPCODE_DIV:
5500 case TGSI_OPCODE_DP2:
5501 case TGSI_OPCODE_DP3:
5502 case TGSI_OPCODE_DP4:
5503 case TGSI_OPCODE_ELSE:
5504 case TGSI_OPCODE_ENDIF:
5505 case TGSI_OPCODE_ENDLOOP:
5506 case TGSI_OPCODE_ENDSUB:
5507 case TGSI_OPCODE_F2I:
5508 case TGSI_OPCODE_F2U:
5509 case TGSI_OPCODE_FLR:
5510 case TGSI_OPCODE_FRC:
5511 case TGSI_OPCODE_FSEQ:
5512 case TGSI_OPCODE_FSGE:
5513 case TGSI_OPCODE_FSLT:
5514 case TGSI_OPCODE_FSNE:
5515 case TGSI_OPCODE_I2F:
5516 case TGSI_OPCODE_IMAX:
5517 case TGSI_OPCODE_IMIN:
5518 case TGSI_OPCODE_INEG:
5519 case TGSI_OPCODE_ISGE:
5520 case TGSI_OPCODE_ISHR:
5521 case TGSI_OPCODE_ISLT:
5522 case TGSI_OPCODE_MAD:
5523 case TGSI_OPCODE_MAX:
5524 case TGSI_OPCODE_MIN:
5525 case TGSI_OPCODE_MUL:
5526 case TGSI_OPCODE_NOP:
5527 case TGSI_OPCODE_NOT:
5528 case TGSI_OPCODE_OR:
5529 case TGSI_OPCODE_RET:
5530 case TGSI_OPCODE_UADD:
5531 case TGSI_OPCODE_USEQ:
5532 case TGSI_OPCODE_USGE:
5533 case TGSI_OPCODE_USLT:
5534 case TGSI_OPCODE_UMIN:
5535 case TGSI_OPCODE_UMAD:
5536 case TGSI_OPCODE_UMAX:
5537 case TGSI_OPCODE_ROUND:
5538 case TGSI_OPCODE_SQRT:
5539 case TGSI_OPCODE_SHL:
5540 case TGSI_OPCODE_TRUNC:
5541 case TGSI_OPCODE_U2F:
5542 case TGSI_OPCODE_UCMP:
5543 case TGSI_OPCODE_USHR:
5544 case TGSI_OPCODE_USNE:
5545 case TGSI_OPCODE_XOR:
5546 /* simple instructions */
5547 return emit_simple(emit, inst);
5548
5549 case TGSI_OPCODE_MOV:
5550 return emit_mov(emit, inst);
5551 case TGSI_OPCODE_EMIT:
5552 return emit_vertex(emit, inst);
5553 case TGSI_OPCODE_ENDPRIM:
5554 return emit_endprim(emit, inst);
5555 case TGSI_OPCODE_IABS:
5556 return emit_iabs(emit, inst);
5557 case TGSI_OPCODE_ARL:
5558 /* fall-through */
5559 case TGSI_OPCODE_UARL:
5560 return emit_arl_uarl(emit, inst);
5561 case TGSI_OPCODE_BGNSUB:
5562 /* no-op */
5563 return TRUE;
5564 case TGSI_OPCODE_CAL:
5565 return emit_cal(emit, inst);
5566 case TGSI_OPCODE_CMP:
5567 return emit_cmp(emit, inst);
5568 case TGSI_OPCODE_COS:
5569 return emit_sincos(emit, inst);
5570 case TGSI_OPCODE_DST:
5571 return emit_dst(emit, inst);
5572 case TGSI_OPCODE_EX2:
5573 return emit_ex2(emit, inst);
5574 case TGSI_OPCODE_EXP:
5575 return emit_exp(emit, inst);
5576 case TGSI_OPCODE_IF:
5577 return emit_if(emit, inst);
5578 case TGSI_OPCODE_KILL:
5579 return emit_kill(emit, inst);
5580 case TGSI_OPCODE_KILL_IF:
5581 return emit_kill_if(emit, inst);
5582 case TGSI_OPCODE_LG2:
5583 return emit_lg2(emit, inst);
5584 case TGSI_OPCODE_LIT:
5585 return emit_lit(emit, inst);
5586 case TGSI_OPCODE_LOG:
5587 return emit_log(emit, inst);
5588 case TGSI_OPCODE_LRP:
5589 return emit_lrp(emit, inst);
5590 case TGSI_OPCODE_POW:
5591 return emit_pow(emit, inst);
5592 case TGSI_OPCODE_RCP:
5593 return emit_rcp(emit, inst);
5594 case TGSI_OPCODE_RSQ:
5595 return emit_rsq(emit, inst);
5596 case TGSI_OPCODE_SAMPLE:
5597 return emit_sample(emit, inst);
5598 case TGSI_OPCODE_SCS:
5599 return emit_scs(emit, inst);
5600 case TGSI_OPCODE_SEQ:
5601 return emit_seq(emit, inst);
5602 case TGSI_OPCODE_SGE:
5603 return emit_sge(emit, inst);
5604 case TGSI_OPCODE_SGT:
5605 return emit_sgt(emit, inst);
5606 case TGSI_OPCODE_SIN:
5607 return emit_sincos(emit, inst);
5608 case TGSI_OPCODE_SLE:
5609 return emit_sle(emit, inst);
5610 case TGSI_OPCODE_SLT:
5611 return emit_slt(emit, inst);
5612 case TGSI_OPCODE_SNE:
5613 return emit_sne(emit, inst);
5614 case TGSI_OPCODE_SSG:
5615 return emit_ssg(emit, inst);
5616 case TGSI_OPCODE_ISSG:
5617 return emit_issg(emit, inst);
5618 case TGSI_OPCODE_TEX:
5619 return emit_tex(emit, inst);
5620 case TGSI_OPCODE_TXP:
5621 return emit_txp(emit, inst);
5622 case TGSI_OPCODE_TXB:
5623 case TGSI_OPCODE_TXB2:
5624 case TGSI_OPCODE_TXL:
5625 return emit_txl_txb(emit, inst);
5626 case TGSI_OPCODE_TXD:
5627 return emit_txd(emit, inst);
5628 case TGSI_OPCODE_TXF:
5629 return emit_txf(emit, inst);
5630 case TGSI_OPCODE_TXQ:
5631 return emit_txq(emit, inst);
5632 case TGSI_OPCODE_UIF:
5633 return emit_if(emit, inst);
5634 case TGSI_OPCODE_UMUL_HI:
5635 case TGSI_OPCODE_IMUL_HI:
5636 case TGSI_OPCODE_UDIV:
5637 case TGSI_OPCODE_IDIV:
5638 /* These cases use only the FIRST of two destination registers */
5639 return emit_simple_1dst(emit, inst, 2, 0);
5640 case TGSI_OPCODE_UMUL:
5641 case TGSI_OPCODE_UMOD:
5642 case TGSI_OPCODE_MOD:
5643 /* These cases use only the SECOND of two destination registers */
5644 return emit_simple_1dst(emit, inst, 2, 1);
5645 case TGSI_OPCODE_END:
5646 if (!emit_post_helpers(emit))
5647 return FALSE;
5648 return emit_simple(emit, inst);
5649
5650 default:
5651 debug_printf("Unimplemented tgsi instruction %s\n",
5652 tgsi_get_opcode_name(opcode));
5653 return FALSE;
5654 }
5655
5656 return TRUE;
5657 }
5658
5659
5660 /**
5661 * Emit the extra instructions to adjust the vertex position.
5662 * There are two possible adjustments:
5663 * 1. Converting from Gallium to VGPU10 coordinate space by applying the
5664 * "prescale" and "pretranslate" values.
5665 * 2. Undoing the viewport transformation when we use the swtnl/draw path.
5666 * \param vs_pos_tmp_index which temporary register contains the vertex pos.
5667 */
5668 static void
5669 emit_vpos_instructions(struct svga_shader_emitter_v10 *emit,
5670 unsigned vs_pos_tmp_index)
5671 {
5672 struct tgsi_full_src_register tmp_pos_src;
5673 struct tgsi_full_dst_register pos_dst;
5674
5675 /* Don't bother to emit any extra vertex instructions if vertex position is
5676 * not written out
5677 */
5678 if (emit->vposition.out_index == INVALID_INDEX)
5679 return;
5680
5681 tmp_pos_src = make_src_temp_reg(vs_pos_tmp_index);
5682 pos_dst = make_dst_output_reg(emit->vposition.out_index);
5683
5684 /* If non-adjusted vertex position register index
5685 * is valid, copy the vertex position from the temporary
5686 * vertex position register before it is modified by the
5687 * prescale computation.
5688 */
5689 if (emit->vposition.so_index != INVALID_INDEX) {
5690 struct tgsi_full_dst_register pos_so_dst =
5691 make_dst_output_reg(emit->vposition.so_index);
5692
5693 /* MOV pos_so, tmp_pos */
5694 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &pos_so_dst,
5695 &tmp_pos_src, FALSE);
5696 }
5697
5698 if (emit->vposition.need_prescale) {
5699 /* This code adjusts the vertex position to match the VGPU10 convention.
5700 * If p is the position computed by the shader (usually by applying the
5701 * modelview and projection matrices), the new position q is computed by:
5702 *
5703 * q.x = p.w * trans.x + p.x * scale.x
5704 * q.y = p.w * trans.y + p.y * scale.y
5705 * q.z = p.w * trans.z + p.z * scale.z;
5706 * q.w = p.w * trans.w + p.w;
5707 */
5708 struct tgsi_full_src_register tmp_pos_src_w =
5709 scalar_src(&tmp_pos_src, TGSI_SWIZZLE_W);
5710 struct tgsi_full_dst_register tmp_pos_dst =
5711 make_dst_temp_reg(vs_pos_tmp_index);
5712 struct tgsi_full_dst_register tmp_pos_dst_xyz =
5713 writemask_dst(&tmp_pos_dst, TGSI_WRITEMASK_XYZ);
5714
5715 struct tgsi_full_src_register prescale_scale =
5716 make_src_const_reg(emit->vposition.prescale_scale_index);
5717 struct tgsi_full_src_register prescale_trans =
5718 make_src_const_reg(emit->vposition.prescale_trans_index);
5719
5720 /* MUL tmp_pos.xyz, tmp_pos, prescale.scale */
5721 emit_instruction_op2(emit, VGPU10_OPCODE_MUL, &tmp_pos_dst_xyz,
5722 &tmp_pos_src, &prescale_scale, FALSE);
5723
5724 /* MAD pos, tmp_pos.wwww, prescale.trans, tmp_pos */
5725 emit_instruction_op3(emit, VGPU10_OPCODE_MAD, &pos_dst, &tmp_pos_src_w,
5726 &prescale_trans, &tmp_pos_src, FALSE);
5727 }
5728 else if (emit->key.vs.undo_viewport) {
5729 /* This code computes the final vertex position from the temporary
5730 * vertex position by undoing the viewport transformation and the
5731 * divide-by-W operation (we convert window coords back to clip coords).
5732 * This is needed when we use the 'draw' module for fallbacks.
5733 * If p is the temp pos in window coords, then the NDC coord q is:
5734 * q.x = (p.x - vp.x_trans) / vp.x_scale * p.w
5735 * q.y = (p.y - vp.y_trans) / vp.y_scale * p.w
5736 * q.z = p.z * p.w
5737 * q.w = p.w
5738 * CONST[vs_viewport_index] contains:
5739 * { 1/vp.x_scale, 1/vp.y_scale, -vp.x_trans, -vp.y_trans }
5740 */
5741 struct tgsi_full_dst_register tmp_pos_dst =
5742 make_dst_temp_reg(vs_pos_tmp_index);
5743 struct tgsi_full_dst_register tmp_pos_dst_xy =
5744 writemask_dst(&tmp_pos_dst, TGSI_WRITEMASK_XY);
5745 struct tgsi_full_src_register tmp_pos_src_wwww =
5746 scalar_src(&tmp_pos_src, TGSI_SWIZZLE_W);
5747
5748 struct tgsi_full_dst_register pos_dst_xyz =
5749 writemask_dst(&pos_dst, TGSI_WRITEMASK_XYZ);
5750 struct tgsi_full_dst_register pos_dst_w =
5751 writemask_dst(&pos_dst, TGSI_WRITEMASK_W);
5752
5753 struct tgsi_full_src_register vp_xyzw =
5754 make_src_const_reg(emit->vs.viewport_index);
5755 struct tgsi_full_src_register vp_zwww =
5756 swizzle_src(&vp_xyzw, TGSI_SWIZZLE_Z, TGSI_SWIZZLE_W,
5757 TGSI_SWIZZLE_W, TGSI_SWIZZLE_W);
5758
5759 /* ADD tmp_pos.xy, tmp_pos.xy, viewport.zwww */
5760 emit_instruction_op2(emit, VGPU10_OPCODE_ADD, &tmp_pos_dst_xy,
5761 &tmp_pos_src, &vp_zwww, FALSE);
5762
5763 /* MUL tmp_pos.xy, tmp_pos.xyzw, viewport.xyzy */
5764 emit_instruction_op2(emit, VGPU10_OPCODE_MUL, &tmp_pos_dst_xy,
5765 &tmp_pos_src, &vp_xyzw, FALSE);
5766
5767 /* MUL pos.xyz, tmp_pos.xyz, tmp_pos.www */
5768 emit_instruction_op2(emit, VGPU10_OPCODE_MUL, &pos_dst_xyz,
5769 &tmp_pos_src, &tmp_pos_src_wwww, FALSE);
5770
5771 /* MOV pos.w, tmp_pos.w */
5772 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &pos_dst_w,
5773 &tmp_pos_src, FALSE);
5774 }
5775 else if (vs_pos_tmp_index != INVALID_INDEX) {
5776 /* This code is to handle the case where the temporary vertex
5777 * position register is created when the vertex shader has stream
5778 * output and prescale is disabled because rasterization is to be
5779 * discarded.
5780 */
5781 struct tgsi_full_dst_register pos_dst =
5782 make_dst_output_reg(emit->vposition.out_index);
5783
5784 /* MOV pos, tmp_pos */
5785 begin_emit_instruction(emit);
5786 emit_opcode(emit, VGPU10_OPCODE_MOV, FALSE);
5787 emit_dst_register(emit, &pos_dst);
5788 emit_src_register(emit, &tmp_pos_src);
5789 end_emit_instruction(emit);
5790 }
5791 }
5792
5793 static void
5794 emit_clipping_instructions(struct svga_shader_emitter_v10 *emit)
5795 {
5796 if (emit->clip_mode == CLIP_DISTANCE) {
5797 /* Copy from copy distance temporary to CLIPDIST & the shadow copy */
5798 emit_clip_distance_instructions(emit);
5799
5800 } else if (emit->clip_mode == CLIP_VERTEX) {
5801 /* Convert TGSI CLIPVERTEX to CLIPDIST */
5802 emit_clip_vertex_instructions(emit);
5803 }
5804
5805 /**
5806 * Emit vertex position and take care of legacy user planes only if
5807 * there is a valid vertex position register index.
5808 * This is to take care of the case
5809 * where the shader doesn't output vertex position. Then in
5810 * this case, don't bother to emit more vertex instructions.
5811 */
5812 if (emit->vposition.out_index == INVALID_INDEX)
5813 return;
5814
5815 /**
5816 * Emit per-vertex clipping instructions for legacy user defined clip planes.
5817 * NOTE: we must emit the clip distance instructions before the
5818 * emit_vpos_instructions() call since the later function will change
5819 * the TEMP[vs_pos_tmp_index] value.
5820 */
5821 if (emit->clip_mode == CLIP_LEGACY) {
5822 /* Emit CLIPDIST for legacy user defined clip planes */
5823 emit_clip_distance_from_vpos(emit, emit->vposition.tmp_index);
5824 }
5825 }
5826
5827
5828 /**
5829 * Emit extra per-vertex instructions. This includes clip-coordinate
5830 * space conversion and computing clip distances. This is called for
5831 * each GS emit-vertex instruction and at the end of VS translation.
5832 */
5833 static void
5834 emit_vertex_instructions(struct svga_shader_emitter_v10 *emit)
5835 {
5836 const unsigned vs_pos_tmp_index = emit->vposition.tmp_index;
5837
5838 /* Emit clipping instructions based on clipping mode */
5839 emit_clipping_instructions(emit);
5840
5841 /**
5842 * Reset the temporary vertex position register index
5843 * so that emit_dst_register() will use the real vertex position output
5844 */
5845 emit->vposition.tmp_index = INVALID_INDEX;
5846
5847 /* Emit vertex position instructions */
5848 emit_vpos_instructions(emit, vs_pos_tmp_index);
5849
5850 /* Restore original vposition.tmp_index value for the next GS vertex.
5851 * It doesn't matter for VS.
5852 */
5853 emit->vposition.tmp_index = vs_pos_tmp_index;
5854 }
5855
5856 /**
5857 * Translate the TGSI_OPCODE_EMIT GS instruction.
5858 */
5859 static boolean
5860 emit_vertex(struct svga_shader_emitter_v10 *emit,
5861 const struct tgsi_full_instruction *inst)
5862 {
5863 unsigned ret = TRUE;
5864
5865 assert(emit->unit == PIPE_SHADER_GEOMETRY);
5866
5867 emit_vertex_instructions(emit);
5868
5869 /* We can't use emit_simple() because the TGSI instruction has one
5870 * operand (vertex stream number) which we must ignore for VGPU10.
5871 */
5872 begin_emit_instruction(emit);
5873 emit_opcode(emit, VGPU10_OPCODE_EMIT, FALSE);
5874 end_emit_instruction(emit);
5875
5876 return ret;
5877 }
5878
5879
5880 /**
5881 * Emit the extra code to convert from VGPU10's boolean front-face
5882 * register to TGSI's signed front-face register.
5883 *
5884 * TODO: Make temporary front-face register a scalar.
5885 */
5886 static void
5887 emit_frontface_instructions(struct svga_shader_emitter_v10 *emit)
5888 {
5889 assert(emit->unit == PIPE_SHADER_FRAGMENT);
5890
5891 if (emit->fs.face_input_index != INVALID_INDEX) {
5892 /* convert vgpu10 boolean face register to gallium +/-1 value */
5893 struct tgsi_full_dst_register tmp_dst =
5894 make_dst_temp_reg(emit->fs.face_tmp_index);
5895 struct tgsi_full_src_register one =
5896 make_immediate_reg_float(emit, 1.0f);
5897 struct tgsi_full_src_register neg_one =
5898 make_immediate_reg_float(emit, -1.0f);
5899
5900 /* MOVC face_tmp, IS_FRONT_FACE.x, 1.0, -1.0 */
5901 begin_emit_instruction(emit);
5902 emit_opcode(emit, VGPU10_OPCODE_MOVC, FALSE);
5903 emit_dst_register(emit, &tmp_dst);
5904 emit_face_register(emit);
5905 emit_src_register(emit, &one);
5906 emit_src_register(emit, &neg_one);
5907 end_emit_instruction(emit);
5908 }
5909 }
5910
5911
5912 /**
5913 * Emit the extra code to convert from VGPU10's fragcoord.w value to 1/w.
5914 */
5915 static void
5916 emit_fragcoord_instructions(struct svga_shader_emitter_v10 *emit)
5917 {
5918 assert(emit->unit == PIPE_SHADER_FRAGMENT);
5919
5920 if (emit->fs.fragcoord_input_index != INVALID_INDEX) {
5921 struct tgsi_full_dst_register tmp_dst =
5922 make_dst_temp_reg(emit->fs.fragcoord_tmp_index);
5923 struct tgsi_full_dst_register tmp_dst_xyz =
5924 writemask_dst(&tmp_dst, TGSI_WRITEMASK_XYZ);
5925 struct tgsi_full_dst_register tmp_dst_w =
5926 writemask_dst(&tmp_dst, TGSI_WRITEMASK_W);
5927 struct tgsi_full_src_register one =
5928 make_immediate_reg_float(emit, 1.0f);
5929 struct tgsi_full_src_register fragcoord =
5930 make_src_reg(TGSI_FILE_INPUT, emit->fs.fragcoord_input_index);
5931
5932 /* save the input index */
5933 unsigned fragcoord_input_index = emit->fs.fragcoord_input_index;
5934 /* set to invalid to prevent substitution in emit_src_register() */
5935 emit->fs.fragcoord_input_index = INVALID_INDEX;
5936
5937 /* MOV fragcoord_tmp.xyz, fragcoord.xyz */
5938 begin_emit_instruction(emit);
5939 emit_opcode(emit, VGPU10_OPCODE_MOV, FALSE);
5940 emit_dst_register(emit, &tmp_dst_xyz);
5941 emit_src_register(emit, &fragcoord);
5942 end_emit_instruction(emit);
5943
5944 /* DIV fragcoord_tmp.w, 1.0, fragcoord.w */
5945 begin_emit_instruction(emit);
5946 emit_opcode(emit, VGPU10_OPCODE_DIV, FALSE);
5947 emit_dst_register(emit, &tmp_dst_w);
5948 emit_src_register(emit, &one);
5949 emit_src_register(emit, &fragcoord);
5950 end_emit_instruction(emit);
5951
5952 /* restore saved value */
5953 emit->fs.fragcoord_input_index = fragcoord_input_index;
5954 }
5955 }
5956
5957
5958 /**
5959 * Emit extra instructions to adjust VS inputs/attributes. This can
5960 * mean casting a vertex attribute from int to float or setting the
5961 * W component to 1, or both.
5962 */
5963 static void
5964 emit_vertex_attrib_instructions(struct svga_shader_emitter_v10 *emit)
5965 {
5966 const unsigned save_w_1_mask = emit->key.vs.adjust_attrib_w_1;
5967 const unsigned save_itof_mask = emit->key.vs.adjust_attrib_itof;
5968 const unsigned save_utof_mask = emit->key.vs.adjust_attrib_utof;
5969 const unsigned save_is_bgra_mask = emit->key.vs.attrib_is_bgra;
5970 const unsigned save_puint_to_snorm_mask = emit->key.vs.attrib_puint_to_snorm;
5971 const unsigned save_puint_to_uscaled_mask = emit->key.vs.attrib_puint_to_uscaled;
5972 const unsigned save_puint_to_sscaled_mask = emit->key.vs.attrib_puint_to_sscaled;
5973
5974 unsigned adjust_mask = (save_w_1_mask |
5975 save_itof_mask |
5976 save_utof_mask |
5977 save_is_bgra_mask |
5978 save_puint_to_snorm_mask |
5979 save_puint_to_uscaled_mask |
5980 save_puint_to_sscaled_mask);
5981
5982 assert(emit->unit == PIPE_SHADER_VERTEX);
5983
5984 if (adjust_mask) {
5985 struct tgsi_full_src_register one =
5986 make_immediate_reg_float(emit, 1.0f);
5987
5988 struct tgsi_full_src_register one_int =
5989 make_immediate_reg_int(emit, 1);
5990
5991 /* We need to turn off these bitmasks while emitting the
5992 * instructions below, then restore them afterward.
5993 */
5994 emit->key.vs.adjust_attrib_w_1 = 0;
5995 emit->key.vs.adjust_attrib_itof = 0;
5996 emit->key.vs.adjust_attrib_utof = 0;
5997 emit->key.vs.attrib_is_bgra = 0;
5998 emit->key.vs.attrib_puint_to_snorm = 0;
5999 emit->key.vs.attrib_puint_to_uscaled = 0;
6000 emit->key.vs.attrib_puint_to_sscaled = 0;
6001
6002 while (adjust_mask) {
6003 unsigned index = u_bit_scan(&adjust_mask);
6004
6005 /* skip the instruction if this vertex attribute is not being used */
6006 if (emit->info.input_usage_mask[index] == 0)
6007 continue;
6008
6009 unsigned tmp = emit->vs.adjusted_input[index];
6010 struct tgsi_full_src_register input_src =
6011 make_src_reg(TGSI_FILE_INPUT, index);
6012
6013 struct tgsi_full_dst_register tmp_dst = make_dst_temp_reg(tmp);
6014 struct tgsi_full_src_register tmp_src = make_src_temp_reg(tmp);
6015 struct tgsi_full_dst_register tmp_dst_w =
6016 writemask_dst(&tmp_dst, TGSI_WRITEMASK_W);
6017
6018 /* ITOF/UTOF/MOV tmp, input[index] */
6019 if (save_itof_mask & (1 << index)) {
6020 emit_instruction_op1(emit, VGPU10_OPCODE_ITOF,
6021 &tmp_dst, &input_src, FALSE);
6022 }
6023 else if (save_utof_mask & (1 << index)) {
6024 emit_instruction_op1(emit, VGPU10_OPCODE_UTOF,
6025 &tmp_dst, &input_src, FALSE);
6026 }
6027 else if (save_puint_to_snorm_mask & (1 << index)) {
6028 emit_puint_to_snorm(emit, &tmp_dst, &input_src);
6029 }
6030 else if (save_puint_to_uscaled_mask & (1 << index)) {
6031 emit_puint_to_uscaled(emit, &tmp_dst, &input_src);
6032 }
6033 else if (save_puint_to_sscaled_mask & (1 << index)) {
6034 emit_puint_to_sscaled(emit, &tmp_dst, &input_src);
6035 }
6036 else {
6037 assert((save_w_1_mask | save_is_bgra_mask) & (1 << index));
6038 emit_instruction_op1(emit, VGPU10_OPCODE_MOV,
6039 &tmp_dst, &input_src, FALSE);
6040 }
6041
6042 if (save_is_bgra_mask & (1 << index)) {
6043 emit_swap_r_b(emit, &tmp_dst, &tmp_src);
6044 }
6045
6046 if (save_w_1_mask & (1 << index)) {
6047 /* MOV tmp.w, 1.0 */
6048 if (emit->key.vs.attrib_is_pure_int & (1 << index)) {
6049 emit_instruction_op1(emit, VGPU10_OPCODE_MOV,
6050 &tmp_dst_w, &one_int, FALSE);
6051 }
6052 else {
6053 emit_instruction_op1(emit, VGPU10_OPCODE_MOV,
6054 &tmp_dst_w, &one, FALSE);
6055 }
6056 }
6057 }
6058
6059 emit->key.vs.adjust_attrib_w_1 = save_w_1_mask;
6060 emit->key.vs.adjust_attrib_itof = save_itof_mask;
6061 emit->key.vs.adjust_attrib_utof = save_utof_mask;
6062 emit->key.vs.attrib_is_bgra = save_is_bgra_mask;
6063 emit->key.vs.attrib_puint_to_snorm = save_puint_to_snorm_mask;
6064 emit->key.vs.attrib_puint_to_uscaled = save_puint_to_uscaled_mask;
6065 emit->key.vs.attrib_puint_to_sscaled = save_puint_to_sscaled_mask;
6066 }
6067 }
6068
6069
6070 /**
6071 * Some common values like 0.0, 1.0, 0.5, etc. are frequently needed
6072 * to implement some instructions. We pre-allocate those values here
6073 * in the immediate constant buffer.
6074 */
6075 static void
6076 alloc_common_immediates(struct svga_shader_emitter_v10 *emit)
6077 {
6078 unsigned n = 0;
6079
6080 emit->common_immediate_pos[n++] =
6081 alloc_immediate_float4(emit, 0.0f, 1.0f, 0.5f, -1.0f);
6082
6083 if (emit->info.opcode_count[TGSI_OPCODE_LIT] > 0) {
6084 emit->common_immediate_pos[n++] =
6085 alloc_immediate_float4(emit, 128.0f, -128.0f, 0.0f, 0.0f);
6086 }
6087
6088 emit->common_immediate_pos[n++] =
6089 alloc_immediate_int4(emit, 0, 1, 0, -1);
6090
6091 if (emit->key.vs.attrib_puint_to_snorm) {
6092 emit->common_immediate_pos[n++] =
6093 alloc_immediate_float4(emit, -2.0f, 2.0f, 3.0f, -1.66666f);
6094 }
6095
6096 if (emit->key.vs.attrib_puint_to_uscaled) {
6097 emit->common_immediate_pos[n++] =
6098 alloc_immediate_float4(emit, 1023.0f, 3.0f, 0.0f, 0.0f);
6099 }
6100
6101 if (emit->key.vs.attrib_puint_to_sscaled) {
6102 emit->common_immediate_pos[n++] =
6103 alloc_immediate_int4(emit, 22, 12, 2, 0);
6104
6105 emit->common_immediate_pos[n++] =
6106 alloc_immediate_int4(emit, 22, 30, 0, 0);
6107 }
6108
6109 unsigned i;
6110
6111 for (i = 0; i < PIPE_MAX_SAMPLERS; i++) {
6112 if (emit->key.tex[i].texel_bias) {
6113 /* Replace 0.0f if more immediate float value is needed */
6114 emit->common_immediate_pos[n++] =
6115 alloc_immediate_float4(emit, 0.0001f, 0.0f, 0.0f, 0.0f);
6116 break;
6117 }
6118 }
6119
6120 assert(n <= ARRAY_SIZE(emit->common_immediate_pos));
6121 emit->num_common_immediates = n;
6122 }
6123
6124
6125 /**
6126 * Emit any extra/helper declarations/code that we might need between
6127 * the declaration section and code section.
6128 */
6129 static boolean
6130 emit_pre_helpers(struct svga_shader_emitter_v10 *emit)
6131 {
6132 /* Properties */
6133 if (emit->unit == PIPE_SHADER_GEOMETRY)
6134 emit_property_instructions(emit);
6135
6136 /* Declare inputs */
6137 if (!emit_input_declarations(emit))
6138 return FALSE;
6139
6140 /* Declare outputs */
6141 if (!emit_output_declarations(emit))
6142 return FALSE;
6143
6144 /* Declare temporary registers */
6145 emit_temporaries_declaration(emit);
6146
6147 /* Declare constant registers */
6148 emit_constant_declaration(emit);
6149
6150 /* Declare samplers and resources */
6151 emit_sampler_declarations(emit);
6152 emit_resource_declarations(emit);
6153
6154 /* Declare clip distance output registers */
6155 if (emit->unit == PIPE_SHADER_VERTEX ||
6156 emit->unit == PIPE_SHADER_GEOMETRY) {
6157 emit_clip_distance_declarations(emit);
6158 }
6159
6160 alloc_common_immediates(emit);
6161
6162 if (emit->unit == PIPE_SHADER_FRAGMENT &&
6163 emit->key.fs.alpha_func != SVGA3D_CMP_ALWAYS) {
6164 float alpha = emit->key.fs.alpha_ref;
6165 emit->fs.alpha_ref_index =
6166 alloc_immediate_float4(emit, alpha, alpha, alpha, alpha);
6167 }
6168
6169 /* Now, emit the constant block containing all the immediates
6170 * declared by shader, as well as the extra ones seen above.
6171 */
6172 emit_vgpu10_immediates_block(emit);
6173
6174 if (emit->unit == PIPE_SHADER_FRAGMENT) {
6175 emit_frontface_instructions(emit);
6176 emit_fragcoord_instructions(emit);
6177 }
6178 else if (emit->unit == PIPE_SHADER_VERTEX) {
6179 emit_vertex_attrib_instructions(emit);
6180 }
6181
6182 return TRUE;
6183 }
6184
6185
6186 /**
6187 * The device has no direct support for the pipe_blend_state::alpha_to_one
6188 * option so we implement it here with shader code.
6189 *
6190 * Note that this is kind of pointless, actually. Here we're clobbering
6191 * the alpha value with 1.0. So if alpha-to-coverage is enabled, we'll wind
6192 * up with 100% coverage. That's almost certainly not what the user wants.
6193 * The work-around is to add extra shader code to compute coverage from alpha
6194 * and write it to the coverage output register (if the user's shader doesn't
6195 * do so already). We'll probably do that in the future.
6196 */
6197 static void
6198 emit_alpha_to_one_instructions(struct svga_shader_emitter_v10 *emit,
6199 unsigned fs_color_tmp_index)
6200 {
6201 struct tgsi_full_src_register one = make_immediate_reg_float(emit, 1.0f);
6202 unsigned i;
6203
6204 /* Note: it's not 100% clear from the spec if we're supposed to clobber
6205 * the alpha for all render targets. But that's what NVIDIA does and
6206 * that's what Piglit tests.
6207 */
6208 for (i = 0; i < emit->fs.num_color_outputs; i++) {
6209 struct tgsi_full_dst_register color_dst;
6210
6211 if (fs_color_tmp_index != INVALID_INDEX && i == 0) {
6212 /* write to the temp color register */
6213 color_dst = make_dst_temp_reg(fs_color_tmp_index);
6214 }
6215 else {
6216 /* write directly to the color[i] output */
6217 color_dst = make_dst_output_reg(emit->fs.color_out_index[i]);
6218 }
6219
6220 color_dst = writemask_dst(&color_dst, TGSI_WRITEMASK_W);
6221
6222 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &color_dst, &one, FALSE);
6223 }
6224 }
6225
6226
6227 /**
6228 * Emit alpha test code. This compares TEMP[fs_color_tmp_index].w
6229 * against the alpha reference value and discards the fragment if the
6230 * comparison fails.
6231 */
6232 static void
6233 emit_alpha_test_instructions(struct svga_shader_emitter_v10 *emit,
6234 unsigned fs_color_tmp_index)
6235 {
6236 /* compare output color's alpha to alpha ref and kill */
6237 unsigned tmp = get_temp_index(emit);
6238 struct tgsi_full_src_register tmp_src = make_src_temp_reg(tmp);
6239 struct tgsi_full_src_register tmp_src_x =
6240 scalar_src(&tmp_src, TGSI_SWIZZLE_X);
6241 struct tgsi_full_dst_register tmp_dst = make_dst_temp_reg(tmp);
6242 struct tgsi_full_src_register color_src =
6243 make_src_temp_reg(fs_color_tmp_index);
6244 struct tgsi_full_src_register color_src_w =
6245 scalar_src(&color_src, TGSI_SWIZZLE_W);
6246 struct tgsi_full_src_register ref_src =
6247 make_src_immediate_reg(emit->fs.alpha_ref_index);
6248 struct tgsi_full_dst_register color_dst =
6249 make_dst_output_reg(emit->fs.color_out_index[0]);
6250
6251 assert(emit->unit == PIPE_SHADER_FRAGMENT);
6252
6253 /* dst = src0 'alpha_func' src1 */
6254 emit_comparison(emit, emit->key.fs.alpha_func, &tmp_dst,
6255 &color_src_w, &ref_src);
6256
6257 /* DISCARD if dst.x == 0 */
6258 begin_emit_instruction(emit);
6259 emit_discard_opcode(emit, FALSE); /* discard if src0.x is zero */
6260 emit_src_register(emit, &tmp_src_x);
6261 end_emit_instruction(emit);
6262
6263 /* If we don't need to broadcast the color below, emit the final color here.
6264 */
6265 if (emit->key.fs.write_color0_to_n_cbufs <= 1) {
6266 /* MOV output.color, tempcolor */
6267 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &color_dst,
6268 &color_src, FALSE); /* XXX saturate? */
6269 }
6270
6271 free_temp_indexes(emit);
6272 }
6273
6274
6275 /**
6276 * Emit instructions for writing a single color output to multiple
6277 * color buffers.
6278 * This is used when the TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS (or
6279 * when key.fs.white_fragments is true).
6280 * property is set and the number of render targets is greater than one.
6281 * \param fs_color_tmp_index index of the temp register that holds the
6282 * color to broadcast.
6283 */
6284 static void
6285 emit_broadcast_color_instructions(struct svga_shader_emitter_v10 *emit,
6286 unsigned fs_color_tmp_index)
6287 {
6288 const unsigned n = emit->key.fs.write_color0_to_n_cbufs;
6289 unsigned i;
6290 struct tgsi_full_src_register color_src;
6291
6292 if (emit->key.fs.white_fragments) {
6293 /* set all color outputs to white */
6294 color_src = make_immediate_reg_float(emit, 1.0f);
6295 }
6296 else {
6297 /* set all color outputs to TEMP[fs_color_tmp_index] */
6298 assert(fs_color_tmp_index != INVALID_INDEX);
6299 color_src = make_src_temp_reg(fs_color_tmp_index);
6300 }
6301
6302 assert(emit->unit == PIPE_SHADER_FRAGMENT);
6303
6304 for (i = 0; i < n; i++) {
6305 unsigned output_reg = emit->fs.color_out_index[i];
6306 struct tgsi_full_dst_register color_dst =
6307 make_dst_output_reg(output_reg);
6308
6309 /* Fill in this semantic here since we'll use it later in
6310 * emit_dst_register().
6311 */
6312 emit->info.output_semantic_name[output_reg] = TGSI_SEMANTIC_COLOR;
6313
6314 /* MOV output.color[i], tempcolor */
6315 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &color_dst,
6316 &color_src, FALSE); /* XXX saturate? */
6317 }
6318 }
6319
6320
6321 /**
6322 * Emit extra helper code after the original shader code, but before the
6323 * last END/RET instruction.
6324 * For vertex shaders this means emitting the extra code to apply the
6325 * prescale scale/translation.
6326 */
6327 static boolean
6328 emit_post_helpers(struct svga_shader_emitter_v10 *emit)
6329 {
6330 if (emit->unit == PIPE_SHADER_VERTEX) {
6331 emit_vertex_instructions(emit);
6332 }
6333 else if (emit->unit == PIPE_SHADER_FRAGMENT) {
6334 const unsigned fs_color_tmp_index = emit->fs.color_tmp_index;
6335
6336 assert(!(emit->key.fs.white_fragments &&
6337 emit->key.fs.write_color0_to_n_cbufs == 0));
6338
6339 /* We no longer want emit_dst_register() to substitute the
6340 * temporary fragment color register for the real color output.
6341 */
6342 emit->fs.color_tmp_index = INVALID_INDEX;
6343
6344 if (emit->key.fs.alpha_to_one) {
6345 emit_alpha_to_one_instructions(emit, fs_color_tmp_index);
6346 }
6347 if (emit->key.fs.alpha_func != SVGA3D_CMP_ALWAYS) {
6348 emit_alpha_test_instructions(emit, fs_color_tmp_index);
6349 }
6350 if (emit->key.fs.write_color0_to_n_cbufs > 1 ||
6351 emit->key.fs.white_fragments) {
6352 emit_broadcast_color_instructions(emit, fs_color_tmp_index);
6353 }
6354 }
6355
6356 return TRUE;
6357 }
6358
6359
6360 /**
6361 * Translate the TGSI tokens into VGPU10 tokens.
6362 */
6363 static boolean
6364 emit_vgpu10_instructions(struct svga_shader_emitter_v10 *emit,
6365 const struct tgsi_token *tokens)
6366 {
6367 struct tgsi_parse_context parse;
6368 boolean ret = TRUE;
6369 boolean pre_helpers_emitted = FALSE;
6370 unsigned inst_number = 0;
6371
6372 tgsi_parse_init(&parse, tokens);
6373
6374 while (!tgsi_parse_end_of_tokens(&parse)) {
6375 tgsi_parse_token(&parse);
6376
6377 switch (parse.FullToken.Token.Type) {
6378 case TGSI_TOKEN_TYPE_IMMEDIATE:
6379 ret = emit_vgpu10_immediate(emit, &parse.FullToken.FullImmediate);
6380 if (!ret)
6381 goto done;
6382 break;
6383
6384 case TGSI_TOKEN_TYPE_DECLARATION:
6385 ret = emit_vgpu10_declaration(emit, &parse.FullToken.FullDeclaration);
6386 if (!ret)
6387 goto done;
6388 break;
6389
6390 case TGSI_TOKEN_TYPE_INSTRUCTION:
6391 if (!pre_helpers_emitted) {
6392 ret = emit_pre_helpers(emit);
6393 if (!ret)
6394 goto done;
6395 pre_helpers_emitted = TRUE;
6396 }
6397 ret = emit_vgpu10_instruction(emit, inst_number++,
6398 &parse.FullToken.FullInstruction);
6399 if (!ret)
6400 goto done;
6401 break;
6402
6403 case TGSI_TOKEN_TYPE_PROPERTY:
6404 ret = emit_vgpu10_property(emit, &parse.FullToken.FullProperty);
6405 if (!ret)
6406 goto done;
6407 break;
6408
6409 default:
6410 break;
6411 }
6412 }
6413
6414 done:
6415 tgsi_parse_free(&parse);
6416 return ret;
6417 }
6418
6419
6420 /**
6421 * Emit the first VGPU10 shader tokens.
6422 */
6423 static boolean
6424 emit_vgpu10_header(struct svga_shader_emitter_v10 *emit)
6425 {
6426 VGPU10ProgramToken ptoken;
6427
6428 /* First token: VGPU10ProgramToken (version info, program type (VS,GS,PS)) */
6429 ptoken.majorVersion = 4;
6430 ptoken.minorVersion = 0;
6431 ptoken.programType = translate_shader_type(emit->unit);
6432 if (!emit_dword(emit, ptoken.value))
6433 return FALSE;
6434
6435 /* Second token: total length of shader, in tokens. We can't fill this
6436 * in until we're all done. Emit zero for now.
6437 */
6438 return emit_dword(emit, 0);
6439 }
6440
6441
6442 static boolean
6443 emit_vgpu10_tail(struct svga_shader_emitter_v10 *emit)
6444 {
6445 VGPU10ProgramToken *tokens;
6446
6447 /* Replace the second token with total shader length */
6448 tokens = (VGPU10ProgramToken *) emit->buf;
6449 tokens[1].value = emit_get_num_tokens(emit);
6450
6451 return TRUE;
6452 }
6453
6454
6455 /**
6456 * Modify the FS to read the BCOLORs and use the FACE register
6457 * to choose between the front/back colors.
6458 */
6459 static const struct tgsi_token *
6460 transform_fs_twoside(const struct tgsi_token *tokens)
6461 {
6462 if (0) {
6463 debug_printf("Before tgsi_add_two_side ------------------\n");
6464 tgsi_dump(tokens,0);
6465 }
6466 tokens = tgsi_add_two_side(tokens);
6467 if (0) {
6468 debug_printf("After tgsi_add_two_side ------------------\n");
6469 tgsi_dump(tokens, 0);
6470 }
6471 return tokens;
6472 }
6473
6474
6475 /**
6476 * Modify the FS to do polygon stipple.
6477 */
6478 static const struct tgsi_token *
6479 transform_fs_pstipple(struct svga_shader_emitter_v10 *emit,
6480 const struct tgsi_token *tokens)
6481 {
6482 const struct tgsi_token *new_tokens;
6483 unsigned unit;
6484
6485 if (0) {
6486 debug_printf("Before pstipple ------------------\n");
6487 tgsi_dump(tokens,0);
6488 }
6489
6490 new_tokens = util_pstipple_create_fragment_shader(tokens, &unit, 0,
6491 TGSI_FILE_INPUT);
6492
6493 emit->fs.pstipple_sampler_unit = unit;
6494
6495 /* Setup texture state for stipple */
6496 emit->sampler_target[unit] = TGSI_TEXTURE_2D;
6497 emit->key.tex[unit].swizzle_r = TGSI_SWIZZLE_X;
6498 emit->key.tex[unit].swizzle_g = TGSI_SWIZZLE_Y;
6499 emit->key.tex[unit].swizzle_b = TGSI_SWIZZLE_Z;
6500 emit->key.tex[unit].swizzle_a = TGSI_SWIZZLE_W;
6501
6502 if (0) {
6503 debug_printf("After pstipple ------------------\n");
6504 tgsi_dump(new_tokens, 0);
6505 }
6506
6507 return new_tokens;
6508 }
6509
6510 /**
6511 * Modify the FS to support anti-aliasing point.
6512 */
6513 static const struct tgsi_token *
6514 transform_fs_aapoint(const struct tgsi_token *tokens,
6515 int aa_coord_index)
6516 {
6517 if (0) {
6518 debug_printf("Before tgsi_add_aa_point ------------------\n");
6519 tgsi_dump(tokens,0);
6520 }
6521 tokens = tgsi_add_aa_point(tokens, aa_coord_index);
6522 if (0) {
6523 debug_printf("After tgsi_add_aa_point ------------------\n");
6524 tgsi_dump(tokens, 0);
6525 }
6526 return tokens;
6527 }
6528
6529 /**
6530 * This is the main entrypoint for the TGSI -> VPGU10 translator.
6531 */
6532 struct svga_shader_variant *
6533 svga_tgsi_vgpu10_translate(struct svga_context *svga,
6534 const struct svga_shader *shader,
6535 const struct svga_compile_key *key,
6536 unsigned unit)
6537 {
6538 struct svga_shader_variant *variant = NULL;
6539 struct svga_shader_emitter_v10 *emit;
6540 const struct tgsi_token *tokens = shader->tokens;
6541 struct svga_vertex_shader *vs = svga->curr.vs;
6542 struct svga_geometry_shader *gs = svga->curr.gs;
6543
6544 assert(unit == PIPE_SHADER_VERTEX ||
6545 unit == PIPE_SHADER_GEOMETRY ||
6546 unit == PIPE_SHADER_FRAGMENT);
6547
6548 /* These two flags cannot be used together */
6549 assert(key->vs.need_prescale + key->vs.undo_viewport <= 1);
6550
6551 SVGA_STATS_TIME_PUSH(svga_sws(svga), SVGA_STATS_TIME_TGSIVGPU10TRANSLATE);
6552 /*
6553 * Setup the code emitter
6554 */
6555 emit = alloc_emitter();
6556 if (!emit)
6557 goto done;
6558
6559 emit->unit = unit;
6560 emit->key = *key;
6561
6562 emit->vposition.need_prescale = (emit->key.vs.need_prescale ||
6563 emit->key.gs.need_prescale);
6564 emit->vposition.tmp_index = INVALID_INDEX;
6565 emit->vposition.so_index = INVALID_INDEX;
6566 emit->vposition.out_index = INVALID_INDEX;
6567
6568 emit->fs.color_tmp_index = INVALID_INDEX;
6569 emit->fs.face_input_index = INVALID_INDEX;
6570 emit->fs.fragcoord_input_index = INVALID_INDEX;
6571
6572 emit->gs.prim_id_index = INVALID_INDEX;
6573
6574 emit->clip_dist_out_index = INVALID_INDEX;
6575 emit->clip_dist_tmp_index = INVALID_INDEX;
6576 emit->clip_dist_so_index = INVALID_INDEX;
6577 emit->clip_vertex_out_index = INVALID_INDEX;
6578
6579 if (emit->key.fs.alpha_func == SVGA3D_CMP_INVALID) {
6580 emit->key.fs.alpha_func = SVGA3D_CMP_ALWAYS;
6581 }
6582
6583 if (unit == PIPE_SHADER_FRAGMENT) {
6584 if (key->fs.light_twoside) {
6585 tokens = transform_fs_twoside(tokens);
6586 }
6587 if (key->fs.pstipple) {
6588 const struct tgsi_token *new_tokens =
6589 transform_fs_pstipple(emit, tokens);
6590 if (tokens != shader->tokens) {
6591 /* free the two-sided shader tokens */
6592 tgsi_free_tokens(tokens);
6593 }
6594 tokens = new_tokens;
6595 }
6596 if (key->fs.aa_point) {
6597 tokens = transform_fs_aapoint(tokens, key->fs.aa_point_coord_index);
6598 }
6599 }
6600
6601 if (SVGA_DEBUG & DEBUG_TGSI) {
6602 debug_printf("#####################################\n");
6603 debug_printf("### TGSI Shader %u\n", shader->id);
6604 tgsi_dump(tokens, 0);
6605 }
6606
6607 /**
6608 * Rescan the header if the token string is different from the one
6609 * included in the shader; otherwise, the header info is already up-to-date
6610 */
6611 if (tokens != shader->tokens) {
6612 tgsi_scan_shader(tokens, &emit->info);
6613 } else {
6614 emit->info = shader->info;
6615 }
6616
6617 emit->num_outputs = emit->info.num_outputs;
6618
6619 if (unit == PIPE_SHADER_FRAGMENT) {
6620 /* Compute FS input remapping to match the output from VS/GS */
6621 if (gs) {
6622 svga_link_shaders(&gs->base.info, &emit->info, &emit->linkage);
6623 } else {
6624 assert(vs);
6625 svga_link_shaders(&vs->base.info, &emit->info, &emit->linkage);
6626 }
6627 } else if (unit == PIPE_SHADER_GEOMETRY) {
6628 assert(vs);
6629 svga_link_shaders(&vs->base.info, &emit->info, &emit->linkage);
6630 }
6631
6632 determine_clipping_mode(emit);
6633
6634 if (unit == PIPE_SHADER_GEOMETRY || unit == PIPE_SHADER_VERTEX) {
6635 if (shader->stream_output != NULL || emit->clip_mode == CLIP_DISTANCE) {
6636 /* if there is stream output declarations associated
6637 * with this shader or the shader writes to ClipDistance
6638 * then reserve extra registers for the non-adjusted vertex position
6639 * and the ClipDistance shadow copy
6640 */
6641 emit->vposition.so_index = emit->num_outputs++;
6642
6643 if (emit->clip_mode == CLIP_DISTANCE) {
6644 emit->clip_dist_so_index = emit->num_outputs++;
6645 if (emit->info.num_written_clipdistance > 4)
6646 emit->num_outputs++;
6647 }
6648 }
6649 }
6650
6651 /*
6652 * Do actual shader translation.
6653 */
6654 if (!emit_vgpu10_header(emit)) {
6655 debug_printf("svga: emit VGPU10 header failed\n");
6656 goto cleanup;
6657 }
6658
6659 if (!emit_vgpu10_instructions(emit, tokens)) {
6660 debug_printf("svga: emit VGPU10 instructions failed\n");
6661 goto cleanup;
6662 }
6663
6664 if (!emit_vgpu10_tail(emit)) {
6665 debug_printf("svga: emit VGPU10 tail failed\n");
6666 goto cleanup;
6667 }
6668
6669 if (emit->register_overflow) {
6670 goto cleanup;
6671 }
6672
6673 /*
6674 * Create, initialize the 'variant' object.
6675 */
6676 variant = svga_new_shader_variant(svga);
6677 if (!variant)
6678 goto cleanup;
6679
6680 variant->shader = shader;
6681 variant->nr_tokens = emit_get_num_tokens(emit);
6682 variant->tokens = (const unsigned *)emit->buf;
6683 emit->buf = NULL; /* buffer is no longer owed by emitter context */
6684 memcpy(&variant->key, key, sizeof(*key));
6685 variant->id = UTIL_BITMASK_INVALID_INDEX;
6686
6687 /* The extra constant starting offset starts with the number of
6688 * shader constants declared in the shader.
6689 */
6690 variant->extra_const_start = emit->num_shader_consts[0];
6691 if (key->gs.wide_point) {
6692 /**
6693 * The extra constant added in the transformed shader
6694 * for inverse viewport scale is to be supplied by the driver.
6695 * So the extra constant starting offset needs to be reduced by 1.
6696 */
6697 assert(variant->extra_const_start > 0);
6698 variant->extra_const_start--;
6699 }
6700
6701 variant->pstipple_sampler_unit = emit->fs.pstipple_sampler_unit;
6702
6703 /* If there was exactly one write to a fragment shader output register
6704 * and it came from a constant buffer, we know all fragments will have
6705 * the same color (except for blending).
6706 */
6707 variant->constant_color_output =
6708 emit->constant_color_output && emit->num_output_writes == 1;
6709
6710 /** keep track in the variant if flat interpolation is used
6711 * for any of the varyings.
6712 */
6713 variant->uses_flat_interp = emit->uses_flat_interp;
6714
6715 if (tokens != shader->tokens) {
6716 tgsi_free_tokens(tokens);
6717 }
6718
6719 cleanup:
6720 free_emitter(emit);
6721
6722 done:
6723 SVGA_STATS_TIME_POP(svga_sws(svga));
6724 return variant;
6725 }