src/gallium/drivers/swr/rasterizer/archrast/events.proto

   1 # Copyright (C) 2016 Intel Corporation.   All Rights Reserved.
   2 #
   3 # Permission is hereby granted, free of charge, to any person obtaining a
   4 # copy of this software and associated documentation files (the "Software"),
   5 # to deal in the Software without restriction, including without limitation
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  10 # The above copyright notice and this permission notice (including the next
  11 # paragraph) shall be included in all copies or substantial portions of the
  12 # Software.
  13 #
  14 # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 # THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18 # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  19 # FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  20 # IN THE SOFTWARE.
  21 #
  22 # Provides definitions for events.
  23
  24 enum GroupType
  25 {
  26     APIClearRenderTarget,
  27     APIDraw,
  28     APIDrawWakeAllThreads,
  29     APIDrawIndexed,
  30     APIDispatch,
  31     APIStoreTiles,
  32     APIGetDrawContext,
  33     APISync,
  34     APIWaitForIdle,
  35     FEProcessDraw,
  36     FEProcessDrawIndexed,
  37     FEFetchShader,
  38     FEVertexShader,
  39     FEHullShader,
  40     FETessellation,
  41     FEDomainShader,
  42     FEGeometryShader,
  43     FEStreamout,
  44     FEPAAssemble,
  45     FEBinPoints,
  46     FEBinLines,
  47     FEBinTriangles,
  48     FETriangleSetup,
  49     FEViewportCull,
  50     FEGuardbandClip,
  51     FEClipPoints,
  52     FEClipLines,
  53     FEClipTriangles,
  54     FECullZeroAreaAndBackface,
  55     FECullBetweenCenters,
  56     FEProcessStoreTiles,
  57     FEProcessInvalidateTiles,
  58     WorkerWorkOnFifoBE,
  59     WorkerFoundWork,
  60     BELoadTiles,
  61     BEDispatch,
  62     BEClear,
  63     BERasterizeLine,
  64     BERasterizeTriangle,
  65     BETriangleSetup,
  66     BEStepSetup,
  67     BECullZeroArea,
  68     BEEmptyTriangle,
  69     BETrivialAccept,
  70     BETrivialReject,
  71     BERasterizePartial,
  72     BEPixelBackend,
  73     BESetup,
  74     BEBarycentric,
  75     BEEarlyDepthTest,
  76     BEPixelShader,
  77     BESingleSampleBackend,
  78     BEPixelRateBackend,
  79     BESampleRateBackend,
  80     BENullBackend,
  81     BELateDepthTest,
  82     BEOutputMerger,
  83     BEStoreTiles,
  84     BEEndTile,
  85     WorkerWaitForThreadEvent,
  86 };
  87
  88 event Start
  89 {
  90     GroupType type;
  91     uint32_t id;
  92 };
  93
  94 event End
  95 {
  96     GroupType type;
  97     uint32_t count;
  98 };
  99
 100 event ThreadStartApiEvent
 101 {
 102 };
 103
 104 event ThreadStartWorkerEvent
 105 {
 106 };
 107
 108 event DrawInstancedEvent
 109 {
 110     uint32_t drawId;
 111     uint32_t topology;
 112     uint32_t numVertices;
 113     int32_t  startVertex;
 114     uint32_t numInstances;
 115     uint32_t startInstance;
 116 };
 117
 118 event DrawIndexedInstancedEvent
 119 {
 120     uint32_t drawId;
 121     uint32_t topology;
 122     uint32_t numIndices;
 123     int32_t  indexOffset;
 124     int32_t  baseVertex;
 125     uint32_t numInstances;
 126     uint32_t startInstance;
 127 };
 128
 129 event DispatchEvent
 130 {
 131     uint32_t drawId;
 132     uint32_t threadGroupCountX;
 133     uint32_t threadGroupCountY;
 134     uint32_t threadGroupCountZ;
 135 };
 136
 137 event FrameEndEvent
 138 {
 139     uint32_t frameId;
 140     uint32_t nextDrawId;
 141 };
 142
 143 ///@brief API Stat: Split draw event for DrawInstanced. In certain cases, Rasty can split draws up into smaller draws.
 144 event DrawInstancedSplitEvent
 145 {
 146     uint32_t drawId;
 147 };
 148
 149 ///@brief API Stat: Split draw event for DrawIndexedInstanced.
 150 event DrawIndexedInstancedSplitEvent
 151 {
 152     uint32_t drawId;
 153 };
 154
 155 ///@brief API Stat: Synchonization event.
 156 event SwrSyncEvent
 157 {
 158     uint32_t drawId;
 159 };
 160
 161 ///@brief API Stat: Invalidate hot tiles (i.e. tile cache)
 162 event SwrInvalidateTilesEvent
 163 {
 164     uint32_t drawId;
 165 };
 166
 167 ///@brief API Stat: Invalidate and discard hot tiles within pixel region
 168 event SwrDiscardRectEvent
 169 {
 170     uint32_t drawId;
 171 };
 172
 173 ///@brief API Stat: Flush tiles out to memory that is typically owned by driver (e.g. Flush RT cache)
 174 event SwrStoreTilesEvent
 175 {
 176     uint32_t drawId;
 177 };
 178
 179 event FrontendStatsEvent
 180 {
 181     uint32_t drawId;
 182     uint64_t IaVertices;
 183     uint64_t IaPrimitives;
 184     uint64_t VsInvocations;
 185     uint64_t HsInvocations;
 186     uint64_t DsInvocations;
 187     uint64_t GsInvocations;
 188     uint64_t GsPrimitives;
 189     uint64_t CInvocations;
 190     uint64_t CPrimitives;
 191     uint64_t SoPrimStorageNeeded0;
 192     uint64_t SoPrimStorageNeeded1;
 193     uint64_t SoPrimStorageNeeded2;
 194     uint64_t SoPrimStorageNeeded3;
 195     uint64_t SoNumPrimsWritten0;
 196     uint64_t SoNumPrimsWritten1;
 197     uint64_t SoNumPrimsWritten2;
 198     uint64_t SoNumPrimsWritten3;
 199 };
 200
 201 event BackendStatsEvent
 202 {
 203     uint32_t drawId;
 204     uint64_t DepthPassCount;
 205     uint64_t PsInvocations;
 206     uint64_t CsInvocations;
 207
 208 };
 209
 210 event EarlyDepthStencilInfoSingleSample
 211 {
 212         uint64_t depthPassMask;
 213         uint64_t stencilPassMask;
 214         uint64_t coverageMask;
 215 };
 216
 217 event EarlyDepthStencilInfoSampleRate
 218 {
 219         uint64_t depthPassMask;
 220         uint64_t stencilPassMask;
 221         uint64_t coverageMask;
 222 };
 223
 224 event EarlyDepthStencilInfoNullPS
 225 {
 226         uint64_t depthPassMask;
 227         uint64_t stencilPassMask;
 228         uint64_t coverageMask;
 229 };
 230
 231 event LateDepthStencilInfoSingleSample
 232 {
 233         uint64_t depthPassMask;
 234         uint64_t stencilPassMask;
 235         uint64_t coverageMask;
 236 };
 237
 238 event LateDepthStencilInfoSampleRate
 239 {
 240         uint64_t depthPassMask;
 241         uint64_t stencilPassMask;
 242         uint64_t coverageMask;
 243 };
 244
 245 event LateDepthStencilInfoNullPS
 246 {
 247         uint64_t depthPassMask;
 248         uint64_t stencilPassMask;
 249         uint64_t coverageMask;
 250 };
 251
 252 event EarlyDepthInfoPixelRate
 253 {
 254         uint64_t depthPassCount;
 255         uint64_t activeLanes;
 256 };
 257
 258
 259 event LateDepthInfoPixelRate
 260 {
 261         uint64_t depthPassCount;
 262         uint64_t activeLanes;
 263 };
 264
 265
 266 event BackendDrawEndEvent
 267 {
 268         uint32_t drawId;
 269 };
 270
 271 event FrontendDrawEndEvent
 272 {
 273         uint32_t drawId;
 274 };
 275
 276 event EarlyZSingleSample
 277 {
 278         uint32_t drawId;
 279         uint64_t passCount;
 280         uint64_t failCount;
 281         uint64_t testCount;
 282 };
 283
 284 event LateZSingleSample
 285 {
 286         uint32_t drawId;
 287         uint64_t passCount;
 288         uint64_t failCount;
 289         uint64_t testCount;
 290 };
 291
 292 event EarlyStencilSingleSample
 293 {
 294         uint32_t drawId;
 295         uint64_t passCount;
 296         uint64_t failCount;
 297         uint64_t testCount;
 298 };
 299
 300 event LateStencilSingleSample
 301 {
 302         uint32_t drawId;
 303         uint64_t passCount;
 304         uint64_t failCount;
 305         uint64_t testCount;
 306 };
 307
 308 event EarlyZSampleRate
 309 {
 310         uint32_t drawId;
 311         uint64_t passCount;
 312         uint64_t failCount;
 313         uint64_t testCount;
 314 };
 315
 316 event LateZSampleRate
 317 {
 318         uint32_t drawId;
 319         uint64_t passCount;
 320         uint64_t failCount;
 321         uint64_t testCount;
 322 };
 323
 324 event EarlyStencilSampleRate
 325 {
 326         uint32_t drawId;
 327         uint64_t passCount;
 328         uint64_t failCount;
 329         uint64_t testCount;
 330 };
 331
 332 event LateStencilSampleRate
 333 {
 334         uint32_t drawId;
 335         uint64_t passCount;
 336         uint64_t failCount;
 337         uint64_t testCount;
 338 };
 339
 340 event EarlyZNullPS
 341 {
 342         uint32_t drawId;
 343         uint64_t passCount;
 344         uint64_t failCount;
 345         uint64_t testCount;
 346 };
 347
 348 event EarlyStencilNullPS
 349 {
 350         uint32_t drawId;
 351         uint64_t passCount;
 352         uint64_t failCount;
 353         uint64_t testCount;
 354 };
 355
 356 event EarlyZPixelRate
 357 {
 358         uint32_t drawId;
 359         uint64_t passCount;
 360         uint64_t failCount;
 361         uint64_t testCount;
 362 };
 363
 364 event LateZPixelRate
 365 {
 366         uint32_t drawId;
 367         uint64_t passCount;
 368         uint64_t failCount;
 369         uint64_t testCount;
 370 };
 371
 372
 373 event EarlyOmZ
 374 {
 375         uint32_t drawId;
 376         uint64_t passCount;
 377         uint64_t failCount;
 378         uint64_t testCount;
 379 };
 380
 381 event EarlyOmStencil
 382 {
 383         uint32_t drawId;
 384         uint64_t passCount;
 385         uint64_t failCount;
 386         uint64_t testCount;
 387 };
 388
 389 event LateOmZ
 390 {
 391         uint32_t drawId;
 392         uint64_t passCount;
 393         uint64_t failCount;
 394         uint64_t testCount;
 395 };
 396
 397 event LateOmStencil
 398 {
 399         uint32_t drawId;
 400         uint64_t passCount;
 401         uint64_t failCount;
 402         uint64_t testCount;
 403 };
 404
 405 event GSPrimInfo
 406 {
 407         uint64_t inputPrimCount;
 408         uint64_t primGeneratedCount;
 409         uint64_t vertsInput;
 410 };
 411
 412 event GSInputPrims
 413 {
 414         uint32_t drawId;
 415         uint64_t inputPrimCount;
 416 };
 417
 418 event GSPrimsGen
 419 {
 420         uint32_t drawId;
 421         uint64_t primGeneratedCount;
 422 };
 423
 424 event GSVertsInput
 425 {
 426         uint32_t drawId;
 427         uint64_t vertsInput;
 428 };
 429
 430 event ClipVertexCount
 431 {
 432         uint64_t vertsPerPrim;
 433         uint64_t primMask;
 434 };
 435
 436 //REMOVE AND REPLACE
 437 event FlushVertClip
 438 {
 439         uint32_t drawId;
 440 };
 441
 442 event VertsClipped
 443 {
 444         uint32_t drawId;
 445         uint64_t clipCount;
 446 };
 447
 448 event TessPrimCount
 449 {
 450         uint64_t primCount;
 451 };
 452
 453 //REMOVE AND REPLACE
 454 event TessPrimFlush
 455 {
 456         uint32_t drawId;
 457 };
 458
 459 event TessPrims
 460 {
 461         uint32_t drawId;
 462         uint64_t primCount;
 463 };