1 # Copyright (C) 2016 Intel Corporation. All Rights Reserved.
3 # Permission is hereby granted, free of charge, to any person obtaining a
4 # copy of this software and associated documentation files (the "Software"),
5 # to deal in the Software without restriction, including without limitation
6 # the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 # and/or sell copies of the Software, and to permit persons to whom the
8 # Software is furnished to do so, subject to the following conditions:
10 # The above copyright notice and this permission notice (including the next
11 # paragraph) shall be included in all copies or substantial portions of the
14 # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 # THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 # FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 # Provides definitions for events.
29 IndexedInstancedSplit = 3
32 event ThreadStartApiEvent
36 event ThreadStartWorkerEvent
49 uint32_t numInstances;
50 uint32_t startInstance;
55 uint32_t splitId; // Split draw count or id.
61 uint32_t threadGroupCountX;
62 uint32_t threadGroupCountY;
63 uint32_t threadGroupCountZ;
72 ///@brief API Stat: Synchonization event.
78 ///@brief API Stat: Invalidate hot tiles (i.e. tile cache)
79 event SwrInvalidateTilesEvent
84 ///@brief API Stat: Invalidate and discard hot tiles within pixel region
85 event SwrDiscardRectEvent
90 ///@brief API Stat: Flush tiles out to memory that is typically owned by driver (e.g. Flush RT cache)
91 event SwrStoreTilesEvent
96 event FrontendStatsEvent
100 uint64_t IaPrimitives;
101 uint64_t VsInvocations;
102 uint64_t HsInvocations;
103 uint64_t DsInvocations;
104 uint64_t GsInvocations;
105 uint64_t GsPrimitives;
106 uint64_t CInvocations;
107 uint64_t CPrimitives;
108 uint64_t SoPrimStorageNeeded0;
109 uint64_t SoPrimStorageNeeded1;
110 uint64_t SoPrimStorageNeeded2;
111 uint64_t SoPrimStorageNeeded3;
112 uint64_t SoNumPrimsWritten0;
113 uint64_t SoNumPrimsWritten1;
114 uint64_t SoNumPrimsWritten2;
115 uint64_t SoNumPrimsWritten3;
118 event BackendStatsEvent
121 uint64_t DepthPassCount;
122 uint64_t PsInvocations;
123 uint64_t CsInvocations;
127 event EarlyZSingleSample
134 event LateZSingleSample
141 event EarlyStencilSingleSample
148 event LateStencilSingleSample
155 event EarlyZSampleRate
162 event LateZSampleRate
169 event EarlyStencilSampleRate
176 event LateStencilSampleRate
183 // Total Early-Z counts, SingleSample and SampleRate
191 // Total LateZ counts, SingleSample and SampleRate
199 // Total EarlyStencil counts, SingleSample and SampleRate
207 // Total LateStencil counts, SingleSample and SampleRate
222 event EarlyStencilNullPS
229 event EarlyZPixelRate
275 uint64_t inputPrimCount;
281 uint64_t primGeneratedCount;
299 uint32_t rastTileCount;
305 uint32_t trivialRejectCount;
306 uint32_t trivialAcceptCount;
307 uint32_t mustClipCount;
313 uint64_t backfacePrimCount;
314 uint64_t degeneratePrimCount;
320 uint32_t alphaTestCount;
321 uint32_t alphaBlendCount;
327 uint32_t numInstExecuted;
333 uint32_t numInstExecuted;
339 uint32_t numInstExecuted;
345 uint32_t numInstExecuted;
351 uint32_t numInstExecuted;
357 uint32_t numInstExecuted;