Revert "swr/rast: Archrast codegen updates"
[mesa.git] / src / gallium / drivers / swr / rasterizer / archrast / events.proto
1 # Copyright (C) 2016 Intel Corporation. All Rights Reserved.
2 #
3 # Permission is hereby granted, free of charge, to any person obtaining a
4 # copy of this software and associated documentation files (the "Software"),
5 # to deal in the Software without restriction, including without limitation
6 # the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 # and/or sell copies of the Software, and to permit persons to whom the
8 # Software is furnished to do so, subject to the following conditions:
9 #
10 # The above copyright notice and this permission notice (including the next
11 # paragraph) shall be included in all copies or substantial portions of the
12 # Software.
13 #
14 # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 # THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 # FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
20 # IN THE SOFTWARE.
21 #
22 # Provides definitions for events.
23
24 enum AR_DRAW_TYPE
25 {
26 Instanced = 0,
27 IndexedInstanced = 1,
28 InstancedSplit = 2,
29 IndexedInstancedSplit = 3
30 };
31
32 event ThreadStartApiEvent
33 {
34 };
35
36 event ThreadStartWorkerEvent
37 {
38 };
39
40 event DrawInfoEvent
41 {
42 uint32_t drawId;
43 AR_DRAW_TYPE type;
44 uint32_t topology;
45 uint32_t numVertices;
46 uint32_t numIndices;
47 int32_t indexOffset;
48 int32_t baseVertex;
49 uint32_t numInstances;
50 uint32_t startInstance;
51 uint32_t tsEnable;
52 uint32_t gsEnable;
53 uint32_t soEnable;
54 uint32_t soTopology;
55 uint32_t splitId; // Split draw count or id.
56 };
57
58 event DispatchEvent
59 {
60 uint32_t drawId;
61 uint32_t threadGroupCountX;
62 uint32_t threadGroupCountY;
63 uint32_t threadGroupCountZ;
64 };
65
66 event FrameEndEvent
67 {
68 uint32_t frameId;
69 uint32_t nextDrawId;
70 };
71
72 ///@brief API Stat: Synchonization event.
73 event SwrSyncEvent
74 {
75 uint32_t drawId;
76 };
77
78 ///@brief API Stat: Invalidate hot tiles (i.e. tile cache)
79 event SwrInvalidateTilesEvent
80 {
81 uint32_t drawId;
82 };
83
84 ///@brief API Stat: Invalidate and discard hot tiles within pixel region
85 event SwrDiscardRectEvent
86 {
87 uint32_t drawId;
88 };
89
90 ///@brief API Stat: Flush tiles out to memory that is typically owned by driver (e.g. Flush RT cache)
91 event SwrStoreTilesEvent
92 {
93 uint32_t drawId;
94 };
95
96 event FrontendStatsEvent
97 {
98 uint32_t drawId;
99 uint64_t IaVertices;
100 uint64_t IaPrimitives;
101 uint64_t VsInvocations;
102 uint64_t HsInvocations;
103 uint64_t DsInvocations;
104 uint64_t GsInvocations;
105 uint64_t GsPrimitives;
106 uint64_t CInvocations;
107 uint64_t CPrimitives;
108 uint64_t SoPrimStorageNeeded0;
109 uint64_t SoPrimStorageNeeded1;
110 uint64_t SoPrimStorageNeeded2;
111 uint64_t SoPrimStorageNeeded3;
112 uint64_t SoNumPrimsWritten0;
113 uint64_t SoNumPrimsWritten1;
114 uint64_t SoNumPrimsWritten2;
115 uint64_t SoNumPrimsWritten3;
116 };
117
118 event BackendStatsEvent
119 {
120 uint32_t drawId;
121 uint64_t DepthPassCount;
122 uint64_t PsInvocations;
123 uint64_t CsInvocations;
124
125 };
126
127 event EarlyZSingleSample
128 {
129 uint32_t drawId;
130 uint64_t passCount;
131 uint64_t failCount;
132 };
133
134 event LateZSingleSample
135 {
136 uint32_t drawId;
137 uint64_t passCount;
138 uint64_t failCount;
139 };
140
141 event EarlyStencilSingleSample
142 {
143 uint32_t drawId;
144 uint64_t passCount;
145 uint64_t failCount;
146 };
147
148 event LateStencilSingleSample
149 {
150 uint32_t drawId;
151 uint64_t passCount;
152 uint64_t failCount;
153 };
154
155 event EarlyZSampleRate
156 {
157 uint32_t drawId;
158 uint64_t passCount;
159 uint64_t failCount;
160 };
161
162 event LateZSampleRate
163 {
164 uint32_t drawId;
165 uint64_t passCount;
166 uint64_t failCount;
167 };
168
169 event EarlyStencilSampleRate
170 {
171 uint32_t drawId;
172 uint64_t passCount;
173 uint64_t failCount;
174 };
175
176 event LateStencilSampleRate
177 {
178 uint32_t drawId;
179 uint64_t passCount;
180 uint64_t failCount;
181 };
182
183 // Total Early-Z counts, SingleSample and SampleRate
184 event EarlyZ
185 {
186 uint32_t drawId;
187 uint64_t passCount;
188 uint64_t failCount;
189 };
190
191 // Total LateZ counts, SingleSample and SampleRate
192 event LateZ
193 {
194 uint32_t drawId;
195 uint64_t passCount;
196 uint64_t failCount;
197 };
198
199 // Total EarlyStencil counts, SingleSample and SampleRate
200 event EarlyStencil
201 {
202 uint32_t drawId;
203 uint64_t passCount;
204 uint64_t failCount;
205 };
206
207 // Total LateStencil counts, SingleSample and SampleRate
208 event LateStencil
209 {
210 uint32_t drawId;
211 uint64_t passCount;
212 uint64_t failCount;
213 };
214
215 event EarlyZNullPS
216 {
217 uint32_t drawId;
218 uint64_t passCount;
219 uint64_t failCount;
220 };
221
222 event EarlyStencilNullPS
223 {
224 uint32_t drawId;
225 uint64_t passCount;
226 uint64_t failCount;
227 };
228
229 event EarlyZPixelRate
230 {
231 uint32_t drawId;
232 uint64_t passCount;
233 uint64_t failCount;
234 };
235
236 event LateZPixelRate
237 {
238 uint32_t drawId;
239 uint64_t passCount;
240 uint64_t failCount;
241 };
242
243
244 event EarlyOmZ
245 {
246 uint32_t drawId;
247 uint64_t passCount;
248 uint64_t failCount;
249 };
250
251 event EarlyOmStencil
252 {
253 uint32_t drawId;
254 uint64_t passCount;
255 uint64_t failCount;
256 };
257
258 event LateOmZ
259 {
260 uint32_t drawId;
261 uint64_t passCount;
262 uint64_t failCount;
263 };
264
265 event LateOmStencil
266 {
267 uint32_t drawId;
268 uint64_t passCount;
269 uint64_t failCount;
270 };
271
272 event GSInputPrims
273 {
274 uint32_t drawId;
275 uint64_t inputPrimCount;
276 };
277
278 event GSPrimsGen
279 {
280 uint32_t drawId;
281 uint64_t primGeneratedCount;
282 };
283
284 event GSVertsInput
285 {
286 uint32_t drawId;
287 uint64_t vertsInput;
288 };
289
290 event TessPrims
291 {
292 uint32_t drawId;
293 uint64_t primCount;
294 };
295
296 event RasterTiles
297 {
298 uint32_t drawId;
299 uint32_t rastTileCount;
300 };
301
302 event ClipperEvent
303 {
304 uint32_t drawId;
305 uint32_t trivialRejectCount;
306 uint32_t trivialAcceptCount;
307 uint32_t mustClipCount;
308 };
309
310 event CullEvent
311 {
312 uint32_t drawId;
313 uint64_t backfacePrimCount;
314 uint64_t degeneratePrimCount;
315 };
316
317 event AlphaEvent
318 {
319 uint32_t drawId;
320 uint32_t alphaTestCount;
321 uint32_t alphaBlendCount;
322 };
323
324 event VSInfo
325 {
326 uint32_t drawId;
327 uint32_t numInstExecuted;
328 uint32_t numSampleExecuted;
329 uint32_t numSampleLExecuted;
330 uint32_t numSampleBExecuted;
331 uint32_t numSampleCExecuted;
332 uint32_t numSampleCLZExecuted;
333 uint32_t numSampleCDExecuted;
334 uint32_t numGather4Executed;
335 uint32_t numGather4CExecuted;
336 uint32_t numGather4CPOExecuted;
337 uint32_t numGather4CPOCExecuted;
338 uint32_t numLodExecuted;
339 };
340
341 event HSInfo
342 {
343 uint32_t drawId;
344 uint32_t numInstExecuted;
345 uint32_t numSampleExecuted;
346 uint32_t numSampleLExecuted;
347 uint32_t numSampleBExecuted;
348 uint32_t numSampleCExecuted;
349 uint32_t numSampleCLZExecuted;
350 uint32_t numSampleCDExecuted;
351 uint32_t numGather4Executed;
352 uint32_t numGather4CExecuted;
353 uint32_t numGather4CPOExecuted;
354 uint32_t numGather4CPOCExecuted;
355 uint32_t numLodExecuted;
356 };
357
358 event DSInfo
359 {
360 uint32_t drawId;
361 uint32_t numInstExecuted;
362 uint32_t numSampleExecuted;
363 uint32_t numSampleLExecuted;
364 uint32_t numSampleBExecuted;
365 uint32_t numSampleCExecuted;
366 uint32_t numSampleCLZExecuted;
367 uint32_t numSampleCDExecuted;
368 uint32_t numGather4Executed;
369 uint32_t numGather4CExecuted;
370 uint32_t numGather4CPOExecuted;
371 uint32_t numGather4CPOCExecuted;
372 uint32_t numLodExecuted;
373 };
374
375 event GSInfo
376 {
377 uint32_t drawId;
378 uint32_t numInstExecuted;
379 uint32_t numSampleExecuted;
380 uint32_t numSampleLExecuted;
381 uint32_t numSampleBExecuted;
382 uint32_t numSampleCExecuted;
383 uint32_t numSampleCLZExecuted;
384 uint32_t numSampleCDExecuted;
385 uint32_t numGather4Executed;
386 uint32_t numGather4CExecuted;
387 uint32_t numGather4CPOExecuted;
388 uint32_t numGather4CPOCExecuted;
389 uint32_t numLodExecuted;
390
391 };
392
393 event PSInfo
394 {
395 uint32_t drawId;
396 uint32_t numInstExecuted;
397 uint32_t numSampleExecuted;
398 uint32_t numSampleLExecuted;
399 uint32_t numSampleBExecuted;
400 uint32_t numSampleCExecuted;
401 uint32_t numSampleCLZExecuted;
402 uint32_t numSampleCDExecuted;
403 uint32_t numGather4Executed;
404 uint32_t numGather4CExecuted;
405 uint32_t numGather4CPOExecuted;
406 uint32_t numGather4CPOCExecuted;
407 uint32_t numLodExecuted;
408 };
409
410 event CSInfo
411 {
412 uint32_t drawId;
413 uint32_t numInstExecuted;
414 uint32_t numSampleExecuted;
415 uint32_t numSampleLExecuted;
416 uint32_t numSampleBExecuted;
417 uint32_t numSampleCExecuted;
418 uint32_t numSampleCLZExecuted;
419 uint32_t numSampleCDExecuted;
420 uint32_t numGather4Executed;
421 uint32_t numGather4CExecuted;
422 uint32_t numGather4CPOExecuted;
423 uint32_t numGather4CPOCExecuted;
424 uint32_t numLodExecuted;
425 };