src/gallium/drivers/swr/rasterizer/archrast/events_private.proto

   1 # Copyright (C) 2018 Intel Corporation.   All Rights Reserved.
   2 #
   3 # Permission is hereby granted, free of charge, to any person obtaining a
   4 # copy of this software and associated documentation files (the "Software"),
   5 # to deal in the Software without restriction, including without limitation
   6 # the rights to use, copy, modify, merge, publish, distribute, sublicense,
   7 # and/or sell copies of the Software, and to permit persons to whom the
   8 # Software is furnished to do so, subject to the following conditions:
   9 #
  10 # The above copyright notice and this permission notice (including the next
  11 # paragraph) shall be included in all copies or substantial portions of the
  12 # Software.
  13 #
  14 # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 # THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18 # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  19 # FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  20 # IN THE SOFTWARE.
  21 #
  22 # Provides definitions for private internal events that are only used internally
  23 # to rasty for communicating information between Rasty and Archrast. One goal for
  24 # ArchRast is to not pollute the Rasty code with lots of calculations, etc. that
  25 # are needed to compute per draw statistics, etc.
  26
  27 event Pipeline::EarlyDepthStencilInfoSingleSample
  28 {
  29     uint64_t depthPassMask;
  30     uint64_t stencilPassMask;
  31     uint64_t coverageMask;
  32 };
  33
  34 event Pipeline::EarlyDepthStencilInfoSampleRate
  35 {
  36     uint64_t depthPassMask;
  37     uint64_t stencilPassMask;
  38     uint64_t coverageMask;
  39 };
  40
  41 event Pipeline::EarlyDepthStencilInfoNullPS
  42 {
  43     uint64_t depthPassMask;
  44     uint64_t stencilPassMask;
  45     uint64_t coverageMask;
  46 };
  47
  48 event Pipeline::LateDepthStencilInfoSingleSample
  49 {
  50     uint64_t depthPassMask;
  51     uint64_t stencilPassMask;
  52     uint64_t coverageMask;
  53 };
  54
  55 event Pipeline::LateDepthStencilInfoSampleRate
  56 {
  57     uint64_t depthPassMask;
  58     uint64_t stencilPassMask;
  59     uint64_t coverageMask;
  60 };
  61
  62 event Pipeline::LateDepthStencilInfoNullPS
  63 {
  64     uint64_t depthPassMask;
  65     uint64_t stencilPassMask;
  66     uint64_t coverageMask;
  67 };
  68
  69 event Pipeline::EarlyDepthInfoPixelRate
  70 {
  71     uint64_t depthPassCount;
  72     uint64_t activeLanes;
  73 };
  74
  75
  76 event Pipeline::LateDepthInfoPixelRate
  77 {
  78     uint64_t depthPassCount;
  79     uint64_t activeLanes;
  80 };
  81
  82
  83 event Pipeline::BackendDrawEndEvent
  84 {
  85     uint32_t drawId;
  86 };
  87
  88 event Pipeline::FrontendDrawEndEvent
  89 {
  90     uint32_t drawId;
  91 };
  92
  93 event Memory::MemoryAccessEvent
  94 {
  95     uint32_t drawId;
  96     uint64_t tsc;
  97     uint64_t ptr;
  98     uint32_t size;
  99     uint8_t isRead;
 100     uint8_t client;
 101 };
 102
 103 event Memory::MemoryStatsEndEvent
 104 {
 105     uint32_t drawId;
 106 };
 107
 108 event Pipeline::TessPrimCount
 109 {
 110     uint64_t primCount;
 111 };
 112
 113 event Pipeline::RasterTileCount
 114 {
 115     uint32_t drawId;
 116     uint64_t rasterTiles;
 117 };
 118
 119 event Pipeline::GSPrimInfo
 120 {
 121     uint64_t inputPrimCount;
 122     uint64_t primGeneratedCount;
 123     uint64_t vertsInput;
 124 };
 125
 126 // validMask is primitives that still need to be clipped. They weren't rejected due to trivial reject or nan.
 127 // clipMask is primitives that need to be clipped. So trivial accepts will be 0 while validMask for that is 1.
 128 // Trivial reject is numInvocations - pop_cnt32(validMask)
 129 // Trivial accept is validMask & ~clipMask
 130 // Must clip count is pop_cnt32(clipMask)
 131 event Pipeline::ClipInfoEvent
 132 {
 133     uint32_t numInvocations;
 134     uint32_t validMask;
 135     uint32_t clipMask;
 136 };
 137
 138 event Pipeline::CullInfoEvent
 139 {
 140     uint32_t drawId;
 141     uint64_t degeneratePrimMask;
 142     uint64_t backfacePrimMask;
 143     uint32_t validMask;
 144 };
 145
 146 event Pipeline::AlphaInfoEvent
 147 {
 148     uint32_t drawId;
 149     uint32_t alphaTestEnable;
 150     uint32_t alphaBlendEnable;
 151 };
 152
 153 event SwrApi::DrawInstancedEvent
 154 {
 155     uint32_t drawId;
 156     uint32_t topology;
 157     uint32_t numVertices;
 158     int32_t  startVertex;
 159     uint32_t numInstances;
 160     uint32_t startInstance;
 161     uint32_t tsEnable;
 162     uint32_t gsEnable;
 163     uint32_t soEnable;
 164     uint32_t soTopology;
 165     uint32_t splitId; // Split draw count or id.
 166 };
 167
 168 event SwrApi::DrawIndexedInstancedEvent
 169 {
 170     uint32_t drawId;
 171     uint32_t topology;
 172     uint32_t numIndices;
 173     int32_t  indexOffset;
 174     int32_t  baseVertex;
 175     uint32_t numInstances;
 176     uint32_t startInstance;
 177     uint32_t tsEnable;
 178     uint32_t gsEnable;
 179     uint32_t soEnable;
 180     uint32_t soTopology;
 181     uint32_t splitId; // Split draw count or id.
 182 };
 183
 184 event Shader::VSStats
 185 {
 186     HANDLE hStats;      // SWR_SHADER_STATS
 187 };
 188
 189 event Shader::HSStats
 190 {
 191     HANDLE hStats;      // SWR_SHADER_STATS
 192 };
 193
 194 event Shader::DSStats
 195 {
 196     HANDLE hStats;      // SWR_SHADER_STATS
 197 };
 198
 199 event Shader::GSStats
 200 {
 201     HANDLE hStats;      // SWR_SHADER_STATS
 202 };
 203
 204 event Shader::PSStats
 205 {
 206     HANDLE hStats;      // SWR_SHADER_STATS
 207 };
 208
 209 event Shader::CSStats
 210 {
 211     HANDLE hStats;      // SWR_SHADER_STATS
 212 };