src/gallium/drivers/swr/rasterizer/archrast/events_private.proto

   1 # Copyright (C) 2018 Intel Corporation.   All Rights Reserved.
   2 #
   3 # Permission is hereby granted, free of charge, to any person obtaining a
   4 # copy of this software and associated documentation files (the "Software"),
   5 # to deal in the Software without restriction, including without limitation
   6 # the rights to use, copy, modify, merge, publish, distribute, sublicense,
   7 # and/or sell copies of the Software, and to permit persons to whom the
   8 # Software is furnished to do so, subject to the following conditions:
   9 #
  10 # The above copyright notice and this permission notice (including the next
  11 # paragraph) shall be included in all copies or substantial portions of the
  12 # Software.
  13 #
  14 # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 # THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18 # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  19 # FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  20 # IN THE SOFTWARE.
  21 #
  22 # Provides definitions for private internal events that are only used internally
  23 # to rasty for communicating information between Rasty and Archrast. One goal for
  24 # ArchRast is to not pollute the Rasty code with lots of calculations, etc. that
  25 # are needed to compute per draw statistics, etc.
  26
  27 event EarlyDepthStencilInfoSingleSample
  28 {
  29     uint64_t depthPassMask;
  30     uint64_t stencilPassMask;
  31     uint64_t coverageMask;
  32 };
  33
  34 event EarlyDepthStencilInfoSampleRate
  35 {
  36     uint64_t depthPassMask;
  37     uint64_t stencilPassMask;
  38     uint64_t coverageMask;
  39 };
  40
  41 event EarlyDepthStencilInfoNullPS
  42 {
  43     uint64_t depthPassMask;
  44     uint64_t stencilPassMask;
  45     uint64_t coverageMask;
  46 };
  47
  48 event LateDepthStencilInfoSingleSample
  49 {
  50     uint64_t depthPassMask;
  51     uint64_t stencilPassMask;
  52     uint64_t coverageMask;
  53 };
  54
  55 event LateDepthStencilInfoSampleRate
  56 {
  57     uint64_t depthPassMask;
  58     uint64_t stencilPassMask;
  59     uint64_t coverageMask;
  60 };
  61
  62 event LateDepthStencilInfoNullPS
  63 {
  64     uint64_t depthPassMask;
  65     uint64_t stencilPassMask;
  66     uint64_t coverageMask;
  67 };
  68
  69 event EarlyDepthInfoPixelRate
  70 {
  71     uint64_t depthPassCount;
  72     uint64_t activeLanes;
  73 };
  74
  75
  76 event LateDepthInfoPixelRate
  77 {
  78     uint64_t depthPassCount;
  79     uint64_t activeLanes;
  80 };
  81
  82
  83 event BackendDrawEndEvent
  84 {
  85     uint32_t drawId;
  86 };
  87
  88 event FrontendDrawEndEvent
  89 {
  90     uint32_t drawId;
  91 };
  92
  93 event TessPrimCount
  94 {
  95     uint64_t primCount;
  96 };
  97
  98 event RasterTileCount
  99 {
 100     uint32_t drawId;
 101     uint64_t rasterTiles;
 102 };
 103
 104 event GSPrimInfo
 105 {
 106     uint64_t inputPrimCount;
 107     uint64_t primGeneratedCount;
 108     uint64_t vertsInput;
 109 };
 110
 111 // validMask is primitives that still need to be clipped. They weren't rejected due to trivial reject or nan.
 112 // clipMask is primitives that need to be clipped. So trivial accepts will be 0 while validMask for that is 1.
 113 // Trivial reject is numInvocations - pop_cnt32(validMask)
 114 // Trivial accept is validMask & ~clipMask
 115 // Must clip count is pop_cnt32(clipMask)
 116 event ClipInfoEvent
 117 {
 118     uint32_t numInvocations;
 119     uint32_t validMask;
 120     uint32_t clipMask;
 121 };
 122
 123 event CullInfoEvent
 124 {
 125     uint32_t drawId;
 126     uint64_t degeneratePrimMask;
 127     uint64_t backfacePrimMask;
 128     uint32_t validMask;
 129 };
 130
 131 event AlphaInfoEvent
 132 {
 133     uint32_t drawId;
 134     uint32_t alphaTestEnable;
 135     uint32_t alphaBlendEnable;
 136 };
 137
 138 event DrawInstancedEvent
 139 {
 140     uint32_t drawId;
 141     uint32_t topology;
 142     uint32_t numVertices;
 143     int32_t  startVertex;
 144     uint32_t numInstances;
 145     uint32_t startInstance;
 146     uint32_t tsEnable;
 147     uint32_t gsEnable;
 148     uint32_t soEnable;
 149     uint32_t soTopology;
 150     uint32_t splitId; // Split draw count or id.
 151 };
 152
 153 event DrawIndexedInstancedEvent
 154 {
 155     uint32_t drawId;
 156     uint32_t topology;
 157     uint32_t numIndices;
 158     int32_t  indexOffset;
 159     int32_t  baseVertex;
 160     uint32_t numInstances;
 161     uint32_t startInstance;
 162     uint32_t tsEnable;
 163     uint32_t gsEnable;
 164     uint32_t soEnable;
 165     uint32_t soTopology;
 166     uint32_t splitId; // Split draw count or id.
 167 };
 168
 169 event VSStats
 170 {
 171     uint32_t numInstExecuted;
 172 };
 173
 174 event HSStats
 175 {
 176     uint32_t numInstExecuted;
 177 };
 178
 179 event DSStats
 180 {
 181     uint32_t numInstExecuted;
 182 };
 183
 184 event GSStats
 185 {
 186     uint32_t numInstExecuted;
 187 };
 188
 189 event PSStats
 190 {
 191     uint32_t numInstExecuted;
 192 };
 193
 194 event CSStats
 195 {
 196     uint32_t numInstExecuted;
 197 };