src/gallium/drivers/swr/rasterizer/core/state.h

   1 /****************************************************************************
   2 * Copyright (C) 2014-2015 Intel Corporation.   All Rights Reserved.
   3 *
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  13 * Software.
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  16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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  21 * IN THE SOFTWARE.
  22 *
  23 * @file state.h
  24 *
  25 * @brief Definitions for API state.
  26 *
  27 ******************************************************************************/
  28 #pragma once
  29
  30 #include "common/formats.h"
  31 #include "common/simdintrin.h"
  32 #include <functional>
  33 #include <algorithm>
  34
  35 //////////////////////////////////////////////////////////////////////////
  36 /// PRIMITIVE_TOPOLOGY.
  37 //////////////////////////////////////////////////////////////////////////
  38 enum PRIMITIVE_TOPOLOGY
  39 {
  40     TOP_UNKNOWN = 0x0,
  41     TOP_POINT_LIST = 0x1,
  42     TOP_LINE_LIST = 0x2,
  43     TOP_LINE_STRIP = 0x3,
  44     TOP_TRIANGLE_LIST = 0x4,
  45     TOP_TRIANGLE_STRIP = 0x5,
  46     TOP_TRIANGLE_FAN = 0x6,
  47     TOP_QUAD_LIST = 0x7,
  48     TOP_QUAD_STRIP = 0x8,
  49     TOP_LINE_LIST_ADJ = 0x9,
  50     TOP_LISTSTRIP_ADJ = 0xA,
  51     TOP_TRI_LIST_ADJ = 0xB,
  52     TOP_TRI_STRIP_ADJ = 0xC,
  53     TOP_TRI_STRIP_REVERSE = 0xD,
  54     TOP_POLYGON = 0xE,
  55     TOP_RECT_LIST = 0xF,
  56     TOP_LINE_LOOP = 0x10,
  57     TOP_POINT_LIST_BF = 0x11,
  58     TOP_LINE_STRIP_CONT = 0x12,
  59     TOP_LINE_STRIP_BF = 0x13,
  60     TOP_LINE_STRIP_CONT_BF = 0x14,
  61     TOP_TRIANGLE_FAN_NOSTIPPLE = 0x16,
  62     TOP_TRIANGLE_DISC = 0x17,   /// @todo What is this??
  63
  64     TOP_PATCHLIST_BASE = 0x1F,  // Invalid topology, used to calculate num verts for a patchlist.
  65     TOP_PATCHLIST_1 = 0x20,     // List of 1-vertex patches
  66     TOP_PATCHLIST_2 = 0x21,
  67     TOP_PATCHLIST_3 = 0x22,
  68     TOP_PATCHLIST_4 = 0x23,
  69     TOP_PATCHLIST_5 = 0x24,
  70     TOP_PATCHLIST_6 = 0x25,
  71     TOP_PATCHLIST_7 = 0x26,
  72     TOP_PATCHLIST_8 = 0x27,
  73     TOP_PATCHLIST_9 = 0x28,
  74     TOP_PATCHLIST_10 = 0x29,
  75     TOP_PATCHLIST_11 = 0x2A,
  76     TOP_PATCHLIST_12 = 0x2B,
  77     TOP_PATCHLIST_13 = 0x2C,
  78     TOP_PATCHLIST_14 = 0x2D,
  79     TOP_PATCHLIST_15 = 0x2E,
  80     TOP_PATCHLIST_16 = 0x2F,
  81     TOP_PATCHLIST_17 = 0x30,
  82     TOP_PATCHLIST_18 = 0x31,
  83     TOP_PATCHLIST_19 = 0x32,
  84     TOP_PATCHLIST_20 = 0x33,
  85     TOP_PATCHLIST_21 = 0x34,
  86     TOP_PATCHLIST_22 = 0x35,
  87     TOP_PATCHLIST_23 = 0x36,
  88     TOP_PATCHLIST_24 = 0x37,
  89     TOP_PATCHLIST_25 = 0x38,
  90     TOP_PATCHLIST_26 = 0x39,
  91     TOP_PATCHLIST_27 = 0x3A,
  92     TOP_PATCHLIST_28 = 0x3B,
  93     TOP_PATCHLIST_29 = 0x3C,
  94     TOP_PATCHLIST_30 = 0x3D,
  95     TOP_PATCHLIST_31 = 0x3E,
  96     TOP_PATCHLIST_32 = 0x3F,   // List of 32-vertex patches
  97 };
  98
  99 //////////////////////////////////////////////////////////////////////////
 100 /// SWR_SHADER_TYPE
 101 //////////////////////////////////////////////////////////////////////////
 102 enum SWR_SHADER_TYPE
 103 {
 104     SHADER_VERTEX,
 105     SHADER_GEOMETRY,
 106     SHADER_DOMAIN,
 107     SHADER_HULL,
 108     SHADER_PIXEL,
 109     SHADER_COMPUTE,
 110
 111     NUM_SHADER_TYPES,
 112 };
 113
 114 //////////////////////////////////////////////////////////////////////////
 115 /// SWR_RENDERTARGET_ATTACHMENT
 116 /// @todo Its not clear what an "attachment" means. Its not common term.
 117 //////////////////////////////////////////////////////////////////////////
 118 enum SWR_RENDERTARGET_ATTACHMENT
 119 {
 120     SWR_ATTACHMENT_COLOR0,
 121     SWR_ATTACHMENT_COLOR1,
 122     SWR_ATTACHMENT_COLOR2,
 123     SWR_ATTACHMENT_COLOR3,
 124     SWR_ATTACHMENT_COLOR4,
 125     SWR_ATTACHMENT_COLOR5,
 126     SWR_ATTACHMENT_COLOR6,
 127     SWR_ATTACHMENT_COLOR7,
 128     SWR_ATTACHMENT_DEPTH,
 129     SWR_ATTACHMENT_STENCIL,
 130
 131     SWR_NUM_ATTACHMENTS
 132 };
 133
 134 #define SWR_NUM_RENDERTARGETS 8
 135
 136 #define SWR_ATTACHMENT_COLOR0_BIT 0x001
 137 #define SWR_ATTACHMENT_COLOR1_BIT 0x002
 138 #define SWR_ATTACHMENT_COLOR2_BIT 0x004
 139 #define SWR_ATTACHMENT_COLOR3_BIT 0x008
 140 #define SWR_ATTACHMENT_COLOR4_BIT 0x010
 141 #define SWR_ATTACHMENT_COLOR5_BIT 0x020
 142 #define SWR_ATTACHMENT_COLOR6_BIT 0x040
 143 #define SWR_ATTACHMENT_COLOR7_BIT 0x080
 144 #define SWR_ATTACHMENT_DEPTH_BIT 0x100
 145 #define SWR_ATTACHMENT_STENCIL_BIT 0x200
 146 #define SWR_ATTACHMENT_MASK_ALL 0x3ff
 147 #define SWR_ATTACHMENT_MASK_COLOR 0x0ff
 148
 149
 150 //////////////////////////////////////////////////////////////////////////
 151 /// @brief SWR Inner Tessellation factor ID
 152 /// See above GetTessFactorOutputPosition code for documentation
 153 enum SWR_INNER_TESSFACTOR_ID
 154 {
 155     SWR_QUAD_U_TRI_INSIDE,
 156     SWR_QUAD_V_INSIDE,
 157
 158     SWR_NUM_INNER_TESS_FACTORS,
 159 };
 160
 161 //////////////////////////////////////////////////////////////////////////
 162 /// @brief SWR Outer Tessellation factor ID
 163 /// See above GetTessFactorOutputPosition code for documentation
 164 enum SWR_OUTER_TESSFACTOR_ID
 165 {
 166     SWR_QUAD_U_EQ0_TRI_U_LINE_DETAIL,
 167     SWR_QUAD_V_EQ0_TRI_V_LINE_DENSITY,
 168     SWR_QUAD_U_EQ1_TRI_W,
 169     SWR_QUAD_V_EQ1,
 170
 171     SWR_NUM_OUTER_TESS_FACTORS,
 172 };
 173
 174
 175 /////////////////////////////////////////////////////////////////////////
 176 /// simdvertex
 177 /// @brief Defines a vertex element that holds all the data for SIMD vertices.
 178 ///        Contains position in clip space, hardcoded to attribute 0,
 179 ///        space for up to 32 attributes, as well as any SGV values generated
 180 ///        by the pipeline
 181 /////////////////////////////////////////////////////////////////////////
 182 enum SWR_VTX_SLOTS
 183 {
 184     VERTEX_POSITION_SLOT             = 0,
 185     VERTEX_POSITION_END_SLOT         = 0,
 186     VERTEX_ATTRIB_START_SLOT         = ( 1 + VERTEX_POSITION_END_SLOT),
 187     VERTEX_ATTRIB_END_SLOT           = (32 + VERTEX_POSITION_END_SLOT),
 188     VERTEX_RTAI_SLOT                 = (33 + VERTEX_POSITION_END_SLOT), // GS writes RenderTargetArrayIndex here
 189     VERTEX_PRIMID_SLOT               = (34 + VERTEX_POSITION_END_SLOT), // GS writes PrimId here
 190     VERTEX_CLIPCULL_DIST_LO_SLOT     = (35 + VERTEX_POSITION_END_SLOT), // VS writes lower 4 clip/cull dist
 191     VERTEX_CLIPCULL_DIST_HI_SLOT     = (36 + VERTEX_POSITION_END_SLOT), // VS writes upper 4 clip/cull dist
 192     VERTEX_POINT_SIZE_SLOT           = (37 + VERTEX_POSITION_END_SLOT), // VS writes point size here
 193     VERTEX_VIEWPORT_ARRAY_INDEX_SLOT = (38 + VERTEX_POSITION_END_SLOT),
 194     SWR_VTX_NUM_SLOTS                 = VERTEX_VIEWPORT_ARRAY_INDEX_SLOT,
 195 };
 196
 197 // SoAoSoA
 198 struct simdvertex
 199 {
 200     simdvector    attrib[SWR_VTX_NUM_SLOTS];
 201 };
 202
 203 //////////////////////////////////////////////////////////////////////////
 204 /// SWR_VS_CONTEXT
 205 /// @brief Input to vertex shader
 206 /////////////////////////////////////////////////////////////////////////
 207 struct SWR_VS_CONTEXT
 208 {
 209     simdvertex* pVin;           // IN: SIMD input vertex data store
 210     simdvertex* pVout;          // OUT: SIMD output vertex data store
 211
 212     uint32_t InstanceID;        // IN: Instance ID, constant across all verts of the SIMD
 213     simdscalari VertexID;       // IN: Vertex ID
 214     simdscalari mask;           // IN: Active mask for shader
 215 #if USE_SIMD16_FRONTEND
 216     uint32_t AlternateOffset;   // IN: amount to offset for interleaving even/odd simd8 in simd16vertex output
 217 #endif
 218 };
 219
 220 /////////////////////////////////////////////////////////////////////////
 221 /// ScalarCPoint
 222 /// @brief defines a control point element as passed from the output
 223 /// of the hull shader to the input of the domain shader
 224 /////////////////////////////////////////////////////////////////////////
 225 struct ScalarAttrib
 226 {
 227     float x;
 228     float y;
 229     float z;
 230     float w;
 231 };
 232
 233 struct ScalarCPoint
 234 {
 235     ScalarAttrib attrib[SWR_VTX_NUM_SLOTS];
 236 };
 237
 238 //////////////////////////////////////////////////////////////////////////
 239 /// SWR_TESSELLATION_FACTORS
 240 /// @brief Tessellation factors structure (non-vector)
 241 /////////////////////////////////////////////////////////////////////////
 242 struct SWR_TESSELLATION_FACTORS
 243 {
 244     float  OuterTessFactors[SWR_NUM_OUTER_TESS_FACTORS];
 245     float  InnerTessFactors[SWR_NUM_INNER_TESS_FACTORS];
 246 };
 247
 248 #define MAX_NUM_VERTS_PER_PRIM 32 // support up to 32 control point patches
 249 struct ScalarPatch
 250 {
 251     SWR_TESSELLATION_FACTORS tessFactors;
 252     ScalarCPoint cp[MAX_NUM_VERTS_PER_PRIM];
 253     ScalarCPoint patchData;
 254 };
 255
 256 //////////////////////////////////////////////////////////////////////////
 257 /// SWR_HS_CONTEXT
 258 /// @brief Input to hull shader
 259 /////////////////////////////////////////////////////////////////////////
 260 struct SWR_HS_CONTEXT
 261 {
 262     simdvertex vert[MAX_NUM_VERTS_PER_PRIM]; // IN: (SIMD) input primitive data
 263     simdscalari PrimitiveID;    // IN: (SIMD) primitive ID generated from the draw call
 264     simdscalari mask;           // IN: Active mask for shader
 265     ScalarPatch* pCPout;        // OUT: Output control point patch
 266                                 // SIMD-sized-array of SCALAR patches
 267 };
 268
 269 //////////////////////////////////////////////////////////////////////////
 270 /// SWR_DS_CONTEXT
 271 /// @brief Input to domain shader
 272 /////////////////////////////////////////////////////////////////////////
 273 struct SWR_DS_CONTEXT
 274 {
 275     uint32_t        PrimitiveID;    // IN: (SCALAR) PrimitiveID for the patch associated with the DS invocation
 276     uint32_t        vectorOffset;   // IN: (SCALAR) vector index offset into SIMD data.
 277     uint32_t        vectorStride;   // IN: (SCALAR) stride (in vectors) of output data per attribute-component
 278     ScalarPatch*    pCpIn;          // IN: (SCALAR) Control patch
 279     simdscalar*     pDomainU;       // IN: (SIMD) Domain Point U coords
 280     simdscalar*     pDomainV;       // IN: (SIMD) Domain Point V coords
 281     simdscalari     mask;           // IN: Active mask for shader
 282     simdscalar*     pOutputData;    // OUT: (SIMD) Vertex Attributes (2D array of vectors, one row per attribute-component)
 283 };
 284
 285 //////////////////////////////////////////////////////////////////////////
 286 /// SWR_GS_CONTEXT
 287 /// @brief Input to geometry shader.
 288 /////////////////////////////////////////////////////////////////////////
 289 struct SWR_GS_CONTEXT
 290 {
 291     simdvertex vert[MAX_NUM_VERTS_PER_PRIM]; // IN: input primitive data for SIMD prims
 292     simdscalari PrimitiveID;        // IN: input primitive ID generated from the draw call
 293     uint32_t InstanceID;            // IN: input instance ID
 294     simdscalari mask;               // IN: Active mask for shader
 295     uint8_t* pStream;               // OUT: output stream (contains vertices for all output streams)
 296     uint8_t* pCutOrStreamIdBuffer;  // OUT: cut or stream id buffer
 297     simdscalari vertexCount;        // OUT: num vertices emitted per SIMD lane
 298 };
 299
 300 struct PixelPositions
 301 {
 302     simdscalar UL;
 303     simdscalar center;
 304     simdscalar sample;
 305     simdscalar centroid;
 306 };
 307
 308 #define SWR_MAX_NUM_MULTISAMPLES 16
 309
 310 //////////////////////////////////////////////////////////////////////////
 311 /// SWR_PS_CONTEXT
 312 /// @brief Input to pixel shader.
 313 /////////////////////////////////////////////////////////////////////////
 314 struct SWR_PS_CONTEXT
 315 {
 316     PixelPositions vX;          // IN: x location(s) of pixels
 317     PixelPositions vY;          // IN: x location(s) of pixels
 318     simdscalar vZ;              // INOUT: z location of pixels
 319     simdscalari activeMask;     // OUT: mask for kill
 320     simdscalar  inputMask;      // IN: input coverage mask for all samples
 321     simdscalari oMask;          // OUT: mask for output coverage
 322
 323     PixelPositions vI;          // barycentric coords evaluated at pixel center, sample position, centroid
 324     PixelPositions vJ;
 325     PixelPositions vOneOverW;   // IN: 1/w
 326
 327     const float* pAttribs;      // IN: pointer to attribute barycentric coefficients
 328     const float* pPerspAttribs; // IN: pointer to attribute/w barycentric coefficients
 329     const float* pRecipW;       // IN: pointer to 1/w coord for each vertex
 330     const float *I;             // IN: Barycentric A, B, and C coefs used to compute I
 331     const float *J;             // IN: Barycentric A, B, and C coefs used to compute J
 332     float recipDet;             // IN: 1/Det, used when barycentric interpolating attributes
 333     const float* pSamplePosX;   // IN: array of sample positions
 334     const float* pSamplePosY;   // IN: array of sample positions
 335     simdvector shaded[SWR_NUM_RENDERTARGETS];
 336                                 // OUT: result color per rendertarget
 337
 338     uint32_t frontFace;         // IN: front- 1, back- 0
 339     uint32_t primID;            // IN: primitive ID
 340     uint32_t sampleIndex;       // IN: sampleIndex
 341
 342     uint32_t rasterizerSampleCount; // IN: sample count used by the rasterizer
 343
 344     uint8_t* pColorBuffer[SWR_NUM_RENDERTARGETS]; // IN: Pointers to render target hottiles
 345 };
 346
 347 //////////////////////////////////////////////////////////////////////////
 348 /// SWR_CS_CONTEXT
 349 /// @brief Input to compute shader.
 350 /////////////////////////////////////////////////////////////////////////
 351 struct SWR_CS_CONTEXT
 352 {
 353     // The ThreadGroupId is the current thread group index relative
 354     // to all thread groups in the Dispatch call. The ThreadId, ThreadIdInGroup,
 355     // and ThreadIdInGroupFlattened can be derived from ThreadGroupId in the shader.
 356
 357     // Compute shader accepts the following system values.
 358     // o ThreadId - Current thread id relative to all other threads in dispatch.
 359     // o ThreadGroupId - Current thread group id relative to all other groups in dispatch.
 360     // o ThreadIdInGroup - Current thread relative to all threads in the current thread group.
 361     // o ThreadIdInGroupFlattened - Flattened linear id derived from ThreadIdInGroup.
 362     //
 363     // All of these system values can be computed in the shader. They will be
 364     // derived from the current tile counter. The tile counter is an atomic counter that
 365     // resides in the draw context and is initialized to the product of the dispatch dims.
 366     //
 367     //  tileCounter = dispatchDims.x * dispatchDims.y * dispatchDims.z
 368     //
 369     // Each CPU worker thread will atomically decrement this counter and passes the current
 370     // count into the shader. When the count reaches 0 then all thread groups in the
 371     // dispatch call have been completed.
 372
 373     uint32_t tileCounter;  // The tile counter value for this thread group.
 374
 375     // Dispatch dimensions used by shader to compute system values from the tile counter.
 376     uint32_t dispatchDims[3];
 377
 378     uint8_t* pTGSM;  // Thread Group Shared Memory pointer.
 379
 380     uint8_t* pSpillFillBuffer;  // Spill/fill buffer for barrier support
 381
 382     uint8_t* pScratchSpace;     // Pointer to scratch space buffer used by the shader, shader is responsible
 383                                 // for subdividing scratch space per instance/simd
 384
 385     uint32_t scratchSpacePerSimd; // Scratch space per work item x SIMD_WIDTH
 386 };
 387
 388 // enums
 389 enum SWR_TILE_MODE
 390 {
 391     SWR_TILE_NONE = 0x0,    // Linear mode (no tiling)
 392     SWR_TILE_MODE_WMAJOR,   // W major tiling
 393     SWR_TILE_MODE_XMAJOR,   // X major tiling
 394     SWR_TILE_MODE_YMAJOR,   // Y major tiling
 395     SWR_TILE_SWRZ,          // SWR-Z tiling
 396
 397     SWR_TILE_MODE_COUNT
 398 };
 399
 400 enum SWR_SURFACE_TYPE
 401 {
 402     SURFACE_1D        = 0,
 403     SURFACE_2D        = 1,
 404     SURFACE_3D        = 2,
 405     SURFACE_CUBE      = 3,
 406     SURFACE_BUFFER    = 4,
 407     SURFACE_STRUCTURED_BUFFER = 5,
 408     SURFACE_NULL       = 7
 409 };
 410
 411 enum SWR_ZFUNCTION
 412 {
 413     ZFUNC_ALWAYS,
 414     ZFUNC_NEVER,
 415     ZFUNC_LT,
 416     ZFUNC_EQ,
 417     ZFUNC_LE,
 418     ZFUNC_GT,
 419     ZFUNC_NE,
 420     ZFUNC_GE,
 421     NUM_ZFUNC
 422 };
 423
 424 enum SWR_STENCILOP
 425 {
 426     STENCILOP_KEEP,
 427     STENCILOP_ZERO,
 428     STENCILOP_REPLACE,
 429     STENCILOP_INCRSAT,
 430     STENCILOP_DECRSAT,
 431     STENCILOP_INCR,
 432     STENCILOP_DECR,
 433     STENCILOP_INVERT
 434 };
 435
 436 enum SWR_BLEND_FACTOR
 437 {
 438     BLENDFACTOR_ONE,
 439     BLENDFACTOR_SRC_COLOR,
 440     BLENDFACTOR_SRC_ALPHA,
 441     BLENDFACTOR_DST_ALPHA,
 442     BLENDFACTOR_DST_COLOR,
 443     BLENDFACTOR_SRC_ALPHA_SATURATE,
 444     BLENDFACTOR_CONST_COLOR,
 445     BLENDFACTOR_CONST_ALPHA,
 446     BLENDFACTOR_SRC1_COLOR,
 447     BLENDFACTOR_SRC1_ALPHA,
 448     BLENDFACTOR_ZERO,
 449     BLENDFACTOR_INV_SRC_COLOR,
 450     BLENDFACTOR_INV_SRC_ALPHA,
 451     BLENDFACTOR_INV_DST_ALPHA,
 452     BLENDFACTOR_INV_DST_COLOR,
 453     BLENDFACTOR_INV_CONST_COLOR,
 454     BLENDFACTOR_INV_CONST_ALPHA,
 455     BLENDFACTOR_INV_SRC1_COLOR,
 456     BLENDFACTOR_INV_SRC1_ALPHA
 457 };
 458
 459 enum SWR_BLEND_OP
 460 {
 461     BLENDOP_ADD,
 462     BLENDOP_SUBTRACT,
 463     BLENDOP_REVSUBTRACT,
 464     BLENDOP_MIN,
 465     BLENDOP_MAX,
 466 };
 467
 468 enum SWR_LOGIC_OP
 469 {
 470     LOGICOP_CLEAR,
 471     LOGICOP_NOR,
 472     LOGICOP_AND_INVERTED,
 473     LOGICOP_COPY_INVERTED,
 474     LOGICOP_AND_REVERSE,
 475     LOGICOP_INVERT,
 476     LOGICOP_XOR,
 477     LOGICOP_NAND,
 478     LOGICOP_AND,
 479     LOGICOP_EQUIV,
 480     LOGICOP_NOOP,
 481     LOGICOP_OR_INVERTED,
 482     LOGICOP_COPY,
 483     LOGICOP_OR_REVERSE,
 484     LOGICOP_OR,
 485     LOGICOP_SET,
 486 };
 487
 488 //////////////////////////////////////////////////////////////////////////
 489 /// SWR_AUX_MODE
 490 /// @brief Specifies how the auxiliary buffer is used by the driver.
 491 //////////////////////////////////////////////////////////////////////////
 492 enum SWR_AUX_MODE
 493 {
 494     AUX_MODE_NONE,
 495     AUX_MODE_COLOR,
 496     AUX_MODE_UAV,
 497     AUX_MODE_DEPTH,
 498 };
 499
 500 //////////////////////////////////////////////////////////////////////////
 501 /// SWR_SURFACE_STATE
 502 //////////////////////////////////////////////////////////////////////////
 503 struct SWR_SURFACE_STATE
 504 {
 505     uint8_t *pBaseAddress;
 506     SWR_SURFACE_TYPE type;  // @llvm_enum
 507     SWR_FORMAT format;      // @llvm_enum
 508     uint32_t width;
 509     uint32_t height;
 510     uint32_t depth;
 511     uint32_t numSamples;
 512     uint32_t samplePattern;
 513     uint32_t pitch;
 514     uint32_t qpitch;
 515     uint32_t minLod;            // for sampled surfaces, the most detailed LOD that can be accessed by sampler
 516     uint32_t maxLod;            // for sampled surfaces, the max LOD that can be accessed
 517     float resourceMinLod;       // for sampled surfaces, the most detailed fractional mip that can be accessed by sampler
 518     uint32_t lod;               // for render targets, the lod being rendered to
 519     uint32_t arrayIndex;        // for render targets, the array index being rendered to for arrayed surfaces
 520     SWR_TILE_MODE tileMode;     // @llvm_enum
 521     uint32_t halign;
 522     uint32_t valign;
 523     uint32_t xOffset;
 524     uint32_t yOffset;
 525
 526     uint32_t lodOffsets[2][15]; // lod offsets for sampled surfaces
 527
 528     uint8_t *pAuxBaseAddress;   // Used for compression, append/consume counter, etc.
 529     SWR_AUX_MODE auxMode;      // @llvm_enum
 530
 531
 532     bool bInterleavedSamples;   // are MSAA samples stored interleaved or planar
 533 };
 534
 535 // vertex fetch state
 536 // WARNING- any changes to this struct need to be reflected
 537 // in the fetch shader jit
 538 struct SWR_VERTEX_BUFFER_STATE
 539 {
 540     uint32_t index;
 541     uint32_t pitch;
 542     const uint8_t *pData;
 543     uint32_t size;
 544     uint32_t numaNode;
 545     uint32_t minVertex;             // min vertex (for bounds checking)
 546     uint32_t maxVertex;             // size / pitch.  precalculated value used by fetch shader for OOB checks
 547     uint32_t partialInboundsSize;   // size % pitch.  precalculated value used by fetch shader for partially OOB vertices
 548 };
 549
 550 struct SWR_INDEX_BUFFER_STATE
 551 {
 552     // Format type for indices (e.g. UINT16, UINT32, etc.)
 553     SWR_FORMAT format; // @llvm_enum
 554     const void *pIndices;
 555     uint32_t size;
 556 };
 557
 558
 559 //////////////////////////////////////////////////////////////////////////
 560 /// SWR_FETCH_CONTEXT
 561 /// @brief Input to fetch shader.
 562 /// @note WARNING - Changes to this struct need to be reflected in the
 563 ///                 fetch shader jit.
 564 /////////////////////////////////////////////////////////////////////////
 565 struct SWR_FETCH_CONTEXT
 566 {
 567     const SWR_VERTEX_BUFFER_STATE* pStreams;    // IN: array of bound vertex buffers
 568     const int32_t* pIndices;                    // IN: pointer to index buffer for indexed draws
 569     const int32_t* pLastIndex;                  // IN: pointer to end of index buffer, used for bounds checking
 570     uint32_t CurInstance;                       // IN: current instance
 571     uint32_t BaseVertex;                        // IN: base vertex
 572     uint32_t StartVertex;                       // IN: start vertex
 573     uint32_t StartInstance;                     // IN: start instance
 574     simdscalari VertexID;                       // OUT: vector of vertex IDs
 575     simdscalari CutMask;                        // OUT: vector mask of indices which have the cut index value
 576 };
 577
 578 //////////////////////////////////////////////////////////////////////////
 579 /// SWR_STATS
 580 ///
 581 /// @brief All statistics generated by SWR go here. These are public
 582 ///        to driver.
 583 /////////////////////////////////////////////////////////////////////////
 584 OSALIGNLINE(struct) SWR_STATS
 585 {
 586     // Occlusion Query
 587     uint64_t DepthPassCount; // Number of passing depth tests. Not exact.
 588
 589     // Pipeline Stats
 590     uint64_t PsInvocations;  // Number of Pixel Shader invocations
 591     uint64_t CsInvocations;  // Number of Compute Shader invocations
 592
 593 };
 594
 595 //////////////////////////////////////////////////////////////////////////
 596 /// SWR_STATS
 597 ///
 598 /// @brief All statistics generated by FE.
 599 /////////////////////////////////////////////////////////////////////////
 600 OSALIGNLINE(struct) SWR_STATS_FE
 601 {
 602     uint64_t IaVertices;    // Number of Fetch Shader vertices
 603     uint64_t IaPrimitives;  // Number of PA primitives.
 604     uint64_t VsInvocations; // Number of Vertex Shader invocations
 605     uint64_t HsInvocations; // Number of Hull Shader invocations
 606     uint64_t DsInvocations; // Number of Domain Shader invocations
 607     uint64_t GsInvocations; // Number of Geometry Shader invocations
 608     uint64_t GsPrimitives;  // Number of prims GS outputs.
 609     uint64_t CInvocations;  // Number of clipper invocations
 610     uint64_t CPrimitives;   // Number of clipper primitives.
 611
 612     // Streamout Stats
 613     uint64_t SoPrimStorageNeeded[4];
 614     uint64_t SoNumPrimsWritten[4];
 615 };
 616
 617 //////////////////////////////////////////////////////////////////////////
 618 /// STREAMOUT_BUFFERS
 619 /////////////////////////////////////////////////////////////////////////
 620
 621 #define MAX_SO_STREAMS 4
 622 #define MAX_SO_BUFFERS 4
 623 #define MAX_ATTRIBUTES 32
 624
 625 struct SWR_STREAMOUT_BUFFER
 626 {
 627     bool enable;
 628     bool soWriteEnable;
 629
 630     // Pointers to streamout buffers.
 631     uint32_t* pBuffer;
 632
 633     // Size of buffer in dwords.
 634     uint32_t bufferSize;
 635
 636     // Vertex pitch of buffer in dwords.
 637     uint32_t pitch;
 638
 639     // Offset into buffer in dwords. SOS will increment this offset.
 640     uint32_t streamOffset;
 641
 642     // Offset to the SO write offset. If not null then we update offset here.
 643     uint32_t* pWriteOffset;
 644
 645 };
 646
 647 //////////////////////////////////////////////////////////////////////////
 648 /// STREAMOUT_STATE
 649 /////////////////////////////////////////////////////////////////////////
 650 struct SWR_STREAMOUT_STATE
 651 {
 652     // This disables stream output.
 653     bool soEnable;
 654
 655     // which streams are enabled for streamout
 656     bool streamEnable[MAX_SO_STREAMS];
 657
 658     // If set then do not send any streams to the rasterizer.
 659     bool rasterizerDisable;
 660
 661     // Specifies which stream to send to the rasterizer.
 662     uint32_t streamToRasterizer;
 663
 664     // The stream masks specify which attributes are sent to which streams.
 665     // These masks help the FE to setup the pPrimData buffer that is passed
 666     // the Stream Output Shader (SOS) function.
 667     uint32_t streamMasks[MAX_SO_STREAMS];
 668
 669     // Number of attributes, including position, per vertex that are streamed out.
 670     // This should match number of bits in stream mask.
 671     uint32_t streamNumEntries[MAX_SO_STREAMS];
 672 };
 673
 674 //////////////////////////////////////////////////////////////////////////
 675 /// STREAMOUT_CONTEXT - Passed to SOS
 676 /////////////////////////////////////////////////////////////////////////
 677 struct SWR_STREAMOUT_CONTEXT
 678 {
 679     uint32_t* pPrimData;
 680     SWR_STREAMOUT_BUFFER* pBuffer[MAX_SO_STREAMS];
 681
 682     // Num prims written for this stream
 683     uint32_t numPrimsWritten;
 684
 685     // Num prims that should have been written if there were no overflow.
 686     uint32_t numPrimStorageNeeded;
 687 };
 688
 689 //////////////////////////////////////////////////////////////////////////
 690 /// SWR_GS_STATE - Geometry shader state
 691 /////////////////////////////////////////////////////////////////////////
 692 struct SWR_GS_STATE
 693 {
 694     bool gsEnable;
 695
 696     // number of input attributes per vertex. used by the frontend to
 697     // optimize assembling primitives for GS
 698     uint32_t numInputAttribs;
 699
 700     // output topology - can be point, tristrip, or linestrip
 701     PRIMITIVE_TOPOLOGY outputTopology;      // @llvm_enum
 702
 703     // maximum number of verts that can be emitted by a single instance of the GS
 704     uint32_t maxNumVerts;
 705
 706     // instance count
 707     uint32_t instanceCount;
 708
 709     // geometry shader emits renderTargetArrayIndex
 710     bool emitsRenderTargetArrayIndex;
 711
 712     // geometry shader emits PrimitiveID
 713     bool emitsPrimitiveID;
 714
 715     // geometry shader emits ViewportArrayIndex
 716     bool emitsViewportArrayIndex;
 717
 718     // if true, geometry shader emits a single stream, with separate cut buffer.
 719     // if false, geometry shader emits vertices for multiple streams to the stream buffer, with a separate StreamID buffer
 720     // to map vertices to streams
 721     bool isSingleStream;
 722
 723     // when single stream is enabled, singleStreamID dictates which stream is being output.
 724     // field ignored if isSingleStream is false
 725     uint32_t singleStreamID;
 726 };
 727
 728
 729 //////////////////////////////////////////////////////////////////////////
 730 /// SWR_TS_OUTPUT_TOPOLOGY - Defines data output by the tessellator / DS
 731 /////////////////////////////////////////////////////////////////////////
 732 enum SWR_TS_OUTPUT_TOPOLOGY
 733 {
 734     SWR_TS_OUTPUT_POINT,
 735     SWR_TS_OUTPUT_LINE,
 736     SWR_TS_OUTPUT_TRI_CW,
 737     SWR_TS_OUTPUT_TRI_CCW,
 738
 739     SWR_TS_OUTPUT_TOPOLOGY_COUNT
 740 };
 741
 742 //////////////////////////////////////////////////////////////////////////
 743 /// SWR_TS_PARTITIONING - Defines tessellation algorithm
 744 /////////////////////////////////////////////////////////////////////////
 745 enum SWR_TS_PARTITIONING
 746 {
 747     SWR_TS_INTEGER,
 748     SWR_TS_ODD_FRACTIONAL,
 749     SWR_TS_EVEN_FRACTIONAL,
 750
 751     SWR_TS_PARTITIONING_COUNT
 752 };
 753
 754 //////////////////////////////////////////////////////////////////////////
 755 /// SWR_TS_DOMAIN - Defines Tessellation Domain
 756 /////////////////////////////////////////////////////////////////////////
 757 enum SWR_TS_DOMAIN
 758 {
 759     SWR_TS_QUAD,
 760     SWR_TS_TRI,
 761     SWR_TS_ISOLINE,
 762
 763     SWR_TS_DOMAIN_COUNT
 764 };
 765
 766 //////////////////////////////////////////////////////////////////////////
 767 /// SWR_TS_STATE - Tessellation state
 768 /////////////////////////////////////////////////////////////////////////
 769 struct SWR_TS_STATE
 770 {
 771     bool                    tsEnable;
 772     SWR_TS_OUTPUT_TOPOLOGY  tsOutputTopology;   // @llvm_enum
 773     SWR_TS_PARTITIONING     partitioning;       // @llvm_enum
 774     SWR_TS_DOMAIN           domain;             // @llvm_enum
 775
 776     PRIMITIVE_TOPOLOGY      postDSTopology;     // @llvm_enum
 777
 778     uint32_t                numHsInputAttribs;
 779     uint32_t                numHsOutputAttribs;
 780     uint32_t                numDsOutputAttribs;
 781 };
 782
 783 // output merger state
 784 struct SWR_RENDER_TARGET_BLEND_STATE
 785 {
 786     uint8_t writeDisableRed : 1;
 787     uint8_t writeDisableGreen : 1;
 788     uint8_t writeDisableBlue : 1;
 789     uint8_t writeDisableAlpha : 1;
 790 };
 791 static_assert(sizeof(SWR_RENDER_TARGET_BLEND_STATE) == 1, "Invalid SWR_RENDER_TARGET_BLEND_STATE size");
 792
 793 enum SWR_MULTISAMPLE_COUNT
 794 {
 795     SWR_MULTISAMPLE_1X = 0,
 796     SWR_MULTISAMPLE_2X,
 797     SWR_MULTISAMPLE_4X,
 798     SWR_MULTISAMPLE_8X,
 799     SWR_MULTISAMPLE_16X,
 800     SWR_MULTISAMPLE_TYPE_COUNT
 801 };
 802
 803 struct SWR_BLEND_STATE
 804 {
 805     // constant blend factor color in RGBA float
 806     float constantColor[4];
 807
 808     // alpha test reference value in unorm8 or float32
 809     uint32_t alphaTestReference;
 810     uint32_t sampleMask;
 811     // all RT's have the same sample count
 812     ///@todo move this to Output Merger state when we refactor
 813     SWR_MULTISAMPLE_COUNT sampleCount;  // @llvm_enum
 814
 815     SWR_RENDER_TARGET_BLEND_STATE renderTarget[SWR_NUM_RENDERTARGETS];
 816 };
 817 static_assert(sizeof(SWR_BLEND_STATE) == 36, "Invalid SWR_BLEND_STATE size");
 818
 819 //////////////////////////////////////////////////////////////////////////
 820 /// FUNCTION POINTERS FOR SHADERS
 821
 822 typedef void(__cdecl *PFN_FETCH_FUNC)(SWR_FETCH_CONTEXT& fetchInfo, simdvertex& out);
 823 typedef void(__cdecl *PFN_VERTEX_FUNC)(HANDLE hPrivateData, SWR_VS_CONTEXT* pVsContext);
 824 typedef void(__cdecl *PFN_HS_FUNC)(HANDLE hPrivateData, SWR_HS_CONTEXT* pHsContext);
 825 typedef void(__cdecl *PFN_DS_FUNC)(HANDLE hPrivateData, SWR_DS_CONTEXT* pDsContext);
 826 typedef void(__cdecl *PFN_GS_FUNC)(HANDLE hPrivateData, SWR_GS_CONTEXT* pGsContext);
 827 typedef void(__cdecl *PFN_CS_FUNC)(HANDLE hPrivateData, SWR_CS_CONTEXT* pCsContext);
 828 typedef void(__cdecl *PFN_SO_FUNC)(SWR_STREAMOUT_CONTEXT& soContext);
 829 typedef void(__cdecl *PFN_PIXEL_KERNEL)(HANDLE hPrivateData, SWR_PS_CONTEXT *pContext);
 830 typedef void(__cdecl *PFN_CPIXEL_KERNEL)(HANDLE hPrivateData, SWR_PS_CONTEXT *pContext);
 831 typedef void(__cdecl *PFN_BLEND_JIT_FUNC)(const SWR_BLEND_STATE*,
 832     simdvector& vSrc, simdvector& vSrc1, simdscalar& vSrc0Alpha, uint32_t sample,
 833     uint8_t* pDst, simdvector& vResult, simdscalari* vOMask, simdscalari* vCoverageMask);
 834 typedef simdscalar(*PFN_QUANTIZE_DEPTH)(simdscalar);
 835
 836
 837
 838 //////////////////////////////////////////////////////////////////////////
 839 /// FRONTEND_STATE
 840 /////////////////////////////////////////////////////////////////////////
 841 struct SWR_FRONTEND_STATE
 842 {
 843     // skip clip test, perspective divide, and viewport transform
 844     // intended for verts in screen space
 845     bool vpTransformDisable;
 846     bool bEnableCutIndex;
 847     union
 848     {
 849         struct
 850         {
 851             uint32_t triFan : 2;
 852             uint32_t lineStripList : 1;
 853             uint32_t triStripList : 2;
 854         };
 855         uint32_t bits;
 856     } provokingVertex;
 857     uint32_t topologyProvokingVertex; // provoking vertex for the draw topology
 858 };
 859
 860 //////////////////////////////////////////////////////////////////////////
 861 /// VIEWPORT_MATRIX
 862 /////////////////////////////////////////////////////////////////////////
 863 struct SWR_VIEWPORT_MATRIX
 864 {
 865     float m00;
 866     float m11;
 867     float m22;
 868     float m30;
 869     float m31;
 870     float m32;
 871 };
 872
 873 //////////////////////////////////////////////////////////////////////////
 874 /// VIEWPORT_MATRIXES
 875 /////////////////////////////////////////////////////////////////////////
 876 struct SWR_VIEWPORT_MATRICES
 877 {
 878     float m00[KNOB_NUM_VIEWPORTS_SCISSORS];
 879     float m11[KNOB_NUM_VIEWPORTS_SCISSORS];
 880     float m22[KNOB_NUM_VIEWPORTS_SCISSORS];
 881     float m30[KNOB_NUM_VIEWPORTS_SCISSORS];
 882     float m31[KNOB_NUM_VIEWPORTS_SCISSORS];
 883     float m32[KNOB_NUM_VIEWPORTS_SCISSORS];
 884 };
 885
 886 //////////////////////////////////////////////////////////////////////////
 887 /// SWR_VIEWPORT
 888 /////////////////////////////////////////////////////////////////////////
 889 struct SWR_VIEWPORT
 890 {
 891     float x;
 892     float y;
 893     float width;
 894     float height;
 895     float minZ;
 896     float maxZ;
 897 };
 898
 899 //////////////////////////////////////////////////////////////////////////
 900 /// SWR_CULLMODE
 901 //////////////////////////////////////////////////////////////////////////
 902 enum SWR_CULLMODE
 903 {
 904     SWR_CULLMODE_BOTH,
 905     SWR_CULLMODE_NONE,
 906     SWR_CULLMODE_FRONT,
 907     SWR_CULLMODE_BACK
 908 };
 909
 910 enum SWR_FILLMODE
 911 {
 912     SWR_FILLMODE_POINT,
 913     SWR_FILLMODE_WIREFRAME,
 914     SWR_FILLMODE_SOLID
 915 };
 916
 917 enum SWR_FRONTWINDING
 918 {
 919     SWR_FRONTWINDING_CW,
 920     SWR_FRONTWINDING_CCW
 921 };
 922
 923
 924 enum SWR_PIXEL_LOCATION
 925 {
 926     SWR_PIXEL_LOCATION_CENTER,
 927     SWR_PIXEL_LOCATION_UL,
 928 };
 929
 930 // fixed point screen space sample locations within a pixel
 931 struct SWR_MULTISAMPLE_POS
 932 {
 933 public:
 934     INLINE void SetXi(uint32_t sampleNum, uint32_t val) { _xi[sampleNum] = val; }; // @llvm_func
 935     INLINE void SetYi(uint32_t sampleNum, uint32_t val) { _yi[sampleNum] = val; }; // @llvm_func
 936     INLINE uint32_t Xi(uint32_t sampleNum) const { return _xi[sampleNum]; }; // @llvm_func
 937     INLINE uint32_t Yi(uint32_t sampleNum) const { return _yi[sampleNum]; }; // @llvm_func
 938     INLINE void SetX(uint32_t sampleNum, float val) { _x[sampleNum] = val; }; // @llvm_func
 939     INLINE void SetY(uint32_t sampleNum, float val) { _y[sampleNum] = val; }; // @llvm_func
 940     INLINE float X(uint32_t sampleNum) const { return _x[sampleNum]; }; // @llvm_func
 941     INLINE float Y(uint32_t sampleNum) const { return _y[sampleNum]; }; // @llvm_func
 942     typedef const float(&sampleArrayT)[SWR_MAX_NUM_MULTISAMPLES]; //@llvm_typedef
 943     INLINE sampleArrayT X() const { return _x; }; // @llvm_func
 944     INLINE sampleArrayT Y() const { return _y; }; // @llvm_func
 945     INLINE const __m128i& vXi(uint32_t sampleNum) const { return _vXi[sampleNum]; }; // @llvm_func
 946     INLINE const __m128i& vYi(uint32_t sampleNum) const { return _vYi[sampleNum]; }; // @llvm_func
 947     INLINE const simdscalar& vX(uint32_t sampleNum) const { return _vX[sampleNum]; }; // @llvm_func
 948     INLINE const simdscalar& vY(uint32_t sampleNum) const { return _vY[sampleNum]; }; // @llvm_func
 949     INLINE const __m128i& TileSampleOffsetsX() const { return tileSampleOffsetsX; }; // @llvm_func
 950     INLINE const __m128i& TileSampleOffsetsY() const { return tileSampleOffsetsY; }; // @llvm_func
 951
 952     INLINE void PrecalcSampleData(int numSamples)   // @llvm_func_start
 953     {
 954         for(int i = 0; i < numSamples; i++)
 955         {
 956             _vXi[i] = _mm_set1_epi32(_xi[i]);
 957             _vYi[i] = _mm_set1_epi32(_yi[i]);
 958             _vX[i] = _simd_set1_ps(_x[i]);
 959             _vY[i] = _simd_set1_ps(_y[i]);
 960         }
 961         // precalculate the raster tile BB for the rasterizer.
 962         CalcTileSampleOffsets(numSamples);
 963     } // @llvm_func_end
 964
 965
 966 private:
 967     INLINE void CalcTileSampleOffsets(int numSamples)   // @llvm_func_start
 968     {
 969         auto expandThenBlend4 = [](uint32_t* min, uint32_t* max, auto mask)
 970         {
 971             __m128i vMin = _mm_set1_epi32(*min);
 972             __m128i vMax = _mm_set1_epi32(*max);
 973             return _simd_blend4_epi32<decltype(mask)::value>(vMin, vMax);
 974         };
 975
 976         auto minXi = std::min_element(std::begin(_xi), &_xi[numSamples]);
 977         auto maxXi = std::max_element(std::begin(_xi), &_xi[numSamples]);
 978         std::integral_constant<int, 0xA> xMask;
 979         // BR(max),    BL(min),    UR(max),    UL(min)
 980         tileSampleOffsetsX = expandThenBlend4(minXi, maxXi, xMask);
 981
 982         auto minYi = std::min_element(std::begin(_yi), &_yi[numSamples]);
 983         auto maxYi = std::max_element(std::begin(_yi), &_yi[numSamples]);
 984         std::integral_constant<int, 0xC> yMask;
 985         // BR(max),    BL(min),    UR(max),    UL(min)
 986         tileSampleOffsetsY = expandThenBlend4(minYi, maxYi, yMask);
 987     };  // @llvm_func_end
 988     // scalar sample values
 989     uint32_t _xi[SWR_MAX_NUM_MULTISAMPLES];
 990     uint32_t _yi[SWR_MAX_NUM_MULTISAMPLES];
 991     float _x[SWR_MAX_NUM_MULTISAMPLES];
 992     float _y[SWR_MAX_NUM_MULTISAMPLES];
 993
 994     // precalc'd / vectorized samples
 995     __m128i _vXi[SWR_MAX_NUM_MULTISAMPLES];
 996     __m128i _vYi[SWR_MAX_NUM_MULTISAMPLES];
 997     simdscalar _vX[SWR_MAX_NUM_MULTISAMPLES];
 998     simdscalar _vY[SWR_MAX_NUM_MULTISAMPLES];
 999     __m128i tileSampleOffsetsX;
1000     __m128i tileSampleOffsetsY;
1001
1002 };
1003
1004 //////////////////////////////////////////////////////////////////////////
1005 /// SWR_RASTSTATE
1006 //////////////////////////////////////////////////////////////////////////
1007 struct SWR_RASTSTATE
1008 {
1009     uint32_t cullMode               : 2;
1010     uint32_t fillMode               : 2;
1011     uint32_t frontWinding           : 1;
1012     uint32_t scissorEnable          : 1;
1013     uint32_t depthClipEnable        : 1;
1014     uint32_t clipHalfZ              : 1;
1015     uint32_t pointParam             : 1;
1016     uint32_t pointSpriteEnable      : 1;
1017     uint32_t pointSpriteTopOrigin   : 1;
1018     uint32_t forcedSampleCount      : 1;
1019     uint32_t pixelOffset            : 1;
1020     uint32_t depthBiasPreAdjusted   : 1;    ///< depth bias constant is in float units, not per-format Z units
1021     uint32_t conservativeRast       : 1;
1022
1023     float pointSize;
1024     float lineWidth;
1025
1026     float depthBias;
1027     float slopeScaledDepthBias;
1028     float depthBiasClamp;
1029     SWR_FORMAT depthFormat;     // @llvm_enum
1030
1031     // sample count the rasterizer is running at
1032     SWR_MULTISAMPLE_COUNT sampleCount;  // @llvm_enum
1033     uint32_t pixelLocation;     // UL or Center
1034     SWR_MULTISAMPLE_POS samplePositions;    // @llvm_struct
1035     bool bIsCenterPattern;   // @llvm_enum
1036
1037     // user clip/cull distance enables
1038     uint8_t cullDistanceMask;
1039     uint8_t clipDistanceMask;
1040 };
1041
1042 enum SWR_CONSTANT_SOURCE
1043 {
1044     SWR_CONSTANT_SOURCE_CONST_0000,
1045     SWR_CONSTANT_SOURCE_CONST_0001_FLOAT,
1046     SWR_CONSTANT_SOURCE_CONST_1111_FLOAT,
1047     SWR_CONSTANT_SOURCE_PRIM_ID
1048 };
1049
1050 struct SWR_ATTRIB_SWIZZLE
1051 {
1052     uint16_t sourceAttrib : 5;          // source attribute
1053     uint16_t constantSource : 2;        // constant source to apply
1054     uint16_t componentOverrideMask : 4; // override component with constant source
1055 };
1056
1057 // backend state
1058 struct SWR_BACKEND_STATE
1059 {
1060     uint32_t constantInterpolationMask;     // bitmask indicating which attributes have constant interpolation
1061     uint32_t pointSpriteTexCoordMask;       // bitmask indicating the attribute(s) which should be interpreted as tex coordinates
1062
1063     uint8_t numAttributes;                  // total number of attributes to send to backend (up to 32)
1064     uint8_t numComponents[32];              // number of components to setup per attribute, this reduces some calculations for unneeded components
1065
1066     bool swizzleEnable;                 // when enabled, core will parse the swizzle map when
1067                                         // setting up attributes for the backend, otherwise
1068                                         // all attributes up to numAttributes will be sent
1069     SWR_ATTRIB_SWIZZLE swizzleMap[32];
1070 };
1071
1072
1073 union SWR_DEPTH_STENCIL_STATE
1074 {
1075     struct
1076     {
1077         // dword 0
1078         uint32_t depthWriteEnable : 1;
1079         uint32_t depthTestEnable : 1;
1080         uint32_t stencilWriteEnable : 1;
1081         uint32_t stencilTestEnable : 1;
1082         uint32_t doubleSidedStencilTestEnable : 1;
1083
1084         uint32_t depthTestFunc : 3;
1085         uint32_t stencilTestFunc : 3;
1086
1087         uint32_t backfaceStencilPassDepthPassOp : 3;
1088         uint32_t backfaceStencilPassDepthFailOp : 3;
1089         uint32_t backfaceStencilFailOp : 3;
1090         uint32_t backfaceStencilTestFunc : 3;
1091         uint32_t stencilPassDepthPassOp : 3;
1092         uint32_t stencilPassDepthFailOp : 3;
1093         uint32_t stencilFailOp : 3;
1094
1095         // dword 1
1096         uint8_t backfaceStencilWriteMask;
1097         uint8_t backfaceStencilTestMask;
1098         uint8_t stencilWriteMask;
1099         uint8_t stencilTestMask;
1100
1101         // dword 2
1102         uint8_t backfaceStencilRefValue;
1103         uint8_t stencilRefValue;
1104     };
1105     uint32_t value[3];
1106 };
1107
1108 enum SWR_SHADING_RATE
1109 {
1110     SWR_SHADING_RATE_PIXEL,
1111     SWR_SHADING_RATE_SAMPLE,
1112     SWR_SHADING_RATE_COUNT,
1113 };
1114
1115 enum SWR_INPUT_COVERAGE
1116 {
1117     SWR_INPUT_COVERAGE_NONE,
1118     SWR_INPUT_COVERAGE_NORMAL,
1119     SWR_INPUT_COVERAGE_INNER_CONSERVATIVE,
1120     SWR_INPUT_COVERAGE_COUNT,
1121 };
1122
1123 enum SWR_PS_POSITION_OFFSET
1124 {
1125     SWR_PS_POSITION_SAMPLE_NONE,
1126     SWR_PS_POSITION_SAMPLE_OFFSET,
1127     SWR_PS_POSITION_CENTROID_OFFSET,
1128     SWR_PS_POSITION_OFFSET_COUNT,
1129 };
1130
1131 enum SWR_BARYCENTRICS_MASK
1132 {
1133     SWR_BARYCENTRIC_PER_PIXEL_MASK = 0x1,
1134     SWR_BARYCENTRIC_CENTROID_MASK = 0x2,
1135     SWR_BARYCENTRIC_PER_SAMPLE_MASK = 0x4,
1136 };
1137
1138 // pixel shader state
1139 struct SWR_PS_STATE
1140 {
1141     // dword 0-1
1142     PFN_PIXEL_KERNEL pfnPixelShader;  // @llvm_pfn
1143
1144     // dword 2
1145     uint32_t killsPixel             : 1;    // pixel shader can kill pixels
1146     uint32_t inputCoverage          : 2;    // ps uses input coverage
1147     uint32_t writesODepth           : 1;    // pixel shader writes to depth
1148     uint32_t usesSourceDepth        : 1;    // pixel shader reads depth
1149     uint32_t shadingRate            : 2;    // shading per pixel / sample / coarse pixel
1150     uint32_t numRenderTargets       : 4;    // number of render target outputs in use (0-8)
1151     uint32_t posOffset              : 2;    // type of offset (none, sample, centroid) to add to pixel position
1152     uint32_t barycentricsMask       : 3;    // which type(s) of barycentric coords does the PS interpolate attributes with
1153     uint32_t usesUAV                : 1;    // pixel shader accesses UAV
1154     uint32_t forceEarlyZ            : 1;    // force execution of early depth/stencil test
1155 };
1156
1157 // depth bounds state
1158 struct SWR_DEPTH_BOUNDS_STATE
1159 {
1160     bool    depthBoundsTestEnable;
1161     float   depthBoundsTestMinValue;
1162     float   depthBoundsTestMaxValue;
1163 };
1164