src/gallium/drivers/swr/rasterizer/core/state.h

   1 /****************************************************************************
   2 * Copyright (C) 2014-2015 Intel Corporation.   All Rights Reserved.
   3 *
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  16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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  21 * IN THE SOFTWARE.
  22 *
  23 * @file state.h
  24 *
  25 * @brief Definitions for API state.
  26 *
  27 ******************************************************************************/
  28 #pragma once
  29
  30 #include "common/formats.h"
  31 #include "common/simdintrin.h"
  32
  33 // clear flags
  34 #define SWR_CLEAR_NONE        0
  35 #define SWR_CLEAR_COLOR      (1 << 0)
  36 #define SWR_CLEAR_DEPTH      (1 << 1)
  37 #define SWR_CLEAR_STENCIL    (1 << 2)
  38
  39 enum DRIVER_TYPE
  40 {
  41     DX,
  42     GL
  43 };
  44
  45 //////////////////////////////////////////////////////////////////////////
  46 /// PRIMITIVE_TOPOLOGY.
  47 //////////////////////////////////////////////////////////////////////////
  48 enum PRIMITIVE_TOPOLOGY
  49 {
  50     TOP_UNKNOWN = 0x0,
  51     TOP_POINT_LIST = 0x1,
  52     TOP_LINE_LIST = 0x2,
  53     TOP_LINE_STRIP = 0x3,
  54     TOP_TRIANGLE_LIST = 0x4,
  55     TOP_TRIANGLE_STRIP = 0x5,
  56     TOP_TRIANGLE_FAN = 0x6,
  57     TOP_QUAD_LIST = 0x7,
  58     TOP_QUAD_STRIP = 0x8,
  59     TOP_LINE_LIST_ADJ = 0x9,
  60     TOP_LISTSTRIP_ADJ = 0xA,
  61     TOP_TRI_LIST_ADJ = 0xB,
  62     TOP_TRI_STRIP_ADJ = 0xC,
  63     TOP_TRI_STRIP_REVERSE = 0xD,
  64     TOP_POLYGON = 0xE,
  65     TOP_RECT_LIST = 0xF,
  66     TOP_LINE_LOOP = 0x10,
  67     TOP_POINT_LIST_BF = 0x11,
  68     TOP_LINE_STRIP_CONT = 0x12,
  69     TOP_LINE_STRIP_BF = 0x13,
  70     TOP_LINE_STRIP_CONT_BF = 0x14,
  71     TOP_TRIANGLE_FAN_NOSTIPPLE = 0x16,
  72     TOP_TRIANGLE_DISC = 0x17,   /// @todo What is this??
  73
  74     TOP_PATCHLIST_BASE = 0x1F,  // Invalid topology, used to calculate num verts for a patchlist.
  75     TOP_PATCHLIST_1 = 0x20,     // List of 1-vertex patches
  76     TOP_PATCHLIST_2 = 0x21,
  77     TOP_PATCHLIST_3 = 0x22,
  78     TOP_PATCHLIST_4 = 0x23,
  79     TOP_PATCHLIST_5 = 0x24,
  80     TOP_PATCHLIST_6 = 0x25,
  81     TOP_PATCHLIST_7 = 0x26,
  82     TOP_PATCHLIST_8 = 0x27,
  83     TOP_PATCHLIST_9 = 0x28,
  84     TOP_PATCHLIST_10 = 0x29,
  85     TOP_PATCHLIST_11 = 0x2A,
  86     TOP_PATCHLIST_12 = 0x2B,
  87     TOP_PATCHLIST_13 = 0x2C,
  88     TOP_PATCHLIST_14 = 0x2D,
  89     TOP_PATCHLIST_15 = 0x2E,
  90     TOP_PATCHLIST_16 = 0x2F,
  91     TOP_PATCHLIST_17 = 0x30,
  92     TOP_PATCHLIST_18 = 0x31,
  93     TOP_PATCHLIST_19 = 0x32,
  94     TOP_PATCHLIST_20 = 0x33,
  95     TOP_PATCHLIST_21 = 0x34,
  96     TOP_PATCHLIST_22 = 0x35,
  97     TOP_PATCHLIST_23 = 0x36,
  98     TOP_PATCHLIST_24 = 0x37,
  99     TOP_PATCHLIST_25 = 0x38,
 100     TOP_PATCHLIST_26 = 0x39,
 101     TOP_PATCHLIST_27 = 0x3A,
 102     TOP_PATCHLIST_28 = 0x3B,
 103     TOP_PATCHLIST_29 = 0x3C,
 104     TOP_PATCHLIST_30 = 0x3D,
 105     TOP_PATCHLIST_31 = 0x3E,
 106     TOP_PATCHLIST_32 = 0x3F,   // List of 32-vertex patches
 107 };
 108
 109 //////////////////////////////////////////////////////////////////////////
 110 /// SWR_SHADER_TYPE
 111 //////////////////////////////////////////////////////////////////////////
 112 enum SWR_SHADER_TYPE
 113 {
 114     SHADER_VERTEX,
 115     SHADER_GEOMETRY,
 116     SHADER_DOMAIN,
 117     SHADER_HULL,
 118     SHADER_PIXEL,
 119     SHADER_COMPUTE,
 120
 121     NUM_SHADER_TYPES,
 122 };
 123
 124 //////////////////////////////////////////////////////////////////////////
 125 /// SWR_RENDERTARGET_ATTACHMENT
 126 /// @todo Its not clear what an "attachment" means. Its not common term.
 127 //////////////////////////////////////////////////////////////////////////
 128 enum SWR_RENDERTARGET_ATTACHMENT
 129 {
 130     SWR_ATTACHMENT_COLOR0,
 131     SWR_ATTACHMENT_COLOR1,
 132     SWR_ATTACHMENT_COLOR2,
 133     SWR_ATTACHMENT_COLOR3,
 134     SWR_ATTACHMENT_COLOR4,
 135     SWR_ATTACHMENT_COLOR5,
 136     SWR_ATTACHMENT_COLOR6,
 137     SWR_ATTACHMENT_COLOR7,
 138     SWR_ATTACHMENT_DEPTH,
 139     SWR_ATTACHMENT_STENCIL,
 140
 141     SWR_NUM_ATTACHMENTS
 142 };
 143
 144 #define SWR_NUM_RENDERTARGETS 8
 145
 146 #define SWR_ATTACHMENT_COLOR0_BIT 0x001
 147 #define SWR_ATTACHMENT_COLOR1_BIT 0x002
 148 #define SWR_ATTACHMENT_COLOR2_BIT 0x004
 149 #define SWR_ATTACHMENT_COLOR3_BIT 0x008
 150 #define SWR_ATTACHMENT_COLOR4_BIT 0x010
 151 #define SWR_ATTACHMENT_COLOR5_BIT 0x020
 152 #define SWR_ATTACHMENT_COLOR6_BIT 0x040
 153 #define SWR_ATTACHMENT_COLOR7_BIT 0x080
 154 #define SWR_ATTACHMENT_DEPTH_BIT 0x100
 155 #define SWR_ATTACHMENT_STENCIL_BIT 0x200
 156 #define SWR_ATTACHMENT_MASK_ALL 0x3ff
 157 #define SWR_ATTACHMENT_MASK_COLOR 0x0ff
 158
 159
 160 //////////////////////////////////////////////////////////////////////////
 161 /// @brief SWR Inner Tessellation factor ID
 162 /// See above GetTessFactorOutputPosition code for documentation
 163 enum SWR_INNER_TESSFACTOR_ID
 164 {
 165     SWR_QUAD_U_TRI_INSIDE,
 166     SWR_QUAD_V_INSIDE,
 167
 168     SWR_NUM_INNER_TESS_FACTORS,
 169 };
 170
 171 //////////////////////////////////////////////////////////////////////////
 172 /// @brief SWR Outer Tessellation factor ID
 173 /// See above GetTessFactorOutputPosition code for documentation
 174 enum SWR_OUTER_TESSFACTOR_ID
 175 {
 176     SWR_QUAD_U_EQ0_TRI_U_LINE_DETAIL,
 177     SWR_QUAD_V_EQ0_TRI_V_LINE_DENSITY,
 178     SWR_QUAD_U_EQ1_TRI_W,
 179     SWR_QUAD_V_EQ1,
 180
 181     SWR_NUM_OUTER_TESS_FACTORS,
 182 };
 183
 184
 185 /////////////////////////////////////////////////////////////////////////
 186 /// simdvertex
 187 /// @brief Defines a vertex element that holds all the data for SIMD vertices.
 188 ///        Contains position in clip space, hardcoded to attribute 0,
 189 ///        space for up to 32 attributes, as well as any SGV values generated
 190 ///        by the pipeline
 191 /////////////////////////////////////////////////////////////////////////
 192 #define VERTEX_POSITION_SLOT 0
 193 #define VERTEX_ATTRIB_START_SLOT 1
 194 #define VERTEX_ATTRIB_END_SLOT 32
 195 #define VERTEX_RTAI_SLOT 33         // GS writes RenderTargetArrayIndex here
 196 #define VERTEX_PRIMID_SLOT 34       // GS writes PrimId here
 197 #define VERTEX_CLIPCULL_DIST_LO_SLOT 35 // VS writes lower 4 clip/cull dist
 198 #define VERTEX_CLIPCULL_DIST_HI_SLOT 36 // VS writes upper 4 clip/cull dist
 199 #define VERTEX_POINT_SIZE_SLOT 37       // VS writes point size here
 200 // SoAoSoA
 201 struct simdvertex
 202 {
 203     simdvector    attrib[KNOB_NUM_ATTRIBUTES];
 204 };
 205
 206 //////////////////////////////////////////////////////////////////////////
 207 /// SWR_VS_CONTEXT
 208 /// @brief Input to vertex shader
 209 /////////////////////////////////////////////////////////////////////////
 210 struct SWR_VS_CONTEXT
 211 {
 212     simdvertex* pVin;           // IN: SIMD input vertex data store
 213     simdvertex* pVout;          // OUT: SIMD output vertex data store
 214
 215     uint32_t InstanceID;    // IN: Instance ID, constant across all verts of the SIMD
 216     simdscalari VertexID;   // IN: Vertex ID
 217     simdscalari mask;       // IN: Active mask for shader
 218 };
 219
 220 /////////////////////////////////////////////////////////////////////////
 221 /// ScalarCPoint
 222 /// @brief defines a control point element as passed from the output
 223 /// of the hull shader to the input of the domain shader
 224 /////////////////////////////////////////////////////////////////////////
 225 struct ScalarAttrib
 226 {
 227     float x;
 228     float y;
 229     float z;
 230     float w;
 231 };
 232
 233 struct ScalarCPoint
 234 {
 235     ScalarAttrib attrib[KNOB_NUM_ATTRIBUTES];
 236 };
 237
 238 //////////////////////////////////////////////////////////////////////////
 239 /// SWR_TESSELLATION_FACTORS
 240 /// @brief Tessellation factors structure (non-vector)
 241 /////////////////////////////////////////////////////////////////////////
 242 struct SWR_TESSELLATION_FACTORS
 243 {
 244     float  OuterTessFactors[SWR_NUM_OUTER_TESS_FACTORS];
 245     float  InnerTessFactors[SWR_NUM_INNER_TESS_FACTORS];
 246 };
 247
 248 #define MAX_NUM_VERTS_PER_PRIM 32 // support up to 32 control point patches
 249 struct ScalarPatch
 250 {
 251     SWR_TESSELLATION_FACTORS tessFactors;
 252     ScalarCPoint cp[MAX_NUM_VERTS_PER_PRIM];
 253     ScalarCPoint patchData;
 254 };
 255
 256 //////////////////////////////////////////////////////////////////////////
 257 /// SWR_HS_CONTEXT
 258 /// @brief Input to hull shader
 259 /////////////////////////////////////////////////////////////////////////
 260 struct SWR_HS_CONTEXT
 261 {
 262     simdvertex vert[MAX_NUM_VERTS_PER_PRIM]; // IN: (SIMD) input primitive data
 263     simdscalari PrimitiveID;    // IN: (SIMD) primitive ID generated from the draw call
 264     simdscalari mask;           // IN: Active mask for shader
 265     ScalarPatch* pCPout;        // OUT: Output control point patch
 266                                 // SIMD-sized-array of SCALAR patches
 267 };
 268
 269 //////////////////////////////////////////////////////////////////////////
 270 /// SWR_DS_CONTEXT
 271 /// @brief Input to domain shader
 272 /////////////////////////////////////////////////////////////////////////
 273 struct SWR_DS_CONTEXT
 274 {
 275     uint32_t        PrimitiveID;    // IN: (SCALAR) PrimitiveID for the patch associated with the DS invocation
 276     uint32_t        vectorOffset;   // IN: (SCALAR) vector index offset into SIMD data.
 277     uint32_t        vectorStride;   // IN: (SCALAR) stride (in vectors) of output data per attribute-component
 278     ScalarPatch*    pCpIn;          // IN: (SCALAR) Control patch
 279     simdscalar*     pDomainU;       // IN: (SIMD) Domain Point U coords
 280     simdscalar*     pDomainV;       // IN: (SIMD) Domain Point V coords
 281     simdscalari     mask;           // IN: Active mask for shader
 282     simdscalar*     pOutputData;    // OUT: (SIMD) Vertex Attributes (2D array of vectors, one row per attribute-component)
 283 };
 284
 285 //////////////////////////////////////////////////////////////////////////
 286 /// SWR_GS_CONTEXT
 287 /// @brief Input to geometry shader.
 288 /////////////////////////////////////////////////////////////////////////
 289 struct SWR_GS_CONTEXT
 290 {
 291     simdvertex vert[MAX_NUM_VERTS_PER_PRIM]; // IN: input primitive data for SIMD prims
 292     simdscalari PrimitiveID;        // IN: input primitive ID generated from the draw call
 293     uint32_t InstanceID;            // IN: input instance ID
 294     simdscalari mask;               // IN: Active mask for shader
 295     uint8_t* pStream;               // OUT: output stream (contains vertices for all output streams)
 296     uint8_t* pCutOrStreamIdBuffer;  // OUT: cut or stream id buffer
 297     simdscalari vertexCount;        // OUT: num vertices emitted per SIMD lane
 298 };
 299
 300 struct PixelPositions
 301 {
 302     simdscalar UL;
 303     simdscalar center;
 304     simdscalar sample;
 305     simdscalar centroid;
 306 };
 307
 308 #define SWR_MAX_NUM_MULTISAMPLES 16
 309
 310 //////////////////////////////////////////////////////////////////////////
 311 /// SWR_PS_CONTEXT
 312 /// @brief Input to pixel shader.
 313 /////////////////////////////////////////////////////////////////////////
 314 struct SWR_PS_CONTEXT
 315 {
 316     PixelPositions vX;          // IN: x location(s) of pixels
 317     PixelPositions vY;          // IN: x location(s) of pixels
 318     simdscalar vZ;              // INOUT: z location of pixels
 319     simdscalari activeMask;     // OUT: mask for kill
 320     simdscalar  inputMask;      // IN: input coverage mask for all samples
 321     simdscalari oMask;          // OUT: mask for output coverage
 322
 323     PixelPositions vI;          // barycentric coords evaluated at pixel center, sample position, centroid
 324     PixelPositions vJ;
 325     PixelPositions vOneOverW;   // IN: 1/w
 326
 327     const float* pAttribs;      // IN: pointer to attribute barycentric coefficients
 328     const float* pPerspAttribs; // IN: pointer to attribute/w barycentric coefficients
 329     const float* pRecipW;       // IN: pointer to 1/w coord for each vertex
 330     const float *I;             // IN: Barycentric A, B, and C coefs used to compute I
 331     const float *J;             // IN: Barycentric A, B, and C coefs used to compute J
 332     float recipDet;             // IN: 1/Det, used when barycentric interpolating attributes
 333     const float* pSamplePosX;   // IN: array of sample positions
 334     const float* pSamplePosY;   // IN: array of sample positions
 335     simdvector shaded[SWR_NUM_RENDERTARGETS];
 336                                 // OUT: result color per rendertarget
 337
 338     uint32_t frontFace;         // IN: front- 1, back- 0
 339     uint32_t primID;            // IN: primitive ID
 340     uint32_t sampleIndex;       // IN: sampleIndex
 341
 342 };
 343
 344 //////////////////////////////////////////////////////////////////////////
 345 /// SWR_CS_CONTEXT
 346 /// @brief Input to compute shader.
 347 /////////////////////////////////////////////////////////////////////////
 348 struct SWR_CS_CONTEXT
 349 {
 350     // The ThreadGroupId is the current thread group index relative
 351     // to all thread groups in the Dispatch call. The ThreadId, ThreadIdInGroup,
 352     // and ThreadIdInGroupFlattened can be derived from ThreadGroupId in the shader.
 353
 354     // Compute shader accepts the following system values.
 355     // o ThreadId - Current thread id relative to all other threads in dispatch.
 356     // o ThreadGroupId - Current thread group id relative to all other groups in dispatch.
 357     // o ThreadIdInGroup - Current thread relative to all threads in the current thread group.
 358     // o ThreadIdInGroupFlattened - Flattened linear id derived from ThreadIdInGroup.
 359     //
 360     // All of these system values can be computed in the shader. They will be
 361     // derived from the current tile counter. The tile counter is an atomic counter that
 362     // resides in the draw context and is initialized to the product of the dispatch dims.
 363     //
 364     //  tileCounter = dispatchDims.x * dispatchDims.y * dispatchDims.z
 365     //
 366     // Each CPU worker thread will atomically decrement this counter and passes the current
 367     // count into the shader. When the count reaches 0 then all thread groups in the
 368     // dispatch call have been completed.
 369
 370     uint32_t tileCounter;  // The tile counter value for this thread group.
 371
 372     // Dispatch dimensions used by shader to compute system values from the tile counter.
 373     uint32_t dispatchDims[3];
 374
 375     uint8_t* pTGSM;  // Thread Group Shared Memory pointer.
 376
 377     uint8_t* pSpillFillBuffer;  // Spill/fill buffer for barrier support
 378 };
 379
 380 // enums
 381 enum SWR_TILE_MODE
 382 {
 383     SWR_TILE_NONE = 0x0,    // Linear mode (no tiling)
 384     SWR_TILE_MODE_WMAJOR,   // W major tiling
 385     SWR_TILE_MODE_XMAJOR,   // X major tiling
 386     SWR_TILE_MODE_YMAJOR,   // Y major tiling
 387     SWR_TILE_SWRZ,          // SWR-Z tiling
 388
 389     SWR_TILE_MODE_COUNT
 390 };
 391
 392 enum SWR_SURFACE_TYPE
 393 {
 394     SURFACE_1D        = 0,
 395     SURFACE_2D        = 1,
 396     SURFACE_3D        = 2,
 397     SURFACE_CUBE      = 3,
 398     SURFACE_BUFFER    = 4,
 399     SURFACE_STRUCTURED_BUFFER = 5,
 400     SURFACE_NULL       = 7
 401 };
 402
 403 enum SWR_ZFUNCTION
 404 {
 405     ZFUNC_ALWAYS,
 406     ZFUNC_NEVER,
 407     ZFUNC_LT,
 408     ZFUNC_EQ,
 409     ZFUNC_LE,
 410     ZFUNC_GT,
 411     ZFUNC_NE,
 412     ZFUNC_GE,
 413     NUM_ZFUNC
 414 };
 415
 416 enum SWR_STENCILOP
 417 {
 418     STENCILOP_KEEP,
 419     STENCILOP_ZERO,
 420     STENCILOP_REPLACE,
 421     STENCILOP_INCRSAT,
 422     STENCILOP_DECRSAT,
 423     STENCILOP_INCR,
 424     STENCILOP_DECR,
 425     STENCILOP_INVERT
 426 };
 427
 428 enum SWR_BLEND_FACTOR
 429 {
 430     BLENDFACTOR_ONE,
 431     BLENDFACTOR_SRC_COLOR,
 432     BLENDFACTOR_SRC_ALPHA,
 433     BLENDFACTOR_DST_ALPHA,
 434     BLENDFACTOR_DST_COLOR,
 435     BLENDFACTOR_SRC_ALPHA_SATURATE,
 436     BLENDFACTOR_CONST_COLOR,
 437     BLENDFACTOR_CONST_ALPHA,
 438     BLENDFACTOR_SRC1_COLOR,
 439     BLENDFACTOR_SRC1_ALPHA,
 440     BLENDFACTOR_ZERO,
 441     BLENDFACTOR_INV_SRC_COLOR,
 442     BLENDFACTOR_INV_SRC_ALPHA,
 443     BLENDFACTOR_INV_DST_ALPHA,
 444     BLENDFACTOR_INV_DST_COLOR,
 445     BLENDFACTOR_INV_CONST_COLOR,
 446     BLENDFACTOR_INV_CONST_ALPHA,
 447     BLENDFACTOR_INV_SRC1_COLOR,
 448     BLENDFACTOR_INV_SRC1_ALPHA
 449 };
 450
 451 enum SWR_BLEND_OP
 452 {
 453     BLENDOP_ADD,
 454     BLENDOP_SUBTRACT,
 455     BLENDOP_REVSUBTRACT,
 456     BLENDOP_MIN,
 457     BLENDOP_MAX,
 458 };
 459
 460 enum SWR_LOGIC_OP
 461 {
 462     LOGICOP_CLEAR,
 463     LOGICOP_NOR,
 464     LOGICOP_AND_INVERTED,
 465     LOGICOP_COPY_INVERTED,
 466     LOGICOP_AND_REVERSE,
 467     LOGICOP_INVERT,
 468     LOGICOP_XOR,
 469     LOGICOP_NAND,
 470     LOGICOP_AND,
 471     LOGICOP_EQUIV,
 472     LOGICOP_NOOP,
 473     LOGICOP_OR_INVERTED,
 474     LOGICOP_COPY,
 475     LOGICOP_OR_REVERSE,
 476     LOGICOP_OR,
 477     LOGICOP_SET,
 478 };
 479
 480 struct SWR_SURFACE_STATE
 481 {
 482     uint8_t *pBaseAddress;
 483     SWR_SURFACE_TYPE type;  // @llvm_enum
 484     SWR_FORMAT format;      // @llvm_enum
 485     uint32_t width;
 486     uint32_t height;
 487     uint32_t depth;
 488     uint32_t numSamples;
 489     uint32_t samplePattern;
 490     uint32_t pitch;
 491     uint32_t qpitch;
 492     uint32_t minLod;            // for sampled surfaces, the most detailed LOD that can be accessed by sampler
 493     uint32_t maxLod;            // for sampled surfaces, the max LOD that can be accessed
 494     float resourceMinLod;       // for sampled surfaces, the most detailed fractional mip that can be accessed by sampler
 495     uint32_t lod;               // for render targets, the lod being rendered to
 496     uint32_t arrayIndex;        // for render targets, the array index being rendered to for arrayed surfaces
 497     SWR_TILE_MODE tileMode;     // @llvm_enum
 498     uint32_t halign;
 499     uint32_t valign;
 500     uint32_t xOffset;
 501     uint32_t yOffset;
 502
 503     uint32_t lodOffsets[2][15]; // lod offsets for sampled surfaces
 504
 505     uint8_t *pAuxBaseAddress;   // Used for compression, append/consume counter, etc.
 506
 507     bool bInterleavedSamples;   // are MSAA samples stored interleaved or planar
 508 };
 509
 510 // vertex fetch state
 511 // WARNING- any changes to this struct need to be reflected
 512 // in the fetch shader jit
 513 struct SWR_VERTEX_BUFFER_STATE
 514 {
 515     uint32_t index;
 516     uint32_t pitch;
 517     const uint8_t *pData;
 518     uint32_t size;
 519     uint32_t numaNode;
 520     uint32_t maxVertex;             // size / pitch.  precalculated value used by fetch shader for OOB checks
 521     uint32_t partialInboundsSize;   // size % pitch.  precalculated value used by fetch shader for partially OOB vertices
 522 };
 523
 524 struct SWR_INDEX_BUFFER_STATE
 525 {
 526     // Format type for indices (e.g. UINT16, UINT32, etc.)
 527     SWR_FORMAT format; // @llvm_enum
 528     const void *pIndices;
 529     uint32_t size;
 530 };
 531
 532
 533 //////////////////////////////////////////////////////////////////////////
 534 /// SWR_FETCH_CONTEXT
 535 /// @brief Input to fetch shader.
 536 /// @note WARNING - Changes to this struct need to be reflected in the
 537 ///                 fetch shader jit.
 538 /////////////////////////////////////////////////////////////////////////
 539 struct SWR_FETCH_CONTEXT
 540 {
 541     const SWR_VERTEX_BUFFER_STATE* pStreams;    // IN: array of bound vertex buffers
 542     const int32_t* pIndices;                    // IN: pointer to index buffer for indexed draws
 543     const int32_t* pLastIndex;                  // IN: pointer to end of index buffer, used for bounds checking
 544     uint32_t CurInstance;                       // IN: current instance
 545     uint32_t BaseVertex;                        // IN: base vertex
 546     uint32_t StartVertex;                       // IN: start vertex
 547     uint32_t StartInstance;                     // IN: start instance
 548     simdscalari VertexID;                       // OUT: vector of vertex IDs
 549     simdscalari CutMask;                        // OUT: vector mask of indices which have the cut index value
 550 };
 551
 552 //////////////////////////////////////////////////////////////////////////
 553 /// SWR_STATS
 554 ///
 555 /// @brief All statistics generated by SWR go here. These are public
 556 ///        to driver.
 557 /////////////////////////////////////////////////////////////////////////
 558 struct SWR_STATS
 559 {
 560     // Occlusion Query
 561     uint64_t DepthPassCount; // Number of passing depth tests. Not exact.
 562
 563     // Pipeline Stats
 564     uint64_t IaVertices;    // Number of Fetch Shader vertices
 565     uint64_t IaPrimitives;  // Number of PA primitives.
 566     uint64_t VsInvocations; // Number of Vertex Shader invocations
 567     uint64_t HsInvocations; // Number of Hull Shader invocations
 568     uint64_t DsInvocations; // Number of Domain Shader invocations
 569     uint64_t GsInvocations; // Number of Geometry Shader invocations
 570     uint64_t PsInvocations; // Number of Pixel Shader invocations
 571     uint64_t CsInvocations; // Number of Compute Shader invocations
 572     uint64_t CInvocations;  // Number of clipper invocations
 573     uint64_t CPrimitives;   // Number of clipper primitives.
 574     uint64_t GsPrimitives;  // Number of prims GS outputs.
 575
 576     // Streamout Stats
 577     uint32_t SoWriteOffset[4];
 578     uint64_t SoPrimStorageNeeded[4];
 579     uint64_t SoNumPrimsWritten[4];
 580 };
 581
 582 //////////////////////////////////////////////////////////////////////////
 583 /// STREAMOUT_BUFFERS
 584 /////////////////////////////////////////////////////////////////////////
 585
 586 #define MAX_SO_STREAMS 4
 587 #define MAX_ATTRIBUTES 32
 588
 589 struct SWR_STREAMOUT_BUFFER
 590 {
 591     bool enable;
 592
 593     // Pointers to streamout buffers.
 594     uint32_t* pBuffer;
 595
 596     // Size of buffer in dwords.
 597     uint32_t bufferSize;
 598
 599     // Vertex pitch of buffer in dwords.
 600     uint32_t pitch;
 601
 602     // Offset into buffer in dwords. SOS will increment this offset.
 603     uint32_t streamOffset;
 604
 605     // Offset to the SO write offset. If not null then we update offset here.
 606     uint32_t* pWriteOffset;
 607
 608 };
 609
 610 //////////////////////////////////////////////////////////////////////////
 611 /// STREAMOUT_STATE
 612 /////////////////////////////////////////////////////////////////////////
 613 struct SWR_STREAMOUT_STATE
 614 {
 615     // This disables stream output.
 616     bool soEnable;
 617
 618     // which streams are enabled for streamout
 619     bool streamEnable[MAX_SO_STREAMS];
 620
 621     // If set then do not send any streams to the rasterizer.
 622     bool rasterizerDisable;
 623
 624     // Specifies which stream to send to the rasterizer.
 625     uint32_t streamToRasterizer;
 626
 627     // The stream masks specify which attributes are sent to which streams.
 628     // These masks help the FE to setup the pPrimData buffer that is passed
 629     // the the Stream Output Shader (SOS) function.
 630     uint32_t streamMasks[MAX_SO_STREAMS];
 631
 632     // Number of attributes, including position, per vertex that are streamed out.
 633     // This should match number of bits in stream mask.
 634     uint32_t streamNumEntries[MAX_SO_STREAMS];
 635 };
 636
 637 //////////////////////////////////////////////////////////////////////////
 638 /// STREAMOUT_CONTEXT - Passed to SOS
 639 /////////////////////////////////////////////////////////////////////////
 640 struct SWR_STREAMOUT_CONTEXT
 641 {
 642     uint32_t* pPrimData;
 643     SWR_STREAMOUT_BUFFER* pBuffer[MAX_SO_STREAMS];
 644
 645     // Num prims written for this stream
 646     uint32_t numPrimsWritten;
 647
 648     // Num prims that should have been written if there were no overflow.
 649     uint32_t numPrimStorageNeeded;
 650 };
 651
 652 //////////////////////////////////////////////////////////////////////////
 653 /// SWR_GS_STATE - Geometry shader state
 654 /////////////////////////////////////////////////////////////////////////
 655 struct SWR_GS_STATE
 656 {
 657     bool gsEnable;
 658
 659     // number of input attributes per vertex. used by the frontend to
 660     // optimize assembling primitives for GS
 661     uint32_t numInputAttribs;
 662
 663     // output topology - can be point, tristrip, or linestrip
 664     PRIMITIVE_TOPOLOGY outputTopology;      // @llvm_enum
 665
 666     // maximum number of verts that can be emitted by a single instance of the GS
 667     uint32_t maxNumVerts;
 668
 669     // instance count
 670     uint32_t instanceCount;
 671
 672     // geometry shader emits renderTargetArrayIndex
 673     bool emitsRenderTargetArrayIndex;
 674
 675     // geometry shader emits PrimitiveID
 676     bool emitsPrimitiveID;
 677
 678     // if true, geometry shader emits a single stream, with separate cut buffer.
 679     // if false, geometry shader emits vertices for multiple streams to the stream buffer, with a separate StreamID buffer
 680     // to map vertices to streams
 681     bool isSingleStream;
 682
 683     // when single stream is enabled, singleStreamID dictates which stream is being output.
 684     // field ignored if isSingleStream is false
 685     uint32_t singleStreamID;
 686 };
 687
 688
 689 //////////////////////////////////////////////////////////////////////////
 690 /// SWR_TS_OUTPUT_TOPOLOGY - Defines data output by the tessellator / DS
 691 /////////////////////////////////////////////////////////////////////////
 692 enum SWR_TS_OUTPUT_TOPOLOGY
 693 {
 694     SWR_TS_OUTPUT_POINT,
 695     SWR_TS_OUTPUT_LINE,
 696     SWR_TS_OUTPUT_TRI_CW,
 697     SWR_TS_OUTPUT_TRI_CCW,
 698
 699     SWR_TS_OUTPUT_TOPOLOGY_COUNT
 700 };
 701
 702 //////////////////////////////////////////////////////////////////////////
 703 /// SWR_TS_PARTITIONING - Defines tessellation algorithm
 704 /////////////////////////////////////////////////////////////////////////
 705 enum SWR_TS_PARTITIONING
 706 {
 707     SWR_TS_INTEGER,
 708     SWR_TS_ODD_FRACTIONAL,
 709     SWR_TS_EVEN_FRACTIONAL,
 710
 711     SWR_TS_PARTITIONING_COUNT
 712 };
 713
 714 //////////////////////////////////////////////////////////////////////////
 715 /// SWR_TS_DOMAIN - Defines Tessellation Domain
 716 /////////////////////////////////////////////////////////////////////////
 717 enum SWR_TS_DOMAIN
 718 {
 719     SWR_TS_QUAD,
 720     SWR_TS_TRI,
 721     SWR_TS_ISOLINE,
 722
 723     SWR_TS_DOMAIN_COUNT
 724 };
 725
 726 //////////////////////////////////////////////////////////////////////////
 727 /// SWR_TS_STATE - Tessellation state
 728 /////////////////////////////////////////////////////////////////////////
 729 struct SWR_TS_STATE
 730 {
 731     bool                    tsEnable;
 732     SWR_TS_OUTPUT_TOPOLOGY  tsOutputTopology;   // @llvm_enum
 733     SWR_TS_PARTITIONING     partitioning;       // @llvm_enum
 734     SWR_TS_DOMAIN           domain;             // @llvm_enum
 735
 736     PRIMITIVE_TOPOLOGY      postDSTopology;     // @llvm_enum
 737
 738     uint32_t                numHsInputAttribs;
 739     uint32_t                numHsOutputAttribs;
 740     uint32_t                numDsOutputAttribs;
 741 };
 742
 743 // output merger state
 744 struct SWR_RENDER_TARGET_BLEND_STATE
 745 {
 746     uint8_t writeDisableRed : 1;
 747     uint8_t writeDisableGreen : 1;
 748     uint8_t writeDisableBlue : 1;
 749     uint8_t writeDisableAlpha : 1;
 750 };
 751 static_assert(sizeof(SWR_RENDER_TARGET_BLEND_STATE) == 1, "Invalid SWR_RENDER_TARGET_BLEND_STATE size");
 752
 753 enum SWR_MULTISAMPLE_COUNT
 754 {
 755     SWR_MULTISAMPLE_1X = 0,
 756     SWR_MULTISAMPLE_2X,
 757     SWR_MULTISAMPLE_4X,
 758     SWR_MULTISAMPLE_8X,
 759     SWR_MULTISAMPLE_16X,
 760     SWR_MULTISAMPLE_TYPE_MAX
 761 };
 762
 763 struct SWR_BLEND_STATE
 764 {
 765     // constant blend factor color in RGBA float
 766     float constantColor[4];
 767
 768     // alpha test reference value in unorm8 or float32
 769     uint32_t alphaTestReference;
 770     uint32_t sampleMask;
 771     // all RT's have the same sample count
 772     ///@todo move this to Output Merger state when we refactor
 773     SWR_MULTISAMPLE_COUNT sampleCount;  // @llvm_enum
 774
 775     SWR_RENDER_TARGET_BLEND_STATE renderTarget[SWR_NUM_RENDERTARGETS];
 776 };
 777 static_assert(sizeof(SWR_BLEND_STATE) == 36, "Invalid SWR_BLEND_STATE size");
 778
 779 //////////////////////////////////////////////////////////////////////////
 780 /// FUNCTION POINTERS FOR SHADERS
 781
 782 typedef void(__cdecl *PFN_FETCH_FUNC)(SWR_FETCH_CONTEXT& fetchInfo, simdvertex& out);
 783 typedef void(__cdecl *PFN_VERTEX_FUNC)(HANDLE hPrivateData, SWR_VS_CONTEXT* pVsContext);
 784 typedef void(__cdecl *PFN_HS_FUNC)(HANDLE hPrivateData, SWR_HS_CONTEXT* pHsContext);
 785 typedef void(__cdecl *PFN_DS_FUNC)(HANDLE hPrivateData, SWR_DS_CONTEXT* pDsContext);
 786 typedef void(__cdecl *PFN_GS_FUNC)(HANDLE hPrivateData, SWR_GS_CONTEXT* pGsContext);
 787 typedef void(__cdecl *PFN_CS_FUNC)(HANDLE hPrivateData, SWR_CS_CONTEXT* pCsContext);
 788 typedef void(__cdecl *PFN_SO_FUNC)(SWR_STREAMOUT_CONTEXT& soContext);
 789 typedef void(__cdecl *PFN_PIXEL_KERNEL)(HANDLE hPrivateData, SWR_PS_CONTEXT *pContext);
 790 typedef void(__cdecl *PFN_CPIXEL_KERNEL)(HANDLE hPrivateData, SWR_PS_CONTEXT *pContext);
 791 typedef void(__cdecl *PFN_BLEND_JIT_FUNC)(const SWR_BLEND_STATE*, simdvector&, simdvector&, uint32_t, uint8_t*, simdvector&, simdscalari*, simdscalari*);
 792 typedef simdscalar(*PFN_QUANTIZE_DEPTH)(simdscalar);
 793
 794 //////////////////////////////////////////////////////////////////////////
 795 /// FRONTEND_STATE
 796 /////////////////////////////////////////////////////////////////////////
 797 struct SWR_FRONTEND_STATE
 798 {
 799     // skip clip test, perspective divide, and viewport transform
 800     // intended for verts in screen space
 801     bool vpTransformDisable;
 802     bool bEnableCutIndex;
 803     union
 804     {
 805         struct
 806         {
 807             uint32_t triFan : 2;
 808             uint32_t lineStripList : 1;
 809             uint32_t triStripList : 2;
 810         };
 811         uint32_t bits;
 812     } provokingVertex;
 813     uint32_t topologyProvokingVertex; // provoking vertex for the draw topology
 814 };
 815
 816 //////////////////////////////////////////////////////////////////////////
 817 /// VIEWPORT_MATRIX
 818 /////////////////////////////////////////////////////////////////////////
 819 struct SWR_VIEWPORT_MATRIX
 820 {
 821     float m00;
 822     float m11;
 823     float m22;
 824     float m30;
 825     float m31;
 826     float m32;
 827 };
 828
 829 //////////////////////////////////////////////////////////////////////////
 830 /// SWR_VIEWPORT
 831 /////////////////////////////////////////////////////////////////////////
 832 struct SWR_VIEWPORT
 833 {
 834     float x;
 835     float y;
 836     float width;
 837     float height;
 838     float minZ;
 839     float maxZ;
 840 };
 841
 842 //////////////////////////////////////////////////////////////////////////
 843 /// SWR_CULLMODE
 844 //////////////////////////////////////////////////////////////////////////
 845 enum SWR_CULLMODE
 846 {
 847     SWR_CULLMODE_BOTH,
 848     SWR_CULLMODE_NONE,
 849     SWR_CULLMODE_FRONT,
 850     SWR_CULLMODE_BACK
 851 };
 852
 853 enum SWR_FILLMODE
 854 {
 855     SWR_FILLMODE_POINT,
 856     SWR_FILLMODE_WIREFRAME,
 857     SWR_FILLMODE_SOLID
 858 };
 859
 860 enum SWR_FRONTWINDING
 861 {
 862     SWR_FRONTWINDING_CW,
 863     SWR_FRONTWINDING_CCW
 864 };
 865
 866
 867 enum SWR_MSAA_SAMPLE_PATTERN
 868 {
 869     SWR_MSAA_CENTER_PATTERN,
 870     SWR_MSAA_STANDARD_PATTERN,
 871     SWR_MSAA_SAMPLE_PATTERN_MAX
 872 };
 873
 874 enum SWR_PIXEL_LOCATION
 875 {
 876     SWR_PIXEL_LOCATION_CENTER,
 877     SWR_PIXEL_LOCATION_UL,
 878 };
 879
 880 // fixed point screen space sample locations within a pixel
 881 struct SWR_MULTISAMPLE_POS
 882 {
 883     uint32_t x;
 884     uint32_t y;
 885 };
 886
 887 enum SWR_MSAA_RASTMODE
 888 {
 889     SWR_MSAA_RASTMODE_OFF_PIXEL,
 890     SWR_MSAA_RASTMODE_OFF_PATTERN,
 891     SWR_MSAA_RASTMODE_ON_PIXEL,
 892     SWR_MSAA_RASTMODE_ON_PATTERN
 893 };
 894
 895 //////////////////////////////////////////////////////////////////////////
 896 /// SWR_RASTSTATE
 897 //////////////////////////////////////////////////////////////////////////
 898 struct SWR_RASTSTATE
 899 {
 900     uint32_t cullMode               : 2;
 901     uint32_t fillMode               : 2;
 902     uint32_t frontWinding           : 1;
 903     uint32_t scissorEnable          : 1;
 904     uint32_t depthClipEnable        : 1;
 905     uint32_t pointParam             : 1;
 906     uint32_t pointSpriteEnable      : 1;
 907     uint32_t pointSpriteTopOrigin   : 1;
 908     uint32_t msaaRastEnable         : 1;
 909     uint32_t forcedSampleCount      : 1;
 910     uint32_t pixelOffset            : 1;
 911     uint32_t depthBiasPreAdjusted   : 1;    ///< depth bias constant is in float units, not per-format Z units
 912
 913     float pointSize;
 914     float lineWidth;
 915
 916     float depthBias;
 917     float slopeScaledDepthBias;
 918     float depthBiasClamp;
 919     SWR_FORMAT depthFormat;     // @llvm_enum
 920
 921     ///@todo: MSAA lines
 922     // multisample state for MSAA lines
 923     SWR_MSAA_RASTMODE rastMode;    // @llvm_enum
 924
 925     // sample count the rasterizer is running at
 926     SWR_MULTISAMPLE_COUNT sampleCount;  // @llvm_enum
 927     uint32_t pixelLocation;     // UL or Center
 928     SWR_MULTISAMPLE_POS iSamplePos[SWR_MAX_NUM_MULTISAMPLES];
 929     SWR_MSAA_SAMPLE_PATTERN samplePattern;   // @llvm_enum
 930
 931     // user clip/cull distance enables
 932     uint8_t cullDistanceMask;
 933     uint8_t clipDistanceMask;
 934 };
 935
 936 // backend state
 937 struct SWR_BACKEND_STATE
 938 {
 939     uint32_t constantInterpolationMask;
 940     uint32_t pointSpriteTexCoordMask;
 941     uint8_t numAttributes;
 942     uint8_t numComponents[KNOB_NUM_ATTRIBUTES];
 943 };
 944
 945
 946 union SWR_DEPTH_STENCIL_STATE
 947 {
 948     struct
 949     {
 950         // dword 0
 951         uint32_t depthWriteEnable : 1;
 952         uint32_t depthTestEnable : 1;
 953         uint32_t stencilWriteEnable : 1;
 954         uint32_t stencilTestEnable : 1;
 955         uint32_t doubleSidedStencilTestEnable : 1;
 956
 957         uint32_t depthTestFunc : 3;
 958         uint32_t stencilTestFunc : 3;
 959
 960         uint32_t backfaceStencilPassDepthPassOp : 3;
 961         uint32_t backfaceStencilPassDepthFailOp : 3;
 962         uint32_t backfaceStencilFailOp : 3;
 963         uint32_t backfaceStencilTestFunc : 3;
 964         uint32_t stencilPassDepthPassOp : 3;
 965         uint32_t stencilPassDepthFailOp : 3;
 966         uint32_t stencilFailOp : 3;
 967
 968         // dword 1
 969         uint8_t backfaceStencilWriteMask;
 970         uint8_t backfaceStencilTestMask;
 971         uint8_t stencilWriteMask;
 972         uint8_t stencilTestMask;
 973
 974         // dword 2
 975         uint8_t backfaceStencilRefValue;
 976         uint8_t stencilRefValue;
 977     };
 978     uint32_t value[3];
 979 };
 980
 981 enum SWR_SHADING_RATE
 982 {
 983     SWR_SHADING_RATE_PIXEL,
 984     SWR_SHADING_RATE_SAMPLE,
 985     SWR_SHADING_RATE_MAX,
 986 };
 987
 988 enum SWR_INPUT_COVERAGE
 989 {
 990     SWR_INPUT_COVERAGE_NONE,
 991     SWR_INPUT_COVERAGE_NORMAL,
 992     SWR_INPUT_COVERAGE_MAX,
 993 };
 994
 995 enum SWR_PS_POSITION_OFFSET
 996 {
 997     SWR_PS_POSITION_SAMPLE_NONE,
 998     SWR_PS_POSITION_SAMPLE_OFFSET,
 999     SWR_PS_POSITION_CENTROID_OFFSET,
1000     SWR_PS_POSITION_OFFSET_MAX,
1001 };
1002
1003 enum SWR_BARYCENTRICS_MASK
1004 {
1005     SWR_BARYCENTRIC_PER_PIXEL_MASK = 0x1,
1006     SWR_BARYCENTRIC_CENTROID_MASK = 0x2,
1007     SWR_BARYCENTRIC_PER_SAMPLE_MASK = 0x4,
1008     SWR_BARYCENTRICS_MASK_MAX = 0x8
1009 };
1010
1011 // pixel shader state
1012 struct SWR_PS_STATE
1013 {
1014     // dword 0-1
1015     PFN_PIXEL_KERNEL pfnPixelShader;  // @llvm_pfn
1016
1017     // dword 2
1018     uint32_t killsPixel         : 1;    // pixel shader can kill pixels
1019     uint32_t inputCoverage      : 1;    // type of input coverage PS uses
1020     uint32_t writesODepth       : 1;    // pixel shader writes to depth
1021     uint32_t usesSourceDepth    : 1;    // pixel shader reads depth
1022     uint32_t shadingRate        : 2;    // shading per pixel / sample / coarse pixel
1023     uint32_t numRenderTargets   : 4;    // number of render target outputs in use (0-8)
1024     uint32_t posOffset          : 2;    // type of offset (none, sample, centroid) to add to pixel position
1025     uint32_t barycentricsMask   : 3;    // which type(s) of barycentric coords does the PS interpolate attributes with
1026     uint32_t usesUAV            : 1;    // pixel shader accesses UAV
1027     uint32_t forceEarlyZ        : 1;    // force execution of early depth/stencil test
1028
1029 };