1 /****************************************************************************
2 * Copyright (C) 2015 Intel Corporation. All Rights Reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 ***************************************************************************/
24 #include "swr_screen.h"
25 #include "swr_context.h"
26 #include "swr_resource.h"
27 #include "swr_fence.h"
28 #include "swr_query.h"
31 #include "util/u_draw.h"
32 #include "util/u_prim.h"
35 * Convert mesa PIPE_PRIM_X to SWR enum PRIMITIVE_TOPOLOGY
37 static INLINE
enum PRIMITIVE_TOPOLOGY
38 swr_convert_prim_topology(const unsigned mode
)
41 case PIPE_PRIM_POINTS
:
42 return TOP_POINT_LIST
;
45 case PIPE_PRIM_LINE_LOOP
:
47 case PIPE_PRIM_LINE_STRIP
:
48 return TOP_LINE_STRIP
;
49 case PIPE_PRIM_TRIANGLES
:
50 return TOP_TRIANGLE_LIST
;
51 case PIPE_PRIM_TRIANGLE_STRIP
:
52 return TOP_TRIANGLE_STRIP
;
53 case PIPE_PRIM_TRIANGLE_FAN
:
54 return TOP_TRIANGLE_FAN
;
57 case PIPE_PRIM_QUAD_STRIP
:
58 return TOP_QUAD_STRIP
;
59 case PIPE_PRIM_POLYGON
:
60 return TOP_TRIANGLE_FAN
; /* XXX TOP_POLYGON; */
61 case PIPE_PRIM_LINES_ADJACENCY
:
62 return TOP_LINE_LIST_ADJ
;
63 case PIPE_PRIM_LINE_STRIP_ADJACENCY
:
64 return TOP_LISTSTRIP_ADJ
;
65 case PIPE_PRIM_TRIANGLES_ADJACENCY
:
66 return TOP_TRI_LIST_ADJ
;
67 case PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
:
68 return TOP_TRI_STRIP_ADJ
;
70 assert(0 && "Unknown topology");
77 * Draw vertex arrays, with optional indexing, optional instancing.
80 swr_draw_vbo(struct pipe_context
*pipe
, const struct pipe_draw_info
*info
)
82 struct swr_context
*ctx
= swr_context(pipe
);
84 if (!swr_check_render_cond(pipe
))
88 util_draw_indirect(pipe
, info
);
92 /* Update derived state, pass draw info to update function */
94 swr_update_derived(pipe
, info
);
96 swr_update_draw_context(ctx
);
98 if (ctx
->vs
->pipe
.stream_output
.num_outputs
) {
99 if (!ctx
->vs
->soFunc
[info
->mode
]) {
100 STREAMOUT_COMPILE_STATE state
= {0};
101 struct pipe_stream_output_info
*so
= &ctx
->vs
->pipe
.stream_output
;
103 state
.numVertsPerPrim
= u_vertices_per_prim(info
->mode
);
105 uint32_t offsets
[MAX_SO_STREAMS
] = {0};
108 for (uint32_t i
= 0; i
< so
->num_outputs
; i
++) {
109 assert(so
->output
[i
].stream
== 0); // @todo
110 uint32_t output_buffer
= so
->output
[i
].output_buffer
;
111 if (so
->output
[i
].dst_offset
!= offsets
[output_buffer
]) {
112 // hole - need to fill
113 state
.stream
.decl
[num
].bufferIndex
= output_buffer
;
114 state
.stream
.decl
[num
].hole
= true;
115 state
.stream
.decl
[num
].componentMask
=
116 (1 << (so
->output
[i
].dst_offset
- offsets
[output_buffer
]))
119 offsets
[output_buffer
] = so
->output
[i
].dst_offset
;
122 state
.stream
.decl
[num
].bufferIndex
= output_buffer
;
123 state
.stream
.decl
[num
].attribSlot
= so
->output
[i
].register_index
- 1;
124 state
.stream
.decl
[num
].componentMask
=
125 ((1 << so
->output
[i
].num_components
) - 1)
126 << so
->output
[i
].start_component
;
127 state
.stream
.decl
[num
].hole
= false;
130 offsets
[output_buffer
] += so
->output
[i
].num_components
;
133 state
.stream
.numDecls
= num
;
135 HANDLE hJitMgr
= swr_screen(pipe
->screen
)->hJitMgr
;
136 ctx
->vs
->soFunc
[info
->mode
] = JitCompileStreamout(hJitMgr
, state
);
137 debug_printf("so shader %p\n", ctx
->vs
->soFunc
[info
->mode
]);
138 assert(ctx
->vs
->soFunc
[info
->mode
] && "Error: SoShader = NULL");
141 SwrSetSoFunc(ctx
->swrContext
, ctx
->vs
->soFunc
[info
->mode
], 0);
144 struct swr_vertex_element_state
*velems
= ctx
->velems
;
146 || (velems
->fsState
.cutIndex
!= info
->restart_index
)
147 || (velems
->fsState
.bEnableCutIndex
!= info
->primitive_restart
)) {
149 velems
->fsState
.cutIndex
= info
->restart_index
;
150 velems
->fsState
.bEnableCutIndex
= info
->primitive_restart
;
152 /* Create Fetch Shader */
153 HANDLE hJitMgr
= swr_screen(ctx
->pipe
.screen
)->hJitMgr
;
154 velems
->fsFunc
= JitCompileFetch(hJitMgr
, velems
->fsState
);
156 debug_printf("fetch shader %p\n", velems
->fsFunc
);
157 assert(velems
->fsFunc
&& "Error: FetchShader = NULL");
160 SwrSetFetchFunc(ctx
->swrContext
, velems
->fsFunc
);
162 /* Set up frontend state
163 * XXX setup provokingVertex & topologyProvokingVertex */
164 SWR_FRONTEND_STATE feState
= {0};
165 if (ctx
->rasterizer
->flatshade_first
) {
166 feState
.provokingVertex
= {1, 0, 0};
168 feState
.provokingVertex
= {2, 1, 2};
171 switch (info
->mode
) {
172 case PIPE_PRIM_TRIANGLE_FAN
:
173 feState
.topologyProvokingVertex
= feState
.provokingVertex
.triFan
;
175 case PIPE_PRIM_TRIANGLE_STRIP
:
176 case PIPE_PRIM_TRIANGLES
:
177 feState
.topologyProvokingVertex
= feState
.provokingVertex
.triStripList
;
179 case PIPE_PRIM_QUAD_STRIP
:
180 case PIPE_PRIM_QUADS
:
181 if (ctx
->rasterizer
->flatshade_first
)
182 feState
.topologyProvokingVertex
= 0;
184 feState
.topologyProvokingVertex
= 3;
186 case PIPE_PRIM_LINES
:
187 case PIPE_PRIM_LINE_LOOP
:
188 case PIPE_PRIM_LINE_STRIP
:
189 feState
.topologyProvokingVertex
= feState
.provokingVertex
.lineStripList
;
192 feState
.topologyProvokingVertex
= 0;
195 feState
.bEnableCutIndex
= info
->primitive_restart
;
196 SwrSetFrontendState(ctx
->swrContext
, &feState
);
199 SwrDrawIndexedInstanced(ctx
->swrContext
,
200 swr_convert_prim_topology(info
->mode
),
202 info
->instance_count
,
205 info
->start_instance
);
207 SwrDrawInstanced(ctx
->swrContext
,
208 swr_convert_prim_topology(info
->mode
),
210 info
->instance_count
,
212 info
->start_instance
);
217 swr_flush(struct pipe_context
*pipe
,
218 struct pipe_fence_handle
**fence
,
221 struct swr_context
*ctx
= swr_context(pipe
);
222 struct swr_screen
*screen
= swr_screen(pipe
->screen
);
223 struct pipe_surface
*cb
= ctx
->framebuffer
.cbufs
[0];
225 /* If the current renderTarget is the display surface, store tiles back to
226 * the surface, in preparation for present (swr_flush_frontbuffer).
227 * Other renderTargets get stored back when attachment changes or
228 * swr_surface_destroy */
229 if (cb
&& swr_resource(cb
->texture
)->display_target
)
230 swr_store_dirty_resource(pipe
, cb
->texture
, SWR_TILE_RESOLVED
);
233 swr_fence_reference(pipe
->screen
, fence
, screen
->flush_fence
);
237 swr_finish(struct pipe_context
*pipe
)
239 struct pipe_fence_handle
*fence
= nullptr;
241 swr_flush(pipe
, &fence
, 0);
242 swr_fence_finish(pipe
->screen
, NULL
, fence
, 0);
243 swr_fence_reference(pipe
->screen
, &fence
, NULL
);
248 * Store SWR HotTiles back to renderTarget surface.
251 swr_store_render_target(struct pipe_context
*pipe
,
253 enum SWR_TILE_STATE post_tile_state
)
255 struct swr_context
*ctx
= swr_context(pipe
);
256 struct swr_draw_context
*pDC
= &ctx
->swrDC
;
257 struct SWR_SURFACE_STATE
*renderTarget
= &pDC
->renderTargets
[attachment
];
259 /* Only proceed if there's a valid surface to store to */
260 if (renderTarget
->pBaseAddress
) {
261 swr_update_draw_context(ctx
);
263 {0, 0, (int32_t)renderTarget
->width
, (int32_t)renderTarget
->height
};
264 SwrStoreTiles(ctx
->swrContext
,
272 swr_store_dirty_resource(struct pipe_context
*pipe
,
273 struct pipe_resource
*resource
,
274 enum SWR_TILE_STATE post_tile_state
)
276 /* Only store resource if it has been written to */
277 if (swr_resource(resource
)->status
& SWR_RESOURCE_WRITE
) {
278 struct swr_context
*ctx
= swr_context(pipe
);
279 struct swr_screen
*screen
= swr_screen(pipe
->screen
);
280 struct swr_resource
*spr
= swr_resource(resource
);
282 swr_draw_context
*pDC
= &ctx
->swrDC
;
283 SWR_SURFACE_STATE
*renderTargets
= pDC
->renderTargets
;
284 for (uint32_t i
= 0; i
< SWR_NUM_ATTACHMENTS
; i
++)
285 if (renderTargets
[i
].pBaseAddress
== spr
->swr
.pBaseAddress
) {
286 swr_store_render_target(pipe
, i
, post_tile_state
);
288 /* Mesa thinks depth/stencil are fused, so we'll never get an
289 * explicit resource for stencil. So, if checking depth, then
290 * also check for stencil. */
291 if (spr
->has_stencil
&& (i
== SWR_ATTACHMENT_DEPTH
)) {
292 swr_store_render_target(
293 pipe
, SWR_ATTACHMENT_STENCIL
, post_tile_state
);
296 /* This fence signals StoreTiles completion */
297 swr_fence_submit(ctx
, screen
->flush_fence
);
305 swr_draw_init(struct pipe_context
*pipe
)
307 pipe
->draw_vbo
= swr_draw_vbo
;
308 pipe
->flush
= swr_flush
;