1 /****************************************************************************
2 * Copyright (C) 2015 Intel Corporation. All Rights Reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 ***************************************************************************/
24 #include "swr_screen.h"
25 #include "swr_context.h"
26 #include "swr_resource.h"
27 #include "swr_fence.h"
28 #include "swr_query.h"
31 #include "util/u_draw.h"
32 #include "util/u_prim.h"
35 * Draw vertex arrays, with optional indexing, optional instancing.
38 swr_draw_vbo(struct pipe_context
*pipe
, const struct pipe_draw_info
*info
)
40 struct swr_context
*ctx
= swr_context(pipe
);
42 if (!swr_check_render_cond(pipe
))
46 util_draw_indirect(pipe
, info
);
50 /* Update derived state, pass draw info to update function */
51 swr_update_derived(pipe
, info
);
53 swr_update_draw_context(ctx
);
55 if (ctx
->vs
->pipe
.stream_output
.num_outputs
) {
56 if (!ctx
->vs
->soFunc
[info
->mode
]) {
57 STREAMOUT_COMPILE_STATE state
= {0};
58 struct pipe_stream_output_info
*so
= &ctx
->vs
->pipe
.stream_output
;
60 state
.numVertsPerPrim
= u_vertices_per_prim(info
->mode
);
62 uint32_t offsets
[MAX_SO_STREAMS
] = {0};
65 for (uint32_t i
= 0; i
< so
->num_outputs
; i
++) {
66 assert(so
->output
[i
].stream
== 0); // @todo
67 uint32_t output_buffer
= so
->output
[i
].output_buffer
;
68 if (so
->output
[i
].dst_offset
!= offsets
[output_buffer
]) {
69 // hole - need to fill
70 state
.stream
.decl
[num
].bufferIndex
= output_buffer
;
71 state
.stream
.decl
[num
].hole
= true;
72 state
.stream
.decl
[num
].componentMask
=
73 (1 << (so
->output
[i
].dst_offset
- offsets
[output_buffer
]))
76 offsets
[output_buffer
] = so
->output
[i
].dst_offset
;
79 state
.stream
.decl
[num
].bufferIndex
= output_buffer
;
80 state
.stream
.decl
[num
].attribSlot
= so
->output
[i
].register_index
- 1;
81 state
.stream
.decl
[num
].componentMask
=
82 ((1 << so
->output
[i
].num_components
) - 1)
83 << so
->output
[i
].start_component
;
84 state
.stream
.decl
[num
].hole
= false;
87 offsets
[output_buffer
] += so
->output
[i
].num_components
;
90 state
.stream
.numDecls
= num
;
92 HANDLE hJitMgr
= swr_screen(pipe
->screen
)->hJitMgr
;
93 ctx
->vs
->soFunc
[info
->mode
] = JitCompileStreamout(hJitMgr
, state
);
94 debug_printf("so shader %p\n", ctx
->vs
->soFunc
[info
->mode
]);
95 assert(ctx
->vs
->soFunc
[info
->mode
] && "Error: SoShader = NULL");
98 SwrSetSoFunc(ctx
->swrContext
, ctx
->vs
->soFunc
[info
->mode
], 0);
101 struct swr_vertex_element_state
*velems
= ctx
->velems
;
102 velems
->fsState
.cutIndex
= info
->restart_index
;
103 velems
->fsState
.bEnableCutIndex
= info
->primitive_restart
;
104 velems
->fsState
.bPartialVertexBuffer
= (info
->min_index
> 0);
106 swr_jit_fetch_key key
;
107 swr_generate_fetch_key(key
, velems
);
108 auto search
= velems
->map
.find(key
);
109 if (search
!= velems
->map
.end()) {
110 velems
->fsFunc
= search
->second
;
112 HANDLE hJitMgr
= swr_screen(ctx
->pipe
.screen
)->hJitMgr
;
113 velems
->fsFunc
= JitCompileFetch(hJitMgr
, velems
->fsState
);
115 debug_printf("fetch shader %p\n", velems
->fsFunc
);
116 assert(velems
->fsFunc
&& "Error: FetchShader = NULL");
118 velems
->map
.insert(std::make_pair(key
, velems
->fsFunc
));
121 SwrSetFetchFunc(ctx
->swrContext
, velems
->fsFunc
);
123 /* Set up frontend state
124 * XXX setup provokingVertex & topologyProvokingVertex */
125 SWR_FRONTEND_STATE feState
= {0};
126 if (ctx
->rasterizer
->flatshade_first
) {
127 feState
.provokingVertex
= {1, 0, 0};
129 feState
.provokingVertex
= {2, 1, 2};
132 enum pipe_prim_type topology
;
134 topology
= (pipe_prim_type
)ctx
->gs
->info
.base
.properties
[TGSI_PROPERTY_GS_OUTPUT_PRIM
];
136 topology
= info
->mode
;
139 case PIPE_PRIM_TRIANGLE_FAN
:
140 feState
.topologyProvokingVertex
= feState
.provokingVertex
.triFan
;
142 case PIPE_PRIM_TRIANGLE_STRIP
:
143 case PIPE_PRIM_TRIANGLES
:
144 feState
.topologyProvokingVertex
= feState
.provokingVertex
.triStripList
;
146 case PIPE_PRIM_QUAD_STRIP
:
147 case PIPE_PRIM_QUADS
:
148 if (ctx
->rasterizer
->flatshade_first
)
149 feState
.topologyProvokingVertex
= 0;
151 feState
.topologyProvokingVertex
= 3;
153 case PIPE_PRIM_LINES
:
154 case PIPE_PRIM_LINE_LOOP
:
155 case PIPE_PRIM_LINE_STRIP
:
156 feState
.topologyProvokingVertex
= feState
.provokingVertex
.lineStripList
;
159 feState
.topologyProvokingVertex
= 0;
162 feState
.bEnableCutIndex
= info
->primitive_restart
;
163 SwrSetFrontendState(ctx
->swrContext
, &feState
);
166 SwrDrawIndexedInstanced(ctx
->swrContext
,
167 swr_convert_prim_topology(info
->mode
),
169 info
->instance_count
,
172 info
->start_instance
);
174 SwrDrawInstanced(ctx
->swrContext
,
175 swr_convert_prim_topology(info
->mode
),
177 info
->instance_count
,
179 info
->start_instance
);
184 swr_flush(struct pipe_context
*pipe
,
185 struct pipe_fence_handle
**fence
,
188 struct swr_context
*ctx
= swr_context(pipe
);
189 struct swr_screen
*screen
= swr_screen(pipe
->screen
);
190 struct pipe_surface
*cb
= ctx
->framebuffer
.cbufs
[0];
192 /* If the current renderTarget is the display surface, store tiles back to
193 * the surface, in preparation for present (swr_flush_frontbuffer).
194 * Other renderTargets get stored back when attachment changes or
195 * swr_surface_destroy */
196 if (cb
&& swr_resource(cb
->texture
)->display_target
)
197 swr_store_dirty_resource(pipe
, cb
->texture
, SWR_TILE_RESOLVED
);
200 swr_fence_reference(pipe
->screen
, fence
, screen
->flush_fence
);
204 swr_finish(struct pipe_context
*pipe
)
206 struct pipe_fence_handle
*fence
= nullptr;
208 swr_flush(pipe
, &fence
, 0);
209 swr_fence_finish(pipe
->screen
, NULL
, fence
, 0);
210 swr_fence_reference(pipe
->screen
, &fence
, NULL
);
215 * Store SWR HotTiles back to renderTarget surface.
218 swr_store_render_target(struct pipe_context
*pipe
,
220 enum SWR_TILE_STATE post_tile_state
)
222 struct swr_context
*ctx
= swr_context(pipe
);
223 struct swr_draw_context
*pDC
= &ctx
->swrDC
;
224 struct SWR_SURFACE_STATE
*renderTarget
= &pDC
->renderTargets
[attachment
];
226 /* Only proceed if there's a valid surface to store to */
227 if (renderTarget
->pBaseAddress
) {
228 swr_update_draw_context(ctx
);
231 (int32_t)u_minify(renderTarget
->width
, renderTarget
->lod
),
232 (int32_t)u_minify(renderTarget
->height
, renderTarget
->lod
)};
233 SwrStoreTiles(ctx
->swrContext
,
241 swr_store_dirty_resource(struct pipe_context
*pipe
,
242 struct pipe_resource
*resource
,
243 enum SWR_TILE_STATE post_tile_state
)
245 /* Only store resource if it has been written to */
246 if (swr_resource(resource
)->status
& SWR_RESOURCE_WRITE
) {
247 struct swr_context
*ctx
= swr_context(pipe
);
248 struct swr_screen
*screen
= swr_screen(pipe
->screen
);
249 struct swr_resource
*spr
= swr_resource(resource
);
251 swr_draw_context
*pDC
= &ctx
->swrDC
;
252 SWR_SURFACE_STATE
*renderTargets
= pDC
->renderTargets
;
253 for (uint32_t i
= 0; i
< SWR_NUM_ATTACHMENTS
; i
++)
254 if (renderTargets
[i
].pBaseAddress
== spr
->swr
.pBaseAddress
||
255 (spr
->secondary
.pBaseAddress
&&
256 renderTargets
[i
].pBaseAddress
== spr
->secondary
.pBaseAddress
)) {
257 swr_store_render_target(pipe
, i
, post_tile_state
);
259 /* Mesa thinks depth/stencil are fused, so we'll never get an
260 * explicit resource for stencil. So, if checking depth, then
261 * also check for stencil. */
262 if (spr
->has_stencil
&& (i
== SWR_ATTACHMENT_DEPTH
)) {
263 swr_store_render_target(
264 pipe
, SWR_ATTACHMENT_STENCIL
, post_tile_state
);
267 /* This fence signals StoreTiles completion */
268 swr_fence_submit(ctx
, screen
->flush_fence
);
276 swr_draw_init(struct pipe_context
*pipe
)
278 pipe
->draw_vbo
= swr_draw_vbo
;
279 pipe
->flush
= swr_flush
;