src/gallium/drivers/swr/swr_draw.cpp

   1 /****************************************************************************
   2  * Copyright (C) 2015 Intel Corporation.   All Rights Reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  ***************************************************************************/
  23
  24 #include "swr_screen.h"
  25 #include "swr_context.h"
  26 #include "swr_resource.h"
  27 #include "swr_fence.h"
  28 #include "swr_query.h"
  29 #include "jit_api.h"
  30
  31 #include "util/u_draw.h"
  32 #include "util/u_prim.h"
  33
  34 /*
  35  * Convert mesa PIPE_PRIM_X to SWR enum PRIMITIVE_TOPOLOGY
  36  */
  37 static INLINE enum PRIMITIVE_TOPOLOGY
  38 swr_convert_prim_topology(const unsigned mode)
  39 {
  40    switch (mode) {
  41    case PIPE_PRIM_POINTS:
  42       return TOP_POINT_LIST;
  43    case PIPE_PRIM_LINES:
  44       return TOP_LINE_LIST;
  45    case PIPE_PRIM_LINE_LOOP:
  46       return TOP_LINE_LOOP;
  47    case PIPE_PRIM_LINE_STRIP:
  48       return TOP_LINE_STRIP;
  49    case PIPE_PRIM_TRIANGLES:
  50       return TOP_TRIANGLE_LIST;
  51    case PIPE_PRIM_TRIANGLE_STRIP:
  52       return TOP_TRIANGLE_STRIP;
  53    case PIPE_PRIM_TRIANGLE_FAN:
  54       return TOP_TRIANGLE_FAN;
  55    case PIPE_PRIM_QUADS:
  56       return TOP_QUAD_LIST;
  57    case PIPE_PRIM_QUAD_STRIP:
  58       return TOP_QUAD_STRIP;
  59    case PIPE_PRIM_POLYGON:
  60       return TOP_TRIANGLE_FAN; /* XXX TOP_POLYGON; */
  61    case PIPE_PRIM_LINES_ADJACENCY:
  62       return TOP_LINE_LIST_ADJ;
  63    case PIPE_PRIM_LINE_STRIP_ADJACENCY:
  64       return TOP_LISTSTRIP_ADJ;
  65    case PIPE_PRIM_TRIANGLES_ADJACENCY:
  66       return TOP_TRI_LIST_ADJ;
  67    case PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY:
  68       return TOP_TRI_STRIP_ADJ;
  69    default:
  70       assert(0 && "Unknown topology");
  71       return TOP_UNKNOWN;
  72    }
  73 };
  74
  75
  76 /*
  77  * Draw vertex arrays, with optional indexing, optional instancing.
  78  */
  79 static void
  80 swr_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
  81 {
  82    struct swr_context *ctx = swr_context(pipe);
  83
  84    if (!swr_check_render_cond(pipe))
  85       return;
  86
  87    if (info->indirect) {
  88       util_draw_indirect(pipe, info);
  89       return;
  90    }
  91
  92    /* Update derived state, pass draw info to update function */
  93    swr_update_derived(pipe, info);
  94
  95    swr_update_draw_context(ctx);
  96
  97    if (ctx->vs->pipe.stream_output.num_outputs) {
  98       if (!ctx->vs->soFunc[info->mode]) {
  99          STREAMOUT_COMPILE_STATE state = {0};
 100          struct pipe_stream_output_info *so = &ctx->vs->pipe.stream_output;
 101
 102          state.numVertsPerPrim = u_vertices_per_prim(info->mode);
 103
 104          uint32_t offsets[MAX_SO_STREAMS] = {0};
 105          uint32_t num = 0;
 106
 107          for (uint32_t i = 0; i < so->num_outputs; i++) {
 108             assert(so->output[i].stream == 0); // @todo
 109             uint32_t output_buffer = so->output[i].output_buffer;
 110             if (so->output[i].dst_offset != offsets[output_buffer]) {
 111                // hole - need to fill
 112                state.stream.decl[num].bufferIndex = output_buffer;
 113                state.stream.decl[num].hole = true;
 114                state.stream.decl[num].componentMask =
 115                   (1 << (so->output[i].dst_offset - offsets[output_buffer]))
 116                   - 1;
 117                num++;
 118                offsets[output_buffer] = so->output[i].dst_offset;
 119             }
 120
 121             state.stream.decl[num].bufferIndex = output_buffer;
 122             state.stream.decl[num].attribSlot = so->output[i].register_index - 1;
 123             state.stream.decl[num].componentMask =
 124                ((1 << so->output[i].num_components) - 1)
 125                << so->output[i].start_component;
 126             state.stream.decl[num].hole = false;
 127             num++;
 128
 129             offsets[output_buffer] += so->output[i].num_components;
 130          }
 131
 132          state.stream.numDecls = num;
 133
 134          HANDLE hJitMgr = swr_screen(pipe->screen)->hJitMgr;
 135          ctx->vs->soFunc[info->mode] = JitCompileStreamout(hJitMgr, state);
 136          debug_printf("so shader    %p\n", ctx->vs->soFunc[info->mode]);
 137          assert(ctx->vs->soFunc[info->mode] && "Error: SoShader = NULL");
 138       }
 139
 140       SwrSetSoFunc(ctx->swrContext, ctx->vs->soFunc[info->mode], 0);
 141    }
 142
 143    struct swr_vertex_element_state *velems = ctx->velems;
 144    if (!velems->fsFunc
 145        || (velems->fsState.cutIndex != info->restart_index)
 146        || (velems->fsState.bEnableCutIndex != info->primitive_restart)) {
 147
 148       velems->fsState.cutIndex = info->restart_index;
 149       velems->fsState.bEnableCutIndex = info->primitive_restart;
 150
 151       /* Create Fetch Shader */
 152       HANDLE hJitMgr = swr_screen(ctx->pipe.screen)->hJitMgr;
 153       velems->fsFunc = JitCompileFetch(hJitMgr, velems->fsState);
 154
 155       debug_printf("fetch shader %p\n", velems->fsFunc);
 156       assert(velems->fsFunc && "Error: FetchShader = NULL");
 157    }
 158
 159    SwrSetFetchFunc(ctx->swrContext, velems->fsFunc);
 160
 161    /* Set up frontend state
 162     * XXX setup provokingVertex & topologyProvokingVertex */
 163    SWR_FRONTEND_STATE feState = {0};
 164    if (ctx->rasterizer->flatshade_first) {
 165       feState.provokingVertex = {1, 0, 0};
 166    } else {
 167       feState.provokingVertex = {2, 1, 2};
 168    }
 169
 170    switch (info->mode) {
 171    case PIPE_PRIM_TRIANGLE_FAN:
 172       feState.topologyProvokingVertex = feState.provokingVertex.triFan;
 173       break;
 174    case PIPE_PRIM_TRIANGLE_STRIP:
 175    case PIPE_PRIM_TRIANGLES:
 176       feState.topologyProvokingVertex = feState.provokingVertex.triStripList;
 177       break;
 178    case PIPE_PRIM_QUAD_STRIP:
 179    case PIPE_PRIM_QUADS:
 180       if (ctx->rasterizer->flatshade_first)
 181          feState.topologyProvokingVertex = 0;
 182       else
 183          feState.topologyProvokingVertex = 3;
 184       break;
 185    case PIPE_PRIM_LINES:
 186    case PIPE_PRIM_LINE_LOOP:
 187    case PIPE_PRIM_LINE_STRIP:
 188       feState.topologyProvokingVertex = feState.provokingVertex.lineStripList;
 189       break;
 190    default:
 191       feState.topologyProvokingVertex = 0;
 192    }
 193
 194    feState.bEnableCutIndex = info->primitive_restart;
 195    SwrSetFrontendState(ctx->swrContext, &feState);
 196
 197    if (info->indexed)
 198       SwrDrawIndexedInstanced(ctx->swrContext,
 199                               swr_convert_prim_topology(info->mode),
 200                               info->count,
 201                               info->instance_count,
 202                               info->start,
 203                               info->index_bias,
 204                               info->start_instance);
 205    else
 206       SwrDrawInstanced(ctx->swrContext,
 207                        swr_convert_prim_topology(info->mode),
 208                        info->count,
 209                        info->instance_count,
 210                        info->start,
 211                        info->start_instance);
 212 }
 213
 214
 215 static void
 216 swr_flush(struct pipe_context *pipe,
 217           struct pipe_fence_handle **fence,
 218           unsigned flags)
 219 {
 220    struct swr_context *ctx = swr_context(pipe);
 221    struct swr_screen *screen = swr_screen(pipe->screen);
 222    struct pipe_surface *cb = ctx->framebuffer.cbufs[0];
 223
 224    /* If the current renderTarget is the display surface, store tiles back to
 225     * the surface, in preparation for present (swr_flush_frontbuffer).
 226     * Other renderTargets get stored back when attachment changes or
 227     * swr_surface_destroy */
 228    if (cb && swr_resource(cb->texture)->display_target)
 229       swr_store_dirty_resource(pipe, cb->texture, SWR_TILE_RESOLVED);
 230
 231    if (fence)
 232       swr_fence_reference(pipe->screen, fence, screen->flush_fence);
 233 }
 234
 235 void
 236 swr_finish(struct pipe_context *pipe)
 237 {
 238    struct pipe_fence_handle *fence = nullptr;
 239
 240    swr_flush(pipe, &fence, 0);
 241    swr_fence_finish(pipe->screen, NULL, fence, 0);
 242    swr_fence_reference(pipe->screen, &fence, NULL);
 243 }
 244
 245
 246 /*
 247  * Store SWR HotTiles back to renderTarget surface.
 248  */
 249 void
 250 swr_store_render_target(struct pipe_context *pipe,
 251                         uint32_t attachment,
 252                         enum SWR_TILE_STATE post_tile_state)
 253 {
 254    struct swr_context *ctx = swr_context(pipe);
 255    struct swr_draw_context *pDC = &ctx->swrDC;
 256    struct SWR_SURFACE_STATE *renderTarget = &pDC->renderTargets[attachment];
 257
 258    /* Only proceed if there's a valid surface to store to */
 259    if (renderTarget->pBaseAddress) {
 260       swr_update_draw_context(ctx);
 261       SWR_RECT full_rect =
 262          {0, 0, (int32_t)renderTarget->width, (int32_t)renderTarget->height};
 263       SwrStoreTiles(ctx->swrContext,
 264                     1 << attachment,
 265                     post_tile_state,
 266                     full_rect);
 267    }
 268 }
 269
 270 void
 271 swr_store_dirty_resource(struct pipe_context *pipe,
 272                          struct pipe_resource *resource,
 273                          enum SWR_TILE_STATE post_tile_state)
 274 {
 275    /* Only store resource if it has been written to */
 276    if (swr_resource(resource)->status & SWR_RESOURCE_WRITE) {
 277       struct swr_context *ctx = swr_context(pipe);
 278       struct swr_screen *screen = swr_screen(pipe->screen);
 279       struct swr_resource *spr = swr_resource(resource);
 280
 281       swr_draw_context *pDC = &ctx->swrDC;
 282       SWR_SURFACE_STATE *renderTargets = pDC->renderTargets;
 283       for (uint32_t i = 0; i < SWR_NUM_ATTACHMENTS; i++)
 284          if (renderTargets[i].pBaseAddress == spr->swr.pBaseAddress ||
 285              (spr->secondary.pBaseAddress &&
 286               renderTargets[i].pBaseAddress == spr->secondary.pBaseAddress)) {
 287             swr_store_render_target(pipe, i, post_tile_state);
 288
 289             /* Mesa thinks depth/stencil are fused, so we'll never get an
 290              * explicit resource for stencil.  So, if checking depth, then
 291              * also check for stencil. */
 292             if (spr->has_stencil && (i == SWR_ATTACHMENT_DEPTH)) {
 293                swr_store_render_target(
 294                   pipe, SWR_ATTACHMENT_STENCIL, post_tile_state);
 295             }
 296
 297             /* This fence signals StoreTiles completion */
 298             swr_fence_submit(ctx, screen->flush_fence);
 299
 300             break;
 301          }
 302    }
 303 }
 304
 305 void
 306 swr_draw_init(struct pipe_context *pipe)
 307 {
 308    pipe->draw_vbo = swr_draw_vbo;
 309    pipe->flush = swr_flush;
 310 }