src/gallium/drivers/swr/swr_draw.cpp

   1 /****************************************************************************
   2  * Copyright (C) 2015 Intel Corporation.   All Rights Reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  ***************************************************************************/
  23
  24 #include "swr_screen.h"
  25 #include "swr_context.h"
  26 #include "swr_resource.h"
  27 #include "swr_fence.h"
  28 #include "swr_query.h"
  29 #include "jit_api.h"
  30
  31 #include "util/u_draw.h"
  32 #include "util/u_prim.h"
  33
  34 /*
  35  * Draw vertex arrays, with optional indexing, optional instancing.
  36  */
  37 static void
  38 swr_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
  39 {
  40    struct swr_context *ctx = swr_context(pipe);
  41
  42    if (!info->count_from_stream_output && !info->indirect &&
  43        !info->primitive_restart &&
  44        !u_trim_pipe_prim(info->mode, (unsigned*)&info->count))
  45       return;
  46
  47    if (!swr_check_render_cond(pipe))
  48       return;
  49
  50    if (info->indirect) {
  51       util_draw_indirect(pipe, info);
  52       return;
  53    }
  54
  55    /* Update derived state, pass draw info to update function */
  56    swr_update_derived(pipe, info);
  57
  58    swr_update_draw_context(ctx);
  59
  60    if (ctx->vs->pipe.stream_output.num_outputs) {
  61       if (!ctx->vs->soFunc[info->mode]) {
  62          STREAMOUT_COMPILE_STATE state = {0};
  63          struct pipe_stream_output_info *so = &ctx->vs->pipe.stream_output;
  64
  65          state.numVertsPerPrim = u_vertices_per_prim(info->mode);
  66
  67          uint32_t offsets[MAX_SO_STREAMS] = {0};
  68          uint32_t num = 0;
  69
  70          for (uint32_t i = 0; i < so->num_outputs; i++) {
  71             assert(so->output[i].stream == 0); // @todo
  72             uint32_t output_buffer = so->output[i].output_buffer;
  73             if (so->output[i].dst_offset != offsets[output_buffer]) {
  74                // hole - need to fill
  75                state.stream.decl[num].bufferIndex = output_buffer;
  76                state.stream.decl[num].hole = true;
  77                state.stream.decl[num].componentMask =
  78                   (1 << (so->output[i].dst_offset - offsets[output_buffer]))
  79                   - 1;
  80                num++;
  81                offsets[output_buffer] = so->output[i].dst_offset;
  82             }
  83
  84             state.stream.decl[num].bufferIndex = output_buffer;
  85             state.stream.decl[num].attribSlot = so->output[i].register_index - 1;
  86             state.stream.decl[num].componentMask =
  87                ((1 << so->output[i].num_components) - 1)
  88                << so->output[i].start_component;
  89             state.stream.decl[num].hole = false;
  90             num++;
  91
  92             offsets[output_buffer] += so->output[i].num_components;
  93          }
  94
  95          state.stream.numDecls = num;
  96
  97          HANDLE hJitMgr = swr_screen(pipe->screen)->hJitMgr;
  98          ctx->vs->soFunc[info->mode] = JitCompileStreamout(hJitMgr, state);
  99          debug_printf("so shader    %p\n", ctx->vs->soFunc[info->mode]);
 100          assert(ctx->vs->soFunc[info->mode] && "Error: SoShader = NULL");
 101       }
 102
 103       ctx->api.pfnSwrSetSoFunc(ctx->swrContext, ctx->vs->soFunc[info->mode], 0);
 104    }
 105
 106    struct swr_vertex_element_state *velems = ctx->velems;
 107    velems->fsState.cutIndex = info->restart_index;
 108    velems->fsState.bEnableCutIndex = info->primitive_restart;
 109    velems->fsState.bPartialVertexBuffer = (info->min_index > 0);
 110
 111    swr_jit_fetch_key key;
 112    swr_generate_fetch_key(key, velems);
 113    auto search = velems->map.find(key);
 114    if (search != velems->map.end()) {
 115       velems->fsFunc = search->second;
 116    } else {
 117       HANDLE hJitMgr = swr_screen(ctx->pipe.screen)->hJitMgr;
 118       velems->fsFunc = JitCompileFetch(hJitMgr, velems->fsState);
 119
 120       debug_printf("fetch shader %p\n", velems->fsFunc);
 121       assert(velems->fsFunc && "Error: FetchShader = NULL");
 122
 123       velems->map.insert(std::make_pair(key, velems->fsFunc));
 124    }
 125
 126    ctx->api.pfnSwrSetFetchFunc(ctx->swrContext, velems->fsFunc);
 127
 128    /* Set up frontend state
 129     * XXX setup provokingVertex & topologyProvokingVertex */
 130    SWR_FRONTEND_STATE feState = {0};
 131
 132    feState.vsVertexSize =
 133       VERTEX_ATTRIB_START_SLOT +
 134       + ctx->vs->info.base.num_outputs
 135       - (ctx->vs->info.base.writes_position ? 1 : 0);
 136
 137    if (ctx->rasterizer->flatshade_first) {
 138       feState.provokingVertex = {1, 0, 0};
 139    } else {
 140       feState.provokingVertex = {2, 1, 2};
 141    }
 142
 143    enum pipe_prim_type topology;
 144    if (ctx->gs)
 145       topology = (pipe_prim_type)ctx->gs->info.base.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
 146    else
 147       topology = info->mode;
 148
 149    switch (topology) {
 150    case PIPE_PRIM_TRIANGLE_FAN:
 151       feState.topologyProvokingVertex = feState.provokingVertex.triFan;
 152       break;
 153    case PIPE_PRIM_TRIANGLE_STRIP:
 154    case PIPE_PRIM_TRIANGLES:
 155       feState.topologyProvokingVertex = feState.provokingVertex.triStripList;
 156       break;
 157    case PIPE_PRIM_QUAD_STRIP:
 158    case PIPE_PRIM_QUADS:
 159       if (ctx->rasterizer->flatshade_first)
 160          feState.topologyProvokingVertex = 0;
 161       else
 162          feState.topologyProvokingVertex = 3;
 163       break;
 164    case PIPE_PRIM_LINES:
 165    case PIPE_PRIM_LINE_LOOP:
 166    case PIPE_PRIM_LINE_STRIP:
 167       feState.topologyProvokingVertex = feState.provokingVertex.lineStripList;
 168       break;
 169    default:
 170       feState.topologyProvokingVertex = 0;
 171    }
 172
 173    feState.bEnableCutIndex = info->primitive_restart;
 174    ctx->api.pfnSwrSetFrontendState(ctx->swrContext, &feState);
 175
 176    if (info->index_size)
 177       ctx->api.pfnSwrDrawIndexedInstanced(ctx->swrContext,
 178                                           swr_convert_prim_topology(info->mode),
 179                                           info->count,
 180                                           info->instance_count,
 181                                           info->start,
 182                                           info->index_bias,
 183                                           info->start_instance);
 184    else
 185       ctx->api.pfnSwrDrawInstanced(ctx->swrContext,
 186                                    swr_convert_prim_topology(info->mode),
 187                                    info->count,
 188                                    info->instance_count,
 189                                    info->start,
 190                                    info->start_instance);
 191 }
 192
 193
 194 static void
 195 swr_flush(struct pipe_context *pipe,
 196           struct pipe_fence_handle **fence,
 197           unsigned flags)
 198 {
 199    struct swr_context *ctx = swr_context(pipe);
 200    struct swr_screen *screen = swr_screen(pipe->screen);
 201    struct pipe_surface *cb = ctx->framebuffer.cbufs[0];
 202
 203    /* If the current renderTarget is the display surface, store tiles back to
 204     * the surface, in preparation for present (swr_flush_frontbuffer).
 205     * Other renderTargets get stored back when attachment changes or
 206     * swr_surface_destroy */
 207    if (cb && swr_resource(cb->texture)->display_target)
 208       swr_store_dirty_resource(pipe, cb->texture, SWR_TILE_RESOLVED);
 209
 210    if (fence)
 211       swr_fence_reference(pipe->screen, fence, screen->flush_fence);
 212 }
 213
 214 void
 215 swr_finish(struct pipe_context *pipe)
 216 {
 217    struct pipe_fence_handle *fence = nullptr;
 218
 219    swr_flush(pipe, &fence, 0);
 220    swr_fence_finish(pipe->screen, NULL, fence, 0);
 221    swr_fence_reference(pipe->screen, &fence, NULL);
 222 }
 223
 224 /*
 225  * Invalidate tiles so they can be reloaded back when needed
 226  */
 227 void
 228 swr_invalidate_render_target(struct pipe_context *pipe,
 229                              uint32_t attachment,
 230                              uint16_t width, uint16_t height)
 231 {
 232    struct swr_context *ctx = swr_context(pipe);
 233
 234    /* grab the rect from the passed in arguments */
 235    swr_update_draw_context(ctx);
 236    SWR_RECT full_rect =
 237       {0, 0, (int32_t)width, (int32_t)height};
 238    ctx->api.pfnSwrInvalidateTiles(ctx->swrContext,
 239                                   1 << attachment,
 240                                   full_rect);
 241 }
 242
 243
 244 /*
 245  * Store SWR HotTiles back to renderTarget surface.
 246  */
 247 void
 248 swr_store_render_target(struct pipe_context *pipe,
 249                         uint32_t attachment,
 250                         enum SWR_TILE_STATE post_tile_state)
 251 {
 252    struct swr_context *ctx = swr_context(pipe);
 253    struct swr_draw_context *pDC = &ctx->swrDC;
 254    struct SWR_SURFACE_STATE *renderTarget = &pDC->renderTargets[attachment];
 255
 256    /* Only proceed if there's a valid surface to store to */
 257    if (renderTarget->pBaseAddress) {
 258       swr_update_draw_context(ctx);
 259       SWR_RECT full_rect =
 260          {0, 0,
 261           (int32_t)u_minify(renderTarget->width, renderTarget->lod),
 262           (int32_t)u_minify(renderTarget->height, renderTarget->lod)};
 263       ctx->api.pfnSwrStoreTiles(ctx->swrContext,
 264                                 1 << attachment,
 265                                 post_tile_state,
 266                                 full_rect);
 267    }
 268 }
 269
 270 void
 271 swr_store_dirty_resource(struct pipe_context *pipe,
 272                          struct pipe_resource *resource,
 273                          enum SWR_TILE_STATE post_tile_state)
 274 {
 275    /* Only store resource if it has been written to */
 276    if (swr_resource(resource)->status & SWR_RESOURCE_WRITE) {
 277       struct swr_context *ctx = swr_context(pipe);
 278       struct swr_screen *screen = swr_screen(pipe->screen);
 279       struct swr_resource *spr = swr_resource(resource);
 280
 281       swr_draw_context *pDC = &ctx->swrDC;
 282       SWR_SURFACE_STATE *renderTargets = pDC->renderTargets;
 283       for (uint32_t i = 0; i < SWR_NUM_ATTACHMENTS; i++)
 284          if (renderTargets[i].pBaseAddress == spr->swr.pBaseAddress ||
 285              (spr->secondary.pBaseAddress &&
 286               renderTargets[i].pBaseAddress == spr->secondary.pBaseAddress)) {
 287             swr_store_render_target(pipe, i, post_tile_state);
 288
 289             /* Mesa thinks depth/stencil are fused, so we'll never get an
 290              * explicit resource for stencil.  So, if checking depth, then
 291              * also check for stencil. */
 292             if (spr->has_stencil && (i == SWR_ATTACHMENT_DEPTH)) {
 293                swr_store_render_target(
 294                   pipe, SWR_ATTACHMENT_STENCIL, post_tile_state);
 295             }
 296
 297             /* This fence signals StoreTiles completion */
 298             swr_fence_submit(ctx, screen->flush_fence);
 299
 300             break;
 301          }
 302    }
 303 }
 304
 305 void
 306 swr_draw_init(struct pipe_context *pipe)
 307 {
 308    pipe->draw_vbo = swr_draw_vbo;
 309    pipe->flush = swr_flush;
 310 }