1 /****************************************************************************
2 * Copyright (C) 2015 Intel Corporation. All Rights Reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 ***************************************************************************/
24 #include "swr_screen.h"
25 #include "swr_context.h"
26 #include "swr_resource.h"
27 #include "swr_fence.h"
28 #include "swr_query.h"
31 #include "util/u_draw.h"
32 #include "util/u_prim.h"
35 * Draw vertex arrays, with optional indexing, optional instancing.
38 swr_draw_vbo(struct pipe_context
*pipe
, const struct pipe_draw_info
*info
)
40 struct swr_context
*ctx
= swr_context(pipe
);
42 if (!info
->count_from_stream_output
&& !info
->indirect
&&
43 !info
->primitive_restart
&&
44 !u_trim_pipe_prim(info
->mode
, (unsigned*)&info
->count
))
47 if (!swr_check_render_cond(pipe
))
51 util_draw_indirect(pipe
, info
);
55 /* If indexed draw, force vertex validation since index buffer comes
58 ctx
->dirty
|= SWR_NEW_VERTEX
;
60 /* Update derived state, pass draw info to update function. */
61 swr_update_derived(pipe
, info
);
63 swr_update_draw_context(ctx
);
65 struct pipe_draw_info resolved_info
;
66 /* DrawTransformFeedback */
67 if (info
->count_from_stream_output
) {
68 // trick copied from softpipe to modify const struct *info
69 memcpy(&resolved_info
, (void*)info
, sizeof(struct pipe_draw_info
));
70 resolved_info
.count
= ctx
->so_primCounter
* resolved_info
.vertices_per_patch
;
71 resolved_info
.max_index
= resolved_info
.count
- 1;
72 info
= &resolved_info
;
75 if (ctx
->vs
->pipe
.stream_output
.num_outputs
) {
76 if (!ctx
->vs
->soFunc
[info
->mode
]) {
77 STREAMOUT_COMPILE_STATE state
= {0};
78 struct pipe_stream_output_info
*so
= &ctx
->vs
->pipe
.stream_output
;
80 state
.numVertsPerPrim
= u_vertices_per_prim(info
->mode
);
82 uint32_t offsets
[MAX_SO_STREAMS
] = {0};
85 for (uint32_t i
= 0; i
< so
->num_outputs
; i
++) {
86 assert(so
->output
[i
].stream
== 0); // @todo
87 uint32_t output_buffer
= so
->output
[i
].output_buffer
;
88 if (so
->output
[i
].dst_offset
!= offsets
[output_buffer
]) {
89 // hole - need to fill
90 state
.stream
.decl
[num
].bufferIndex
= output_buffer
;
91 state
.stream
.decl
[num
].hole
= true;
92 state
.stream
.decl
[num
].componentMask
=
93 (1 << (so
->output
[i
].dst_offset
- offsets
[output_buffer
]))
96 offsets
[output_buffer
] = so
->output
[i
].dst_offset
;
99 unsigned attrib_slot
= so
->output
[i
].register_index
;
100 attrib_slot
= swr_so_adjust_attrib(attrib_slot
, ctx
->vs
);
102 state
.stream
.decl
[num
].bufferIndex
= output_buffer
;
103 state
.stream
.decl
[num
].attribSlot
= attrib_slot
;
104 state
.stream
.decl
[num
].componentMask
=
105 ((1 << so
->output
[i
].num_components
) - 1)
106 << so
->output
[i
].start_component
;
107 state
.stream
.decl
[num
].hole
= false;
110 offsets
[output_buffer
] += so
->output
[i
].num_components
;
113 state
.stream
.numDecls
= num
;
115 HANDLE hJitMgr
= swr_screen(pipe
->screen
)->hJitMgr
;
116 ctx
->vs
->soFunc
[info
->mode
] = JitCompileStreamout(hJitMgr
, state
);
117 debug_printf("so shader %p\n", ctx
->vs
->soFunc
[info
->mode
]);
118 assert(ctx
->vs
->soFunc
[info
->mode
] && "Error: SoShader = NULL");
121 ctx
->api
.pfnSwrSetSoFunc(ctx
->swrContext
, ctx
->vs
->soFunc
[info
->mode
], 0);
124 struct swr_vertex_element_state
*velems
= ctx
->velems
;
125 if (info
->primitive_restart
)
126 velems
->fsState
.cutIndex
= info
->restart_index
;
128 velems
->fsState
.cutIndex
= 0;
129 velems
->fsState
.bEnableCutIndex
= info
->primitive_restart
;
130 velems
->fsState
.bPartialVertexBuffer
= (info
->min_index
> 0);
132 swr_jit_fetch_key key
;
133 swr_generate_fetch_key(key
, velems
);
134 auto search
= velems
->map
.find(key
);
135 if (search
!= velems
->map
.end()) {
136 velems
->fsFunc
= search
->second
;
138 HANDLE hJitMgr
= swr_screen(ctx
->pipe
.screen
)->hJitMgr
;
139 velems
->fsFunc
= JitCompileFetch(hJitMgr
, velems
->fsState
);
141 debug_printf("fetch shader %p\n", velems
->fsFunc
);
142 assert(velems
->fsFunc
&& "Error: FetchShader = NULL");
144 velems
->map
.insert(std::make_pair(key
, velems
->fsFunc
));
147 ctx
->api
.pfnSwrSetFetchFunc(ctx
->swrContext
, velems
->fsFunc
);
149 /* Set up frontend state
150 * XXX setup provokingVertex & topologyProvokingVertex */
151 SWR_FRONTEND_STATE feState
= {0};
153 // feState.vsVertexSize seeds the PA size that is used as an interface
154 // between all the shader stages, so it has to be large enough to
155 // incorporate all interfaces between stages
157 // max of gs and vs num_outputs
158 feState
.vsVertexSize
= ctx
->vs
->info
.base
.num_outputs
;
160 ctx
->gs
->info
.base
.num_outputs
> feState
.vsVertexSize
) {
161 feState
.vsVertexSize
= ctx
->gs
->info
.base
.num_outputs
;
164 if (ctx
->vs
->info
.base
.num_outputs
) {
165 // gs does not adjust for position in SGV slot at input from vs
167 feState
.vsVertexSize
--;
170 // other (non-SGV) slots start at VERTEX_ATTRIB_START_SLOT
171 feState
.vsVertexSize
+= VERTEX_ATTRIB_START_SLOT
;
173 // The PA in the clipper does not handle BE vertex sizes
174 // different from FE. Increase vertexsize only for the cases that needed it
176 // primid needs a slot
177 if (ctx
->fs
->info
.base
.uses_primid
)
178 feState
.vsVertexSize
++;
179 // sprite coord enable
180 if (ctx
->rasterizer
->sprite_coord_enable
)
181 feState
.vsVertexSize
++;
184 if (ctx
->rasterizer
->flatshade_first
) {
185 feState
.provokingVertex
= {1, 0, 0};
187 feState
.provokingVertex
= {2, 1, 2};
190 enum pipe_prim_type topology
;
192 topology
= (pipe_prim_type
)ctx
->gs
->info
.base
.properties
[TGSI_PROPERTY_GS_OUTPUT_PRIM
];
194 topology
= info
->mode
;
197 case PIPE_PRIM_TRIANGLE_FAN
:
198 feState
.topologyProvokingVertex
= feState
.provokingVertex
.triFan
;
200 case PIPE_PRIM_TRIANGLE_STRIP
:
201 case PIPE_PRIM_TRIANGLES
:
202 feState
.topologyProvokingVertex
= feState
.provokingVertex
.triStripList
;
204 case PIPE_PRIM_QUAD_STRIP
:
205 case PIPE_PRIM_QUADS
:
206 if (ctx
->rasterizer
->flatshade_first
)
207 feState
.topologyProvokingVertex
= 0;
209 feState
.topologyProvokingVertex
= 3;
211 case PIPE_PRIM_LINES
:
212 case PIPE_PRIM_LINE_LOOP
:
213 case PIPE_PRIM_LINE_STRIP
:
214 feState
.topologyProvokingVertex
= feState
.provokingVertex
.lineStripList
;
217 feState
.topologyProvokingVertex
= 0;
220 feState
.bEnableCutIndex
= info
->primitive_restart
;
221 ctx
->api
.pfnSwrSetFrontendState(ctx
->swrContext
, &feState
);
223 if (info
->index_size
)
224 ctx
->api
.pfnSwrDrawIndexedInstanced(ctx
->swrContext
,
225 swr_convert_prim_topology(info
->mode
),
227 info
->instance_count
,
230 info
->start_instance
);
232 ctx
->api
.pfnSwrDrawInstanced(ctx
->swrContext
,
233 swr_convert_prim_topology(info
->mode
),
235 info
->instance_count
,
237 info
->start_instance
);
239 /* On client-buffer draw, we used client buffer directly, without
240 * copy. Block until draw is finished.
241 * VMD is an example application that benefits from this. */
242 if (ctx
->dirty
& SWR_BLOCK_CLIENT_DRAW
) {
243 struct swr_screen
*screen
= swr_screen(pipe
->screen
);
244 swr_fence_submit(ctx
, screen
->flush_fence
);
245 swr_fence_finish(pipe
->screen
, NULL
, screen
->flush_fence
, 0);
251 swr_flush(struct pipe_context
*pipe
,
252 struct pipe_fence_handle
**fence
,
255 struct swr_context
*ctx
= swr_context(pipe
);
256 struct swr_screen
*screen
= swr_screen(pipe
->screen
);
258 for (int i
=0; i
< ctx
->framebuffer
.nr_cbufs
; i
++) {
259 struct pipe_surface
*cb
= ctx
->framebuffer
.cbufs
[i
];
261 swr_store_dirty_resource(pipe
, cb
->texture
, SWR_TILE_RESOLVED
);
264 if (ctx
->framebuffer
.zsbuf
) {
265 swr_store_dirty_resource(pipe
, ctx
->framebuffer
.zsbuf
->texture
,
270 swr_fence_reference(pipe
->screen
, fence
, screen
->flush_fence
);
274 swr_finish(struct pipe_context
*pipe
)
276 struct pipe_fence_handle
*fence
= nullptr;
278 swr_flush(pipe
, &fence
, 0);
279 swr_fence_finish(pipe
->screen
, NULL
, fence
, 0);
280 swr_fence_reference(pipe
->screen
, &fence
, NULL
);
284 * Invalidate tiles so they can be reloaded back when needed
287 swr_invalidate_render_target(struct pipe_context
*pipe
,
289 uint16_t width
, uint16_t height
)
291 struct swr_context
*ctx
= swr_context(pipe
);
293 /* grab the rect from the passed in arguments */
294 swr_update_draw_context(ctx
);
296 {0, 0, (int32_t)width
, (int32_t)height
};
297 ctx
->api
.pfnSwrInvalidateTiles(ctx
->swrContext
,
304 * Store SWR HotTiles back to renderTarget surface.
307 swr_store_render_target(struct pipe_context
*pipe
,
309 enum SWR_TILE_STATE post_tile_state
)
311 struct swr_context
*ctx
= swr_context(pipe
);
312 struct swr_draw_context
*pDC
= &ctx
->swrDC
;
313 struct SWR_SURFACE_STATE
*renderTarget
= &pDC
->renderTargets
[attachment
];
315 /* Only proceed if there's a valid surface to store to */
316 if (renderTarget
->xpBaseAddress
) {
317 swr_update_draw_context(ctx
);
320 (int32_t)u_minify(renderTarget
->width
, renderTarget
->lod
),
321 (int32_t)u_minify(renderTarget
->height
, renderTarget
->lod
)};
322 ctx
->api
.pfnSwrStoreTiles(ctx
->swrContext
,
330 swr_store_dirty_resource(struct pipe_context
*pipe
,
331 struct pipe_resource
*resource
,
332 enum SWR_TILE_STATE post_tile_state
)
334 /* Only store resource if it has been written to */
335 if (swr_resource(resource
)->status
& SWR_RESOURCE_WRITE
) {
336 struct swr_context
*ctx
= swr_context(pipe
);
337 struct swr_screen
*screen
= swr_screen(pipe
->screen
);
338 struct swr_resource
*spr
= swr_resource(resource
);
340 swr_draw_context
*pDC
= &ctx
->swrDC
;
341 SWR_SURFACE_STATE
*renderTargets
= pDC
->renderTargets
;
342 for (uint32_t i
= 0; i
< SWR_NUM_ATTACHMENTS
; i
++)
343 if (renderTargets
[i
].xpBaseAddress
== spr
->swr
.xpBaseAddress
||
344 (spr
->secondary
.xpBaseAddress
&&
345 renderTargets
[i
].xpBaseAddress
== spr
->secondary
.xpBaseAddress
)) {
346 swr_store_render_target(pipe
, i
, post_tile_state
);
348 /* Mesa thinks depth/stencil are fused, so we'll never get an
349 * explicit resource for stencil. So, if checking depth, then
350 * also check for stencil. */
351 if (spr
->has_stencil
&& (i
== SWR_ATTACHMENT_DEPTH
)) {
352 swr_store_render_target(
353 pipe
, SWR_ATTACHMENT_STENCIL
, post_tile_state
);
356 /* This fence signals StoreTiles completion */
357 swr_fence_submit(ctx
, screen
->flush_fence
);
365 swr_draw_init(struct pipe_context
*pipe
)
367 pipe
->draw_vbo
= swr_draw_vbo
;
368 pipe
->flush
= swr_flush
;