1 /****************************************************************************
2 * Copyright (C) 2015 Intel Corporation. All Rights Reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 ***************************************************************************/
24 #include "swr_context.h"
25 #include "swr_public.h"
26 #include "swr_screen.h"
27 #include "swr_resource.h"
28 #include "swr_fence.h"
29 #include "gen_knobs.h"
31 #include "pipe/p_screen.h"
32 #include "pipe/p_defines.h"
33 #include "util/u_memory.h"
34 #include "util/format/u_format.h"
35 #include "util/u_inlines.h"
36 #include "util/u_cpu_detect.h"
37 #include "util/format/u_format_s3tc.h"
38 #include "util/u_string.h"
39 #include "util/u_screen.h"
41 #include "frontend/sw_winsys.h"
45 #include "memory/TilingFunctions.h"
52 * XXX Check max texture size values against core and sampler.
54 #define SWR_MAX_TEXTURE_SIZE (2 * 1024 * 1024 * 1024ULL) /* 2GB */
55 /* Not all texture formats can fit into 2GB limit, but we have to
56 live with that. See lp_limits.h for more details */
57 #define SWR_MAX_TEXTURE_2D_SIZE 16384
58 #define SWR_MAX_TEXTURE_3D_LEVELS 12 /* 2K x 2K x 2K for now */
59 #define SWR_MAX_TEXTURE_CUBE_LEVELS 14 /* 8K x 8K for now */
60 #define SWR_MAX_TEXTURE_ARRAY_LAYERS 512 /* 8K x 512 / 8K x 8K x 512 */
62 /* Default max client_copy_limit */
63 #define SWR_CLIENT_COPY_LIMIT 8192
65 /* Flag indicates creation of alternate surface, to prevent recursive loop
66 * in resource creation when msaa_force_enable is set. */
67 #define SWR_RESOURCE_FLAG_ALT_SURFACE (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
71 swr_get_name(struct pipe_screen
*screen
)
74 snprintf(buf
, sizeof(buf
), "SWR (LLVM " MESA_LLVM_VERSION_STRING
", %u bits)",
75 lp_native_vector_width
);
80 swr_get_vendor(struct pipe_screen
*screen
)
82 return "Intel Corporation";
86 swr_is_format_supported(struct pipe_screen
*_screen
,
87 enum pipe_format format
,
88 enum pipe_texture_target target
,
89 unsigned sample_count
,
90 unsigned storage_sample_count
,
93 struct swr_screen
*screen
= swr_screen(_screen
);
94 struct sw_winsys
*winsys
= screen
->winsys
;
95 const struct util_format_description
*format_desc
;
97 assert(target
== PIPE_BUFFER
|| target
== PIPE_TEXTURE_1D
98 || target
== PIPE_TEXTURE_1D_ARRAY
99 || target
== PIPE_TEXTURE_2D
100 || target
== PIPE_TEXTURE_2D_ARRAY
101 || target
== PIPE_TEXTURE_RECT
102 || target
== PIPE_TEXTURE_3D
103 || target
== PIPE_TEXTURE_CUBE
104 || target
== PIPE_TEXTURE_CUBE_ARRAY
);
106 if (MAX2(1, sample_count
) != MAX2(1, storage_sample_count
))
109 format_desc
= util_format_description(format
);
113 if ((sample_count
> screen
->msaa_max_count
)
114 || !util_is_power_of_two_or_zero(sample_count
))
117 if (bind
& PIPE_BIND_DISPLAY_TARGET
) {
118 if (!winsys
->is_displaytarget_format_supported(winsys
, bind
, format
))
122 if (bind
& PIPE_BIND_RENDER_TARGET
) {
123 if (format_desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
)
126 if (mesa_to_swr_format(format
) == (SWR_FORMAT
)-1)
130 * Although possible, it is unnatural to render into compressed or YUV
131 * surfaces. So disable these here to avoid going into weird paths
132 * inside gallium frontends.
134 if (format_desc
->block
.width
!= 1 || format_desc
->block
.height
!= 1)
138 if (bind
& PIPE_BIND_DEPTH_STENCIL
) {
139 if (format_desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
)
142 if (mesa_to_swr_format(format
) == (SWR_FORMAT
)-1)
146 if (bind
& PIPE_BIND_VERTEX_BUFFER
) {
147 if (mesa_to_swr_format(format
) == (SWR_FORMAT
)-1) {
152 if (format_desc
->layout
== UTIL_FORMAT_LAYOUT_ASTC
||
153 format_desc
->layout
== UTIL_FORMAT_LAYOUT_FXT1
)
158 if (format_desc
->layout
== UTIL_FORMAT_LAYOUT_ETC
&&
159 format
!= PIPE_FORMAT_ETC1_RGB8
) {
163 if ((bind
& (PIPE_BIND_RENDER_TARGET
| PIPE_BIND_SAMPLER_VIEW
)) &&
164 ((bind
& PIPE_BIND_DISPLAY_TARGET
) == 0)) {
165 /* Disable all 3-channel formats, where channel size != 32 bits.
166 * In some cases we run into crashes (in generate_unswizzled_blend()),
167 * for 3-channel RGB16 variants, there was an apparent LLVM bug.
168 * In any case, disabling the shallower 3-channel formats avoids a
169 * number of issues with GL_ARB_copy_image support.
171 if (format_desc
->is_array
&&
172 format_desc
->nr_channels
== 3 &&
173 format_desc
->block
.bits
!= 96) {
182 swr_get_param(struct pipe_screen
*screen
, enum pipe_cap param
)
186 case PIPE_CAP_MAX_RENDER_TARGETS
:
187 return PIPE_MAX_COLOR_BUFS
;
188 case PIPE_CAP_MAX_TEXTURE_2D_SIZE
:
189 return SWR_MAX_TEXTURE_2D_SIZE
;
190 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
191 return SWR_MAX_TEXTURE_3D_LEVELS
;
192 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
193 return SWR_MAX_TEXTURE_CUBE_LEVELS
;
194 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
195 return MAX_SO_STREAMS
;
196 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
197 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
198 return MAX_ATTRIBUTES
* 4;
199 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
200 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
202 case PIPE_CAP_MAX_VERTEX_STREAMS
:
204 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
206 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
207 return SWR_MAX_TEXTURE_ARRAY_LAYERS
;
208 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
209 case PIPE_CAP_MIN_TEXEL_OFFSET
:
211 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
212 case PIPE_CAP_MAX_TEXEL_OFFSET
:
214 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
216 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
218 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY
:
220 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
222 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
224 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
226 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
228 case PIPE_CAP_MAX_VIEWPORTS
:
229 return KNOB_NUM_VIEWPORTS_SCISSORS
;
230 case PIPE_CAP_ENDIANNESS
:
231 return PIPE_ENDIAN_NATIVE
;
233 /* supported features */
234 case PIPE_CAP_NPOT_TEXTURES
:
235 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
236 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS
:
237 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD
:
238 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES
:
239 case PIPE_CAP_VERTEX_SHADER_SATURATE
:
240 case PIPE_CAP_POINT_SPRITE
:
241 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
242 case PIPE_CAP_OCCLUSION_QUERY
:
243 case PIPE_CAP_QUERY_TIME_ELAPSED
:
244 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
245 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
246 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE
:
247 case PIPE_CAP_TEXTURE_SWIZZLE
:
248 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
249 case PIPE_CAP_INDEP_BLEND_ENABLE
:
250 case PIPE_CAP_INDEP_BLEND_FUNC
:
251 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
252 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
253 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
254 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
255 case PIPE_CAP_PRIMITIVE_RESTART
:
256 case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX
:
257 case PIPE_CAP_TGSI_INSTANCEID
:
258 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
259 case PIPE_CAP_START_INSTANCE
:
260 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
261 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
262 case PIPE_CAP_CONDITIONAL_RENDER
:
263 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
264 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
265 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
266 case PIPE_CAP_USER_VERTEX_BUFFERS
:
267 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS
:
268 case PIPE_CAP_QUERY_TIMESTAMP
:
269 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
270 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
271 case PIPE_CAP_DRAW_INDIRECT
:
273 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
274 case PIPE_CAP_CLIP_HALFZ
:
275 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
276 case PIPE_CAP_DEPTH_BOUNDS_TEST
:
277 case PIPE_CAP_CLEAR_TEXTURE
:
278 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
279 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
280 case PIPE_CAP_CULL_DISTANCE
:
281 case PIPE_CAP_CUBE_MAP_ARRAY
:
282 case PIPE_CAP_DOUBLES
:
283 case PIPE_CAP_TEXTURE_QUERY_LOD
:
284 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
:
285 case PIPE_CAP_TGSI_TG4_COMPONENT_IN_SWIZZLE
:
286 case PIPE_CAP_QUERY_SO_OVERFLOW
:
287 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
291 * If user has explicitly set max_sample_count = 1 (via SWR_MSAA_MAX_COUNT)
292 * then disable all MSAA support and go back to old (FAKE_SW_MSAA) caps. */
293 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
294 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE
:
295 return (swr_screen(screen
)->msaa_max_count
> 1) ? 1 : 0;
296 case PIPE_CAP_FAKE_SW_MSAA
:
297 return (swr_screen(screen
)->msaa_max_count
> 1) ? 0 : 1;
299 /* fetch jit change for 2-4GB buffers requires alignment */
300 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
301 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
302 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
305 /* unsupported features */
306 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
307 case PIPE_CAP_PCI_GROUP
:
308 case PIPE_CAP_PCI_BUS
:
309 case PIPE_CAP_PCI_DEVICE
:
310 case PIPE_CAP_PCI_FUNCTION
:
311 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY
:
313 case PIPE_CAP_MAX_GS_INVOCATIONS
:
315 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE
:
317 case PIPE_CAP_MAX_VARYINGS
:
320 case PIPE_CAP_VENDOR_ID
:
322 case PIPE_CAP_DEVICE_ID
:
324 case PIPE_CAP_ACCELERATED
:
326 case PIPE_CAP_VIDEO_MEMORY
: {
327 /* XXX: Do we want to return the full amount of system memory ? */
328 uint64_t system_memory
;
330 if (!os_get_total_physical_memory(&system_memory
))
333 return (int)(system_memory
>> 20);
336 return u_pipe_screen_get_param_defaults(screen
, param
);
341 swr_get_shader_param(struct pipe_screen
*screen
,
342 enum pipe_shader_type shader
,
343 enum pipe_shader_cap param
)
345 if (shader
== PIPE_SHADER_VERTEX
||
346 shader
== PIPE_SHADER_FRAGMENT
||
347 shader
== PIPE_SHADER_GEOMETRY
348 || shader
== PIPE_SHADER_TESS_CTRL
||
349 shader
== PIPE_SHADER_TESS_EVAL
351 return gallivm_get_shader_param(param
);
359 swr_get_paramf(struct pipe_screen
*screen
, enum pipe_capf param
)
362 case PIPE_CAPF_MAX_LINE_WIDTH
:
363 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
364 case PIPE_CAPF_MAX_POINT_WIDTH
:
365 return 255.0; /* arbitrary */
366 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
368 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
370 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
371 return 16.0; /* arbitrary */
372 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE
:
373 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE
:
374 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY
:
377 /* should only get here on unhandled cases */
378 debug_printf("Unexpected PIPE_CAPF %d query\n", param
);
383 mesa_to_swr_format(enum pipe_format format
)
385 static const std::map
<pipe_format
,SWR_FORMAT
> mesa2swr
= {
386 /* depth / stencil */
387 {PIPE_FORMAT_Z16_UNORM
, R16_UNORM
}, // z
388 {PIPE_FORMAT_Z32_FLOAT
, R32_FLOAT
}, // z
389 {PIPE_FORMAT_Z24_UNORM_S8_UINT
, R24_UNORM_X8_TYPELESS
}, // z
390 {PIPE_FORMAT_Z24X8_UNORM
, R24_UNORM_X8_TYPELESS
}, // z
391 {PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
, R32_FLOAT_X8X24_TYPELESS
}, // z
394 {PIPE_FORMAT_A8_UNORM
, A8_UNORM
},
395 {PIPE_FORMAT_A16_UNORM
, A16_UNORM
},
396 {PIPE_FORMAT_A16_FLOAT
, A16_FLOAT
},
397 {PIPE_FORMAT_A32_FLOAT
, A32_FLOAT
},
400 {PIPE_FORMAT_B5G6R5_UNORM
, B5G6R5_UNORM
},
401 {PIPE_FORMAT_B5G6R5_SRGB
, B5G6R5_UNORM_SRGB
},
402 {PIPE_FORMAT_B5G5R5A1_UNORM
, B5G5R5A1_UNORM
},
403 {PIPE_FORMAT_B5G5R5X1_UNORM
, B5G5R5X1_UNORM
},
404 {PIPE_FORMAT_B4G4R4A4_UNORM
, B4G4R4A4_UNORM
},
405 {PIPE_FORMAT_B8G8R8A8_UNORM
, B8G8R8A8_UNORM
},
406 {PIPE_FORMAT_B8G8R8A8_SRGB
, B8G8R8A8_UNORM_SRGB
},
407 {PIPE_FORMAT_B8G8R8X8_UNORM
, B8G8R8X8_UNORM
},
408 {PIPE_FORMAT_B8G8R8X8_SRGB
, B8G8R8X8_UNORM_SRGB
},
411 {PIPE_FORMAT_R10G10B10A2_UNORM
, R10G10B10A2_UNORM
},
412 {PIPE_FORMAT_R10G10B10A2_SNORM
, R10G10B10A2_SNORM
},
413 {PIPE_FORMAT_R10G10B10A2_USCALED
, R10G10B10A2_USCALED
},
414 {PIPE_FORMAT_R10G10B10A2_SSCALED
, R10G10B10A2_SSCALED
},
415 {PIPE_FORMAT_R10G10B10A2_UINT
, R10G10B10A2_UINT
},
418 {PIPE_FORMAT_R10G10B10X2_USCALED
, R10G10B10X2_USCALED
},
421 {PIPE_FORMAT_B10G10R10A2_UNORM
, B10G10R10A2_UNORM
},
422 {PIPE_FORMAT_B10G10R10A2_SNORM
, B10G10R10A2_SNORM
},
423 {PIPE_FORMAT_B10G10R10A2_USCALED
, B10G10R10A2_USCALED
},
424 {PIPE_FORMAT_B10G10R10A2_SSCALED
, B10G10R10A2_SSCALED
},
425 {PIPE_FORMAT_B10G10R10A2_UINT
, B10G10R10A2_UINT
},
428 {PIPE_FORMAT_B10G10R10X2_UNORM
, B10G10R10X2_UNORM
},
431 {PIPE_FORMAT_R11G11B10_FLOAT
, R11G11B10_FLOAT
},
433 /* 32 bits per component */
434 {PIPE_FORMAT_R32_FLOAT
, R32_FLOAT
},
435 {PIPE_FORMAT_R32G32_FLOAT
, R32G32_FLOAT
},
436 {PIPE_FORMAT_R32G32B32_FLOAT
, R32G32B32_FLOAT
},
437 {PIPE_FORMAT_R32G32B32A32_FLOAT
, R32G32B32A32_FLOAT
},
438 {PIPE_FORMAT_R32G32B32X32_FLOAT
, R32G32B32X32_FLOAT
},
440 {PIPE_FORMAT_R32_USCALED
, R32_USCALED
},
441 {PIPE_FORMAT_R32G32_USCALED
, R32G32_USCALED
},
442 {PIPE_FORMAT_R32G32B32_USCALED
, R32G32B32_USCALED
},
443 {PIPE_FORMAT_R32G32B32A32_USCALED
, R32G32B32A32_USCALED
},
445 {PIPE_FORMAT_R32_SSCALED
, R32_SSCALED
},
446 {PIPE_FORMAT_R32G32_SSCALED
, R32G32_SSCALED
},
447 {PIPE_FORMAT_R32G32B32_SSCALED
, R32G32B32_SSCALED
},
448 {PIPE_FORMAT_R32G32B32A32_SSCALED
, R32G32B32A32_SSCALED
},
450 {PIPE_FORMAT_R32_UINT
, R32_UINT
},
451 {PIPE_FORMAT_R32G32_UINT
, R32G32_UINT
},
452 {PIPE_FORMAT_R32G32B32_UINT
, R32G32B32_UINT
},
453 {PIPE_FORMAT_R32G32B32A32_UINT
, R32G32B32A32_UINT
},
455 {PIPE_FORMAT_R32_SINT
, R32_SINT
},
456 {PIPE_FORMAT_R32G32_SINT
, R32G32_SINT
},
457 {PIPE_FORMAT_R32G32B32_SINT
, R32G32B32_SINT
},
458 {PIPE_FORMAT_R32G32B32A32_SINT
, R32G32B32A32_SINT
},
460 /* 16 bits per component */
461 {PIPE_FORMAT_R16_UNORM
, R16_UNORM
},
462 {PIPE_FORMAT_R16G16_UNORM
, R16G16_UNORM
},
463 {PIPE_FORMAT_R16G16B16_UNORM
, R16G16B16_UNORM
},
464 {PIPE_FORMAT_R16G16B16A16_UNORM
, R16G16B16A16_UNORM
},
465 {PIPE_FORMAT_R16G16B16X16_UNORM
, R16G16B16X16_UNORM
},
467 {PIPE_FORMAT_R16_USCALED
, R16_USCALED
},
468 {PIPE_FORMAT_R16G16_USCALED
, R16G16_USCALED
},
469 {PIPE_FORMAT_R16G16B16_USCALED
, R16G16B16_USCALED
},
470 {PIPE_FORMAT_R16G16B16A16_USCALED
, R16G16B16A16_USCALED
},
472 {PIPE_FORMAT_R16_SNORM
, R16_SNORM
},
473 {PIPE_FORMAT_R16G16_SNORM
, R16G16_SNORM
},
474 {PIPE_FORMAT_R16G16B16_SNORM
, R16G16B16_SNORM
},
475 {PIPE_FORMAT_R16G16B16A16_SNORM
, R16G16B16A16_SNORM
},
477 {PIPE_FORMAT_R16_SSCALED
, R16_SSCALED
},
478 {PIPE_FORMAT_R16G16_SSCALED
, R16G16_SSCALED
},
479 {PIPE_FORMAT_R16G16B16_SSCALED
, R16G16B16_SSCALED
},
480 {PIPE_FORMAT_R16G16B16A16_SSCALED
, R16G16B16A16_SSCALED
},
482 {PIPE_FORMAT_R16_UINT
, R16_UINT
},
483 {PIPE_FORMAT_R16G16_UINT
, R16G16_UINT
},
484 {PIPE_FORMAT_R16G16B16_UINT
, R16G16B16_UINT
},
485 {PIPE_FORMAT_R16G16B16A16_UINT
, R16G16B16A16_UINT
},
487 {PIPE_FORMAT_R16_SINT
, R16_SINT
},
488 {PIPE_FORMAT_R16G16_SINT
, R16G16_SINT
},
489 {PIPE_FORMAT_R16G16B16_SINT
, R16G16B16_SINT
},
490 {PIPE_FORMAT_R16G16B16A16_SINT
, R16G16B16A16_SINT
},
492 {PIPE_FORMAT_R16_FLOAT
, R16_FLOAT
},
493 {PIPE_FORMAT_R16G16_FLOAT
, R16G16_FLOAT
},
494 {PIPE_FORMAT_R16G16B16_FLOAT
, R16G16B16_FLOAT
},
495 {PIPE_FORMAT_R16G16B16A16_FLOAT
, R16G16B16A16_FLOAT
},
496 {PIPE_FORMAT_R16G16B16X16_FLOAT
, R16G16B16X16_FLOAT
},
498 /* 8 bits per component */
499 {PIPE_FORMAT_R8_UNORM
, R8_UNORM
},
500 {PIPE_FORMAT_R8G8_UNORM
, R8G8_UNORM
},
501 {PIPE_FORMAT_R8G8B8_UNORM
, R8G8B8_UNORM
},
502 {PIPE_FORMAT_R8G8B8_SRGB
, R8G8B8_UNORM_SRGB
},
503 {PIPE_FORMAT_R8G8B8A8_UNORM
, R8G8B8A8_UNORM
},
504 {PIPE_FORMAT_R8G8B8A8_SRGB
, R8G8B8A8_UNORM_SRGB
},
505 {PIPE_FORMAT_R8G8B8X8_UNORM
, R8G8B8X8_UNORM
},
506 {PIPE_FORMAT_R8G8B8X8_SRGB
, R8G8B8X8_UNORM_SRGB
},
508 {PIPE_FORMAT_R8_USCALED
, R8_USCALED
},
509 {PIPE_FORMAT_R8G8_USCALED
, R8G8_USCALED
},
510 {PIPE_FORMAT_R8G8B8_USCALED
, R8G8B8_USCALED
},
511 {PIPE_FORMAT_R8G8B8A8_USCALED
, R8G8B8A8_USCALED
},
513 {PIPE_FORMAT_R8_SNORM
, R8_SNORM
},
514 {PIPE_FORMAT_R8G8_SNORM
, R8G8_SNORM
},
515 {PIPE_FORMAT_R8G8B8_SNORM
, R8G8B8_SNORM
},
516 {PIPE_FORMAT_R8G8B8A8_SNORM
, R8G8B8A8_SNORM
},
518 {PIPE_FORMAT_R8_SSCALED
, R8_SSCALED
},
519 {PIPE_FORMAT_R8G8_SSCALED
, R8G8_SSCALED
},
520 {PIPE_FORMAT_R8G8B8_SSCALED
, R8G8B8_SSCALED
},
521 {PIPE_FORMAT_R8G8B8A8_SSCALED
, R8G8B8A8_SSCALED
},
523 {PIPE_FORMAT_R8_UINT
, R8_UINT
},
524 {PIPE_FORMAT_R8G8_UINT
, R8G8_UINT
},
525 {PIPE_FORMAT_R8G8B8_UINT
, R8G8B8_UINT
},
526 {PIPE_FORMAT_R8G8B8A8_UINT
, R8G8B8A8_UINT
},
528 {PIPE_FORMAT_R8_SINT
, R8_SINT
},
529 {PIPE_FORMAT_R8G8_SINT
, R8G8_SINT
},
530 {PIPE_FORMAT_R8G8B8_SINT
, R8G8B8_SINT
},
531 {PIPE_FORMAT_R8G8B8A8_SINT
, R8G8B8A8_SINT
},
533 /* These formats are valid for vertex data, but should not be used
534 * for render targets.
537 {PIPE_FORMAT_R32_FIXED
, R32_SFIXED
},
538 {PIPE_FORMAT_R32G32_FIXED
, R32G32_SFIXED
},
539 {PIPE_FORMAT_R32G32B32_FIXED
, R32G32B32_SFIXED
},
540 {PIPE_FORMAT_R32G32B32A32_FIXED
, R32G32B32A32_SFIXED
},
542 {PIPE_FORMAT_R64_FLOAT
, R64_FLOAT
},
543 {PIPE_FORMAT_R64G64_FLOAT
, R64G64_FLOAT
},
544 {PIPE_FORMAT_R64G64B64_FLOAT
, R64G64B64_FLOAT
},
545 {PIPE_FORMAT_R64G64B64A64_FLOAT
, R64G64B64A64_FLOAT
},
547 /* These formats have entries in SWR but don't have Load/StoreTile
548 * implementations. That means these aren't renderable, and thus having
549 * a mapping entry here is detrimental.
553 {PIPE_FORMAT_L8_UNORM, L8_UNORM},
554 {PIPE_FORMAT_I8_UNORM, I8_UNORM},
555 {PIPE_FORMAT_L8A8_UNORM, L8A8_UNORM},
556 {PIPE_FORMAT_L16_UNORM, L16_UNORM},
557 {PIPE_FORMAT_UYVY, YCRCB_SWAPUVY},
559 {PIPE_FORMAT_L8_SRGB, L8_UNORM_SRGB},
560 {PIPE_FORMAT_L8A8_SRGB, L8A8_UNORM_SRGB},
562 {PIPE_FORMAT_DXT1_RGBA, BC1_UNORM},
563 {PIPE_FORMAT_DXT3_RGBA, BC2_UNORM},
564 {PIPE_FORMAT_DXT5_RGBA, BC3_UNORM},
566 {PIPE_FORMAT_DXT1_SRGBA, BC1_UNORM_SRGB},
567 {PIPE_FORMAT_DXT3_SRGBA, BC2_UNORM_SRGB},
568 {PIPE_FORMAT_DXT5_SRGBA, BC3_UNORM_SRGB},
570 {PIPE_FORMAT_RGTC1_UNORM, BC4_UNORM},
571 {PIPE_FORMAT_RGTC1_SNORM, BC4_SNORM},
572 {PIPE_FORMAT_RGTC2_UNORM, BC5_UNORM},
573 {PIPE_FORMAT_RGTC2_SNORM, BC5_SNORM},
575 {PIPE_FORMAT_L16A16_UNORM, L16A16_UNORM},
576 {PIPE_FORMAT_I16_UNORM, I16_UNORM},
577 {PIPE_FORMAT_L16_FLOAT, L16_FLOAT},
578 {PIPE_FORMAT_L16A16_FLOAT, L16A16_FLOAT},
579 {PIPE_FORMAT_I16_FLOAT, I16_FLOAT},
580 {PIPE_FORMAT_L32_FLOAT, L32_FLOAT},
581 {PIPE_FORMAT_L32A32_FLOAT, L32A32_FLOAT},
582 {PIPE_FORMAT_I32_FLOAT, I32_FLOAT},
584 {PIPE_FORMAT_I8_UINT, I8_UINT},
585 {PIPE_FORMAT_L8_UINT, L8_UINT},
586 {PIPE_FORMAT_L8A8_UINT, L8A8_UINT},
588 {PIPE_FORMAT_I8_SINT, I8_SINT},
589 {PIPE_FORMAT_L8_SINT, L8_SINT},
590 {PIPE_FORMAT_L8A8_SINT, L8A8_SINT},
595 auto it
= mesa2swr
.find(format
);
596 if (it
== mesa2swr
.end())
597 return (SWR_FORMAT
)-1;
603 swr_displaytarget_layout(struct swr_screen
*screen
, struct swr_resource
*res
)
605 struct sw_winsys
*winsys
= screen
->winsys
;
606 struct sw_displaytarget
*dt
;
608 const unsigned width
= align(res
->swr
.width
, res
->swr
.halign
);
609 const unsigned height
= align(res
->swr
.height
, res
->swr
.valign
);
612 dt
= winsys
->displaytarget_create(winsys
,
622 void *map
= winsys
->displaytarget_map(winsys
, dt
, 0);
624 res
->display_target
= dt
;
625 res
->swr
.xpBaseAddress
= (gfxptr_t
)map
;
627 /* Clear the display target surface */
629 memset(map
, 0, height
* stride
);
631 winsys
->displaytarget_unmap(winsys
, dt
);
637 swr_texture_layout(struct swr_screen
*screen
,
638 struct swr_resource
*res
,
641 struct pipe_resource
*pt
= &res
->base
;
643 pipe_format fmt
= pt
->format
;
644 const struct util_format_description
*desc
= util_format_description(fmt
);
646 res
->has_depth
= util_format_has_depth(desc
);
647 res
->has_stencil
= util_format_has_stencil(desc
);
649 if (res
->has_stencil
&& !res
->has_depth
)
650 fmt
= PIPE_FORMAT_R8_UINT
;
652 /* We always use the SWR layout. For 2D and 3D textures this looks like:
654 * |<------- pitch ------->|
655 * +=======================+-------
661 * +-----------+-----------+ |
663 * | Level 1 | L3L3 | |
665 * +===========+===========+-------
671 * +-----------+-----------+
675 * +===========+===========+
677 * The overall width in bytes is known as the pitch, while the overall
678 * height in rows is the qpitch. Array slices are laid out logically below
679 * one another, qpitch rows apart. For 3D surfaces, the "level" values are
680 * just invalid for the higher array numbers (since depth is also
681 * minified). 1D and 1D array surfaces are stored effectively the same way,
682 * except that pitch never plays into it. All the levels are logically
683 * adjacent to each other on the X axis. The qpitch becomes the number of
684 * elements between array slices, while the pitch is unused.
686 * Each level's sizes are subject to the valign and halign settings of the
687 * surface. For compressed formats that swr is unaware of, we will use an
688 * appropriately-sized uncompressed format, and scale the widths/heights.
690 * This surface is stored inside res->swr. For depth/stencil textures,
691 * res->secondary will have an identically-laid-out but R8_UINT-formatted
692 * stencil tree. In the Z32F_S8 case, the primary surface still has 64-bpp
693 * texels, to simplify map/unmap logic which copies the stencil values
697 res
->swr
.width
= pt
->width0
;
698 res
->swr
.height
= pt
->height0
;
699 res
->swr
.type
= swr_convert_target_type(pt
->target
);
700 res
->swr
.tileMode
= SWR_TILE_NONE
;
701 res
->swr
.format
= mesa_to_swr_format(fmt
);
702 res
->swr
.numSamples
= std::max(1u, pt
->nr_samples
);
704 if (pt
->bind
& (PIPE_BIND_RENDER_TARGET
| PIPE_BIND_DEPTH_STENCIL
)) {
705 res
->swr
.halign
= KNOB_MACROTILE_X_DIM
;
706 res
->swr
.valign
= KNOB_MACROTILE_Y_DIM
;
708 /* If SWR_MSAA_FORCE_ENABLE is set, turn on MSAA and override requested
709 * surface sample count. */
710 if (screen
->msaa_force_enable
) {
711 res
->swr
.numSamples
= screen
->msaa_max_count
;
712 swr_print_info("swr_texture_layout: forcing sample count: %d\n",
713 res
->swr
.numSamples
);
720 unsigned halign
= res
->swr
.halign
* util_format_get_blockwidth(fmt
);
721 unsigned width
= align(pt
->width0
, halign
);
722 if (pt
->target
== PIPE_TEXTURE_1D
|| pt
->target
== PIPE_TEXTURE_1D_ARRAY
) {
723 for (int level
= 1; level
<= pt
->last_level
; level
++)
724 width
+= align(u_minify(pt
->width0
, level
), halign
);
725 res
->swr
.pitch
= util_format_get_blocksize(fmt
);
726 res
->swr
.qpitch
= util_format_get_nblocksx(fmt
, width
);
728 // The pitch is the overall width of the texture in bytes. Most of the
729 // time this is the pitch of level 0 since all the other levels fit
730 // underneath it. However in some degenerate situations, the width of
731 // level1 + level2 may be larger. In that case, we use those
732 // widths. This can happen if, e.g. halign is 32, and the width of level
733 // 0 is 32 or less. In that case, the aligned levels 1 and 2 will also
734 // be 32 each, adding up to 64.
735 unsigned valign
= res
->swr
.valign
* util_format_get_blockheight(fmt
);
736 if (pt
->last_level
> 1) {
737 width
= std::max
<uint32_t>(
739 align(u_minify(pt
->width0
, 1), halign
) +
740 align(u_minify(pt
->width0
, 2), halign
));
742 res
->swr
.pitch
= util_format_get_stride(fmt
, width
);
744 // The qpitch is controlled by either the height of the second LOD, or
745 // the combination of all the later LODs.
746 unsigned height
= align(pt
->height0
, valign
);
747 if (pt
->last_level
== 1) {
748 height
+= align(u_minify(pt
->height0
, 1), valign
);
749 } else if (pt
->last_level
> 1) {
750 unsigned level1
= align(u_minify(pt
->height0
, 1), valign
);
752 for (int level
= 2; level
<= pt
->last_level
; level
++) {
753 level2
+= align(u_minify(pt
->height0
, level
), valign
);
755 height
+= std::max(level1
, level2
);
757 res
->swr
.qpitch
= util_format_get_nblocksy(fmt
, height
);
760 if (pt
->target
== PIPE_TEXTURE_3D
)
761 res
->swr
.depth
= pt
->depth0
;
763 res
->swr
.depth
= pt
->array_size
;
765 // Fix up swr format if necessary so that LOD offset computation works
766 if (res
->swr
.format
== (SWR_FORMAT
)-1) {
767 switch (util_format_get_blocksize(fmt
)) {
769 unreachable("Unexpected format block size");
770 case 1: res
->swr
.format
= R8_UINT
; break;
771 case 2: res
->swr
.format
= R16_UINT
; break;
772 case 4: res
->swr
.format
= R32_UINT
; break;
774 if (util_format_is_compressed(fmt
))
775 res
->swr
.format
= BC4_UNORM
;
777 res
->swr
.format
= R32G32_UINT
;
780 if (util_format_is_compressed(fmt
))
781 res
->swr
.format
= BC5_UNORM
;
783 res
->swr
.format
= R32G32B32A32_UINT
;
788 for (int level
= 0; level
<= pt
->last_level
; level
++) {
789 res
->mip_offsets
[level
] =
790 ComputeSurfaceOffset
<false>(0, 0, 0, 0, 0, level
, &res
->swr
);
793 size_t total_size
= (uint64_t)res
->swr
.depth
* res
->swr
.qpitch
*
794 res
->swr
.pitch
* res
->swr
.numSamples
;
796 // Let non-sampled textures (e.g. buffer objects) bypass the size limit
797 if (swr_resource_is_texture(&res
->base
) && total_size
> SWR_MAX_TEXTURE_SIZE
)
801 res
->swr
.xpBaseAddress
= (gfxptr_t
)AlignedMalloc(total_size
, 64);
802 if (!res
->swr
.xpBaseAddress
)
805 if (res
->has_depth
&& res
->has_stencil
) {
806 res
->secondary
= res
->swr
;
807 res
->secondary
.format
= R8_UINT
;
808 res
->secondary
.pitch
= res
->swr
.pitch
/ util_format_get_blocksize(fmt
);
810 for (int level
= 0; level
<= pt
->last_level
; level
++) {
811 res
->secondary_mip_offsets
[level
] =
812 ComputeSurfaceOffset
<false>(0, 0, 0, 0, 0, level
, &res
->secondary
);
815 total_size
= res
->secondary
.depth
* res
->secondary
.qpitch
*
816 res
->secondary
.pitch
* res
->secondary
.numSamples
;
818 res
->secondary
.xpBaseAddress
= (gfxptr_t
) AlignedMalloc(total_size
, 64);
819 if (!res
->secondary
.xpBaseAddress
) {
820 AlignedFree((void *)res
->swr
.xpBaseAddress
);
830 swr_can_create_resource(struct pipe_screen
*screen
,
831 const struct pipe_resource
*templat
)
833 struct swr_resource res
;
834 memset(&res
, 0, sizeof(res
));
836 return swr_texture_layout(swr_screen(screen
), &res
, false);
839 /* Helper function that conditionally creates a single-sample resolve resource
840 * and attaches it to main multisample resource. */
842 swr_create_resolve_resource(struct pipe_screen
*_screen
,
843 struct swr_resource
*msaa_res
)
845 struct swr_screen
*screen
= swr_screen(_screen
);
847 /* If resource is multisample, create a single-sample resolve resource */
848 if (msaa_res
->base
.nr_samples
> 1 || (screen
->msaa_force_enable
&&
849 !(msaa_res
->base
.flags
& SWR_RESOURCE_FLAG_ALT_SURFACE
))) {
851 /* Create a single-sample copy of the resource. Copy the original
852 * resource parameters and set flag to prevent recursion when re-calling
854 struct pipe_resource alt_template
= msaa_res
->base
;
855 alt_template
.nr_samples
= 0;
856 alt_template
.flags
|= SWR_RESOURCE_FLAG_ALT_SURFACE
;
858 /* Note: Display_target is a special single-sample resource, only the
859 * display_target has been created already. */
860 if (msaa_res
->base
.bind
& (PIPE_BIND_DISPLAY_TARGET
| PIPE_BIND_SCANOUT
861 | PIPE_BIND_SHARED
)) {
862 /* Allocate the multisample buffers. */
863 if (!swr_texture_layout(screen
, msaa_res
, true))
866 /* Alt resource will only be bound as PIPE_BIND_RENDER_TARGET
867 * remove the DISPLAY_TARGET, SCANOUT, and SHARED bindings */
868 alt_template
.bind
= PIPE_BIND_RENDER_TARGET
;
871 /* Allocate single-sample resolve surface */
872 struct pipe_resource
*alt
;
873 alt
= _screen
->resource_create(_screen
, &alt_template
);
877 /* Attach it to the multisample resource */
878 msaa_res
->resolve_target
= alt
;
880 /* Hang resolve surface state off the multisample surface state to so
881 * StoreTiles knows where to resolve the surface. */
882 msaa_res
->swr
.xpAuxBaseAddress
= (gfxptr_t
)&swr_resource(alt
)->swr
;
885 return true; /* success */
888 static struct pipe_resource
*
889 swr_resource_create(struct pipe_screen
*_screen
,
890 const struct pipe_resource
*templat
)
892 struct swr_screen
*screen
= swr_screen(_screen
);
893 struct swr_resource
*res
= CALLOC_STRUCT(swr_resource
);
897 res
->base
= *templat
;
898 pipe_reference_init(&res
->base
.reference
, 1);
899 res
->base
.screen
= &screen
->base
;
901 if (swr_resource_is_texture(&res
->base
)) {
902 if (res
->base
.bind
& (PIPE_BIND_DISPLAY_TARGET
| PIPE_BIND_SCANOUT
903 | PIPE_BIND_SHARED
)) {
904 /* displayable surface
905 * first call swr_texture_layout without allocating to finish
906 * filling out the SWR_SURFACE_STATE in res */
907 swr_texture_layout(screen
, res
, false);
908 if (!swr_displaytarget_layout(screen
, res
))
912 if (!swr_texture_layout(screen
, res
, true))
916 /* If resource was multisample, create resolve resource and attach
917 * it to multisample resource. */
918 if (!swr_create_resolve_resource(_screen
, res
))
922 /* other data (vertex buffer, const buffer, etc) */
923 assert(util_format_get_blocksize(templat
->format
) == 1);
924 assert(templat
->height0
== 1);
925 assert(templat
->depth0
== 1);
926 assert(templat
->last_level
== 0);
928 /* Easiest to just call swr_texture_layout, as it sets up
929 * SWR_SURFACE_STATE in res */
930 if (!swr_texture_layout(screen
, res
, true))
942 swr_resource_destroy(struct pipe_screen
*p_screen
, struct pipe_resource
*pt
)
944 struct swr_screen
*screen
= swr_screen(p_screen
);
945 struct swr_resource
*spr
= swr_resource(pt
);
947 if (spr
->display_target
) {
948 /* If resource is display target, winsys manages the buffer and will
949 * free it on displaytarget_destroy. */
950 swr_fence_finish(p_screen
, NULL
, screen
->flush_fence
, 0);
952 struct sw_winsys
*winsys
= screen
->winsys
;
953 winsys
->displaytarget_destroy(winsys
, spr
->display_target
);
955 if (spr
->swr
.numSamples
> 1) {
956 /* Free an attached resolve resource */
957 struct swr_resource
*alt
= swr_resource(spr
->resolve_target
);
958 swr_fence_work_free(screen
->flush_fence
, (void*)(alt
->swr
.xpBaseAddress
), true);
960 /* Free multisample buffer */
961 swr_fence_work_free(screen
->flush_fence
, (void*)(spr
->swr
.xpBaseAddress
), true);
964 /* For regular resources, defer deletion */
965 swr_resource_unused(pt
);
967 if (spr
->swr
.numSamples
> 1) {
968 /* Free an attached resolve resource */
969 struct swr_resource
*alt
= swr_resource(spr
->resolve_target
);
970 swr_fence_work_free(screen
->flush_fence
, (void*)(alt
->swr
.xpBaseAddress
), true);
973 swr_fence_work_free(screen
->flush_fence
, (void*)(spr
->swr
.xpBaseAddress
), true);
974 swr_fence_work_free(screen
->flush_fence
,
975 (void*)(spr
->secondary
.xpBaseAddress
), true);
977 /* If work queue grows too large, submit a fence to force queue to
978 * drain. This is mainly to decrease the amount of memory used by the
979 * piglit streaming-texture-leak test */
980 if (screen
->pipe
&& swr_fence(screen
->flush_fence
)->work
.count
> 64)
981 swr_fence_submit(swr_context(screen
->pipe
), screen
->flush_fence
);
989 swr_flush_frontbuffer(struct pipe_screen
*p_screen
,
990 struct pipe_resource
*resource
,
993 void *context_private
,
994 struct pipe_box
*sub_box
)
996 struct swr_screen
*screen
= swr_screen(p_screen
);
997 struct sw_winsys
*winsys
= screen
->winsys
;
998 struct swr_resource
*spr
= swr_resource(resource
);
999 struct pipe_context
*pipe
= screen
->pipe
;
1000 struct swr_context
*ctx
= swr_context(pipe
);
1003 swr_fence_finish(p_screen
, NULL
, screen
->flush_fence
, 0);
1004 swr_resource_unused(resource
);
1005 ctx
->api
.pfnSwrEndFrame(ctx
->swrContext
);
1008 /* Multisample resolved into resolve_target at flush with store_resource */
1009 if (pipe
&& spr
->swr
.numSamples
> 1) {
1010 struct pipe_resource
*resolve_target
= spr
->resolve_target
;
1012 /* Once resolved, copy into display target */
1013 SWR_SURFACE_STATE
*resolve
= &swr_resource(resolve_target
)->swr
;
1015 void *map
= winsys
->displaytarget_map(winsys
, spr
->display_target
,
1016 PIPE_TRANSFER_WRITE
);
1017 memcpy(map
, (void*)(resolve
->xpBaseAddress
), resolve
->pitch
* resolve
->height
);
1018 winsys
->displaytarget_unmap(winsys
, spr
->display_target
);
1021 debug_assert(spr
->display_target
);
1022 if (spr
->display_target
)
1023 winsys
->displaytarget_display(
1024 winsys
, spr
->display_target
, context_private
, sub_box
);
1029 swr_destroy_screen_internal(struct swr_screen
**screen
)
1031 struct pipe_screen
*p_screen
= &(*screen
)->base
;
1033 swr_fence_finish(p_screen
, NULL
, (*screen
)->flush_fence
, 0);
1034 swr_fence_reference(p_screen
, &(*screen
)->flush_fence
, NULL
);
1036 JitDestroyContext((*screen
)->hJitMgr
);
1038 if ((*screen
)->pLibrary
)
1039 util_dl_close((*screen
)->pLibrary
);
1047 swr_destroy_screen(struct pipe_screen
*p_screen
)
1049 struct swr_screen
*screen
= swr_screen(p_screen
);
1050 struct sw_winsys
*winsys
= screen
->winsys
;
1052 swr_print_info("SWR destroy screen!\n");
1054 if (winsys
->destroy
)
1055 winsys
->destroy(winsys
);
1057 swr_destroy_screen_internal(&screen
);
1062 swr_validate_env_options(struct swr_screen
*screen
)
1064 /* The client_copy_limit sets a maximum on the amount of user-buffer memory
1065 * copied to scratch space on a draw. Past this, the draw will access
1066 * user-buffer directly and then block. This is faster than queuing many
1067 * large client draws. */
1068 screen
->client_copy_limit
= SWR_CLIENT_COPY_LIMIT
;
1069 int client_copy_limit
=
1070 debug_get_num_option("SWR_CLIENT_COPY_LIMIT", SWR_CLIENT_COPY_LIMIT
);
1071 if (client_copy_limit
> 0)
1072 screen
->client_copy_limit
= client_copy_limit
;
1074 /* XXX msaa under development, disable by default for now */
1075 screen
->msaa_max_count
= 1; /* was SWR_MAX_NUM_MULTISAMPLES; */
1077 /* validate env override values, within range and power of 2 */
1078 int msaa_max_count
= debug_get_num_option("SWR_MSAA_MAX_COUNT", 1);
1079 if (msaa_max_count
!= 1) {
1080 if ((msaa_max_count
< 1) || (msaa_max_count
> SWR_MAX_NUM_MULTISAMPLES
)
1081 || !util_is_power_of_two_or_zero(msaa_max_count
)) {
1082 fprintf(stderr
, "SWR_MSAA_MAX_COUNT invalid: %d\n", msaa_max_count
);
1083 fprintf(stderr
, "must be power of 2 between 1 and %d" \
1084 " (or 1 to disable msaa)\n",
1085 SWR_MAX_NUM_MULTISAMPLES
);
1086 fprintf(stderr
, "(msaa disabled)\n");
1090 swr_print_info("SWR_MSAA_MAX_COUNT: %d\n", msaa_max_count
);
1092 screen
->msaa_max_count
= msaa_max_count
;
1095 screen
->msaa_force_enable
= debug_get_bool_option(
1096 "SWR_MSAA_FORCE_ENABLE", false);
1097 if (screen
->msaa_force_enable
)
1098 swr_print_info("SWR_MSAA_FORCE_ENABLE: true\n");
1102 struct pipe_screen
*
1103 swr_create_screen_internal(struct sw_winsys
*winsys
)
1105 struct swr_screen
*screen
= CALLOC_STRUCT(swr_screen
);
1110 if (!lp_build_init()) {
1115 screen
->winsys
= winsys
;
1116 screen
->base
.get_name
= swr_get_name
;
1117 screen
->base
.get_vendor
= swr_get_vendor
;
1118 screen
->base
.is_format_supported
= swr_is_format_supported
;
1119 screen
->base
.context_create
= swr_create_context
;
1120 screen
->base
.can_create_resource
= swr_can_create_resource
;
1122 screen
->base
.destroy
= swr_destroy_screen
;
1123 screen
->base
.get_param
= swr_get_param
;
1124 screen
->base
.get_shader_param
= swr_get_shader_param
;
1125 screen
->base
.get_paramf
= swr_get_paramf
;
1127 screen
->base
.resource_create
= swr_resource_create
;
1128 screen
->base
.resource_destroy
= swr_resource_destroy
;
1130 screen
->base
.flush_frontbuffer
= swr_flush_frontbuffer
;
1132 // Pass in "" for architecture for run-time determination
1133 screen
->hJitMgr
= JitCreateContext(KNOB_SIMD_WIDTH
, "", "swr");
1135 swr_fence_init(&screen
->base
);
1137 swr_validate_env_options(screen
);
1139 return &screen
->base
;