1 /****************************************************************************
2 * Copyright (C) 2015 Intel Corporation. All Rights Reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 ***************************************************************************/
24 #include "swr_context.h"
25 #include "swr_public.h"
26 #include "swr_screen.h"
27 #include "swr_resource.h"
28 #include "swr_fence.h"
29 #include "gen_knobs.h"
31 #include "pipe/p_screen.h"
32 #include "pipe/p_defines.h"
33 #include "util/u_memory.h"
34 #include "util/u_format.h"
35 #include "util/u_inlines.h"
36 #include "util/u_cpu_detect.h"
37 #include "util/u_format_s3tc.h"
38 #include "util/u_string.h"
40 #include "state_tracker/sw_winsys.h"
44 #include "memory/TilingFunctions.h"
51 * XXX Check max texture size values against core and sampler.
53 #define SWR_MAX_TEXTURE_SIZE (2 * 1024 * 1024 * 1024ULL) /* 2GB */
54 #define SWR_MAX_TEXTURE_2D_LEVELS 14 /* 8K x 8K for now */
55 #define SWR_MAX_TEXTURE_3D_LEVELS 12 /* 2K x 2K x 2K for now */
56 #define SWR_MAX_TEXTURE_CUBE_LEVELS 14 /* 8K x 8K for now */
57 #define SWR_MAX_TEXTURE_ARRAY_LAYERS 512 /* 8K x 512 / 8K x 8K x 512 */
59 /* Default max client_copy_limit */
60 #define SWR_CLIENT_COPY_LIMIT 8192
62 /* Flag indicates creation of alternate surface, to prevent recursive loop
63 * in resource creation when msaa_force_enable is set. */
64 #define SWR_RESOURCE_FLAG_ALT_SURFACE (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
68 swr_get_name(struct pipe_screen
*screen
)
71 util_snprintf(buf
, sizeof(buf
), "SWR (LLVM %u.%u, %u bits)",
72 HAVE_LLVM
>> 8, HAVE_LLVM
& 0xff,
73 lp_native_vector_width
);
78 swr_get_vendor(struct pipe_screen
*screen
)
80 return "Intel Corporation";
84 swr_is_format_supported(struct pipe_screen
*_screen
,
85 enum pipe_format format
,
86 enum pipe_texture_target target
,
87 unsigned sample_count
,
88 unsigned storage_sample_count
,
91 struct swr_screen
*screen
= swr_screen(_screen
);
92 struct sw_winsys
*winsys
= screen
->winsys
;
93 const struct util_format_description
*format_desc
;
95 assert(target
== PIPE_BUFFER
|| target
== PIPE_TEXTURE_1D
96 || target
== PIPE_TEXTURE_1D_ARRAY
97 || target
== PIPE_TEXTURE_2D
98 || target
== PIPE_TEXTURE_2D_ARRAY
99 || target
== PIPE_TEXTURE_RECT
100 || target
== PIPE_TEXTURE_3D
101 || target
== PIPE_TEXTURE_CUBE
102 || target
== PIPE_TEXTURE_CUBE_ARRAY
);
104 if (MAX2(1, sample_count
) != MAX2(1, storage_sample_count
))
107 format_desc
= util_format_description(format
);
111 if ((sample_count
> screen
->msaa_max_count
)
112 || !util_is_power_of_two_or_zero(sample_count
))
115 if (bind
& PIPE_BIND_DISPLAY_TARGET
) {
116 if (!winsys
->is_displaytarget_format_supported(winsys
, bind
, format
))
120 if (bind
& PIPE_BIND_RENDER_TARGET
) {
121 if (format_desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
)
124 if (mesa_to_swr_format(format
) == (SWR_FORMAT
)-1)
128 * Although possible, it is unnatural to render into compressed or YUV
129 * surfaces. So disable these here to avoid going into weird paths
130 * inside the state trackers.
132 if (format_desc
->block
.width
!= 1 || format_desc
->block
.height
!= 1)
136 if (bind
& PIPE_BIND_DEPTH_STENCIL
) {
137 if (format_desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
)
140 if (mesa_to_swr_format(format
) == (SWR_FORMAT
)-1)
144 if (format_desc
->layout
== UTIL_FORMAT_LAYOUT_BPTC
||
145 format_desc
->layout
== UTIL_FORMAT_LAYOUT_ASTC
) {
149 if (format_desc
->layout
== UTIL_FORMAT_LAYOUT_ETC
&&
150 format
!= PIPE_FORMAT_ETC1_RGB8
) {
158 swr_get_param(struct pipe_screen
*screen
, enum pipe_cap param
)
162 case PIPE_CAP_MAX_RENDER_TARGETS
:
163 return PIPE_MAX_COLOR_BUFS
;
164 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
165 return SWR_MAX_TEXTURE_2D_LEVELS
;
166 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
167 return SWR_MAX_TEXTURE_3D_LEVELS
;
168 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
169 return SWR_MAX_TEXTURE_CUBE_LEVELS
;
170 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
171 return MAX_SO_STREAMS
;
172 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
173 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
174 return MAX_ATTRIBUTES
* 4;
175 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
176 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
178 case PIPE_CAP_MAX_VERTEX_STREAMS
:
180 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
182 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
183 return SWR_MAX_TEXTURE_ARRAY_LAYERS
;
184 case PIPE_CAP_MIN_TEXEL_OFFSET
:
186 case PIPE_CAP_MAX_TEXEL_OFFSET
:
188 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
190 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY
:
192 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
194 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
196 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
198 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
200 case PIPE_CAP_MAX_VIEWPORTS
:
202 case PIPE_CAP_ENDIANNESS
:
203 return PIPE_ENDIAN_NATIVE
;
204 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
205 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
206 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE
:
209 /* supported features */
210 case PIPE_CAP_NPOT_TEXTURES
:
211 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
212 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS
:
214 case PIPE_CAP_POINT_SPRITE
:
215 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
216 case PIPE_CAP_OCCLUSION_QUERY
:
217 case PIPE_CAP_QUERY_TIME_ELAPSED
:
218 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
219 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
220 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE
:
221 case PIPE_CAP_TEXTURE_SWIZZLE
:
222 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
223 case PIPE_CAP_INDEP_BLEND_ENABLE
:
224 case PIPE_CAP_INDEP_BLEND_FUNC
:
225 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
226 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
227 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
228 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
229 case PIPE_CAP_PRIMITIVE_RESTART
:
230 case PIPE_CAP_TGSI_INSTANCEID
:
231 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
232 case PIPE_CAP_START_INSTANCE
:
233 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
234 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
235 case PIPE_CAP_CONDITIONAL_RENDER
:
236 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
237 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
238 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
239 case PIPE_CAP_USER_VERTEX_BUFFERS
:
240 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS
:
241 case PIPE_CAP_QUERY_TIMESTAMP
:
242 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
243 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
244 case PIPE_CAP_DRAW_INDIRECT
:
246 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
247 case PIPE_CAP_CLIP_HALFZ
:
248 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
249 case PIPE_CAP_DEPTH_BOUNDS_TEST
:
250 case PIPE_CAP_CLEAR_TEXTURE
:
251 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
252 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
253 case PIPE_CAP_CULL_DISTANCE
:
254 case PIPE_CAP_CUBE_MAP_ARRAY
:
255 case PIPE_CAP_DOUBLES
:
259 * If user has explicitly set max_sample_count = 1 (via SWR_MSAA_MAX_COUNT)
260 * then disable all MSAA support and go back to old (FAKE_SW_MSAA) caps. */
261 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
262 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE
:
263 return (swr_screen(screen
)->msaa_max_count
> 1) ? 1 : 0;
264 case PIPE_CAP_FAKE_SW_MSAA
:
265 return (swr_screen(screen
)->msaa_max_count
> 1) ? 0 : 1;
267 /* fetch jit change for 2-4GB buffers requires alignment */
268 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
269 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
270 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
273 /* unsupported features */
274 case PIPE_CAP_ANISOTROPIC_FILTER
:
275 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
276 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
277 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
278 case PIPE_CAP_TEXTURE_BARRIER
:
279 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
280 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
281 case PIPE_CAP_COMPUTE
:
282 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
283 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
284 case PIPE_CAP_TGSI_TEXCOORD
:
285 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
286 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
287 case PIPE_CAP_TEXTURE_GATHER_SM5
:
288 case PIPE_CAP_TEXTURE_QUERY_LOD
:
289 case PIPE_CAP_SAMPLE_SHADING
:
290 case PIPE_CAP_TEXTURE_GATHER_OFFSETS
:
291 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
292 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
293 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
294 case PIPE_CAP_VERTEXID_NOBASE
:
295 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY
:
296 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY
:
297 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
:
298 case PIPE_CAP_TGSI_TXQS
:
299 case PIPE_CAP_FORCE_PERSAMPLE_INTERP
:
300 case PIPE_CAP_SHAREABLE_SHADERS
:
301 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
:
302 case PIPE_CAP_DRAW_PARAMETERS
:
303 case PIPE_CAP_TGSI_PACK_HALF_FLOAT
:
304 case PIPE_CAP_MULTI_DRAW_INDIRECT
:
305 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS
:
306 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL
:
307 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL
:
308 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
:
309 case PIPE_CAP_INVALIDATE_BUFFER
:
310 case PIPE_CAP_GENERATE_MIPMAP
:
311 case PIPE_CAP_STRING_MARKER
:
312 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY
:
313 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS
:
314 case PIPE_CAP_QUERY_BUFFER_OBJECT
:
315 case PIPE_CAP_QUERY_MEMORY_INFO
:
316 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR
:
317 case PIPE_CAP_PCI_GROUP
:
318 case PIPE_CAP_PCI_BUS
:
319 case PIPE_CAP_PCI_DEVICE
:
320 case PIPE_CAP_PCI_FUNCTION
:
321 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT
:
322 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES
:
323 case PIPE_CAP_TGSI_VOTE
:
324 case PIPE_CAP_MAX_WINDOW_RECTANGLES
:
325 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED
:
326 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS
:
327 case PIPE_CAP_TGSI_ARRAY_COMPONENTS
:
328 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS
:
329 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
330 case PIPE_CAP_NATIVE_FENCE_FD
:
331 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY
:
332 case PIPE_CAP_TGSI_FS_FBFETCH
:
333 case PIPE_CAP_TGSI_MUL_ZERO_WINS
:
335 case PIPE_CAP_INT64_DIVMOD
:
336 case PIPE_CAP_TGSI_TEX_TXF_LZ
:
337 case PIPE_CAP_TGSI_CLOCK
:
338 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE
:
339 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE
:
340 case PIPE_CAP_TGSI_BALLOT
:
341 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT
:
342 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX
:
343 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION
:
344 case PIPE_CAP_POST_DEPTH_COVERAGE
:
345 case PIPE_CAP_BINDLESS_TEXTURE
:
346 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF
:
347 case PIPE_CAP_QUERY_SO_OVERFLOW
:
348 case PIPE_CAP_MEMOBJ
:
349 case PIPE_CAP_LOAD_CONSTBUF
:
350 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS
:
351 case PIPE_CAP_TILE_RASTER_ORDER
:
352 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES
:
353 case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS
:
354 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET
:
355 case PIPE_CAP_CONTEXT_PRIORITY_MASK
:
356 case PIPE_CAP_FENCE_SIGNAL
:
357 case PIPE_CAP_CONSTBUF0_FLAGS
:
358 case PIPE_CAP_PACKED_UNIFORMS
:
359 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES
:
360 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES
:
361 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES
:
362 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES
:
363 case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE
:
364 case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS
:
365 case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS
:
367 case PIPE_CAP_MAX_GS_INVOCATIONS
:
369 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE
:
372 case PIPE_CAP_VENDOR_ID
:
374 case PIPE_CAP_DEVICE_ID
:
376 case PIPE_CAP_ACCELERATED
:
378 case PIPE_CAP_VIDEO_MEMORY
: {
379 /* XXX: Do we want to return the full amount of system memory ? */
380 uint64_t system_memory
;
382 if (!os_get_total_physical_memory(&system_memory
))
385 return (int)(system_memory
>> 20);
389 /* should only get here on unhandled cases */
390 debug_printf("Unexpected PIPE_CAP %d query\n", param
);
395 swr_get_shader_param(struct pipe_screen
*screen
,
396 enum pipe_shader_type shader
,
397 enum pipe_shader_cap param
)
399 if (shader
== PIPE_SHADER_VERTEX
||
400 shader
== PIPE_SHADER_FRAGMENT
||
401 shader
== PIPE_SHADER_GEOMETRY
)
402 return gallivm_get_shader_param(param
);
404 // Todo: tesselation, compute
410 swr_get_paramf(struct pipe_screen
*screen
, enum pipe_capf param
)
413 case PIPE_CAPF_MAX_LINE_WIDTH
:
414 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
415 case PIPE_CAPF_MAX_POINT_WIDTH
:
416 return 255.0; /* arbitrary */
417 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
419 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
421 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
422 return 16.0; /* arbitrary */
423 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE
:
424 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE
:
425 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY
:
428 /* should only get here on unhandled cases */
429 debug_printf("Unexpected PIPE_CAPF %d query\n", param
);
434 mesa_to_swr_format(enum pipe_format format
)
436 static const std::map
<pipe_format
,SWR_FORMAT
> mesa2swr
= {
437 /* depth / stencil */
438 {PIPE_FORMAT_Z16_UNORM
, R16_UNORM
}, // z
439 {PIPE_FORMAT_Z32_FLOAT
, R32_FLOAT
}, // z
440 {PIPE_FORMAT_Z24_UNORM_S8_UINT
, R24_UNORM_X8_TYPELESS
}, // z
441 {PIPE_FORMAT_Z24X8_UNORM
, R24_UNORM_X8_TYPELESS
}, // z
442 {PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
, R32_FLOAT_X8X24_TYPELESS
}, // z
445 {PIPE_FORMAT_A8_UNORM
, A8_UNORM
},
446 {PIPE_FORMAT_A16_UNORM
, A16_UNORM
},
447 {PIPE_FORMAT_A16_FLOAT
, A16_FLOAT
},
448 {PIPE_FORMAT_A32_FLOAT
, A32_FLOAT
},
451 {PIPE_FORMAT_B5G6R5_UNORM
, B5G6R5_UNORM
},
452 {PIPE_FORMAT_B5G6R5_SRGB
, B5G6R5_UNORM_SRGB
},
453 {PIPE_FORMAT_B5G5R5A1_UNORM
, B5G5R5A1_UNORM
},
454 {PIPE_FORMAT_B5G5R5X1_UNORM
, B5G5R5X1_UNORM
},
455 {PIPE_FORMAT_B4G4R4A4_UNORM
, B4G4R4A4_UNORM
},
456 {PIPE_FORMAT_B8G8R8A8_UNORM
, B8G8R8A8_UNORM
},
457 {PIPE_FORMAT_B8G8R8A8_SRGB
, B8G8R8A8_UNORM_SRGB
},
458 {PIPE_FORMAT_B8G8R8X8_UNORM
, B8G8R8X8_UNORM
},
459 {PIPE_FORMAT_B8G8R8X8_SRGB
, B8G8R8X8_UNORM_SRGB
},
462 {PIPE_FORMAT_R10G10B10A2_UNORM
, R10G10B10A2_UNORM
},
463 {PIPE_FORMAT_R10G10B10A2_SNORM
, R10G10B10A2_SNORM
},
464 {PIPE_FORMAT_R10G10B10A2_USCALED
, R10G10B10A2_USCALED
},
465 {PIPE_FORMAT_R10G10B10A2_SSCALED
, R10G10B10A2_SSCALED
},
466 {PIPE_FORMAT_R10G10B10A2_UINT
, R10G10B10A2_UINT
},
469 {PIPE_FORMAT_R10G10B10X2_USCALED
, R10G10B10X2_USCALED
},
472 {PIPE_FORMAT_B10G10R10A2_UNORM
, B10G10R10A2_UNORM
},
473 {PIPE_FORMAT_B10G10R10A2_SNORM
, B10G10R10A2_SNORM
},
474 {PIPE_FORMAT_B10G10R10A2_USCALED
, B10G10R10A2_USCALED
},
475 {PIPE_FORMAT_B10G10R10A2_SSCALED
, B10G10R10A2_SSCALED
},
476 {PIPE_FORMAT_B10G10R10A2_UINT
, B10G10R10A2_UINT
},
479 {PIPE_FORMAT_B10G10R10X2_UNORM
, B10G10R10X2_UNORM
},
482 {PIPE_FORMAT_R11G11B10_FLOAT
, R11G11B10_FLOAT
},
484 /* 32 bits per component */
485 {PIPE_FORMAT_R32_FLOAT
, R32_FLOAT
},
486 {PIPE_FORMAT_R32G32_FLOAT
, R32G32_FLOAT
},
487 {PIPE_FORMAT_R32G32B32_FLOAT
, R32G32B32_FLOAT
},
488 {PIPE_FORMAT_R32G32B32A32_FLOAT
, R32G32B32A32_FLOAT
},
489 {PIPE_FORMAT_R32G32B32X32_FLOAT
, R32G32B32X32_FLOAT
},
491 {PIPE_FORMAT_R32_USCALED
, R32_USCALED
},
492 {PIPE_FORMAT_R32G32_USCALED
, R32G32_USCALED
},
493 {PIPE_FORMAT_R32G32B32_USCALED
, R32G32B32_USCALED
},
494 {PIPE_FORMAT_R32G32B32A32_USCALED
, R32G32B32A32_USCALED
},
496 {PIPE_FORMAT_R32_SSCALED
, R32_SSCALED
},
497 {PIPE_FORMAT_R32G32_SSCALED
, R32G32_SSCALED
},
498 {PIPE_FORMAT_R32G32B32_SSCALED
, R32G32B32_SSCALED
},
499 {PIPE_FORMAT_R32G32B32A32_SSCALED
, R32G32B32A32_SSCALED
},
501 {PIPE_FORMAT_R32_UINT
, R32_UINT
},
502 {PIPE_FORMAT_R32G32_UINT
, R32G32_UINT
},
503 {PIPE_FORMAT_R32G32B32_UINT
, R32G32B32_UINT
},
504 {PIPE_FORMAT_R32G32B32A32_UINT
, R32G32B32A32_UINT
},
506 {PIPE_FORMAT_R32_SINT
, R32_SINT
},
507 {PIPE_FORMAT_R32G32_SINT
, R32G32_SINT
},
508 {PIPE_FORMAT_R32G32B32_SINT
, R32G32B32_SINT
},
509 {PIPE_FORMAT_R32G32B32A32_SINT
, R32G32B32A32_SINT
},
511 /* 16 bits per component */
512 {PIPE_FORMAT_R16_UNORM
, R16_UNORM
},
513 {PIPE_FORMAT_R16G16_UNORM
, R16G16_UNORM
},
514 {PIPE_FORMAT_R16G16B16_UNORM
, R16G16B16_UNORM
},
515 {PIPE_FORMAT_R16G16B16A16_UNORM
, R16G16B16A16_UNORM
},
516 {PIPE_FORMAT_R16G16B16X16_UNORM
, R16G16B16X16_UNORM
},
518 {PIPE_FORMAT_R16_USCALED
, R16_USCALED
},
519 {PIPE_FORMAT_R16G16_USCALED
, R16G16_USCALED
},
520 {PIPE_FORMAT_R16G16B16_USCALED
, R16G16B16_USCALED
},
521 {PIPE_FORMAT_R16G16B16A16_USCALED
, R16G16B16A16_USCALED
},
523 {PIPE_FORMAT_R16_SNORM
, R16_SNORM
},
524 {PIPE_FORMAT_R16G16_SNORM
, R16G16_SNORM
},
525 {PIPE_FORMAT_R16G16B16_SNORM
, R16G16B16_SNORM
},
526 {PIPE_FORMAT_R16G16B16A16_SNORM
, R16G16B16A16_SNORM
},
528 {PIPE_FORMAT_R16_SSCALED
, R16_SSCALED
},
529 {PIPE_FORMAT_R16G16_SSCALED
, R16G16_SSCALED
},
530 {PIPE_FORMAT_R16G16B16_SSCALED
, R16G16B16_SSCALED
},
531 {PIPE_FORMAT_R16G16B16A16_SSCALED
, R16G16B16A16_SSCALED
},
533 {PIPE_FORMAT_R16_UINT
, R16_UINT
},
534 {PIPE_FORMAT_R16G16_UINT
, R16G16_UINT
},
535 {PIPE_FORMAT_R16G16B16_UINT
, R16G16B16_UINT
},
536 {PIPE_FORMAT_R16G16B16A16_UINT
, R16G16B16A16_UINT
},
538 {PIPE_FORMAT_R16_SINT
, R16_SINT
},
539 {PIPE_FORMAT_R16G16_SINT
, R16G16_SINT
},
540 {PIPE_FORMAT_R16G16B16_SINT
, R16G16B16_SINT
},
541 {PIPE_FORMAT_R16G16B16A16_SINT
, R16G16B16A16_SINT
},
543 {PIPE_FORMAT_R16_FLOAT
, R16_FLOAT
},
544 {PIPE_FORMAT_R16G16_FLOAT
, R16G16_FLOAT
},
545 {PIPE_FORMAT_R16G16B16_FLOAT
, R16G16B16_FLOAT
},
546 {PIPE_FORMAT_R16G16B16A16_FLOAT
, R16G16B16A16_FLOAT
},
547 {PIPE_FORMAT_R16G16B16X16_FLOAT
, R16G16B16X16_FLOAT
},
549 /* 8 bits per component */
550 {PIPE_FORMAT_R8_UNORM
, R8_UNORM
},
551 {PIPE_FORMAT_R8G8_UNORM
, R8G8_UNORM
},
552 {PIPE_FORMAT_R8G8B8_UNORM
, R8G8B8_UNORM
},
553 {PIPE_FORMAT_R8G8B8_SRGB
, R8G8B8_UNORM_SRGB
},
554 {PIPE_FORMAT_R8G8B8A8_UNORM
, R8G8B8A8_UNORM
},
555 {PIPE_FORMAT_R8G8B8A8_SRGB
, R8G8B8A8_UNORM_SRGB
},
556 {PIPE_FORMAT_R8G8B8X8_UNORM
, R8G8B8X8_UNORM
},
557 {PIPE_FORMAT_R8G8B8X8_SRGB
, R8G8B8X8_UNORM_SRGB
},
559 {PIPE_FORMAT_R8_USCALED
, R8_USCALED
},
560 {PIPE_FORMAT_R8G8_USCALED
, R8G8_USCALED
},
561 {PIPE_FORMAT_R8G8B8_USCALED
, R8G8B8_USCALED
},
562 {PIPE_FORMAT_R8G8B8A8_USCALED
, R8G8B8A8_USCALED
},
564 {PIPE_FORMAT_R8_SNORM
, R8_SNORM
},
565 {PIPE_FORMAT_R8G8_SNORM
, R8G8_SNORM
},
566 {PIPE_FORMAT_R8G8B8_SNORM
, R8G8B8_SNORM
},
567 {PIPE_FORMAT_R8G8B8A8_SNORM
, R8G8B8A8_SNORM
},
569 {PIPE_FORMAT_R8_SSCALED
, R8_SSCALED
},
570 {PIPE_FORMAT_R8G8_SSCALED
, R8G8_SSCALED
},
571 {PIPE_FORMAT_R8G8B8_SSCALED
, R8G8B8_SSCALED
},
572 {PIPE_FORMAT_R8G8B8A8_SSCALED
, R8G8B8A8_SSCALED
},
574 {PIPE_FORMAT_R8_UINT
, R8_UINT
},
575 {PIPE_FORMAT_R8G8_UINT
, R8G8_UINT
},
576 {PIPE_FORMAT_R8G8B8_UINT
, R8G8B8_UINT
},
577 {PIPE_FORMAT_R8G8B8A8_UINT
, R8G8B8A8_UINT
},
579 {PIPE_FORMAT_R8_SINT
, R8_SINT
},
580 {PIPE_FORMAT_R8G8_SINT
, R8G8_SINT
},
581 {PIPE_FORMAT_R8G8B8_SINT
, R8G8B8_SINT
},
582 {PIPE_FORMAT_R8G8B8A8_SINT
, R8G8B8A8_SINT
},
584 /* These formats are valid for vertex data, but should not be used
585 * for render targets.
588 {PIPE_FORMAT_R32_FIXED
, R32_SFIXED
},
589 {PIPE_FORMAT_R32G32_FIXED
, R32G32_SFIXED
},
590 {PIPE_FORMAT_R32G32B32_FIXED
, R32G32B32_SFIXED
},
591 {PIPE_FORMAT_R32G32B32A32_FIXED
, R32G32B32A32_SFIXED
},
593 {PIPE_FORMAT_R64_FLOAT
, R64_FLOAT
},
594 {PIPE_FORMAT_R64G64_FLOAT
, R64G64_FLOAT
},
595 {PIPE_FORMAT_R64G64B64_FLOAT
, R64G64B64_FLOAT
},
596 {PIPE_FORMAT_R64G64B64A64_FLOAT
, R64G64B64A64_FLOAT
},
598 /* These formats have entries in SWR but don't have Load/StoreTile
599 * implementations. That means these aren't renderable, and thus having
600 * a mapping entry here is detrimental.
604 {PIPE_FORMAT_L8_UNORM, L8_UNORM},
605 {PIPE_FORMAT_I8_UNORM, I8_UNORM},
606 {PIPE_FORMAT_L8A8_UNORM, L8A8_UNORM},
607 {PIPE_FORMAT_L16_UNORM, L16_UNORM},
608 {PIPE_FORMAT_UYVY, YCRCB_SWAPUVY},
610 {PIPE_FORMAT_L8_SRGB, L8_UNORM_SRGB},
611 {PIPE_FORMAT_L8A8_SRGB, L8A8_UNORM_SRGB},
613 {PIPE_FORMAT_DXT1_RGBA, BC1_UNORM},
614 {PIPE_FORMAT_DXT3_RGBA, BC2_UNORM},
615 {PIPE_FORMAT_DXT5_RGBA, BC3_UNORM},
617 {PIPE_FORMAT_DXT1_SRGBA, BC1_UNORM_SRGB},
618 {PIPE_FORMAT_DXT3_SRGBA, BC2_UNORM_SRGB},
619 {PIPE_FORMAT_DXT5_SRGBA, BC3_UNORM_SRGB},
621 {PIPE_FORMAT_RGTC1_UNORM, BC4_UNORM},
622 {PIPE_FORMAT_RGTC1_SNORM, BC4_SNORM},
623 {PIPE_FORMAT_RGTC2_UNORM, BC5_UNORM},
624 {PIPE_FORMAT_RGTC2_SNORM, BC5_SNORM},
626 {PIPE_FORMAT_L16A16_UNORM, L16A16_UNORM},
627 {PIPE_FORMAT_I16_UNORM, I16_UNORM},
628 {PIPE_FORMAT_L16_FLOAT, L16_FLOAT},
629 {PIPE_FORMAT_L16A16_FLOAT, L16A16_FLOAT},
630 {PIPE_FORMAT_I16_FLOAT, I16_FLOAT},
631 {PIPE_FORMAT_L32_FLOAT, L32_FLOAT},
632 {PIPE_FORMAT_L32A32_FLOAT, L32A32_FLOAT},
633 {PIPE_FORMAT_I32_FLOAT, I32_FLOAT},
635 {PIPE_FORMAT_I8_UINT, I8_UINT},
636 {PIPE_FORMAT_L8_UINT, L8_UINT},
637 {PIPE_FORMAT_L8A8_UINT, L8A8_UINT},
639 {PIPE_FORMAT_I8_SINT, I8_SINT},
640 {PIPE_FORMAT_L8_SINT, L8_SINT},
641 {PIPE_FORMAT_L8A8_SINT, L8A8_SINT},
646 auto it
= mesa2swr
.find(format
);
647 if (it
== mesa2swr
.end())
648 return (SWR_FORMAT
)-1;
654 swr_displaytarget_layout(struct swr_screen
*screen
, struct swr_resource
*res
)
656 struct sw_winsys
*winsys
= screen
->winsys
;
657 struct sw_displaytarget
*dt
;
659 const unsigned width
= align(res
->swr
.width
, res
->swr
.halign
);
660 const unsigned height
= align(res
->swr
.height
, res
->swr
.valign
);
663 dt
= winsys
->displaytarget_create(winsys
,
673 void *map
= winsys
->displaytarget_map(winsys
, dt
, 0);
675 res
->display_target
= dt
;
676 res
->swr
.xpBaseAddress
= (gfxptr_t
)map
;
678 /* Clear the display target surface */
680 memset(map
, 0, height
* stride
);
682 winsys
->displaytarget_unmap(winsys
, dt
);
688 swr_texture_layout(struct swr_screen
*screen
,
689 struct swr_resource
*res
,
692 struct pipe_resource
*pt
= &res
->base
;
694 pipe_format fmt
= pt
->format
;
695 const struct util_format_description
*desc
= util_format_description(fmt
);
697 res
->has_depth
= util_format_has_depth(desc
);
698 res
->has_stencil
= util_format_has_stencil(desc
);
700 if (res
->has_stencil
&& !res
->has_depth
)
701 fmt
= PIPE_FORMAT_R8_UINT
;
703 /* We always use the SWR layout. For 2D and 3D textures this looks like:
705 * |<------- pitch ------->|
706 * +=======================+-------
712 * +-----------+-----------+ |
714 * | Level 1 | L3L3 | |
716 * +===========+===========+-------
722 * +-----------+-----------+
726 * +===========+===========+
728 * The overall width in bytes is known as the pitch, while the overall
729 * height in rows is the qpitch. Array slices are laid out logically below
730 * one another, qpitch rows apart. For 3D surfaces, the "level" values are
731 * just invalid for the higher array numbers (since depth is also
732 * minified). 1D and 1D array surfaces are stored effectively the same way,
733 * except that pitch never plays into it. All the levels are logically
734 * adjacent to each other on the X axis. The qpitch becomes the number of
735 * elements between array slices, while the pitch is unused.
737 * Each level's sizes are subject to the valign and halign settings of the
738 * surface. For compressed formats that swr is unaware of, we will use an
739 * appropriately-sized uncompressed format, and scale the widths/heights.
741 * This surface is stored inside res->swr. For depth/stencil textures,
742 * res->secondary will have an identically-laid-out but R8_UINT-formatted
743 * stencil tree. In the Z32F_S8 case, the primary surface still has 64-bpp
744 * texels, to simplify map/unmap logic which copies the stencil values
748 res
->swr
.width
= pt
->width0
;
749 res
->swr
.height
= pt
->height0
;
750 res
->swr
.type
= swr_convert_target_type(pt
->target
);
751 res
->swr
.tileMode
= SWR_TILE_NONE
;
752 res
->swr
.format
= mesa_to_swr_format(fmt
);
753 res
->swr
.numSamples
= std::max(1u, pt
->nr_samples
);
755 if (pt
->bind
& (PIPE_BIND_RENDER_TARGET
| PIPE_BIND_DEPTH_STENCIL
)) {
756 res
->swr
.halign
= KNOB_MACROTILE_X_DIM
;
757 res
->swr
.valign
= KNOB_MACROTILE_Y_DIM
;
759 /* If SWR_MSAA_FORCE_ENABLE is set, turn on MSAA and override requested
760 * surface sample count. */
761 if (screen
->msaa_force_enable
) {
762 res
->swr
.numSamples
= screen
->msaa_max_count
;
763 fprintf(stderr
,"swr_texture_layout: forcing sample count: %d\n",
764 res
->swr
.numSamples
);
771 unsigned halign
= res
->swr
.halign
* util_format_get_blockwidth(fmt
);
772 unsigned width
= align(pt
->width0
, halign
);
773 if (pt
->target
== PIPE_TEXTURE_1D
|| pt
->target
== PIPE_TEXTURE_1D_ARRAY
) {
774 for (int level
= 1; level
<= pt
->last_level
; level
++)
775 width
+= align(u_minify(pt
->width0
, level
), halign
);
776 res
->swr
.pitch
= util_format_get_blocksize(fmt
);
777 res
->swr
.qpitch
= util_format_get_nblocksx(fmt
, width
);
779 // The pitch is the overall width of the texture in bytes. Most of the
780 // time this is the pitch of level 0 since all the other levels fit
781 // underneath it. However in some degenerate situations, the width of
782 // level1 + level2 may be larger. In that case, we use those
783 // widths. This can happen if, e.g. halign is 32, and the width of level
784 // 0 is 32 or less. In that case, the aligned levels 1 and 2 will also
785 // be 32 each, adding up to 64.
786 unsigned valign
= res
->swr
.valign
* util_format_get_blockheight(fmt
);
787 if (pt
->last_level
> 1) {
788 width
= std::max
<uint32_t>(
790 align(u_minify(pt
->width0
, 1), halign
) +
791 align(u_minify(pt
->width0
, 2), halign
));
793 res
->swr
.pitch
= util_format_get_stride(fmt
, width
);
795 // The qpitch is controlled by either the height of the second LOD, or
796 // the combination of all the later LODs.
797 unsigned height
= align(pt
->height0
, valign
);
798 if (pt
->last_level
== 1) {
799 height
+= align(u_minify(pt
->height0
, 1), valign
);
800 } else if (pt
->last_level
> 1) {
801 unsigned level1
= align(u_minify(pt
->height0
, 1), valign
);
803 for (int level
= 2; level
<= pt
->last_level
; level
++) {
804 level2
+= align(u_minify(pt
->height0
, level
), valign
);
806 height
+= std::max(level1
, level2
);
808 res
->swr
.qpitch
= util_format_get_nblocksy(fmt
, height
);
811 if (pt
->target
== PIPE_TEXTURE_3D
)
812 res
->swr
.depth
= pt
->depth0
;
814 res
->swr
.depth
= pt
->array_size
;
816 // Fix up swr format if necessary so that LOD offset computation works
817 if (res
->swr
.format
== (SWR_FORMAT
)-1) {
818 switch (util_format_get_blocksize(fmt
)) {
820 unreachable("Unexpected format block size");
821 case 1: res
->swr
.format
= R8_UINT
; break;
822 case 2: res
->swr
.format
= R16_UINT
; break;
823 case 4: res
->swr
.format
= R32_UINT
; break;
825 if (util_format_is_compressed(fmt
))
826 res
->swr
.format
= BC4_UNORM
;
828 res
->swr
.format
= R32G32_UINT
;
831 if (util_format_is_compressed(fmt
))
832 res
->swr
.format
= BC5_UNORM
;
834 res
->swr
.format
= R32G32B32A32_UINT
;
839 for (int level
= 0; level
<= pt
->last_level
; level
++) {
840 res
->mip_offsets
[level
] =
841 ComputeSurfaceOffset
<false>(0, 0, 0, 0, 0, level
, &res
->swr
);
844 size_t total_size
= (uint64_t)res
->swr
.depth
* res
->swr
.qpitch
*
845 res
->swr
.pitch
* res
->swr
.numSamples
;
846 if (total_size
> SWR_MAX_TEXTURE_SIZE
)
850 res
->swr
.xpBaseAddress
= (gfxptr_t
)AlignedMalloc(total_size
, 64);
851 if (!res
->swr
.xpBaseAddress
)
854 if (res
->has_depth
&& res
->has_stencil
) {
855 res
->secondary
= res
->swr
;
856 res
->secondary
.format
= R8_UINT
;
857 res
->secondary
.pitch
= res
->swr
.pitch
/ util_format_get_blocksize(fmt
);
859 for (int level
= 0; level
<= pt
->last_level
; level
++) {
860 res
->secondary_mip_offsets
[level
] =
861 ComputeSurfaceOffset
<false>(0, 0, 0, 0, 0, level
, &res
->secondary
);
864 total_size
= res
->secondary
.depth
* res
->secondary
.qpitch
*
865 res
->secondary
.pitch
* res
->secondary
.numSamples
;
867 res
->secondary
.xpBaseAddress
= (gfxptr_t
) AlignedMalloc(total_size
, 64);
868 if (!res
->secondary
.xpBaseAddress
) {
869 AlignedFree((void *)res
->swr
.xpBaseAddress
);
879 swr_can_create_resource(struct pipe_screen
*screen
,
880 const struct pipe_resource
*templat
)
882 struct swr_resource res
;
883 memset(&res
, 0, sizeof(res
));
885 return swr_texture_layout(swr_screen(screen
), &res
, false);
888 /* Helper function that conditionally creates a single-sample resolve resource
889 * and attaches it to main multisample resource. */
891 swr_create_resolve_resource(struct pipe_screen
*_screen
,
892 struct swr_resource
*msaa_res
)
894 struct swr_screen
*screen
= swr_screen(_screen
);
896 /* If resource is multisample, create a single-sample resolve resource */
897 if (msaa_res
->base
.nr_samples
> 1 || (screen
->msaa_force_enable
&&
898 !(msaa_res
->base
.flags
& SWR_RESOURCE_FLAG_ALT_SURFACE
))) {
900 /* Create a single-sample copy of the resource. Copy the original
901 * resource parameters and set flag to prevent recursion when re-calling
903 struct pipe_resource alt_template
= msaa_res
->base
;
904 alt_template
.nr_samples
= 0;
905 alt_template
.flags
|= SWR_RESOURCE_FLAG_ALT_SURFACE
;
907 /* Note: Display_target is a special single-sample resource, only the
908 * display_target has been created already. */
909 if (msaa_res
->base
.bind
& (PIPE_BIND_DISPLAY_TARGET
| PIPE_BIND_SCANOUT
910 | PIPE_BIND_SHARED
)) {
911 /* Allocate the multisample buffers. */
912 if (!swr_texture_layout(screen
, msaa_res
, true))
915 /* Alt resource will only be bound as PIPE_BIND_RENDER_TARGET
916 * remove the DISPLAY_TARGET, SCANOUT, and SHARED bindings */
917 alt_template
.bind
= PIPE_BIND_RENDER_TARGET
;
920 /* Allocate single-sample resolve surface */
921 struct pipe_resource
*alt
;
922 alt
= _screen
->resource_create(_screen
, &alt_template
);
926 /* Attach it to the multisample resource */
927 msaa_res
->resolve_target
= alt
;
929 /* Hang resolve surface state off the multisample surface state to so
930 * StoreTiles knows where to resolve the surface. */
931 msaa_res
->swr
.xpAuxBaseAddress
= (gfxptr_t
)&swr_resource(alt
)->swr
;
934 return true; /* success */
937 static struct pipe_resource
*
938 swr_resource_create(struct pipe_screen
*_screen
,
939 const struct pipe_resource
*templat
)
941 struct swr_screen
*screen
= swr_screen(_screen
);
942 struct swr_resource
*res
= CALLOC_STRUCT(swr_resource
);
946 res
->base
= *templat
;
947 pipe_reference_init(&res
->base
.reference
, 1);
948 res
->base
.screen
= &screen
->base
;
950 if (swr_resource_is_texture(&res
->base
)) {
951 if (res
->base
.bind
& (PIPE_BIND_DISPLAY_TARGET
| PIPE_BIND_SCANOUT
952 | PIPE_BIND_SHARED
)) {
953 /* displayable surface
954 * first call swr_texture_layout without allocating to finish
955 * filling out the SWR_SURFACE_STATE in res */
956 swr_texture_layout(screen
, res
, false);
957 if (!swr_displaytarget_layout(screen
, res
))
961 if (!swr_texture_layout(screen
, res
, true))
965 /* If resource was multisample, create resolve resource and attach
966 * it to multisample resource. */
967 if (!swr_create_resolve_resource(_screen
, res
))
971 /* other data (vertex buffer, const buffer, etc) */
972 assert(util_format_get_blocksize(templat
->format
) == 1);
973 assert(templat
->height0
== 1);
974 assert(templat
->depth0
== 1);
975 assert(templat
->last_level
== 0);
977 /* Easiest to just call swr_texture_layout, as it sets up
978 * SWR_SURFACE_STATE in res */
979 if (!swr_texture_layout(screen
, res
, true))
991 swr_resource_destroy(struct pipe_screen
*p_screen
, struct pipe_resource
*pt
)
993 struct swr_screen
*screen
= swr_screen(p_screen
);
994 struct swr_resource
*spr
= swr_resource(pt
);
996 if (spr
->display_target
) {
997 /* If resource is display target, winsys manages the buffer and will
998 * free it on displaytarget_destroy. */
999 swr_fence_finish(p_screen
, NULL
, screen
->flush_fence
, 0);
1001 struct sw_winsys
*winsys
= screen
->winsys
;
1002 winsys
->displaytarget_destroy(winsys
, spr
->display_target
);
1004 if (spr
->swr
.numSamples
> 1) {
1005 /* Free an attached resolve resource */
1006 struct swr_resource
*alt
= swr_resource(spr
->resolve_target
);
1007 swr_fence_work_free(screen
->flush_fence
, (void*)(alt
->swr
.xpBaseAddress
), true);
1009 /* Free multisample buffer */
1010 swr_fence_work_free(screen
->flush_fence
, (void*)(spr
->swr
.xpBaseAddress
), true);
1013 /* For regular resources, defer deletion */
1014 swr_resource_unused(pt
);
1016 if (spr
->swr
.numSamples
> 1) {
1017 /* Free an attached resolve resource */
1018 struct swr_resource
*alt
= swr_resource(spr
->resolve_target
);
1019 swr_fence_work_free(screen
->flush_fence
, (void*)(alt
->swr
.xpBaseAddress
), true);
1022 swr_fence_work_free(screen
->flush_fence
, (void*)(spr
->swr
.xpBaseAddress
), true);
1023 swr_fence_work_free(screen
->flush_fence
,
1024 (void*)(spr
->secondary
.xpBaseAddress
), true);
1026 /* If work queue grows too large, submit a fence to force queue to
1027 * drain. This is mainly to decrease the amount of memory used by the
1028 * piglit streaming-texture-leak test */
1029 if (screen
->pipe
&& swr_fence(screen
->flush_fence
)->work
.count
> 64)
1030 swr_fence_submit(swr_context(screen
->pipe
), screen
->flush_fence
);
1038 swr_flush_frontbuffer(struct pipe_screen
*p_screen
,
1039 struct pipe_resource
*resource
,
1042 void *context_private
,
1043 struct pipe_box
*sub_box
)
1045 struct swr_screen
*screen
= swr_screen(p_screen
);
1046 struct sw_winsys
*winsys
= screen
->winsys
;
1047 struct swr_resource
*spr
= swr_resource(resource
);
1048 struct pipe_context
*pipe
= screen
->pipe
;
1049 struct swr_context
*ctx
= swr_context(pipe
);
1052 swr_fence_finish(p_screen
, NULL
, screen
->flush_fence
, 0);
1053 swr_resource_unused(resource
);
1054 ctx
->api
.pfnSwrEndFrame(ctx
->swrContext
);
1057 /* Multisample resolved into resolve_target at flush with store_resource */
1058 if (pipe
&& spr
->swr
.numSamples
> 1) {
1059 struct pipe_resource
*resolve_target
= spr
->resolve_target
;
1061 /* Once resolved, copy into display target */
1062 SWR_SURFACE_STATE
*resolve
= &swr_resource(resolve_target
)->swr
;
1064 void *map
= winsys
->displaytarget_map(winsys
, spr
->display_target
,
1065 PIPE_TRANSFER_WRITE
);
1066 memcpy(map
, (void*)(resolve
->xpBaseAddress
), resolve
->pitch
* resolve
->height
);
1067 winsys
->displaytarget_unmap(winsys
, spr
->display_target
);
1070 debug_assert(spr
->display_target
);
1071 if (spr
->display_target
)
1072 winsys
->displaytarget_display(
1073 winsys
, spr
->display_target
, context_private
, sub_box
);
1078 swr_destroy_screen_internal(struct swr_screen
**screen
)
1080 struct pipe_screen
*p_screen
= &(*screen
)->base
;
1082 swr_fence_finish(p_screen
, NULL
, (*screen
)->flush_fence
, 0);
1083 swr_fence_reference(p_screen
, &(*screen
)->flush_fence
, NULL
);
1085 JitDestroyContext((*screen
)->hJitMgr
);
1087 if ((*screen
)->pLibrary
)
1088 util_dl_close((*screen
)->pLibrary
);
1096 swr_destroy_screen(struct pipe_screen
*p_screen
)
1098 struct swr_screen
*screen
= swr_screen(p_screen
);
1099 struct sw_winsys
*winsys
= screen
->winsys
;
1101 fprintf(stderr
, "SWR destroy screen!\n");
1103 if (winsys
->destroy
)
1104 winsys
->destroy(winsys
);
1106 swr_destroy_screen_internal(&screen
);
1111 swr_validate_env_options(struct swr_screen
*screen
)
1113 /* The client_copy_limit sets a maximum on the amount of user-buffer memory
1114 * copied to scratch space on a draw. Past this, the draw will access
1115 * user-buffer directly and then block. This is faster than queuing many
1116 * large client draws. */
1117 screen
->client_copy_limit
= SWR_CLIENT_COPY_LIMIT
;
1118 int client_copy_limit
=
1119 debug_get_num_option("SWR_CLIENT_COPY_LIMIT", SWR_CLIENT_COPY_LIMIT
);
1120 if (client_copy_limit
> 0)
1121 screen
->client_copy_limit
= client_copy_limit
;
1123 /* XXX msaa under development, disable by default for now */
1124 screen
->msaa_max_count
= 1; /* was SWR_MAX_NUM_MULTISAMPLES; */
1126 /* validate env override values, within range and power of 2 */
1127 int msaa_max_count
= debug_get_num_option("SWR_MSAA_MAX_COUNT", 1);
1128 if (msaa_max_count
!= 1) {
1129 if ((msaa_max_count
< 1) || (msaa_max_count
> SWR_MAX_NUM_MULTISAMPLES
)
1130 || !util_is_power_of_two_or_zero(msaa_max_count
)) {
1131 fprintf(stderr
, "SWR_MSAA_MAX_COUNT invalid: %d\n", msaa_max_count
);
1132 fprintf(stderr
, "must be power of 2 between 1 and %d" \
1133 " (or 1 to disable msaa)\n",
1134 SWR_MAX_NUM_MULTISAMPLES
);
1138 fprintf(stderr
, "SWR_MSAA_MAX_COUNT: %d\n", msaa_max_count
);
1139 if (msaa_max_count
== 1)
1140 fprintf(stderr
, "(msaa disabled)\n");
1142 screen
->msaa_max_count
= msaa_max_count
;
1145 screen
->msaa_force_enable
= debug_get_bool_option(
1146 "SWR_MSAA_FORCE_ENABLE", false);
1147 if (screen
->msaa_force_enable
)
1148 fprintf(stderr
, "SWR_MSAA_FORCE_ENABLE: true\n");
1152 struct pipe_screen
*
1153 swr_create_screen_internal(struct sw_winsys
*winsys
)
1155 struct swr_screen
*screen
= CALLOC_STRUCT(swr_screen
);
1160 if (!lp_build_init()) {
1165 screen
->winsys
= winsys
;
1166 screen
->base
.get_name
= swr_get_name
;
1167 screen
->base
.get_vendor
= swr_get_vendor
;
1168 screen
->base
.is_format_supported
= swr_is_format_supported
;
1169 screen
->base
.context_create
= swr_create_context
;
1170 screen
->base
.can_create_resource
= swr_can_create_resource
;
1172 screen
->base
.destroy
= swr_destroy_screen
;
1173 screen
->base
.get_param
= swr_get_param
;
1174 screen
->base
.get_shader_param
= swr_get_shader_param
;
1175 screen
->base
.get_paramf
= swr_get_paramf
;
1177 screen
->base
.resource_create
= swr_resource_create
;
1178 screen
->base
.resource_destroy
= swr_resource_destroy
;
1180 screen
->base
.flush_frontbuffer
= swr_flush_frontbuffer
;
1182 // Pass in "" for architecture for run-time determination
1183 screen
->hJitMgr
= JitCreateContext(KNOB_SIMD_WIDTH
, "", "swr");
1185 swr_fence_init(&screen
->base
);
1187 swr_validate_env_options(screen
);
1189 return &screen
->base
;