1 /****************************************************************************
2 * Copyright (C) 2015 Intel Corporation. All Rights Reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 ***************************************************************************/
24 #include "pipe/p_screen.h"
25 #include "pipe/p_defines.h"
26 #include "util/u_memory.h"
27 #include "util/u_format.h"
28 #include "util/u_inlines.h"
29 #include "util/u_cpu_detect.h"
30 #include "util/u_format_s3tc.h"
32 #include "state_tracker/sw_winsys.h"
35 #include "gallivm/lp_bld_limits.h"
38 #include "swr_public.h"
39 #include "swr_screen.h"
40 #include "swr_context.h"
41 #include "swr_resource.h"
42 #include "swr_fence.h"
43 #include "gen_knobs.h"
50 /* MSVC case instensitive compare */
51 #if defined(PIPE_CC_MSVC)
52 #define strcasecmp lstrcmpiA
57 * XXX Check max texture size values against core and sampler.
59 #define SWR_MAX_TEXTURE_SIZE (4 * 1024 * 1024 * 1024ULL) /* 4GB */
60 #define SWR_MAX_TEXTURE_2D_LEVELS 14 /* 8K x 8K for now */
61 #define SWR_MAX_TEXTURE_3D_LEVELS 12 /* 2K x 2K x 2K for now */
62 #define SWR_MAX_TEXTURE_CUBE_LEVELS 14 /* 8K x 8K for now */
63 #define SWR_MAX_TEXTURE_ARRAY_LAYERS 512 /* 8K x 512 / 8K x 8K x 512 */
66 swr_get_name(struct pipe_screen
*screen
)
72 swr_get_vendor(struct pipe_screen
*screen
)
74 return "Intel Corporation";
78 swr_is_format_supported(struct pipe_screen
*screen
,
79 enum pipe_format format
,
80 enum pipe_texture_target target
,
81 unsigned sample_count
,
84 struct sw_winsys
*winsys
= swr_screen(screen
)->winsys
;
85 const struct util_format_description
*format_desc
;
87 assert(target
== PIPE_BUFFER
|| target
== PIPE_TEXTURE_1D
88 || target
== PIPE_TEXTURE_1D_ARRAY
89 || target
== PIPE_TEXTURE_2D
90 || target
== PIPE_TEXTURE_2D_ARRAY
91 || target
== PIPE_TEXTURE_RECT
92 || target
== PIPE_TEXTURE_3D
93 || target
== PIPE_TEXTURE_CUBE
94 || target
== PIPE_TEXTURE_CUBE_ARRAY
);
96 format_desc
= util_format_description(format
);
100 if (sample_count
> 1)
104 & (PIPE_BIND_DISPLAY_TARGET
| PIPE_BIND_SCANOUT
| PIPE_BIND_SHARED
)) {
105 if (!winsys
->is_displaytarget_format_supported(winsys
, bind
, format
))
109 if (bind
& PIPE_BIND_RENDER_TARGET
) {
110 if (format_desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
)
113 if (mesa_to_swr_format(format
) == (SWR_FORMAT
)-1)
117 * Although possible, it is unnatural to render into compressed or YUV
118 * surfaces. So disable these here to avoid going into weird paths
119 * inside the state trackers.
121 if (format_desc
->block
.width
!= 1 || format_desc
->block
.height
!= 1)
125 if (bind
& PIPE_BIND_DEPTH_STENCIL
) {
126 if (format_desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
)
129 if (mesa_to_swr_format(format
) == (SWR_FORMAT
)-1)
133 if (format_desc
->layout
== UTIL_FORMAT_LAYOUT_BPTC
||
134 format_desc
->layout
== UTIL_FORMAT_LAYOUT_ASTC
) {
138 if (format_desc
->layout
== UTIL_FORMAT_LAYOUT_ETC
&&
139 format
!= PIPE_FORMAT_ETC1_RGB8
) {
143 if (format_desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
144 return util_format_s3tc_enabled
;
151 swr_get_param(struct pipe_screen
*screen
, enum pipe_cap param
)
154 case PIPE_CAP_NPOT_TEXTURES
:
155 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
156 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS
:
158 case PIPE_CAP_TWO_SIDED_STENCIL
:
162 case PIPE_CAP_ANISOTROPIC_FILTER
:
164 case PIPE_CAP_POINT_SPRITE
:
166 case PIPE_CAP_MAX_RENDER_TARGETS
:
167 return PIPE_MAX_COLOR_BUFS
;
168 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
170 case PIPE_CAP_OCCLUSION_QUERY
:
171 case PIPE_CAP_QUERY_TIME_ELAPSED
:
172 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
174 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
176 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
178 case PIPE_CAP_TEXTURE_SWIZZLE
:
180 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
182 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
183 return SWR_MAX_TEXTURE_2D_LEVELS
;
184 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
185 return SWR_MAX_TEXTURE_3D_LEVELS
;
186 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
187 return SWR_MAX_TEXTURE_CUBE_LEVELS
;
188 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
190 case PIPE_CAP_INDEP_BLEND_ENABLE
:
192 case PIPE_CAP_INDEP_BLEND_FUNC
:
194 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
195 return 0; // Don't support lower left frag coord.
196 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
197 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
198 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
200 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
202 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
203 return MAX_SO_STREAMS
;
204 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
205 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
206 return MAX_ATTRIBUTES
;
207 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
208 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
210 case PIPE_CAP_MAX_VERTEX_STREAMS
:
212 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
214 case PIPE_CAP_PRIMITIVE_RESTART
:
216 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
218 case PIPE_CAP_TGSI_INSTANCEID
:
219 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
220 case PIPE_CAP_START_INSTANCE
:
222 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
223 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
225 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
226 return SWR_MAX_TEXTURE_ARRAY_LAYERS
;
227 case PIPE_CAP_MIN_TEXEL_OFFSET
:
229 case PIPE_CAP_MAX_TEXEL_OFFSET
:
231 case PIPE_CAP_CONDITIONAL_RENDER
:
233 case PIPE_CAP_TEXTURE_BARRIER
:
235 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
236 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
: /* draw module */
237 case PIPE_CAP_VERTEX_COLOR_CLAMPED
: /* draw module */
239 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
241 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
243 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
245 case PIPE_CAP_COMPUTE
:
247 case PIPE_CAP_USER_VERTEX_BUFFERS
:
248 case PIPE_CAP_USER_INDEX_BUFFERS
:
249 case PIPE_CAP_USER_CONSTANT_BUFFERS
:
250 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
251 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
253 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
255 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
256 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
257 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
258 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
259 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
261 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
263 case PIPE_CAP_QUERY_TIMESTAMP
:
265 case PIPE_CAP_CUBE_MAP_ARRAY
:
267 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
269 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
271 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
273 case PIPE_CAP_TGSI_TEXCOORD
:
274 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
276 case PIPE_CAP_MAX_VIEWPORTS
:
278 case PIPE_CAP_ENDIANNESS
:
279 return PIPE_ENDIAN_NATIVE
;
280 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
281 case PIPE_CAP_TEXTURE_GATHER_SM5
:
283 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
285 case PIPE_CAP_TEXTURE_QUERY_LOD
:
286 case PIPE_CAP_SAMPLE_SHADING
:
287 case PIPE_CAP_TEXTURE_GATHER_OFFSETS
:
288 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
289 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
290 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
292 case PIPE_CAP_FAKE_SW_MSAA
:
294 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
295 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
297 case PIPE_CAP_DRAW_INDIRECT
:
300 case PIPE_CAP_VENDOR_ID
:
302 case PIPE_CAP_DEVICE_ID
:
304 case PIPE_CAP_ACCELERATED
:
306 case PIPE_CAP_VIDEO_MEMORY
: {
307 /* XXX: Do we want to return the full amount of system memory ? */
308 uint64_t system_memory
;
310 if (!os_get_total_physical_memory(&system_memory
))
313 return (int)(system_memory
>> 20);
317 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
319 case PIPE_CAP_CLIP_HALFZ
:
321 case PIPE_CAP_VERTEXID_NOBASE
:
323 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
325 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE
:
327 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY
:
329 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY
:
331 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
:
333 case PIPE_CAP_DEPTH_BOUNDS_TEST
:
335 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
336 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
338 case PIPE_CAP_CULL_DISTANCE
:
340 case PIPE_CAP_TGSI_TXQS
:
341 case PIPE_CAP_FORCE_PERSAMPLE_INTERP
:
342 case PIPE_CAP_SHAREABLE_SHADERS
:
343 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
:
344 case PIPE_CAP_CLEAR_TEXTURE
:
345 case PIPE_CAP_DRAW_PARAMETERS
:
346 case PIPE_CAP_TGSI_PACK_HALF_FLOAT
:
347 case PIPE_CAP_MULTI_DRAW_INDIRECT
:
348 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS
:
349 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL
:
350 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL
:
351 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
:
352 case PIPE_CAP_INVALIDATE_BUFFER
:
353 case PIPE_CAP_GENERATE_MIPMAP
:
354 case PIPE_CAP_STRING_MARKER
:
355 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY
:
356 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS
:
357 case PIPE_CAP_QUERY_BUFFER_OBJECT
:
358 case PIPE_CAP_QUERY_MEMORY_INFO
:
359 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR
:
360 case PIPE_CAP_PCI_GROUP
:
361 case PIPE_CAP_PCI_BUS
:
362 case PIPE_CAP_PCI_DEVICE
:
363 case PIPE_CAP_PCI_FUNCTION
:
364 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT
:
365 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES
:
366 case PIPE_CAP_TGSI_VOTE
:
367 case PIPE_CAP_MAX_WINDOW_RECTANGLES
:
368 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED
:
369 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS
:
370 case PIPE_CAP_TGSI_ARRAY_COMPONENTS
:
374 /* should only get here on unhandled cases */
375 debug_printf("Unexpected PIPE_CAP %d query\n", param
);
380 swr_get_shader_param(struct pipe_screen
*screen
,
382 enum pipe_shader_cap param
)
384 if (shader
== PIPE_SHADER_VERTEX
|| shader
== PIPE_SHADER_FRAGMENT
)
385 return gallivm_get_shader_param(param
);
387 // Todo: geometry, tesselation, compute
393 swr_get_paramf(struct pipe_screen
*screen
, enum pipe_capf param
)
396 case PIPE_CAPF_MAX_LINE_WIDTH
:
397 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
398 case PIPE_CAPF_MAX_POINT_WIDTH
:
399 return 255.0; /* arbitrary */
400 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
402 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
404 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
406 case PIPE_CAPF_GUARD_BAND_LEFT
:
407 case PIPE_CAPF_GUARD_BAND_TOP
:
408 case PIPE_CAPF_GUARD_BAND_RIGHT
:
409 case PIPE_CAPF_GUARD_BAND_BOTTOM
:
412 /* should only get here on unhandled cases */
413 debug_printf("Unexpected PIPE_CAPF %d query\n", param
);
418 mesa_to_swr_format(enum pipe_format format
)
420 static const std::map
<pipe_format
,SWR_FORMAT
> mesa2swr
= {
421 {PIPE_FORMAT_NONE
, (SWR_FORMAT
)-1},
422 {PIPE_FORMAT_B8G8R8A8_UNORM
, B8G8R8A8_UNORM
},
423 {PIPE_FORMAT_B8G8R8X8_UNORM
, B8G8R8X8_UNORM
},
424 {PIPE_FORMAT_A8R8G8B8_UNORM
, (SWR_FORMAT
)-1},
425 {PIPE_FORMAT_X8R8G8B8_UNORM
, (SWR_FORMAT
)-1},
426 {PIPE_FORMAT_B5G5R5A1_UNORM
, B5G5R5A1_UNORM
},
427 {PIPE_FORMAT_B4G4R4A4_UNORM
, B4G4R4A4_UNORM
},
428 {PIPE_FORMAT_B5G6R5_UNORM
, B5G6R5_UNORM
},
429 {PIPE_FORMAT_R10G10B10A2_UNORM
, R10G10B10A2_UNORM
},
430 {PIPE_FORMAT_L8_UNORM
, L8_UNORM
},
431 {PIPE_FORMAT_A8_UNORM
, A8_UNORM
},
432 {PIPE_FORMAT_I8_UNORM
, I8_UNORM
},
433 {PIPE_FORMAT_L8A8_UNORM
, L8A8_UNORM
},
434 {PIPE_FORMAT_L16_UNORM
, L16_UNORM
},
435 {PIPE_FORMAT_UYVY
, YCRCB_SWAPUVY
},
436 {PIPE_FORMAT_YUYV
, (SWR_FORMAT
)-1},
437 {PIPE_FORMAT_Z16_UNORM
, R16_UNORM
}, // z
438 {PIPE_FORMAT_Z32_UNORM
, (SWR_FORMAT
)-1},
439 {PIPE_FORMAT_Z32_FLOAT
, R32_FLOAT
}, // z
440 {PIPE_FORMAT_Z24_UNORM_S8_UINT
, R24_UNORM_X8_TYPELESS
}, // z
441 {PIPE_FORMAT_S8_UINT_Z24_UNORM
, (SWR_FORMAT
)-1},
442 {PIPE_FORMAT_Z24X8_UNORM
, R24_UNORM_X8_TYPELESS
}, // z
443 {PIPE_FORMAT_X8Z24_UNORM
, (SWR_FORMAT
)-1},
444 {PIPE_FORMAT_S8_UINT
, (SWR_FORMAT
)-1},
445 {PIPE_FORMAT_R64_FLOAT
, (SWR_FORMAT
)-1},
446 {PIPE_FORMAT_R64G64_FLOAT
, (SWR_FORMAT
)-1},
447 {PIPE_FORMAT_R64G64B64_FLOAT
, (SWR_FORMAT
)-1},
448 {PIPE_FORMAT_R64G64B64A64_FLOAT
, (SWR_FORMAT
)-1},
449 {PIPE_FORMAT_R32_FLOAT
, R32_FLOAT
},
450 {PIPE_FORMAT_R32G32_FLOAT
, R32G32_FLOAT
},
451 {PIPE_FORMAT_R32G32B32_FLOAT
, R32G32B32_FLOAT
},
452 {PIPE_FORMAT_R32G32B32A32_FLOAT
, R32G32B32A32_FLOAT
},
453 {PIPE_FORMAT_R32_UNORM
, (SWR_FORMAT
)-1},
454 {PIPE_FORMAT_R32G32_UNORM
, (SWR_FORMAT
)-1},
455 {PIPE_FORMAT_R32G32B32_UNORM
, (SWR_FORMAT
)-1},
456 {PIPE_FORMAT_R32G32B32A32_UNORM
, (SWR_FORMAT
)-1},
457 {PIPE_FORMAT_R32_USCALED
, R32_USCALED
},
458 {PIPE_FORMAT_R32G32_USCALED
, R32G32_USCALED
},
459 {PIPE_FORMAT_R32G32B32_USCALED
, R32G32B32_USCALED
},
460 {PIPE_FORMAT_R32G32B32A32_USCALED
, R32G32B32A32_USCALED
},
461 {PIPE_FORMAT_R32_SNORM
, (SWR_FORMAT
)-1},
462 {PIPE_FORMAT_R32G32_SNORM
, (SWR_FORMAT
)-1},
463 {PIPE_FORMAT_R32G32B32_SNORM
, (SWR_FORMAT
)-1},
464 {PIPE_FORMAT_R32G32B32A32_SNORM
, (SWR_FORMAT
)-1},
465 {PIPE_FORMAT_R32_SSCALED
, R32_SSCALED
},
466 {PIPE_FORMAT_R32G32_SSCALED
, R32G32_SSCALED
},
467 {PIPE_FORMAT_R32G32B32_SSCALED
, R32G32B32_SSCALED
},
468 {PIPE_FORMAT_R32G32B32A32_SSCALED
, R32G32B32A32_SSCALED
},
469 {PIPE_FORMAT_R16_UNORM
, R16_UNORM
},
470 {PIPE_FORMAT_R16G16_UNORM
, R16G16_UNORM
},
471 {PIPE_FORMAT_R16G16B16_UNORM
, R16G16B16_UNORM
},
472 {PIPE_FORMAT_R16G16B16A16_UNORM
, R16G16B16A16_UNORM
},
473 {PIPE_FORMAT_R16_USCALED
, R16_USCALED
},
474 {PIPE_FORMAT_R16G16_USCALED
, R16G16_USCALED
},
475 {PIPE_FORMAT_R16G16B16_USCALED
, R16G16B16_USCALED
},
476 {PIPE_FORMAT_R16G16B16A16_USCALED
, R16G16B16A16_USCALED
},
477 {PIPE_FORMAT_R16_SNORM
, R16_SNORM
},
478 {PIPE_FORMAT_R16G16_SNORM
, R16G16_SNORM
},
479 {PIPE_FORMAT_R16G16B16_SNORM
, R16G16B16_SNORM
},
480 {PIPE_FORMAT_R16G16B16A16_SNORM
, R16G16B16A16_SNORM
},
481 {PIPE_FORMAT_R16_SSCALED
, R16_SSCALED
},
482 {PIPE_FORMAT_R16G16_SSCALED
, R16G16_SSCALED
},
483 {PIPE_FORMAT_R16G16B16_SSCALED
, R16G16B16_SSCALED
},
484 {PIPE_FORMAT_R16G16B16A16_SSCALED
, R16G16B16A16_SSCALED
},
485 {PIPE_FORMAT_R8_UNORM
, R8_UNORM
},
486 {PIPE_FORMAT_R8G8_UNORM
, R8G8_UNORM
},
487 {PIPE_FORMAT_R8G8B8_UNORM
, R8G8B8_UNORM
},
488 {PIPE_FORMAT_R8G8B8A8_UNORM
, R8G8B8A8_UNORM
},
489 {PIPE_FORMAT_X8B8G8R8_UNORM
, (SWR_FORMAT
)-1},
490 {PIPE_FORMAT_R8_USCALED
, R8_USCALED
},
491 {PIPE_FORMAT_R8G8_USCALED
, R8G8_USCALED
},
492 {PIPE_FORMAT_R8G8B8_USCALED
, R8G8B8_USCALED
},
493 {PIPE_FORMAT_R8G8B8A8_USCALED
, R8G8B8A8_USCALED
},
494 {PIPE_FORMAT_R8_SNORM
, R8_SNORM
},
495 {PIPE_FORMAT_R8G8_SNORM
, R8G8_SNORM
},
496 {PIPE_FORMAT_R8G8B8_SNORM
, R8G8B8_SNORM
},
497 {PIPE_FORMAT_R8G8B8A8_SNORM
, R8G8B8A8_SNORM
},
498 {PIPE_FORMAT_R8_SSCALED
, R8_SSCALED
},
499 {PIPE_FORMAT_R8G8_SSCALED
, R8G8_SSCALED
},
500 {PIPE_FORMAT_R8G8B8_SSCALED
, R8G8B8_SSCALED
},
501 {PIPE_FORMAT_R8G8B8A8_SSCALED
, R8G8B8A8_SSCALED
},
502 {PIPE_FORMAT_R32_FIXED
, (SWR_FORMAT
)-1},
503 {PIPE_FORMAT_R32G32_FIXED
, (SWR_FORMAT
)-1},
504 {PIPE_FORMAT_R32G32B32_FIXED
, (SWR_FORMAT
)-1},
505 {PIPE_FORMAT_R32G32B32A32_FIXED
, (SWR_FORMAT
)-1},
506 {PIPE_FORMAT_R16_FLOAT
, R16_FLOAT
},
507 {PIPE_FORMAT_R16G16_FLOAT
, R16G16_FLOAT
},
508 {PIPE_FORMAT_R16G16B16_FLOAT
, R16G16B16_FLOAT
},
509 {PIPE_FORMAT_R16G16B16A16_FLOAT
, R16G16B16A16_FLOAT
},
511 {PIPE_FORMAT_L8_SRGB
, L8_UNORM_SRGB
},
512 {PIPE_FORMAT_L8A8_SRGB
, L8A8_UNORM_SRGB
},
513 {PIPE_FORMAT_R8G8B8_SRGB
, R8G8B8_UNORM_SRGB
},
514 {PIPE_FORMAT_A8B8G8R8_SRGB
, (SWR_FORMAT
)-1},
515 {PIPE_FORMAT_X8B8G8R8_SRGB
, (SWR_FORMAT
)-1},
516 {PIPE_FORMAT_B8G8R8A8_SRGB
, B8G8R8A8_UNORM_SRGB
},
517 {PIPE_FORMAT_B8G8R8X8_SRGB
, B8G8R8X8_UNORM_SRGB
},
518 {PIPE_FORMAT_A8R8G8B8_SRGB
, (SWR_FORMAT
)-1},
519 {PIPE_FORMAT_X8R8G8B8_SRGB
, (SWR_FORMAT
)-1},
520 {PIPE_FORMAT_R8G8B8A8_SRGB
, R8G8B8A8_UNORM_SRGB
},
522 {PIPE_FORMAT_DXT1_RGB
, (SWR_FORMAT
)-1},
523 {PIPE_FORMAT_DXT1_RGBA
, BC1_UNORM
},
524 {PIPE_FORMAT_DXT3_RGBA
, BC2_UNORM
},
525 {PIPE_FORMAT_DXT5_RGBA
, BC3_UNORM
},
527 {PIPE_FORMAT_DXT1_SRGB
, (SWR_FORMAT
)-1},
528 {PIPE_FORMAT_DXT1_SRGBA
, BC1_UNORM_SRGB
},
529 {PIPE_FORMAT_DXT3_SRGBA
, BC2_UNORM_SRGB
},
530 {PIPE_FORMAT_DXT5_SRGBA
, BC3_UNORM_SRGB
},
532 {PIPE_FORMAT_RGTC1_UNORM
, BC4_UNORM
},
533 {PIPE_FORMAT_RGTC1_SNORM
, BC4_SNORM
},
534 {PIPE_FORMAT_RGTC2_UNORM
, BC5_UNORM
},
535 {PIPE_FORMAT_RGTC2_SNORM
, BC5_SNORM
},
537 {PIPE_FORMAT_R8G8_B8G8_UNORM
, (SWR_FORMAT
)-1},
538 {PIPE_FORMAT_G8R8_G8B8_UNORM
, (SWR_FORMAT
)-1},
540 {PIPE_FORMAT_R8SG8SB8UX8U_NORM
, (SWR_FORMAT
)-1},
541 {PIPE_FORMAT_R5SG5SB6U_NORM
, (SWR_FORMAT
)-1},
543 {PIPE_FORMAT_A8B8G8R8_UNORM
, (SWR_FORMAT
)-1},
544 {PIPE_FORMAT_B5G5R5X1_UNORM
, B5G5R5X1_UNORM
},
545 {PIPE_FORMAT_R10G10B10A2_USCALED
, R10G10B10A2_USCALED
},
546 {PIPE_FORMAT_R11G11B10_FLOAT
, R11G11B10_FLOAT
},
547 {PIPE_FORMAT_R9G9B9E5_FLOAT
, R9G9B9E5_SHAREDEXP
},
548 {PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
, R32_FLOAT_X8X24_TYPELESS
}, // z
549 {PIPE_FORMAT_R1_UNORM
, (SWR_FORMAT
)-1},
550 {PIPE_FORMAT_R10G10B10X2_USCALED
, R10G10B10X2_USCALED
},
551 {PIPE_FORMAT_R10G10B10X2_SNORM
, (SWR_FORMAT
)-1},
552 {PIPE_FORMAT_L4A4_UNORM
, (SWR_FORMAT
)-1},
553 {PIPE_FORMAT_B10G10R10A2_UNORM
, B10G10R10A2_UNORM
},
554 {PIPE_FORMAT_R10SG10SB10SA2U_NORM
, (SWR_FORMAT
)-1},
555 {PIPE_FORMAT_R8G8Bx_SNORM
, (SWR_FORMAT
)-1},
556 {PIPE_FORMAT_R8G8B8X8_UNORM
, R8G8B8X8_UNORM
},
557 {PIPE_FORMAT_B4G4R4X4_UNORM
, (SWR_FORMAT
)-1},
559 {PIPE_FORMAT_X24S8_UINT
, (SWR_FORMAT
)-1},
560 {PIPE_FORMAT_S8X24_UINT
, (SWR_FORMAT
)-1},
561 {PIPE_FORMAT_X32_S8X24_UINT
, (SWR_FORMAT
)-1},
563 {PIPE_FORMAT_B2G3R3_UNORM
, (SWR_FORMAT
)-1},
564 {PIPE_FORMAT_L16A16_UNORM
, L16A16_UNORM
},
565 {PIPE_FORMAT_A16_UNORM
, A16_UNORM
},
566 {PIPE_FORMAT_I16_UNORM
, I16_UNORM
},
568 {PIPE_FORMAT_LATC1_UNORM
, (SWR_FORMAT
)-1},
569 {PIPE_FORMAT_LATC1_SNORM
, (SWR_FORMAT
)-1},
570 {PIPE_FORMAT_LATC2_UNORM
, (SWR_FORMAT
)-1},
571 {PIPE_FORMAT_LATC2_SNORM
, (SWR_FORMAT
)-1},
573 {PIPE_FORMAT_A8_SNORM
, (SWR_FORMAT
)-1},
574 {PIPE_FORMAT_L8_SNORM
, (SWR_FORMAT
)-1},
575 {PIPE_FORMAT_L8A8_SNORM
, (SWR_FORMAT
)-1},
576 {PIPE_FORMAT_I8_SNORM
, (SWR_FORMAT
)-1},
577 {PIPE_FORMAT_A16_SNORM
, (SWR_FORMAT
)-1},
578 {PIPE_FORMAT_L16_SNORM
, (SWR_FORMAT
)-1},
579 {PIPE_FORMAT_L16A16_SNORM
, (SWR_FORMAT
)-1},
580 {PIPE_FORMAT_I16_SNORM
, (SWR_FORMAT
)-1},
582 {PIPE_FORMAT_A16_FLOAT
, A16_FLOAT
},
583 {PIPE_FORMAT_L16_FLOAT
, L16_FLOAT
},
584 {PIPE_FORMAT_L16A16_FLOAT
, L16A16_FLOAT
},
585 {PIPE_FORMAT_I16_FLOAT
, I16_FLOAT
},
586 {PIPE_FORMAT_A32_FLOAT
, A32_FLOAT
},
587 {PIPE_FORMAT_L32_FLOAT
, L32_FLOAT
},
588 {PIPE_FORMAT_L32A32_FLOAT
, L32A32_FLOAT
},
589 {PIPE_FORMAT_I32_FLOAT
, I32_FLOAT
},
591 {PIPE_FORMAT_YV12
, (SWR_FORMAT
)-1},
592 {PIPE_FORMAT_YV16
, (SWR_FORMAT
)-1},
593 {PIPE_FORMAT_IYUV
, (SWR_FORMAT
)-1},
594 {PIPE_FORMAT_NV12
, (SWR_FORMAT
)-1},
595 {PIPE_FORMAT_NV21
, (SWR_FORMAT
)-1},
597 {PIPE_FORMAT_A4R4_UNORM
, (SWR_FORMAT
)-1},
598 {PIPE_FORMAT_R4A4_UNORM
, (SWR_FORMAT
)-1},
599 {PIPE_FORMAT_R8A8_UNORM
, (SWR_FORMAT
)-1},
600 {PIPE_FORMAT_A8R8_UNORM
, (SWR_FORMAT
)-1},
602 {PIPE_FORMAT_R10G10B10A2_SSCALED
, R10G10B10A2_SSCALED
},
603 {PIPE_FORMAT_R10G10B10A2_SNORM
, R10G10B10A2_SNORM
},
605 {PIPE_FORMAT_B10G10R10A2_USCALED
, B10G10R10A2_USCALED
},
606 {PIPE_FORMAT_B10G10R10A2_SSCALED
, B10G10R10A2_SSCALED
},
607 {PIPE_FORMAT_B10G10R10A2_SNORM
, B10G10R10A2_SNORM
},
609 {PIPE_FORMAT_R8_UINT
, R8_UINT
},
610 {PIPE_FORMAT_R8G8_UINT
, R8G8_UINT
},
611 {PIPE_FORMAT_R8G8B8_UINT
, R8G8B8_UINT
},
612 {PIPE_FORMAT_R8G8B8A8_UINT
, R8G8B8A8_UINT
},
614 {PIPE_FORMAT_R8_SINT
, R8_SINT
},
615 {PIPE_FORMAT_R8G8_SINT
, R8G8_SINT
},
616 {PIPE_FORMAT_R8G8B8_SINT
, R8G8B8_SINT
},
617 {PIPE_FORMAT_R8G8B8A8_SINT
, R8G8B8A8_SINT
},
619 {PIPE_FORMAT_R16_UINT
, R16_UINT
},
620 {PIPE_FORMAT_R16G16_UINT
, R16G16_UINT
},
621 {PIPE_FORMAT_R16G16B16_UINT
, R16G16B16_UINT
},
622 {PIPE_FORMAT_R16G16B16A16_UINT
, R16G16B16A16_UINT
},
624 {PIPE_FORMAT_R16_SINT
, R16_SINT
},
625 {PIPE_FORMAT_R16G16_SINT
, R16G16_SINT
},
626 {PIPE_FORMAT_R16G16B16_SINT
, R16G16B16_SINT
},
627 {PIPE_FORMAT_R16G16B16A16_SINT
, R16G16B16A16_SINT
},
629 {PIPE_FORMAT_R32_UINT
, R32_UINT
},
630 {PIPE_FORMAT_R32G32_UINT
, R32G32_UINT
},
631 {PIPE_FORMAT_R32G32B32_UINT
, R32G32B32_UINT
},
632 {PIPE_FORMAT_R32G32B32A32_UINT
, R32G32B32A32_UINT
},
634 {PIPE_FORMAT_R32_SINT
, R32_SINT
},
635 {PIPE_FORMAT_R32G32_SINT
, R32G32_SINT
},
636 {PIPE_FORMAT_R32G32B32_SINT
, R32G32B32_SINT
},
637 {PIPE_FORMAT_R32G32B32A32_SINT
, R32G32B32A32_SINT
},
639 {PIPE_FORMAT_A8_UINT
, (SWR_FORMAT
)-1},
640 {PIPE_FORMAT_I8_UINT
, I8_UINT
},
641 {PIPE_FORMAT_L8_UINT
, L8_UINT
},
642 {PIPE_FORMAT_L8A8_UINT
, L8A8_UINT
},
644 {PIPE_FORMAT_A8_SINT
, (SWR_FORMAT
)-1},
645 {PIPE_FORMAT_I8_SINT
, I8_SINT
},
646 {PIPE_FORMAT_L8_SINT
, L8_SINT
},
647 {PIPE_FORMAT_L8A8_SINT
, L8A8_SINT
},
649 {PIPE_FORMAT_A16_UINT
, (SWR_FORMAT
)-1},
650 {PIPE_FORMAT_I16_UINT
, (SWR_FORMAT
)-1},
651 {PIPE_FORMAT_L16_UINT
, (SWR_FORMAT
)-1},
652 {PIPE_FORMAT_L16A16_UINT
, (SWR_FORMAT
)-1},
654 {PIPE_FORMAT_A16_SINT
, (SWR_FORMAT
)-1},
655 {PIPE_FORMAT_I16_SINT
, (SWR_FORMAT
)-1},
656 {PIPE_FORMAT_L16_SINT
, (SWR_FORMAT
)-1},
657 {PIPE_FORMAT_L16A16_SINT
, (SWR_FORMAT
)-1},
659 {PIPE_FORMAT_A32_UINT
, (SWR_FORMAT
)-1},
660 {PIPE_FORMAT_I32_UINT
, (SWR_FORMAT
)-1},
661 {PIPE_FORMAT_L32_UINT
, (SWR_FORMAT
)-1},
662 {PIPE_FORMAT_L32A32_UINT
, (SWR_FORMAT
)-1},
664 {PIPE_FORMAT_A32_SINT
, (SWR_FORMAT
)-1},
665 {PIPE_FORMAT_I32_SINT
, (SWR_FORMAT
)-1},
666 {PIPE_FORMAT_L32_SINT
, (SWR_FORMAT
)-1},
667 {PIPE_FORMAT_L32A32_SINT
, (SWR_FORMAT
)-1},
669 {PIPE_FORMAT_B10G10R10A2_UINT
, B10G10R10A2_UINT
},
671 {PIPE_FORMAT_ETC1_RGB8
, (SWR_FORMAT
)-1},
673 {PIPE_FORMAT_R8G8_R8B8_UNORM
, (SWR_FORMAT
)-1},
674 {PIPE_FORMAT_G8R8_B8R8_UNORM
, (SWR_FORMAT
)-1},
676 {PIPE_FORMAT_R8G8B8X8_SNORM
, (SWR_FORMAT
)-1},
677 {PIPE_FORMAT_R8G8B8X8_SRGB
, (SWR_FORMAT
)-1},
678 {PIPE_FORMAT_R8G8B8X8_UINT
, (SWR_FORMAT
)-1},
679 {PIPE_FORMAT_R8G8B8X8_SINT
, (SWR_FORMAT
)-1},
680 {PIPE_FORMAT_B10G10R10X2_UNORM
, B10G10R10X2_UNORM
},
681 {PIPE_FORMAT_R16G16B16X16_UNORM
, R16G16B16X16_UNORM
},
682 {PIPE_FORMAT_R16G16B16X16_SNORM
, (SWR_FORMAT
)-1},
683 {PIPE_FORMAT_R16G16B16X16_FLOAT
, R16G16B16X16_FLOAT
},
684 {PIPE_FORMAT_R16G16B16X16_UINT
, (SWR_FORMAT
)-1},
685 {PIPE_FORMAT_R16G16B16X16_SINT
, (SWR_FORMAT
)-1},
686 {PIPE_FORMAT_R32G32B32X32_FLOAT
, R32G32B32X32_FLOAT
},
687 {PIPE_FORMAT_R32G32B32X32_UINT
, (SWR_FORMAT
)-1},
688 {PIPE_FORMAT_R32G32B32X32_SINT
, (SWR_FORMAT
)-1},
690 {PIPE_FORMAT_R8A8_SNORM
, (SWR_FORMAT
)-1},
691 {PIPE_FORMAT_R16A16_UNORM
, (SWR_FORMAT
)-1},
692 {PIPE_FORMAT_R16A16_SNORM
, (SWR_FORMAT
)-1},
693 {PIPE_FORMAT_R16A16_FLOAT
, (SWR_FORMAT
)-1},
694 {PIPE_FORMAT_R32A32_FLOAT
, (SWR_FORMAT
)-1},
695 {PIPE_FORMAT_R8A8_UINT
, (SWR_FORMAT
)-1},
696 {PIPE_FORMAT_R8A8_SINT
, (SWR_FORMAT
)-1},
697 {PIPE_FORMAT_R16A16_UINT
, (SWR_FORMAT
)-1},
698 {PIPE_FORMAT_R16A16_SINT
, (SWR_FORMAT
)-1},
699 {PIPE_FORMAT_R32A32_UINT
, (SWR_FORMAT
)-1},
700 {PIPE_FORMAT_R32A32_SINT
, (SWR_FORMAT
)-1},
701 {PIPE_FORMAT_R10G10B10A2_UINT
, R10G10B10A2_UINT
},
703 {PIPE_FORMAT_B5G6R5_SRGB
, B5G6R5_UNORM_SRGB
}
707 return mesa2swr
.at(format
);
709 catch (std::out_of_range
) {
710 debug_printf("asked to convert unsupported format %s\n",
711 util_format_name(format
));
713 return (SWR_FORMAT
)-1;
718 swr_displaytarget_layout(struct swr_screen
*screen
, struct swr_resource
*res
)
720 struct sw_winsys
*winsys
= screen
->winsys
;
721 struct sw_displaytarget
*dt
;
724 dt
= winsys
->displaytarget_create(winsys
,
735 void *map
= winsys
->displaytarget_map(winsys
, dt
, 0);
737 res
->display_target
= dt
;
738 res
->swr
.pBaseAddress
= (uint8_t*) map
;
740 /* Clear the display target surface */
742 memset(map
, 0, res
->alignedHeight
* stride
);
744 winsys
->displaytarget_unmap(winsys
, dt
);
750 swr_texture_layout(struct swr_screen
*screen
,
751 struct swr_resource
*res
,
754 struct pipe_resource
*pt
= &res
->base
;
756 pipe_format fmt
= pt
->format
;
757 const struct util_format_description
*desc
= util_format_description(fmt
);
759 res
->has_depth
= util_format_has_depth(desc
);
760 res
->has_stencil
= util_format_has_stencil(desc
);
762 if (res
->has_stencil
&& !res
->has_depth
)
763 fmt
= PIPE_FORMAT_R8_UINT
;
765 res
->swr
.width
= pt
->width0
;
766 res
->swr
.height
= pt
->height0
;
767 res
->swr
.depth
= pt
->depth0
;
768 res
->swr
.type
= swr_convert_target_type(pt
->target
);
769 res
->swr
.tileMode
= SWR_TILE_NONE
;
770 res
->swr
.format
= mesa_to_swr_format(fmt
);
771 res
->swr
.numSamples
= (1 << pt
->nr_samples
);
773 SWR_FORMAT_INFO finfo
= GetFormatInfo(res
->swr
.format
);
775 size_t total_size
= 0;
776 unsigned width
= pt
->width0
;
777 unsigned height
= pt
->height0
;
778 unsigned depth
= pt
->depth0
;
779 unsigned layers
= pt
->array_size
;
781 for (int level
= 0; level
<= pt
->last_level
; level
++) {
782 unsigned alignedWidth
, alignedHeight
;
785 if (pt
->bind
& (PIPE_BIND_RENDER_TARGET
| PIPE_BIND_DEPTH_STENCIL
)) {
786 alignedWidth
= align(width
, KNOB_MACROTILE_X_DIM
);
787 alignedHeight
= align(height
, KNOB_MACROTILE_Y_DIM
);
789 alignedWidth
= width
;
790 alignedHeight
= height
;
794 res
->alignedWidth
= alignedWidth
;
795 res
->alignedHeight
= alignedHeight
;
798 res
->row_stride
[level
] = alignedWidth
* finfo
.Bpp
;
799 res
->img_stride
[level
] = res
->row_stride
[level
] * alignedHeight
;
800 res
->mip_offsets
[level
] = total_size
;
802 if (pt
->target
== PIPE_TEXTURE_3D
)
804 else if (pt
->target
== PIPE_TEXTURE_1D_ARRAY
805 || pt
->target
== PIPE_TEXTURE_2D_ARRAY
806 || pt
->target
== PIPE_TEXTURE_CUBE
807 || pt
->target
== PIPE_TEXTURE_CUBE_ARRAY
)
812 total_size
+= res
->img_stride
[level
] * num_slices
;
813 if (total_size
> SWR_MAX_TEXTURE_SIZE
)
816 width
= u_minify(width
, 1);
817 height
= u_minify(height
, 1);
818 depth
= u_minify(depth
, 1);
821 res
->swr
.halign
= res
->alignedWidth
;
822 res
->swr
.valign
= res
->alignedHeight
;
823 res
->swr
.pitch
= res
->row_stride
[0];
826 res
->swr
.pBaseAddress
= (uint8_t *)AlignedMalloc(total_size
, 64);
828 if (res
->has_depth
&& res
->has_stencil
) {
829 SWR_FORMAT_INFO finfo
= GetFormatInfo(res
->secondary
.format
);
830 res
->secondary
.width
= pt
->width0
;
831 res
->secondary
.height
= pt
->height0
;
832 res
->secondary
.depth
= pt
->depth0
;
833 res
->secondary
.type
= SURFACE_2D
;
834 res
->secondary
.tileMode
= SWR_TILE_NONE
;
835 res
->secondary
.format
= R8_UINT
;
836 res
->secondary
.numSamples
= (1 << pt
->nr_samples
);
837 res
->secondary
.pitch
= res
->alignedWidth
* finfo
.Bpp
;
839 res
->secondary
.pBaseAddress
= (uint8_t *)AlignedMalloc(
840 res
->alignedHeight
* res
->secondary
.pitch
, 64);
848 swr_can_create_resource(struct pipe_screen
*screen
,
849 const struct pipe_resource
*templat
)
851 struct swr_resource res
;
852 memset(&res
, 0, sizeof(res
));
854 return swr_texture_layout(swr_screen(screen
), &res
, false);
857 static struct pipe_resource
*
858 swr_resource_create(struct pipe_screen
*_screen
,
859 const struct pipe_resource
*templat
)
861 struct swr_screen
*screen
= swr_screen(_screen
);
862 struct swr_resource
*res
= CALLOC_STRUCT(swr_resource
);
866 res
->base
= *templat
;
867 pipe_reference_init(&res
->base
.reference
, 1);
868 res
->base
.screen
= &screen
->base
;
870 if (swr_resource_is_texture(&res
->base
)) {
871 if (res
->base
.bind
& (PIPE_BIND_DISPLAY_TARGET
| PIPE_BIND_SCANOUT
872 | PIPE_BIND_SHARED
)) {
873 /* displayable surface
874 * first call swr_texture_layout without allocating to finish
875 * filling out the SWR_SURFAE_STATE in res */
876 swr_texture_layout(screen
, res
, false);
877 if (!swr_displaytarget_layout(screen
, res
))
881 if (!swr_texture_layout(screen
, res
, true))
885 /* other data (vertex buffer, const buffer, etc) */
886 assert(util_format_get_blocksize(templat
->format
) == 1);
887 assert(templat
->height0
== 1);
888 assert(templat
->depth0
== 1);
889 assert(templat
->last_level
== 0);
891 /* Easiest to just call swr_texture_layout, as it sets up
892 * SWR_SURFAE_STATE in res */
893 if (!swr_texture_layout(screen
, res
, true))
905 swr_resource_destroy(struct pipe_screen
*p_screen
, struct pipe_resource
*pt
)
907 struct swr_screen
*screen
= swr_screen(p_screen
);
908 struct swr_resource
*spr
= swr_resource(pt
);
909 struct pipe_context
*pipe
= screen
->pipe
;
911 /* Only wait on fence if the resource is being used */
912 if (pipe
&& spr
->status
) {
913 /* But, if there's no fence pending, submit one.
914 * XXX: Remove once draw timestamps are implmented. */
915 if (!swr_is_fence_pending(screen
->flush_fence
))
916 swr_fence_submit(swr_context(pipe
), screen
->flush_fence
);
918 swr_fence_finish(p_screen
, NULL
, screen
->flush_fence
, 0);
919 swr_resource_unused(pt
);
923 * Free resource primary surface. If resource is display target, winsys
924 * manages the buffer and will free it on displaytarget_destroy.
926 if (spr
->display_target
) {
928 struct sw_winsys
*winsys
= screen
->winsys
;
929 winsys
->displaytarget_destroy(winsys
, spr
->display_target
);
931 AlignedFree(spr
->swr
.pBaseAddress
);
933 AlignedFree(spr
->secondary
.pBaseAddress
);
940 swr_flush_frontbuffer(struct pipe_screen
*p_screen
,
941 struct pipe_resource
*resource
,
944 void *context_private
,
945 struct pipe_box
*sub_box
)
947 struct swr_screen
*screen
= swr_screen(p_screen
);
948 struct sw_winsys
*winsys
= screen
->winsys
;
949 struct swr_resource
*spr
= swr_resource(resource
);
950 struct pipe_context
*pipe
= screen
->pipe
;
953 swr_fence_finish(p_screen
, NULL
, screen
->flush_fence
, 0);
954 swr_resource_unused(resource
);
955 SwrEndFrame(swr_context(pipe
)->swrContext
);
958 debug_assert(spr
->display_target
);
959 if (spr
->display_target
)
960 winsys
->displaytarget_display(
961 winsys
, spr
->display_target
, context_private
, sub_box
);
966 swr_destroy_screen(struct pipe_screen
*p_screen
)
968 struct swr_screen
*screen
= swr_screen(p_screen
);
969 struct sw_winsys
*winsys
= screen
->winsys
;
971 fprintf(stderr
, "SWR destroy screen!\n");
973 swr_fence_finish(p_screen
, NULL
, screen
->flush_fence
, 0);
974 swr_fence_reference(p_screen
, &screen
->flush_fence
, NULL
);
976 JitDestroyContext(screen
->hJitMgr
);
979 winsys
->destroy(winsys
);
986 swr_create_screen(struct sw_winsys
*winsys
)
988 struct swr_screen
*screen
= CALLOC_STRUCT(swr_screen
);
993 if (!getenv("KNOB_MAX_PRIMS_PER_DRAW")) {
994 g_GlobalKnobs
.MAX_PRIMS_PER_DRAW
.Value(49152);
997 screen
->winsys
= winsys
;
998 screen
->base
.get_name
= swr_get_name
;
999 screen
->base
.get_vendor
= swr_get_vendor
;
1000 screen
->base
.is_format_supported
= swr_is_format_supported
;
1001 screen
->base
.context_create
= swr_create_context
;
1002 screen
->base
.can_create_resource
= swr_can_create_resource
;
1004 screen
->base
.destroy
= swr_destroy_screen
;
1005 screen
->base
.get_param
= swr_get_param
;
1006 screen
->base
.get_shader_param
= swr_get_shader_param
;
1007 screen
->base
.get_paramf
= swr_get_paramf
;
1009 screen
->base
.resource_create
= swr_resource_create
;
1010 screen
->base
.resource_destroy
= swr_resource_destroy
;
1012 screen
->base
.flush_frontbuffer
= swr_flush_frontbuffer
;
1014 screen
->hJitMgr
= JitCreateContext(KNOB_SIMD_WIDTH
, KNOB_ARCH_STR
, "swr");
1016 swr_fence_init(&screen
->base
);
1018 util_format_s3tc_init();
1020 return &screen
->base
;
1024 swr_get_winsys(struct pipe_screen
*pipe
)
1026 return ((struct swr_screen
*)pipe
)->winsys
;
1029 struct sw_displaytarget
*
1030 swr_get_displaytarget(struct pipe_resource
*resource
)
1032 return ((struct swr_resource
*)resource
)->display_target
;