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3d3d1034150687c1a4ce10e526da748957d1936c
[mesa.git] / src / gallium / drivers / swr / swr_screen.cpp
1 /****************************************************************************
2 * Copyright (C) 2015 Intel Corporation. All Rights Reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 ***************************************************************************/
23
24 #include "swr_context.h"
25 #include "swr_public.h"
26 #include "swr_screen.h"
27 #include "swr_resource.h"
28 #include "swr_fence.h"
29 #include "gen_knobs.h"
30
31 #include "pipe/p_screen.h"
32 #include "pipe/p_defines.h"
33 #include "util/u_memory.h"
34 #include "util/u_format.h"
35 #include "util/u_inlines.h"
36 #include "util/u_cpu_detect.h"
37 #include "util/u_format_s3tc.h"
38 #include "util/u_string.h"
39
40 #include "state_tracker/sw_winsys.h"
41
42 #include "jit_api.h"
43
44 #include "memory/TilingFunctions.h"
45
46 #include <stdio.h>
47 #include <map>
48
49 /* MSVC case instensitive compare */
50 #if defined(PIPE_CC_MSVC)
51 #define strcasecmp lstrcmpiA
52 #endif
53
54 /*
55 * Max texture sizes
56 * XXX Check max texture size values against core and sampler.
57 */
58 #define SWR_MAX_TEXTURE_SIZE (4 * 1024 * 1024 * 1024ULL) /* 4GB */
59 #define SWR_MAX_TEXTURE_2D_LEVELS 14 /* 8K x 8K for now */
60 #define SWR_MAX_TEXTURE_3D_LEVELS 12 /* 2K x 2K x 2K for now */
61 #define SWR_MAX_TEXTURE_CUBE_LEVELS 14 /* 8K x 8K for now */
62 #define SWR_MAX_TEXTURE_ARRAY_LAYERS 512 /* 8K x 512 / 8K x 8K x 512 */
63
64 static const char *
65 swr_get_name(struct pipe_screen *screen)
66 {
67 static char buf[100];
68 util_snprintf(buf, sizeof(buf), "SWR (LLVM %u.%u, %u bits)",
69 HAVE_LLVM >> 8, HAVE_LLVM & 0xff,
70 lp_native_vector_width );
71 return buf;
72 }
73
74 static const char *
75 swr_get_vendor(struct pipe_screen *screen)
76 {
77 return "Intel Corporation";
78 }
79
80 static boolean
81 swr_is_format_supported(struct pipe_screen *screen,
82 enum pipe_format format,
83 enum pipe_texture_target target,
84 unsigned sample_count,
85 unsigned bind)
86 {
87 struct sw_winsys *winsys = swr_screen(screen)->winsys;
88 const struct util_format_description *format_desc;
89
90 assert(target == PIPE_BUFFER || target == PIPE_TEXTURE_1D
91 || target == PIPE_TEXTURE_1D_ARRAY
92 || target == PIPE_TEXTURE_2D
93 || target == PIPE_TEXTURE_2D_ARRAY
94 || target == PIPE_TEXTURE_RECT
95 || target == PIPE_TEXTURE_3D
96 || target == PIPE_TEXTURE_CUBE
97 || target == PIPE_TEXTURE_CUBE_ARRAY);
98
99 format_desc = util_format_description(format);
100 if (!format_desc)
101 return FALSE;
102
103 if (sample_count > 1)
104 return FALSE;
105
106 if (bind
107 & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT | PIPE_BIND_SHARED)) {
108 if (!winsys->is_displaytarget_format_supported(winsys, bind, format))
109 return FALSE;
110 }
111
112 if (bind & PIPE_BIND_RENDER_TARGET) {
113 if (format_desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS)
114 return FALSE;
115
116 if (mesa_to_swr_format(format) == (SWR_FORMAT)-1)
117 return FALSE;
118
119 /*
120 * Although possible, it is unnatural to render into compressed or YUV
121 * surfaces. So disable these here to avoid going into weird paths
122 * inside the state trackers.
123 */
124 if (format_desc->block.width != 1 || format_desc->block.height != 1)
125 return FALSE;
126 }
127
128 if (bind & PIPE_BIND_DEPTH_STENCIL) {
129 if (format_desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
130 return FALSE;
131
132 if (mesa_to_swr_format(format) == (SWR_FORMAT)-1)
133 return FALSE;
134 }
135
136 if (format_desc->layout == UTIL_FORMAT_LAYOUT_BPTC ||
137 format_desc->layout == UTIL_FORMAT_LAYOUT_ASTC) {
138 return FALSE;
139 }
140
141 if (format_desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
142 format != PIPE_FORMAT_ETC1_RGB8) {
143 return FALSE;
144 }
145
146 if (format_desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
147 return util_format_s3tc_enabled;
148 }
149
150 return TRUE;
151 }
152
153 static int
154 swr_get_param(struct pipe_screen *screen, enum pipe_cap param)
155 {
156 switch (param) {
157 /* limits */
158 case PIPE_CAP_MAX_RENDER_TARGETS:
159 return PIPE_MAX_COLOR_BUFS;
160 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
161 return SWR_MAX_TEXTURE_2D_LEVELS;
162 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
163 return SWR_MAX_TEXTURE_3D_LEVELS;
164 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
165 return SWR_MAX_TEXTURE_CUBE_LEVELS;
166 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
167 return MAX_SO_STREAMS;
168 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
169 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
170 return MAX_ATTRIBUTES * 4;
171 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
172 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
173 return 1024;
174 case PIPE_CAP_MAX_VERTEX_STREAMS:
175 return 1;
176 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
177 return 2048;
178 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
179 return SWR_MAX_TEXTURE_ARRAY_LAYERS;
180 case PIPE_CAP_MIN_TEXEL_OFFSET:
181 return -8;
182 case PIPE_CAP_MAX_TEXEL_OFFSET:
183 return 7;
184 case PIPE_CAP_GLSL_FEATURE_LEVEL:
185 return 330;
186 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
187 return 16;
188 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
189 return 64;
190 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
191 return 65536;
192 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
193 return 0;
194 case PIPE_CAP_MAX_VIEWPORTS:
195 return 1;
196 case PIPE_CAP_ENDIANNESS:
197 return PIPE_ENDIAN_NATIVE;
198 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
199 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
200 return 0;
201
202 /* supported features */
203 case PIPE_CAP_NPOT_TEXTURES:
204 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
205 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
206 case PIPE_CAP_TWO_SIDED_STENCIL:
207 case PIPE_CAP_SM3:
208 case PIPE_CAP_POINT_SPRITE:
209 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
210 case PIPE_CAP_OCCLUSION_QUERY:
211 case PIPE_CAP_QUERY_TIME_ELAPSED:
212 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
213 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
214 case PIPE_CAP_TEXTURE_SHADOW_MAP:
215 case PIPE_CAP_TEXTURE_SWIZZLE:
216 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
217 case PIPE_CAP_INDEP_BLEND_ENABLE:
218 case PIPE_CAP_INDEP_BLEND_FUNC:
219 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
220 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
221 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
222 case PIPE_CAP_DEPTH_CLIP_DISABLE:
223 case PIPE_CAP_PRIMITIVE_RESTART:
224 case PIPE_CAP_TGSI_INSTANCEID:
225 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
226 case PIPE_CAP_START_INSTANCE:
227 case PIPE_CAP_SEAMLESS_CUBE_MAP:
228 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
229 case PIPE_CAP_CONDITIONAL_RENDER:
230 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
231 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
232 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
233 case PIPE_CAP_USER_VERTEX_BUFFERS:
234 case PIPE_CAP_USER_CONSTANT_BUFFERS:
235 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
236 case PIPE_CAP_QUERY_TIMESTAMP:
237 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
238 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
239 case PIPE_CAP_FAKE_SW_MSAA:
240 case PIPE_CAP_DRAW_INDIRECT:
241 case PIPE_CAP_UMA:
242 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
243 case PIPE_CAP_CLIP_HALFZ:
244 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
245 case PIPE_CAP_DEPTH_BOUNDS_TEST:
246 case PIPE_CAP_CLEAR_TEXTURE:
247 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
248 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
249 case PIPE_CAP_CULL_DISTANCE:
250 case PIPE_CAP_CUBE_MAP_ARRAY:
251 case PIPE_CAP_DOUBLES:
252 return 1;
253
254 /* unsupported features */
255 case PIPE_CAP_ANISOTROPIC_FILTER:
256 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
257 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
258 case PIPE_CAP_SHADER_STENCIL_EXPORT:
259 case PIPE_CAP_TEXTURE_BARRIER:
260 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
261 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
262 case PIPE_CAP_COMPUTE:
263 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
264 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
265 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
266 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
267 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
268 case PIPE_CAP_TEXTURE_MULTISAMPLE:
269 case PIPE_CAP_TGSI_TEXCOORD:
270 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
271 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
272 case PIPE_CAP_TEXTURE_GATHER_SM5:
273 case PIPE_CAP_TEXTURE_QUERY_LOD:
274 case PIPE_CAP_SAMPLE_SHADING:
275 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
276 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
277 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
278 case PIPE_CAP_SAMPLER_VIEW_TARGET:
279 case PIPE_CAP_VERTEXID_NOBASE:
280 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
281 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
282 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
283 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
284 case PIPE_CAP_TGSI_TXQS:
285 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
286 case PIPE_CAP_SHAREABLE_SHADERS:
287 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
288 case PIPE_CAP_DRAW_PARAMETERS:
289 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
290 case PIPE_CAP_MULTI_DRAW_INDIRECT:
291 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
292 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
293 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
294 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
295 case PIPE_CAP_INVALIDATE_BUFFER:
296 case PIPE_CAP_GENERATE_MIPMAP:
297 case PIPE_CAP_STRING_MARKER:
298 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
299 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
300 case PIPE_CAP_QUERY_BUFFER_OBJECT:
301 case PIPE_CAP_QUERY_MEMORY_INFO:
302 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
303 case PIPE_CAP_PCI_GROUP:
304 case PIPE_CAP_PCI_BUS:
305 case PIPE_CAP_PCI_DEVICE:
306 case PIPE_CAP_PCI_FUNCTION:
307 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
308 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
309 case PIPE_CAP_TGSI_VOTE:
310 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
311 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
312 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
313 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
314 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
315 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
316 case PIPE_CAP_NATIVE_FENCE_FD:
317 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
318 case PIPE_CAP_TGSI_FS_FBFETCH:
319 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
320 case PIPE_CAP_INT64:
321 case PIPE_CAP_INT64_DIVMOD:
322 case PIPE_CAP_TGSI_TEX_TXF_LZ:
323 case PIPE_CAP_TGSI_CLOCK:
324 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
325 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
326 case PIPE_CAP_TGSI_BALLOT:
327 return 0;
328
329 case PIPE_CAP_VENDOR_ID:
330 return 0xFFFFFFFF;
331 case PIPE_CAP_DEVICE_ID:
332 return 0xFFFFFFFF;
333 case PIPE_CAP_ACCELERATED:
334 return 0;
335 case PIPE_CAP_VIDEO_MEMORY: {
336 /* XXX: Do we want to return the full amount of system memory ? */
337 uint64_t system_memory;
338
339 if (!os_get_total_physical_memory(&system_memory))
340 return 0;
341
342 return (int)(system_memory >> 20);
343 }
344 }
345
346 /* should only get here on unhandled cases */
347 debug_printf("Unexpected PIPE_CAP %d query\n", param);
348 return 0;
349 }
350
351 static int
352 swr_get_shader_param(struct pipe_screen *screen,
353 enum pipe_shader_type shader,
354 enum pipe_shader_cap param)
355 {
356 if (shader == PIPE_SHADER_VERTEX ||
357 shader == PIPE_SHADER_FRAGMENT ||
358 shader == PIPE_SHADER_GEOMETRY)
359 return gallivm_get_shader_param(param);
360
361 // Todo: tesselation, compute
362 return 0;
363 }
364
365
366 static float
367 swr_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
368 {
369 switch (param) {
370 case PIPE_CAPF_MAX_LINE_WIDTH:
371 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
372 case PIPE_CAPF_MAX_POINT_WIDTH:
373 return 255.0; /* arbitrary */
374 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
375 return 0.0;
376 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
377 return 0.0;
378 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
379 return 16.0; /* arbitrary */
380 case PIPE_CAPF_GUARD_BAND_LEFT:
381 case PIPE_CAPF_GUARD_BAND_TOP:
382 case PIPE_CAPF_GUARD_BAND_RIGHT:
383 case PIPE_CAPF_GUARD_BAND_BOTTOM:
384 return 0.0;
385 }
386 /* should only get here on unhandled cases */
387 debug_printf("Unexpected PIPE_CAPF %d query\n", param);
388 return 0.0;
389 }
390
391 SWR_FORMAT
392 mesa_to_swr_format(enum pipe_format format)
393 {
394 static const std::map<pipe_format,SWR_FORMAT> mesa2swr = {
395 /* depth / stencil */
396 {PIPE_FORMAT_Z16_UNORM, R16_UNORM}, // z
397 {PIPE_FORMAT_Z32_FLOAT, R32_FLOAT}, // z
398 {PIPE_FORMAT_Z24_UNORM_S8_UINT, R24_UNORM_X8_TYPELESS}, // z
399 {PIPE_FORMAT_Z24X8_UNORM, R24_UNORM_X8_TYPELESS}, // z
400 {PIPE_FORMAT_Z32_FLOAT_S8X24_UINT, R32_FLOAT_X8X24_TYPELESS}, // z
401
402 /* alpha */
403 {PIPE_FORMAT_A8_UNORM, A8_UNORM},
404 {PIPE_FORMAT_A16_UNORM, A16_UNORM},
405 {PIPE_FORMAT_A16_FLOAT, A16_FLOAT},
406 {PIPE_FORMAT_A32_FLOAT, A32_FLOAT},
407
408 /* odd sizes, bgr */
409 {PIPE_FORMAT_B5G6R5_UNORM, B5G6R5_UNORM},
410 {PIPE_FORMAT_B5G6R5_SRGB, B5G6R5_UNORM_SRGB},
411 {PIPE_FORMAT_B5G5R5A1_UNORM, B5G5R5A1_UNORM},
412 {PIPE_FORMAT_B5G5R5X1_UNORM, B5G5R5X1_UNORM},
413 {PIPE_FORMAT_B4G4R4A4_UNORM, B4G4R4A4_UNORM},
414 {PIPE_FORMAT_B8G8R8A8_UNORM, B8G8R8A8_UNORM},
415 {PIPE_FORMAT_B8G8R8A8_SRGB, B8G8R8A8_UNORM_SRGB},
416 {PIPE_FORMAT_B8G8R8X8_UNORM, B8G8R8X8_UNORM},
417 {PIPE_FORMAT_B8G8R8X8_SRGB, B8G8R8X8_UNORM_SRGB},
418
419 /* rgb10a2 */
420 {PIPE_FORMAT_R10G10B10A2_UNORM, R10G10B10A2_UNORM},
421 {PIPE_FORMAT_R10G10B10A2_SNORM, R10G10B10A2_SNORM},
422 {PIPE_FORMAT_R10G10B10A2_USCALED, R10G10B10A2_USCALED},
423 {PIPE_FORMAT_R10G10B10A2_SSCALED, R10G10B10A2_SSCALED},
424 {PIPE_FORMAT_R10G10B10A2_UINT, R10G10B10A2_UINT},
425
426 /* rgb10x2 */
427 {PIPE_FORMAT_R10G10B10X2_USCALED, R10G10B10X2_USCALED},
428
429 /* bgr10a2 */
430 {PIPE_FORMAT_B10G10R10A2_UNORM, B10G10R10A2_UNORM},
431 {PIPE_FORMAT_B10G10R10A2_SNORM, B10G10R10A2_SNORM},
432 {PIPE_FORMAT_B10G10R10A2_USCALED, B10G10R10A2_USCALED},
433 {PIPE_FORMAT_B10G10R10A2_SSCALED, B10G10R10A2_SSCALED},
434 {PIPE_FORMAT_B10G10R10A2_UINT, B10G10R10A2_UINT},
435
436 /* bgr10x2 */
437 {PIPE_FORMAT_B10G10R10X2_UNORM, B10G10R10X2_UNORM},
438
439 /* r11g11b10 */
440 {PIPE_FORMAT_R11G11B10_FLOAT, R11G11B10_FLOAT},
441
442 /* 32 bits per component */
443 {PIPE_FORMAT_R32_FLOAT, R32_FLOAT},
444 {PIPE_FORMAT_R32G32_FLOAT, R32G32_FLOAT},
445 {PIPE_FORMAT_R32G32B32_FLOAT, R32G32B32_FLOAT},
446 {PIPE_FORMAT_R32G32B32A32_FLOAT, R32G32B32A32_FLOAT},
447 {PIPE_FORMAT_R32G32B32X32_FLOAT, R32G32B32X32_FLOAT},
448
449 {PIPE_FORMAT_R32_USCALED, R32_USCALED},
450 {PIPE_FORMAT_R32G32_USCALED, R32G32_USCALED},
451 {PIPE_FORMAT_R32G32B32_USCALED, R32G32B32_USCALED},
452 {PIPE_FORMAT_R32G32B32A32_USCALED, R32G32B32A32_USCALED},
453
454 {PIPE_FORMAT_R32_SSCALED, R32_SSCALED},
455 {PIPE_FORMAT_R32G32_SSCALED, R32G32_SSCALED},
456 {PIPE_FORMAT_R32G32B32_SSCALED, R32G32B32_SSCALED},
457 {PIPE_FORMAT_R32G32B32A32_SSCALED, R32G32B32A32_SSCALED},
458
459 {PIPE_FORMAT_R32_UINT, R32_UINT},
460 {PIPE_FORMAT_R32G32_UINT, R32G32_UINT},
461 {PIPE_FORMAT_R32G32B32_UINT, R32G32B32_UINT},
462 {PIPE_FORMAT_R32G32B32A32_UINT, R32G32B32A32_UINT},
463
464 {PIPE_FORMAT_R32_SINT, R32_SINT},
465 {PIPE_FORMAT_R32G32_SINT, R32G32_SINT},
466 {PIPE_FORMAT_R32G32B32_SINT, R32G32B32_SINT},
467 {PIPE_FORMAT_R32G32B32A32_SINT, R32G32B32A32_SINT},
468
469 /* 16 bits per component */
470 {PIPE_FORMAT_R16_UNORM, R16_UNORM},
471 {PIPE_FORMAT_R16G16_UNORM, R16G16_UNORM},
472 {PIPE_FORMAT_R16G16B16_UNORM, R16G16B16_UNORM},
473 {PIPE_FORMAT_R16G16B16A16_UNORM, R16G16B16A16_UNORM},
474 {PIPE_FORMAT_R16G16B16X16_UNORM, R16G16B16X16_UNORM},
475
476 {PIPE_FORMAT_R16_USCALED, R16_USCALED},
477 {PIPE_FORMAT_R16G16_USCALED, R16G16_USCALED},
478 {PIPE_FORMAT_R16G16B16_USCALED, R16G16B16_USCALED},
479 {PIPE_FORMAT_R16G16B16A16_USCALED, R16G16B16A16_USCALED},
480
481 {PIPE_FORMAT_R16_SNORM, R16_SNORM},
482 {PIPE_FORMAT_R16G16_SNORM, R16G16_SNORM},
483 {PIPE_FORMAT_R16G16B16_SNORM, R16G16B16_SNORM},
484 {PIPE_FORMAT_R16G16B16A16_SNORM, R16G16B16A16_SNORM},
485
486 {PIPE_FORMAT_R16_SSCALED, R16_SSCALED},
487 {PIPE_FORMAT_R16G16_SSCALED, R16G16_SSCALED},
488 {PIPE_FORMAT_R16G16B16_SSCALED, R16G16B16_SSCALED},
489 {PIPE_FORMAT_R16G16B16A16_SSCALED, R16G16B16A16_SSCALED},
490
491 {PIPE_FORMAT_R16_UINT, R16_UINT},
492 {PIPE_FORMAT_R16G16_UINT, R16G16_UINT},
493 {PIPE_FORMAT_R16G16B16_UINT, R16G16B16_UINT},
494 {PIPE_FORMAT_R16G16B16A16_UINT, R16G16B16A16_UINT},
495
496 {PIPE_FORMAT_R16_SINT, R16_SINT},
497 {PIPE_FORMAT_R16G16_SINT, R16G16_SINT},
498 {PIPE_FORMAT_R16G16B16_SINT, R16G16B16_SINT},
499 {PIPE_FORMAT_R16G16B16A16_SINT, R16G16B16A16_SINT},
500
501 {PIPE_FORMAT_R16_FLOAT, R16_FLOAT},
502 {PIPE_FORMAT_R16G16_FLOAT, R16G16_FLOAT},
503 {PIPE_FORMAT_R16G16B16_FLOAT, R16G16B16_FLOAT},
504 {PIPE_FORMAT_R16G16B16A16_FLOAT, R16G16B16A16_FLOAT},
505 {PIPE_FORMAT_R16G16B16X16_FLOAT, R16G16B16X16_FLOAT},
506
507 /* 8 bits per component */
508 {PIPE_FORMAT_R8_UNORM, R8_UNORM},
509 {PIPE_FORMAT_R8G8_UNORM, R8G8_UNORM},
510 {PIPE_FORMAT_R8G8B8_UNORM, R8G8B8_UNORM},
511 {PIPE_FORMAT_R8G8B8_SRGB, R8G8B8_UNORM_SRGB},
512 {PIPE_FORMAT_R8G8B8A8_UNORM, R8G8B8A8_UNORM},
513 {PIPE_FORMAT_R8G8B8A8_SRGB, R8G8B8A8_UNORM_SRGB},
514 {PIPE_FORMAT_R8G8B8X8_UNORM, R8G8B8X8_UNORM},
515 {PIPE_FORMAT_R8G8B8X8_SRGB, R8G8B8X8_UNORM_SRGB},
516
517 {PIPE_FORMAT_R8_USCALED, R8_USCALED},
518 {PIPE_FORMAT_R8G8_USCALED, R8G8_USCALED},
519 {PIPE_FORMAT_R8G8B8_USCALED, R8G8B8_USCALED},
520 {PIPE_FORMAT_R8G8B8A8_USCALED, R8G8B8A8_USCALED},
521
522 {PIPE_FORMAT_R8_SNORM, R8_SNORM},
523 {PIPE_FORMAT_R8G8_SNORM, R8G8_SNORM},
524 {PIPE_FORMAT_R8G8B8_SNORM, R8G8B8_SNORM},
525 {PIPE_FORMAT_R8G8B8A8_SNORM, R8G8B8A8_SNORM},
526
527 {PIPE_FORMAT_R8_SSCALED, R8_SSCALED},
528 {PIPE_FORMAT_R8G8_SSCALED, R8G8_SSCALED},
529 {PIPE_FORMAT_R8G8B8_SSCALED, R8G8B8_SSCALED},
530 {PIPE_FORMAT_R8G8B8A8_SSCALED, R8G8B8A8_SSCALED},
531
532 {PIPE_FORMAT_R8_UINT, R8_UINT},
533 {PIPE_FORMAT_R8G8_UINT, R8G8_UINT},
534 {PIPE_FORMAT_R8G8B8_UINT, R8G8B8_UINT},
535 {PIPE_FORMAT_R8G8B8A8_UINT, R8G8B8A8_UINT},
536
537 {PIPE_FORMAT_R8_SINT, R8_SINT},
538 {PIPE_FORMAT_R8G8_SINT, R8G8_SINT},
539 {PIPE_FORMAT_R8G8B8_SINT, R8G8B8_SINT},
540 {PIPE_FORMAT_R8G8B8A8_SINT, R8G8B8A8_SINT},
541
542 /* These formats are valid for vertex data, but should not be used
543 * for render targets.
544 */
545
546 {PIPE_FORMAT_R32_FIXED, R32_SFIXED},
547 {PIPE_FORMAT_R32G32_FIXED, R32G32_SFIXED},
548 {PIPE_FORMAT_R32G32B32_FIXED, R32G32B32_SFIXED},
549 {PIPE_FORMAT_R32G32B32A32_FIXED, R32G32B32A32_SFIXED},
550
551 {PIPE_FORMAT_R64_FLOAT, R64_FLOAT},
552 {PIPE_FORMAT_R64G64_FLOAT, R64G64_FLOAT},
553 {PIPE_FORMAT_R64G64B64_FLOAT, R64G64B64_FLOAT},
554 {PIPE_FORMAT_R64G64B64A64_FLOAT, R64G64B64A64_FLOAT},
555
556 /* These formats have entries in SWR but don't have Load/StoreTile
557 * implementations. That means these aren't renderable, and thus having
558 * a mapping entry here is detrimental.
559 */
560 /*
561
562 {PIPE_FORMAT_L8_UNORM, L8_UNORM},
563 {PIPE_FORMAT_I8_UNORM, I8_UNORM},
564 {PIPE_FORMAT_L8A8_UNORM, L8A8_UNORM},
565 {PIPE_FORMAT_L16_UNORM, L16_UNORM},
566 {PIPE_FORMAT_UYVY, YCRCB_SWAPUVY},
567
568 {PIPE_FORMAT_L8_SRGB, L8_UNORM_SRGB},
569 {PIPE_FORMAT_L8A8_SRGB, L8A8_UNORM_SRGB},
570
571 {PIPE_FORMAT_DXT1_RGBA, BC1_UNORM},
572 {PIPE_FORMAT_DXT3_RGBA, BC2_UNORM},
573 {PIPE_FORMAT_DXT5_RGBA, BC3_UNORM},
574
575 {PIPE_FORMAT_DXT1_SRGBA, BC1_UNORM_SRGB},
576 {PIPE_FORMAT_DXT3_SRGBA, BC2_UNORM_SRGB},
577 {PIPE_FORMAT_DXT5_SRGBA, BC3_UNORM_SRGB},
578
579 {PIPE_FORMAT_RGTC1_UNORM, BC4_UNORM},
580 {PIPE_FORMAT_RGTC1_SNORM, BC4_SNORM},
581 {PIPE_FORMAT_RGTC2_UNORM, BC5_UNORM},
582 {PIPE_FORMAT_RGTC2_SNORM, BC5_SNORM},
583
584 {PIPE_FORMAT_L16A16_UNORM, L16A16_UNORM},
585 {PIPE_FORMAT_I16_UNORM, I16_UNORM},
586 {PIPE_FORMAT_L16_FLOAT, L16_FLOAT},
587 {PIPE_FORMAT_L16A16_FLOAT, L16A16_FLOAT},
588 {PIPE_FORMAT_I16_FLOAT, I16_FLOAT},
589 {PIPE_FORMAT_L32_FLOAT, L32_FLOAT},
590 {PIPE_FORMAT_L32A32_FLOAT, L32A32_FLOAT},
591 {PIPE_FORMAT_I32_FLOAT, I32_FLOAT},
592
593 {PIPE_FORMAT_I8_UINT, I8_UINT},
594 {PIPE_FORMAT_L8_UINT, L8_UINT},
595 {PIPE_FORMAT_L8A8_UINT, L8A8_UINT},
596
597 {PIPE_FORMAT_I8_SINT, I8_SINT},
598 {PIPE_FORMAT_L8_SINT, L8_SINT},
599 {PIPE_FORMAT_L8A8_SINT, L8A8_SINT},
600
601 */
602 };
603
604 auto it = mesa2swr.find(format);
605 if (it == mesa2swr.end())
606 return (SWR_FORMAT)-1;
607 else
608 return it->second;
609 }
610
611 static boolean
612 swr_displaytarget_layout(struct swr_screen *screen, struct swr_resource *res)
613 {
614 struct sw_winsys *winsys = screen->winsys;
615 struct sw_displaytarget *dt;
616
617 const unsigned width = align(res->swr.width, res->swr.halign);
618 const unsigned height = align(res->swr.height, res->swr.valign);
619
620 UINT stride;
621 dt = winsys->displaytarget_create(winsys,
622 res->base.bind,
623 res->base.format,
624 width, height,
625 64, NULL,
626 &stride);
627
628 if (dt == NULL)
629 return FALSE;
630
631 void *map = winsys->displaytarget_map(winsys, dt, 0);
632
633 res->display_target = dt;
634 res->swr.pBaseAddress = (uint8_t*) map;
635
636 /* Clear the display target surface */
637 if (map)
638 memset(map, 0, height * stride);
639
640 winsys->displaytarget_unmap(winsys, dt);
641
642 return TRUE;
643 }
644
645 static bool
646 swr_texture_layout(struct swr_screen *screen,
647 struct swr_resource *res,
648 boolean allocate)
649 {
650 struct pipe_resource *pt = &res->base;
651
652 pipe_format fmt = pt->format;
653 const struct util_format_description *desc = util_format_description(fmt);
654
655 res->has_depth = util_format_has_depth(desc);
656 res->has_stencil = util_format_has_stencil(desc);
657
658 if (res->has_stencil && !res->has_depth)
659 fmt = PIPE_FORMAT_R8_UINT;
660
661 /* We always use the SWR layout. For 2D and 3D textures this looks like:
662 *
663 * |<------- pitch ------->|
664 * +=======================+-------
665 * |Array 0 | ^
666 * | | |
667 * | Level 0 | |
668 * | | |
669 * | | qpitch
670 * +-----------+-----------+ |
671 * | | L2L2L2L2 | |
672 * | Level 1 | L3L3 | |
673 * | | L4 | v
674 * +===========+===========+-------
675 * |Array 1 |
676 * | |
677 * | Level 0 |
678 * | |
679 * | |
680 * +-----------+-----------+
681 * | | L2L2L2L2 |
682 * | Level 1 | L3L3 |
683 * | | L4 |
684 * +===========+===========+
685 *
686 * The overall width in bytes is known as the pitch, while the overall
687 * height in rows is the qpitch. Array slices are laid out logically below
688 * one another, qpitch rows apart. For 3D surfaces, the "level" values are
689 * just invalid for the higher array numbers (since depth is also
690 * minified). 1D and 1D array surfaces are stored effectively the same way,
691 * except that pitch never plays into it. All the levels are logically
692 * adjacent to each other on the X axis. The qpitch becomes the number of
693 * elements between array slices, while the pitch is unused.
694 *
695 * Each level's sizes are subject to the valign and halign settings of the
696 * surface. For compressed formats that swr is unaware of, we will use an
697 * appropriately-sized uncompressed format, and scale the widths/heights.
698 *
699 * This surface is stored inside res->swr. For depth/stencil textures,
700 * res->secondary will have an identically-laid-out but R8_UINT-formatted
701 * stencil tree. In the Z32F_S8 case, the primary surface still has 64-bpp
702 * texels, to simplify map/unmap logic which copies the stencil values
703 * in/out.
704 */
705
706 res->swr.width = pt->width0;
707 res->swr.height = pt->height0;
708 res->swr.type = swr_convert_target_type(pt->target);
709 res->swr.tileMode = SWR_TILE_NONE;
710 res->swr.format = mesa_to_swr_format(fmt);
711 res->swr.numSamples = std::max(1u, pt->nr_samples);
712
713 if (pt->bind & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DEPTH_STENCIL)) {
714 res->swr.halign = KNOB_MACROTILE_X_DIM;
715 res->swr.valign = KNOB_MACROTILE_Y_DIM;
716 } else {
717 res->swr.halign = 1;
718 res->swr.valign = 1;
719 }
720
721 unsigned halign = res->swr.halign * util_format_get_blockwidth(fmt);
722 unsigned width = align(pt->width0, halign);
723 if (pt->target == PIPE_TEXTURE_1D || pt->target == PIPE_TEXTURE_1D_ARRAY) {
724 for (int level = 1; level <= pt->last_level; level++)
725 width += align(u_minify(pt->width0, level), halign);
726 res->swr.pitch = util_format_get_blocksize(fmt);
727 res->swr.qpitch = util_format_get_nblocksx(fmt, width);
728 } else {
729 // The pitch is the overall width of the texture in bytes. Most of the
730 // time this is the pitch of level 0 since all the other levels fit
731 // underneath it. However in some degenerate situations, the width of
732 // level1 + level2 may be larger. In that case, we use those
733 // widths. This can happen if, e.g. halign is 32, and the width of level
734 // 0 is 32 or less. In that case, the aligned levels 1 and 2 will also
735 // be 32 each, adding up to 64.
736 unsigned valign = res->swr.valign * util_format_get_blockheight(fmt);
737 if (pt->last_level > 1) {
738 width = std::max<uint32_t>(
739 width,
740 align(u_minify(pt->width0, 1), halign) +
741 align(u_minify(pt->width0, 2), halign));
742 }
743 res->swr.pitch = util_format_get_stride(fmt, width);
744
745 // The qpitch is controlled by either the height of the second LOD, or
746 // the combination of all the later LODs.
747 unsigned height = align(pt->height0, valign);
748 if (pt->last_level == 1) {
749 height += align(u_minify(pt->height0, 1), valign);
750 } else if (pt->last_level > 1) {
751 unsigned level1 = align(u_minify(pt->height0, 1), valign);
752 unsigned level2 = 0;
753 for (int level = 2; level <= pt->last_level; level++) {
754 level2 += align(u_minify(pt->height0, level), valign);
755 }
756 height += std::max(level1, level2);
757 }
758 res->swr.qpitch = util_format_get_nblocksy(fmt, height);
759 }
760
761 if (pt->target == PIPE_TEXTURE_3D)
762 res->swr.depth = pt->depth0;
763 else
764 res->swr.depth = pt->array_size;
765
766 // Fix up swr format if necessary so that LOD offset computation works
767 if (res->swr.format == (SWR_FORMAT)-1) {
768 switch (util_format_get_blocksize(fmt)) {
769 default:
770 unreachable("Unexpected format block size");
771 case 1: res->swr.format = R8_UINT; break;
772 case 2: res->swr.format = R16_UINT; break;
773 case 4: res->swr.format = R32_UINT; break;
774 case 8:
775 if (util_format_is_compressed(fmt))
776 res->swr.format = BC4_UNORM;
777 else
778 res->swr.format = R32G32_UINT;
779 break;
780 case 16:
781 if (util_format_is_compressed(fmt))
782 res->swr.format = BC5_UNORM;
783 else
784 res->swr.format = R32G32B32A32_UINT;
785 break;
786 }
787 }
788
789 for (int level = 0; level <= pt->last_level; level++) {
790 res->mip_offsets[level] =
791 ComputeSurfaceOffset<false>(0, 0, 0, 0, 0, level, &res->swr);
792 }
793
794 size_t total_size =
795 (size_t)res->swr.depth * res->swr.qpitch * res->swr.pitch;
796 if (total_size > SWR_MAX_TEXTURE_SIZE)
797 return false;
798
799 if (allocate) {
800 res->swr.pBaseAddress = (uint8_t *)AlignedMalloc(total_size, 64);
801
802 if (res->has_depth && res->has_stencil) {
803 res->secondary = res->swr;
804 res->secondary.format = R8_UINT;
805 res->secondary.pitch = res->swr.pitch / util_format_get_blocksize(fmt);
806
807 for (int level = 0; level <= pt->last_level; level++) {
808 res->secondary_mip_offsets[level] =
809 ComputeSurfaceOffset<false>(0, 0, 0, 0, 0, level, &res->secondary);
810 }
811
812 res->secondary.pBaseAddress = (uint8_t *)AlignedMalloc(
813 res->secondary.depth * res->secondary.qpitch *
814 res->secondary.pitch, 64);
815 }
816 }
817
818 return true;
819 }
820
821 static boolean
822 swr_can_create_resource(struct pipe_screen *screen,
823 const struct pipe_resource *templat)
824 {
825 struct swr_resource res;
826 memset(&res, 0, sizeof(res));
827 res.base = *templat;
828 return swr_texture_layout(swr_screen(screen), &res, false);
829 }
830
831 static struct pipe_resource *
832 swr_resource_create(struct pipe_screen *_screen,
833 const struct pipe_resource *templat)
834 {
835 struct swr_screen *screen = swr_screen(_screen);
836 struct swr_resource *res = CALLOC_STRUCT(swr_resource);
837 if (!res)
838 return NULL;
839
840 res->base = *templat;
841 pipe_reference_init(&res->base.reference, 1);
842 res->base.screen = &screen->base;
843
844 if (swr_resource_is_texture(&res->base)) {
845 if (res->base.bind & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT
846 | PIPE_BIND_SHARED)) {
847 /* displayable surface
848 * first call swr_texture_layout without allocating to finish
849 * filling out the SWR_SURFAE_STATE in res */
850 swr_texture_layout(screen, res, false);
851 if (!swr_displaytarget_layout(screen, res))
852 goto fail;
853 } else {
854 /* texture map */
855 if (!swr_texture_layout(screen, res, true))
856 goto fail;
857 }
858 } else {
859 /* other data (vertex buffer, const buffer, etc) */
860 assert(util_format_get_blocksize(templat->format) == 1);
861 assert(templat->height0 == 1);
862 assert(templat->depth0 == 1);
863 assert(templat->last_level == 0);
864
865 /* Easiest to just call swr_texture_layout, as it sets up
866 * SWR_SURFAE_STATE in res */
867 if (!swr_texture_layout(screen, res, true))
868 goto fail;
869 }
870
871 return &res->base;
872
873 fail:
874 FREE(res);
875 return NULL;
876 }
877
878 static void
879 swr_resource_destroy(struct pipe_screen *p_screen, struct pipe_resource *pt)
880 {
881 struct swr_screen *screen = swr_screen(p_screen);
882 struct swr_resource *spr = swr_resource(pt);
883
884 if (spr->display_target) {
885 /* If resource is display target, winsys manages the buffer and will
886 * free it on displaytarget_destroy. */
887 swr_fence_finish(p_screen, NULL, screen->flush_fence, 0);
888
889 struct sw_winsys *winsys = screen->winsys;
890 winsys->displaytarget_destroy(winsys, spr->display_target);
891
892 } else {
893 /* For regular resources, defer deletion */
894 swr_resource_unused(pt);
895 swr_fence_work_free(screen->flush_fence, spr->swr.pBaseAddress, true);
896 swr_fence_work_free(screen->flush_fence,
897 spr->secondary.pBaseAddress, true);
898 }
899
900 FREE(spr);
901 }
902
903
904 static void
905 swr_flush_frontbuffer(struct pipe_screen *p_screen,
906 struct pipe_resource *resource,
907 unsigned level,
908 unsigned layer,
909 void *context_private,
910 struct pipe_box *sub_box)
911 {
912 struct swr_screen *screen = swr_screen(p_screen);
913 struct sw_winsys *winsys = screen->winsys;
914 struct swr_resource *spr = swr_resource(resource);
915 struct pipe_context *pipe = screen->pipe;
916
917 if (pipe) {
918 swr_fence_finish(p_screen, NULL, screen->flush_fence, 0);
919 swr_resource_unused(resource);
920 SwrEndFrame(swr_context(pipe)->swrContext);
921 }
922
923 debug_assert(spr->display_target);
924 if (spr->display_target)
925 winsys->displaytarget_display(
926 winsys, spr->display_target, context_private, sub_box);
927 }
928
929
930 static void
931 swr_destroy_screen(struct pipe_screen *p_screen)
932 {
933 struct swr_screen *screen = swr_screen(p_screen);
934 struct sw_winsys *winsys = screen->winsys;
935
936 fprintf(stderr, "SWR destroy screen!\n");
937
938 swr_fence_finish(p_screen, NULL, screen->flush_fence, 0);
939 swr_fence_reference(p_screen, &screen->flush_fence, NULL);
940
941 JitDestroyContext(screen->hJitMgr);
942
943 if (winsys->destroy)
944 winsys->destroy(winsys);
945
946 FREE(screen);
947 }
948
949 PUBLIC
950 struct pipe_screen *
951 swr_create_screen_internal(struct sw_winsys *winsys)
952 {
953 struct swr_screen *screen = CALLOC_STRUCT(swr_screen);
954
955 if (!screen)
956 return NULL;
957
958 if (!getenv("KNOB_MAX_PRIMS_PER_DRAW")) {
959 g_GlobalKnobs.MAX_PRIMS_PER_DRAW.Value(49152);
960 }
961
962 if (!lp_build_init()) {
963 FREE(screen);
964 return NULL;
965 }
966
967 screen->winsys = winsys;
968 screen->base.get_name = swr_get_name;
969 screen->base.get_vendor = swr_get_vendor;
970 screen->base.is_format_supported = swr_is_format_supported;
971 screen->base.context_create = swr_create_context;
972 screen->base.can_create_resource = swr_can_create_resource;
973
974 screen->base.destroy = swr_destroy_screen;
975 screen->base.get_param = swr_get_param;
976 screen->base.get_shader_param = swr_get_shader_param;
977 screen->base.get_paramf = swr_get_paramf;
978
979 screen->base.resource_create = swr_resource_create;
980 screen->base.resource_destroy = swr_resource_destroy;
981
982 screen->base.flush_frontbuffer = swr_flush_frontbuffer;
983
984 screen->hJitMgr = JitCreateContext(KNOB_SIMD_WIDTH, KNOB_ARCH_STR, "swr");
985
986 swr_fence_init(&screen->base);
987
988 util_format_s3tc_init();
989
990 return &screen->base;
991 }
992