1 /****************************************************************************
2 * Copyright (C) 2015 Intel Corporation. All Rights Reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 ***************************************************************************/
24 #include "swr_context.h"
25 #include "swr_public.h"
26 #include "swr_screen.h"
27 #include "swr_resource.h"
28 #include "swr_fence.h"
29 #include "gen_knobs.h"
31 #include "pipe/p_screen.h"
32 #include "pipe/p_defines.h"
33 #include "util/u_memory.h"
34 #include "util/u_format.h"
35 #include "util/u_inlines.h"
36 #include "util/u_cpu_detect.h"
37 #include "util/u_format_s3tc.h"
39 #include "state_tracker/sw_winsys.h"
42 #include "gallivm/lp_bld_limits.h"
47 #include "memory/TilingFunctions.h"
52 /* MSVC case instensitive compare */
53 #if defined(PIPE_CC_MSVC)
54 #define strcasecmp lstrcmpiA
59 * XXX Check max texture size values against core and sampler.
61 #define SWR_MAX_TEXTURE_SIZE (4 * 1024 * 1024 * 1024ULL) /* 4GB */
62 #define SWR_MAX_TEXTURE_2D_LEVELS 14 /* 8K x 8K for now */
63 #define SWR_MAX_TEXTURE_3D_LEVELS 12 /* 2K x 2K x 2K for now */
64 #define SWR_MAX_TEXTURE_CUBE_LEVELS 14 /* 8K x 8K for now */
65 #define SWR_MAX_TEXTURE_ARRAY_LAYERS 512 /* 8K x 512 / 8K x 8K x 512 */
68 swr_get_name(struct pipe_screen
*screen
)
74 swr_get_vendor(struct pipe_screen
*screen
)
76 return "Intel Corporation";
80 swr_is_format_supported(struct pipe_screen
*screen
,
81 enum pipe_format format
,
82 enum pipe_texture_target target
,
83 unsigned sample_count
,
86 struct sw_winsys
*winsys
= swr_screen(screen
)->winsys
;
87 const struct util_format_description
*format_desc
;
89 assert(target
== PIPE_BUFFER
|| target
== PIPE_TEXTURE_1D
90 || target
== PIPE_TEXTURE_1D_ARRAY
91 || target
== PIPE_TEXTURE_2D
92 || target
== PIPE_TEXTURE_2D_ARRAY
93 || target
== PIPE_TEXTURE_RECT
94 || target
== PIPE_TEXTURE_3D
95 || target
== PIPE_TEXTURE_CUBE
96 || target
== PIPE_TEXTURE_CUBE_ARRAY
);
98 format_desc
= util_format_description(format
);
102 if (sample_count
> 1)
106 & (PIPE_BIND_DISPLAY_TARGET
| PIPE_BIND_SCANOUT
| PIPE_BIND_SHARED
)) {
107 if (!winsys
->is_displaytarget_format_supported(winsys
, bind
, format
))
111 if (bind
& PIPE_BIND_RENDER_TARGET
) {
112 if (format_desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
)
115 if (mesa_to_swr_format(format
) == (SWR_FORMAT
)-1)
119 * Although possible, it is unnatural to render into compressed or YUV
120 * surfaces. So disable these here to avoid going into weird paths
121 * inside the state trackers.
123 if (format_desc
->block
.width
!= 1 || format_desc
->block
.height
!= 1)
127 if (bind
& PIPE_BIND_DEPTH_STENCIL
) {
128 if (format_desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
)
131 if (mesa_to_swr_format(format
) == (SWR_FORMAT
)-1)
135 if (format_desc
->layout
== UTIL_FORMAT_LAYOUT_BPTC
||
136 format_desc
->layout
== UTIL_FORMAT_LAYOUT_ASTC
) {
140 if (format_desc
->layout
== UTIL_FORMAT_LAYOUT_ETC
&&
141 format
!= PIPE_FORMAT_ETC1_RGB8
) {
145 if (format_desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
146 return util_format_s3tc_enabled
;
153 swr_get_param(struct pipe_screen
*screen
, enum pipe_cap param
)
157 case PIPE_CAP_MAX_RENDER_TARGETS
:
158 return PIPE_MAX_COLOR_BUFS
;
159 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
160 return SWR_MAX_TEXTURE_2D_LEVELS
;
161 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
162 return SWR_MAX_TEXTURE_3D_LEVELS
;
163 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
164 return SWR_MAX_TEXTURE_CUBE_LEVELS
;
165 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
166 return MAX_SO_STREAMS
;
167 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
168 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
169 return MAX_ATTRIBUTES
;
170 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
171 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
173 case PIPE_CAP_MAX_VERTEX_STREAMS
:
175 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
177 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
178 return SWR_MAX_TEXTURE_ARRAY_LAYERS
;
179 case PIPE_CAP_MIN_TEXEL_OFFSET
:
181 case PIPE_CAP_MAX_TEXEL_OFFSET
:
183 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
185 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
187 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
189 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
191 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
193 case PIPE_CAP_MAX_VIEWPORTS
:
195 case PIPE_CAP_ENDIANNESS
:
196 return PIPE_ENDIAN_NATIVE
;
197 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
198 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
201 /* supported features */
202 case PIPE_CAP_NPOT_TEXTURES
:
203 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
204 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS
:
205 case PIPE_CAP_TWO_SIDED_STENCIL
:
207 case PIPE_CAP_POINT_SPRITE
:
208 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
209 case PIPE_CAP_OCCLUSION_QUERY
:
210 case PIPE_CAP_QUERY_TIME_ELAPSED
:
211 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
212 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
213 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
214 case PIPE_CAP_TEXTURE_SWIZZLE
:
215 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
216 case PIPE_CAP_INDEP_BLEND_ENABLE
:
217 case PIPE_CAP_INDEP_BLEND_FUNC
:
218 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
219 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
220 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
221 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
222 case PIPE_CAP_PRIMITIVE_RESTART
:
223 case PIPE_CAP_TGSI_INSTANCEID
:
224 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
225 case PIPE_CAP_START_INSTANCE
:
226 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
227 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
228 case PIPE_CAP_CONDITIONAL_RENDER
:
229 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
230 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
231 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
232 case PIPE_CAP_USER_VERTEX_BUFFERS
:
233 case PIPE_CAP_USER_INDEX_BUFFERS
:
234 case PIPE_CAP_USER_CONSTANT_BUFFERS
:
235 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS
:
236 case PIPE_CAP_QUERY_TIMESTAMP
:
237 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
238 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
239 case PIPE_CAP_FAKE_SW_MSAA
:
240 case PIPE_CAP_DRAW_INDIRECT
:
242 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
243 case PIPE_CAP_CLIP_HALFZ
:
244 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
245 case PIPE_CAP_DEPTH_BOUNDS_TEST
:
246 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
247 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
248 case PIPE_CAP_CULL_DISTANCE
:
249 case PIPE_CAP_CUBE_MAP_ARRAY
:
252 /* unsupported features */
253 case PIPE_CAP_ANISOTROPIC_FILTER
:
254 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
255 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
256 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
257 case PIPE_CAP_TEXTURE_BARRIER
:
258 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
259 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
260 case PIPE_CAP_COMPUTE
:
261 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
262 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
263 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
264 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
265 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
266 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
267 case PIPE_CAP_TGSI_TEXCOORD
:
268 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
269 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
270 case PIPE_CAP_TEXTURE_GATHER_SM5
:
271 case PIPE_CAP_TEXTURE_QUERY_LOD
:
272 case PIPE_CAP_SAMPLE_SHADING
:
273 case PIPE_CAP_TEXTURE_GATHER_OFFSETS
:
274 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
275 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
276 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
277 case PIPE_CAP_VERTEXID_NOBASE
:
278 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE
:
279 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY
:
280 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY
:
281 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
:
282 case PIPE_CAP_TGSI_TXQS
:
283 case PIPE_CAP_FORCE_PERSAMPLE_INTERP
:
284 case PIPE_CAP_SHAREABLE_SHADERS
:
285 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
:
286 case PIPE_CAP_CLEAR_TEXTURE
:
287 case PIPE_CAP_DRAW_PARAMETERS
:
288 case PIPE_CAP_TGSI_PACK_HALF_FLOAT
:
289 case PIPE_CAP_MULTI_DRAW_INDIRECT
:
290 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS
:
291 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL
:
292 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL
:
293 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
:
294 case PIPE_CAP_INVALIDATE_BUFFER
:
295 case PIPE_CAP_GENERATE_MIPMAP
:
296 case PIPE_CAP_STRING_MARKER
:
297 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY
:
298 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS
:
299 case PIPE_CAP_QUERY_BUFFER_OBJECT
:
300 case PIPE_CAP_QUERY_MEMORY_INFO
:
301 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR
:
302 case PIPE_CAP_PCI_GROUP
:
303 case PIPE_CAP_PCI_BUS
:
304 case PIPE_CAP_PCI_DEVICE
:
305 case PIPE_CAP_PCI_FUNCTION
:
306 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT
:
307 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES
:
308 case PIPE_CAP_TGSI_VOTE
:
309 case PIPE_CAP_MAX_WINDOW_RECTANGLES
:
310 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED
:
311 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS
:
312 case PIPE_CAP_TGSI_ARRAY_COMPONENTS
:
313 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS
:
314 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
317 case PIPE_CAP_VENDOR_ID
:
319 case PIPE_CAP_DEVICE_ID
:
321 case PIPE_CAP_ACCELERATED
:
323 case PIPE_CAP_VIDEO_MEMORY
: {
324 /* XXX: Do we want to return the full amount of system memory ? */
325 uint64_t system_memory
;
327 if (!os_get_total_physical_memory(&system_memory
))
330 return (int)(system_memory
>> 20);
334 /* should only get here on unhandled cases */
335 debug_printf("Unexpected PIPE_CAP %d query\n", param
);
340 swr_get_shader_param(struct pipe_screen
*screen
,
342 enum pipe_shader_cap param
)
344 if (shader
== PIPE_SHADER_VERTEX
|| shader
== PIPE_SHADER_FRAGMENT
)
345 return gallivm_get_shader_param(param
);
347 // Todo: geometry, tesselation, compute
353 swr_get_paramf(struct pipe_screen
*screen
, enum pipe_capf param
)
356 case PIPE_CAPF_MAX_LINE_WIDTH
:
357 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
358 case PIPE_CAPF_MAX_POINT_WIDTH
:
359 return 255.0; /* arbitrary */
360 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
362 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
364 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
365 return 16.0; /* arbitrary */
366 case PIPE_CAPF_GUARD_BAND_LEFT
:
367 case PIPE_CAPF_GUARD_BAND_TOP
:
368 case PIPE_CAPF_GUARD_BAND_RIGHT
:
369 case PIPE_CAPF_GUARD_BAND_BOTTOM
:
372 /* should only get here on unhandled cases */
373 debug_printf("Unexpected PIPE_CAPF %d query\n", param
);
378 mesa_to_swr_format(enum pipe_format format
)
380 static const std::map
<pipe_format
,SWR_FORMAT
> mesa2swr
= {
381 /* depth / stencil */
382 {PIPE_FORMAT_Z16_UNORM
, R16_UNORM
}, // z
383 {PIPE_FORMAT_Z32_FLOAT
, R32_FLOAT
}, // z
384 {PIPE_FORMAT_Z24_UNORM_S8_UINT
, R24_UNORM_X8_TYPELESS
}, // z
385 {PIPE_FORMAT_Z24X8_UNORM
, R24_UNORM_X8_TYPELESS
}, // z
386 {PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
, R32_FLOAT_X8X24_TYPELESS
}, // z
389 {PIPE_FORMAT_A8_UNORM
, A8_UNORM
},
390 {PIPE_FORMAT_A16_UNORM
, A16_UNORM
},
391 {PIPE_FORMAT_A16_FLOAT
, A16_FLOAT
},
392 {PIPE_FORMAT_A32_FLOAT
, A32_FLOAT
},
395 {PIPE_FORMAT_B5G6R5_UNORM
, B5G6R5_UNORM
},
396 {PIPE_FORMAT_B5G6R5_SRGB
, B5G6R5_UNORM_SRGB
},
397 {PIPE_FORMAT_B5G5R5A1_UNORM
, B5G5R5A1_UNORM
},
398 {PIPE_FORMAT_B5G5R5X1_UNORM
, B5G5R5X1_UNORM
},
399 {PIPE_FORMAT_B4G4R4A4_UNORM
, B4G4R4A4_UNORM
},
400 {PIPE_FORMAT_B8G8R8A8_UNORM
, B8G8R8A8_UNORM
},
401 {PIPE_FORMAT_B8G8R8A8_SRGB
, B8G8R8A8_UNORM_SRGB
},
402 {PIPE_FORMAT_B8G8R8X8_UNORM
, B8G8R8X8_UNORM
},
403 {PIPE_FORMAT_B8G8R8X8_SRGB
, B8G8R8X8_UNORM_SRGB
},
406 {PIPE_FORMAT_R10G10B10A2_UNORM
, R10G10B10A2_UNORM
},
407 {PIPE_FORMAT_R10G10B10A2_SNORM
, R10G10B10A2_SNORM
},
408 {PIPE_FORMAT_R10G10B10A2_USCALED
, R10G10B10A2_USCALED
},
409 {PIPE_FORMAT_R10G10B10A2_SSCALED
, R10G10B10A2_SSCALED
},
410 {PIPE_FORMAT_R10G10B10A2_UINT
, R10G10B10A2_UINT
},
413 {PIPE_FORMAT_R10G10B10X2_USCALED
, R10G10B10X2_USCALED
},
416 {PIPE_FORMAT_B10G10R10A2_UNORM
, B10G10R10A2_UNORM
},
417 {PIPE_FORMAT_B10G10R10A2_SNORM
, B10G10R10A2_SNORM
},
418 {PIPE_FORMAT_B10G10R10A2_USCALED
, B10G10R10A2_USCALED
},
419 {PIPE_FORMAT_B10G10R10A2_SSCALED
, B10G10R10A2_SSCALED
},
420 {PIPE_FORMAT_B10G10R10A2_UINT
, B10G10R10A2_UINT
},
423 {PIPE_FORMAT_B10G10R10X2_UNORM
, B10G10R10X2_UNORM
},
426 {PIPE_FORMAT_R11G11B10_FLOAT
, R11G11B10_FLOAT
},
428 /* 32 bits per component */
429 {PIPE_FORMAT_R32_FLOAT
, R32_FLOAT
},
430 {PIPE_FORMAT_R32G32_FLOAT
, R32G32_FLOAT
},
431 {PIPE_FORMAT_R32G32B32_FLOAT
, R32G32B32_FLOAT
},
432 {PIPE_FORMAT_R32G32B32A32_FLOAT
, R32G32B32A32_FLOAT
},
433 {PIPE_FORMAT_R32G32B32X32_FLOAT
, R32G32B32X32_FLOAT
},
435 {PIPE_FORMAT_R32_USCALED
, R32_USCALED
},
436 {PIPE_FORMAT_R32G32_USCALED
, R32G32_USCALED
},
437 {PIPE_FORMAT_R32G32B32_USCALED
, R32G32B32_USCALED
},
438 {PIPE_FORMAT_R32G32B32A32_USCALED
, R32G32B32A32_USCALED
},
440 {PIPE_FORMAT_R32_SSCALED
, R32_SSCALED
},
441 {PIPE_FORMAT_R32G32_SSCALED
, R32G32_SSCALED
},
442 {PIPE_FORMAT_R32G32B32_SSCALED
, R32G32B32_SSCALED
},
443 {PIPE_FORMAT_R32G32B32A32_SSCALED
, R32G32B32A32_SSCALED
},
445 {PIPE_FORMAT_R32_UINT
, R32_UINT
},
446 {PIPE_FORMAT_R32G32_UINT
, R32G32_UINT
},
447 {PIPE_FORMAT_R32G32B32_UINT
, R32G32B32_UINT
},
448 {PIPE_FORMAT_R32G32B32A32_UINT
, R32G32B32A32_UINT
},
450 {PIPE_FORMAT_R32_SINT
, R32_SINT
},
451 {PIPE_FORMAT_R32G32_SINT
, R32G32_SINT
},
452 {PIPE_FORMAT_R32G32B32_SINT
, R32G32B32_SINT
},
453 {PIPE_FORMAT_R32G32B32A32_SINT
, R32G32B32A32_SINT
},
455 /* 16 bits per component */
456 {PIPE_FORMAT_R16_UNORM
, R16_UNORM
},
457 {PIPE_FORMAT_R16G16_UNORM
, R16G16_UNORM
},
458 {PIPE_FORMAT_R16G16B16_UNORM
, R16G16B16_UNORM
},
459 {PIPE_FORMAT_R16G16B16A16_UNORM
, R16G16B16A16_UNORM
},
460 {PIPE_FORMAT_R16G16B16X16_UNORM
, R16G16B16X16_UNORM
},
462 {PIPE_FORMAT_R16_USCALED
, R16_USCALED
},
463 {PIPE_FORMAT_R16G16_USCALED
, R16G16_USCALED
},
464 {PIPE_FORMAT_R16G16B16_USCALED
, R16G16B16_USCALED
},
465 {PIPE_FORMAT_R16G16B16A16_USCALED
, R16G16B16A16_USCALED
},
467 {PIPE_FORMAT_R16_SNORM
, R16_SNORM
},
468 {PIPE_FORMAT_R16G16_SNORM
, R16G16_SNORM
},
469 {PIPE_FORMAT_R16G16B16_SNORM
, R16G16B16_SNORM
},
470 {PIPE_FORMAT_R16G16B16A16_SNORM
, R16G16B16A16_SNORM
},
472 {PIPE_FORMAT_R16_SSCALED
, R16_SSCALED
},
473 {PIPE_FORMAT_R16G16_SSCALED
, R16G16_SSCALED
},
474 {PIPE_FORMAT_R16G16B16_SSCALED
, R16G16B16_SSCALED
},
475 {PIPE_FORMAT_R16G16B16A16_SSCALED
, R16G16B16A16_SSCALED
},
477 {PIPE_FORMAT_R16_UINT
, R16_UINT
},
478 {PIPE_FORMAT_R16G16_UINT
, R16G16_UINT
},
479 {PIPE_FORMAT_R16G16B16_UINT
, R16G16B16_UINT
},
480 {PIPE_FORMAT_R16G16B16A16_UINT
, R16G16B16A16_UINT
},
482 {PIPE_FORMAT_R16_SINT
, R16_SINT
},
483 {PIPE_FORMAT_R16G16_SINT
, R16G16_SINT
},
484 {PIPE_FORMAT_R16G16B16_SINT
, R16G16B16_SINT
},
485 {PIPE_FORMAT_R16G16B16A16_SINT
, R16G16B16A16_SINT
},
487 {PIPE_FORMAT_R16_FLOAT
, R16_FLOAT
},
488 {PIPE_FORMAT_R16G16_FLOAT
, R16G16_FLOAT
},
489 {PIPE_FORMAT_R16G16B16_FLOAT
, R16G16B16_FLOAT
},
490 {PIPE_FORMAT_R16G16B16A16_FLOAT
, R16G16B16A16_FLOAT
},
491 {PIPE_FORMAT_R16G16B16X16_FLOAT
, R16G16B16X16_FLOAT
},
493 /* 8 bits per component */
494 {PIPE_FORMAT_R8_UNORM
, R8_UNORM
},
495 {PIPE_FORMAT_R8G8_UNORM
, R8G8_UNORM
},
496 {PIPE_FORMAT_R8G8B8_UNORM
, R8G8B8_UNORM
},
497 {PIPE_FORMAT_R8G8B8_SRGB
, R8G8B8_UNORM_SRGB
},
498 {PIPE_FORMAT_R8G8B8A8_UNORM
, R8G8B8A8_UNORM
},
499 {PIPE_FORMAT_R8G8B8A8_SRGB
, R8G8B8A8_UNORM_SRGB
},
500 {PIPE_FORMAT_R8G8B8X8_UNORM
, R8G8B8X8_UNORM
},
501 {PIPE_FORMAT_R8G8B8X8_SRGB
, R8G8B8X8_UNORM_SRGB
},
503 {PIPE_FORMAT_R8_USCALED
, R8_USCALED
},
504 {PIPE_FORMAT_R8G8_USCALED
, R8G8_USCALED
},
505 {PIPE_FORMAT_R8G8B8_USCALED
, R8G8B8_USCALED
},
506 {PIPE_FORMAT_R8G8B8A8_USCALED
, R8G8B8A8_USCALED
},
508 {PIPE_FORMAT_R8_SNORM
, R8_SNORM
},
509 {PIPE_FORMAT_R8G8_SNORM
, R8G8_SNORM
},
510 {PIPE_FORMAT_R8G8B8_SNORM
, R8G8B8_SNORM
},
511 {PIPE_FORMAT_R8G8B8A8_SNORM
, R8G8B8A8_SNORM
},
513 {PIPE_FORMAT_R8_SSCALED
, R8_SSCALED
},
514 {PIPE_FORMAT_R8G8_SSCALED
, R8G8_SSCALED
},
515 {PIPE_FORMAT_R8G8B8_SSCALED
, R8G8B8_SSCALED
},
516 {PIPE_FORMAT_R8G8B8A8_SSCALED
, R8G8B8A8_SSCALED
},
518 {PIPE_FORMAT_R8_UINT
, R8_UINT
},
519 {PIPE_FORMAT_R8G8_UINT
, R8G8_UINT
},
520 {PIPE_FORMAT_R8G8B8_UINT
, R8G8B8_UINT
},
521 {PIPE_FORMAT_R8G8B8A8_UINT
, R8G8B8A8_UINT
},
523 {PIPE_FORMAT_R8_SINT
, R8_SINT
},
524 {PIPE_FORMAT_R8G8_SINT
, R8G8_SINT
},
525 {PIPE_FORMAT_R8G8B8_SINT
, R8G8B8_SINT
},
526 {PIPE_FORMAT_R8G8B8A8_SINT
, R8G8B8A8_SINT
},
528 /* These formats have entries in SWR but don't have Load/StoreTile
529 * implementations. That means these aren't renderable, and thus having
530 * a mapping entry here is detrimental.
534 {PIPE_FORMAT_L8_UNORM, L8_UNORM},
535 {PIPE_FORMAT_I8_UNORM, I8_UNORM},
536 {PIPE_FORMAT_L8A8_UNORM, L8A8_UNORM},
537 {PIPE_FORMAT_L16_UNORM, L16_UNORM},
538 {PIPE_FORMAT_UYVY, YCRCB_SWAPUVY},
540 {PIPE_FORMAT_L8_SRGB, L8_UNORM_SRGB},
541 {PIPE_FORMAT_L8A8_SRGB, L8A8_UNORM_SRGB},
543 {PIPE_FORMAT_DXT1_RGBA, BC1_UNORM},
544 {PIPE_FORMAT_DXT3_RGBA, BC2_UNORM},
545 {PIPE_FORMAT_DXT5_RGBA, BC3_UNORM},
547 {PIPE_FORMAT_DXT1_SRGBA, BC1_UNORM_SRGB},
548 {PIPE_FORMAT_DXT3_SRGBA, BC2_UNORM_SRGB},
549 {PIPE_FORMAT_DXT5_SRGBA, BC3_UNORM_SRGB},
551 {PIPE_FORMAT_RGTC1_UNORM, BC4_UNORM},
552 {PIPE_FORMAT_RGTC1_SNORM, BC4_SNORM},
553 {PIPE_FORMAT_RGTC2_UNORM, BC5_UNORM},
554 {PIPE_FORMAT_RGTC2_SNORM, BC5_SNORM},
556 {PIPE_FORMAT_L16A16_UNORM, L16A16_UNORM},
557 {PIPE_FORMAT_I16_UNORM, I16_UNORM},
558 {PIPE_FORMAT_L16_FLOAT, L16_FLOAT},
559 {PIPE_FORMAT_L16A16_FLOAT, L16A16_FLOAT},
560 {PIPE_FORMAT_I16_FLOAT, I16_FLOAT},
561 {PIPE_FORMAT_L32_FLOAT, L32_FLOAT},
562 {PIPE_FORMAT_L32A32_FLOAT, L32A32_FLOAT},
563 {PIPE_FORMAT_I32_FLOAT, I32_FLOAT},
565 {PIPE_FORMAT_I8_UINT, I8_UINT},
566 {PIPE_FORMAT_L8_UINT, L8_UINT},
567 {PIPE_FORMAT_L8A8_UINT, L8A8_UINT},
569 {PIPE_FORMAT_I8_SINT, I8_SINT},
570 {PIPE_FORMAT_L8_SINT, L8_SINT},
571 {PIPE_FORMAT_L8A8_SINT, L8A8_SINT},
576 auto it
= mesa2swr
.find(format
);
577 if (it
== mesa2swr
.end())
578 return (SWR_FORMAT
)-1;
584 swr_displaytarget_layout(struct swr_screen
*screen
, struct swr_resource
*res
)
586 struct sw_winsys
*winsys
= screen
->winsys
;
587 struct sw_displaytarget
*dt
;
589 const unsigned width
= align(res
->swr
.width
, res
->swr
.halign
);
590 const unsigned height
= align(res
->swr
.height
, res
->swr
.valign
);
593 dt
= winsys
->displaytarget_create(winsys
,
603 void *map
= winsys
->displaytarget_map(winsys
, dt
, 0);
605 res
->display_target
= dt
;
606 res
->swr
.pBaseAddress
= (uint8_t*) map
;
608 /* Clear the display target surface */
610 memset(map
, 0, height
* stride
);
612 winsys
->displaytarget_unmap(winsys
, dt
);
618 swr_texture_layout(struct swr_screen
*screen
,
619 struct swr_resource
*res
,
622 struct pipe_resource
*pt
= &res
->base
;
624 pipe_format fmt
= pt
->format
;
625 const struct util_format_description
*desc
= util_format_description(fmt
);
627 res
->has_depth
= util_format_has_depth(desc
);
628 res
->has_stencil
= util_format_has_stencil(desc
);
630 if (res
->has_stencil
&& !res
->has_depth
)
631 fmt
= PIPE_FORMAT_R8_UINT
;
633 /* We always use the SWR layout. For 2D and 3D textures this looks like:
635 * |<------- pitch ------->|
636 * +=======================+-------
642 * +-----------+-----------+ |
644 * | Level 1 | L3L3 | |
646 * +===========+===========+-------
652 * +-----------+-----------+
656 * +===========+===========+
658 * The overall width in bytes is known as the pitch, while the overall
659 * height in rows is the qpitch. Array slices are laid out logically below
660 * one another, qpitch rows apart. For 3D surfaces, the "level" values are
661 * just invalid for the higher array numbers (since depth is also
662 * minified). 1D and 1D array surfaces are stored effectively the same way,
663 * except that pitch never plays into it. All the levels are logically
664 * adjacent to each other on the X axis. The qpitch becomes the number of
665 * elements between array slices, while the pitch is unused.
667 * Each level's sizes are subject to the valign and halign settings of the
668 * surface. For compressed formats that swr is unaware of, we will use an
669 * appropriately-sized uncompressed format, and scale the widths/heights.
671 * This surface is stored inside res->swr. For depth/stencil textures,
672 * res->secondary will have an identically-laid-out but R8_UINT-formatted
673 * stencil tree. In the Z32F_S8 case, the primary surface still has 64-bpp
674 * texels, to simplify map/unmap logic which copies the stencil values
678 res
->swr
.width
= pt
->width0
;
679 res
->swr
.height
= pt
->height0
;
680 res
->swr
.type
= swr_convert_target_type(pt
->target
);
681 res
->swr
.tileMode
= SWR_TILE_NONE
;
682 res
->swr
.format
= mesa_to_swr_format(fmt
);
683 res
->swr
.numSamples
= std::max(1u, pt
->nr_samples
);
685 if (pt
->bind
& (PIPE_BIND_RENDER_TARGET
| PIPE_BIND_DEPTH_STENCIL
)) {
686 res
->swr
.halign
= KNOB_MACROTILE_X_DIM
;
687 res
->swr
.valign
= KNOB_MACROTILE_Y_DIM
;
693 unsigned halign
= res
->swr
.halign
* util_format_get_blockwidth(fmt
);
694 unsigned width
= align(pt
->width0
, halign
);
695 if (pt
->target
== PIPE_TEXTURE_1D
|| pt
->target
== PIPE_TEXTURE_1D_ARRAY
) {
696 for (int level
= 1; level
<= pt
->last_level
; level
++)
697 width
+= align(u_minify(pt
->width0
, level
), halign
);
698 res
->swr
.pitch
= util_format_get_blocksize(fmt
);
699 res
->swr
.qpitch
= util_format_get_nblocksx(fmt
, width
);
701 // The pitch is the overall width of the texture in bytes. Most of the
702 // time this is the pitch of level 0 since all the other levels fit
703 // underneath it. However in some degenerate situations, the width of
704 // level1 + level2 may be larger. In that case, we use those
705 // widths. This can happen if, e.g. halign is 32, and the width of level
706 // 0 is 32 or less. In that case, the aligned levels 1 and 2 will also
707 // be 32 each, adding up to 64.
708 unsigned valign
= res
->swr
.valign
* util_format_get_blockheight(fmt
);
709 if (pt
->last_level
> 1) {
710 width
= std::max
<uint32_t>(
712 align(u_minify(pt
->width0
, 1), halign
) +
713 align(u_minify(pt
->width0
, 2), halign
));
715 res
->swr
.pitch
= util_format_get_stride(fmt
, width
);
717 // The qpitch is controlled by either the height of the second LOD, or
718 // the combination of all the later LODs.
719 unsigned height
= align(pt
->height0
, valign
);
720 if (pt
->last_level
== 1) {
721 height
+= align(u_minify(pt
->height0
, 1), valign
);
722 } else if (pt
->last_level
> 1) {
723 unsigned level1
= align(u_minify(pt
->height0
, 1), valign
);
725 for (int level
= 2; level
<= pt
->last_level
; level
++) {
726 level2
+= align(u_minify(pt
->height0
, level
), valign
);
728 height
+= std::max(level1
, level2
);
730 res
->swr
.qpitch
= util_format_get_nblocksy(fmt
, height
);
733 if (pt
->target
== PIPE_TEXTURE_3D
)
734 res
->swr
.depth
= pt
->depth0
;
736 res
->swr
.depth
= pt
->array_size
;
738 // Fix up swr format if necessary so that LOD offset computation works
739 if (res
->swr
.format
== (SWR_FORMAT
)-1) {
740 switch (util_format_get_blocksize(fmt
)) {
742 unreachable("Unexpected format block size");
743 case 1: res
->swr
.format
= R8_UINT
; break;
744 case 2: res
->swr
.format
= R16_UINT
; break;
745 case 4: res
->swr
.format
= R32_UINT
; break;
747 if (util_format_is_compressed(fmt
))
748 res
->swr
.format
= BC4_UNORM
;
750 res
->swr
.format
= R32G32_UINT
;
753 if (util_format_is_compressed(fmt
))
754 res
->swr
.format
= BC5_UNORM
;
756 res
->swr
.format
= R32G32B32A32_UINT
;
761 for (int level
= 0; level
<= pt
->last_level
; level
++) {
762 res
->mip_offsets
[level
] =
763 ComputeSurfaceOffset
<false>(0, 0, 0, 0, 0, level
, &res
->swr
);
767 (size_t)res
->swr
.depth
* res
->swr
.qpitch
* res
->swr
.pitch
;
768 if (total_size
> SWR_MAX_TEXTURE_SIZE
)
772 res
->swr
.pBaseAddress
= (uint8_t *)AlignedMalloc(total_size
, 64);
774 if (res
->has_depth
&& res
->has_stencil
) {
775 res
->secondary
= res
->swr
;
776 res
->secondary
.format
= R8_UINT
;
777 res
->secondary
.pitch
= res
->swr
.pitch
/ util_format_get_blocksize(fmt
);
779 for (int level
= 0; level
<= pt
->last_level
; level
++) {
780 res
->secondary_mip_offsets
[level
] =
781 ComputeSurfaceOffset
<false>(0, 0, 0, 0, 0, level
, &res
->secondary
);
784 res
->secondary
.pBaseAddress
= (uint8_t *)AlignedMalloc(
785 res
->secondary
.depth
* res
->secondary
.qpitch
*
786 res
->secondary
.pitch
, 64);
794 swr_can_create_resource(struct pipe_screen
*screen
,
795 const struct pipe_resource
*templat
)
797 struct swr_resource res
;
798 memset(&res
, 0, sizeof(res
));
800 return swr_texture_layout(swr_screen(screen
), &res
, false);
803 static struct pipe_resource
*
804 swr_resource_create(struct pipe_screen
*_screen
,
805 const struct pipe_resource
*templat
)
807 struct swr_screen
*screen
= swr_screen(_screen
);
808 struct swr_resource
*res
= CALLOC_STRUCT(swr_resource
);
812 res
->base
= *templat
;
813 pipe_reference_init(&res
->base
.reference
, 1);
814 res
->base
.screen
= &screen
->base
;
816 if (swr_resource_is_texture(&res
->base
)) {
817 if (res
->base
.bind
& (PIPE_BIND_DISPLAY_TARGET
| PIPE_BIND_SCANOUT
818 | PIPE_BIND_SHARED
)) {
819 /* displayable surface
820 * first call swr_texture_layout without allocating to finish
821 * filling out the SWR_SURFAE_STATE in res */
822 swr_texture_layout(screen
, res
, false);
823 if (!swr_displaytarget_layout(screen
, res
))
827 if (!swr_texture_layout(screen
, res
, true))
831 /* other data (vertex buffer, const buffer, etc) */
832 assert(util_format_get_blocksize(templat
->format
) == 1);
833 assert(templat
->height0
== 1);
834 assert(templat
->depth0
== 1);
835 assert(templat
->last_level
== 0);
837 /* Easiest to just call swr_texture_layout, as it sets up
838 * SWR_SURFAE_STATE in res */
839 if (!swr_texture_layout(screen
, res
, true))
851 swr_resource_destroy(struct pipe_screen
*p_screen
, struct pipe_resource
*pt
)
853 struct swr_screen
*screen
= swr_screen(p_screen
);
854 struct swr_resource
*spr
= swr_resource(pt
);
855 struct pipe_context
*pipe
= screen
->pipe
;
857 /* Only wait on fence if the resource is being used */
858 if (pipe
&& spr
->status
) {
859 /* But, if there's no fence pending, submit one.
860 * XXX: Remove once draw timestamps are implmented. */
861 if (!swr_is_fence_pending(screen
->flush_fence
))
862 swr_fence_submit(swr_context(pipe
), screen
->flush_fence
);
864 swr_fence_finish(p_screen
, NULL
, screen
->flush_fence
, 0);
865 swr_resource_unused(pt
);
869 * Free resource primary surface. If resource is display target, winsys
870 * manages the buffer and will free it on displaytarget_destroy.
872 if (spr
->display_target
) {
874 struct sw_winsys
*winsys
= screen
->winsys
;
875 winsys
->displaytarget_destroy(winsys
, spr
->display_target
);
877 AlignedFree(spr
->swr
.pBaseAddress
);
879 AlignedFree(spr
->secondary
.pBaseAddress
);
886 swr_flush_frontbuffer(struct pipe_screen
*p_screen
,
887 struct pipe_resource
*resource
,
890 void *context_private
,
891 struct pipe_box
*sub_box
)
893 struct swr_screen
*screen
= swr_screen(p_screen
);
894 struct sw_winsys
*winsys
= screen
->winsys
;
895 struct swr_resource
*spr
= swr_resource(resource
);
896 struct pipe_context
*pipe
= screen
->pipe
;
899 swr_fence_finish(p_screen
, NULL
, screen
->flush_fence
, 0);
900 swr_resource_unused(resource
);
901 SwrEndFrame(swr_context(pipe
)->swrContext
);
904 debug_assert(spr
->display_target
);
905 if (spr
->display_target
)
906 winsys
->displaytarget_display(
907 winsys
, spr
->display_target
, context_private
, sub_box
);
912 swr_destroy_screen(struct pipe_screen
*p_screen
)
914 struct swr_screen
*screen
= swr_screen(p_screen
);
915 struct sw_winsys
*winsys
= screen
->winsys
;
917 fprintf(stderr
, "SWR destroy screen!\n");
919 swr_fence_finish(p_screen
, NULL
, screen
->flush_fence
, 0);
920 swr_fence_reference(p_screen
, &screen
->flush_fence
, NULL
);
922 JitDestroyContext(screen
->hJitMgr
);
925 winsys
->destroy(winsys
);
932 swr_create_screen_internal(struct sw_winsys
*winsys
)
934 struct swr_screen
*screen
= CALLOC_STRUCT(swr_screen
);
939 if (!getenv("KNOB_MAX_PRIMS_PER_DRAW")) {
940 g_GlobalKnobs
.MAX_PRIMS_PER_DRAW
.Value(49152);
943 screen
->winsys
= winsys
;
944 screen
->base
.get_name
= swr_get_name
;
945 screen
->base
.get_vendor
= swr_get_vendor
;
946 screen
->base
.is_format_supported
= swr_is_format_supported
;
947 screen
->base
.context_create
= swr_create_context
;
948 screen
->base
.can_create_resource
= swr_can_create_resource
;
950 screen
->base
.destroy
= swr_destroy_screen
;
951 screen
->base
.get_param
= swr_get_param
;
952 screen
->base
.get_shader_param
= swr_get_shader_param
;
953 screen
->base
.get_paramf
= swr_get_paramf
;
955 screen
->base
.resource_create
= swr_resource_create
;
956 screen
->base
.resource_destroy
= swr_resource_destroy
;
958 screen
->base
.flush_frontbuffer
= swr_flush_frontbuffer
;
960 screen
->hJitMgr
= JitCreateContext(KNOB_SIMD_WIDTH
, KNOB_ARCH_STR
, "swr");
962 swr_fence_init(&screen
->base
);
964 util_format_s3tc_init();
966 return &screen
->base
;