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swr: Fix build with GCC 10.
[mesa.git] / src / gallium / drivers / swr / swr_screen.cpp
1 /****************************************************************************
2 * Copyright (C) 2015 Intel Corporation. All Rights Reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 ***************************************************************************/
23
24 #include "swr_context.h"
25 #include "swr_public.h"
26 #include "swr_screen.h"
27 #include "swr_resource.h"
28 #include "swr_fence.h"
29 #include "gen_knobs.h"
30
31 #include "pipe/p_screen.h"
32 #include "pipe/p_defines.h"
33 #include "util/u_memory.h"
34 #include "util/format/u_format.h"
35 #include "util/u_inlines.h"
36 #include "util/u_cpu_detect.h"
37 #include "util/format/u_format_s3tc.h"
38 #include "util/u_string.h"
39 #include "util/u_screen.h"
40
41 #include "state_tracker/sw_winsys.h"
42
43 #include "jit_api.h"
44
45 #include "memory/TilingFunctions.h"
46
47 #include <stdio.h>
48 #include <map>
49
50 /*
51 * Max texture sizes
52 * XXX Check max texture size values against core and sampler.
53 */
54 #define SWR_MAX_TEXTURE_SIZE (2 * 1024 * 1024 * 1024ULL) /* 2GB */
55 #define SWR_MAX_TEXTURE_2D_SIZE 8192
56 #define SWR_MAX_TEXTURE_3D_LEVELS 12 /* 2K x 2K x 2K for now */
57 #define SWR_MAX_TEXTURE_CUBE_LEVELS 14 /* 8K x 8K for now */
58 #define SWR_MAX_TEXTURE_ARRAY_LAYERS 512 /* 8K x 512 / 8K x 8K x 512 */
59
60 /* Default max client_copy_limit */
61 #define SWR_CLIENT_COPY_LIMIT 8192
62
63 /* Flag indicates creation of alternate surface, to prevent recursive loop
64 * in resource creation when msaa_force_enable is set. */
65 #define SWR_RESOURCE_FLAG_ALT_SURFACE (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
66
67
68 static const char *
69 swr_get_name(struct pipe_screen *screen)
70 {
71 static char buf[100];
72 snprintf(buf, sizeof(buf), "SWR (LLVM " MESA_LLVM_VERSION_STRING ", %u bits)",
73 lp_native_vector_width);
74 return buf;
75 }
76
77 static const char *
78 swr_get_vendor(struct pipe_screen *screen)
79 {
80 return "Intel Corporation";
81 }
82
83 static bool
84 swr_is_format_supported(struct pipe_screen *_screen,
85 enum pipe_format format,
86 enum pipe_texture_target target,
87 unsigned sample_count,
88 unsigned storage_sample_count,
89 unsigned bind)
90 {
91 struct swr_screen *screen = swr_screen(_screen);
92 struct sw_winsys *winsys = screen->winsys;
93 const struct util_format_description *format_desc;
94
95 assert(target == PIPE_BUFFER || target == PIPE_TEXTURE_1D
96 || target == PIPE_TEXTURE_1D_ARRAY
97 || target == PIPE_TEXTURE_2D
98 || target == PIPE_TEXTURE_2D_ARRAY
99 || target == PIPE_TEXTURE_RECT
100 || target == PIPE_TEXTURE_3D
101 || target == PIPE_TEXTURE_CUBE
102 || target == PIPE_TEXTURE_CUBE_ARRAY);
103
104 if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
105 return false;
106
107 format_desc = util_format_description(format);
108 if (!format_desc)
109 return false;
110
111 if ((sample_count > screen->msaa_max_count)
112 || !util_is_power_of_two_or_zero(sample_count))
113 return false;
114
115 if (bind & PIPE_BIND_DISPLAY_TARGET) {
116 if (!winsys->is_displaytarget_format_supported(winsys, bind, format))
117 return false;
118 }
119
120 if (bind & PIPE_BIND_RENDER_TARGET) {
121 if (format_desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS)
122 return false;
123
124 if (mesa_to_swr_format(format) == (SWR_FORMAT)-1)
125 return false;
126
127 /*
128 * Although possible, it is unnatural to render into compressed or YUV
129 * surfaces. So disable these here to avoid going into weird paths
130 * inside the state trackers.
131 */
132 if (format_desc->block.width != 1 || format_desc->block.height != 1)
133 return false;
134 }
135
136 if (bind & PIPE_BIND_DEPTH_STENCIL) {
137 if (format_desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
138 return false;
139
140 if (mesa_to_swr_format(format) == (SWR_FORMAT)-1)
141 return false;
142 }
143
144 if (format_desc->layout == UTIL_FORMAT_LAYOUT_ASTC ||
145 format_desc->layout == UTIL_FORMAT_LAYOUT_FXT1)
146 {
147 return false;
148 }
149
150 if (format_desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
151 format != PIPE_FORMAT_ETC1_RGB8) {
152 return false;
153 }
154
155 if ((bind & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_SAMPLER_VIEW)) &&
156 ((bind & PIPE_BIND_DISPLAY_TARGET) == 0)) {
157 /* Disable all 3-channel formats, where channel size != 32 bits.
158 * In some cases we run into crashes (in generate_unswizzled_blend()),
159 * for 3-channel RGB16 variants, there was an apparent LLVM bug.
160 * In any case, disabling the shallower 3-channel formats avoids a
161 * number of issues with GL_ARB_copy_image support.
162 */
163 if (format_desc->is_array &&
164 format_desc->nr_channels == 3 &&
165 format_desc->block.bits != 96) {
166 return false;
167 }
168 }
169
170 return TRUE;
171 }
172
173 static int
174 swr_get_param(struct pipe_screen *screen, enum pipe_cap param)
175 {
176 switch (param) {
177 /* limits */
178 case PIPE_CAP_MAX_RENDER_TARGETS:
179 return PIPE_MAX_COLOR_BUFS;
180 case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
181 return SWR_MAX_TEXTURE_2D_SIZE;
182 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
183 return SWR_MAX_TEXTURE_3D_LEVELS;
184 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
185 return SWR_MAX_TEXTURE_CUBE_LEVELS;
186 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
187 return MAX_SO_STREAMS;
188 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
189 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
190 return MAX_ATTRIBUTES * 4;
191 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
192 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
193 return 1024;
194 case PIPE_CAP_MAX_VERTEX_STREAMS:
195 return 4;
196 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
197 return 2048;
198 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
199 return SWR_MAX_TEXTURE_ARRAY_LAYERS;
200 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
201 case PIPE_CAP_MIN_TEXEL_OFFSET:
202 return -8;
203 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
204 case PIPE_CAP_MAX_TEXEL_OFFSET:
205 return 7;
206 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
207 return 4;
208 case PIPE_CAP_GLSL_FEATURE_LEVEL:
209 return 330;
210 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
211 return 140;
212 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
213 return 16;
214 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
215 return 64;
216 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
217 return 65536;
218 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
219 return 1;
220 case PIPE_CAP_MAX_VIEWPORTS:
221 return KNOB_NUM_VIEWPORTS_SCISSORS;
222 case PIPE_CAP_ENDIANNESS:
223 return PIPE_ENDIAN_NATIVE;
224 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
225 return 0;
226
227 /* supported features */
228 case PIPE_CAP_NPOT_TEXTURES:
229 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
230 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
231 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
232 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
233 case PIPE_CAP_VERTEX_SHADER_SATURATE:
234 case PIPE_CAP_POINT_SPRITE:
235 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
236 case PIPE_CAP_OCCLUSION_QUERY:
237 case PIPE_CAP_QUERY_TIME_ELAPSED:
238 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
239 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
240 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
241 case PIPE_CAP_TEXTURE_SWIZZLE:
242 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
243 case PIPE_CAP_INDEP_BLEND_ENABLE:
244 case PIPE_CAP_INDEP_BLEND_FUNC:
245 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
246 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
247 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
248 case PIPE_CAP_DEPTH_CLIP_DISABLE:
249 case PIPE_CAP_PRIMITIVE_RESTART:
250 case PIPE_CAP_TGSI_INSTANCEID:
251 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
252 case PIPE_CAP_START_INSTANCE:
253 case PIPE_CAP_SEAMLESS_CUBE_MAP:
254 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
255 case PIPE_CAP_CONDITIONAL_RENDER:
256 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
257 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
258 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
259 case PIPE_CAP_USER_VERTEX_BUFFERS:
260 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
261 case PIPE_CAP_QUERY_TIMESTAMP:
262 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
263 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
264 case PIPE_CAP_DRAW_INDIRECT:
265 case PIPE_CAP_UMA:
266 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
267 case PIPE_CAP_CLIP_HALFZ:
268 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
269 case PIPE_CAP_DEPTH_BOUNDS_TEST:
270 case PIPE_CAP_CLEAR_TEXTURE:
271 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
272 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
273 case PIPE_CAP_CULL_DISTANCE:
274 case PIPE_CAP_CUBE_MAP_ARRAY:
275 case PIPE_CAP_DOUBLES:
276 case PIPE_CAP_TEXTURE_QUERY_LOD:
277 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
278 case PIPE_CAP_TGSI_TG4_COMPONENT_IN_SWIZZLE:
279 case PIPE_CAP_QUERY_SO_OVERFLOW:
280 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
281 return 1;
282
283 /* MSAA support
284 * If user has explicitly set max_sample_count = 1 (via SWR_MSAA_MAX_COUNT)
285 * then disable all MSAA support and go back to old (FAKE_SW_MSAA) caps. */
286 case PIPE_CAP_TEXTURE_MULTISAMPLE:
287 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
288 return (swr_screen(screen)->msaa_max_count > 1) ? 1 : 0;
289 case PIPE_CAP_FAKE_SW_MSAA:
290 return (swr_screen(screen)->msaa_max_count > 1) ? 0 : 1;
291
292 /* fetch jit change for 2-4GB buffers requires alignment */
293 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
294 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
295 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
296 return 1;
297
298 /* unsupported features */
299 case PIPE_CAP_ANISOTROPIC_FILTER:
300 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
301 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
302 case PIPE_CAP_SHADER_STENCIL_EXPORT:
303 case PIPE_CAP_TEXTURE_BARRIER:
304 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
305 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
306 case PIPE_CAP_COMPUTE:
307 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
308 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
309 case PIPE_CAP_TGSI_TEXCOORD:
310 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
311 case PIPE_CAP_TEXTURE_GATHER_SM5:
312 case PIPE_CAP_SAMPLE_SHADING:
313 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
314 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
315 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
316 case PIPE_CAP_SAMPLER_VIEW_TARGET:
317 case PIPE_CAP_VERTEXID_NOBASE:
318 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
319 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
320 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
321 case PIPE_CAP_TGSI_TXQS:
322 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
323 case PIPE_CAP_SHAREABLE_SHADERS:
324 case PIPE_CAP_DRAW_PARAMETERS:
325 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
326 case PIPE_CAP_MULTI_DRAW_INDIRECT:
327 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
328 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
329 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
330 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
331 case PIPE_CAP_INVALIDATE_BUFFER:
332 case PIPE_CAP_GENERATE_MIPMAP:
333 case PIPE_CAP_STRING_MARKER:
334 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
335 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
336 case PIPE_CAP_QUERY_BUFFER_OBJECT:
337 case PIPE_CAP_QUERY_MEMORY_INFO:
338 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
339 case PIPE_CAP_PCI_GROUP:
340 case PIPE_CAP_PCI_BUS:
341 case PIPE_CAP_PCI_DEVICE:
342 case PIPE_CAP_PCI_FUNCTION:
343 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
344 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
345 case PIPE_CAP_TGSI_VOTE:
346 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
347 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
348 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
349 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
350 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
351 case PIPE_CAP_NATIVE_FENCE_FD:
352 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
353 case PIPE_CAP_FBFETCH:
354 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
355 case PIPE_CAP_INT64:
356 case PIPE_CAP_INT64_DIVMOD:
357 case PIPE_CAP_TGSI_TEX_TXF_LZ:
358 case PIPE_CAP_TGSI_CLOCK:
359 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
360 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
361 case PIPE_CAP_TGSI_BALLOT:
362 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
363 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
364 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
365 case PIPE_CAP_POST_DEPTH_COVERAGE:
366 case PIPE_CAP_BINDLESS_TEXTURE:
367 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
368 case PIPE_CAP_MEMOBJ:
369 case PIPE_CAP_LOAD_CONSTBUF:
370 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
371 case PIPE_CAP_TILE_RASTER_ORDER:
372 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
373 case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
374 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
375 case PIPE_CAP_CONTEXT_PRIORITY_MASK:
376 case PIPE_CAP_FENCE_SIGNAL:
377 case PIPE_CAP_CONSTBUF0_FLAGS:
378 case PIPE_CAP_PACKED_UNIFORMS:
379 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
380 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
381 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
382 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
383 case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
384 case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
385 case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
386 case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
387 case PIPE_CAP_IMAGE_LOAD_FORMATTED:
388 case PIPE_CAP_TGSI_ATOMINC_WRAP:
389 return 0;
390 case PIPE_CAP_MAX_GS_INVOCATIONS:
391 return 32;
392 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
393 return 1 << 27;
394 case PIPE_CAP_MAX_VARYINGS:
395 return 32;
396
397 case PIPE_CAP_VENDOR_ID:
398 return 0xFFFFFFFF;
399 case PIPE_CAP_DEVICE_ID:
400 return 0xFFFFFFFF;
401 case PIPE_CAP_ACCELERATED:
402 return 0;
403 case PIPE_CAP_VIDEO_MEMORY: {
404 /* XXX: Do we want to return the full amount of system memory ? */
405 uint64_t system_memory;
406
407 if (!os_get_total_physical_memory(&system_memory))
408 return 0;
409
410 return (int)(system_memory >> 20);
411 }
412 default:
413 return u_pipe_screen_get_param_defaults(screen, param);
414 }
415 }
416
417 static int
418 swr_get_shader_param(struct pipe_screen *screen,
419 enum pipe_shader_type shader,
420 enum pipe_shader_cap param)
421 {
422 if (shader == PIPE_SHADER_VERTEX ||
423 shader == PIPE_SHADER_FRAGMENT ||
424 shader == PIPE_SHADER_GEOMETRY
425 || shader == PIPE_SHADER_TESS_CTRL ||
426 shader == PIPE_SHADER_TESS_EVAL
427 )
428 return gallivm_get_shader_param(param);
429
430 // Todo: compute
431 return 0;
432 }
433
434
435 static float
436 swr_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
437 {
438 switch (param) {
439 case PIPE_CAPF_MAX_LINE_WIDTH:
440 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
441 case PIPE_CAPF_MAX_POINT_WIDTH:
442 return 255.0; /* arbitrary */
443 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
444 return 0.0;
445 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
446 return 0.0;
447 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
448 return 16.0; /* arbitrary */
449 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
450 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
451 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
452 return 0.0f;
453 }
454 /* should only get here on unhandled cases */
455 debug_printf("Unexpected PIPE_CAPF %d query\n", param);
456 return 0.0;
457 }
458
459 SWR_FORMAT
460 mesa_to_swr_format(enum pipe_format format)
461 {
462 static const std::map<pipe_format,SWR_FORMAT> mesa2swr = {
463 /* depth / stencil */
464 {PIPE_FORMAT_Z16_UNORM, R16_UNORM}, // z
465 {PIPE_FORMAT_Z32_FLOAT, R32_FLOAT}, // z
466 {PIPE_FORMAT_Z24_UNORM_S8_UINT, R24_UNORM_X8_TYPELESS}, // z
467 {PIPE_FORMAT_Z24X8_UNORM, R24_UNORM_X8_TYPELESS}, // z
468 {PIPE_FORMAT_Z32_FLOAT_S8X24_UINT, R32_FLOAT_X8X24_TYPELESS}, // z
469
470 /* alpha */
471 {PIPE_FORMAT_A8_UNORM, A8_UNORM},
472 {PIPE_FORMAT_A16_UNORM, A16_UNORM},
473 {PIPE_FORMAT_A16_FLOAT, A16_FLOAT},
474 {PIPE_FORMAT_A32_FLOAT, A32_FLOAT},
475
476 /* odd sizes, bgr */
477 {PIPE_FORMAT_B5G6R5_UNORM, B5G6R5_UNORM},
478 {PIPE_FORMAT_B5G6R5_SRGB, B5G6R5_UNORM_SRGB},
479 {PIPE_FORMAT_B5G5R5A1_UNORM, B5G5R5A1_UNORM},
480 {PIPE_FORMAT_B5G5R5X1_UNORM, B5G5R5X1_UNORM},
481 {PIPE_FORMAT_B4G4R4A4_UNORM, B4G4R4A4_UNORM},
482 {PIPE_FORMAT_B8G8R8A8_UNORM, B8G8R8A8_UNORM},
483 {PIPE_FORMAT_B8G8R8A8_SRGB, B8G8R8A8_UNORM_SRGB},
484 {PIPE_FORMAT_B8G8R8X8_UNORM, B8G8R8X8_UNORM},
485 {PIPE_FORMAT_B8G8R8X8_SRGB, B8G8R8X8_UNORM_SRGB},
486
487 /* rgb10a2 */
488 {PIPE_FORMAT_R10G10B10A2_UNORM, R10G10B10A2_UNORM},
489 {PIPE_FORMAT_R10G10B10A2_SNORM, R10G10B10A2_SNORM},
490 {PIPE_FORMAT_R10G10B10A2_USCALED, R10G10B10A2_USCALED},
491 {PIPE_FORMAT_R10G10B10A2_SSCALED, R10G10B10A2_SSCALED},
492 {PIPE_FORMAT_R10G10B10A2_UINT, R10G10B10A2_UINT},
493
494 /* rgb10x2 */
495 {PIPE_FORMAT_R10G10B10X2_USCALED, R10G10B10X2_USCALED},
496
497 /* bgr10a2 */
498 {PIPE_FORMAT_B10G10R10A2_UNORM, B10G10R10A2_UNORM},
499 {PIPE_FORMAT_B10G10R10A2_SNORM, B10G10R10A2_SNORM},
500 {PIPE_FORMAT_B10G10R10A2_USCALED, B10G10R10A2_USCALED},
501 {PIPE_FORMAT_B10G10R10A2_SSCALED, B10G10R10A2_SSCALED},
502 {PIPE_FORMAT_B10G10R10A2_UINT, B10G10R10A2_UINT},
503
504 /* bgr10x2 */
505 {PIPE_FORMAT_B10G10R10X2_UNORM, B10G10R10X2_UNORM},
506
507 /* r11g11b10 */
508 {PIPE_FORMAT_R11G11B10_FLOAT, R11G11B10_FLOAT},
509
510 /* 32 bits per component */
511 {PIPE_FORMAT_R32_FLOAT, R32_FLOAT},
512 {PIPE_FORMAT_R32G32_FLOAT, R32G32_FLOAT},
513 {PIPE_FORMAT_R32G32B32_FLOAT, R32G32B32_FLOAT},
514 {PIPE_FORMAT_R32G32B32A32_FLOAT, R32G32B32A32_FLOAT},
515 {PIPE_FORMAT_R32G32B32X32_FLOAT, R32G32B32X32_FLOAT},
516
517 {PIPE_FORMAT_R32_USCALED, R32_USCALED},
518 {PIPE_FORMAT_R32G32_USCALED, R32G32_USCALED},
519 {PIPE_FORMAT_R32G32B32_USCALED, R32G32B32_USCALED},
520 {PIPE_FORMAT_R32G32B32A32_USCALED, R32G32B32A32_USCALED},
521
522 {PIPE_FORMAT_R32_SSCALED, R32_SSCALED},
523 {PIPE_FORMAT_R32G32_SSCALED, R32G32_SSCALED},
524 {PIPE_FORMAT_R32G32B32_SSCALED, R32G32B32_SSCALED},
525 {PIPE_FORMAT_R32G32B32A32_SSCALED, R32G32B32A32_SSCALED},
526
527 {PIPE_FORMAT_R32_UINT, R32_UINT},
528 {PIPE_FORMAT_R32G32_UINT, R32G32_UINT},
529 {PIPE_FORMAT_R32G32B32_UINT, R32G32B32_UINT},
530 {PIPE_FORMAT_R32G32B32A32_UINT, R32G32B32A32_UINT},
531
532 {PIPE_FORMAT_R32_SINT, R32_SINT},
533 {PIPE_FORMAT_R32G32_SINT, R32G32_SINT},
534 {PIPE_FORMAT_R32G32B32_SINT, R32G32B32_SINT},
535 {PIPE_FORMAT_R32G32B32A32_SINT, R32G32B32A32_SINT},
536
537 /* 16 bits per component */
538 {PIPE_FORMAT_R16_UNORM, R16_UNORM},
539 {PIPE_FORMAT_R16G16_UNORM, R16G16_UNORM},
540 {PIPE_FORMAT_R16G16B16_UNORM, R16G16B16_UNORM},
541 {PIPE_FORMAT_R16G16B16A16_UNORM, R16G16B16A16_UNORM},
542 {PIPE_FORMAT_R16G16B16X16_UNORM, R16G16B16X16_UNORM},
543
544 {PIPE_FORMAT_R16_USCALED, R16_USCALED},
545 {PIPE_FORMAT_R16G16_USCALED, R16G16_USCALED},
546 {PIPE_FORMAT_R16G16B16_USCALED, R16G16B16_USCALED},
547 {PIPE_FORMAT_R16G16B16A16_USCALED, R16G16B16A16_USCALED},
548
549 {PIPE_FORMAT_R16_SNORM, R16_SNORM},
550 {PIPE_FORMAT_R16G16_SNORM, R16G16_SNORM},
551 {PIPE_FORMAT_R16G16B16_SNORM, R16G16B16_SNORM},
552 {PIPE_FORMAT_R16G16B16A16_SNORM, R16G16B16A16_SNORM},
553
554 {PIPE_FORMAT_R16_SSCALED, R16_SSCALED},
555 {PIPE_FORMAT_R16G16_SSCALED, R16G16_SSCALED},
556 {PIPE_FORMAT_R16G16B16_SSCALED, R16G16B16_SSCALED},
557 {PIPE_FORMAT_R16G16B16A16_SSCALED, R16G16B16A16_SSCALED},
558
559 {PIPE_FORMAT_R16_UINT, R16_UINT},
560 {PIPE_FORMAT_R16G16_UINT, R16G16_UINT},
561 {PIPE_FORMAT_R16G16B16_UINT, R16G16B16_UINT},
562 {PIPE_FORMAT_R16G16B16A16_UINT, R16G16B16A16_UINT},
563
564 {PIPE_FORMAT_R16_SINT, R16_SINT},
565 {PIPE_FORMAT_R16G16_SINT, R16G16_SINT},
566 {PIPE_FORMAT_R16G16B16_SINT, R16G16B16_SINT},
567 {PIPE_FORMAT_R16G16B16A16_SINT, R16G16B16A16_SINT},
568
569 {PIPE_FORMAT_R16_FLOAT, R16_FLOAT},
570 {PIPE_FORMAT_R16G16_FLOAT, R16G16_FLOAT},
571 {PIPE_FORMAT_R16G16B16_FLOAT, R16G16B16_FLOAT},
572 {PIPE_FORMAT_R16G16B16A16_FLOAT, R16G16B16A16_FLOAT},
573 {PIPE_FORMAT_R16G16B16X16_FLOAT, R16G16B16X16_FLOAT},
574
575 /* 8 bits per component */
576 {PIPE_FORMAT_R8_UNORM, R8_UNORM},
577 {PIPE_FORMAT_R8G8_UNORM, R8G8_UNORM},
578 {PIPE_FORMAT_R8G8B8_UNORM, R8G8B8_UNORM},
579 {PIPE_FORMAT_R8G8B8_SRGB, R8G8B8_UNORM_SRGB},
580 {PIPE_FORMAT_R8G8B8A8_UNORM, R8G8B8A8_UNORM},
581 {PIPE_FORMAT_R8G8B8A8_SRGB, R8G8B8A8_UNORM_SRGB},
582 {PIPE_FORMAT_R8G8B8X8_UNORM, R8G8B8X8_UNORM},
583 {PIPE_FORMAT_R8G8B8X8_SRGB, R8G8B8X8_UNORM_SRGB},
584
585 {PIPE_FORMAT_R8_USCALED, R8_USCALED},
586 {PIPE_FORMAT_R8G8_USCALED, R8G8_USCALED},
587 {PIPE_FORMAT_R8G8B8_USCALED, R8G8B8_USCALED},
588 {PIPE_FORMAT_R8G8B8A8_USCALED, R8G8B8A8_USCALED},
589
590 {PIPE_FORMAT_R8_SNORM, R8_SNORM},
591 {PIPE_FORMAT_R8G8_SNORM, R8G8_SNORM},
592 {PIPE_FORMAT_R8G8B8_SNORM, R8G8B8_SNORM},
593 {PIPE_FORMAT_R8G8B8A8_SNORM, R8G8B8A8_SNORM},
594
595 {PIPE_FORMAT_R8_SSCALED, R8_SSCALED},
596 {PIPE_FORMAT_R8G8_SSCALED, R8G8_SSCALED},
597 {PIPE_FORMAT_R8G8B8_SSCALED, R8G8B8_SSCALED},
598 {PIPE_FORMAT_R8G8B8A8_SSCALED, R8G8B8A8_SSCALED},
599
600 {PIPE_FORMAT_R8_UINT, R8_UINT},
601 {PIPE_FORMAT_R8G8_UINT, R8G8_UINT},
602 {PIPE_FORMAT_R8G8B8_UINT, R8G8B8_UINT},
603 {PIPE_FORMAT_R8G8B8A8_UINT, R8G8B8A8_UINT},
604
605 {PIPE_FORMAT_R8_SINT, R8_SINT},
606 {PIPE_FORMAT_R8G8_SINT, R8G8_SINT},
607 {PIPE_FORMAT_R8G8B8_SINT, R8G8B8_SINT},
608 {PIPE_FORMAT_R8G8B8A8_SINT, R8G8B8A8_SINT},
609
610 /* These formats are valid for vertex data, but should not be used
611 * for render targets.
612 */
613
614 {PIPE_FORMAT_R32_FIXED, R32_SFIXED},
615 {PIPE_FORMAT_R32G32_FIXED, R32G32_SFIXED},
616 {PIPE_FORMAT_R32G32B32_FIXED, R32G32B32_SFIXED},
617 {PIPE_FORMAT_R32G32B32A32_FIXED, R32G32B32A32_SFIXED},
618
619 {PIPE_FORMAT_R64_FLOAT, R64_FLOAT},
620 {PIPE_FORMAT_R64G64_FLOAT, R64G64_FLOAT},
621 {PIPE_FORMAT_R64G64B64_FLOAT, R64G64B64_FLOAT},
622 {PIPE_FORMAT_R64G64B64A64_FLOAT, R64G64B64A64_FLOAT},
623
624 /* These formats have entries in SWR but don't have Load/StoreTile
625 * implementations. That means these aren't renderable, and thus having
626 * a mapping entry here is detrimental.
627 */
628 /*
629
630 {PIPE_FORMAT_L8_UNORM, L8_UNORM},
631 {PIPE_FORMAT_I8_UNORM, I8_UNORM},
632 {PIPE_FORMAT_L8A8_UNORM, L8A8_UNORM},
633 {PIPE_FORMAT_L16_UNORM, L16_UNORM},
634 {PIPE_FORMAT_UYVY, YCRCB_SWAPUVY},
635
636 {PIPE_FORMAT_L8_SRGB, L8_UNORM_SRGB},
637 {PIPE_FORMAT_L8A8_SRGB, L8A8_UNORM_SRGB},
638
639 {PIPE_FORMAT_DXT1_RGBA, BC1_UNORM},
640 {PIPE_FORMAT_DXT3_RGBA, BC2_UNORM},
641 {PIPE_FORMAT_DXT5_RGBA, BC3_UNORM},
642
643 {PIPE_FORMAT_DXT1_SRGBA, BC1_UNORM_SRGB},
644 {PIPE_FORMAT_DXT3_SRGBA, BC2_UNORM_SRGB},
645 {PIPE_FORMAT_DXT5_SRGBA, BC3_UNORM_SRGB},
646
647 {PIPE_FORMAT_RGTC1_UNORM, BC4_UNORM},
648 {PIPE_FORMAT_RGTC1_SNORM, BC4_SNORM},
649 {PIPE_FORMAT_RGTC2_UNORM, BC5_UNORM},
650 {PIPE_FORMAT_RGTC2_SNORM, BC5_SNORM},
651
652 {PIPE_FORMAT_L16A16_UNORM, L16A16_UNORM},
653 {PIPE_FORMAT_I16_UNORM, I16_UNORM},
654 {PIPE_FORMAT_L16_FLOAT, L16_FLOAT},
655 {PIPE_FORMAT_L16A16_FLOAT, L16A16_FLOAT},
656 {PIPE_FORMAT_I16_FLOAT, I16_FLOAT},
657 {PIPE_FORMAT_L32_FLOAT, L32_FLOAT},
658 {PIPE_FORMAT_L32A32_FLOAT, L32A32_FLOAT},
659 {PIPE_FORMAT_I32_FLOAT, I32_FLOAT},
660
661 {PIPE_FORMAT_I8_UINT, I8_UINT},
662 {PIPE_FORMAT_L8_UINT, L8_UINT},
663 {PIPE_FORMAT_L8A8_UINT, L8A8_UINT},
664
665 {PIPE_FORMAT_I8_SINT, I8_SINT},
666 {PIPE_FORMAT_L8_SINT, L8_SINT},
667 {PIPE_FORMAT_L8A8_SINT, L8A8_SINT},
668
669 */
670 };
671
672 auto it = mesa2swr.find(format);
673 if (it == mesa2swr.end())
674 return (SWR_FORMAT)-1;
675 else
676 return it->second;
677 }
678
679 static bool
680 swr_displaytarget_layout(struct swr_screen *screen, struct swr_resource *res)
681 {
682 struct sw_winsys *winsys = screen->winsys;
683 struct sw_displaytarget *dt;
684
685 const unsigned width = align(res->swr.width, res->swr.halign);
686 const unsigned height = align(res->swr.height, res->swr.valign);
687
688 UINT stride;
689 dt = winsys->displaytarget_create(winsys,
690 res->base.bind,
691 res->base.format,
692 width, height,
693 64, NULL,
694 &stride);
695
696 if (dt == NULL)
697 return false;
698
699 void *map = winsys->displaytarget_map(winsys, dt, 0);
700
701 res->display_target = dt;
702 res->swr.xpBaseAddress = (gfxptr_t)map;
703
704 /* Clear the display target surface */
705 if (map)
706 memset(map, 0, height * stride);
707
708 winsys->displaytarget_unmap(winsys, dt);
709
710 return true;
711 }
712
713 static bool
714 swr_texture_layout(struct swr_screen *screen,
715 struct swr_resource *res,
716 bool allocate)
717 {
718 struct pipe_resource *pt = &res->base;
719
720 pipe_format fmt = pt->format;
721 const struct util_format_description *desc = util_format_description(fmt);
722
723 res->has_depth = util_format_has_depth(desc);
724 res->has_stencil = util_format_has_stencil(desc);
725
726 if (res->has_stencil && !res->has_depth)
727 fmt = PIPE_FORMAT_R8_UINT;
728
729 /* We always use the SWR layout. For 2D and 3D textures this looks like:
730 *
731 * |<------- pitch ------->|
732 * +=======================+-------
733 * |Array 0 | ^
734 * | | |
735 * | Level 0 | |
736 * | | |
737 * | | qpitch
738 * +-----------+-----------+ |
739 * | | L2L2L2L2 | |
740 * | Level 1 | L3L3 | |
741 * | | L4 | v
742 * +===========+===========+-------
743 * |Array 1 |
744 * | |
745 * | Level 0 |
746 * | |
747 * | |
748 * +-----------+-----------+
749 * | | L2L2L2L2 |
750 * | Level 1 | L3L3 |
751 * | | L4 |
752 * +===========+===========+
753 *
754 * The overall width in bytes is known as the pitch, while the overall
755 * height in rows is the qpitch. Array slices are laid out logically below
756 * one another, qpitch rows apart. For 3D surfaces, the "level" values are
757 * just invalid for the higher array numbers (since depth is also
758 * minified). 1D and 1D array surfaces are stored effectively the same way,
759 * except that pitch never plays into it. All the levels are logically
760 * adjacent to each other on the X axis. The qpitch becomes the number of
761 * elements between array slices, while the pitch is unused.
762 *
763 * Each level's sizes are subject to the valign and halign settings of the
764 * surface. For compressed formats that swr is unaware of, we will use an
765 * appropriately-sized uncompressed format, and scale the widths/heights.
766 *
767 * This surface is stored inside res->swr. For depth/stencil textures,
768 * res->secondary will have an identically-laid-out but R8_UINT-formatted
769 * stencil tree. In the Z32F_S8 case, the primary surface still has 64-bpp
770 * texels, to simplify map/unmap logic which copies the stencil values
771 * in/out.
772 */
773
774 res->swr.width = pt->width0;
775 res->swr.height = pt->height0;
776 res->swr.type = swr_convert_target_type(pt->target);
777 res->swr.tileMode = SWR_TILE_NONE;
778 res->swr.format = mesa_to_swr_format(fmt);
779 res->swr.numSamples = std::max(1u, pt->nr_samples);
780
781 if (pt->bind & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DEPTH_STENCIL)) {
782 res->swr.halign = KNOB_MACROTILE_X_DIM;
783 res->swr.valign = KNOB_MACROTILE_Y_DIM;
784
785 /* If SWR_MSAA_FORCE_ENABLE is set, turn on MSAA and override requested
786 * surface sample count. */
787 if (screen->msaa_force_enable) {
788 res->swr.numSamples = screen->msaa_max_count;
789 swr_print_info("swr_texture_layout: forcing sample count: %d\n",
790 res->swr.numSamples);
791 }
792 } else {
793 res->swr.halign = 1;
794 res->swr.valign = 1;
795 }
796
797 unsigned halign = res->swr.halign * util_format_get_blockwidth(fmt);
798 unsigned width = align(pt->width0, halign);
799 if (pt->target == PIPE_TEXTURE_1D || pt->target == PIPE_TEXTURE_1D_ARRAY) {
800 for (int level = 1; level <= pt->last_level; level++)
801 width += align(u_minify(pt->width0, level), halign);
802 res->swr.pitch = util_format_get_blocksize(fmt);
803 res->swr.qpitch = util_format_get_nblocksx(fmt, width);
804 } else {
805 // The pitch is the overall width of the texture in bytes. Most of the
806 // time this is the pitch of level 0 since all the other levels fit
807 // underneath it. However in some degenerate situations, the width of
808 // level1 + level2 may be larger. In that case, we use those
809 // widths. This can happen if, e.g. halign is 32, and the width of level
810 // 0 is 32 or less. In that case, the aligned levels 1 and 2 will also
811 // be 32 each, adding up to 64.
812 unsigned valign = res->swr.valign * util_format_get_blockheight(fmt);
813 if (pt->last_level > 1) {
814 width = std::max<uint32_t>(
815 width,
816 align(u_minify(pt->width0, 1), halign) +
817 align(u_minify(pt->width0, 2), halign));
818 }
819 res->swr.pitch = util_format_get_stride(fmt, width);
820
821 // The qpitch is controlled by either the height of the second LOD, or
822 // the combination of all the later LODs.
823 unsigned height = align(pt->height0, valign);
824 if (pt->last_level == 1) {
825 height += align(u_minify(pt->height0, 1), valign);
826 } else if (pt->last_level > 1) {
827 unsigned level1 = align(u_minify(pt->height0, 1), valign);
828 unsigned level2 = 0;
829 for (int level = 2; level <= pt->last_level; level++) {
830 level2 += align(u_minify(pt->height0, level), valign);
831 }
832 height += std::max(level1, level2);
833 }
834 res->swr.qpitch = util_format_get_nblocksy(fmt, height);
835 }
836
837 if (pt->target == PIPE_TEXTURE_3D)
838 res->swr.depth = pt->depth0;
839 else
840 res->swr.depth = pt->array_size;
841
842 // Fix up swr format if necessary so that LOD offset computation works
843 if (res->swr.format == (SWR_FORMAT)-1) {
844 switch (util_format_get_blocksize(fmt)) {
845 default:
846 unreachable("Unexpected format block size");
847 case 1: res->swr.format = R8_UINT; break;
848 case 2: res->swr.format = R16_UINT; break;
849 case 4: res->swr.format = R32_UINT; break;
850 case 8:
851 if (util_format_is_compressed(fmt))
852 res->swr.format = BC4_UNORM;
853 else
854 res->swr.format = R32G32_UINT;
855 break;
856 case 16:
857 if (util_format_is_compressed(fmt))
858 res->swr.format = BC5_UNORM;
859 else
860 res->swr.format = R32G32B32A32_UINT;
861 break;
862 }
863 }
864
865 for (int level = 0; level <= pt->last_level; level++) {
866 res->mip_offsets[level] =
867 ComputeSurfaceOffset<false>(0, 0, 0, 0, 0, level, &res->swr);
868 }
869
870 size_t total_size = (uint64_t)res->swr.depth * res->swr.qpitch *
871 res->swr.pitch * res->swr.numSamples;
872
873 // Let non-sampled textures (e.g. buffer objects) bypass the size limit
874 if (swr_resource_is_texture(&res->base) && total_size > SWR_MAX_TEXTURE_SIZE)
875 return false;
876
877 if (allocate) {
878 res->swr.xpBaseAddress = (gfxptr_t)AlignedMalloc(total_size, 64);
879 if (!res->swr.xpBaseAddress)
880 return false;
881
882 if (res->has_depth && res->has_stencil) {
883 res->secondary = res->swr;
884 res->secondary.format = R8_UINT;
885 res->secondary.pitch = res->swr.pitch / util_format_get_blocksize(fmt);
886
887 for (int level = 0; level <= pt->last_level; level++) {
888 res->secondary_mip_offsets[level] =
889 ComputeSurfaceOffset<false>(0, 0, 0, 0, 0, level, &res->secondary);
890 }
891
892 total_size = res->secondary.depth * res->secondary.qpitch *
893 res->secondary.pitch * res->secondary.numSamples;
894
895 res->secondary.xpBaseAddress = (gfxptr_t) AlignedMalloc(total_size, 64);
896 if (!res->secondary.xpBaseAddress) {
897 AlignedFree((void *)res->swr.xpBaseAddress);
898 return false;
899 }
900 }
901 }
902
903 return true;
904 }
905
906 static bool
907 swr_can_create_resource(struct pipe_screen *screen,
908 const struct pipe_resource *templat)
909 {
910 struct swr_resource res;
911 memset(&res, 0, sizeof(res));
912 res.base = *templat;
913 return swr_texture_layout(swr_screen(screen), &res, false);
914 }
915
916 /* Helper function that conditionally creates a single-sample resolve resource
917 * and attaches it to main multisample resource. */
918 static bool
919 swr_create_resolve_resource(struct pipe_screen *_screen,
920 struct swr_resource *msaa_res)
921 {
922 struct swr_screen *screen = swr_screen(_screen);
923
924 /* If resource is multisample, create a single-sample resolve resource */
925 if (msaa_res->base.nr_samples > 1 || (screen->msaa_force_enable &&
926 !(msaa_res->base.flags & SWR_RESOURCE_FLAG_ALT_SURFACE))) {
927
928 /* Create a single-sample copy of the resource. Copy the original
929 * resource parameters and set flag to prevent recursion when re-calling
930 * resource_create */
931 struct pipe_resource alt_template = msaa_res->base;
932 alt_template.nr_samples = 0;
933 alt_template.flags |= SWR_RESOURCE_FLAG_ALT_SURFACE;
934
935 /* Note: Display_target is a special single-sample resource, only the
936 * display_target has been created already. */
937 if (msaa_res->base.bind & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT
938 | PIPE_BIND_SHARED)) {
939 /* Allocate the multisample buffers. */
940 if (!swr_texture_layout(screen, msaa_res, true))
941 return false;
942
943 /* Alt resource will only be bound as PIPE_BIND_RENDER_TARGET
944 * remove the DISPLAY_TARGET, SCANOUT, and SHARED bindings */
945 alt_template.bind = PIPE_BIND_RENDER_TARGET;
946 }
947
948 /* Allocate single-sample resolve surface */
949 struct pipe_resource *alt;
950 alt = _screen->resource_create(_screen, &alt_template);
951 if (!alt)
952 return false;
953
954 /* Attach it to the multisample resource */
955 msaa_res->resolve_target = alt;
956
957 /* Hang resolve surface state off the multisample surface state to so
958 * StoreTiles knows where to resolve the surface. */
959 msaa_res->swr.xpAuxBaseAddress = (gfxptr_t)&swr_resource(alt)->swr;
960 }
961
962 return true; /* success */
963 }
964
965 static struct pipe_resource *
966 swr_resource_create(struct pipe_screen *_screen,
967 const struct pipe_resource *templat)
968 {
969 struct swr_screen *screen = swr_screen(_screen);
970 struct swr_resource *res = CALLOC_STRUCT(swr_resource);
971 if (!res)
972 return NULL;
973
974 res->base = *templat;
975 pipe_reference_init(&res->base.reference, 1);
976 res->base.screen = &screen->base;
977
978 if (swr_resource_is_texture(&res->base)) {
979 if (res->base.bind & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT
980 | PIPE_BIND_SHARED)) {
981 /* displayable surface
982 * first call swr_texture_layout without allocating to finish
983 * filling out the SWR_SURFACE_STATE in res */
984 swr_texture_layout(screen, res, false);
985 if (!swr_displaytarget_layout(screen, res))
986 goto fail;
987 } else {
988 /* texture map */
989 if (!swr_texture_layout(screen, res, true))
990 goto fail;
991 }
992
993 /* If resource was multisample, create resolve resource and attach
994 * it to multisample resource. */
995 if (!swr_create_resolve_resource(_screen, res))
996 goto fail;
997
998 } else {
999 /* other data (vertex buffer, const buffer, etc) */
1000 assert(util_format_get_blocksize(templat->format) == 1);
1001 assert(templat->height0 == 1);
1002 assert(templat->depth0 == 1);
1003 assert(templat->last_level == 0);
1004
1005 /* Easiest to just call swr_texture_layout, as it sets up
1006 * SWR_SURFACE_STATE in res */
1007 if (!swr_texture_layout(screen, res, true))
1008 goto fail;
1009 }
1010
1011 return &res->base;
1012
1013 fail:
1014 FREE(res);
1015 return NULL;
1016 }
1017
1018 static void
1019 swr_resource_destroy(struct pipe_screen *p_screen, struct pipe_resource *pt)
1020 {
1021 struct swr_screen *screen = swr_screen(p_screen);
1022 struct swr_resource *spr = swr_resource(pt);
1023
1024 if (spr->display_target) {
1025 /* If resource is display target, winsys manages the buffer and will
1026 * free it on displaytarget_destroy. */
1027 swr_fence_finish(p_screen, NULL, screen->flush_fence, 0);
1028
1029 struct sw_winsys *winsys = screen->winsys;
1030 winsys->displaytarget_destroy(winsys, spr->display_target);
1031
1032 if (spr->swr.numSamples > 1) {
1033 /* Free an attached resolve resource */
1034 struct swr_resource *alt = swr_resource(spr->resolve_target);
1035 swr_fence_work_free(screen->flush_fence, (void*)(alt->swr.xpBaseAddress), true);
1036
1037 /* Free multisample buffer */
1038 swr_fence_work_free(screen->flush_fence, (void*)(spr->swr.xpBaseAddress), true);
1039 }
1040 } else {
1041 /* For regular resources, defer deletion */
1042 swr_resource_unused(pt);
1043
1044 if (spr->swr.numSamples > 1) {
1045 /* Free an attached resolve resource */
1046 struct swr_resource *alt = swr_resource(spr->resolve_target);
1047 swr_fence_work_free(screen->flush_fence, (void*)(alt->swr.xpBaseAddress), true);
1048 }
1049
1050 swr_fence_work_free(screen->flush_fence, (void*)(spr->swr.xpBaseAddress), true);
1051 swr_fence_work_free(screen->flush_fence,
1052 (void*)(spr->secondary.xpBaseAddress), true);
1053
1054 /* If work queue grows too large, submit a fence to force queue to
1055 * drain. This is mainly to decrease the amount of memory used by the
1056 * piglit streaming-texture-leak test */
1057 if (screen->pipe && swr_fence(screen->flush_fence)->work.count > 64)
1058 swr_fence_submit(swr_context(screen->pipe), screen->flush_fence);
1059 }
1060
1061 FREE(spr);
1062 }
1063
1064
1065 static void
1066 swr_flush_frontbuffer(struct pipe_screen *p_screen,
1067 struct pipe_resource *resource,
1068 unsigned level,
1069 unsigned layer,
1070 void *context_private,
1071 struct pipe_box *sub_box)
1072 {
1073 struct swr_screen *screen = swr_screen(p_screen);
1074 struct sw_winsys *winsys = screen->winsys;
1075 struct swr_resource *spr = swr_resource(resource);
1076 struct pipe_context *pipe = screen->pipe;
1077 struct swr_context *ctx = swr_context(pipe);
1078
1079 if (pipe) {
1080 swr_fence_finish(p_screen, NULL, screen->flush_fence, 0);
1081 swr_resource_unused(resource);
1082 ctx->api.pfnSwrEndFrame(ctx->swrContext);
1083 }
1084
1085 /* Multisample resolved into resolve_target at flush with store_resource */
1086 if (pipe && spr->swr.numSamples > 1) {
1087 struct pipe_resource *resolve_target = spr->resolve_target;
1088
1089 /* Once resolved, copy into display target */
1090 SWR_SURFACE_STATE *resolve = &swr_resource(resolve_target)->swr;
1091
1092 void *map = winsys->displaytarget_map(winsys, spr->display_target,
1093 PIPE_TRANSFER_WRITE);
1094 memcpy(map, (void*)(resolve->xpBaseAddress), resolve->pitch * resolve->height);
1095 winsys->displaytarget_unmap(winsys, spr->display_target);
1096 }
1097
1098 debug_assert(spr->display_target);
1099 if (spr->display_target)
1100 winsys->displaytarget_display(
1101 winsys, spr->display_target, context_private, sub_box);
1102 }
1103
1104
1105 void
1106 swr_destroy_screen_internal(struct swr_screen **screen)
1107 {
1108 struct pipe_screen *p_screen = &(*screen)->base;
1109
1110 swr_fence_finish(p_screen, NULL, (*screen)->flush_fence, 0);
1111 swr_fence_reference(p_screen, &(*screen)->flush_fence, NULL);
1112
1113 JitDestroyContext((*screen)->hJitMgr);
1114
1115 if ((*screen)->pLibrary)
1116 util_dl_close((*screen)->pLibrary);
1117
1118 FREE(*screen);
1119 *screen = NULL;
1120 }
1121
1122
1123 static void
1124 swr_destroy_screen(struct pipe_screen *p_screen)
1125 {
1126 struct swr_screen *screen = swr_screen(p_screen);
1127 struct sw_winsys *winsys = screen->winsys;
1128
1129 swr_print_info("SWR destroy screen!\n");
1130
1131 if (winsys->destroy)
1132 winsys->destroy(winsys);
1133
1134 swr_destroy_screen_internal(&screen);
1135 }
1136
1137
1138 static void
1139 swr_validate_env_options(struct swr_screen *screen)
1140 {
1141 /* The client_copy_limit sets a maximum on the amount of user-buffer memory
1142 * copied to scratch space on a draw. Past this, the draw will access
1143 * user-buffer directly and then block. This is faster than queuing many
1144 * large client draws. */
1145 screen->client_copy_limit = SWR_CLIENT_COPY_LIMIT;
1146 int client_copy_limit =
1147 debug_get_num_option("SWR_CLIENT_COPY_LIMIT", SWR_CLIENT_COPY_LIMIT);
1148 if (client_copy_limit > 0)
1149 screen->client_copy_limit = client_copy_limit;
1150
1151 /* XXX msaa under development, disable by default for now */
1152 screen->msaa_max_count = 1; /* was SWR_MAX_NUM_MULTISAMPLES; */
1153
1154 /* validate env override values, within range and power of 2 */
1155 int msaa_max_count = debug_get_num_option("SWR_MSAA_MAX_COUNT", 1);
1156 if (msaa_max_count != 1) {
1157 if ((msaa_max_count < 1) || (msaa_max_count > SWR_MAX_NUM_MULTISAMPLES)
1158 || !util_is_power_of_two_or_zero(msaa_max_count)) {
1159 fprintf(stderr, "SWR_MSAA_MAX_COUNT invalid: %d\n", msaa_max_count);
1160 fprintf(stderr, "must be power of 2 between 1 and %d" \
1161 " (or 1 to disable msaa)\n",
1162 SWR_MAX_NUM_MULTISAMPLES);
1163 fprintf(stderr, "(msaa disabled)\n");
1164 msaa_max_count = 1;
1165 }
1166
1167 swr_print_info("SWR_MSAA_MAX_COUNT: %d\n", msaa_max_count);
1168
1169 screen->msaa_max_count = msaa_max_count;
1170 }
1171
1172 screen->msaa_force_enable = debug_get_bool_option(
1173 "SWR_MSAA_FORCE_ENABLE", false);
1174 if (screen->msaa_force_enable)
1175 swr_print_info("SWR_MSAA_FORCE_ENABLE: true\n");
1176 }
1177
1178
1179 struct pipe_screen *
1180 swr_create_screen_internal(struct sw_winsys *winsys)
1181 {
1182 struct swr_screen *screen = CALLOC_STRUCT(swr_screen);
1183
1184 if (!screen)
1185 return NULL;
1186
1187 if (!lp_build_init()) {
1188 FREE(screen);
1189 return NULL;
1190 }
1191
1192 screen->winsys = winsys;
1193 screen->base.get_name = swr_get_name;
1194 screen->base.get_vendor = swr_get_vendor;
1195 screen->base.is_format_supported = swr_is_format_supported;
1196 screen->base.context_create = swr_create_context;
1197 screen->base.can_create_resource = swr_can_create_resource;
1198
1199 screen->base.destroy = swr_destroy_screen;
1200 screen->base.get_param = swr_get_param;
1201 screen->base.get_shader_param = swr_get_shader_param;
1202 screen->base.get_paramf = swr_get_paramf;
1203
1204 screen->base.resource_create = swr_resource_create;
1205 screen->base.resource_destroy = swr_resource_destroy;
1206
1207 screen->base.flush_frontbuffer = swr_flush_frontbuffer;
1208
1209 // Pass in "" for architecture for run-time determination
1210 screen->hJitMgr = JitCreateContext(KNOB_SIMD_WIDTH, "", "swr");
1211
1212 swr_fence_init(&screen->base);
1213
1214 swr_validate_env_options(screen);
1215
1216 return &screen->base;
1217 }