src/gallium/drivers/swr/swr_screen.cpp

   1 /****************************************************************************
   2  * Copyright (C) 2015 Intel Corporation.   All Rights Reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  ***************************************************************************/
  23
  24 #include "pipe/p_screen.h"
  25 #include "pipe/p_defines.h"
  26 #include "util/u_memory.h"
  27 #include "util/u_format.h"
  28 #include "util/u_inlines.h"
  29 #include "util/u_cpu_detect.h"
  30 #include "util/u_format_s3tc.h"
  31
  32 #include "state_tracker/sw_winsys.h"
  33
  34 extern "C" {
  35 #include "gallivm/lp_bld_limits.h"
  36 }
  37
  38 #include "swr_public.h"
  39 #include "swr_screen.h"
  40 #include "swr_context.h"
  41 #include "swr_resource.h"
  42 #include "swr_fence.h"
  43 #include "gen_knobs.h"
  44
  45 #include "jit_api.h"
  46
  47 #include <stdio.h>
  48 #include <map>
  49
  50 /* MSVC case instensitive compare */
  51 #if defined(PIPE_CC_MSVC)
  52    #define strcasecmp lstrcmpiA
  53 #endif
  54
  55 /*
  56  * Max texture sizes
  57  * XXX Check max texture size values against core and sampler.
  58  */
  59 #define SWR_MAX_TEXTURE_SIZE (4 * 1024 * 1024 * 1024ULL) /* 4GB */
  60 #define SWR_MAX_TEXTURE_2D_LEVELS 14  /* 8K x 8K for now */
  61 #define SWR_MAX_TEXTURE_3D_LEVELS 12  /* 2K x 2K x 2K for now */
  62 #define SWR_MAX_TEXTURE_CUBE_LEVELS 14  /* 8K x 8K for now */
  63 #define SWR_MAX_TEXTURE_ARRAY_LAYERS 512 /* 8K x 512 / 8K x 8K x 512 */
  64
  65 static const char *
  66 swr_get_name(struct pipe_screen *screen)
  67 {
  68    return "SWR";
  69 }
  70
  71 static const char *
  72 swr_get_vendor(struct pipe_screen *screen)
  73 {
  74    return "Intel Corporation";
  75 }
  76
  77 static boolean
  78 swr_is_format_supported(struct pipe_screen *screen,
  79                         enum pipe_format format,
  80                         enum pipe_texture_target target,
  81                         unsigned sample_count,
  82                         unsigned bind)
  83 {
  84    struct sw_winsys *winsys = swr_screen(screen)->winsys;
  85    const struct util_format_description *format_desc;
  86
  87    assert(target == PIPE_BUFFER || target == PIPE_TEXTURE_1D
  88           || target == PIPE_TEXTURE_1D_ARRAY
  89           || target == PIPE_TEXTURE_2D
  90           || target == PIPE_TEXTURE_2D_ARRAY
  91           || target == PIPE_TEXTURE_RECT
  92           || target == PIPE_TEXTURE_3D
  93           || target == PIPE_TEXTURE_CUBE
  94           || target == PIPE_TEXTURE_CUBE_ARRAY);
  95
  96    format_desc = util_format_description(format);
  97    if (!format_desc)
  98       return FALSE;
  99
 100    if (sample_count > 1)
 101       return FALSE;
 102
 103    if (bind
 104        & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT | PIPE_BIND_SHARED)) {
 105       if (!winsys->is_displaytarget_format_supported(winsys, bind, format))
 106          return FALSE;
 107    }
 108
 109    if (bind & PIPE_BIND_RENDER_TARGET) {
 110       if (format_desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS)
 111          return FALSE;
 112
 113       if (mesa_to_swr_format(format) == (SWR_FORMAT)-1)
 114          return FALSE;
 115
 116       /*
 117        * Although possible, it is unnatural to render into compressed or YUV
 118        * surfaces. So disable these here to avoid going into weird paths
 119        * inside the state trackers.
 120        */
 121       if (format_desc->block.width != 1 || format_desc->block.height != 1)
 122          return FALSE;
 123    }
 124
 125    if (bind & PIPE_BIND_DEPTH_STENCIL) {
 126       if (format_desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
 127          return FALSE;
 128
 129       if (mesa_to_swr_format(format) == (SWR_FORMAT)-1)
 130          return FALSE;
 131    }
 132
 133    if (format_desc->layout == UTIL_FORMAT_LAYOUT_BPTC ||
 134        format_desc->layout == UTIL_FORMAT_LAYOUT_ASTC) {
 135       return FALSE;
 136    }
 137
 138    if (format_desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
 139        format != PIPE_FORMAT_ETC1_RGB8) {
 140       return FALSE;
 141    }
 142
 143    if (format_desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
 144       return util_format_s3tc_enabled;
 145    }
 146
 147    return TRUE;
 148 }
 149
 150 static int
 151 swr_get_param(struct pipe_screen *screen, enum pipe_cap param)
 152 {
 153    switch (param) {
 154    case PIPE_CAP_NPOT_TEXTURES:
 155    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 156    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 157       return 1;
 158    case PIPE_CAP_TWO_SIDED_STENCIL:
 159       return 1;
 160    case PIPE_CAP_SM3:
 161       return 1;
 162    case PIPE_CAP_ANISOTROPIC_FILTER:
 163       return 0;
 164    case PIPE_CAP_POINT_SPRITE:
 165       return 1;
 166    case PIPE_CAP_MAX_RENDER_TARGETS:
 167       return PIPE_MAX_COLOR_BUFS;
 168    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 169       return 1;
 170    case PIPE_CAP_OCCLUSION_QUERY:
 171    case PIPE_CAP_QUERY_TIME_ELAPSED:
 172    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 173       return 1;
 174    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 175       return 1;
 176    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 177       return 1;
 178    case PIPE_CAP_TEXTURE_SWIZZLE:
 179       return 1;
 180    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 181       return 0;
 182    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 183       return SWR_MAX_TEXTURE_2D_LEVELS;
 184    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 185       return SWR_MAX_TEXTURE_3D_LEVELS;
 186    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 187       return SWR_MAX_TEXTURE_CUBE_LEVELS;
 188    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 189       return 1;
 190    case PIPE_CAP_INDEP_BLEND_ENABLE:
 191       return 1;
 192    case PIPE_CAP_INDEP_BLEND_FUNC:
 193       return 1;
 194    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 195       return 0; // Don't support lower left frag coord.
 196    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 197    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 198    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 199       return 1;
 200    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 201       return 1;
 202    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 203       return MAX_SO_STREAMS;
 204    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 205    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 206       return MAX_ATTRIBUTES;
 207    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 208    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 209       return 1024;
 210    case PIPE_CAP_MAX_VERTEX_STREAMS:
 211       return 1;
 212    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 213       return 2048;
 214    case PIPE_CAP_PRIMITIVE_RESTART:
 215       return 1;
 216    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 217       return 1;
 218    case PIPE_CAP_TGSI_INSTANCEID:
 219    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 220    case PIPE_CAP_START_INSTANCE:
 221       return 1;
 222    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 223    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 224       return 1;
 225    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 226       return SWR_MAX_TEXTURE_ARRAY_LAYERS;
 227    case PIPE_CAP_MIN_TEXEL_OFFSET:
 228       return -8;
 229    case PIPE_CAP_MAX_TEXEL_OFFSET:
 230       return 7;
 231    case PIPE_CAP_CONDITIONAL_RENDER:
 232       return 1;
 233    case PIPE_CAP_TEXTURE_BARRIER:
 234       return 0;
 235    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 236    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED: /* draw module */
 237    case PIPE_CAP_VERTEX_COLOR_CLAMPED: /* draw module */
 238       return 1;
 239    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 240       return 1;
 241    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 242       return 330;
 243    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 244       return 1;
 245    case PIPE_CAP_COMPUTE:
 246       return 0;
 247    case PIPE_CAP_USER_VERTEX_BUFFERS:
 248    case PIPE_CAP_USER_INDEX_BUFFERS:
 249    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 250    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 251    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 252       return 1;
 253    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 254       return 16;
 255    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 256    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 257    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 258    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 259    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 260       return 0;
 261    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 262       return 64;
 263    case PIPE_CAP_QUERY_TIMESTAMP:
 264       return 1;
 265    case PIPE_CAP_CUBE_MAP_ARRAY:
 266       return 0;
 267    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 268       return 1;
 269    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 270       return 65536;
 271    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 272       return 0;
 273    case PIPE_CAP_TGSI_TEXCOORD:
 274    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 275       return 0;
 276    case PIPE_CAP_MAX_VIEWPORTS:
 277       return 1;
 278    case PIPE_CAP_ENDIANNESS:
 279       return PIPE_ENDIAN_NATIVE;
 280    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 281    case PIPE_CAP_TEXTURE_GATHER_SM5:
 282       return 0;
 283    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 284       return 1;
 285    case PIPE_CAP_TEXTURE_QUERY_LOD:
 286    case PIPE_CAP_SAMPLE_SHADING:
 287    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 288    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 289    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 290    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 291       return 0;
 292    case PIPE_CAP_FAKE_SW_MSAA:
 293       return 1;
 294    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 295    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 296       return 0;
 297    case PIPE_CAP_DRAW_INDIRECT:
 298       return 1;
 299
 300    case PIPE_CAP_VENDOR_ID:
 301       return 0xFFFFFFFF;
 302    case PIPE_CAP_DEVICE_ID:
 303       return 0xFFFFFFFF;
 304    case PIPE_CAP_ACCELERATED:
 305       return 0;
 306    case PIPE_CAP_VIDEO_MEMORY: {
 307       /* XXX: Do we want to return the full amount of system memory ? */
 308       uint64_t system_memory;
 309
 310       if (!os_get_total_physical_memory(&system_memory))
 311          return 0;
 312
 313       return (int)(system_memory >> 20);
 314    }
 315    case PIPE_CAP_UMA:
 316       return 1;
 317    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 318       return 1;
 319    case PIPE_CAP_CLIP_HALFZ:
 320       return 1;
 321    case PIPE_CAP_VERTEXID_NOBASE:
 322       return 0;
 323    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 324       return 1;
 325    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 326       return 0;
 327    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 328       return 0; // xxx
 329    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 330       return 0;
 331    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 332       return 0;
 333    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 334       return 0; // xxx
 335    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 336    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 337       return 1;
 338    case PIPE_CAP_CULL_DISTANCE:
 339       return 1;
 340    case PIPE_CAP_TGSI_TXQS:
 341    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 342    case PIPE_CAP_SHAREABLE_SHADERS:
 343    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 344    case PIPE_CAP_CLEAR_TEXTURE:
 345    case PIPE_CAP_DRAW_PARAMETERS:
 346    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 347    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 348    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 349    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 350    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 351    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 352    case PIPE_CAP_INVALIDATE_BUFFER:
 353    case PIPE_CAP_GENERATE_MIPMAP:
 354    case PIPE_CAP_STRING_MARKER:
 355    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 356    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 357    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 358    case PIPE_CAP_QUERY_MEMORY_INFO:
 359    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 360    case PIPE_CAP_PCI_GROUP:
 361    case PIPE_CAP_PCI_BUS:
 362    case PIPE_CAP_PCI_DEVICE:
 363    case PIPE_CAP_PCI_FUNCTION:
 364    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 365    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 366    case PIPE_CAP_TGSI_VOTE:
 367    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 368    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 369    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 370       return 0;
 371    }
 372
 373    /* should only get here on unhandled cases */
 374    debug_printf("Unexpected PIPE_CAP %d query\n", param);
 375    return 0;
 376 }
 377
 378 static int
 379 swr_get_shader_param(struct pipe_screen *screen,
 380                      unsigned shader,
 381                      enum pipe_shader_cap param)
 382 {
 383    if (shader == PIPE_SHADER_VERTEX || shader == PIPE_SHADER_FRAGMENT)
 384       return gallivm_get_shader_param(param);
 385
 386    // Todo: geometry, tesselation, compute
 387    return 0;
 388 }
 389
 390
 391 static float
 392 swr_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
 393 {
 394    switch (param) {
 395    case PIPE_CAPF_MAX_LINE_WIDTH:
 396    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 397    case PIPE_CAPF_MAX_POINT_WIDTH:
 398       return 255.0; /* arbitrary */
 399    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 400       return 0.0;
 401    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 402       return 0.0;
 403    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 404       return 0.0;
 405    case PIPE_CAPF_GUARD_BAND_LEFT:
 406    case PIPE_CAPF_GUARD_BAND_TOP:
 407    case PIPE_CAPF_GUARD_BAND_RIGHT:
 408    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 409       return 0.0;
 410    }
 411    /* should only get here on unhandled cases */
 412    debug_printf("Unexpected PIPE_CAPF %d query\n", param);
 413    return 0.0;
 414 }
 415
 416 SWR_FORMAT
 417 mesa_to_swr_format(enum pipe_format format)
 418 {
 419    static const std::map<pipe_format,SWR_FORMAT> mesa2swr = {
 420       {PIPE_FORMAT_NONE,                   (SWR_FORMAT)-1},
 421       {PIPE_FORMAT_B8G8R8A8_UNORM,         B8G8R8A8_UNORM},
 422       {PIPE_FORMAT_B8G8R8X8_UNORM,         B8G8R8X8_UNORM},
 423       {PIPE_FORMAT_A8R8G8B8_UNORM,         (SWR_FORMAT)-1},
 424       {PIPE_FORMAT_X8R8G8B8_UNORM,         (SWR_FORMAT)-1},
 425       {PIPE_FORMAT_B5G5R5A1_UNORM,         B5G5R5A1_UNORM},
 426       {PIPE_FORMAT_B4G4R4A4_UNORM,         B4G4R4A4_UNORM},
 427       {PIPE_FORMAT_B5G6R5_UNORM,           B5G6R5_UNORM},
 428       {PIPE_FORMAT_R10G10B10A2_UNORM,      R10G10B10A2_UNORM},
 429       {PIPE_FORMAT_L8_UNORM,               L8_UNORM},
 430       {PIPE_FORMAT_A8_UNORM,               A8_UNORM},
 431       {PIPE_FORMAT_I8_UNORM,               I8_UNORM},
 432       {PIPE_FORMAT_L8A8_UNORM,             L8A8_UNORM},
 433       {PIPE_FORMAT_L16_UNORM,              L16_UNORM},
 434       {PIPE_FORMAT_UYVY,                   YCRCB_SWAPUVY},
 435       {PIPE_FORMAT_YUYV,                   (SWR_FORMAT)-1},
 436       {PIPE_FORMAT_Z16_UNORM,              R16_UNORM}, // z
 437       {PIPE_FORMAT_Z32_UNORM,              (SWR_FORMAT)-1},
 438       {PIPE_FORMAT_Z32_FLOAT,              R32_FLOAT}, // z
 439       {PIPE_FORMAT_Z24_UNORM_S8_UINT,      R24_UNORM_X8_TYPELESS}, // z
 440       {PIPE_FORMAT_S8_UINT_Z24_UNORM,      (SWR_FORMAT)-1},
 441       {PIPE_FORMAT_Z24X8_UNORM,            R24_UNORM_X8_TYPELESS}, // z
 442       {PIPE_FORMAT_X8Z24_UNORM,            (SWR_FORMAT)-1},
 443       {PIPE_FORMAT_S8_UINT,                (SWR_FORMAT)-1},
 444       {PIPE_FORMAT_R64_FLOAT,              (SWR_FORMAT)-1},
 445       {PIPE_FORMAT_R64G64_FLOAT,           (SWR_FORMAT)-1},
 446       {PIPE_FORMAT_R64G64B64_FLOAT,        (SWR_FORMAT)-1},
 447       {PIPE_FORMAT_R64G64B64A64_FLOAT,     (SWR_FORMAT)-1},
 448       {PIPE_FORMAT_R32_FLOAT,              R32_FLOAT},
 449       {PIPE_FORMAT_R32G32_FLOAT,           R32G32_FLOAT},
 450       {PIPE_FORMAT_R32G32B32_FLOAT,        R32G32B32_FLOAT},
 451       {PIPE_FORMAT_R32G32B32A32_FLOAT,     R32G32B32A32_FLOAT},
 452       {PIPE_FORMAT_R32_UNORM,              (SWR_FORMAT)-1},
 453       {PIPE_FORMAT_R32G32_UNORM,           (SWR_FORMAT)-1},
 454       {PIPE_FORMAT_R32G32B32_UNORM,        (SWR_FORMAT)-1},
 455       {PIPE_FORMAT_R32G32B32A32_UNORM,     (SWR_FORMAT)-1},
 456       {PIPE_FORMAT_R32_USCALED,            R32_USCALED},
 457       {PIPE_FORMAT_R32G32_USCALED,         R32G32_USCALED},
 458       {PIPE_FORMAT_R32G32B32_USCALED,      R32G32B32_USCALED},
 459       {PIPE_FORMAT_R32G32B32A32_USCALED,   R32G32B32A32_USCALED},
 460       {PIPE_FORMAT_R32_SNORM,              (SWR_FORMAT)-1},
 461       {PIPE_FORMAT_R32G32_SNORM,           (SWR_FORMAT)-1},
 462       {PIPE_FORMAT_R32G32B32_SNORM,        (SWR_FORMAT)-1},
 463       {PIPE_FORMAT_R32G32B32A32_SNORM,     (SWR_FORMAT)-1},
 464       {PIPE_FORMAT_R32_SSCALED,            R32_SSCALED},
 465       {PIPE_FORMAT_R32G32_SSCALED,         R32G32_SSCALED},
 466       {PIPE_FORMAT_R32G32B32_SSCALED,      R32G32B32_SSCALED},
 467       {PIPE_FORMAT_R32G32B32A32_SSCALED,   R32G32B32A32_SSCALED},
 468       {PIPE_FORMAT_R16_UNORM,              R16_UNORM},
 469       {PIPE_FORMAT_R16G16_UNORM,           R16G16_UNORM},
 470       {PIPE_FORMAT_R16G16B16_UNORM,        R16G16B16_UNORM},
 471       {PIPE_FORMAT_R16G16B16A16_UNORM,     R16G16B16A16_UNORM},
 472       {PIPE_FORMAT_R16_USCALED,            R16_USCALED},
 473       {PIPE_FORMAT_R16G16_USCALED,         R16G16_USCALED},
 474       {PIPE_FORMAT_R16G16B16_USCALED,      R16G16B16_USCALED},
 475       {PIPE_FORMAT_R16G16B16A16_USCALED,   R16G16B16A16_USCALED},
 476       {PIPE_FORMAT_R16_SNORM,              R16_SNORM},
 477       {PIPE_FORMAT_R16G16_SNORM,           R16G16_SNORM},
 478       {PIPE_FORMAT_R16G16B16_SNORM,        R16G16B16_SNORM},
 479       {PIPE_FORMAT_R16G16B16A16_SNORM,     R16G16B16A16_SNORM},
 480       {PIPE_FORMAT_R16_SSCALED,            R16_SSCALED},
 481       {PIPE_FORMAT_R16G16_SSCALED,         R16G16_SSCALED},
 482       {PIPE_FORMAT_R16G16B16_SSCALED,      R16G16B16_SSCALED},
 483       {PIPE_FORMAT_R16G16B16A16_SSCALED,   R16G16B16A16_SSCALED},
 484       {PIPE_FORMAT_R8_UNORM,               R8_UNORM},
 485       {PIPE_FORMAT_R8G8_UNORM,             R8G8_UNORM},
 486       {PIPE_FORMAT_R8G8B8_UNORM,           R8G8B8_UNORM},
 487       {PIPE_FORMAT_R8G8B8A8_UNORM,         R8G8B8A8_UNORM},
 488       {PIPE_FORMAT_X8B8G8R8_UNORM,         (SWR_FORMAT)-1},
 489       {PIPE_FORMAT_R8_USCALED,             R8_USCALED},
 490       {PIPE_FORMAT_R8G8_USCALED,           R8G8_USCALED},
 491       {PIPE_FORMAT_R8G8B8_USCALED,         R8G8B8_USCALED},
 492       {PIPE_FORMAT_R8G8B8A8_USCALED,       R8G8B8A8_USCALED},
 493       {PIPE_FORMAT_R8_SNORM,               R8_SNORM},
 494       {PIPE_FORMAT_R8G8_SNORM,             R8G8_SNORM},
 495       {PIPE_FORMAT_R8G8B8_SNORM,           R8G8B8_SNORM},
 496       {PIPE_FORMAT_R8G8B8A8_SNORM,         R8G8B8A8_SNORM},
 497       {PIPE_FORMAT_R8_SSCALED,             R8_SSCALED},
 498       {PIPE_FORMAT_R8G8_SSCALED,           R8G8_SSCALED},
 499       {PIPE_FORMAT_R8G8B8_SSCALED,         R8G8B8_SSCALED},
 500       {PIPE_FORMAT_R8G8B8A8_SSCALED,       R8G8B8A8_SSCALED},
 501       {PIPE_FORMAT_R32_FIXED,              (SWR_FORMAT)-1},
 502       {PIPE_FORMAT_R32G32_FIXED,           (SWR_FORMAT)-1},
 503       {PIPE_FORMAT_R32G32B32_FIXED,        (SWR_FORMAT)-1},
 504       {PIPE_FORMAT_R32G32B32A32_FIXED,     (SWR_FORMAT)-1},
 505       {PIPE_FORMAT_R16_FLOAT,              R16_FLOAT},
 506       {PIPE_FORMAT_R16G16_FLOAT,           R16G16_FLOAT},
 507       {PIPE_FORMAT_R16G16B16_FLOAT,        R16G16B16_FLOAT},
 508       {PIPE_FORMAT_R16G16B16A16_FLOAT,     R16G16B16A16_FLOAT},
 509
 510       {PIPE_FORMAT_L8_SRGB,                L8_UNORM_SRGB},
 511       {PIPE_FORMAT_L8A8_SRGB,              L8A8_UNORM_SRGB},
 512       {PIPE_FORMAT_R8G8B8_SRGB,            R8G8B8_UNORM_SRGB},
 513       {PIPE_FORMAT_A8B8G8R8_SRGB,          (SWR_FORMAT)-1},
 514       {PIPE_FORMAT_X8B8G8R8_SRGB,          (SWR_FORMAT)-1},
 515       {PIPE_FORMAT_B8G8R8A8_SRGB,          B8G8R8A8_UNORM_SRGB},
 516       {PIPE_FORMAT_B8G8R8X8_SRGB,          B8G8R8X8_UNORM_SRGB},
 517       {PIPE_FORMAT_A8R8G8B8_SRGB,          (SWR_FORMAT)-1},
 518       {PIPE_FORMAT_X8R8G8B8_SRGB,          (SWR_FORMAT)-1},
 519       {PIPE_FORMAT_R8G8B8A8_SRGB,          R8G8B8A8_UNORM_SRGB},
 520
 521       {PIPE_FORMAT_DXT1_RGB,               (SWR_FORMAT)-1},
 522       {PIPE_FORMAT_DXT1_RGBA,              BC1_UNORM},
 523       {PIPE_FORMAT_DXT3_RGBA,              BC2_UNORM},
 524       {PIPE_FORMAT_DXT5_RGBA,              BC3_UNORM},
 525
 526       {PIPE_FORMAT_DXT1_SRGB,              (SWR_FORMAT)-1},
 527       {PIPE_FORMAT_DXT1_SRGBA,             BC1_UNORM_SRGB},
 528       {PIPE_FORMAT_DXT3_SRGBA,             BC2_UNORM_SRGB},
 529       {PIPE_FORMAT_DXT5_SRGBA,             BC3_UNORM_SRGB},
 530
 531       {PIPE_FORMAT_RGTC1_UNORM,            BC4_UNORM},
 532       {PIPE_FORMAT_RGTC1_SNORM,            BC4_SNORM},
 533       {PIPE_FORMAT_RGTC2_UNORM,            BC5_UNORM},
 534       {PIPE_FORMAT_RGTC2_SNORM,            BC5_SNORM},
 535
 536       {PIPE_FORMAT_R8G8_B8G8_UNORM,        (SWR_FORMAT)-1},
 537       {PIPE_FORMAT_G8R8_G8B8_UNORM,        (SWR_FORMAT)-1},
 538
 539       {PIPE_FORMAT_R8SG8SB8UX8U_NORM,      (SWR_FORMAT)-1},
 540       {PIPE_FORMAT_R5SG5SB6U_NORM,         (SWR_FORMAT)-1},
 541
 542       {PIPE_FORMAT_A8B8G8R8_UNORM,         (SWR_FORMAT)-1},
 543       {PIPE_FORMAT_B5G5R5X1_UNORM,         B5G5R5X1_UNORM},
 544       {PIPE_FORMAT_R10G10B10A2_USCALED,    R10G10B10A2_USCALED},
 545       {PIPE_FORMAT_R11G11B10_FLOAT,        R11G11B10_FLOAT},
 546       {PIPE_FORMAT_R9G9B9E5_FLOAT,         R9G9B9E5_SHAREDEXP},
 547       {PIPE_FORMAT_Z32_FLOAT_S8X24_UINT,   R32_FLOAT_X8X24_TYPELESS}, // z
 548       {PIPE_FORMAT_R1_UNORM,               (SWR_FORMAT)-1},
 549       {PIPE_FORMAT_R10G10B10X2_USCALED,    R10G10B10X2_USCALED},
 550       {PIPE_FORMAT_R10G10B10X2_SNORM,      (SWR_FORMAT)-1},
 551       {PIPE_FORMAT_L4A4_UNORM,             (SWR_FORMAT)-1},
 552       {PIPE_FORMAT_B10G10R10A2_UNORM,      B10G10R10A2_UNORM},
 553       {PIPE_FORMAT_R10SG10SB10SA2U_NORM,   (SWR_FORMAT)-1},
 554       {PIPE_FORMAT_R8G8Bx_SNORM,           (SWR_FORMAT)-1},
 555       {PIPE_FORMAT_R8G8B8X8_UNORM,         R8G8B8X8_UNORM},
 556       {PIPE_FORMAT_B4G4R4X4_UNORM,         (SWR_FORMAT)-1},
 557
 558       {PIPE_FORMAT_X24S8_UINT,             (SWR_FORMAT)-1},
 559       {PIPE_FORMAT_S8X24_UINT,             (SWR_FORMAT)-1},
 560       {PIPE_FORMAT_X32_S8X24_UINT,         (SWR_FORMAT)-1},
 561
 562       {PIPE_FORMAT_B2G3R3_UNORM,           (SWR_FORMAT)-1},
 563       {PIPE_FORMAT_L16A16_UNORM,           L16A16_UNORM},
 564       {PIPE_FORMAT_A16_UNORM,              A16_UNORM},
 565       {PIPE_FORMAT_I16_UNORM,              I16_UNORM},
 566
 567       {PIPE_FORMAT_LATC1_UNORM,            (SWR_FORMAT)-1},
 568       {PIPE_FORMAT_LATC1_SNORM,            (SWR_FORMAT)-1},
 569       {PIPE_FORMAT_LATC2_UNORM,            (SWR_FORMAT)-1},
 570       {PIPE_FORMAT_LATC2_SNORM,            (SWR_FORMAT)-1},
 571
 572       {PIPE_FORMAT_A8_SNORM,               (SWR_FORMAT)-1},
 573       {PIPE_FORMAT_L8_SNORM,               (SWR_FORMAT)-1},
 574       {PIPE_FORMAT_L8A8_SNORM,             (SWR_FORMAT)-1},
 575       {PIPE_FORMAT_I8_SNORM,               (SWR_FORMAT)-1},
 576       {PIPE_FORMAT_A16_SNORM,              (SWR_FORMAT)-1},
 577       {PIPE_FORMAT_L16_SNORM,              (SWR_FORMAT)-1},
 578       {PIPE_FORMAT_L16A16_SNORM,           (SWR_FORMAT)-1},
 579       {PIPE_FORMAT_I16_SNORM,              (SWR_FORMAT)-1},
 580
 581       {PIPE_FORMAT_A16_FLOAT,              A16_FLOAT},
 582       {PIPE_FORMAT_L16_FLOAT,              L16_FLOAT},
 583       {PIPE_FORMAT_L16A16_FLOAT,           L16A16_FLOAT},
 584       {PIPE_FORMAT_I16_FLOAT,              I16_FLOAT},
 585       {PIPE_FORMAT_A32_FLOAT,              A32_FLOAT},
 586       {PIPE_FORMAT_L32_FLOAT,              L32_FLOAT},
 587       {PIPE_FORMAT_L32A32_FLOAT,           L32A32_FLOAT},
 588       {PIPE_FORMAT_I32_FLOAT,              I32_FLOAT},
 589
 590       {PIPE_FORMAT_YV12,                   (SWR_FORMAT)-1},
 591       {PIPE_FORMAT_YV16,                   (SWR_FORMAT)-1},
 592       {PIPE_FORMAT_IYUV,                   (SWR_FORMAT)-1},
 593       {PIPE_FORMAT_NV12,                   (SWR_FORMAT)-1},
 594       {PIPE_FORMAT_NV21,                   (SWR_FORMAT)-1},
 595
 596       {PIPE_FORMAT_A4R4_UNORM,             (SWR_FORMAT)-1},
 597       {PIPE_FORMAT_R4A4_UNORM,             (SWR_FORMAT)-1},
 598       {PIPE_FORMAT_R8A8_UNORM,             (SWR_FORMAT)-1},
 599       {PIPE_FORMAT_A8R8_UNORM,             (SWR_FORMAT)-1},
 600
 601       {PIPE_FORMAT_R10G10B10A2_SSCALED,    R10G10B10A2_SSCALED},
 602       {PIPE_FORMAT_R10G10B10A2_SNORM,      R10G10B10A2_SNORM},
 603
 604       {PIPE_FORMAT_B10G10R10A2_USCALED,    B10G10R10A2_USCALED},
 605       {PIPE_FORMAT_B10G10R10A2_SSCALED,    B10G10R10A2_SSCALED},
 606       {PIPE_FORMAT_B10G10R10A2_SNORM,      B10G10R10A2_SNORM},
 607
 608       {PIPE_FORMAT_R8_UINT,                R8_UINT},
 609       {PIPE_FORMAT_R8G8_UINT,              R8G8_UINT},
 610       {PIPE_FORMAT_R8G8B8_UINT,            R8G8B8_UINT},
 611       {PIPE_FORMAT_R8G8B8A8_UINT,          R8G8B8A8_UINT},
 612
 613       {PIPE_FORMAT_R8_SINT,                R8_SINT},
 614       {PIPE_FORMAT_R8G8_SINT,              R8G8_SINT},
 615       {PIPE_FORMAT_R8G8B8_SINT,            R8G8B8_SINT},
 616       {PIPE_FORMAT_R8G8B8A8_SINT,          R8G8B8A8_SINT},
 617
 618       {PIPE_FORMAT_R16_UINT,               R16_UINT},
 619       {PIPE_FORMAT_R16G16_UINT,            R16G16_UINT},
 620       {PIPE_FORMAT_R16G16B16_UINT,         R16G16B16_UINT},
 621       {PIPE_FORMAT_R16G16B16A16_UINT,      R16G16B16A16_UINT},
 622
 623       {PIPE_FORMAT_R16_SINT,               R16_SINT},
 624       {PIPE_FORMAT_R16G16_SINT,            R16G16_SINT},
 625       {PIPE_FORMAT_R16G16B16_SINT,         R16G16B16_SINT},
 626       {PIPE_FORMAT_R16G16B16A16_SINT,      R16G16B16A16_SINT},
 627
 628       {PIPE_FORMAT_R32_UINT,               R32_UINT},
 629       {PIPE_FORMAT_R32G32_UINT,            R32G32_UINT},
 630       {PIPE_FORMAT_R32G32B32_UINT,         R32G32B32_UINT},
 631       {PIPE_FORMAT_R32G32B32A32_UINT,      R32G32B32A32_UINT},
 632
 633       {PIPE_FORMAT_R32_SINT,               R32_SINT},
 634       {PIPE_FORMAT_R32G32_SINT,            R32G32_SINT},
 635       {PIPE_FORMAT_R32G32B32_SINT,         R32G32B32_SINT},
 636       {PIPE_FORMAT_R32G32B32A32_SINT,      R32G32B32A32_SINT},
 637
 638       {PIPE_FORMAT_A8_UINT,                (SWR_FORMAT)-1},
 639       {PIPE_FORMAT_I8_UINT,                I8_UINT},
 640       {PIPE_FORMAT_L8_UINT,                L8_UINT},
 641       {PIPE_FORMAT_L8A8_UINT,              L8A8_UINT},
 642
 643       {PIPE_FORMAT_A8_SINT,                (SWR_FORMAT)-1},
 644       {PIPE_FORMAT_I8_SINT,                I8_SINT},
 645       {PIPE_FORMAT_L8_SINT,                L8_SINT},
 646       {PIPE_FORMAT_L8A8_SINT,              L8A8_SINT},
 647
 648       {PIPE_FORMAT_A16_UINT,               (SWR_FORMAT)-1},
 649       {PIPE_FORMAT_I16_UINT,               (SWR_FORMAT)-1},
 650       {PIPE_FORMAT_L16_UINT,               (SWR_FORMAT)-1},
 651       {PIPE_FORMAT_L16A16_UINT,            (SWR_FORMAT)-1},
 652
 653       {PIPE_FORMAT_A16_SINT,               (SWR_FORMAT)-1},
 654       {PIPE_FORMAT_I16_SINT,               (SWR_FORMAT)-1},
 655       {PIPE_FORMAT_L16_SINT,               (SWR_FORMAT)-1},
 656       {PIPE_FORMAT_L16A16_SINT,            (SWR_FORMAT)-1},
 657
 658       {PIPE_FORMAT_A32_UINT,               (SWR_FORMAT)-1},
 659       {PIPE_FORMAT_I32_UINT,               (SWR_FORMAT)-1},
 660       {PIPE_FORMAT_L32_UINT,               (SWR_FORMAT)-1},
 661       {PIPE_FORMAT_L32A32_UINT,            (SWR_FORMAT)-1},
 662
 663       {PIPE_FORMAT_A32_SINT,               (SWR_FORMAT)-1},
 664       {PIPE_FORMAT_I32_SINT,               (SWR_FORMAT)-1},
 665       {PIPE_FORMAT_L32_SINT,               (SWR_FORMAT)-1},
 666       {PIPE_FORMAT_L32A32_SINT,            (SWR_FORMAT)-1},
 667
 668       {PIPE_FORMAT_B10G10R10A2_UINT,       B10G10R10A2_UINT},
 669
 670       {PIPE_FORMAT_ETC1_RGB8,              (SWR_FORMAT)-1},
 671
 672       {PIPE_FORMAT_R8G8_R8B8_UNORM,        (SWR_FORMAT)-1},
 673       {PIPE_FORMAT_G8R8_B8R8_UNORM,        (SWR_FORMAT)-1},
 674
 675       {PIPE_FORMAT_R8G8B8X8_SNORM,         (SWR_FORMAT)-1},
 676       {PIPE_FORMAT_R8G8B8X8_SRGB,          (SWR_FORMAT)-1},
 677       {PIPE_FORMAT_R8G8B8X8_UINT,          (SWR_FORMAT)-1},
 678       {PIPE_FORMAT_R8G8B8X8_SINT,          (SWR_FORMAT)-1},
 679       {PIPE_FORMAT_B10G10R10X2_UNORM,      B10G10R10X2_UNORM},
 680       {PIPE_FORMAT_R16G16B16X16_UNORM,     R16G16B16X16_UNORM},
 681       {PIPE_FORMAT_R16G16B16X16_SNORM,     (SWR_FORMAT)-1},
 682       {PIPE_FORMAT_R16G16B16X16_FLOAT,     R16G16B16X16_FLOAT},
 683       {PIPE_FORMAT_R16G16B16X16_UINT,      (SWR_FORMAT)-1},
 684       {PIPE_FORMAT_R16G16B16X16_SINT,      (SWR_FORMAT)-1},
 685       {PIPE_FORMAT_R32G32B32X32_FLOAT,     R32G32B32X32_FLOAT},
 686       {PIPE_FORMAT_R32G32B32X32_UINT,      (SWR_FORMAT)-1},
 687       {PIPE_FORMAT_R32G32B32X32_SINT,      (SWR_FORMAT)-1},
 688
 689       {PIPE_FORMAT_R8A8_SNORM,             (SWR_FORMAT)-1},
 690       {PIPE_FORMAT_R16A16_UNORM,           (SWR_FORMAT)-1},
 691       {PIPE_FORMAT_R16A16_SNORM,           (SWR_FORMAT)-1},
 692       {PIPE_FORMAT_R16A16_FLOAT,           (SWR_FORMAT)-1},
 693       {PIPE_FORMAT_R32A32_FLOAT,           (SWR_FORMAT)-1},
 694       {PIPE_FORMAT_R8A8_UINT,              (SWR_FORMAT)-1},
 695       {PIPE_FORMAT_R8A8_SINT,              (SWR_FORMAT)-1},
 696       {PIPE_FORMAT_R16A16_UINT,            (SWR_FORMAT)-1},
 697       {PIPE_FORMAT_R16A16_SINT,            (SWR_FORMAT)-1},
 698       {PIPE_FORMAT_R32A32_UINT,            (SWR_FORMAT)-1},
 699       {PIPE_FORMAT_R32A32_SINT,            (SWR_FORMAT)-1},
 700       {PIPE_FORMAT_R10G10B10A2_UINT,       R10G10B10A2_UINT},
 701
 702       {PIPE_FORMAT_B5G6R5_SRGB,            B5G6R5_UNORM_SRGB}
 703    };
 704
 705    try {
 706       return mesa2swr.at(format);
 707    }
 708    catch (std::out_of_range) {
 709       debug_printf("asked to convert unsupported format %s\n",
 710                    util_format_name(format));
 711
 712       return (SWR_FORMAT)-1;
 713    }
 714 }
 715
 716 static boolean
 717 swr_displaytarget_layout(struct swr_screen *screen, struct swr_resource *res)
 718 {
 719    struct sw_winsys *winsys = screen->winsys;
 720    struct sw_displaytarget *dt;
 721
 722    UINT stride;
 723    dt = winsys->displaytarget_create(winsys,
 724                                      res->base.bind,
 725                                      res->base.format,
 726                                      res->alignedWidth,
 727                                      res->alignedHeight,
 728                                      64, NULL,
 729                                      &stride);
 730
 731    if (dt == NULL)
 732       return FALSE;
 733
 734    void *map = winsys->displaytarget_map(winsys, dt, 0);
 735
 736    res->display_target = dt;
 737    res->swr.pBaseAddress = (uint8_t*) map;
 738
 739    /* Clear the display target surface */
 740    if (map)
 741       memset(map, 0, res->alignedHeight * stride);
 742
 743    winsys->displaytarget_unmap(winsys, dt);
 744
 745    return TRUE;
 746 }
 747
 748 static boolean
 749 swr_texture_layout(struct swr_screen *screen,
 750                    struct swr_resource *res,
 751                    boolean allocate)
 752 {
 753    struct pipe_resource *pt = &res->base;
 754
 755    pipe_format fmt = pt->format;
 756    const struct util_format_description *desc = util_format_description(fmt);
 757
 758    res->has_depth = util_format_has_depth(desc);
 759    res->has_stencil = util_format_has_stencil(desc);
 760
 761    if (res->has_stencil && !res->has_depth)
 762       fmt = PIPE_FORMAT_R8_UINT;
 763
 764    res->swr.width = pt->width0;
 765    res->swr.height = pt->height0;
 766    res->swr.depth = pt->depth0;
 767    res->swr.type = swr_convert_target_type(pt->target);
 768    res->swr.tileMode = SWR_TILE_NONE;
 769    res->swr.format = mesa_to_swr_format(fmt);
 770    res->swr.numSamples = (1 << pt->nr_samples);
 771
 772    SWR_FORMAT_INFO finfo = GetFormatInfo(res->swr.format);
 773
 774    size_t total_size = 0;
 775    unsigned width = pt->width0;
 776    unsigned height = pt->height0;
 777    unsigned depth = pt->depth0;
 778    unsigned layers = pt->array_size;
 779
 780    for (int level = 0; level <= pt->last_level; level++) {
 781       unsigned alignedWidth, alignedHeight;
 782       unsigned num_slices;
 783
 784       if (pt->bind & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DEPTH_STENCIL)) {
 785          alignedWidth = align(width, KNOB_MACROTILE_X_DIM);
 786          alignedHeight = align(height, KNOB_MACROTILE_Y_DIM);
 787       } else {
 788          alignedWidth = width;
 789          alignedHeight = height;
 790       }
 791
 792       if (level == 0) {
 793          res->alignedWidth = alignedWidth;
 794          res->alignedHeight = alignedHeight;
 795       }
 796
 797       res->row_stride[level] = alignedWidth * finfo.Bpp;
 798       res->img_stride[level] = res->row_stride[level] * alignedHeight;
 799       res->mip_offsets[level] = total_size;
 800
 801       if (pt->target == PIPE_TEXTURE_3D)
 802          num_slices = depth;
 803       else if (pt->target == PIPE_TEXTURE_1D_ARRAY
 804                || pt->target == PIPE_TEXTURE_2D_ARRAY
 805                || pt->target == PIPE_TEXTURE_CUBE
 806                || pt->target == PIPE_TEXTURE_CUBE_ARRAY)
 807          num_slices = layers;
 808       else
 809          num_slices = 1;
 810
 811       total_size += res->img_stride[level] * num_slices;
 812       if (total_size > SWR_MAX_TEXTURE_SIZE)
 813          return FALSE;
 814
 815       width = u_minify(width, 1);
 816       height = u_minify(height, 1);
 817       depth = u_minify(depth, 1);
 818    }
 819
 820    res->swr.halign = res->alignedWidth;
 821    res->swr.valign = res->alignedHeight;
 822    res->swr.pitch = res->row_stride[0];
 823
 824    if (allocate) {
 825       res->swr.pBaseAddress = (uint8_t *)AlignedMalloc(total_size, 64);
 826
 827       if (res->has_depth && res->has_stencil) {
 828          SWR_FORMAT_INFO finfo = GetFormatInfo(res->secondary.format);
 829          res->secondary.width = pt->width0;
 830          res->secondary.height = pt->height0;
 831          res->secondary.depth = pt->depth0;
 832          res->secondary.type = SURFACE_2D;
 833          res->secondary.tileMode = SWR_TILE_NONE;
 834          res->secondary.format = R8_UINT;
 835          res->secondary.numSamples = (1 << pt->nr_samples);
 836          res->secondary.pitch = res->alignedWidth * finfo.Bpp;
 837
 838          res->secondary.pBaseAddress = (uint8_t *)AlignedMalloc(
 839             res->alignedHeight * res->secondary.pitch, 64);
 840       }
 841    }
 842
 843    return TRUE;
 844 }
 845
 846 static boolean
 847 swr_can_create_resource(struct pipe_screen *screen,
 848                         const struct pipe_resource *templat)
 849 {
 850    struct swr_resource res;
 851    memset(&res, 0, sizeof(res));
 852    res.base = *templat;
 853    return swr_texture_layout(swr_screen(screen), &res, false);
 854 }
 855
 856 static struct pipe_resource *
 857 swr_resource_create(struct pipe_screen *_screen,
 858                     const struct pipe_resource *templat)
 859 {
 860    struct swr_screen *screen = swr_screen(_screen);
 861    struct swr_resource *res = CALLOC_STRUCT(swr_resource);
 862    if (!res)
 863       return NULL;
 864
 865    res->base = *templat;
 866    pipe_reference_init(&res->base.reference, 1);
 867    res->base.screen = &screen->base;
 868
 869    if (swr_resource_is_texture(&res->base)) {
 870       if (res->base.bind & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT
 871                             | PIPE_BIND_SHARED)) {
 872          /* displayable surface
 873           * first call swr_texture_layout without allocating to finish
 874           * filling out the SWR_SURFAE_STATE in res */
 875          swr_texture_layout(screen, res, false);
 876          if (!swr_displaytarget_layout(screen, res))
 877             goto fail;
 878       } else {
 879          /* texture map */
 880          if (!swr_texture_layout(screen, res, true))
 881             goto fail;
 882       }
 883    } else {
 884       /* other data (vertex buffer, const buffer, etc) */
 885       assert(util_format_get_blocksize(templat->format) == 1);
 886       assert(templat->height0 == 1);
 887       assert(templat->depth0 == 1);
 888       assert(templat->last_level == 0);
 889
 890       /* Easiest to just call swr_texture_layout, as it sets up
 891        * SWR_SURFAE_STATE in res */
 892       if (!swr_texture_layout(screen, res, true))
 893          goto fail;
 894    }
 895
 896    return &res->base;
 897
 898 fail:
 899    FREE(res);
 900    return NULL;
 901 }
 902
 903 static void
 904 swr_resource_destroy(struct pipe_screen *p_screen, struct pipe_resource *pt)
 905 {
 906    struct swr_screen *screen = swr_screen(p_screen);
 907    struct swr_resource *spr = swr_resource(pt);
 908    struct pipe_context *pipe = screen->pipe;
 909
 910    /* Only wait on fence if the resource is being used */
 911    if (pipe && spr->status) {
 912       /* But, if there's no fence pending, submit one.
 913        * XXX: Remove once draw timestamps are implmented. */
 914       if (!swr_is_fence_pending(screen->flush_fence))
 915          swr_fence_submit(swr_context(pipe), screen->flush_fence);
 916
 917       swr_fence_finish(p_screen, NULL, screen->flush_fence, 0);
 918       swr_resource_unused(pt);
 919    }
 920
 921    /*
 922     * Free resource primary surface.  If resource is display target, winsys
 923     * manages the buffer and will free it on displaytarget_destroy.
 924     */
 925    if (spr->display_target) {
 926       /* display target */
 927       struct sw_winsys *winsys = screen->winsys;
 928       winsys->displaytarget_destroy(winsys, spr->display_target);
 929    } else
 930       AlignedFree(spr->swr.pBaseAddress);
 931
 932    AlignedFree(spr->secondary.pBaseAddress);
 933
 934    FREE(spr);
 935 }
 936
 937
 938 static void
 939 swr_flush_frontbuffer(struct pipe_screen *p_screen,
 940                       struct pipe_resource *resource,
 941                       unsigned level,
 942                       unsigned layer,
 943                       void *context_private,
 944                       struct pipe_box *sub_box)
 945 {
 946    struct swr_screen *screen = swr_screen(p_screen);
 947    struct sw_winsys *winsys = screen->winsys;
 948    struct swr_resource *spr = swr_resource(resource);
 949    struct pipe_context *pipe = screen->pipe;
 950
 951    if (pipe) {
 952       swr_fence_finish(p_screen, NULL, screen->flush_fence, 0);
 953       swr_resource_unused(resource);
 954       SwrEndFrame(swr_context(pipe)->swrContext);
 955    }
 956
 957    debug_assert(spr->display_target);
 958    if (spr->display_target)
 959       winsys->displaytarget_display(
 960          winsys, spr->display_target, context_private, sub_box);
 961 }
 962
 963
 964 static void
 965 swr_destroy_screen(struct pipe_screen *p_screen)
 966 {
 967    struct swr_screen *screen = swr_screen(p_screen);
 968    struct sw_winsys *winsys = screen->winsys;
 969
 970    fprintf(stderr, "SWR destroy screen!\n");
 971
 972    swr_fence_finish(p_screen, NULL, screen->flush_fence, 0);
 973    swr_fence_reference(p_screen, &screen->flush_fence, NULL);
 974
 975    JitDestroyContext(screen->hJitMgr);
 976
 977    if (winsys->destroy)
 978       winsys->destroy(winsys);
 979
 980    FREE(screen);
 981 }
 982
 983 PUBLIC
 984 struct pipe_screen *
 985 swr_create_screen(struct sw_winsys *winsys)
 986 {
 987    struct swr_screen *screen = CALLOC_STRUCT(swr_screen);
 988
 989    if (!screen)
 990       return NULL;
 991
 992    if (!getenv("KNOB_MAX_PRIMS_PER_DRAW")) {
 993       g_GlobalKnobs.MAX_PRIMS_PER_DRAW.Value(49152);
 994    }
 995
 996    screen->winsys = winsys;
 997    screen->base.get_name = swr_get_name;
 998    screen->base.get_vendor = swr_get_vendor;
 999    screen->base.is_format_supported = swr_is_format_supported;
1000    screen->base.context_create = swr_create_context;
1001    screen->base.can_create_resource = swr_can_create_resource;
1002
1003    screen->base.destroy = swr_destroy_screen;
1004    screen->base.get_param = swr_get_param;
1005    screen->base.get_shader_param = swr_get_shader_param;
1006    screen->base.get_paramf = swr_get_paramf;
1007
1008    screen->base.resource_create = swr_resource_create;
1009    screen->base.resource_destroy = swr_resource_destroy;
1010
1011    screen->base.flush_frontbuffer = swr_flush_frontbuffer;
1012
1013    screen->hJitMgr = JitCreateContext(KNOB_SIMD_WIDTH, KNOB_ARCH_STR, "swr");
1014
1015    swr_fence_init(&screen->base);
1016
1017    util_format_s3tc_init();
1018
1019    return &screen->base;
1020 }
1021
1022 struct sw_winsys *
1023 swr_get_winsys(struct pipe_screen *pipe)
1024 {
1025    return ((struct swr_screen *)pipe)->winsys;
1026 }
1027
1028 struct sw_displaytarget *
1029 swr_get_displaytarget(struct pipe_resource *resource)
1030 {
1031    return ((struct swr_resource *)resource)->display_target;
1032 }